Page 1
HV5522/HV5530
HV5622/HV5630
32-Channel Serial To Parallel Converter
With Open Drain Outputs
Ordering Information
Package Options
Device Recommended 44 J-Lead Quad 44 J-Lead Quad 44 Lead Quad
Operating V
HV5522 220V HV5522DJ HV5522PJ HV5522PG HV5522X
HV5530 300V HV5530DJ HV5530PJ HV5530PG HV5530X
HV5622 220V HV5622DJ HV5622PJ HV5622PG HV5622X
HV5630 300V HV5630DJ HV5630PJ HV5630PG HV5630X
max Ceramic Chip Carrier Plastic Chip Carrier Plastic Gullwing
PP
Die
Features
❏ Processed with HVCMOS® technology
❏ Sink current minimum 100mA
❏ Shift register speed 8MHz
❏ Polarity and Blanking inputs
❏ CMOS compatible inputs
❏ Forward and reverse shifting options
❏ Diode to V
❏ 44-lead ceramic surface mount package
❏ Hi-Rel processing available
allows efficient power recovery
PP
Absolute Maximum Ratings
Supply voltage, V
Output voltage, V
Logic input levels
Ground current
Continuous total power dissipation3Ceramic 1500mW
Operating temperature range Ceramic -55°C to +125°C
Storage temperature range -65°C to +150°C
Lead temperature 1.6mm (1/16 inch) 260°C
from case for 10 seconds
Notes:
1. All voltages are referenced to V
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20°C for plastic and at 15mW/°C for ceramic.
1
DD
1
PP
1
2
HV5530/HV5630 -0.5V to +315V
HV5522/HV5622 -0.5V to +230V
Plastic 1200mW
Plastic -40°C to +85°C
.
SS
-0.5V to +15V
-0.5V to VDD + 0.5V
1.5A
General Description
The HV55 and HV56 are low-voltage serial to high-voltage
parallel converters with open drain outputs. These devices have
been designed for use as drivers for AC-electroluminescent
displays. They can also be used in any application requiring
multiple output high voltage current sinking capabilities such as
driving inkjet and electrostatic print heads, plasma panels, vacuum
fluorescent, or large matrix LCD displays.
These devices consist of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. Data is shifted through the shift register on the high to low
transition of the clock. The HV55 shifts in the counterclockwise
direction when viewed from the top of the package, and the HV56
shifts in the clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. Operation of the shift register is not
affected by the LE (latch enable), BL (blanking), or the POL
(polarity) inputs. Transfer of data from the shift register to the latch
occurs when the LE (latch enable) input is high. The data in the
latch is stored when LE is low.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1
Page 2
HV5522/HV5530/HV5622/HV5630
Electrical Characteristics (over recommended operating conditions unless noted)
DC Characteristics
Symbol Parameter Min Max Units Conditions
I
DD
I
DDQ
I
O(OFF)
I
IH
I
IL
V
OH
V
OL
V
OC
VDD supply current 15 mA f
Quiescent VDD supply current 100 µAVIN = 0V
Off state output current 10 µA All outputs high
High-level logic input current 1 µAVIH = V
Low-level logic input current -1 µAVIL = 0V
High-level output data out VDD - 1.0V V I
Low-level output voltage
HV
OUT
15.0 V I
Data out 1.0 V I
HV
clamp voltage -1.5 V IOL = -100mA
OUT
= 8MHz
CLK
F
DATA
= 4MHz
All SWS parallel
DD
= -100µA
Dout
= +100mA
HVout
= +100µA
Dout
AC Characteristics (V
= 12V, TC = 25°C)
DD
Symbol Parameter Min Max Units Conditions
f
CLK
t
W
t
SU
t
H
t
ON
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
Clock frequency 8 MHz
Clock width high or low 62 ns
Data set-up time before clock falls 25 ns
Data hold time after clock falls 10 ns
Turn on time, HV
from enable 500 ns RL = 2KΩ to VPP MAX
OUT
Delay time clock to data high to low 100 ns CL = 15pF
Delay time clock to data low to high 100 ns CL = 15pF
Delay time clock to LE low to high 50 ns
Width of LE pulse 50 ns
LE set-up time before clock falls 50 ns
Recommended Operating Conditions
Symbol Parameter Min Max Units
V
DD
HV
OUT
V
IH
V
IL
f
CLK
T
A
Note:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
3. Set all inputs to a known state.
Power-down sequence should be the reverse of the above.
DD
.
Logic supply voltage 10.8 13.2 V
High voltage output
HV5530 and HV5630 -0.3 +300 V
HV5522 and HV5622 -0.3 +220 V
High-level input voltage VDD - 2V V
DD
Low-level input voltage 0 2.0 V
Clock frequency 8 MHz
Operating free-air temperature
Plastic -40 +85 °C
Ceramic -55 +125 °C
V
2
Page 3
Input and Output Equivalent Circuits
HV5522/HV5530/HV5622/HV5630
V
DD
Input
V
SS
Logic Inputs
Switching Waveforms
Clock
Data Out
50% 50% 50%
t
WH
V
DD
HV
OUT
Data Out
V
SS
Logic Data Output
HV
IN
High Voltage Outputs
V
SS
V
IH
Data Valid50% 50%Data Input
V
t
SU
t
H
IL
V
IH
50%
V
t
WL
IL
V
OH
50%
V
t
DLH
t
50%
DHL
OL
V
OH
V
OL
Latch Enable
HV
OUT
w/ S/R HIGH
3
t
DLE
50%
V
50%
t
WLE
t
SLE
10%
t
ON
IH
V
IL
V
OH
V
OL
Page 4
Functional Block Diagram
Polarity
Blanking
Latch Enable
HV5522/HV5530/HV5622/HV5630
HV
1
OUT
Data Input
Clock
Latch
HV
OUT
2
Latch
32-Bit
Shift
Register
(Outputs 3 to 30
not shown)
31
HV
OUT
Latch
32
HV
OUT
Data Out
Latch
Function Table
Inputs Outputs
Function Shift Reg HV Outputs Data Out
All on X X X L L * *…*OnOn…On *
All off X X X L H * *…* Off Off…Off *
Invert mode X X L H L * *…***…**
Load S/R H or L
Load
Latches
Transparent
Latch mode
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion.
* = dependent on previous stage’s state before the last CLK ↓ or last LE high.
Data CLK LE BL POL
↓ LHHH or L *…***…**
XH or L
↑ HH **…***…**
12…32 1 2…32 *
XH or L ↑ HL**…***…**
L ↓ HHHL*…* Off *…**
H
↓ H HHH*…*On*…**
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Page 5
HV5522/HV5530/HV5622/HV5630
Pin Configurations
HV55
44 Pin J-Lead Package
Pin Function Pin Function
1HV
2HV
3HV
4HV
5HV
6HV
7HV
8HV
9HV
10 HV
11 HV
12 HV
13 HV
14 HV
15 HV
16 HV
17 HV
18 Data Out 40 HV
19 N/C 41 HV
20 N/C 42 HV
21 N/C 43 HV
22 Polarity 44 HV
16 23 Clock
OUT
17 24 V
OUT
18 25 V
OUT
19 26 Latch Enable
OUT
20 27 Data In
OUT
21 28 Blanking
OUT
22 29 N/C
OUT
23 30 HV
OUT
24 31 HV
OUT
25 32 HV
OUT
26 33 HV
OUT
27 34 HV
OUT
28 35 HV
OUT
29 36 HV
OUT
30 37 HV
OUT
31 38 HV
OUT
32 39 HV
OUT
SS
DD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Package Outline
39 38 37 36 35 34
40
41
42
43
44
1
2
3
4
5
6
7 8 9 10 11 12
top view
44-pin J-Lead Package
33 32 31 30 29
28
27
26
25
24
23
22
21
20
19
18
13 14 15 16 17
HV56
44 Pin J-Lead Package
Pin Function Pin Function
1HV
2HV
3HV
4HV
5HV
6HV
7HV
8HV
9HV
10 HV
11 HV
12 HV
13 HV
14 HV
15 HV
16 HV
17 HV
17 23 Clock
OUT
16 24 V
OUT
15 25 V
OUT
14 26 Latch Enable
OUT
13 27 Data In
OUT
12 28 Blanking
OUT
11 29 N/C
OUT
10 30 HV
OUT
931HV
OUT
832HV
OUT
733HV
OUT
634HV
OUT
535HV
OUT
436HV
OUT
337HV
OUT
238HV
OUT
139HV
OUT
18 Data Out 40 HV
19 N/C 41 HV
20 N/C 42 HV
21 N/C 43 HV
22 Polarity 44 HV
SS
DD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
5
Page 6
HV5522/HV5530/HV5622/HV5630
Pin Configurations
HV55
44-Pin Quad Plastic Gullwing Package
Pin Function
1HV
2HV
3HV
4HV
5HV
6HV
7HV
8HV
9HV
10 HV
11 HV
12 HV
13 HV
14 HV
15 HV
16 HV
17 HV
18 HV
19 HV
20 HV
21 HV
22 HV
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Function
23 Data Out
24 N/C
25 N/C
26 N/C
27 Polarity
28 Clock
29 V
SS
30 V
DD
31 Latch Enable
32 Data In
33 Blanking
34 N/C
35 HV
36 HV
37 HV
38 HV
39 HV
40 HV
41 HV
42 HV
43 HV
44 HV
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
2
3
4
5
6
7
8
9
10
Package Outline
40
42
44
1
2
3
4
5
6
7
8
9
10
11
12
44-pin Quad Plastic Gullwing Package
41
43
13 14 151617
top view
39 38 37 36 35 34
20
19
18
21
33
32
31
30
29
28
27
26
25
24
23
22
HV56
44-Pin Quad Plastic Gullwing Package
Pin Function
1HV
2HV
3HV
4HV
5HV
6HV
7HV
8HV
9HV
10 HV
11 HV
12 HV
13 HV
14 HV
15 HV
16 HV
17 HV
18 HV
19 HV
20 HV
21 HV
22 HV
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Pin Function
23 Data Out
24 N/C
25 N/C
26 N/C
27 Polarity
28 Clock
29 V
SS
30 V
DD
31 Latch Enable
32 Data In
33 Blanking
34 N/C
35 HV
36 HV
37 HV
38 HV
39 HV
40 HV
41 HV
42 HV
43 HV
44 HV
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
32
31
30
29
28
27
26
25
24
23
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
12/13/010
1235 Bordeaux Drive, Sunnyvale, CA 94089
6
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
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