Datasheet HT1625 Datasheet (Holtek Semiconductor Inc)

RAM Mapping 64´8 LCD Controller for I/O mC

Features

Operating voltage: 2.7V~5.2V

·

Built-in RC oscillator

·

External 32.768kHz crystal or 32kHz

·

frequency source input 1/4 bias, 1/8 duty, frame frequency is 64Hz

·

Max. 64´8 patterns, 8 commons, 64 segments

·

Built-in internal resistor type bias generator

·

3-wire serial interface

·

8 kinds of time base/WDT selection

·

Time base or WDT overflow output

·

Built-in LCD display RAM

·

General Description

HT1625 is a peripheral device specially de signed for I/O type mC used to expand the dis play capability. The max. display segment of the device are 512 patterns (64´8). It also sup ports serial interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1625 is a memory mapping and multi-function LCD controller. The software

HT1625

R/W address auto increment

·

Two selectable buzzer frequencies

·

(2kHz/4kHz) Power down command reduces power

·

consumption Software configuration feature

·

Data mode and Command mode instructions

·

Three data accessing modes

·

VLCD pin to adjust LCD operating voltage

·

Cascade application

·

configuration feature of the HT1625 make it

suitable for multiple LCD applications includ

ing LCD modules and display subsystems. Only three lines are required for the interface be

tween the host controller and the HT1625. The HT162X series have many kinds of products that match various applications.

-

Selection Table

HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270

COM 448 8 8

SEG 32 32 32 32 48

Built-in Osc.

Crystal Osc.

ÖÖ Ö ÖÖÖ Ö

ÖÖ ÖÖÖ Ö

1 April 21, 2000

8

64

16 16 16

48 64 64

Block Diagram

HT1625

Pin Assignment

OSCO

OSCI

CS

RD

WR

DATA

VDD

VSS

BZ

DATA

VSS OSCI OSCO

VDD

VLCD

IR Q

COM 0 COM 1 COM 2 COM 3

COM 4

COM 5

COM 6

CS

RD

WR

BZ BZ

T1 T2 T3

NC

NC NC NC NC

NC

D ispla y R A M

C ontrol

and Tim ing Circuit

Tone Frequency

G enerator

SEG 56

SEG 55

SEG 61

SEG 63

SEG 62

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

COM 7NCNC

SEG 57

SEG 60

SEG 59

SEG 58

H T1625

100 Q FP

SEG 2

SEG 0

SEG 1

SEG 3

SEG 4

LC D D river/ Bias Circuit

W atchdog Tim er

and

Tim e Base G enerator

SEG 54

SEG 53

SEG 52

SEG 51

SEG 50

SEG 49

SEG 6

SEG 5

SEG 7

SEG 8

SEG 9

SEG 10

SEG 11

SEG 48

SEG 12

COM 0

COM 7

SEG 0

SEG 63

VLCD

IR Q

SEG 47

SEG 46

SEG 45

SEG 44

81828384858687888990919293949596979899100

SEG43

80 79

NC SEG42

78

SEG41

77

SEG40

76

SEG39

75

SEG38

74 73

SEG37 SEG36

72

SEG35

71

SEG34

70

SEG33

69

SEG32

68

SEG31

67

SEG30

66

SEG29

65

SEG28

64 63

SEG27

62

SEG26

61

SEG25

60

SEG24

59

SEG23

58

SEG22

57

SEG21

56

NC

55

NC

54

SEG20

53

SEG19

52

SEG18

51

SEG17

SEG 13

SEG 14

SEG 15

SEG 16

2 April 21, 2000

Pad Assignment

CS

HT1625

SEG 43

SEG 44

SEG 45

SEG 46

SEG 47

SEG 48

SEG 49

SEG 50

SEG 51

SEG 52

SEG 53

SEG 54

SEG 55

SEG 56

SEG 57

SEG 58

SEG 59

SEG 60

SEG 61

SEG 62

SEG 63

RD

WR

DATA

VSS

OSCI

OSCO

VDD

VLCD

IR Q

BZ

T1

T2

T3

COM 0

COM 1

COM 2

COM 3

COM 4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

COM 5

8542864387

21652266236724682569267027712872297330743175327633773478357936

COM 6

COM 7

SEG 0

SEG 1

SEG 2

80

81

SEG 3

SEG 4

SEG 5

SEG 6

SEG 7

SEG 8

SEG 42

64

SEG 41

63

SEG 40

62

SEG 39

61

SEG 38

60

SEG 37

SEG 36

59

SEG 35

58

SEG 34

57

56

SEG 33

SEG 32

(0 , 0 )

37

38823983408441

SEG 9

SEG 10

SEG 11

SEG 12

SEG 13

SEG 14

SEG 15

SEG 16

SEG 17

SEG 18

55

54

SEG 31

53

SEG 30

52

SEG 29

51

SEG 28

50

SEG 27

49

SEG 26

48

SEG 25

47

SEG 24

46

SEG 23

SEG 22

45

SEG 21

44

SEG 20

SEG 19

Chip size: 192 ´ 211 (mil)

2

* The IC substrate should be connected to VDD in the PCB layout artwork.

3 April 21, 2000

Pad Coordinates Unit: mil

Pad No. X Y Pad No. X Y

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 3.02 34 9.65 35 16.28 36 22.91 37 29.54 38 41.52 39 48.15 40 60.14 41 66.77 42 78.75 43 90.57 44 90.57

-90.18

-89.42

-90.18

-90.18 -3.61

-90.18 -10.24

-90.18 -16.87

-90.18 -23.50

-90.18 -30.13

-90.18 -36.76

-90.18 -43.39

-90.18 -92.22

-83.17 -99.53

-76.54 -99.53

-69.91 -99.53

-63.28 -99.53

-56.65 -99.53

-50.02 -99.53

-43.39 -99.53

-36.76 -99.53

-30.13 -99.53

-23.50 -99.53

-16.87 -99.53

-10.24 -99.53

-3.61 -99.53

98.56 45 90.57

91.93 46 90.57

85.30 47 89.80

75.95 48 89.80

57.76 49 89.80

45.77 50 89.80

39.14 51 89.80

32.51 52 89.80

25.03 53 89.80

15.94 54 89.80

5.82 55 89.80 6.33 56 89.80 12.96 57 89.80 24.95 58 89.80 31.58 59 89.80 43.56 60 89.80 50.19 61 89.80 62.18 62 89.80 68.81 63 89.80 80.79 64 89.80 87.42 65 89.38 98.22 66 77.39 98.22 67 70.76 98.22 68 58.78 98.22 69 52.15 98.22 70 40.16 98.22 71 32.09 99.32 72 25.46 99.32 73 18.83 99.32 74 12.20 99.32 75 5.57 99.32

-99.53

-98.60

-97.79

-91.16

76 77 78 79 80 81 82 83 84 85 86 87

-1.06

-7.69

-14.32

-20.95

-27.58

-34.21

-40.84

-47.47

-54.10

-60.73

-67.36

-73.99

-84.53

-77.90

-68.13

-61.50

-49.51

-42.88

-30.90

-24.27

-12.28

-5.65

99.32

HT1625

4 April 21, 2000

HT1625

Pad Description

Pad No. Pad Name I/O Description

READ clock input with pull-high resistor. Data in the RAM of the HT1625 are clocked out on the rising edge of the RD

1RD

2WR

3 DATA I/O Serial data input/output with pull-high resistor

4 VSS

5 OSCI I The OSCI and OSCO pads are connected to a 32.768kHz crystal

6 OSCO O

7 VDD

8 VLCD I LCD operating voltage input pad.

9 IRQ

10, 11 BZ, BZ

12~14 T1~T3 I Not connected

15~22 COM0~COM7 O LCD common outputs

23~86 SEG0~SEG63 O LCD segment outputs

87 CS

I

clocked out data will appear on the data line. The host controller can use the next falling edge to latch the clocked out data.

WRITE clock input with pull-high resistor. Data on the DATA

I

line are latched into the HT1625 on the rising edge of the WR sig nal.

Negative power supply, Ground

¾

in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is se lected instead, the OSCI and OSCO pads can be left open.

Positive power supply

¾

Time base or Watchdog Timer overflow flag, NMOS open drain

O

output

O 2kHz or 4kHz tone frequency output pair

Chip selection input with pull-high resistor. When the CS high, the data and command read from or write to the HT1625 are disabled. The serial interface circuit is also reset. But if the

I

CS

is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1625 are all enabled.

signal. The

-

is logic

Absolute Maximum Ratings

Supply Voltage ..............................-0.3V to 5.5V

Input Voltage ................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo sure to extreme conditions may affect device reliability.

-0.3V to VDD+0.3V

SS

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-25°Cto75°C

5 April 21, 2000

-

HT1625

D.C. Characteristics

Symbol Parameter

V

DD

I

DD1

I

DD2

I

DD11

I

DD22

I

STB

V

IL

V

IH

I

OL1

I

OH1

I

OL1

I

OH1

I

OL2

I

OH2

I

OL3

I

OH3

R

PH

Operating Voltage

Operating Current

Standby Current

Input Low Voltage

Input High Voltage

BZ, BZ, IRQ

BZ, BZ

DATA

LCD Common Sink Current

LCD Common Source Current

LCD Segment Sink Current

LCD Segment Source Current

Pull-high Resistor

Test Conditions

V

DD

Conditions

¾¾

3V

No load/LCD ON On-chip RC oscillator

5V

3V

No load/LCD ON Crystal oscillator

5V

3V

No load/LCD OFF On-chip RC oscillator

5V

3V

No load/LCD OFF Crystal oscillator

5V

3V

No load Power down mode

5V

3V

DATA, WR,CS,RD

5V 0

3V

DATA, WR,CS,RD

5V 4.0

V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V 50 100 150

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

DATA, WR,CS,RD

Min. Typ. Max. Unit

2.7

¾

155 310

¾

260 420

¾

150 310

¾

250 420

¾

830

¾

20 60

¾ ¾¾ ¾¾

112

¾

224

¾

0

¾ ¾

2.4

¾ ¾

0.9 1.8

1.7 3

-0.9 -1.8 ¾

-1.7 -3 ¾

0.9 1.8

1.7 3

-0.9 -1.8 ¾

-1.7 -3 ¾

80 160

180 360

-40 -80 ¾mA

-90 -180 ¾mA

50 100

120 240

-30 -60 ¾mA

-70 -140 ¾mA

100 200 300

Ta=25°C

5.2 V

mA mA mA mA mA mA

20

mA

35

mA mA mA

0.6 V

1.0 V

3V

5V

mA

¾

mA

¾

mA

¾

mA

¾

mA

¾mA ¾mA

kW kW

6 April 21, 2000

HT1625

A.C. Characteristics

Symbol Parameter

f

SYS1

f

SYS2

f

LCD1

f

LCD2

t

COM

f

CLK1

f

CLK2

t

CS

t

CLK

t

r,tf

t

su

t

h

t

su1

t

h1

System Clock

LCD Frame Frequency

LCD Common Period

Serial Data Clock (WR Pin)

Serial Data Clock (RD Pin)

Serial Interface Reset Pulse Width (Figure 3)

WR,RDInput Pulse Width

Rise/Fall Time Serial Data Clock Width (Figure 1)

Setup Time for DATA to WR, RD

Clock Width (Figure 2)

Hold Time for DATA to WR, RD

Clock Width (Figure 2)

Setup Time for CS to WR,RD Clock Width (Figure 3)

Hold Time for CS to WR,RD Clock Width (Figure 3)

(Figure 1)

Ta=25°C

Test Conditions

Min. Typ. Max. Unit

V

DD

3V

Conditions

22 32 40 kHz

On-chip RC oscillator

5V 24 32 40 kHz

3V

¾

32

¾

kHz

External clock source

5V

3V

¾

32

¾

kHz

44 64 80 Hz

On-chip RC oscillator

5V 48 64 80 Hz

3V

¾

64

¾

Hz

External clock source

5V

n: Number of COM

¾

3V

64

¾

n/f

¾

LCD

¾¾

Hz

¾

sec

¾

150 kHz

Duty cycle 50%

5V

3V

¾¾

300 kHz

75 kHz

Duty cycle 50%

5V

CS

¾

Write mode 3.34

¾¾

¾

150 kHz

250

¾

¾¾

3V

Read mode 6.67

Write mode 1.67

¾¾

5V

Read mode 3.34

¾¾

3V

¾¾

120

¾

5V

3V

¾¾

120

¾

5V

3V

¾¾

120

¾

5V

3V

¾¾

100

¾

5V

3V

¾¾

100

¾

5V

ns

ms

ns

7 April 21, 2000

HT1625

D

W R , R D Clock

90%

50%

10%

t

f

t

CLK

t

r

t

CLK

Figure 1

t

CS

WR, RD Clock

50%

FIR ST

Clock

t

LAS T Clock

h1

t

su1

Figure 2

Functional Description

Display memory - RAM structure

The static display RAM is organized into 128´4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns.

COM 4COM 5COM 6COM 7

VALID DATA

50%

t

su

50%

t

h

V

DD

GND

DB

WR, RD Clock

Figure 1

V

DD

GND

V

DD

GND

Time base and Watchdog Timer - WDT

The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR , WDT DIS/EN/CLR and IRQ

EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ

pin will remain at logic low level until the CLR WDT or the IRQ DIS command is issued.

COM 0COM 1COM 2COM 3

V

GN

V

GN

DD

SEG 0

SEG 1

SEG 2

SEG 3

SEG 63

D3 D2 D1 D0

1

3

5

7

127

Addr

Data

D a ta 4 B its

(D 3, D 2, D 1, D 0)

D3 D2 D1 D0

RAM mapping

8 April 21, 2000

0

2

4

6

126

Addr

Data

Address 7 B its

(A 6 , A 5 , ...., A 0 )

HT1625

Tim e Base

C lock S ource

/256

CLR Tim er

WDT

/4

CLR W DT

Timer and WDT configurations

If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is re moved.

Buzzer tone output

A simple tone generator is implemented in the HT1625. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone.

Command format

The HT1625 can be configured by the software setting. There are two mode commands to configure the HT1625 resource and to transfer the LCD display data.

T IM E R E N /D IS

WDT EN/DIS

V

DD

D

CK

Q

IR Q E N /D IS

R

IR Q

The following are the data mode ID and the command mode ID:

-

Operation Mode ID

READ Data 1 1 0

WRITE Data 1 0 1

READ-MODIFY-WRITE Data 1 0 1

COMMAND Command 1 0 0

If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive com mand or the non-successive address data mode,

pin should be set to ²1² and the previous

the CS operation mode will be reset also. The CS returns to ²0², a new operation mode ID should be issued first.

-

Name Command Code Function

TONE OFF 0000-1000-X Turn-off tone output

TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4kHz

TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2kHz

9 April 21, 2000

Timing Diagrams

READ mode (command code:110)

CS

WR

RD

HT1625

DATA

1

A6 A6

1

M em ory A ddress 1 (M A 1) Data (M A2)

A1 A0 D0 D1

0A5A4A3 A2

READ mode (successive address reading)

CS

WR

RD

0 A5 A4A3 A2A1A0D0D1D2D3

DATA

1

A6

1

M em ory A ddress (M A ) D ata (M A )

D2 D3

D ata (M A1) M em ory A ddress 2 (M A 2)

0A5A4A3 A2

1

D1 D2 D3 D0 D1 D2 D3

D0

D ata (M A+1) Data (M A +2) D ata (M A +3)

A1 A0 D0 D1

D0 D1

D2 D3

D0

10 April 21, 2000

WRITE mode (command code:101)

CS

WR

HT1625

DATA

1A5A4A3 A2

1

0

M em ory A ddress 1 (M A 1) D ata (M A1)

A1 A0 D 0 D1

WRITE mode (successive address writing)

CS

WR

1A5A4A3 A2

DATA

1

A6

0

M em ory A ddress (M A ) Data (M A)

A1 A0 D0 D1

D2 D3

1A5A4A3 A2

1

A6A6

0

M em ory A ddress 2 (M A 2) D ata (M A2)

D2 D3

D0 D1

D ata (M A+1) Data (M A+ 2) D ata (M A +3)

D0 D1

A1 A0 D0 D1

D2 D3

D0 D1

D2 D3

D0

11 April 21, 2000

READ-MODIFY-WRITE mode (command code:101)

CS

WR

RD

HT1625

DATA

1A5A4A3 A2

1

0

M em ory Address 1 (M A1) D ata (M A1)

A1 A0 D0 D1

D2 D3

D0 D1

Data (MA1)

D2 D3

1

READ-MODIFY-WRITE mode (successive address accessing)

CS

WR

RD

DATA

1A5A4A3 A2

1

0

A6

M em ory A ddress (M A) D ata (M A )

A1 A0 D 0 D1

D2 D3

D0 D1

D ata (M A) D ata (M A+1) Data (M A +1)

A5A4A3 A2

A6A6

1

0

M em ory Address 2 (M A2) D ata (M A2)

D2 D3

D0 D1

A1 A0 D0 D1

D2 D3

D0

D1

Data (M A+2)

D2 D3

D0

12 April 21, 2000

Command mode (command code:100)

CS

WR

HT1625

DATA

1

0

0C8C7C6 C5

C4 C3 C2 C1

C om m and 1

Mode (data and command mode)

CS

WR

DATA

RD

C om m and

or

D ata M ode

Address and D ata

C0

C om m and

D ata M ode

C8C7C6 C5

or

C4 C3 C2 C1

C om m and iC om m and... C om m and

Address and D ata

C0

C om m and

D ata M ode

or

D ata M ode

Address and D ata

13 April 21, 2000

Application Circuits

m

C

C lock O ut

External C lock 1 (32kHz)

External C lock 2 (32kHz)

On-chip OSC

C rystal

32768H z

HT1625

CS

*

RD

WR

DATA

*

R

IR Q

OSCI

OSCO

C O M 0 ~ C O M 7 S E G 0 ~ S E G 6 3

H T1625

1/4 Bias, 1/8 D uty

LC D Panel

VDD

VLCD

BZ

*

VR

Piezo

*Note:

The connection of IRQ

The voltage applied to V

Adjust VR to fit LCD display, at V

and RD pin can be selected depending on the requirement of the mC.

pin must be lower than VDD.

LCD

DD

=5V, V

=4V, VR=15kW±20%.

LCD

Adjust R (external Pull-high resistance) to fit user¢s time base clock.

14 April 21, 2000

Instruction Set Summary

Name ID Command Code D/C Function Def.

READ

WRITE

READMODIFYWRITE

SYS DIS

SYS EN

LCD OFF

LCD ON

TIMER DIS

WDT DIS

TIMER EN

WDT EN

TONE OFF

CLR TIMER

CLR WDT

RC 32K

EXT (XTAL) 32K

TONE 4K

TONE 2K

DIS

IRQ

EN

IRQ

F1

F2

F4

A6A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM

110

A6A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM

101

A6A5A4A3A2A1A0D0D1D2D3 D Read and Write data to the RAM

101

0000-0000-X C

100

0000-0001-X C Turn on system oscillator

100

0000-0010-X C Turn off LCD display Yes

100

0000-0011-X C Turn on LCD display

100

0000-0100-X C Disable time base output Yes

100

0000-0101-X C Disable WDT time-out flag output Yes

100

0000-0110-X C Enable time base output

100

0000-0111-X C Enable WDT time-out flag output

100

0000-1000-X C Turn off tone outputs Yes

100

0000-1101-X C

100

0000-1111-X C

100

0001-10XX-X C

100

0001-11XX-X C

100

010X-XXXX-X C Tone frequency output: 4kHz

100

0110-XXXX-X C Tone frequency output: 2kHz

100

100X-0XXX-X C Disable IRQ output Yes

100

100X-1XXX-X C Enable IRQ output

100

101X-0000-X C

100

101X-0001-X C

100

101X-0010-X C

100

Turn off both system oscillator and LCD bias generator

Clear the contents of thetime base generator

Clear the contents of the WDT stage

System clock source, on-chip RC oscillator

System clock source, external 32kHz clock source or crystal oscillator 32.768kHz

Time base clock output: 1Hz The WDT time-out flag after: 4s

Time base clock output: 2Hz The WDT time-out flag after: 2s

Time base clock output: 4Hz The WDT time-out flag after: 1s

HT1625

Yes

15 April 21, 2000

Name ID Command Code D/C Function Def.

F8

F16

F32

F64

F128

TEST

NORMAL

Note:

X : Don¢t care

A6~A0 : RAM address

D3~D0 : RAM data

D/C : Data/Command mode

Def. : Power on reset default

All the bold forms, namely 110, 101, and 100, are mode commands. Of these, 100indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1625 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1625.

101X-0011-X C

100

101X-0100-X C

100

101X-0101-X C

100

101X-0110-X C

100

101X-0111-X C

100

1110-0000-X C

100

1110-0011-X C Normal mode Yes

100

Time base clock output: 8Hz The WDT time-out flag after: 1/2 s

Time base clock output: 16Hz The WDT time-out flag after: 1/4 s

Time base clock output: 32Hz The WDT time-out flag after: 1/8 s

Time base clock output: 64Hz The WDT time-out flag after: 1/16 s

Time base clock output: 128Hz The WDT time-out flag after: 1/32 s

Test mode, user don¢t use.

HT1625

Yes

16 April 21, 2000

HT1625

Holtek Semiconductor Inc. (Headquarters)

No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189

Holtek Semiconductor Inc. (Taipei Office)

5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline)

Holtek Semiconductor (Hong Kong) Ltd.

RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

17 April 21, 2000

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