Datasheet HT16220 Datasheet (Holtek Semiconductor Inc)

RAM Mapping 32´8 LCD Controller for I/O mC

Features

Operating voltage: 2.7V~5.2V

·

External Crystal 32.768kHz oscillator

·

1/4 bias, 1/8 duty, frame frequency is 64Hz

·

Max. 32´8 patterns, 8 commons, 32 segments

·

Built-in internal resistor type bias generator

·

3-wire serial interface

·

8 kinds of time base/WDT selection

·

Time base or WDT overflow output

·

Built-in LCD display RAM

·

R/W address auto increment

·

General Description

HT16220 is a peripheral device specially de
signed for I/O type mC used to expand the dis
play capability. The max. display segment of
the device are 256 patterns (32´8). It also sup
ports serial interface, buzzer sound, watchdog
timer or time base timer functions. The
HT16220 is a memory mapping and
multi-function LCD controller. The software

HT16220

Two selectable buzzer frequencies

·

(2kHz/4kHz)
Power down command reduces power

·

consumption
Software configuration feature

·

Data mode and Command mode instructions

·

Three data accessing modes

·

VLCD pin to adjust LCD operating voltage

·

Cascade application

·

configuration feature of the HT16220 make it

­suitable for multiple LCD applications includ

­ing LCD modules and display subsystems. Only
three lines are required for the interface be

­tween the host controller and the HT16220.
The HT162X series have many kinds of prod
ucts that match various applications.

-

-

-

Selection Table

HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270

COM

SEG

Built-in Osc.

Crystal Osc.

448 8 8 8 16 16 16

32 32 32 32 48 64 48 64 64

ÖÖ ÖÖÖÖ

ÖÖ

Ö

1 April 21, 2000

ÖÖÖ Ö

Block Diagram

HT16220

OSCO

OSCI

CS

RD

WR

DATA

VDD

VSS

BZ

Tone Frequency

BZ

Pin Assignment

CS
NC

RD

WR

DATA

VSS

VDD

VLC D

IR Q

BZ

BZ

NC

OSCO

OSCI

T1

T2

T3

NC

COM 0

C ontrol

and
Tim ing
Circuit

G enerator

SEG30

SEG31

63

64

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

202122

19

W atchdog Tim er

Tim e B ase G enerator

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

57

58

59

60

61

62

H T16220

64 Q FP

23

242526272829303132

D ispla y R A M

LCD Driver/
Bias Circuit

and

SEG23

SEG20

SEG21

SEG22

56

53

54

55

NC

52

COM 0

COM 7

SEG 0

SEG 31

VLCD

IR Q

NC

51
50

NC

NC

49

SEG19

48

SEG18

47

SEG17

46

SEG16

45

SEG15

44

SEG14

43

SEG13

42

SEG12

41

SEG11

40

SEG10

39

SEG9

38

SEG8

37

SEG7

36

NC

35

NC

34

SEG6

33

COM 4

COM 1

COM 2

COM 3

COM 5

COM 6

COM 7

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

2 April 21, 2000

Pad Assignment

CS

RD

WR

DATA

VSS

VDD

VLCD

IR Q

BZ

BZ

OSCO

OSCI

T1

T2

T3

4

5

6

7

8

9

10

11

12

13

14

15

HT16220

SEG 20

SEG 22

SEG 23

SEG 25

SEG 26

SEG 27

SEG 28

SEG 29

SEG 30

SEG 31

51

52

53

54

55

1

2

3

16

17

COM 1

COM 0

50

49

18

COM 2

SEG24

48

19

COM 3

47

46

20

COM 4

SEG 21

(0 ,0 )

21

COM 5

45

44

22

COM 6

23

COM 7

24

SEG 0

25

SEG 1

26

SEG 2

27

SEG 3

28

SEG 4

29

SEG 5

43

42

41

40

39

38

37

36

35

34

33

32

31

30

SEG 6

SEG 19

SEG 18

SEG 17
SEG 16

SEG 15

SEG 14

SEG 13

SEG 12

SEG 11

SEG 10

SEG 9

SEG 8

SEG 7

Chip size: 151 ´ 157 (mil)

2

* The IC substrate should be connected to VDD in the PCB layout artwork.

3 April 21, 2000

Pad Coordinates Unit: mil

Pad No. X Y Pad No. X Y

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22 14.66
23 21.29
24 27.92
25 34.55
26 41.18
27 47.81
28 54.44

-68.76 72.04

-68.76 59.71

-68.76

-69.53

-69.70

-69.70

-69.70

-69.70

-69.70 -10.28

-69.70 -23.55

-69.70 -38.93

-69.70 -45.56

-69.70 -56.53

-69.70 -63.83

-69.70 -70.46

-39.57 -71.57

-32.94 -71.57

-20.53 -71.57

-13.90 -71.57

-1.49 -71.57

5.14 -71.57

53.08 31 68.98

39.40 32 68.98

24.82 33 68.98 2.85

18.19 34 68.98 9.48

11.56 35 68.98 16.11

1.36 36 68.98 22.74

-72.33

-72.33

-72.33

-72.33

-72.33

-72.33

-72.33

29 61.07
30 67.70

37 68.98 29.37
38 68.98 36.00
39 68.98 42.63
40 68.98 49.26
41 68.98 55.89
42 68.98 62.52
43 68.98 69.15
44 13.85 72.04
45 7.22 72.04
46 0.60 72.04
47
48
49
50
51
52
53
54
55

-6.03

-12.66

-19.30

-25.92

-32.56

-39.19

-45.81

-52.44

-59.08

-72.33

-72.33

-10.41

-3.78

72.04

72.04

72.04

72.04

72.04

72.04

72.04

72.04

72.04

HT16220

4 April 21, 2000

Pad Description

Pad No. Pad Name I/O Description

Chip selection input with pull-high resistor. When the CS
logic high, the data and command read from or written to the

1CS

2RD

3WR

4 DATA I/O Serial data input/output with pull-high resistor

5 VSS

6 VDD

7 VLCD I LCD operating voltage input pad.

8 IRQ

9, 10 BZ, BZ

11 OSCO O Crystal oscillator output pin

12 OSCI I Crystal oscillator input pin

13~15 T1~T3 I Not connected

16~23 COM0~COM7 O LCD common outputs

24~55 SEG0~SEG31 O LCD segment outputs

HT16220 are disabled. The serial interface circuit is also reset

I

But if the CS
data and command transmission between the host controller
and the HT16220 are all enabled.

READ clock input with pull-high resistor. Data in the RAM of
the HT16220 are clocked out on the rising edge of the RD
nal. The clocked out data will appear on the data line. The host

I

controller can use the next falling edge to latch the clocked out
data.

WRITE clock input with pull-high resistor. Data on the DATA

I

line are latched into the HT16220 on the rising edge of the WR
signal.

Negative power supply, ground

¾

Positive power supply

¾

Time base or watchdog timer overflow flag, NMOS open drain

O

output.

O 2kHz or 4kHz tone frequency output pair

is at logic low level and is input to the CS pad, the

HT16220

is

sig

-

Absolute Maximum Ratings

Supply Voltage ..............................-0.3V to 5.5V

Input Voltage ................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo
sure to extreme conditions may affect device reliability.

-0.3V to VDD+0.3V

SS

Storage Temperature ................-50°Cto125°C

Operating Temperature .............-25°Cto75°C

5 April 21, 2000

-

-

HT16220

D.C. Characteristics

Symbol Parameter

V

I

I

I

V

V

I

I

I

I

I

I

I

I

R

DD

DD1

DD2

STB

IL

IH

OL1

OH1

OL1

OH1

OL2

OH2

OL3

OH3

PH

Operating Voltage

Operating Current

Operating Current

Standby Current

Input Low Voltage

Input High Voltage

BZ, BZ, IRQ

BZ, BZ

DATA

DATA

LCD Common Sink Current

LCD Common Source Current

LCD Segment Sink Current

LCD Segment Source Current

Pull-high Resistor

Test Conditions

V

DD

Conditions

¾¾

3V

No load LCD ON
Crystal oscillator

5V

3V

No load/LCD OFF
Crystal oscillator

5V

3V

No load
Power down mode

5V

3V

DATA, WR,CS,RD

5V 0

3V

DATA, WR,CS,RD

5V 4.0

V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V 50 100 150

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

DATA, WR,CS,RD

Min. Typ. Max. Unit

2.7

¾

5.2 V

¾¾
¾¾
¾¾
¾¾

0

18

216

0.6 V

¾

1.0 V

¾
¾

¾
¾

2.4

¾

0.9 1.8

1.7 3

-0.9 -1.8 ¾

-1.7 -3 ¾

200 450

250 500

-200 -450 ¾mA

-250 -500 ¾mA

15 40

100 200

-15 -30 ¾mA

-45 -90 ¾mA

15 30

70 150

-6 -13 ¾mA

-20 -40 ¾mA

100 200 300

Ta=25°C

50

mA

65

mA

20

mA

30

mA
mA
mA

3V

5V

mA

¾

mA

¾

mA

mA

¾mA
¾mA

¾mA
¾mA

¾mA
¾mA

kW
kW

6 April 21, 2000

HT16220

A.C. Characteristics

Symbol Parameter

f

SYS

f

LCD

t

COM

f

CLK1

f

CLK2

t

CS

t

CLK

t

r,tf

t

SU

t

h

t

SU1

t

h1

System Clock

LCD Frame Frequency

LCD Common Period

Serial Data Clock (WR Pin)

Serial Data Clock (RD Pin)

Serial Interface Reset Pulse
Width (Figure 3)

WR,RDInput Pulse Width

Rise/Fall Time Serial Data
Clock (Figure 1)

Setup Time for DATA to WR,
RD

Serial Data Clock

Hold Time for DATA to WR,
RD

Serial Data Clock

Setup Time for CS to WR,RD
Clock Width (Figure 3)

Hold Time for CS to WR,RD
Clock Width (Figure 3)

(Figure 1)

(Figure 2)

(Figure 2)

Test Conditions

V

DD

Conditions

3V

Crystal oscillator

5V

3V

Crystal oscillator

5V

n: Number of COM

¾

3V

Duty cycle 50%

5V

3V

Duty cycle 50%

5V

CS

¾

Write mode 3.34

3V

Read mode 6.67

Write mode 1.67

5V

Read mode 3.34

3V

¾¾

5V

3V

¾¾

5V

3V

¾¾

5V

3V

¾¾

5V

3V

¾¾

5V

Ta=25°C

Min. Typ. Max. Unit

n/f

32

32

64

64

LCD

¾

¾

¾

¾

¾

¾¾

¾¾

¾¾

¾¾

250

¾

kHz

¾

kHz

¾

Hz

¾

Hz

¾

sec

¾

150 kHz

300 kHz

75 kHz

150 kHz

ns

¾

¾¾

ms

¾¾

¾¾

ms

¾¾

120

120

120

100

100

¾

¾

¾

¾

¾

ns

ns

ns

ns

ns

7 April 21, 2000

HT16220

(D3,

)

WR, RD
Clock

90%

50%

10%

t

f

t

CLK

t

r

t

CLK

-

V

GND

Figure 1

t

CS

WR, RD
Clock

50%

50%

FIR ST

Clock

CS

t

SU1

LAST
Clock

t

h1

-

GND

-

GND

V

V

Figure 3

Functional Description

Display memory - RAM structure

The static display RAM is organized into 64´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can
beaccessedbytheREAD,WRITEand
READ-MODIFY-WRITE commands. The fol­lowing is a mapping from the RAM to the LCD
patterns.

COM 4COM 5COM 6COM 7

VALID D ATA

DD

DB

W R , R D
Clock

50%

50%

t

h

t

su

Figure 2

DD

DD

Time base and watchdog timer - WDT

The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR,
WDT DIS/EN/CLR and IRQ

EN/DIS are inde­pendent from each other. Once the WDT
time-out occurs, the IRQ

pin will stay at a logic
low level until the CLR WDT or the IRQ
commandisissued.

COM 0COM 1COM 2COM 3

V

GND

V

GND

-

DD

DD

DIS

SEG 0

SEG 1

SEG 2

SEG 3

SEG 31

D3 D2 D1 D0

1

3

5

7

63

Addr

Data

Data 4 Bits

D 2, D 1, D 0

D3 D2 D1 D0

0

2

4

6

62

Addr

Data

RAM mapping

8 April 21, 2000

Address 6 B its

(A 5 , A 4 , ...., A 0 )

HT16220

Tim e Base

V

DD

/4

CLR W DT

T IM E R E N /D IS

WDT EN/DIS

Q

D

CK

R

IR Q E N /D IS

C lock S o urce

/256

CLR Tim er

WDT

Timer and WDT configurations

If an external clock is selected as the source of
system frequency, the SYS DIS command turns
out invalid and the power down mode fails to be
carried out until the external clock source is re
moved.

Buzzer tone output

A simple tone generator is implemented in the
HT16220. The tone generator can output a pair
of differential driving signals on the BZ and BZ
which are used to generate a single tone.

The following are the data mode ID and the
command mode ID:

-

Operation Mode ID

READ Data 1 1 0

WRITE Data 1 0 1

READ-MODIFY-WRITE Data 1 0 1

COMMAND Command 1 0 0

If successive commands have been issued, the
command mode ID can be omitted. While the

Command format

The HT16220 can be configured by the software
setting. There are two mode commands to con­figure the HT16220 resource and to transfer
the LCD display data.

system is operating in the non-successive com­mand or the non-successive address data mode,

pin should be set to ²1² and the previous

the CS
operation mode will be reset also. The CS
returns to ²0², a new operation mode ID should
be issued first.

Name Command Code Function

TONE OFF 0000-1000-X Turn-off tone output

TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4kHz

TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2kHz

IR Q

pin

9 April 21, 2000

Timing Diagrams

READ mode (command code:110)

CS

WR

RD

HT16220

DATA

0A5A4A3 A2

1

1

M em ory Address 1 (M A1)

A1 A0 D0 D1

READ mode (successive address reading)

CS

WR

RD

DATA

1

1

0A5A4A3 A2

M em ory Address (M A) D ata (M A )

A1 A0 D0 D1

D2 D3

Data (MA1)

D2 D3

0A5A4A3 A2

1

1

M em ory Address 2 (M A2)

D2 D3

D0 D1

D ata (M A+1) D ata (M A +2) Data (M A +3)

D0 D1

A1A0D0 D1

D2 D3

D0 D1

Data (MA2)

D2

D2 D3

D3

D0

10 April 21, 2000

WRITE mode (command code:101)

CS

WR

HT16220

DATA

1A5A4A3 A2

1

0

M em ory Address 1 (M A1) D ata (M A 1)

A1 A0 D0 D1

WRITE mode (successive address writing)

CS

WR

DATA

1

0

1A5A4A3 A2

M em ory Address (M A) D ata (M A )

A1 A0 D0 D1

D2 D3

D2 D3

1A5A4A3 A2

1

0

M em ory Address 2 (M A2) D ata (M A 2)

D2 D3

D0 D1

D ata (M A+1) D ata (M A +2) Data (M A +3)

D0 D1

A1 A0 D0 D1

D2 D3

D0 D1

D2 D3

D2 D3

D0

11 April 21, 2000

READ-MODIFY-WRITE mode (command code:101)

CS

WR

RD

HT16220

DATA

1A5A4A3 A2

1

0

M em ory A ddress 1 (M A 1) D ata (M A1)

A1 A0 D0 D1

D2 D3

D0 D1

Data (M A1)

D2 D3

READ-MODIFY-WRITE mode (successive address accessing)

CS

WR

RD

DATA

1

0

1A5A4A3 A2

M em ory A ddress (M A) D ata (M A )

A1 A0 D 0 D1

D2 D3

D2 D3

D0 D1

D ata (M A ) D ata (M A+1) Data (M A+ 1)

D0 D1

1

A5A4A3 A2

1

0

M em ory A ddress 2 (M A 2) D ata (M A2)

D2 D3

D0 D1

D2 D3

A1 A0 D 0 D1

D2 D3

D0

D1

Data (M A+2)

D2 D3

D0

12 April 21, 2000

Command mode (command code:100)

CS

WR

HT16220

DATA

1

0

0C8C7C6 C5

C4 C3 C2 C1

C om m and 1

Mode (data and command mode)

CS

WR

DATA

RD

C om m and

or

D ata M ode

Address and D ata

C0

C om m and

D ata M ode

C8C7C6 C5

or

C4 C3 C2 C1

C om m and iC om m and... C om m and

Address and D ata

C om m and

D ata M ode

C0

or

or

D ata M ode

Address and D ata

13 April 21, 2000

Application Circuits

HT16220

*Note:

CS

*

RD

WR

m

C

DATA

H T16220

*

R

IR Q

COM 0~COM7 SEG0~SEG31

1/4 B ias, 1/8 D uty

VDD

VLCD

BZ

BZ

OSCI

OSCO

LC D Panel

The connection of IRQ

The voltage applied to V

Adjust VR to fit LCD display, at V

and RD pin can be selected depending on the requirement of the mC.

pin must be lower than VDD.

LCD

DD

=5V, V

=4V, VR=15kW±20%.

LCD

Adjust R (external pull-high resistance) to fit user¢s time base clock.

*

VR

Piezo

C rystal 32768H z oscillator

14 April 21, 2000

Command Summary

Name ID Command Code D/C Function Def.

READ

WRITE

READ­MODIFY­WRITE

SYS DIS

SYS EN

LCD OFF

LCD ON

TIMER DIS

WDT DIS

TIMER EN

WDT EN

TONE OFF

CLR TIMER

CLR WDT

TONE 4K

TONE 2K

DIS

IRQ

EN

IRQ

F1

F2

F4

F8

F16

A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM

110

A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM

101

A5A4A3A2A1A0D0D1D2D3 D Read and Write data to the RAM

101

0000-0000-X C

100

0000-0001-X C Turn on system oscillator

100

0000-0010-X C Turn off LCD display Yes

100

0000-0011-X C Turn on LCD display

100

0000-0100-X C Disable time base output Yes

100

0000-0101-X C Disable WDT time-out flag output Yes

100

0000-0110-X C Enable time base output

100

0000-0111-X C Enable WDT time-out flag output

100

0000-1000-X C Turn off tone outputs Yes

100

0000-1101-X C

100

0000-1111-X C Clear the contents of the WDT stage

100

010X-XXXX-X C Tone frequency output: 4kHz

100

0110-XXXX-X C Tone frequency output: 2kHz

100

100X-0XXX-X C Disable IRQ output Yes

100

100X-1XXX-X C Enable IRQ output

100

101X-0000-X C

100

101X-0001-X C

100

101X-0010-X C

100

101X-0011-X C

100

101X-0100-X C

100

Turn off both system oscillator
and LCD bias generator

Clear the contents of the time base
generator

Time base clock output: 1Hz
The WDT time-out flag after: 4s

Time base clock output: 2Hz
The WDT time-out flag after: 2s

Time base clock output: 4Hz
The WDT time-out flag after: 1s

Time base clock output: 8Hz
The WDT time-out flag after: 1/2 s

Time base clock output: 16Hz
The WDT time-out flag after: 1/4 s

HT16220

Yes

15 April 21, 2000

HT16220

Name ID Command Code D/C Function Def.

F32

F64

F128

TEST

NORMAL

Note:

X : Don¢t care

A5~A0 : RAM address

D3~D0 : RAM data

D/C : Data/Command mode

Def. : Power on reset default

All the bold forms, namely 110, 101, and 100, are mode commands. Of these, 100indicates the
command mode ID. If successive commands have been issued, the command mode ID except for the
first command will be omitted. The source of the tone frequency and of the time base/WDT clock fre
quency can be derived from a 32.768kHz crystal oscillator or an external 32kHz clock. Calculation of
the frequency is based on the system frequency sources as stated above. It is recommended that the
host controller should initialize the HT16220 after power on reset, for power on reset may fail, which
in turn leads to malfunctioning of the HT16220.

101X-0101-X C

100

101X-0110-X C

100

101X-0111-X C

100

1110-0000-X C

100

1110-0011-X C Normal mode Yes

100

Time base clock output: 32Hz
The WDT time-out flag after: 1/8 s

Time base clock output: 64Hz
The WDT time-out flag after: 1/16 s

Time base clock output: 128Hz
The WDT time-out flag after: 1/32 s

Test mode, user don¢t use.

Yes

-

16 April 21, 2000

HT16220

Holtek Semiconductor Inc. (Headquarters)

No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: [phone]
Fax: [phone]

Holtek Semiconductor Inc. (Taipei Office)

5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: [phone]
Fax: [phone]
Fax: [phone] (International sales hotline)

Holtek Semiconductor (Hong Kong) Ltd.

RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: [phone]
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Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

17 April 21, 2000

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