Datasheet HT1622 Datasheet (Holtek Semiconductor Inc)

RAM Mapping 32´8 LCD Controller for I/O mC

Features

Operating voltage: 2.7V~5.2V

·

Built-in RC oscillator

·

1/4 bias, 1/8 duty, frame frequency is 64Hz

·

Max. 32´8 patterns, 8 commons, 32 segments

·

Built-in internal resistor type bias generator

·

3-wire serial interface

·

8 kinds of time base/WDT selection

·

Time base or WDT overflow output

·

Built-in LCD display RAM

·

R/W address auto increment

·

General Description

HT1622 is a peripheral device specially de signed for I/O type mC used to expand the dis play capability. The max. display segment of the device are 256 patterns (32´8). It also sup ports serial interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1622 is a memory mapping and multi-func tion LCD controller. The software configuration

HT1622

Two selectable buzzer frequencies

·

(2kHz/4kHz) Power down command reduces power

·

consumption Software configuration feature

·

Data mode and Command mode instructions

·

Three data accessing modes

·

VLCD pin to adjust LCD operating voltage

·

Cascade application

·

feature of the HT1622 make it suitable for mul

tiple LCD applications including LCD modules

and display subsystems. Only three lines are required for the interface between the host con

troller and the HT1622. The HT162X series have many kinds of products that match vari ous applications.

-

Selection Table

HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270

COM 44

SEG 32 32

Built-in Osc.

Crystal Osc.

Ö Ö Ö ÖÖÖ Ö

Ö Ö ÖÖÖÖ

8

32

888161616

32 48 64 48 64 64

1 April 21, 2000

Block Diagram

OSCI

CS

RD

WR

DATA

C ontrol

and Tim ing Circuit

D isp lay R A M

LC D D river/ Bias Circuit

HT1622

COM 0

COM 7

SEG 0

Pin Assignment

VDD

VSS

BZ

CS

NC

RD

WR

DATA

VSS

OSCI

VDD

VLCD

IR Q

BZ

NC

BZ

T1

T2

T3

COM 0

COM 1

NC

Tone Frequency

G enerator

SEG28

SEG29

SEG30

SEG31

61

62

63

64

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

23

2021222425262728293031

W atchdog Tim er

Tim e B ase G enerator

SEG23

SEG24

SEG25

SEG26

SEG27

56

57

58

59

60

H T1622

-

64 Q FP

and

SEG22

55

SEG 31

VLCD

IR Q

SEG20

SEG21

NC

52

53

54

NC

51 50

NC

49

SEG19

48

SEG18

47

SEG17

46

SEG16

45

SEG15

44

SEG14

43

SEG13

42

SEG12

41

SEG11

40

SEG10

39

SEG9

38

SEG8

37

SEG7

36

NC

35

NC

34

32

NC

33

COM 5

COM 2

COM 3

COM 4

COM 6

COM 7

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

2 April 21, 2000

Pad Assignment

CS

RD

WR

DATA

VSS

OSCI

VDD

VLCD

IR Q

BZ

T1

T2

T3

COM 0

COM 1

HT1622

SEG 31

SEG 30

SEG 29

SEG 28

SEG 27

SEG 26

SEG 25

SEG 24

SEG 23

SEG 22

SEG 21

SEG 20

1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

COM 2

COM 3

COM 4

COM 5

4317441845194620472148224923502451255226532754

(0 ,0 )

28229

COM 6

COM 7

SEG 0

SEG 1

SEG 2

SEG 3

SEG 4

SEG 5

42

SEG19

41

SEG18

40

SEG17

39

SEG16

38

SEG15

37

SEG14

36

SEG13

35

SEG12

34

SEG11

33

SEG10

32

SEG9

31

SEG8

30

SEG7

SEG 6

Chip size: 149 ´ 155 (mil)

2

* The IC substrate should be connected to VDD in the PCB layout artwork.

3 April 21, 2000

HT1622

Pad Coordinates Unit: mil

Pad No. X Y Pad No. X Y

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 5.48 23 15.00 24 21.63 25 28.26 26 34.89 27 41.52

-68.43

-69.19

-69.36

-69.36 -3.57

-69.36 -16.92

-69.36 -33.83

-69.36 -43.52

-69.36 -50.15

-69.36 -56.78

-69.36 -63.41

-69.36 -70.04

-39.23 -71.14

-32.60 -71.14

-20.19 -71.14

-13.56 -71.14

-1.15 -71.14

71.78 28 48.15

59.46 29 54.78

52.83 30 69.32

39.14 31 69.32

23.89 32 69.32 2.59

16.32 33 69.32 9.22

9.69 34 69.32 15.85

3.06 35 69.32 22.48 36 69.32 29.11 37 69.32 35.74 38 69.32 42.37 39 69.32 49.00 40 69.32 55.63 41 69.32 62.26 42 69.32 68.89 43 14.19 71.78 44 7.57 71.78 45 0.94 71.78

-71.14

-71.91

46 47 48 49 50 51 52 53 54

-5.70

-12.32

-18.95

-25.58

-32.22

-38.85

-45.47

-52.10

-58.74

-71.91

-10.67

-4.04

71.78

4 April 21, 2000

Pad Description

Pad No. Pad Name I/O Description

Chip selection input with Pull-high resistor. When the CS high, the data and command read from or written to the HT1622

1CS

2RD

3WR

4 DATA I/O Serial data input/output with Pull-high resistor

5 VSS

6 OSCI I

7 VDD

8 VLCD I LCD operating voltage input pad

9 IRQ O

10, 11 BZ, BZ

12~14 T1~T3 I Not connected

15~22 COM0~COM7 O LCD common outputs

23~54 SEG0~SEG31 O LCD segment outputs

are disabled. The serial interface circuit is also reset. But if CS

I

at logic low level and is input to the CS mand transmission between the host controller and the HT1622 are all enabled.

READ clock input with Pull-high resistor. Data in the RAM of the HT1622 are clocked out on the rising edge of the RD

I

The clocked out data will appear on the data line. The host con troller can use the next falling edge to latch the clocked out data.

WRITE clock input with Pull-high resistor. Data on the DATA

I

line are latched into the HT1622 on the rising edge of the WR sig nal.

Negative power supply, ground

¾

If the system clock comes from an external clock source, the ex ternal clock source should be connected to the OSCI pad.

Positive power supply

¾

Time base or Watchdog Timer overflow flag, NMOS open drain output

O 2kHz or 4kHz tone frequency output pair

pad, the data and com

HT1622

is logic

is

-

signal.

-

Absolute Maximum Ratings

Supply Voltage..............................-0.3V to 5.5V

Input Voltage ................V

Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi

mum Ratings may cause substantial damage to the device. Functional operation of this de vice at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

-0.3V to VDD+0.3V

SS

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-25°Cto75°C

5 April 21, 2000

-

HT1622

D.C. Characteristics

Symbol Parameter

V

I

V

I

R

DD

DD1

DD2

STB

IL

IH

OL1

OH1

OL1

OH1

OL2

OH2

OL3

OH3

PH

Operating Voltage

Operating Current

Standby Current

Input Low Voltage

Input High Voltage

BZ, BZ, IRQ

BZ, BZ

DATA

LCD Common Sink Current

LCD Common Source Current

LCD Segment Sink Current

LCD Segment Source Current

Pull-high Resistor

Test Conditions

V

DD

Conditions

¾¾

3V

No load/LCD ON On-chip RC oscillator

5V

3V

No load/LCD OFF On-chip RC oscillator

5V

3V

No load Power down mode

5V

3V

DATA, WR,CS,RD

5V 0

3V

DATA, WR,CS,RD

5V 4.0

V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V 50 100 150

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

DATA, WR,CS,RD

Min. Typ. Max. Unit

2.7

¾ ¾ ¾ ¾ ¾ ¾

0

¾

80 210

135 415

830

20 55

18

216

¾ ¾

2.4

¾ ¾

0.9 1.8

1.7 3

-0.9 -1.8 ¾

-1.7 -3 ¾

200 450

250 500

-200 -450 ¾mA

-250 -500 ¾mA

15 40

100 200

-15 -30 ¾mA

-45 -90 ¾mA

15 30

70 150

-6 -13 ¾mA

-20 -40 ¾mA

100 200 300

Ta=25°C

5.2 V

mA mA mA mA mA mA

0.6 V

1.0 V

3V

5V

mA

¾

mA

¾

mA

¾mA ¾mA

kW kW

6 April 21, 2000

HT1622

A.C. Characteristics

Symbol Parameter

f

SYS1

f

SYS2

f

LCD1

f

LCD2

t

COM

f

CLK1

f

CLK2

t

CS

t

CLK

t

r,tf

t

su

t

h

t

su1

t

h1

System Clock 3V On-chip RC oscillator 22 32 40 kHz

System Clock

LCD Frame Frequency

LCD Common Period

Serial Data Clock (WR pin)

Serial Data Clock (RD pin)

Serial Interface Reset Pulse Width (Figure 3)

WR,RDInput Pulse Width

Rise/Fall Time Serial Data Clock Width (Figure 1)

Setup Time for DATA to WR, RD

Clock Width (Figure 2)

Hold Time for DATA to WR, RD

, Clock Width (Figure 2)

Setup Time for CS to WR,RD Clock Width (Figure 3)

Hold Time for CS to WR,RD Clock Width (Figure 3)

(Figure 1)

Ta=25°C

Test Conditions

Min. Typ. Max. Unit

V

DD

Conditions

5V 24 32 40 kHz

3V

¾

32

¾

kHz

External clock source

5V

3V

¾

32

¾

kHz

44 64 80 Hz

On-chip RC oscillator

5V 48 64 80 Hz

3V

¾

64

¾¾

External clock source

5V

n: Number of COM

¾

3V

64

¾

n/f

¾

LCD

¾¾

¾

150 kHz

Duty cycle 50%

5V

3V

¾¾

300 kHz

75 kHz

Duty cycle 50%

5V

CS

¾

Write mode 3.34

¾¾

¾

150 kHz

250

¾

¾¾

3V

Read mode 6.67

Write mode 1.67

¾¾

5V

Read mode 3.34

¾¾

3V

¾¾

120

¾

5V

3V

¾¾

120

¾

5V

3V

¾¾

120

¾

5V

3V

¾¾

100

¾

5V

3V

¾¾

100

¾

5V

sec

ns

ms

ns

7 April 21, 2000

HT1622

D

(D3,

)

WR, RD Clock

90%

50%

10%

t

f

t

CLK

t

r

t

CLK

V

GN

DD

Figure 1

t

W R , R D Clock

CS

50%

FIR ST

t

su1

50%

Clock

LAST Clock

CS

t

h1

V

DD

GND

V

DD

GND

Figure 3

Functional Description

Display memory - RAM structure

The static display RAM is organized into 64´4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns.

COM 4COM 5COM 6COM 7

W R , R D Clock

DB

VALID DATA

50%

t

su

50%

t

h

V

GN

V

GN

DD

Figure 2

Time base and Watchdog Timer (WDT)

The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ

pin will remain at logic low level until the CLR WDT or the IRQ

DIS command is issued.

COM 0COM 1COM 2COM 3

SEG 0

SEG 1

SEG 2

SEG 3

SEG 31

D3 D2 D1 D0

1

3

5

7

63

Addr

Data

Data 4 Bits

D3 D2 D1 D0

D 2, D 1, D 0

RAM mapping

8 April 21, 2000

Data

0

2

4

6

(A 5 , A 4 , ...., A 0 )

62

Addr

Address 6 B its

HT1622

Tim e B ase

C lo ck S o urce

/256

CLR Timer

V

WDT

/4

CLR W DT

TIM ER EN /D IS

W D T E N /D IS

DD

D

CK

R

Q

IR Q E N /D IS

Timer and WDT configurations

If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is re moved.

Buzzer tone output

A simple tone generator is implemented in the HT1622. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone.

The following are the data mode ID and the command mode ID:

-

Operation Mode ID

READ Data 1 1 0

WRITE Data 1 0 1

READ-MODIFY-WRITE Data 1 0 1

COMMAND Command 1 0 0

If successive commands have been issued, the command mode ID can be omitted. While the

Command format

The HT1622 can be configured by the software setting. There are two mode commands to configure the HT1622 resource and to transfer the LCD display data.

system is operating in a non-successive command or a non-successive address data mode, the CS

pin should be set to "1" and the previous operation mode will be reset also. The CS returns to "0", a new operation mode ID should be issued first.

Name Command Code Function

TONE OFF 0000-1000-X Turn-off tone output

TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4kHz

TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2kHz

IR Q

9 April 21, 2000

Timing Diagrams

READ mode (command code:110)

CS

WR

RD

HT1622

DATA

0A5A4A3 A2

1

M em ory A ddress 1 (M A1) D ata (M A2)

A1A0D0D1

D ata (M A1) M em ory A ddress 2 (M A2)

READ mode (successive address reading)

CS

WR

RD

DATA

1

0A5A4A3 A2

M e m o ry A d d re s s (M A ) D a ta (M A )

A1A0D0D1

D2

D3

D2

0A5A4A3 A2

1

D2

D3

D0D1

D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )

D3

D0D1

A1A0D0D1

D2

D3

D0D1

D2

D3

D0

10 April 21, 2000

WRITE mode (command code:101)

CS

WR

HT1622

DATA

1A5A4A3 A2

1

0

M em ory A ddress 1 (M A1)D ata (M A1)

A1A0D0D1

WRITE mode (successive address writing)

CS

WR

DATA

1A5A4A3 A2

1

0

M e m o ry A d d re s s (M A ) D a ta (M A )

A1A0D0D1

D2

D3

D2

1A5A4A3 A2

1

0

M em ory A ddress 2 (M A2)D ata (M A2)

D2

D3

D0D1

D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )

D3

D0D1

A1A0D0D1

D2

D3

D0D1

D2

D3

D0

11 April 21, 2000

READ-MODIFY-WRITE mode (command code:101)

CS

WR

RD

HT1622

DATA

1A5A4A3 A2

1

0

M em ory A ddress 1 (M A1)D ata (M A1)

A1A0D0D1

D2

D3

D2

D0D1

D a ta ( M A 1 )

D3

EAD-MODIFY-WRITE mode (successive address accessing)

CS

WR

RD

DATA

1

0

1A5A4A3 A2

M e m o ry A d d re s s (M A ) D a ta (M A )

A1A0D0D1

D2

D3

D2

D0D1

D a ta ( M A ) D a ta (M A + 1 ) D a ta (M A + 1 )

D3

1

D0D1

A5A4A3 A2

1

0

M em ory A ddress 2 (M A2)D ata (M A2)

D2

D3

D0D1

A1A0D0D1

D2

D3

D2

D0

D1

D a ta ( M A + 2 )

D2

D3

D0

12 April 21, 2000

Command mode (command code:100)

CS

WR

HT1622

DATA

1

0

0C8C7C6 C5

C4C3C2C1

C om m and 1

Mode (data and command mode)

CS

WR

DATA

RD

C om m and

or

D a ta M o d e

Address and D ata

C0

C om m and

or

D a ta M o d e

C8C7C6 C5

Address and D ata

C4C3C2C1

C om m and iC om m and... C om m and

C0

C om m and

or

D a ta M o d e

or

D a ta M o d e

Address and D ata

13 April 21, 2000

Application Circuits

HT1622

CS

*

RD

m

C

WR

DATA

*

R

IR Q

C O M 0 ~ C O M 7 S E G 0 ~ S E G 3 1

H T 1622

1/4 Bias, 1/8 D uty

LC D Panel

Note:

The connection of IRQ

The voltage applied to V

Adjust VR to fit LCD display, at V

and RD pin can be selected depending on the requirement of the mC.

pin must be lower than VDD.

LCD

DD

=5V, V

=4V, VR=15kW±20%.

LCD

Adjust R (external pull-high resistance) to fit user s time base clock.

VDD

VLCD

BZ

*

VR

Piezo

14 April 21, 2000

HT1622

Command Summary

Name ID Command Code D/C Function Def.

READ 110 A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM

WRITE 101 A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM

READMODIFYWRITE

SYS DIS 1000000-0000-X C

SYS EN 100 0000-0001-X C Turn on system oscillator

LCD OFF 100 0000-0010-X C Turn off LCD display Yes

LCD ON 100 0000-0011-X C Turn on LCD display

TIMER DIS 1000000-0100-X C Disable time base output Yes

WDT DIS 100 0000-0101-X C Disable WDT time-out flag output Yes

TIMER EN 1000000-0110-X C Enable time base output

WDT EN 100 0000-0111-X C Enable WDT time-out flag output

TONE OFF 100 0000-1000-X C Turn off tone outputs Yes

CLR TIMER 1000000-1101-X C

CLR WDT 100 0000-1111-X C Clear the contents of WDT stage

RC 32K 100 0001-10XX-X C

EXT 32K 100 0001-11XX-X C

TONE 4K 100 010X-XXXX-X C Tone frequency output: 4kHz

TONE 2K 100 0110-XXXX-X C Tone frequency output: 2kHz

IRQ

DIS 100 100X-0XXX-X C Disable IRQ output Yes

EN 100100X-1XXX-X C Enable IRQ output

IRQ

F1 100 101X-0000-X C

F2 100 101X-0001-X C

F4 100 101X-0010-X C

F8 100 101X-0011-X C

101 A5A4A3A2A1A0D0D1D2D3 D Read and Write data to the RAM

Turn off both system oscillator and LCD bias generator

Clear the contents of the time base generator

System clock source, on-chip RC oscillator

System clock source, external clock source

Time base clock output: 1Hz The WDT time-out flag after: 4s

Time base clock output: 2Hz The WDT time-out flag after: 2s

Time base clock output: 4Hz The WDT time-out flag after: 1s

Time base clock output: 8Hz The WDT time-out flag after: 1/2 s

Yes

15 April 21, 2000

HT1622

Name ID Command Code D/C Function Def.

F16 100 101X-0100-X C

F32 100 101X-0101-X C

F64 100 101X-0110-X C

F128 100 101X-0111-X C

TEST 1001110-0000-X C Test mode, user don t use.

NORMAL 100 1110-0011-X C Normal mode Yes

Note: X : Don t care

A5~A0 : RAM address

D3~D0 : RAM data

D/C : Data/Command mode

Def. : Power on reset default

All the bold forms, namely 110, 101, and 100, are mode commands. Of these, 100indicates the command mode ID. If successive commands have been issued, the command mode ID ex cept for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 32kHz RC oscillator or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1622 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1622.

Time base clock output: 16Hz The WDT time-out flag after: 1/4 s

Time base clock output: 32Hz The WDT time-out flag after: 1/8 s

Time base clock output: 64Hz The WDT time-out flag after: 1/16 s

Time base clock output: 128Hz The WDT time-out flag after: 1/32 s

Yes

-

16 April 21, 2000

HT1622

Holtek Semiconductor Inc. (Headquarters)

No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189

Holtek Semiconductor Inc. (Taipei Office)

5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline)

Holtek Semiconductor (Hong Kong) Ltd.

RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applicationsmentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

17 April 21, 2000

-