Datasheet HD74CDC857 Datasheet (HIT)

HD74CDC857

3.3/2.5-V Phase-lock Loop Clock Driver

ADE-205-222E (Z)

6th. Edition

July 1999

Description

The HD74CDC857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is
specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.

Features

• Supports 100 MHz to 150 MHz operation range

• Distributes one differential clock input pair to ten differential clock outputs pairs

• SSTL_2 (Stub Series Terminated Logic) differential inputs and LVCMOS reset (G) input

• Supports spread spectrum clock

• External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input

• Supports both 3.3 V/2.5V analog supply voltage (AVCC), and 2.5 V V

• No external RC network required

• Sleep mode detection

• 48pin TSSOP (Thin Shrink Small Outline Package)

Note: 1. 200 MHz (Max) ver. will be available by 4Q/’99

*1

DDQ

Function Table

Inputs : Outputs : PLL
G CLK CLK : Y Y FBOUT FBOUT

LLH:ZZZZ:off
LHL:ZZZZ:off
H L H : L H L H : run
HHL:HLHL:run
X 0 MHz 0 MHz : Z Z Z Z : off

H : High level
L : Low level
Z : High impedance
X : Don’t care

HD74CDC857

T

Pin Arrangement

GND

Y0

Y0

V

DDQ

Y1

Y1

GND
GND

Y2

Y2

V

DDQ

V

DDQ

CLK

CLK

V

DDQ

AV

CC

AGND

GND

Y3

Y3

V

DDQ

Y4

Y4

GND

10
11
12
13
14
15
16
17
18

19

20
21
22
23
24

GND

1
2

3
4
5

6
7

8

9

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

Y5

Y5
V

DDQ

Y6

Y6

GND
GND

Y7

Y7
V

DDQ

G
FBIN

FBIN

V

DDQ

FBOU

FBOUT
GND

Y8

Y8
V

DDQ

Y9

Y9

GND

(Top view)

2

HD74CDC857

Q

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage V
Input voltage V
Output voltage

*1

Input clamp current I
Output clamp current I
Continuous output current I
Supply current through each V

or GND I

DDQ

V

IK

OK

O

VDDQ

DDQ

I

O

or I

Maximum power dissipation
at Ta = 55°C (in still air)

Storage temperature T

stg

Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage

to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.

1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.

–0.5 to 4.6 V
–0.5 to 4.6 V
–0.5 to V

DD

V

+0.5
–50 mA VI < 0
–50 mA VO < 0

±50 mA VO = 0 to V
±100 mA

GND

0.7 W

–65 to +150 °C

DDQ

3

HD74CDC857

Q

Q

Recommended Operating Conditions

Item Symbol Min Typ Max Unit Conditions

Supply voltage AV

(1) 2.3 — 2.7 V f

CC

AVCC (2) 3.0 — 3.6 f
Output supply voltage V
DC input signal voltage

*1

High level input voltage V
Low level input voltage V
High level input voltage V
Low level input voltage V
Differential input signal voltage *2V

Differential cross point voltage

Reference voltage

*4

*3

Output current I

DDQ

IHD

ILD

IHG

ILG

ID

V

ref

OH

I

OL

2.3 — 2.7 V
–0.3 — V

+0.3 V All pins

DDQ

1.7 — — V
— — 0.8 V

1.7 — V

+0.3 V G input pin

DDQ

–0.3 — 0.7 V G input pin

0.36 — V

0.7 — V

0.5×V

— 0.5×V

DD

–0.35

+0.6 V DC

DDQ

+0.6 AC

DDQ

DD

+0.35

V

1.15 1.25 1.35 V Vref = 0.5 × V
–7 — –30 mA

7—30
Input slew rate SR 1 — — V/ns
Operating temperature T

a

0—70°C
Notes: Unused inputs must be held high or low to prevent them from floating.

Feedback inputs (FBIN, FBIN) may float when the device is in low power mode.

1. DC input signal voltage specifies the allowable dc execution of differential input.

2. Differential input signal voltage specifies the differential voltage |VTR–VCP| required for
switching, where VTR is the true input level and VCP is the complementary input level.

3. Differential cross point voltage is expected to track variations of V

and is the voltage at which

DDQ

the differential signals must be crossing. (See figure1-1)

4. V

is the reference DC level, when using single clock input. When CLK (pin#13) is single ended

ref

input, CLK (pin#14) must be set V

. (See figure1-2)

ref

= 100 to 150 MHz

CLK

= 130 to 150 MHz

CLK

DDQ

4

VTR

VCP

V

ID

Crossing point

Figure 1-1 Differential input levels

HD74CDC857

V

DDQ

GND

CLK

CLK

Figure 1-2 Single input levels

V

DDQ

V

ref

GND

CLK

*4

CLK

V

ref

5

HD74CDC857

Logic Diagram

G

CLK

CLK

FBIN

FBIN

AV

CC

PLL

Y0

Y0

Y1

Y1

Y2

Y2

Y3

Y3

Y4

Y4

Y5

Y5

Y6

Y6

Y7

Y7

Y8

Y8

Y9

Y9

FBOUT

FBOUT

Note: All inputs and outputs are associated with V = 2.5 V.

DDQ

6

HD74CDC857

CC

CC

Pin Function

Pin name No. Type Description

AGND 17 Ground Analog ground. AGND provides the ground reference for the

analog circuitry.

AV

CC

CLK, CLK 13, 14 I Clock input. CLK provides the clock signal to be distributed by the

FBIN, FBIN 35, 36 I Feedback input. FBIN provides the feedback signal to the internal

FBOUT, FBOUT 32, 33 O Feedback output. FBOUT is dedicated for external feedback. It

G 37 I Output bank enable. G is the output enable for all outputs. When

GND 1, 7, 8, 18,

V

DDQ

Y 3, 5, 10, 20,

Y 2, 6, 9, 19,

16 Power Analog power supply. AVCC provides the power reference for the

analog circuitry. In addition, AV
for test purposes. When AV

can be used to bypass the PLL

is strapped to ground, PLL is

bypassed and CLK is buffered directly to the device outputs.

HD74CDC857 clock driver. CLK is used to provide the reference
signal to the integrated PLL that generates the clock output
signals. CLK must have a fixed frequency and fixed phase for the
PLL to obtain phase lock. Once the circuit is powered up and a
valid CLK signal is applied, a stabilization time is required for the
PLL to phase lock the feedback signal to its reference signal.

PLL. FBIN must be hard-wired to FBOUT to complete the PLL.
The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.

switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.

G is low, VCO will stop and all outputs are disabled to a high
impedance state. When G will be returned high, PLL will re­synchroniz to CLK frequency and all outputs are enabled.

Ground Ground
24, 25, 31,
41, 42, 48

4, 11, 12,

Power Power supply
15, 21, 28,
34, 38, 45

O Clock outputs. These outputs provide low-skew copies of CLK.
22, 27, 29,
39, 44, 46

O Clock outputs. These outputs provide low-skew copies of CLK.
23, 26, 30,
40, 43, 47

7

HD74CDC857

Electrical Characteristics

Item Symbol Min Typ *1Max Unit Test Conditions

Input clamp
voltage

CLK, CLK
FBIN, FBIN, G

Output voltage V

Input current I
Input capacitance C

Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended

operating conditions.

Switching Characteristics

V

IK

OH

— — –1.2 V II = –18 mA, V

= 2.3 V

DDQ

VCC–0.2 — — V IOH = –100 µA, VCC = 2.3 to 2.7 V

1.95 — — IOH = –8 mA, VCC = 2.3 V

1.70 — — IOH = –16 mA, VCC = 2.3 V

V

OL

— — 0.2 IOL = 100 µA, VCC = 2.3 to 2.7 V
— — 0.35 IOL = 8 mA, VCC = 2.3 V
— — 0.55 IOL = 16 mA, VCC = 2.3 V

I

I

——±10 µAVI = 0 V to 2.7 V, V
——4pF

= 2.7 V

DDQ

Item Symbol Min Typ Max Unit Test Conditions

Cycle to cycle jitter –100 — 100 ps See figure 2
Phase error time t
Output skew t
Differential clock skew t

(phase error)

sk (o)

sk (diff)

–150 — 150 ps See figure 2, 3, 4
— — 200 ps See figure 2

–100 — 100 ps See figure 2
Duty cycle 45 — 55 % See figure 2
Output impedance Z
Clock frequency f

O

CLK

—25—Ω See figure 2

100 — 150

130 — 150

*1

MHz See figure 2, AVCC = 2.5±0.2 V

*1

See figure 2, AVCC = 2.5±0.2 V
or AV

= 3.3±0.3 V

CC

Slew rate 1.2 — — V/ns See figure 2
Stabilization time — — 0.1 ms See figure 2, 3

Note: 1. 200 MHz (Max) ver. will be available by 4Q/’99.

8

HD74CDC857

Differential clock outputs are directly terminated by a 120 Ω resistor. Figure 2 is typical usage conditions
of outputs load.

V

DDQ

V

DDQ

Device
under
test

OUT

R =

T

120 Ω

OUT

Figure 2 Differential signal using direct termination resistor

V

IH

V +0.35 V

Differential cross
point voltage

V

0.5 × V

ref

V

IH

V

IL

DDQ

1.7 V

0.8 V

ref

V

ref

V –0.35 V

ref

V

IL

Figure 3 CLKIN waveforms

9

HD74CDC857

(Differential input)

CLKIN

FBIN

t

(phase error)

CLKIN

(Single input)

FBIN

FBOUT

Yx

Yx

Yx'

t

(phase error)

t

sk(o)

V

ref

10

Yx

Yx

t

sk(o)

t

sk(diff)

Figure 4 Timings

Package Dimensions

12.50

+0.3
–0.1

HD74CDC857

Unit : mm

2548

+0.3

–0.1

6.10

124

+0.1

0.20

–0.05

0.50

0.08

M

0.65 Max

0.10

0.05 Min

1.20 max

8.10 ± 0.3

0.15 ± 0.05

Hitachi code

EIAJ code

JEDEC code

10° Max

0.50 ± 0.1

TTP-48DC

—
—

11

HD74CDC857

Cautions

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copyright, trademark, or other intellectual property rights for information contained in this document.
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intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail­safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

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12

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