Datasheet HD74HC173 Datasheet (HIT)

Page 1

HD74HC173

4-bit D-type Register (with 3-state Outputs)

Description

The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level.

The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Clearing is enabled by taking the clear input to a logic high level. The data outputs change state on the positive going edge of the clock.

Features

• High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Function Table

Inputs

Data Enable

Clear Clock G

HXXXXL LLXXXQ L HXXQ

L XHXQ L LLLL L LLHH

Note: When either M or N (or both) is (are) high the output is disabled to the high-impedance state;

however sequential operation of the flip-flops is not affected.

Data D Output Q

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HD74HC173

Pin Arrangement

Output Control

Output

Clock

GND

Output

Control

Clear

Data Enable

Clear

Data Input

Data Enable Input

(Top view)

Absolute Maximum Ratings

Item Symbol Rating Unit

Supply voltage range V Input voltage V Output voltage V DC current drain per pin I DC current drain per VCC, GND ICC, I DC input diode current I DC output diode current I Power dissipation per package P

OUT

GND

Storage temperature Tstg –65 to +150 °C

–0.5 to +7.0 V –0.5 to VCC + 0.5 V –0.5 to VCC + 0.5 V

±35 mA ±75 mA ±20 mA ±20 mA

500 mW

Page 3

Block Diagram

4D G

HD74HC173

DQ C

Clock

Clear

Control M

Control N

Page 4

HD74HC173

DC Characteristics

Ta = –40 to

Ta = 25°C

Item Symbol V

Input voltage V

(V) Min Typ Max Min Max Unit Test Conditions

2.0 1.5 — — 1.5 — V

4.5 3.15 — — 3.15 —

6.0 4.2 — — 4.2 —

2.0 — — 0.5 — 0.5 V

4.5 — — 1.35 — 1.35

6.0 — — 1.8 — 1.8

Output voltage V

2.0 1.9 2.0 — 1.9 — V Vin = VIH or VILIOH = –20 µA

4.5 4.4 4.5 — 4.4 —

6.0 5.9 6.0 — 5.9 —

4.5 4.18 — — 4.13 — IOH = –6 mA

6.0 5.68 — — 5.63 — IOH = –7.8 mA

2.0 — 0.0 0.1 — 0.1 V Vin = VIH or VILIOL = 20 µA

4.5 — 0.0 0.1 — 0.1

6.0 — 0.0 0.1 — 0.1

4.5 — — 0.26 — 0.33 IOL = 6 mA

6.0 — — 0.26 — 0.33 IOL = 7.8 mA

Off-state output

6.0 — — ±0.5 — ±5.0 µA Vin = VIH or VIL,

current Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply

6.0 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA

current

+85°C

Vout = V

or GND

Page 5

AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)

Ta = –40 to

Ta = 25°C

Item Symbol V

Maximum clock f

max

(V) Min Typ Max Min Max Unit Test Conditions

2.0 — — 5 — 4 MHz

frequency 4.5 — — 27 — 21

6.0 — — 32 — 25 Propagation delay t time t

PLH

PHL

2.0 — — 175 — 220 ns Clock to Q

4.5 — 14 35 — 44

6.0 — — 30 — 37

PHL

2.0 — — 150 — 190 ns Clear to Q

4.5 — 14 30 — 38

6.0 — — 26 — 33 Enable time t

2.0 — — 150 — 190 ns

4.5 — 12 30 — 38

6.0 — — 26 — 33 Disable time t

2.0 — — 150 — 190 ns

4.5 — 12 30 — 38

6.0 — — 26 — 33 Setup time t

2.0 100 — — 125 — ns

4.5 20 4 — 25 —

6.0 17 – — 21 — Removal time t

rem

2.0 90 — — 115 — ns

4.5 18 0 — 23 —

6.0 15 — — 20 — Hold time t

2.0 5 — — 5 — ns

4.5 5 –2 — 5 —

6.0 5 — — 5 — Pulse width t

2.0 80 — — 100 — ns

4.5 16 4 — 20 —

6.0 14 — — 17 — Output rise/fall t time t

TLH

THL

2.0 — — 60 — 75 ns

4.5 — 4 12 — 15

6.0 — — 10 — 13 Input capacitance Cin — — 5 10 — 10 pF

+85°C

HD74HC173

Page 6

19.20

20.00 Max

16 9

1.3

Unit: mm

6.30

7.40 Max

1.11 Max

2.54 ± 0.25

0.48 ± 0.10

5.06 Max

2.54 Min

0.51 Min

Hitachi Code JEDEC EIAJ Weight

7.62

+ 0.13

0.25

– 0.05

0° – 15°

(reference value)

DP-16 Conforms Conforms

1.07 g

Page 7

Unit: mm

10.06

10.5 Max 9

5.5

0.80 Max

1.27

*0.42 ± 0.08

0.40 ± 0.06

*Dimension including the plating thickness

Base material dimension

0.12

0.10 ± 0.10

0.15

2.20 Max

7.80

0.20 ± 0.04

*0.22 ± 0.05

0.70 ± 0.20

Hitachi Code JEDEC EIAJ

(reference value)

Weight

+ 0.20 – 0.30

1.15

0° – 8°

FP-16DA — Conforms

0.24 g

Page 8

Unit: mm

9.9

10.3 Max 9

1.27

0.635 Max

*0.42 ± 0.08

0.40 ± 0.06

*Dimension including the plating thickness

Base material dimension

0.25

+ 0.11

– 0.04

0.14

0.15

3.95

1.75 Max

6.10

1.08

0.20 ± 0.03

*0.22 ± 0.03

0.60

Hitachi Code JEDEC EIAJ Weight

+ 0.10 – 0.30

0° – 8°

+ 0.67 – 0.20

(reference value)

FP-16DN Conforms Conforms

0.15 g

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Cautions

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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

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