Datasheet FX019P, FX019DW Datasheet (Consumer Microcircuits Limited)

1

Features

4 Digitally Controlled Amplifier s
15 Gain/Attenuation Steps
3 Amplifiers, with a ± 3dB Range

in 0.43dB Steps
1 'Volume' Amplifier, with a

± 14dB Range in 2dB Steps

FX019

Brief Description

This product replaces the need for manual trimming
of audible signals by using the host microprocessor to
digitally control the set-up of all audio levels during
development, production/calibration and operation.

Applications include:

(i) Control, adjustment and set-up of communications
equipment by an Intelligent ATE without manual
intervention – eg. Deviation, Microphone and L/S
Levels, Rx Audio Level etc.

(ii) Automatic Dynamic Compensation of drift caused
by variations in temperature, linearity, etc.

(iii)Fully automated servicing and re-alignment.
The FX019 is a low-power, single 5-volt CMOS

device available in plastic DIL and Small Outline
(S.O.I.C.) SMD package versions.

Publication D/019/4 December 1995

8-Bit Serial Data Control
Output Mute Function
Audio and Data Gain Control

Applications
Telecoms, Radio and Industrial

Applications

CML Semiconductor Products

FX019

2

3

3

3

4

4

SERIAL DATA
INPUT

LOAD/LATCH

LOAD/LATCH

CHIP SELECT

1

1

2

2

Ch1

Ch2

Ch4

Ch3

V

DD

V

BIAS

SERIAL CLOCK
INPUT

V

SS

8-BIT SERIAL DATA INPUT

AND

LINE DECODERS

CONTROLLED AUDIO OUTPUT LINES

VOLUME

Digitally Controlled
Quad Amplifier Array

PRODUCT INFORMATION

The FX019 Digitally Adjustable Amplifier Array is
available to replace trimmer potentiometers and
volume controls in Cellular, PMR, Telephony and
Communications applications where d.c., voice or
data signals need adjustment.
The FX019 is a single-chip LSI consisting of four
digitally controlled amplifier stages, each with 15
distinct gain/attenuation steps. Control of each
individual amplifier is by an 8-bit serial data stream.
Three of the amplifier stages offer a +/-3dB range in
steps of 0.43dB, whilst the remaining amplifier offers a
+/-14dB range in steps of 2dB, and is suggested for
volume control applications. Each amplifier includes a
16th 'Off' state which when applied, mutes the output
audio from that channel. This array uses a Chip
Select input to select one of two FX019s in a system.

Fig.1 Functional Block Diagram

2

Pin Number Function

FX019DW

FX019P

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Analogue Inputs :

These individual amplifier inputs are self-biasing, a.c. input
analogue signals must be capacitively coupled to these pins, as
shown in Figure 2.
Note that amplifiers Ch1 to Ch4 are 'inverting amplifiers.'

Controlled Analogue Outputs :

The individual "Gain Controlled" amplifier outputs.
Ch1 to Ch3 range from -3dB to +3dB in 0.43dB steps, Ch4 could be
utilized as a volume control, ranging from -14dB to +14dB in 2.0dB
steps.
In the “OFF” mode there is no output from the selected amplifier.

Serial Clock : This external clock pulse input is used to “clock in” the Control Data. See Figure 4,
Serial Control Data Load Timing. This input has an internal 1MΩ pullup resistor.

Load/Latch : Governs the loading and execution of the control data. During serial data loading
this input should be kept at a logical '0' to ensure that data rippling past the latches has no effect.
When all 8 bits have been loaded, this input should be strobed '0' - '1' - '0' to latch the new data in.
Data is executed on the falling edge of the strobe. If the Load/Latch input is used this pin should
be left open circuit. This input has an internal 1MΩ pullup resistor.

Load/Latch : The inverted Load/Latch input. This function governs the loading and execution of
the control data. During serial data loading this input should be kept at a logical '1' to ensure that
data rippling past the latches has no effect. When all 8 bits have been loaded, this input should be
strobed '1' - '0' - '1' to latch the new data in. Data is executed on the rising edge of the strobe.
If the Load/Latch input is used this pin should be left open circuit. This input has an internal 1MΩ
pulldown resistor.

Ch1 Input :

Ch2 Input :

Ch3 Input :

Ch4 Input :

V

SS

: Negative supply rail (GND).

V

BIAS

: The output of the on-chip bias circuitry, held at VDD/2. This pin should be decoupled to V

SS

as shown in Figure 2.

Ch4 Output :

Ch3 Output :

Ch2 Output :

Ch1 Output :

Chip Select : A logic input to select one of two FX019 microcircuits in a system, see Table 1.

This input has an internal 1MΩ pulldown resistor.

Control Data Input : Operation of the 4 amplifier channels (Ch1 – Ch4) is controlled by the 8 bits
of data entered serially at this pin. The data is entered (bit 7 to bit 0) on the rising edge of the
external Serial Clock. The data format is described in Tables 1, 2 and Figure 4. This input has an
internal 1MΩ pullup resistor.

V

DD

: Positive supply rail. A single +5-volt power supply is required.

3

Fig.3 SINAD vs Input Level – Typical Values

Application Notes

INPUT LEVEL dB

SINAD (dB)

30

40

50

60

-40

-30 -20 -10

0

10.0 25.0 75.0 250.0 775.0

1000.0

1730.0

-17

110.0

mVrms

7.0

Input Frequency = 1.0kHz
Input Level 0dB ref = 775mVrms
Ch1 2, 3 or 4 Gain Set to 0dB

V

DD

V

DD

V

SS

C

6

C

1

C

2

C

3

C

4

C

5

V

SS

V

BIAS

V

SS

1
2
3
4
5
6
7
8

16
15
14
13
12

11

10

9

FX019

SERIAL CLOCK INPUT

CONTROL DAT A INPUT
CHIP SELECT
CHANNEL 1 OUTPUT
CHANNEL 2 OUTPUT

CHANNEL 3 OUTPUT
CHANNEL 4 OUTPUT

CHANNEL 1 INPUT
CHANNEL 2 INPUT
CHANNEL 3 INPUT
CHANNEL 4 INPUT

LOAD/LATCH
LOAD/LATCH

Application Recommendations

(f) Analogue tracks should not run parallel to digital
tracks.

(g) A "Ground Plane" connected to V

SS

will assist in
eliminating external pick-up on the channel input and
output pins.

(h) Do not run high-level output tracks close to low­level input tracks.

(i) Input signal amplitudes should be applied with due
regard to Figure 3.

(a) A noisy or badly regulated power supply can
cause instability and/or variance of selected gains.

(b) Care should be taken on the design and layout of
the printed circuit board.

(c) All external components (Figure 2) should be
kept close to the FX019 package.

(d) Inputs and outputs should be screened wherever
possible.

(e) Tracks should be kept shor t.

To avoid excess noise and instability in the final installation it is recommended that the following points be noted.

Notes

(1) Channel Amplifiers 1 to 4 are inverting amplifiers.
(2) Analogue input capacitors C

1

to C4 are only required for a.c.

input signals, d.c. input signals do not require these components.

Component Value

C

1

to C

4

0.1µF

C

5

1.0µF

C

6

1.0µF

Tolerances: C = ± 20%

Fig.2 External Component Connections

4

Table 2 Gain Control Word Format

Bit 3 Bit2 Bit 1 Bit 0 Stage 1, 2, 3 Stage 4
MSB LSB (0.43dB) (2.0dB)

0000 OFF OFF
0001 -3.0 -14.0dB
0010 -2.571 -12.0
0011 -2.143 -10.0
0100 -1.714 -8.0
0101 -1.286 -6.0
0110 -0.857 -4.0
0111 -0.428 -2.0
1000 0 0
1001 0.428 2.0
1010 0.857 4.0
1011 1.286 6.0
1100 1.714 8.0
1101 2.143 10.0
1110 2.571 12.0
1111 3.0 14.0

t

LLW

Load/Latch Pulse Width

t

LLO

Load/Latch Over Time

t

DS

Data Set-up Time

t

DH

Data Hold Time

t

LLD

Load/Latch Delay

Timing

t

PWH

Serial Clock "High" Pulse Width

t

PWL

Serial Clock "Low" Pulse Width

The gain of each amplifier block (Channel 1 to
Channel 4) in the FX019 is set by a separate 8-bit
data word ( bit 7 to bit 0 ). This 8-bit word, consisting
of 4 Address bits (bit 7 to bit 4) and 4 Gain Control
bits (bit 3 to bit 0), is loaded to the Control Data Input
in serial format using the external data clock.

Data Loading

The 8-bit data word is loaded

bit 7 first and bit 0

last.
Bit 7 must be a logic “1” to address the chip.
If bit 7 in the word is a logic “0” that 8-bit word will not be
executed. The Chip Select input permits the use of two
devices in a system; To facilitate this, Bit 6 can be either
a logic “0” or “1.” Figure 4 (below) shows the timing
information required to load and operate this device.

Control Data and Timing

Fig.4 Serial Control Data Loading Diagram

Chip

1

Chip

2

Table 1 Address Word Format

Bit 7 Bit 6 Bit 5 Bit 4 Channel Chip Chip
MSB LSB Selected Select Number

1000 1 0
1001 2 0
1010 3 0
1011 4 0

1100 1 1
1101 2 1
1110 3 1
1111 4 1

Data is loaded to the FX019 on the rising edge of the
Serial Clock. Loaded data is executed on the falling
(rising) edge of the Load/Latch (Load/Latch) pulse.
Table 1 shows the format of each 4-bit Address word,
Table 2 shows the format of each Gain Control word
with Figure 4 describing the data loading operation and
timing.

SERIAL DATA CLOCK

t

PWL

t

PWH

t

DS

Loaded Last

Logic ’1’

Loaded

First

BIT 7

BIT 6

BIT 1

BIT 0

t

DH

SERIAL DATA IN

(ONE 8-BIT WORD)

t

LLO

8th
Clock
Pulse

Next
Clock
Pulse

t

LLD

t

LLW

LOAD/LATCH

LOAD/LATCH

5

Specification

Absolute Maximum Ratings

Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits
is not implied.
Supply voltage -0.3 to 7.0V
Input voltage at any pin (ref V

SS

= 0V) -0.3 to (V

DD

+ 0.3V)

Sink/source current (supply pins) +/- 30mA

(other pins) +/- 20mA

Total device dissipation @ T

AMB

25°C 800mW Max.

Derating 10mW/°C
Operating temperature range: FX019DW/P -40°C to +85°C (plastic)

Storage temperature range: FX019DW/P -40°C to +85°C (plastic)

Operating Limits

All device characteristics are measured under the following conditions unless otherwise specified:
V

DD

= 5.0V, T

AMB

= 25°C. Audio Level 0dB ref: = 775mVrms. Amplifier Gain Set = 0dB.

Characteristics See Note Min. Typ. Max. Unit

Static Values

Supply Voltage (V

DD

) 4.5 5.0 5.5 V

Supply Current - 1.5 - mA

Dynamic Values
Control Functions

Input Logic '1' 3.5 – – V
Input Logic '0' – – 1.5 V
Digital Input Impedances 0.5 1.0 – MΩ
Amplifier Stages (General)
Bandwidth (-3dB) 20.0 – – kHz
Output Impedance – 1.0 - kΩ
Total Harmonic Distortion 1 – 0.35 0.5 %
Output Noise Level (per stage) 2 – 180.0 400.0 µVrms
Onset of Clipping 3 – 1.73 – Vrms
Gain Variation 4 – – 0.1 dB
Interstage Isolation – 60.0 – dB
“Trimmer” Stages (Ch1 – Ch3)
Gain -3.0 +3.0 dB
Gain per Step (15 in No.) – 0.43 – dB
Step Error 5 – – ±0.2 dB
Input Impedance 100.0 – – kΩ
“Volume” Stage (Ch4)
Gain -14.0 +14.0 dB
Gain per Step (15 in No.) – 2.0 – dB
Step Error 5 – – ±0.4 dB
Input Impedance 50.0 – – kΩ

Timing (Figure 4)

Serial Clock "High" Pulse Width (t

PWH

) 250 – – ns

Serial Clock "Low" Pulse Width (t

PWL

) 250 – – ns

Data Set-up Time (t

DS

) 150 – – ns

Data Hold Time (t

DH

) 50.0 – – ns

Load/Latch Pulse Width (t

LLW

) 150 – – ns

Load/Latch Delay (t

LLD

) 200 – – ns

Load/Latch Over (t

LLO

) – – 50.0 n s

Serial Data Clock Frequency – – 2.0 MHz

Notes

1. Gain Set 0dB, Input Level 1kHz -3.0dB (549mVrms).

2. With an a.c short-circuit input, measured in a 30kHz bandwidth.

3. See Figure 3.

4. Over the temperature and supply voltage range.

5. With reference to a 1.0kHz signal.

6

Handling Precautions

The FX019 is a CMOS LSI circuit which includes input
protection. However precautions should be taken to
prevent static discharges which may cause damage.

CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied
and CML reserves the right at any time without notice to change the said circuitry.

Ordering Information

FX019DW 16-pin plastic S.O.I.C. (D4)
FX019P 16-pin plastic DIL (P3)

Package Outlines

The FX019 is available in the package styles outlined
below. Mechanical package diagrams and specifications
are detailed in Section 10 of this document.
Pin 1 identification marking is shown on the relevant
diagram and pins on all package styles number
anti-clockwise when viewed from the top.

NOT TO SCALE

Max. Body Length 19.24mm
Max. Body Width 6.41mm
Stand-Off 0.51mm

NOT TO SCALE

Max. Body Length 10.31mm
Max. Body Width 7.59mm
Stand-Off 0.20mm

FX019DW 16-pin plastic S.O.I.C. (D4) FX019P 16-pin plastic DIL (P3)