Page 1
FW801 PHY IEEE * 1394A
One-Cable Transceiver/Arbiter Device
Supports provisions of IEEE 1394-1995 Standard
Distinguishing Features
■
Compliant with IEEE P1394a Draft 2.0 Standard
for a High Performance Serial Bus (Supple-
ment)
Supports extended BIAS_HANDSHAKE time for
■
enhanced interoperability with camcorders
While unpowered and connected to the bus, will not
■
drive TPBIAS on a connected port even if receiving
incoming bias voltage on that port
Does not require external filter capacitors for PLL
■
Does not require a separate 5 V supply for 5 V link
■
controller interoperability
Interoperable across 1394 cable with 1394 physical
■
layers (PHY) using 5 V supplies
Interoperable with 1394 link-layer controllers using
■
5 V supplies
Device powerdown feature to conserve energy in
■
battery-powered applications
Interface to link-layer controller supports Annex J
■
electrical isolation as well as bus-keeper isolation
■
for a High Performance Serial Bus
Fully interoperable with FireWire† implementation
■
of IEEE 1394-1995
Reports cable power fail interrupt when voltage at
■
CPS pin falls below 7.5 V
Separate cable bias and driver termination voltage
■
supply for port
Other Features
48-pin TQFP package
■
Single 3.3 V supply operation
■
Data interface to link-layer controller provided
■
through 2/4/8 parallel lines at 50 Mbits/s
25 MHz crystal oscillator and PLL provide transmit/
■
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s and link-layer controller clock at
50 MHz
Multiple separate package signals provided for
■
analog and digital supplies and grounds
Data Sheet, Rev. 1
June 2001
Features
Provides one fully compliant cable port at
■
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s
Fully supports Open HCI requirements
■
Supports arbitrated short bus reset to improve
■
utilization of the bus
Supports ack-accelerated arbitration and fly-by
■
concatenation
Supports connection debounce
■
Supports multispeed packet concatenation
■
Supports PHY pinging and remote PHY access
■
packets
Fully supports suspend/resume
■
Supports PHY-link interface initialization and reset
■
Supports 1394a register set
■
Supports LPS/link-on as a part of PHY-link inter-
■
face
Description
The Agere Systems Inc. FW801 device provides the
analog physical layer functions needed to implement a one-port node in a cable-based IEEE 13941995 and IEEE P1394a network.
The cable port incorporates two differential line
transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection status, for initialization and
arbitration, and for packet reception and transmission. The PHY is designed to interface with a linklayer controller (LLC).
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
† FireWire is a registered trademark of Apple Computer, Inc.
Page 2
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Table of Contents
Contents Page
Distinguishing Features ............................................................................................................................................ 1
Features ................................................................................................................................................................... 1
Other Features ......................................................................................................................................................... 1
Description ................................................................................................................................................................ 1
Signal Information ..................................................................................................................................................... 6
Application Information ............................................................................................................................................. 9
1394 Application Support Contact Information ....................................................................................................... 10
Absolute Maximum Ratings .................................................................................................................................... 11
Electrical Characteristics ........................................................................................................................................12
Timing Characteristics ............................................................................................................................................ 15
Timing Waveforms .................................................................................................................................................. 16
Internal Register Configuration ............................................................................................................................... 17
Outline Diagrams .................................................................................................................................................... 22
List of Figures
Figure 1. Block Diagram .......................................................................................................................................... 5
Figure 2. Pin Assignments ....................................................................................................................................... 6
Figure 3. Typical External Component Connections ............................................................................................... 9
Figure 4. Typical Port Termination Network .......................................................................................................... 10
Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ............................................................ 16
Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms ...................................................................... 16
List of Tables
Table 1. Signal Descriptions ..................................................................................................................................... 6
Table 2. Absolute Maximum Ratings ...................................................................................................................... 11
Table 3. Analog Characteristics .............................................................................................................................. 12
Table 4. Driver Characteristics ............................................................................................................................... 13
Table 5. Device Characteristics ..............................................................................................................................14
Table 6. Switching Characteristics ......................................................................................................................... 15
Table 7. Clock Characteristics ................................................................................................................................15
Table 8. PHY Register Map for the Cable Environment ........................................................................................17
Table 9. PHY Register Fields for the Cable Environment ...................................................................................... 17
Table 10. PHY Register Page 0: Port Status Page ................................................................................................ 19
Table 11. PHY Register Port Status Page Fields ................................................................................................... 20
Table 12. PHY Register Page 1: Vendor Identification Page ...............................................................................21
Table 13. PHY Register Vendor Identification Page Fields .................................................................................... 21
22 Agere Systems Inc.
Page 3
Data Sheet, Rev. 1 FW801 PHY IEEE 1394A
June 2001 One-Cable Transceiver/Arbiter Device
Description
The PHY requires either an external 24.576 MHz
crystal or crystal oscillator. The internal oscillator
drives an internal phase-locked loop (PLL), which
generates the required 400 MHz reference signal. The
400 MHz reference signal is internally divided to
provide the 49.152 MHz, 98.304 MHz, and
196.608 MHz clock signals that control transmission of
the outbound encoded strobe and data information.
The 49.152 MHz clock signal is also supplied to the
associated LLC for synchronization of the two chips
and is used for resynchronization of the received data.
The powerdown function, when enabled by the PD
signal high, stops operation of the PLL and disables all
circuitry except the cable-not-active signal circuitry.
The PHY supports an isolation barrier between itself
and its LLC. When /ISO is tied high, the link interface
outputs behave normally. When /ISO is tied low,
internal differentiating logic is enabled, and the outputs
become short pulses, which can be coupled through a
capacitor or transformer as described in the
IEEE 1394-1995 Annex J. To operate with bus-keeper
isolation, the /ISO pin of the FW801 must be tied high.
Data bits to be transmitted through the cable ports are
received from the LLC on two, four, or eight data lines
(D[0:7]), and are latched internally in the PHY in
synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and
transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or
393.216 Mbits/s as the outbound data-strobe
information stream. During transmission, the encoded
data information is transmitted differentially on the TPA
and TPB cable pair(s).
During packet reception, the TPA and TPB
transmitters of the receiving cable port are disabled,
and the receivers for that port are enabled. The
encoded data information is received on the TPA and
TPB cable pair. The received data-strobe information
is decoded to recover the receive clock signal and the
serial data bits. The serial data bits are split into two,
four, or eight parallel streams, resynchronized to the
local system clock, and sent to the associated LLC.
The received data is also transmitted (repeated) out of
the other active (connected) cable ports.
Both the TPA and TPB cable interfaces incorporate
differential comparators to monitor the line states
during initialization and arbitration. The outputs of
these comparators are used by the internal logic to
determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage.
The value of this common-mode voltage is used during
arbitration to set the speed of the next packet
(continued)
transmission. In addition, the TPB channel monitors
the incoming cable common-mode voltage for the
presence of the remotely supplied twisted-pair bias
voltage. This monitor is called bias-detect.
The TPBIAS circuit monitors the value of incoming
TPA pair common-mode voltage when local TPBIAS is
inactive. Because this circuit has an internal current
source and the connected node has a current sink, the
monitored value indicates the cable connection status.
This monitor is called connect-detect.
Both the TPB bias-detect monitor and TPBIAS
connect-detect monitor are used in suspend/resume
signaling and cable connection detection.
The PHY provides a 1.86 V nominal bias voltage for
driver load termination. This bias voltage, when seen
through a cable by a remote receiver, indicates the
presence of an active connection. The value of this
bias voltage has been chosen to allow interoperability
between transceiver chips operating from 5 V or 3 V
nominal supplies. This bias voltage source should be
stabilized by using an external filter capacitor of
approximately 0.33 µF.
The transmitter circuitry, the receiver circuitry, and the
twisted-pair bias voltage circuity are all disabled with a
powerdown condition. The powerdown condition
occurs when the PD input is high. The port transmitter
circuitry and the receiver circuitry are also disabled
when the port is disabled, suspended, or
disconnected.
The line drivers in the PHY operate in a highimpedance current mode and are designed to work
with external 112 Ω line-termination resistor networks.
One network is provided at each end of each twistedpair cable. Each network is composed of a pair of
series-connected 56 Ω resistors. The midpoint of the
pair of resistors that is directly connected to the
twisted-pair A (TPA) signals is connected to the
TPBIAS voltage signal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B
(TPB) signals is coupled to ground through a parallel
RC network with recommended resistor and capacitor
values of 5 kΩ and 220 pF, respectively. The value of
the external resistors are specified to meet the draft
standard specifications when connected in parallel
with the internal receiver circuits.
The driver output current, along with other internal
operating currents, is set by an external resistor. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 kΩ ± 1%.
Agere Systems Inc. 3
Page 4
FW801 PHY IEEE 1394A Data Sheet, Rev. 1
One-Cable Transceiver/Arbiter Device June 2001
Description
The signal, C/LKON, as an input, indicates whether a
node is a contender for bus manager. When the
C/LKON signal is asserted, it means the node is a contender for bus manager. When the signal is not
asserted, it means that the node is not a contender.
The C bit corresponds to bit 20 in the self-ID packet
(see Table 4-29 of the IEEE 1394-1995 standard for
additional details).
The power-class bits of the self-ID packet do not have
a default value. These bits can be initialized and read/
written through the LLC using the PHY Register Map
Figure 6-1 of the IEEE P1394a Draft 2.0 standard. See
Table 8 for the address space of the Pwr_class
register.
A powerdown signal (PD) is provided to allow a powerdown mode where most of the PHY circuits are
powered down to conserve energy in battery-powered
applications. A cable status signal, CNA, provides a
high output when none of twisted-pair cable ports are
receiving incoming bias voltage. This output is not
debounced. The CNA output can be used to determine when to power the PHY down or up. In the
powerdown mode, all circuitry is disabled except the
CNA circuitry. It should be noted that when the device
is powered down, it does not act in a repeater mode.
When the power supply of the PHY is removed while
the twisted-pair cables are connected, the PHY transmitter and receiver circuitry has been designed to
present a high impedance to the cable in order to not
load the TPBIAS signal voltage on the other end of the
cable.
(continued)
For reliable operation, the TPBn signals must be terminated using the normal termination network regardless
of whether a cable is connected to a port or not connected to a port. When a port does not have a cable
connected, internal connect-detect circuitry will keep
the port in a disconnected state.
Note: All gap counts on all nodes of a 1394 bus must
be identical. This may be accomplished by using
PHY configuration packets (see Section 4.3.4.3
of IEEE 1394-1995 standard) or by using two
bus resets, which resets the gap counts to the
maximum level (3Fh).
The link power status (LPS) signal works with the
C/LKON signal to manage the LLC power usage of the
node. The LPS signal indicates that the LLC of the
node is powered up or powered down. If LPS is inactive for more than 1.2 µs and less than 25 µs, PHY/link
interface is reset. If LPS is inactive for greater than
25 µs, the PHY will disable the PHY/link interface to
save power. If the PHY then receives a link-on packet,
the C/LKON signal is activated to output a 6.114 MHz
signal, which can be used by the LLC to power itself
up. Once the LLC is powered up, the LPS signal communicates this to the PHY and the PHY/link interface
is enabled. C/LKON signal is turned off when both LPS
is active and Link_active bit (see Table 9) is set.
Two of the signals are used to set up various test conditions used in manufacturing. These signals, SE and
SM, should be connected to V
SS for normal operation.
4 Agere Systems Inc.
Page 5
Data Sheet, Rev. 1
June 2001
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Description
SYSCLK
LREQ
CTL0
CTL1
C/LKON
(continued)
CPS
LPS
/ISO
CNA
D0
D1
D2
D3
D4
D5
D6
D7
SE
SM
LINK
INTERFACE
I/O
RECEIVED
DATA
DECODER/
RETIMER
ARBITRATION
AND
CONTROL
STATE
MACHINE
LOGIC
BIAS
VOLTAGE
AND
CURRENT
GENERATOR
CABLE PORT 0
R0
R1
TPA0+
TPA0–
TPBIAS0
TPB0+
TPB0–
PD
/RESET
TRANSMIT
DATA
ENCODER
Figure 1. Block Diagram
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND
CLOCK
GENERATOR
XI
XO
5-5459.e (F)
Agere Systems Inc. 5
Page 6
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Signal Information
SYSCLK
VSSLREQ
46
47
CTL0
CTL1
D0
D1
V
D2
D3
D4
D5
D6
D7
V
DD
SS
48
1
2
3
4
5
6
7
8
9
10
11
12
13
PIN #1 IDENTIFIER
14
15
XI
XO
/RESET
43
44
45
AGERE FW801
16
17
18
Data Sheet, Rev. 1
June 2001
DD
SS
DD
R0
R1
V
VSSPLLV
PLLV
37
38
39
40
41
42
19
20
21
22
23
V
SSA
36
V
35
SSA
V
DDA
34
V
DDA
33
TPBIAS0
32
TPA0+
31
TPA0–
30
TPB0+
29
TPB0–
28
V
27
SSA
V
26
SSA
25
DDA
V
24
CNA
SS
DD
V
LPS
PD
V
C/LKON
SS
DD
SE
V
/ISO
CPS
SM
V
Note: Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Figure 2. Pin Assignments
Table 1. Signal Descriptions
Pin Signal* Type Name/Description
17 C/LKON I/O Bus Manager Capable Input and Link-On Output. On hardware reset, this pin is
used to set the default value of the contender status indicated during self-ID. The
bit value programming is done by tying the signal through a 10 kΩ resistor to V
(high, bus manager capable) or to GND (low, not bus manager capable). Using
either the pull-up or pull-down resistor allows the link-on output to override the input
value when necessary.
After hardware reset, this pin is set as an output, C/LKON indicates the reception of
a link-on message by asserting a 6.114 MHz signal.
13 CNA O Cable-Not-Active Output. CNA is asserted high when none of the PHY ports are
receiving an incoming bias voltage. This circuit remains active during the powerdown mode.
20 CPS I Cable Power Status. CPS is normally connected to the cable power through a
400 kΩ resistor. This circuit drives an internal comparator that detects the presence
of cable power. This information is maintained in one internal register and is available to the LLC by way of a register read (see IEEE P1394a Draft 2.0 Standard for
a High Performance Serial Bus (Supplement)).
* Active-low signals are indicated by “/ ” at the beginning of signal names, within this document.
5-7302.b (F)
DD
66 Agere Systems Inc.
Page 7
Data Sheet, Rev. 1
June 2001
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Signal Information
(continued)
Table 1. Signal Descriptions (continued)
Pin Signal* Type Name/Description
1 CTL0 I/O Control I/O. The CTLn signals are bidirectional communications control
signals between the PHY and the LLC. These signals control the passage
2CTL1
of information between the two devices. Bus-keeper circuitry is built into
these terminals.
3, 4, 6, 7,
8, 9, 10,
D[0:7] I/O Data I/O. The Dn signals are bidirectional and pass data between the
PHY and the LLC. Bus-keeper circuitry is built into these terminals.
11
19 /ISO I Link Interface Isolation Disable Input (Active-Low). /ISO controls the
operation of an internal pulse differentiating function used on the
PHY-LLC interface signals, CTLn and Dn, when they operate as outputs.
When /ISO is asserted low, the isolation barrier is implemented between
PHY and its LLC (as described in Annex J of IEEE 1394-1995).
/ISO is normally tied high to disable isolation differentiation. Bus-keepers
are enabled when /ISO is high (inactive) on CTL, D, and LREQ. When
/ISO is low (active), the bus-keepers are disabled. Please refer to Agere’s
application note AP98-074CMPR for more information on isolation.
14 LPS I Link Power Status. LPS is connected to either the V
DD supplying the
LLC or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2 µs and less than 25 µs, interface is reset. If LPS is inactive for
greater than 25 µs, the PHY will disable to save power. FW801 continues
its repeater function.
48 LREQ I Link Request. LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
18 PD I Powerdown. When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal.
41 PLLV
DD — Power for PLL Circuit. PLLVDD
supplies power to the PLL circuitry
portion of the device.
42 PLLV
SS — Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground
plane.
37 R0 I Current Setting Resistor. An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
38 R1
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 kΩ ± 1% should be used to meet the
IEEE 1394-1995 standard requirements for output voltage limits.
45 /RESET I Reset (Active-Low). When /RESET is asserted low (active), a bus reset
condition is set on the active cable ports and the internal logic is reset to
the reset start state. An internal pull-up resistor, which is connected to
V
DD
, is provided, so only an external delay capacitor in parallel with a
resistor is required to ensure that the capacitor is discharged when PHY
power is removed. This input is a standard logic buffer and can also be
driven by an open-drain logic output buffer.
23 SE I Test Mode Control. SE is used during the manufacturing test and should
be tied to V
SS.
24 SM I Test Mode Control. SM is used during the manufacturing test and should
be tied to V
* Active-low signals are indicated by “/ ” at the beginning of signal names, within this document.
SS.
Agere Systems Inc. 7
Page 8
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Signal Information
(continued)
Table 1. Signal Descriptions (continued)
Pin Signal* Type Name/Description
46 SYSCLK O System Clock. SYSCLK provides a 49.152 MHz clock signal, which is
synchronized with the data transfers to the LLC.
31 TPA0+ Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
30 TPA0− Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
29 TPB0+ Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-
pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
28 TPB0− Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-
pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
32 TPBIAS0 Analog I/O Portn, Twisted-Pair Bias. TPBIAS provides the 1.86 V nominal bias
voltage needed for proper operation of the twisted-pair cable drivers and
receivers and for sending a valid cable connection signal to the remote
nodes.
5, 16, 22,
V
DD
— Digital Power. VDD supplies power to the digital portion of the device.
39
25, 33, 34 V
DDA
— Analog Circuit Power. V
DDA
supplies power to the analog portion of the
device.
12, 15, 21,
40, 47
26, 27, 35,
36
V
V
SS
SSA
— Digital Ground. All VSS signals should be tied to the low-impedance
ground plane.
— Analog Circuit Ground. All V
SSA
signals should be tied together to a low-
impedance ground plane.
43 XI — Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant
fundamental mode crystal. Although, when a 24.576 MHz clock source is
used, it can be connected to XI with XO left unconnected. The optimum
44 XO
values for the external shunt capacitors are dependent on the specifications of the crystal used. The suggested values of 12 pF are appropriate
for crystal with 15 pF specified loads.
* Active-low signals are indicated by “/ ” at the beginning of signal names, within this document.
88 Agere Systems Inc.
Page 9
Data Sheet, Rev. 1
June 2001
Application Information
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
LLC
CTL0
CTL1
D0
D1
DD
V
D2
D3
D4
D5
D6
D7
V
SS
0.1 µF
1
2
3
4
5
6
7
8
9
10
11
12
12 pF
LLC
SS
LREQ
V
47
48
PIN #1 IDENTIFIER
13
14
LLC
SYSCLK
46
15
/RESET
45
16
12 pF
24.576 MHz
XO
XI
PLLVSSPLLVDD
43
44
42
AGERE FW801A
17
18
19
41
20
2.49 kΩ
VSS
VDD
R1
R0
37
38
39
40
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
VSSA
VSSA
VDDA
VDDA
TPBIAS0
TPA0+
TPA0–
TPB0+
TPB0–
SSA
V
VSSA
VDDA
PORT 0*
LPS
CNA
DD
OR V
LCC PULSE
* See Figure 4 for typical port termination network.
Figure 3. Typical External Component Connections
SS
V
VDD
PD
/ISO
SS
V
CPS
VDD
SE
SM
C/LKON
10 kΩ
LKON
BUS
MANAGER
400 kΩ
CABLE
POWER
5-6767.a (F)
Agere Systems Inc. 9
Page 10
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Application Information
36
35
34
33
32
31
30
29
28
27
26
V
SSA
VSSA
VDDA
VDDA
TPBIAS0
56 Ω 56 Ω
TPA0+
TPA0–
TPB0+
TPB0–
56 Ω 56 Ω
V
SSA
VSSA
(continued)
5 kΩ220 pF
0.33 µF
5
3
1
6
IEEE 1394-1995 STANDARD
CONNECTOR
4
2
25
V
DDA
CABLE
POWER
Figure 4. Typical Port Termination Network
1394 Application Support Contact Information
E-mail: 1394support@agere.com
VGVP
5-7654 (F)
1010 Agere Systems Inc.
Page 11
Data Sheet, Rev. 1
June 2001
One-Cable Transceiver/Arbiter Device
FW801 PHY IEEE 1394A
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Supply Voltage Range V
Input Voltage Range* V
Output Voltage Range at Any Output V
Operating Free Air Temperature T
Storage Temperature Range T
* Except for 5 V tolerant I/O (CTL0, CTL1, D0—D7, and LREQ) where VI max = 5.5 V.
DD 3.0 3.6 V
I
O
A
stg –65 150 °C
−0.5 V
−0.5 V
DD + 0.5 V
DD + 0.5 V
070°C
Agere Systems Inc. 11
Page 12
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Electrical Characteristics
Table 3. Analog Characteristics
Parameter Test Conditions Symbol Min Typ Max Unit
Supply Voltage Source power node V
Differential Input Voltage Cable inputs, 100 Mbits/s operation V
Cable inputs, 200 Mbits/s operation V
Cable inputs, 400 Mbits/s operation V
Cable inputs, during arbitration V
Common-mode Voltage
Source Power Mode
Common-mode Voltage
Nonsource Power Mode*
Receive Input Jitter TPA, TPB cable inputs,
Receive Input Skew Between TPA and TPB cable inputs,
Between TPA and TPB cable inputs,
Between TPA and TPB cable inputs,
Positive Arbitration
Comparator Input
Threshold Voltage
Negative Arbitration
Comparator Input
Threshold Voltage
Speed Signal Input
Threshold Voltage
Output Current TPBIAS outputs I
TPBIAS Output Voltage At rated I/O current V
Current Source for
Connect Detect Circuit
* For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard).
TPB cable inputs,
speed signaling off
TPB cable inputs,
S100 speed signaling on
TPB cable inputs,
S200 speed signaling on
TPB cable inputs,
S400 speed signaling on
TPB cable inputs,
speed signaling off
TPB cable inputs,
S100 speed signaling on
TPB cable inputs,
S200 speed signaling on
TPB cable inputs,
S400 speed signaling on
100 Mbits/s operation
TPA, TPB cable inputs,
200 Mbits/s operation
TPA, TPB cable inputs,
400 Mbits/s operation
100 Mbits/s operation
200 Mbits/s operation
400 Mbits/s operation
—V
—V
200 Mbits/s V
400 Mbits/s V
—I
CM—SP—100
V
CM—SP—200 0.935 — 2.515 V
V
CM—SP—400 0.532 — 2.515 V
V
CM—NSP—100 1.165 — 2.015 V
V
CM—NSP—200 0.935 — 2.015 V
V
CM—NSP—400 0.532 — 2.015 V
V
Data Sheet, Rev. 1
June 2001
DD—SP 3.0 3.3 3.6 V
ID—100
ID—200 132 — 260 mV
ID—400 100 — 260 mV
ID—ARB 168 — 265 mV
V
CM 1.165 — 2.515 V
VCM 1.165 — 2.015 V
———1.08ns
———0.5ns
— — — 0.315 ns
———0.8ns
———0.55ns
———0.5ns
TH
+89—168mV
TH
− –168 — –89 mV
TH—S200 45 — 139 mV
TH—S400 266 — 445 mV
O –5 — 2.5 mA
O
CD — — 76 µA
142 — 260 mV
1.165 — 2.515 V
1.665 — 2.015 V
1212 Agere Systems Inc.
Page 13
Data Sheet, Rev. 1
June 2001
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Electrical Characteristics
(continued)
Table 4. Driver Characteristics
Parameter Test Conditions Symbol Min Typ Max Unit
Differential Output Voltage 56 Ω load V
Off-state Common-mode Voltage Drivers disabled V
Driver Differential Current,
TPA+, TPA−, TPB+, TPB−
Common-mode Speed Signaling
Current, TPB+, TPB−
Driver enabled,
speed signaling off*
200 Mbits/s speed
signaling enabled
†
400 Mbits/s speed
signaling enabled
* Limits are defined as the algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− as the algebraic sum of driver
currents.
† Limits are defined as the absolute limit of each of TPB+ and TPB− driver currents.
†
OD 172 — 265 mV
OFF ——20mV
IDIFF
SP
I
ISP
−1.05 — 1.05 mA
−2.53 — −4.84 mA
−8.1 — −12.4 mA
Agere Systems Inc. 13
Page 14
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Electrical Characteristics
(continued)
Table 5. Device Characteristics
Parameter Test Conditions Symbol Min Typ Max Unit
Supply Current:
DD = 3.3 V
V
Port Active
High-level Output Voltage Electrical Character-
istics (continued)
I
OH max, VDD = min
Low-level Output Voltage I
OL min, VDD = max VOL ——0.4V
High-level Input Voltage CMOS inputs V
Low-level Input Voltage CMOS inputs V
Pull-up Current,
V
I = 0 V II 11 — 32 µA
/RESET Input
Powerup Reset Time,
V
I = 0 V — 2 — — ms
/RESET Input
Rising Input Threshold Voltage
—VI
/RESET Input
Output Current SYSCLK I
Control, data I
@ CMOS
CNA I
C/LKON I
Input Current,
V
I = VDD or 0 V II ——°±1 µA
LREQ, LPS, PD, SE, SM,
PC[0:2] Inputs
Off-state Output Current,
= V
V
or 0 V I
O
DD
CTL[0:1], D[0:7], C/LKON I/Os
Power Status Input Threshold
400 kΩ resistor V
Voltage, CPS Input
Rising Input Threshold Voltage*,
—V
LREQ, CTLn, Dn
Falling Input Threshold Voltage*,
—V
LREQ, CTLn, Dn
Bus Holding Current,
V
I
= 1/2(VDD) — 250 — 550 µA
LREQ, CTLn, Dn
Rising Input Threshold Voltage
—V
LPS
Falling Input Threshold Voltage
—V
LPS
* Device is capable of both differentiated and undifferentiated operation.
I
DD —135—mA
OH VDD – 0.4 — — V
V
IH 0.7VDD —— V
IL
RST
OL/IOH
— — 0.2V
1.1 — 1.4 V
–16 — 16 mA
DD
V
@ TTL
OL/IOH
OL/IOH
OL/IOH –2 — 2 mA
OZ
TH 7.5 — 8.5 V
IT+VDD/2 + 0.3 — VDD/2 + 0.8 V
IT
− V
LIH — — 0.24VDD + 1 V
LIL
–12 — 12 mA
–16 — 16 mA
——°±5 µA
DD
/2 – 0.8 — VDD/2 – 0.3 V
0.24VDD + 0.2 — — V
1414 Agere Systems Inc.
Page 15
Data Sheet, Rev. 1
June 2001
One-Cable Transceiver/Arbiter Device
FW801 PHY IEEE 1394A
Timing Characteristics
Table 6. Switching Characteristics
Symbol Parameter Measured Test Conditions Min Typ Max Unit
— Jitter, Transmit TPA, TPB — — — 0.15 ns
— Transmit Skew Between
TPA and TPB
r Rise Time, Transmit (TPA/TPB) 10% to 90% RI = 56 Ω,
t
t
f
Fall Time, Transmit (TPA/TPB) 90% to 10% RI = 56 Ω,
t
su Setup Time,
50% to 50% See Figure 5. 6 — — ns
Dn, CTLn, LREQ↑↓ to SYSCLK↑
t
h Hold Time,
50% to 50% See Figure 5. 0 — — ns
Dn, CTLn, LREQ↑↓ from SYSCLK↑
t
d Delay Time,
50% to 50% See Figure 6. 1 — 6 ns
SYSCLK↑ to Dn, CTLn↑↓
———±0.1 ns
——1.2ns
C
I = 10 pF
——1.2ns
C
I
= 10 pF
Table 7. Clock Characteristics
Parameter Symbol Min Typ Max Unit
External Clock Source Frequency f 24.5735 24.5760 24.5785 MHz
Agere Systems Inc. 15
Page 16
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Timing Waveforms
SYSCLK
Data Sheet, Rev. 1
June 2001
tsu
th
Dn, CTLn, LREQ
Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms
SYSCLK
td
Dn, CTLn
Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms
5-6017.a (F)
5-6018.a (F)
1616 Agere Systems Inc.
Page 17
Data Sheet, Rev. 1
June 2001
Internal Register Configuration
The PHY register map is shown below in Table 8.
Table 8. PHY Register Map for the Cable Environment
Address Contents
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
2 Physical_ID R PS
0000
0001
2 RHB IBR Gap_count
0010
2 Extended (7)
0011
2 Max_speed
0100
2 Link_active Contender Jitter Pwr_class
0101
2 Resume_int ISBR Loop Pwr_fail Timeout Port_event Enab_accel Enab_multi
0110
2
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
01112 Page_select
1000
2 Register 0 Page_select
XXXXX
XXXXX
XXXXX
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Tot al _p or ts
Delay
Port_select
11112 Register 7 Page_select
REQUIRED
The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values
not specified are resolved by the operation of the PHY state machines subsequent to a power reset.
Table 9. PHY Register Fields for the Cable Environment
Field Size Type Power Reset
Value
Physical_ID 6 r 000000 The address of this node determined during self-identification. A
R 1 r 0 When set to one, indicates that this node is the root.
PS 1 r — Cable power active.
RHB 1 rw 0 Root hold-off bit. When set to one, the force_root variable is TRUE,
IBR 1 rw 0 Initiate bus reset. When set to one, instructs the PHY to set ibr
Gap_count 6 rw 3F
Extended 3 r 7 This field has a constant value of seven, which indicates the
16 Used to configure the arbitration timer setting in order to optimize
XXXXX
value of 63 indicates a malconfigured bus; the link will not transmit
any packets.
which instructs the PHY to attempt to become the root during the
next tree identify process.
TRUE and reset_time to RESET_TIME. These values in turn
cause the PHY to initiate a bus reset without arbitration; the reset
signal is asserted for 166 µs. This bit is self-clearing.
gap times according to the topology of the bus. See Section 4.3.6
of IEEE Standard 1394-1995 for the encoding of this field.
extended PHY register map.
RESERVED
Description
Agere Systems Inc. 17
Page 18
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Internal Register Configuration
(continued)
Table 9. PHY Register Fields for the Cable Environment (continued)
Field Size Type Power Reset Value Description
Total_ports 4 r 1 The number of ports implemented by this PHY. This count
reflects the number.
Max_speed 3 r 010
2 Indicates the speed(s) this PHY supports:
000
2 = 98.304 Mbits/s
001
2 = 98.304 and 196.608 Mbits/s
010
2 = 98.304, 196.608, and 393.216 Mbits/s
011
2
= 98.304, 196.608, 393.216, and 786.43 Mbits/s
100
2
= 98.304, 196.608, 393.216, 786.432, and
1,572.864 Mbits/s
101
2
= 98.304, 196.608, 393.216, 786.432, 1,572.864, and
3,145.728 Mbits/s
All other values are reserved for future definition.
Delay 4 r 0000 Worst-case repeater delay, expressed as 144 + (delay * 20) ns.
Link_active 1 rw 1 Link Active. Cleared or set by software to control the value of
the L bit transmitted in the node’s self-ID packet 0, which will be
the logical AND of this bit and LPS active.
Contender 1 rw See description. Cleared or set by software to control the value of the C bit trans-
mitted in the self-ID packet. Powerup reset value is set by
C/LKON pin.
Jitter 3 r 000 The difference between the fastest and slowest repeater data
delay, expressed as (jitter + 1) * 20 ns.
Pwr_class 3 rw See description. Power-Class. Controls the value of the pwr field transmitted in
the self-ID packet. See Section 4.3.4.1 of IEEE Standard 13941995 for the encoding of this field. The power-class bits of the
self-ID packet do not have a default value.
Resume_int 1 rw 0 Resume Interrupt Enable. When set to one, the PHY will set
Port_event to one if resume operations commence for any port.
ISBR 1 rw 0 Initiate Short (Arbitrated) Bus Reset. A write of one to this bit
instructs the PHY to set ISBR true and reset_time to
SHORT_RESET_TIME. These values in turn cause the PHY to
arbitrate and issue a short bus reset. This bit is self-clearing.
Loop 1 rw 0 Loop Detect. A write of one to this bit clears it to zero.
Pwr_fail 1 rw 0 Cable Power Failure Detect. Set to one when the PS bit
changes from one to zero. A write of one to this bit clears it to
zero.
Timeout 1 rw 0 Arbitration State Machine Timeout. A write of one to this bit
clears it to zero (see MAX_ARB_STATE_TIME).
Port_event 1 rw 0 Port Event Detect. The PHY sets this bit to one if any of con-
nected, bias, disabled, or fault change for a port whose
Int_enable bit is one. The PHY also sets this bit to one if
resume operations commence for any port and Resume_int is
one. A write of one to this bit clears it to zero.
1818 Agere Systems Inc.
Page 19
Data Sheet, Rev. 1
June 2001
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Internal Register Configuration
Table 9. PHY Register Fields for the Cable Environment (continued)
Field Size Type Power Reset
Value
Enab_accel 1 rw 0 Enable Arbitration Acceleration. When set to one, the PHY will
Enab_multi 1 rw 0 Enable multispeed packet concatenation. When set to one, the link
Page_select 3 rw 000 Selects which of eight possible PHY register pages are accessible
Port_select 4 rw 000 If the page selected by Page_select presents per-port information,
The port status page is used to access configuration and status information for each of the PHY’s ports. The port is
selected by writing zero to Page_select and the desired port number to Port_select in the PHY register at address
0111
2. The format of the port status page is illustrated by Table 10 below; reserved fields are shown shaded. The
meanings of the register fields with the port status page are defined by Table 11.
(continued)
Description
use the enhancements specified in clause 7.10 of 1394a specification. PHY behavior is unspecified if the value of Enab_accel is
changed while a bus request is pending.
will signal the speed of all packets to the PHY.
through the window at PHY register addresses 1000
1111
2, inclusive.
this field selects which port’s registers are accessible through the
window at PHY register addresses 1000
Ports are numbered monotonically starting at zero, p0.
2
through 11112, inclusive.
2 through
Table 10. PHY Register Page 0: Port Status Page
Address Contents
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
1000
2
1001
2 Negotiated_speed Int_enable Fault
2
1010
1011
11002
11012
11102
1111
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
2
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
2
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
AStat BStat Child Connected Bias Disabled
REQUIRED
XXXXX
RESERVED
XXXXX XXXXX XXXXX
Agere Systems Inc. 19
Page 20
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Internal Register Configuration
The meaning of the register fields with the port status page are defined by Table 11 below.
Table 11. PHY Register Port Status Page Fields
Field Size Type Power Reset
AStat 2 r — TPA line state for the port:
BStat 2 r — TPB line state for the port (same encoding as AStat).
Child 1 r 0 If equal to one, the port is a child; otherwise, a parent. The
Connected 1 r 0 If equal to one, the port is connected.
Bias 1 r 0 If equal to one, incoming TPBIAS is detected.
Disabled 1 rw 0 If equal to one, the port is disabled.
Negotiated_speed 3 r 000 Indicates the maximum speed negotiated between this PHY
Int_enable 1 rw 0 Enable port event interrupts. When set to one, the PHY will
Fault 1 rw 0 Set to one if an error is detected during a suspend or resume
(continued)
Value
Description
00
2 = invalid
01
2 = 1
10
2 = 0
11
2 = Z
meaning of this bit is undefined from the time a bus reset is
detected until the PHY transitions to state T1: Child Handshake during the tree identify process (see Section 4.4.2.2 in
IEEE Standard 1394-1995).
port and its immediately connected port; the encoding is the
same as for they PHY register Max_speed field.
set Port_event to one if any of connected, bias, disabled, or
fault (for this port) change state.
operation. A write of one to this bit clears it to zero.
2020 Agere Systems Inc.
Page 21
Data Sheet, Rev. 1
June 2001
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Internal Register Configuration
(continued)
The vendor identification page is used to identify the PHY’s vendor and compliance level. The page is selected by
writing one to Page_select in the PHY register at address 0111
2
. The format of the vendor identification page is
shown in Table 12; reserved fields are shown shaded.
Table 12. PHY Register Page 1: Vendor Identification Page
Address Contents
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
1000
2 Compliance_level
1001
2
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
10102
10112 Vendor_ID
1100
2
11012
11102 Product_ID
1111
2
REQUIRED
XXXXX
RESERVED
The meaning of the register fields within the vendor identification page are defined by Table 13.
Table 13. PHY Register Vendor Identification Page Fields
Field Size Type Description
Compliance_level 8 r Standard to which the PHY implementation complies:
0 = not specified
1 = IEEE P1394a
Agere’s FW801 compliance level is 1.
All other values reserved for future standardization.
Vendor_ID 24 r The company ID or organizationally unique identifier (OUI) of the manufacturer
of the PHY. Agere’s vendor ID is 00601D
16. This number is obtained from the
IEEE registration authority committee (RAC). The most significant byte of
Vendor_ID appears at PHY register location 1010
1100
2.
2 and the least significant at
Product_ID 24 r The meaning of this number is determined by the company or organization that
16
has been granted Vendor_ID. Agere’s FW801 product ID is 081401
significant byte of Product_ID appears at PHY register location 1101
least significant at 1111
2
.
. The most
2
and the
The vendor-dependent page provides access to information used in manufacturing test of the FW801.
Agere Systems Inc. 21
Page 22
FW801 PHY IEEE 1394A
One-Cable Transceiver/Arbiter Device
Outline Diagrams
48-Pin TQFP
Dimensions are in millimeters.
9.00 ± 0.20
7.00 ± 0.20
PIN #1
IDENTIFIER ZONE
48
1
37
36
Data Sheet, Rev. 1
June 2001
1.00 REF
0.25
GAGE PLANE
SEATING PLANE
0.45/0.75
7.00
± 0.20
DETAIL A
9.00
± 0.20
12
13
24
25
0.106/0.200
0.19/0.27
DETAIL A
DETAIL B
1.40 ± 0.05
1.60 MAX
DETAIL B
0.08
M
SEATING PLANE
0.08
0.50 TYP
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@micro.lucent.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266
JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
0.05/0.15
5-2363 (F)
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
June 2001
DS99-300CMPR-1 (Replaces DS99-300CMPR)
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