Datasheet FSYE913A0R, FSYE913A0D Datasheet (Intersil Corporation)

FSYE913A0D, FSYE913A0R

Data Sheet February 2000 File Number 4744

Radiation Hardened, SEGR Resistant
P-Channel Power MOSFETs

The Discrete Products Operation of Intersil Corporation has
developed a series of Radiation Hardened MOSFETs
specifically designed for commercial and military space
applications. Enhanced Power MOSFET immunity to Single
Event Effects (SEE), Single Event Gate Rupture (SEGR) in
particular, is combined with 100K RADS of total dose
hardness to providedeviceswhichareideallysuitedtoharsh
space environments. The dose rate and neutron tolerance
necessary for military applications have not been sacrificed.

The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.

This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS)
structure. It is specially designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, motor drives,
relay drivers and drivers for high-power bipolar switching
transistors requiring high speed and low gate drive power.
This type can be operated directly from integrated circuits.

Reliability screening is available as either commercial, TXV
equivalent of MIL-S-19500, or Space equivalent of
MIL-S-19500. Contact Intersil Corporation for any desired
deviations from the data sheet.

Ordering Information

Features

• 9A, -100V, r

• Total Dose

- Meets Pre-RAD Specifications to 100K RAD (Si)

• Single Event

- Safe Operating Area Curve for Single Event Effects

- SEE Immunity for LET of 36MeV/mg/cm
V

up to 80% of Rated Breakdown and

DS

V

of 10V Off-Bias

GS

• Dose Rate

- Typically Survives 3E9 RAD (Si)/s at 80% BV

- Typically Survives 2E12 if Current Limited to I

• Photo Current

- 1.5nA Per-RAD(Si)/s Typically

• Neutron

- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm

- Usable to 3E14 Neutrons/cm

DS(ON)

= 0.280Ω

2

2

with

2

Symbol

D

G

S

Packaging

SMD.5

DSS

DM

RAD LEVEL SCREENING LEVEL PART NUMBER/BRAND

10K Commercial FSYE913A0D1
10K TXV FSYE913A0D3
100K Commercial FSYE913A0R1
100K TXV FSYE913A0R3
100K Space FSYE913A0R4

Formerly available as type TA17796.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 2000

FSYE913A0D, FSYE913A0R

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

FSYE913A0D, FSYE913A0R UNITS

Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DS

DGR

-100 V

-100 V

Continuous Drain Current

TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

D
D

DM

GS

9A
5A

27 A

±20 V

Maximum Power Dissipation

TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

T
T

42 W
17 W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33 W/oC

Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .I

Continuous Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

AS

S

SM

L

27 A

9A

27 A

-55 to 150
300

o

C

o

C

(Distance >0.063in (1.6mm) from Case, 10s Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

DSSID

GS(TH)VGS

= 1mA, VGS = 0V -100 - - V

= VDS,

ID = 1mA

TC = -55oC - - -7.0 V
TC = 25oC -2.0 - -6.0 V
TC = 125oC -1.0 - - V

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

DSS

GSS

VDS = -80V,
VGS = 0V

TC = 25oC--25µA
TC = 125oC - - 250 µA

VGS = ±20V TC = 25oC - - 100 nA

TC = 125oC 200 nA
Drain to Source On-State Voltage V
Drain to Source On Resistance r

Turn-On Delay Time t

DS(ON)VGS

DS(ON)12ID

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 12V Q
Threshold Gate Charge Q
Gate Charge Source Q
Gate Charge Drain Q
Plateau Voltage V

(PLATEAU)ID

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R

r

f

g(12)

g(TH)

gs

gd

ISS
OSS
RSS

JC

θ

= -12V, ID = 9A -3.02 V

= 5A,

VGS = -12V
VDD = -50V, ID = 9A,

RL = 5.6Ω, VGS = -12V,
RGS = 7.5Ω

TC = 25oC - 0.190 0.280 Ω
TC = 125oC - - 0.440 Ω

- - 20 ns

- - 40 ns

- - 40 ns

- - 35 ns

= 0V to -20V VDD = -50V,

VGS = 0V to -12V - 36 41 nC

ID = 9A

- - 61 nC

VGS = 0V to -2V - - 2.4 nC

- 6.6 7.8 nC

-1720nC

= 9A, VDS = -15V - -7 - V

VDS = -25V, VGS = 0V,
f = 1MHz

- 945 - pF

- 315 - pF

- 100 - pF

- - 3.0

o

C/W

2

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Forward Voltage V
Reverse Recovery Time t

SD

rr

FSYE913A0D, FSYE913A0R

ISD = 9A -0.6 - -1.8 V
ISD = 9A, dISD/dt = 100A/µs - - 170 ns

Electrical Specifications up to 100K RAD T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Drain to Source Breakdown Volts (Note 3) BV
Gate to Source Threshold Volts (Note 3) V
Gate to Body Leakage (Notes 2, 3) I
Zero Gate Leakage (Note 3) I
Drain to Source On-State Volts (Notes 1, 3) V
Drain to Source On Resistance (Notes 1, 3) r

DS(ON)12VGS

DSS

GS(TH)

GSS
DSS

DS(ON)VGS

VGS = 0, ID = 1mA -100 - V
VGS = VDS, ID = 1mA -2.0 -6.0 V
VGS = ±20V, VDS = 0V - 100 nA
VGS = 0, VDS = -80V - 25 µA

= -12V, ID = 9A - -3.02 V
= -12V, ID = 5A - 0.280 Ω

NOTES:

1. Pulse test, 300µs Max.

2. Absolute value.

3. Insitu Gamma bias must be sampled for both VGS = -12V, VDS = 0V and VGS = 0V, VDS = 80% BV

DSS

.

Single Event Effects (SEB, SEGR) Note 4

ENVIRONMENT (NOTE 5)

TEST SYMBOL

ION

SPECIES

TYPICAL LET

(MeV/mg/cm)

TYPICAL

RANGE (µ)

Single Event Effects Safe Operating Area SEESOA Ni 26 43 20 -100

Br 37 36 10 -100
Br 37 36 15 -80
Br 37 36 20 -50

NOTES:

4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.

5. Fluence = 1E5 ions/cm2 (typical), T = 25oC.

6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).

APPLIED

VGS BIAS

(V)

(NOTE 6)

MAXIMUM

VDSBIAS (V)

Typical Performance Curves Unless Otherwise Specified

LET = 26MeV/mg/cm2, RANGE = 43µ
LET = 37MeV/mg/cm2, RANGE = 36µ

V

(V)

GS

(V)

DS

V

-120
FLUENCE = 1E5 IONS/cm2 (TYPICAL)

-100

-80

-60

-40

-20
TEMP = 25oC

0

0101520255

FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIREDTO LIMIT

3

1E-3

1E-4

1E-5

1E-6

LIMITING INDUCTANCE (HENRY)

1E-7

-30
DRAIN SUPPLY (V)

GAMMA DOT CURRENT TO I

-300-100-10

AS

ILM = 10A

30A

100A

300A

-1000

FSYE913A0D, FSYE913A0R

Typical Performance Curves Unless Otherwise Specified (Continued)

12

100

10

TC = 25oC

8

6

, DRAIN (A)

D

I

4

2

0

TC, CASE TEMPERATURE (oC)

500-50

100

150

FIGURE 3. MAXIMUMCONTINUOUS DRAIN CURRENT vs

TEMPERATURE

-12V

V

G

Q

GS

Q

G

Q

GD

10

1

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

0.1

-1

DS(ON)

-10 -100

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

2.5
PULSE DURATION = 250ms, VGS = -12V, ID = 5A

2.0

DS(ON)

1.5

1.0

NORMALIZED r

0.5

100µs

1ms

10ms

-300

CHARGE

BASIC GATE CHARGE WAVEFORM

0.0

-80 -40 0 40 80 120 160

FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED r

10

)

1

θJC

NORMALIZED

0.01

THERMAL RESPONSE (Z

0.001

0.1

0.5

0.2

0.1

0.05

0.02

0.01

-5

10

SINGLE PULSE

-4

10

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

1/t2

JC

θ

10

FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE

, JUNCTION TEMPERATURE (oC)

T

J

vs JUNCTION TEMPERATURE

DS(ON)

P

DM

+ T

C

-1

t
t

0

10

1
2

1

10

4

FSYE913A0D, FSYE913A0R

Typical Performance Curves Unless Otherwise Specified (Continued)

40

STARTING TJ = 25oC

10

STARTING TJ = 150oC

IF R = 0

, AVALANCHE CURRENT (A)

tAV = (L) (IAS) / (1.3 RATED BV

AS

I

IF R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BV

1

0.01

0.1

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

DSS

110

FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING

Test Circuits and Waveforms

- VDD) + 1]

VARY t

TO OBTAIN

P

REQUIRED PEAK I

0V

t

P

VGS≤ 20V

CURRENT

TRANSFORMER

50Ω

AS

ELECTRONIC SWITCH OPENS

WHEN I

V

DS

L

+

I

AS

-

50Ω

DUT

IS REACHED

AS

+

V

DD

-

50V-150V

BV

DSS

t

P

I

AS

t

AV

FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS

t

t

d(ON)

90%

ON

t

r

V

DD

R

L

V

DS

V

DS

V

DS

t

d(OFF)

t

OFF

V

DD

t

f

90%

0V

V

GS

= -12V

DUT

R

GS

V

GS

10%

10%

10%

90%

50%50%

PULSE WIDTH

FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS

5

FSYE913A0D, FSYE913A0R

Screening Information

Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).

Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) T

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

Gate to Source Leakage Current I
Zero Gate Voltage Drain Current I
Drain to Source On Resistance r
Gate Threshold Voltage V

NOTES:

7. Or 100% of Initial Reading (whichever is greater).

8. Of Initial Reading.

DS(ON)

GS(TH)

GSS
DSS

VGS = ±20V ±20 (Note 7) nA
VDS = 80% Rated Value ±25 (Note 7) µA
TC = 125oC at Rated I
ID = 1.0mA ±20% (Note 8) V

Screening Information

TEST JANTXV EQUIVALENT JANS EQUIVALENT

Gate Stress VGS = -30V, t = 250µsV
Pind Optional Required
Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,

Subgroup 2 (All Static Tests at 25oC)

Steady State Gate
Bias (Gate Stress)

Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests

Steady State Reverse
Bias (Drain Stress)

PDA 10% 5%
Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A,

NOTE:

9. Test limits are identical pre and post burn-in.

MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours

and Limits Table
MIL-STD-750, Method 1042, Condition A

VDS = 80% of Rated Value,
TA = 150oC, Time = 160 hours

= 25oC, Unless Otherwise Specified

C

D

MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)

MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours

All Delta Parameters Listed in the Delta Tests
and Limits Table

MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours

Subgroups 2 and 3

±20% (Note 8) Ω

= -30V, t = 250µs

GS

Additional Screening Tests

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

Safe Operating Area SOA VDS = -80V, t = 10ms 1.2 A
Unclamped Inductive Switching I
Thermal Response ∆V
Thermal Impedance ∆V

6

AS

SD
SD

V

GS(PEAK)

tH = 10ms; VH = -25V; IH = 1A 74 mV
tH = 100ms; VH = -25V; IH = 1A 165 mV

= -15V, L = 0.1mH 27 A

FSYE913A0D, FSYE913A0R

Rad Hard Data Packages - Intersil Power Transistors

TXV Equivalent

1. RAD HARD TXV EQUIVALENT - STANDARD DATA
PACKAGE

A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
D. Group A - Attributes Data Sheet
E. Group B - Attributes Data Sheet
F. Group C - Attributes Data Sheet

G. Group D - Attributes Data Sheet

2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA
PACKAGE

A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet

- Precondition Lot Traveler

- Pre and Post Burn-In Read and Record
Data

D. Group A - Attributes Data Sheet

- Group A Lot Traveler

E. Group B - Attributes Data Sheet

- Group B Lot Traveler

- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup B3)

- Bond Strength Data (Subgroup B3)

- Pre and Post High Temperature Operating
Life Read and Record Data (SubgroupB6)

F. Group C - Attributes Data Sheet

- Group C Lot Traveler

- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup C6)

- Bond Strength Data (Subgroup C6)

G. Group D - Attributes Data Sheet

- Group D Lot Traveler

- Pre and Post RAD Read and Record Data

Class S - Equivalents

1. RAD HARD “S” EQUIVALENT - STANDARD DATA
PACKAGE

A. Certificate of Compliance

B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet

- Hi-Rel Lot Traveler

- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data

- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data

F. Group A - Attributes Data Sheet

G. Group B - Attributes Data Sheet

H. Group C - Attributes Data Sheet

I. Group D - Attributes Data Sheet

2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL
DATA PACKAGE

A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet

- Hi-Rel Lot Traveler

- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data

- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data

- X-Ray and X-Ray Report

F. Group A - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Subgroups A2, A3, A4, A5 and A7 Data

G. Group B - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Subgroups B1, B3, B4, B5 and B6 Data

H. Group C - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Subgroups C1, C2, C3 and C6 Data

I. Group D - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Pre and Post Radiation Data

7

SMD.5

3 PAD CERAMIC LEADLESS CHIP CARRIER

FSYE913A0D, FSYE913A0R

E

SYMBOL

NOTESMIN MAX MIN MAX

A 0.108 0.118 2.74 2.99 -

b 0.090 0.100 2.28 2.54 -

D 0.291 0.301 7.39 7.64 -

INCHES MILLIMETERS

D

D

1

D

2

0.281 0.291 7.13 7.39 -

0.070 0.080 1.78 2.03 -

E 0.395 0.405 10.03 10.28 -

E

1

E

2

0.220 0.230 5.58 5.84 -

0.120 0.130 3.04 3.30 -

NOTES:

1. No current JEDEC outline for this package.

A

2. Controlling dimension: Inch.

3. Revision 2 dated 11-99.

E

1

D

1

3

E

2

2

D

2

1

1 - GATE
2 - SOURCE
3 - DRAIN

b

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
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TEL: [phone]
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ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

8

FSYE913A0D, FSYE913A0R

9