Datasheet FSL117MRIN Datasheet (Fairchild)

FSL117MRIN Green-Mode Fairchild Power Switch (FPS™)

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

June 2012

Features

 Advanced Soft Burst Mode for

Low Standby Power and Low Audible Noise

 Random Frequency Fluctuation (RFF) for Low EMI  Pulse-by-Pulse Current Limit  Overload Protection (OLP), Over-Voltage Protection

(OVP), Abnormal Over-Current Protection (AOCP), Internal Thermal Shutdown (TSD) with Hysteresis, Output-Short Protection (OSP), Line Over-Voltage Protection (LOVP), and Under-Voltage Lockout (UVLO) with Hysteresis

 Low Operating Current (0.4mA) in Burst Mode  Internal Startup Circuit  Internal Avalanche-Rugged 700V SenseFET  Built-in Soft-Start: 15ms  Auto-Restart Mode

Applications

Power Supply for Home Appliances, LCD Monitors,



STBs, and DVD Players

Description

The FSL117MRIN is an integrated Pulse Width Modulation (PWM) controller and 700V SenseFET specifically designed for offline Switched-Mode Power Supplies (SMPS) with minimal external components. The PWM controller includes an integrated fixedfrequency oscillator, Line Over-Voltage Protection (LOVP), Under-Voltage Lockout (UVLO), Leading-Edge Blanking (LEB), optimized gate driver, internal soft-start, temperature-compensated precise current sources for loop compensation, and self-protection circuitry. Compared with a discrete MOSFET and PWM controller solution, the FSL117MRIN can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. This device provides a basic platform for cost-effective design of a flyback converter.

Ordering Information

Output Power Table

Operating

Part Number Package

FSL117MRIN 8-DIP -40°C ~ +125°C 0.8A 11 10W 15W 6W 10W

Notes:

1. Pb-free package per JEDEC J-STD-020B.

2. The junction temperature can limit the maximum output power.

3. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.

4. Maximum practical continuous power in an open-frame design at 50C ambient temperature.

(1)

Junction

Temperature

Current

Limit

(Typ.)

R

DS(ON)

(Max.)

230VAC ±15% 85~265VAC

Open

Adapter

(3)

Frame

(4)

Adapter

(2)

Open

(3)

Frame

(4)

Application Circuit

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Internal Block Diagram

Figure 1. Typical Application Circuit

Figure 2. Internal Block Diagram

Pin Configuration

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Figure 3. Pin Assignments (Top View)

Pin Definitions

Pin # Name Description

1 GND

2 V

3 FB

4 V

5 V

6

7

Drain

8

Ground. This pin is the control ground and the SenseFET source. Power Supply. This pin is the positive supply input, which provides the internal operating

CC

current for both startup and steady-state operation.

Feedback. This pin is internally connected to the inverting input of the PWM comparator.

The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 7V, the overload protection triggers, which shuts down the FPS.

Line Over-Voltage Input. This pin is the input pin of line voltage. The voltage, which is

divided by resistors, is input of this pin. If this pin voltage higher than V

IN

triggers, which shuts down the FPS Do not leave this pin floating. If LOVP is not used, this pin should be connected directly to the GND.

Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link.

At startup, the internal high-voltage current source supplies internal bias and charges the

STR

external capacitor connected to the V source (I

SenseFET Drain. High-voltage power SenseFET drain connection.

) is disabled.

CH

pin. Once VCC reaches 12V, the internal current

CC

voltage, the LOVP

INH

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V

STR

V

Drain Pin Voltage 700 V

DS

V

CC

V

Feedback Pin Voltage -0.3 10.0 V

FB

VIN VIN Pin Voltage -0.3 10.0 V

I

Drain Current Pulsed

DM

EAS Single Pulsed Avalanche Energy

PD

T

J

T

Storage Temperature -55 +150

STG

ESD

Notes:

5. Non-repetitive rating: pulse width is limited by maximum junction temperature.

6. L=51mH, starting TJ=25C.

7. Infinite cooling condition (refer to the SEMI G30-88).

8. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics.

Pin Voltage 700 V

STR

Pin Voltage 26 V

CC

(5)

4 A

(6)

50 mJ

Total Power Dissipation (T

=25C)

C

(7)

1.5 W

Maximum Junction Temperature +150

Operating Junction Temperature

Electrostatic Discharge Capability

Human Body Model, JESD22-A114 5

Charged Device Model, JESD22-C101 2

(8)

-40

+125

C

kV

Thermal Impedance

TA=25°C unless otherwise specified. All items are tested with the standards JESD 51-2 and 51-10.

Symbol Parameter Value Unit

JA Junction-to-Ambient Thermal Impedance

JC Junction-to-Case Thermal Impedance

Notes:

9. Free standing without heat sink; without copper clad. (Measurement condition: Just before junction temperature TJ enter into OTP.)

10. Measured on the DRAIN pin close to plastic interface.

(9)

80 °C/W

(10)

20 °C/W

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Electrical Characteristics

TJ = 25C unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Unit

SenseFET Section

BV

Drain-Source Breakdown Voltage VCC=0V, ID=200µA 700 V

DSS

I

Zero-Gate-Voltage Drain Current

DSS

R

Drain-Source On-State Resistance VGS=10V, ID=0.5A 8.8 11.0 

DS(ON)

C

Input Capacitance

ISS

C

Output Capacitance

OSS

t

Rise Time V

r

t

Fall Time V

f

t

Turn-On Delay V

d(on)

t

Turn-Off Delay V

d(off)

(11)

V

(11)

V

=560V, TA=125C

DS

=25V, VGS=0V, f=1MHz 250 pF

DS

=25V, V

DS

=350V, I

DS

=350V, I

DS

=350V, I

DS

=350V, I

DS

=0V, f=1MHz 25 pF

GS

=1.0A 4 ns

D

=1.0A 10 ns

D

=1.0A 12 ns

D

=1.0A 30 ns

D

200 µA

Control Section

f

Switching Frequency

S

f

D

MAX

D

MIN

Switching Frequency Variation

S

Maximum Duty Ratio V

Minimum Duty Ratio V

(11)

V

(11)

=14V, V

CC

=4V 61 67 73 kHz

FB

-25C < TJ < 125C ±5 ±10 %

=14V, V

CC

=14V, VFB=0V 0 %

CC

=4V 61 67 73 %

FB

IFB Feedback Source Current VFB=0V 65 90 115 µA

V

START

V

STOP

t

V

RECOMM

S/S

UVLO Threshold Voltage

After Turn-on, V

Internal Soft-Start Time V

Recommended VCC Range 13 23 V

V

FB

STR

=0V, V

=40V, V

Sweep 11 12 13 V

CC

=0V 7.0 7.5 8.0 V

FB

Sweep 15 ms

CC

Burst Mode Section

V

BURH

V

BURL

V

Hys

Burst-Mode Voltage VCC=14V, VFB Sweep

0.30 0.35 0.40 V

150 mV

0.45 0.50 0.55 V

Protection Section

I

Peak Drain Current Limit

LIM

V

Shutdown Feedback Voltage V

SD

I

Shutdown Delay Current V

DELAY

t

Leading-Edge Blanking Time

LEB

V

Over-Voltage Protection VCC Sweep 23.0 24.5 26.0 V

OVP

V

INH

V

INHYS

t

OSP

V

OSP

t

OSP_FB

TSD

T

Hys

Line Over-Voltage Protection Threshold Voltage

Line Over-Voltage Protection Hysteresis

Output-Short

Threshold VFB 1.8 2.0 2.2 V

Protection

V

Thermal Shutdown Temperature

Hysteresis 60

Threshold Time

(11)

FB

Blanking Time 2.0 2.5 3.0 µs

(11,12)

di/dt=170mA/s

=14V, V

CC

=14V, V

CC

Sweep 6.45 7.00 7.55 V

FB

=4V 1.2 2.0 2.8 µA

FB

300 ns

VCC=14V, V

Sweep 1.87 1.95 2.03 V

IN

Sweep 0.06 V

IN

OSP Triggered when t (Lasts Longer than t

Shutdown Temperature 125 135 145

(11)

ON<tOSP

& VFB>V

OSP

OSP_FB

0.70 0.80 0.90 A

0.7 1.0 1.3 µs

)

C

Continued on the following page…

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Electrical Characteristics (Continued)

TJ = 25C unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Unit

Total Device Section

I

OP

I

OPS

I

START

I

CH

V

STR

Operating Supply Current, (Control Part in Burst Mode)

Operating Switching Current, (Control Part and SenseFET Part)

Start Current

Startup Charging Current V

Minimum V

Supply Voltage VCC=VFB=0V, V

STR

Notes:

11. Although these parameters are guaranteed, they are not 100% tested in production.

12. t

includes gate turn-on time.

LEB

V

=14V, VFB=0V 0.3 0.4 0.5 mA

CC

VCC=14V, VFB=2V 0.8 1.2 1.6 mA

VCC=11V (Before VCC Reaches V

=0V, V

CC=VFB

)

START

=40V 0.7 1.0 1.3 mA

STR

Sweep 26 V

STR

85 120 155

A

A

Typical Performance Characteristics

Characteristic graphs are normalized at TA=25°C.

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 4. Operating Supply Current (IOP) vs. T

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐ 25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 5. Operating Switching Current (I

.

1.40

1.30

1.20

1.10

1.00

0.90

Normalized

0.80

0.70

0.60 ‐40'C ‐ 25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

OPS

) vs. T

.

Figure 6. Startup Charging Current (ICH) vs. T

1.40

1.30

1.20

1.10

1.00

0.90

Normalized

0.80

0.70

0.60 ‐40'C ‐ 25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

.

Temperature [ °C]

Figure 8. Feedback Source Current (IFB) vs. T

Figure 9. Shutdown Delay Current (I

.

Figure 7. Peak Drain Current Limit (I

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75 'C 90'C 110'C 120'C 125'C

LIM

Temperature [ °C]

DELAY

) vs. T

.

V

A

V

A

f

A

Typical Performance Characteristics

Characteristic graphs are normalized at TA=25°C.

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75'C 9 0'C 110'C 120'C 125'C

Temperature [ °C]

Figure 10. UVLO Threshold Voltage (

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐ 25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

START

) vs. T

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75'C 9 0'C 110'C 120'C 125'C

Temperature [ °C]

Figure 11. UVLO Threshold Voltage (

.

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75 'C 90'C 110'C 120'C 125'C

Temperature [ °C]

STOP

) vs. T

.

Figure 12. Shutdown Feedback Voltage (VSD) vs. T

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75 'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 14. Switching Frequency (

) vs. T

S

.

Figure 13. Over-Voltage Protection (V

.

1.20

1.15

1.10

1.05

1.00

0.95

Normalized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

Figure 15. Maximum Duty Ratio (D

MAX

OVP

) vs. T

.

V

Typical Performance Characteristics

Characteristic graphs are normalized at TA=25°C.



1.20

1.15

1.10

1.05

1.00

0.95

Norm alized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

1.20

1.15

1.10

1.05

1.00

0.95

Norm alized

0.90

0.85

0.80 ‐40'C ‐25'C 0'C 25'C 50'C 75'C 90'C 110'C 120'C 125'C

Temperature [ °C]

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Figure 16. Line OVP (V

INH

) vs. T

A

Figure 17. Hysteresis of LOVP (

INHYS

) vs. T

A.

Functional Description

1. Startup: At startup, an internal high-voltage current

source supplies the internal bias and charges the external capacitor (C illustrated in Figure 18. When V FSL117MRIN begins switching and the internal highvoltage current source is disabled. Normal switching operation continues and the power is supplied from the auxiliary transformer winding unless VCC goes below the stop voltage of 7.5V.

Figure 18. Startup Block

2. Soft-Start: The internal soft-start circuit increases the

PWM comparator inverting input voltage, together with the SenseFET current, slowly after startup. The typical soft-start time is 15ms. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased to smoothly establish the required output voltage. This helps prevent transformer saturation and reduces stress on the secondary diode during startup.

) connected to the VCC pin, as

Vcc

reaches 12V, the

CC

3. Feedback Control: This device employs current-

mode control, as shown in Figure 19. An opto-coupler (such as the FOD817) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the R

resistor makes it possible to

SENSE

control the switching duty cycle. When the reference pin voltage of the shunt regulator exceeds the internal reference voltage of 2.5V, the opto-coupler LED current increases, pulling down the feedback voltage and reducing drain current. This typically occurs when the input voltage is increased or the output load is decreased.

3.1 Pulse-by-Pulse Current Limit: Because current-

mode control is employed, the peak current through the SenseFET is limited by the inverting input of the PWM comparator (V

*), as shown in Figure 19.

FB

Assuming that the 90A current source flows only through the internal resistor (3R + R = 27k), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (VFB) exceeds

2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage. Therefore, the peak value of the current through the SenseFET is limited.

3.2 Leading-Edge Blanking (LEB): At the instant the

internal SenseFET is turned on, a high-current spike usually occurs through the SenseFET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the R

SENSE

resistor leads to incorrect feedback operation in the current-mode PWM control. To counter this effect, the FSL117MRIN employs a leading-edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for t

(300ns) after the SenseFET is turned on.

LEB

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Figure 19. Pulse Width Modulation Circuit

4. Protection Circuits: The FSL117MRIN has several

self-protective functions, such as Overload Protection (OLP), Abnormal Over-Current Protection (AOCP), Output-Short Protection (OSP), Over-Voltage Protection (OVP), and Thermal Shutdown (TSD). All the protections are implemented as auto-restart. Once a fault condition is detected, switching is terminated and the SenseFET remains off. This causes VCC to fall. When V

B

B falls to the Under-Voltage Lockout (UVLO)

CC

stop voltage of 7.5V, the protection is reset and the startup circuit charges the VCC capacitor. When VCC reaches the start voltage of 12.0V, the FSL117MRIN resumes normal operation. If the fault condition is not removed, the SenseFET remains off and V

drops to

CC

stop voltage again. In this manner, the auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. Because these protection circuits are fully integrated into the IC without external components, the reliability is improved without increasing cost.

blocked and the 2.0µA current source starts to charge CFB slowly up. In this condition, VFB continues increasing until it reaches 7.0V, when the switching operation is terminated, as shown in Figure 21. The delay for shutdown is the time required to charge C

FB

from 2.5V to 7.0V with 2.0µA. A 25 ~ 50ms delay is

typical for most applications. This protection is implemented as Auto-Restart Mode.

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Figure 20. Auto-Restart Protection Waveforms

4.1 Overload Protection (OLP): Overload is defined

as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger to protect the SMPS. However, even when the SMPS is in normal operation, the overload protection circuit can be triggered during load transition. To avoid this undesired operation, the overload protection circuit is designed to trigger only after a specified time to determine whether it is a transient situation or a true overload situation. Because of the pulse-by-pulse current-limit capability, the maximum peak current through the SenseFET is limited and, therefore, the maximum input power is restricted with a given input voltage. If the output consumes more than this maximum power, the output voltage (V

) decreases

OUT

below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (VFB). If VFB exceeds 2.5V, D1 is

Figure 21. Overload Protection

4.2 Abnormal Over-Current Protection (AOCP):

When the secondary rectifier diodes or the transformer pins are shorted, a steep current with extremely high di/dt can flow through the SenseFET during the minimum turn-on time. Overload protection is not enough to protect the FSL117MRIN in that abnormal case; since severe current stress is imposed on the SenseFET until OLP is triggered. The internal AOCP circuit is shown in Figure 22. When the gate turn-on signal is applied to the power SenseFET, the AOCP block is enabled and monitors the current through the sensing-resistor. The voltage across the resistor is compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, the set signal is applied to the S-R latch, resulting in the shutdown of the SMPS.

Figure 22. Abnormal Over-Current Protection

4.3. Output-Short Protection (OSP): If the output is

shorted, steep current with extremely high di/dt can flow through the SenseFET during the minimum turnon time. Such a steep current creates high-voltage stress on the drain of the SenseFET when turned off. To protect the device from this abnormal condition, OSP is included. It is comprised of detecting V SenseFET turn-on time. When the V

is higher than

FB

2.0V and the SenseFET turn-on time is lower than

1.0s, the FSL117MRIN recognizes this condition as an abnormal error and shuts down PWM switching until VCC reaches V

again. An abnormal condition

START

output short is shown in Figure 23.

and

4.6 Line Over-Voltage Protection (LOVP): If the line

input voltage is increased until unwanted level, high line input voltage brings high-voltage stress on the entire system. To protect from this abnormal condition, LOVP is included. It is comprised of detecting V

using divided resistors. When VIN is

IN

higher than 1.95V, this condition is recognized as an abnormal error and PWM switching shuts down until

decreases to around 1.89V (60mV hysteresis).

V

IN

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Figure 23. Output-Short Protection

4.4 Over-Voltage Protection (OVP): If the

secondary-side feedback circuit malfunctions or a solder defect causes an opening in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then VFB climbs up in a similar manner to the overload situation, forcing the preset maximum current to be supplied to the SMPS until the overload protection is triggered. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the overload protection is triggered, resulting in the breakdown of the devices in the secondary side. To prevent this situation, an OVP circuit is employed. In general, the V and the FSL117MRIN uses V monitoring the output voltage. If V an OVP circuit is triggered, resulting in the termination of the switching operation. To avoid undesired activation of OVP during normal operation, V be designed to be below 24.5V.

4.5 Thermal Shutdown (TSD): The SenseFET and

the control IC on a die in one package makes it easier for the control IC to detect the temperature of the SenseFET. If the temperature exceeds ~140C, the thermal shutdown is triggered and stops operation. The FSL117MRIN operates in auto-restart mode until the temperature decreases to around 75C, when normal operation resumes.

is proportional to the output voltage

CC

instead of directly

CC

exceeds 24.5V,

CC

should

CC

Figure 24. Line Over-Voltage Protection

5. Soft Burst Mode: To minimize power dissipation in

Standby Mode, the FSL117MRIN enters Burst Mode. As the load decreases, the feedback voltage decreases. The device automatically enters Burst Mode when the feedback voltage drops below V

BURL

(300mV), as shown in Figure 25. At this point, switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes V

(450mV), switching resumes. Feedback voltage

BURH

then falls and the process repeats. Burst Mode alternately enables and disables switching of the SenseFET, reducing switching loss in Standby Mode.

Figure 25. Burst-Mode Operation

6. Random Frequency Fluctuation (RFF):

Fluctuating switching frequency of an SMPS can reduce EMI by spreading the energy over a wide frequency range. The amount of EMI reduction is directly related to the switching frequency variation, which is limited internally. The switching frequency is determined randomly by external feedback voltage and an internal free-running oscillator at every switching instant. This random frequency fluctuation scatters the EMI noise around typical switching frequency (67kHz) effectively and can reduce the cost of the input filter included to meet the EMI requirements (e.g. EN55022).

Figure 26. Random Frequency Fluctuation

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

Physical Dimensions

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)

9.83

9.00

6.67

6.096

8.255

7.61

3.60

3.00

3.683

3.20

0.356

0.20

5.08 MAX

0.33 MIN

(0.56)

2.54

0.56

0.355

1.65

1.27

7.62

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANC

ES PER

ASME Y14.5M-1994

E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.

7.62

9.957

7.87

Figure 27. 8-Lead, Dual Inline Package, 8DIP.

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

FSL117MRIN — Green-Mode Fairchild Power Switch (FPS™)