Datasheet FSL110R, FSL110D Datasheet (Intersil Corporation)

FSL110D, FSL110R

Data Sheet October 1998 File Number 4224.3

3.5A, 100V, 0.600 Ohm, Rad Hard, SEGR
Resistant, N-Channel Power MOSFETs

The Discrete Products Operation of Intersil has developeda
series of Radiation Hardened MOSFETs specifically
designed for commercial and military space applications.
Enhanced Power MOSFET immunity toSingleEvent Effects
(SEE), Single Event Gate Rupture (SEGR) in particular, is
combined with 100K RADS of total dose hardness to provide
devices which are ideally suited to harsh space
environments. The dose rate and neutron tolerance
necessary for military applications have not been sacrificed.

The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.

This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS)
structure. It is specially designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, motor drives,
relay drivers and drivers for high-power bipolar switching
transistors requiring high speed and low gate drive power.
This type can be operated directly from integrated circuits.

Reliability screening is available as either commercial, TXV
equivalent of MIL-S-19500, or Space equivalent of
MIL-S-19500. Contact Intersil for any desired deviations
from the data sheet.

Features

• 3.5A, 100V, r

• Total Dose

- Meets Pre-RAD Specifications to 100K RAD (Si)

• Single Event

- Safe Operating Area Curve for Single Event Effects

- SEE Immunity for LET of 36MeV/mg/cm
V

up to 80% of Rated Breakdown and

DS

V

of 10V Off-Bias

GS

• Dose Rate

- Typically Survives 3E9 RAD (Si)/s at 80% BV

- Typically Survives 2E12 if Current Limited to I

• Photo Current

- 0.3nA Per-RAD(Si)/s Typically

• Neutron

- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm

- Usable to 3E14 Neutrons/cm

DS(ON)

= 0.600Ω

2

2

with

2

Symbol

D

G

S

DSS

DM

Ordering Information

RAD LEVEL SCREENING LEVEL PART NUMBER/BRAND

10K Commercial FSL110D1
10K TXV FSL110D3
100K Commercial FSL110R1
100K TXV FSL110R3
100K Space FSL110R4

Formerly available as type TA17616.

4-1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Package

TO-205AF

http://www.intersil.com or 407-727-9207

DGS

| Copyright © Intersil Corporation 1999

FSL110D, FSL110R

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

FSL110D, FSL110R UNITS

Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

DS

DGR

100 V
100 V

Continuous Drain Current

TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

D
D

DM

GS

3.5 A

2.5 A

10.5 A
±20 V

Maximum Power Dissipation

TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

T
T

15 W

6W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.12 W/oC

Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .I

Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

AS

S

SM

L

10.5 A

3.5 A

10.5 A

-55 to 150
300

o

C

o

C

(Distance >0.063in (1.6mm) from Case, 10s Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate Threshold Voltage V

DSSID

GS(TH)VGS

= 1mA, VGS = 0V 100 - - V

= VDS,

ID = 1mA

TC = -55oC - - 5.0 V
TC = 25oC 1.5 - 4.0 V
TC = 125oC 0.5 - - V

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

DSS

GSS

VDS = 80V,
VGS = 0V

TC = 25oC--25µA
TC = 125oC - - 250 µA

VGS = ±20V TC = 25oC - - 100 nA

TC = 125oC - 200 nA
Drain to Source On-State Voltage V
Drain to Source On Resistance r

Turn-On Delay Time t

DS(ON)VGS

DS(ON)12ID

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge Q

g(TOT)VGS

Gate Charge at 12V Q
Threshold Gate Charge Q
Gate Charge Source Q
Gate Charge Drain Q
Plateau Voltage V

(PLATEAU)ID

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

r

f

g(12)

g(TH)

gs

gd

ISS
OSS
RSS

JC

θ

JA

θ

= 12V, ID = 3.5A - 2.21 V

= 2.5A,

VGS = 12V
VDD = 50V, ID = 3.5A,

RL = 14.3Ω, VGS 12V,
RGS = 7.5Ω

TC = 25oC - 0.520 0.600 Ω
TC = 125oC - - 0.960 Ω

- - 30 ns

- - 60 ns

- - 30 ns

- - 55 ns

= 0V to 20V VDD = 50V,

VGS = 0V to 12V - 7.6 8.5 nC

ID = 3.5A

- - 15 nC

VGS = 0V to 2V - - 0.62 nC

- 2.2 2.8 nC

- 4.3 4.9 nC

= 3.5A, VDS = 15V - 8 - V

VDS = 25V, VGS = 0V,
f = 1MHz

- 155 - pF

-70-pF

-20-pF

- - 8.3

- - 175

o
o

C/W
C/W

4-2

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Forward Voltage V
Reverse Recovery Time t

SD

rr

FSL110D, FSL110R

ISD = 3.5A 0.6 - 1.8 V
ISD = 3.5A, dISD/dt = 100A/µs - - 220 ns

Electrical Specifications up to 100K RAD T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Drain to Source Breakdown Volts (Note 3) BV
Gate to Source Threshold Volts (Note 3) V
Gate to Body Leakage (Notes 2, 3) I
Zero Gate Leakage (Note 3) I
Drain to Source On-State Volts (Notes 1, 3) V
Drain to Source On Resistance (Notes 1, 3) r

DS(ON)12

DSS

GS(TH)

GSS
DSS

DS(ON)

VGS = 0, ID = 1mA 100 - V
VGS = VDS, ID = 1mA 1.5 4.0 V
VGS = ±20V, VDS = 0V - 100 nA
VGS = 0, VDS = 80V - 25 µA
VGS = 12V, ID = 3.5A - 2.21 V
VGS = 12V, ID = 2.5A - 0.600 Ω

NOTES:

1. Pulse test, 300µs Max.

2. Absolute value.

3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BV

DSS

.

Single Event Effects (SEB, SEGR) (Note 4)

ENVIRONMENT (NOTE 5)

TEST SYMBOL

ION

SPECIES

TYPICAL LET

(MeV/mg/cm)

TYPICAL

RANGE (µ)

Single Event Effects Safe Operating Area SEESOA Ni 26 43 -20 100

Br 37 36 -10 100
Br 37 36 -15 80
Br 37 36 -20 50

NOTES:

4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.

5. Fluence = 1E5 ions/cm2 (typical), T = 25oC.

6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).

APPLIED

VGS BIAS

(V)

(NOTE 6)

MAXIMUM

VDSBIAS (V)

Typical Performance Curves

LET = 26MeV/mg/cm

120

FLUENCE = 1E5 IONS/cm2 (TYPICAL)

100

80

(V)

60

DS

V

40

20

TEMP = 25oC

0

0 -10

LET = 37MeV/mg/cm2, RANGE = 36µ

-5
(V)

V

GS

Unless Otherwise Specified

2

, RANGE = 43µ

-15

-20 -25

LIMITING INDUCTANCE (HENRY)

1E-3

1E-4

1E-5

1E-6

1E-7

30

DRAIN SUPPLY (V)

ILM = 10A

30A

100A

300A

30010010

FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT

GAMMA DOT CURRENT TO I

AS

4-3

1000

FSL110D, FSL110R

Typical Performance Curves

4

3

2

, DRAIN (A)

D

I

1

0

TC, CASE TEMPERATURE (oC)

500-50

Unless Otherwise Specified (Continued)

100

FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs

TEMPERATURE

12V

Q

G

150

100

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

10

1

, DRAIN CURRENT (A)

D

I

0.1

0.01
VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

100µs

1ms

10ms

100ms

1

10 100

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

2.5
PULSE DURATION = 250ms, VGS = 12V, ID = 2.5A

2.0

DS(ON)

1.5

TC = 25oC

Q

GS

V

G

Q

GD

CHARGE

1.0

NORMALIZED r

0.5

0.0

-80 -40 0 40 80 120 160

FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED r

)

1

θJC

NORMALIZED

THERMAL RESPONSE (Z

0.001

0.1

0.01

0.5

0.2

0.1

0.05

0.02

0.01

-5

10

SINGLE PULSE

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

T

, JUNCTION TEMPERATURE (oC)

J

vs JUNCTION TEMPERA TURE

DS(ON)

P

DM

1/t2

+ T

θJC

C

-1

10

t

1

t

2

0

10

1

10

FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE

4-4

FSL110D, FSL110R

Typical Performance Curves

10

, AVALANCHE CURRENT (A)

AS

I

Test Circuits and Waveforms

ELECTRONIC SWITCH OPENS

V

Unless Otherwise Specified (Continued)

t

= (L/R) ln [(IAS*R) / (1.3 RATED BV

AV

t

= (L) (IAS) / (1.3 RATED BV

AV

STARTING TJ = 25oC

STARTING TJ = 150oC

1

0.01 0.1 1 10
, TIME IN AVALANCHE (ms)

t

AV

- VDD) + 1]

DSS

DSS

IF R ≠ 0

IF R = 0

- VDD)

FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING

WHEN I

DS

IS REACHED

AS

L

BV

DSS

P

t

AV

VARY t

TO OBTAIN

P

REQUIRED PEAK I

VGS≤ 20V

t

0V

P

CURRENT

TRANSFORMER

50Ω

AS

+

I

AS

-

+

V

DD

-

DUT

50Ω

50V-150V

t

I

AS

FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS

t

t

d(ON)

90%

ON

10%

t

r

PULSE WIDTH

0V

VGS = 12V

V

DD

R

L

V

DS

DUT

R

GS

V

DS

V

GS

10%

V

DS

t

d(OFF)

90%

t

OFF

50%50%

V

t

f

10%

DD

90%

FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS

4-5

FSL110D, FSL110R

Screening Information

Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).

Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) T

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

= 25oC, Unless Otherwise Specified

C

Gate to Source Leakage Current I
Zero Gate Voltage Drain Current I
Drain to Source On Resistance r
Gate Threshold Voltage V

NOTES:

7. Or 100% of Initial Reading (whichever is greater).

8. Of Initial Reading.

DS(ON)

GS(TH)

GSS

DSS

VGS = ±20V ±20 (Note 7) nA
VDS = 80% Rated Value ±25 (Note 7) µA
TC = 25oC at Rated I
ID = 1.0mA ±20% (Note 8) V

D

±20% (Note 8) Ω

Screening Information

TEST JANTXV EQUIVALENT JANS EQUIVALENT

Gate Stress VGS = 30V, t = 250µsV
Pind Optional Required
Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,

Subgroup 2 (All Static Tests at 25oC)

Steady State Gate
Bias (Gate Stress)

Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests

MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours

and Limits Table

= 30V, t = 250µs

GS

MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)

MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours

All Delta Parameters Listed in the Delta Tests
and Limits Table

Steady State Reverse
Bias (Drain Stress)

PDA 10% 5%
Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A,

NOTE:

9. Test limits are identical pre and post burn-in.

MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 160 hours

MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours

Subgroups 2 and 3

Additional Screening Tests

PARAMETER SYMBOL TEST CONDITIONS MAX UNITS

Safe Operating Area SOA VDS = 80V, t = 10ms 0.65 A
Unclamped Inductive Switching I
Thermal Response ∆V
Thermal Impedance ∆V

AS

SD

SD

V

GS(PEAK)

tH = 10ms; VH = 15V; IH = 1A 90 mV
tH = 500ms; VH = 15V; IH = 1A 230 mV

= 15V, L = 0.1mH 10.5 A

4-6

FSL110D, FSL110R

Rad Hard Data Packages - Intersil Power Transistors

TXV Equivalent

1. Rad Hard TXV Equivalent - Standard Data Package

A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
D. Group A - Attributes Data Sheet
E. Group B - Attributes Data Sheet

F. Group C - Attributes Data Sheet

G. Group D - Attributes Data Sheet

2. Rad Hard TXV Equivalent - Optional Data Package

A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet

- Precondition Lot Traveler

- Pre and Post Burn-In Read and Record
Data

D. Group A - Attributes Data Sheet

- Group A Lot Traveler

E. Group B - Attributes Data Sheet

- Group B Lot Traveler

- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup B3)

- Bond Strength Data (Subgroup B3)

- Pre and PostHigh Temperature Operating
Life Read and Record Data (Subgroup B6)

F. Group C - Attributes Data Sheet

- Group C Lot Traveler

- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup C6)

- Bond Strength Data (Subgroup C6)

G. Group D - Attributes Data Sheet

- Group D Lot Traveler

- Pre and Post RAD Read and Record Data

Class S - Equivalents

1. Rad Hard “S” Equivalent - Standard Data Package

A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report

E. Preconditioning Attributes Data Sheet

Hi-Rel Lot Traveler
HTRB - Hi TempGate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi TempDrain Stress Post Reverse
Bias Delta Data

F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet

I. Group D - Attributes Data Sheet

2. Rad Hard Max. “S” Equivalent - Optional Data Package

A. Certificate of Compliance

B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report

E. Preconditioning - Attributes Data Sheet

- Hi-Rel Lot Traveler

- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data

- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data

- X-Ray and X-Ray Report

F. Group A - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Subgroups A2, A3, A4, A5 and A7 Data

G. Group B - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Subgroups B1, B3, B4, B5 and B6 Data

H. Group C - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Subgroups C1, C2, C3 and C6 Data

I. Group D - Attributes Data Sheet

- Hi-Rel Lot Traveler

- Pre and Post Radiation Data

4-7

FSL110D, FSL110R

TO-205AF

3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE

ØD

ØD

1

A

P

SYMBOL

A 0.160 0.180 4.07 4.57 -

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

Øb 0.016 0.021 0.41 0.53 2, 3

h

L

e

1

e

2

45

j

1

o

SEATING
PLANE

Øb

e

o

90

2

3

k

ØD 0.350 0.370 8.89 9.39 -

ØD

0.315 0.335 8.01 8.50 -

1

e 0.095 0.105 2.42 2.66 4

e

1

e

2

0.190 0.210 4.83 5.33 4

0.095 0.105 2.42 2.66 4

h 0.010 0.020 0.26 0.50 -

j 0.028 0.034 0.72 0.86 ­k 0.029 0.045 0.74 1.14 ­L 0.500 0.560 12.70 14.22 3

P 0.075 - 1.91 - 5

NOTES:

1. These dimensions are within allowable dimensions of Rev. E of
JEDEC TO-205AF outline dated 11-82.

2. Lead dimension (without solder).

3. Solder coating may vary along lead length, add typically 0.002
inches (0.05mm) for solder coating.

4. Positionof leadtobe measured0.100inches (2.54mm)frombottom
of seating plane.

5. This zone controlled for automatic handling. The variation in
actual diameter within this zone shall not exceed 0.010 inches
(0.254mm).

6. Lead no. 3 butt welded to stem base.

7. Controlling dimension: Inch.

8. Revision 3 dated 6-94.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly , the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

4-8

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