Datasheet FPBL15SH60 Datasheet (Fairchild Semiconductor)

FPBL15SH60

Smart Power Module (SPM)

General Description

FPBL15SH60 is an advanced smart power module (SPM)
that Fairchild has newly developed and designed to provide
very compact and low cost, yet high performance ac motor
drives mainly targeting high speed low-power inverter­driven application like washing machines. It combines
optimized circuit protection and drive matched to low-loss
IGBTs. Highly effective short-circuit current detection/
protection is realized through the use of advanced current
sensing IGBT chips that allow continuous monitoring of the
IGBTs current. System reliability is further enhanced by the
integrated under-voltage lock-out protection. The high
speed built-in HVIC provides opto-coupler-less IGBT gate
driving capability that further reduce the overall size of the
inverter system design. In addition the incorporated HVIC
facilitates the use of single-supply drive topology enabling
the FPBL15SH60 to be driven by only one drive supply
voltage without negative bias.

FPBL15SH60

Features

• UL Certified No. E209204

• 600V-15A 3-phase IGBT inverter bridge including control
ICs for gate driving and protection

• Single-grounded power supply due to built-in HVIC

• Typical switching frequency of 15kHz

• Inverter power rating of 0.75kW / 100~253 Vac

• Isolation rating of 2500Vrms/min.

• Very low leakage current due to using ceramic substrate

• Adjustable current protection level by varying series
resistor value with sense-IGBTs

Applications

• AC 100V ~ 253V three-phase inverter drive for small
power (0.75kW) ac motor drives

• Home appliances applications requiring high switching
frequency operation like washing machines drive system

• Application ratings:

- Power : 0.75kW / 100~253 Vac

- Switching frequency : Typical 15kHz (PWM Control)

- 100% load current : 5A (Irms)

- 150% load current : 7.5A (Irms)

External View and Marking Information

Top View Bottom View

57 mm

55 mm

Device Name

Version, Lot Code

Marking

Fig. 1.

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

Integrated Power Functions

• 600V-15A IGBT inverter for three-phase DC/AC power conversion (Please refer to Fig. 3)

Integrated Drive, Protection and System Control Functions

• For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting

• For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC)

• Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side supply)

• Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input

Control circuit under-voltage (UV) protection
Note) Available bootstrap circuit example is given in Figs. 10, 15 and 16.

Control supply circuit under-voltage (UV) protection

Pin Configuration

Top View

V

S(U)

V

B(U)

V

CC(UH)

IN

V

COM

IN
IN

IN

C

CC(L)

(UL)
(VL)

(WL)

V

FOD

C

R

NC
NC

NC

(L)

FO

SC

SC

(UH)

V

S(V)

V

B(V)

V

CC(VH)

IN

(VH)

COM

V

S(W)

V

B(W)

V

CC(WH)

IN

(WH)

FPBL15SH60

(H)

WVUNP

Fig. 2.

Pin Descriptions

Pin Number Pin Name Pin Description

1V

CC(L)

2COM
3IN
4IN
5IN
6V
7C
8C

9R
10 NC No Connection
11 NC No Connection
12 NC No Connection
13 W Output Terminal for W Phase
14 V Output Terminal for V Phase
15 U Output Terminal for U Phase
16 N Negative DC–Link Input

©2002 Fairchild Semiconductor Corporation

(UL)
(VL)

(WL)

FO

FOD

SC
SC

Low-side Common Bias Voltage for IC and IGBTs Driving
Low-side Common Supply Ground

(L)

Signal Input Terminal for Low-side U Phase
Signal Input T erminal for Low-side V Phase
Signal Input T erminal for Low-side W Phase
Fault Output Terminal
Capacitor for Fault Output Duration Time Selection
Capacitor (Low-pass Filter) for Short-current Detection Input

Resistor for Short-circuit Current Detection

Rev. C, February 2002

Pin Descriptions (Continued)

Pin Number Pin Name Pin Description

17 P Positive DC–Link Input
18 IN
19 V
20 V
21 V

(WH)

CC(WH)

B(W)
S(W)

22 COM
23 IN
24 V
25 V
26 V

CC(VH)

B(V)
S(V)

27 IN
28 V
29 V
30 V

CC(UH)

B(U)
S(U)

(VH)

(UH)

Signal Input Terminal for High-side W Phase
High-side Bias Voltage for W Phase IC
High-side Bias Voltage for W Phase IGBT Driving
High-side Bias Voltage Ground for W Phase IGBT Driving
High-side Common Supply Ground

(H)

Signal Input Terminal for High-side V Phase
High-side Bias Voltage for V Phase IC
High-side Bias Voltage for V Phase IGBT Driving
High-side Bias Voltage Ground for V Phase IGBT Driving
Signal Input Terminal for High-side U Phase
High-side Bias Voltage for U Phase IC
High-side Bias Voltage for U Phase IGBT Driving
High-side Bias Voltage Ground for U Phase IGBT Driving

Internal Equivalent Circuit and Input/Output Pins

(1) V

(2) COM

(3) IN

(4) IN

(5) IN

(6) V

FO

(7) C

FOD

(8) C

SC

(9) R

SC

(10) NC
(11) NC
(12) NC

CC(L)

(L)

(UL)

(VL)

(WL)

V

CC

COM

IN

(UL)

IN

(VL)

IN

(WL)

V

(FO)

C

(FOD)

C

(SC)

(L)

Uout

Vout

Wout

VB
HO
VS

VB
HO
VS

VB
HO
VS

Vcc

COM

Vcc

COM

Vcc

COM

FPBL15SH60

(29) V

B(U)

(28) V

CC(UH)

IN

IN

IN

(27) IN

(UH)

(30) V

S(U)

(25) V

B(V)

(24) V

CC(VH)

(23) IN

(VH)

(22) COM
(26) V

S(V)

(20) V

B(W)

(19) V

CC(WH)

(18) IN

(WH)

(21) V

S(W)

(H)

WVUN

(13)

Note

1. Inverter low-side ( (1) - (12) pins) is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving,
current sensing and protection functions.

2. Inverter power side ( (13) - (17) pins) is composed of two inverter dc-link input terminals and three inverter output terminals.

3. Inverter high-side ( (18) - (30) pins) is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT.

(14) (15) (16)

P

(17)

Fig. 3.

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

Absolute Maximum Ratings

Inverter Part

Supply Voltage V
Supply Voltage (Surge) V
Collector-Emitter Voltage V
Each IGBT Collector Current ± I
Each IGBT Collector Current (Peak) ± I
Collector Dissipation P
Operating Junction Temperature T

Note

1. It would be recommended that the average junction temperature should be limited to TJ ≤ 125°C (@TC ≤ 100°C) in order to guarantee safe operation.

(TC = 25°C, Unless Otherwise Specified)

Item Symbol Condition Rating Unit

DC

PN(Surge)

CES

Applied to DC - Link 450 V
Applied between P- N 500 V

600 V

TC = 25°C (Note Fig. 4) 15 A

C

TC = 25°C (Note Fig. 4) 30 A

CP

TC = 25°C per One Chip 47 W

C

(Note 1) -55 ~ 150 °C

J

FPBL15SH60

Control Part

(TC = 25°C, Unless Otherwise Specified)

Item Symbol Condition Rating Unit

Control Supply Voltage V
High-side Control Bias Voltage V

Applied between V

CC

Applied between V

BS

V

Input Signal Voltage V

Applied between IN

IN

IN
Fault Output Supply Voltage V
Fault Output Current I
Current Sensing Input Voltage V

Applied between VFO - COM

FO

Sink Current at VFO Pin 5 mA

FO

Applied between CSC - COM

SC

Total System

Item Symbol Condition Rating Unit

Self Protection Supply Voltage Limit
(Short Circuit Protection Capability)

Module Case Operation Temperature T
Storage T emperature T
Isolation Voltage V

V

DC(PROT)

S(W)

(UL)

STG

ISO

, IN

(VL)

, IN

(WL)

CC(H)

- V

B(U)

(UH)

- COM

- COM

, IN

S(U)

(VH)

(L)

, V

(WH)

CC(L)

- V

- COM

- COM

S(V)

, V

B(W)

(H)

(L)

-

-0.3~VCC+0.5 V

-0.3~VCC+0.5 V

(H)

, V

B(V)

, IN

(L)

(L)

Applied to DC - Link,

= VBS = 13.5 ~ 16.5V

V

CC

T

= 125°C, Non-repetitive, less than 6µs

J

Note Fig. 4 -20 ~ 100 °C

C

-55 ~ 150 °C

60Hz, Sinusoidal, AC 1 minute, Connection

2500 V

Pins to Heat- sink Plate

18 V
20 V

-0.3 ~ 6.0 V

400 V

rms

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

V

COM

IN
IN

IN

C

CC(L)

(UL)
(VL)

(WL)

V

FOD

C

R

NC
NC

NC

FPBL15SH60

Case Temperature (TC) Detecting Point

V

S(U)

V

B(U)

V

CC(UH)

IN

(L)

FO

SC

SC

WVUNP

Fig. 4. Tc Measurement Point

(UH)

V

S(V)

V

B(V)

V

CC(VH)

IN

(VH)

COM

V

S(W)

V

B(W)

V

CC(WH)

IN

(WH)

(H)

Ceramic
Substate

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

Absolute Maximum Ratings

Thermal Resistance

Item Symbol Condition Min. Typ. Max. Unit

Junction to Case Thermal

R

th(j-c)Q

Resistance

R

Contact Thermal

R

Resistance

Note

2. For the measurement point of case temperature (Tc), please refer to Fig. 4.

Each IGBT under Inverter Operating Condition
(Note 2)

Each FWDi under Inverter Operating Condition

th(j-c)F

(Note 2)
Ceramic Substrate (per 1 Module)

th(c-f)

Thermal Grease Applied

Electrical Characteristics

Inverter Part

Collector - Emitter
Saturation Voltage

FWDi Forward Voltage V

Switching Times t

Collector - Emitter
Leakage Current

(Tj = 25°C, Unless Otherwise Specified)

Item Symbol Condition Min. Typ. Max. Unit

V

CE(SAT)VCC

FM

ON

t

C(ON)

t

OFF

t

C(OFF)

t

rr

I

CES

= VBS = 15V

V

= 0V

IN

VIN = 5V IC = 15A, Tj = 25°C - - 2.3 V

VPN = 300V, VCC = VBS = 15V
I

= 15A, Tj = 25°C

C

= 5V ↔ 0V, Inductive Load

V

IN

(High-Low Side)
(Note 3)

VCE = V

, Tj = 25°C - - 250 µA

CES

- - 2.61 °C/W

- - 3.73 °C/W

- - 0.06 °C/W

= 15A, Tj = 25°C - - 2.8 V

I

C

= 15A, Tj = 125°C - - 2.9 V

I

C

= 15A, Tj = 125°C - - 2.1 V

I

C

-0.39-µs

-0.12-µs

-0.53-µs

-0.16-µs

-0.1-µs

FPBL15SH60

Note

3. tON and t
internally. For the detailed information, please see Fig. 5.

include the propagation delay time of th e internal drive IC. t

OFF

C(ON)

and t

are the switching time o f IGBT itself u nder the given gate drivin g condition

C(OFF)

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

V

V

IN(ON)

IN(ON)

FPBL15SH60

100% I

100% I

C

t

t

rr

rr

V

V

CE

CE

V

V

IN

IN

t

t

ON

ON

10% I

10% I

(a) Turn-on

(a) Turn-on (b) Turn-off

C

I

I

C

C

t

t

C(ON)

C(ON)

90% I

90% I

C

C

10% V

10% V

C

C

CE

CE

Fig 5. Switching Time Definition

V

V

IN(OFF)

IN(OFF)

V

V

IN

IN

t

t

I

I

C

C

OFF

OFF

10% VCE10% I

10% VCE10% I

(b) Turn-off

t

t

C(OFF)

C(OFF)

V

V

CE

CE

C

C

VCE: 100V/div.

VCE: 100V/div.

time : 100ns/div.

time : 100ns/div.

(a) Turn-on

(a) Turn-on

: 5A/div.

: 5A/div.

I

I

C

C

IC: 5A/div.

IC: 5A/div.

time : 100ns/div.

time : 100ns/div.

(b) Turn-off

(b) Turn-off

Fig. 6. Experimental Results of Switching Waveforms

Test Condition: Vdc=300V, Vcc=15V, L=500uH (Inductive Load), T

VCE: 100V/div.

VCE: 100V/div.

=25°°°°C

C

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

Electrical Characteristics

Control Part

Control Supply Voltage V
High-Side Bias Voltage V

Quiescent V
Current

Quiescent V
Current

Fault Output Voltage V

PWM Input Frequency f
Allowable Input Signal

Blanking Time Considering
Leg Arm-Short

Short Circuit Trip Level V
Sensing Voltage

of IGBT Current
Supply Circuit Under-

Voltage Protection

Fault-Out Pulse Width t

ON Threshold Voltage V
OFF Threshold Voltage V
ON Threshold Voltage V
OFF Threshold Voltage V

Note

4. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be
selected around 56 Ω in order to make the SC trip-level of about 20A.
Please refer to Fig. 7 which shows the current sensing characteristics according to sensing resistor RSC.

5. The fault-out pulse width t

(Tj = 25°C, Unless Otherwise Specified)

Item Symbol Condition Min. Typ. Max. Unit

Supply

CC

Supply

BS

Applied between V

CC

Applied between V

BS

V

- V

B(W)

I

QCCLVCC

I

QCCHVCC

I

QBSVBS

FOHVSC

V

FOLVSC

PWMTC

t

dead

SC(ref)TJ

V

SEN

UV

CCDTJ

UV

CCR

UV

BSD

UV

BSR

FODVCC

IN(ON)

IN(OFF)

IN(ON)

IN(OFF)

depends on the capacitance value of C

FOD

= 15V

IN

(UL, VL, WL)

= 15V

IN

(UH, VH, WH)

= 15V

IN

(UH, VH, WH)

= 0V, VFO Circuit: 4.7kΩ to 5V Pull-up 4.5 - - V
= 1V, VFO Circuit: 4.7kΩ to 5V Pull-up - - 1.1 V

≤ 100°C, TJ ≤ 125°C - 15 - kHz

-20°C ≤ TC ≤ 100°C 1.5 - - us

= 25°, VCC = 15V (Note 4) 0.45 0.51 0.56 V

-20°C ≤ TC ≤ 100°C, @ RSC = 82 Ω and
I

= 15A (Note Fig. 7)

C

≤ 125°C Detection Level 11.5 12 12.5 V

= 15V, C(sc) = 1V

= 33nF (Note 5)

C

FOD

High-Side Applied between IN

Low-Side Applied between IN

S(W)

CC(H),VCC(L)
B(U)

= 5V

= 5V

= 5V

according to the following approximate equation : C

FOD

- COM 13.5 15 16.5 V

- V

, V

- V

S(U)

V

CC(L)

V

CC(U)

COM
V

B(U)

V

B(W)

- COM

, V

(H)

- V

S(U)

- V

B(V)

CC(V)

S(W)

, V

,

S(V)

(L)

, V

-

CC(W)

-V

B(V)

S(V)

13.5 15 16.5 V

--26mA

- - 130 uA

,

- - 420 uA

0.37 0.45 0.56 V

Reset Level 12 12.5 13 V
Detection Level 7.3 9.0 10.8 V
Reset Level 8.6 10.3 12 V

1.4 1.8 2.0 ms

, IN

,

(UH)

(UL)

, IN

(VH)

(VL)

- COM

IN

(WH)

IN

(WL)

- COM

(H)

(L)

--0.8V

3.0 - - V

,

--0.8V

3.0 - - V

= 18.3 x 10-6 x t

FOD

FOD

[F]

FPBL15SH60

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

FPBL15SH60

90

80

70

[A]

SC

60

50

40

30

SC Trip Current I

20

10

10 20 30 40 50 60 70 80 90

Sensing Resistor RSC [Ω]

Fig. 7. Relationship between Sensing Resistor and SC Trip Current
for Short-Circuit Protection
(I

= 82 ×××× Rating Current(15A) / RSC)

SC

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

Mechanical Characteris ti cs and Ratings

FPBL15SH60

Item Condition

Mounting Torque Mounting Screw: M3

(Note 6 and 7)

Ceramic Flatness (Note Fig. 8) 0 - +100 um
Weight -56-g

Recommended 10kg•cm 8 10 12 Kg•cm
Recommended 0.98N•m 0.78 0. 98 1.17 N•m

Limits

Min. Typ. Max.

Units

Fig. 8. Flatness Measurement Position of The Ceramic Substrate

Note

6. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction.

7. Avoid one side tightening stress. Fig.9 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to

be damaged.

4

4

2222

1

1

3

3

Fig. 9. Mounting Screws Torque Order (1 →→→→ 2 →→→→ 3 →→→→ 4)

2222

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

Recommended Operating Conditions

FPBL15SH60

Item Symbol Condition

Supply Voltage V
Control Supply Voltage V

High-Side Bias Voltage V

Blanking Time for Preventing

t

PN
CC

BS

dead

Applied between P - N - 300 400 V
Applied between V

- COM

V

CC(L)

Applied between V
V

- V

B(W)

S(W)

CC(H)

(L)

B(U)

For Each Input Signal 1.5 - - us

Arm-short
PWM Input Signal f
Input ON Threshold Voltage V
Input OFF Threshold Voltage V

PWMTC

IN(ON)

IN(OFF)

≤ 100°C, TJ ≤ 125°C - 15 - kHz
Applied between UIN,VIN, WIN - COM 0 ~ 0.65 V
Applied between UIN,VIN, WIN - COM 4 ~ 5.5 V

ICs Internal Structure and Input/Output Conditions

D

BS

UV

DETECT

PULSE
FILTER

HVIC

HVIC

HVICHVIC

15V Line

15V Line

15V Line15V Line

5V Line

5V Line

5V Line5V Line

R

C

R

BS

VCC

VCC

VCCVCC

(UH,VH,WH)

(UH,VH,WH)

(UH,VH,WH)(UH,VH,WH)

LEVEL

C

BP15

P

PH

IN

IN

ININ

(UH,VH,WH)

(UH,VH,WH)

(UH,VH,WH)(UH,VH,WH)

COM

COM

COMCOM

SHIFT

PULSE

GENERATOR

- COM

- V

S(U)

R
R
S Q

, V

(H)

B(V)

,

VS

VS

VSVS

- V

VB

VB

VBVB

(UH,VH,WH)

(UH,VH,WH)

(UH,VH,WH)(UH,VH,WH)

(UH,VH,WH)

(UH,VH,WH)

(UH,VH,WH)(UH,VH,WH)

S(V)

Value

Min. Typ. Max.

13.5 15 16.5 V

,

13.5 15 16.5 V

C

C

BSC

BS

Unit

PPPP

U,V,W

U,V,W

LVIC

LVIC

TIME

DELAY

LVICLVIC

BUFFER

SOFT_OFF
CONTROL

SC

DETECTION

OUTPUT

(UL,VL,WL)

R

F

C

SC

R

VCC

VCC

VCCVCC

(L)

(L)

(L)(L)

5V Line

5V Line

5V Line5V Line

R

R

P

PF

IN

IN

ININ

(UL,VL,WL)

(UL,VL,WL)

(UL,VL,WL)(UL,VL,WL)

VVVV

FO

FO

FOFO

C

C

PF

PL

C

FOD

Note

1. One LVIC drives three Sense-IGBTs and can do short-circuit current protection also. Three sense emitters are commonly connected to RSC terminal to detect
short-circuit current. Low-side part of the inverter consists of three sense-IGBTs

2. One HVIC drives one normal-IGBT. High-side part of the inverter consists of three normal-IGBTs

3. Each IC has under voltage detection and protection function.

4. The logic input is compatible with standard CMOS or LSTTL outputs.

5. RPCP coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each
SPM gating input pin.

6. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.

CCCC

FOD

FOD

FODFOD

UV

DETECT

BANDGAP

REFERENCE

PULSE

GENERATOR

(HYSTERISIS)

FAULT OUTPUT

DURATION

TIME

DELAY

UV

LATCH_UP

UV

PROTECTION

SC

PROTECTION

SC

LATCH_UP

U,V,WU,V,W

NNNN

SC

Fig. 10.

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

Time Charts of SPMs Protective Function

Input Signal

FPBL15SH60

Internal IGBT

Gate-Emitter Voltage

Control Supply Voltage

Output Current

Fault Output Signal

P1 : Normal operation - IGBT ON and conducting current
P2 : Under voltage detection
P3 : IGBT gate interrupt
P4 : Fault signal generation
P5 : Under voltage reset
P6 : Normal operation - IGBT ON and conducting current

Fig. 11. Under-Voltage Protection (Low-side)

Input Signal

UV

detect
P1

P3

P2

P4

P5

UV

reset

P6

Internal IGBT

Gate-Emitter Voltage

Control Supply Voltage

V

BS

Output Current

Fault Output Signal

P1 : Normal operation - IGBT ON and conducting current
P2 : Under voltage detection
P3 : IGBT gate interrupt
P4 : No fault signal
P5 : Under voltage reset
P6 : Normal operation - IGBT ON and conducting current

Fig. 12. Under-Voltage Protection (High-side)

©2002 Fairchild Semiconductor Corporation

UV

detect
P1

P4

P3

P2

P5

UV

reset

P6

Rev. C, February 2002

Input Signal

FPBL15SH60

P5

Internal IGBT

P6

Gate-Emitter Voltage

SC Detection

P1

P4

Output Current

P7

P2

SC Reference

Sensing Voltage

RC Filter Delay

Fault Output Signal

P1 : Normal operation - IGBT ON and conducting currents
P2 : Short-circuit current detection
P3 : IGBT gate interrupt / Fault signal generation
P4 : IGBT is slowly turned off
P5 : IGBT OFF signal
P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation
P7 : IGBT OFF sta te
P8 : Fault-output reset and normal operation start

Voltage (0.5V)

P3

P8

Fig. 13. Short-circuit Current Protection (Low-side Operation only)

4.7k

Ω

100

Ω

100

Ω

CPU

100

Ω

1nF

Note

It would be recommended that by-pass capacitors for the gating input signals, IN
for the fault output signal, VFO, as close as possible.

©2002 Fairchild Semiconductor Corporation

Fig. 14. Recommended CPU I/O Interface Circuit

5V-Line

FPBL15SH 60

4.7k

(XX)

4.7k

Ω

should be placed on the SPM pins and on the both sides of CPU and SPM

Ω

,,

IN

(UH)IN(VH)

,,

IN

(UL)IN(VL)

V

FO

1.2nF0.47nF1nF
COM

IN

IN

(WH)

(WL)

Rev. C, February 2002

1000uF

1000uF

One-leg Diagram of FPBL15SH60

15V-Line

15V-Line

20Ω

20Ω

220uF

220uF

0.1uF

0.1uF

0.1uF

0.1uF

One-leg Diagram of FPBL15SH60

Vcc

VB

Vcc

VB

IN

HO

IN

HO

COM

VS

COM

VS

Vcc

Vcc

IN

OUT

IN

OUT

COM

COM

Fig. 15. Recommended Bootstrap Operation Circuit and Parameters

P

P

Inverter

Inverter
Output

Output

N

N

FPBL15SH60

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

FPBL15SH60

Gating UL

Gating VL

Gating WL

(1) V

(2) COM

(3) IN

(4) IN

(5) IN

(6) V

(7) C

(8) C

(9) R

(10) NC
(11) NC

(12) NC

Fault

CC(L)

V

CC

(L)

COM

(L)

(UL)

(VL)

(WL)

FO

FOD

SC

SC

Uout

IN

(UL)

IN

(VL)

Vout

IN

(WL)

V

(FO)

Wout

C

(FOD)

C

(SC)

C

BPF

RSRSRSR

S

5V line

R

RPRPR

P

P

C

C

C

C

PL

PL

PL

PF

C

FOD

C

SC

R

F

R

SC

CPU

(13)

(14) (15) (16) (17) P

WV U N

Gating UH

Gating VH

Gating WH

R

RSR

S

S

RBSD

V

V

CC(UH)

Vcc

VB

IN

IN

HO

COM

VS

VB
HO
VS

VB
HO
VS

C

DCS

COM

COM

V

V

V

CC(VH)

Vcc

IN

IN

COM

V

V

V

CC(WH)

Vcc

IN

IN

V

BS

(29)

B(U)

(28)
(27)

(UH)

C

C

(30)

BS

BSC

S(U)

(25)

B(V)

(24)
(23)

(VH)

(22)

(H)

(26)

S(V)

(20)

B(W)

(19)

(18)

(WH)

(21)

S(W)

RBSD

BS

CBSC

BSC

RBSD

BS

CBSC

BSC

C

SPC15

15V line

5V line

RPR

R

P

P

CPHC

C

PH

PH

C

SP15

M

+-

Vdc

Note

1. RPCPL/RPCPH coupling at each SPM input is recommended in order to prevent input signals’ oscillation and it should be as close as possible to each SPM inp ut
pin.

2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is
possible.

3. VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resistance. Please
refer to Fig. 14.

4. C

of around 7 times larger than bootstrap capacitor CBS is recommended.

SP15

5. VFO output pulse width should be determined by connecting an external capacitor(C
then tFO = 300 µs (typ.)) Please refer to the note 5 for calculation method.

6. Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ resistance (other RC coupling circuits at each input may be needed
depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board). Approximately a 0.22~2nF by-pass capacitor
should be used across each power supply connection terminals.

7. To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible.

8. In the short-circuit protection circui t, plea se select th e RFCSC time constant in the range 3~4 µs. RF should be at least 30 times larger than RSC. (Recommended
Example: RSC = 56 Ω, RF = 3.9kΩ and CSC = 1nF)

9. Each capacitor should be mounted as close to the pins of the SPM as possible.

10.To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high frequency non­inductive capacitor of around 0.1~0.22 uF between the P&N pins is recommended.

11. Relays are used at almost every syste ms o f electr ical equ ipments of home app liances. In the s e cases, ther e should be suf fi cient distance b etw een the CPU a nd
the relays. It is recommended that the distance be 5cm at least

) between C

FOD

(pin7) and COM

FOD

(pin2). (Example : if C

(L)

FOD

= 5.6 nF,

Fig. 16. Application Circuit

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

Detailed Package Outline Drawings

FPBL15SH60

©2002 Fairchild Semiconductor Corporation

Rev. C, February 2002

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.

ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™

2

CMOS™

E
EnSigna™
FACT™
FACT Quiet Series™

STAR*POWER is used under license

®

FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™

OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench

®

QFET™
QS™
QT Optoelectronics™
Quiet Series™
SLIENT SWITCHER

SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TruTranslation™
TinyLogic™
UHC™

®

UltraFET

VCX™

®

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

2. A critical component is any com ponent of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

©2002 Fairchild Semiconductor Corporation Rev. H4

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.