Datasheet FPBL10SH60 Datasheet (Fairchild Semiconductor)

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

FPBL10SH60

Smart Power Module (SPM)

General Description

FPBL10SH60 is an advanced smart power module (SPM)
that Fairchild has newly developed and designed to provide
very compact and low cost, yet high performance ac motor
drives mainly targeting high speed low-power inverter­driven application like washing machines. It combines
optimized circuit protection and drive matched to low-loss
IGBTs. Highly effective short-circuit current detection/
protection is realized through the use of advanced current
sensing IGBT chips that allow continuous monitoring of the
IGBTs current. System reliability is further enhanced by the
integrated under-voltage lock-out protection. The high
speed built-in HVIC provides opto-coupler-less IGBT gate
driving capability that further reduce the overall size of the
inverter system design. In addition the incorporated HVIC
facilitates the use of single-supply drive topology enabling
the FPBL10SH60 to be driven by only one drive supply
voltage without negative bias.

Features

• UL Certified No. E209204

• 600V-10A 3-phase IGBT inverter bridge including control
ICs for gate driving and protection

• Single-grounded power supply due to built-in HVIC

• Typical switching frequency of 15kHz

• Inverter power rating of 0.4kW / 100~253 Vac

• Isolation rating of 2500Vrms/min.

• Very low leakage current due to using ceramic substrate

• Adjustable current protection level by varying series
resistor value with sense-IGBTs

Applications

• AC 100V ~ 253V three-phase inverter drive for small
power (0.4kW) ac motor drives

• Home appliances applications requiring high switching
frequency operation like washing machines drive system

• Application ratings:

- Power : 0.4 kW / 100~253 Vac

- Switching frequency : Typical 15kHz (PWM Control)

- 100% load current : 3A (Irms)

- 150% load current : 4.5A (Irms)

External View and Marking Information

Fig. 1.

55 mm

57 mm

Top View Bottom View

Marking

Device Name

Version, Lot Code

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Integrated Power Functions

• 600V-10A IGBT inverter for three-phase DC/AC power conversion (Please refer to Fig. 3)

Integrated Drive, Protection and System Control Functions

• For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting
Control circuit under-voltage (UV) protection
Note) Available bootstrap circuit example is given in Figs. 10, 15 and 16.

• For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC)
Control supply circuit under-voltage (UV) protection

• Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side supply)

• Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input

Pin Configuration

Fig. 2.

Pin Descriptions

Pin Number Pin Name Pin Description

1V

CC(L)

Low-side Common Bias Voltage for IC and IGBTs Driving

2COM

(L)

Low-side Common Supply Ground

3IN

(UL)

Signal Input T erminal for Low-side U Phase

4IN

(VL)

Signal Input T erminal for Low-side V Phase

5IN

(WL)

Signal Input T erminal for Low-side W Phase

6V

FO

Fault Output Terminal

7C

FOD

Capacitor for Fault Output Duration Time Selection

8C

SC

Capacitor (Low-pass Filter) for Short-current Detection Input

9R

SC

Resistor for Short-circuit Current Detection
10 NC No Connection
11 NC No Connection
12 NC No Connection
13 W Output Terminal for W Phase
14 V Output Terminal for V Phase
15 U Output Terminal for U Phase
16 N Negative DC–Link Input

V

CC(L)

COM

(L)

IN

(UL)

IN

(VL)

IN

(WL)

V

FO

C

FOD

C

SC

R

SC

NC
NC

NC

WVUNP

V

S(U)

V

B(U)

V

CC(UH)

IN

(UH)

V

S(V)

V

B(V)

V

CC(VH)

IN

(VH)

COM

(H)

V

S(W)

V

B(W)

V

CC(WH)

IN

(WH)

Top View

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Internal Equivalent Circuit and Input/Output Pins

Note

1. Inverter low-side ( (1) - (12) pins) is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving,
current sensing and protection functions.

2. Inverter power side ( (13) - (17) pins) is composed of two inverter dc-link input terminals and three inverter output terminals.

3. Inverter high-side ( (18) - (30) pins) is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT.

Fig. 3.

17 P Positive DC–Link Input
18 IN

(WH)

Signal Input T erminal for High-side W Phase

19 V

CC(WH)

High-side Bias Voltage for W Phase IC

20 V

B(W)

High-side Bias Voltage for W Phase IGBT Driving

21 V

S(W)

High-side Bias Voltage Ground for W Phase IGBT Driving

22 COM

(H)

High-side Common Supply Ground

23 IN

(VH)

Signal Input T erminal for High-side V Phase

24 V

CC(VH)

High-side Bias Voltage for V Phase IC

25 V

B(V)

High-side Bias Voltage for V Phase IGBT Driving

26 V

S(V)

High-side Bias Voltage Ground for V Phase IGBT Driving

27 IN

(UH)

Signal Input T erminal for High-side U Phase

28 V

CC(UH)

High-side Bias Voltage for U Phase IC

29 V

B(U)

High-side Bias Voltage for U Phase IGBT Driving

30 V

S(U)

High-side Bias Voltage Ground for U Phase IGBT Driving

Pin Descriptions (Continued)

Pin Number Pin Name Pin Description

WVUN

(14) (15) (16)

(17)

P

(1) V

CC(L)

(2) COM

(L)

(3) IN

(UL)

(4) IN

(VL)

(5) IN

(WL)

(6) V

FO

(7) C

FOD

(8) C

SC

(12) NC

(11) NC

(13)

(29) V

B(U)

(22) COM

(H)

(27) IN

(UH)

(30) V

S(U)

(28) V

CC(UH)

(25) V

B(V)

(23) IN

(VH)

(24) V

CC(VH)

(26) V

S(V)

(20) V

B(W)

(18) IN

(WH)

(19) V

CC(WH)

(21) V

S(W)

(10) NC

(9) R

SC

V

CC

Wout

Uout

Vout

C

(SC)

C

(FOD)

V

(FO)

IN

(WL)

IN

(VL)

IN

(UL)

COM

(L)

Vcc

IN

COM

VB
HO
VS

Vcc

IN

COM

VB
HO
VS

Vcc

IN

COM

VB
HO
VS

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Absolute Maximum Ratings

Inverter Part

(TC = 25°C, Unless Otherwise Specified)

Note

1. It would be recommended that the average junction temperature should be limited to TJ ≤ 125°C (@TC ≤ 100°C) in order to guarantee safe operation.

Control Part

(TC = 25°C, Unless Otherwise Specified)

Total System

Item Symbol Condition Rating Unit

Supply Voltage V

DC

Applied to DC - Link 450 V

Supply Voltage (Surge) V

PN(Surge)

Applied between P- N 500 V

Collector-Emitter Voltage V

CES

600 V

Each IGBT Collector Current ± I

C

TC = 25°C (Note Fig. 4) 10 A

Each IGBT Collector Current (Peak) ± I

CP

TC = 25°C (Note Fig. 4) 20 A

Collector Dissipation P

C

TC = 25°C per One Chip 43 W

Operating Junction Temperature T

J

(Note 1) -55 ~ 150 °C

Item Symbol Condition Rating Unit

Control Supply Voltage V

CC

Applied between V

CC(H)

- COM

(H)

, V

CC(L)

- COM

(L)

18 V

High-side Control Bias Voltage V

BS

Applied between V

B(U)

- V

S(U)

, V

B(V)

- V

S(V)

, V

B(W)

-

V

S(W)

20 V

Input Signal Voltage V

IN

Applied between IN

(UH)

, IN

(VH)

, IN

(WH)

- COM

(H)

IN

(UL)

, IN

(VL)

, IN

(WL)

- COM

(L)

-0.3 ~ 6.0 V

Fault Output Supply Voltage V

FO

Applied between VFO - COM

(L)

-0.3~VCC+0.5 V

Fault Output Current I

FO

Sink Current at VFO Pin 5 mA

Current Sensing Input Voltage V

SC

Applied between CSC - COM

(L)

-0.3~VCC+0.5 V

Item Symbol Condition Rating Unit

Self Protection Supply Voltage Limit
(Short Circuit Protection Capability)

V

DC(PROT)

Applied to DC - Link,
V

CC

= VBS = 13.5 ~ 16.5V

T

J

= 125°C, Non-repetitive, less than 6µs

400 V

Module Case Operation Temperature T

C

Note Fig. 4 -20 ~ 100 °C

Storage Temperature T

STG

-55 ~ 150 °C

Isolation Voltage V

ISO

60Hz, Sinusoidal, AC 1 minute, Connection
Pins to Heat-sink Plate

2500 V

rms

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Fig. 4. Tc Measurement Point

V

CC(L)

COM

(L)

IN

(UL)

IN

(VL)

IN

(WL)

V

FO

C

FOD

C

SC

R

SC

NC
NC

NC

WVUNP

V

S(U)

V

B(U)

V

CC(UH)

IN

(UH)

V

S(V)

V

B(V)

V

CC(VH)

IN

(VH)

COM

(H)

V

S(W)

V

B(W)

V

CC(WH)

IN

(WH)

Case Temperature (TC) Detecting Point

Ceramic
Substate

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Absolute Maximum Ratings

Thermal Resistance

Note

2. For the measurement point of case temperature (Tc), please refer to Fig. 4.

Electrical Characteristics

Inverter Part

(Tj = 25°C, Unless Otherwise Specified)

Note

3. tON and t

OFF

include the propagation del ay time of th e internal drive IC. t

C(ON)

and t

C(OFF)

are the switching time o f IGBT itself u nder the given gate drivin g condition

internally. For the detailed information, please see Fig. 5.

Item Symbol Condition Min. Typ. Max. Unit

Junction to Case Thermal
Resistance

R

th(j-c)Q

Each IGBT under Inverter Operating Condition
(Note 2)

- - 2.89 °C/W

R

th(j-c)F

Each FWDi under Inverter Operating Condition
(Note 2)

- - 3.73 °C/W

Contact Thermal
Resistance

R

th(c-f)

Ceramic Substrate (per 1 Module)
Thermal Grease Applied

- - 0.06 °C/W

Item Symbol Condition Min. Typ. Max. Unit

Collector - Emitter
Saturation Voltage

V

CE(SAT)VCC

= VBS = 15V

V

IN

= 0V

I

C

= 10A, Tj = 25°C - - 2.8 V

I

C

= 10A, Tj = 125°C - - 2.9 V

FWDi Forward Voltage V

FMVIN

= 5V IC = 10A, Tj = 25°C - - 2.3 V

I

C

= 10A, Tj = 125°C - - 2.1 V

Switching Times t

ON

VPN = 300V, VCC = VBS = 15V
I

C

= 10A, Tj = 25°C

V

IN

= 5V ↔ 0V, Inductive Load

(High-Low Side)
(Note 3)

-0.37- µs

t

C(ON)

-0.12- µs

t

OFF

-0.53- µs

t

C(OFF)

-0.2-µs

t

rr

-0.1-µs

Collector - Emitter
Leakage Current

I

CESVCE

= V

CES

, Tj = 25°C - - 250 µA

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Fig 5. Switching Time Definition

Fig. 6. Experimental Results of Switching Waveforms

Test Condition: Vdc=300V, Vcc=15V, L=500uH (Inductive Load), T

C

=25°°°°C

t

rr

I

C

V

CE

V

IN

t

ON

t

C(ON)

V

IN(ON)

10% I

C

90% I

C

10% V

CE

100% I

C

(a) Turn-on

t

rr

I

C

V

CE

V

IN

t

ON

t

C(ON)

V

IN(ON)

10% I

C

90% I

C

10% V

CE

100% I

C

(a) Turn-on (b) Turn-off

I

C

V

CE

V

IN

t

OFF

t

C(OFF)

10% VCE10% I

C

V

IN(OFF)

(b) Turn-off

I

C

V

CE

V

IN

t

OFF

t

C(OFF)

10% VCE10% I

C

V

IN(OFF)

(a) Turn-o n

V

CE

: 100V/div.

I

C

: 5A/div.

time : 100ns/div.

(b) Turn-off

V

CE

: 100V/div.

I

C

: 5A/div.

time : 100ns/div.

(a) Turn-o n

V

CE

: 100V/div.

I

C

: 5A/div.

time : 100ns/div.

(b) Turn-off

V

CE

: 100V/div.

I

C

: 5A/div.

time : 100ns/div.

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Electrical Characteristics

Control Part

(Tj = 25°C, Unless Otherwise Specified)

Note

4. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be
selected around 56 Ω in order to make the SC trip-level of about 15A.
Please refer to Fig. 7 which shows the current sensing characteristics according to sensing resistor RSC.

5. The fault-out pulse width t

FOD

depends on the capacitance value of C

FOD

according to the following approximate equation : C

FOD

= 18.3 x 10-6 x t

FOD

[F]

Item Symbol Condition Min. Typ. Max. Unit

Control Supply Voltage V

CC

Applied between V

CC(H),VCC(L)

- COM 13.5 15 16.5 V

High-Side Bias Voltage V

BS

Applied between V

B(U)

- V

S(U)

, V

B(V)

- V

S(V)

,

V

B(W)

- V

S(W)

13.5 15 16.5 V

Quiescent V

CC

Supply

Current

I

QCCLVCC

= 15V

IN

(UL, VL, WL)

= 5V

V

CC(L)

- COM

(L)

--26mA

I

QCCHVCC

= 15V

IN

(UH, VH, WH)

= 5V

V

CC(U)

, V

CC(V)

, V

CC(W)

-

COM

(H)

- - 130 uA

Quiescent V

BS

Supply

Current

I

QBSVBS

= 15V

IN

(UH, VH, WH)

= 5V

V

B(U)

- V

S(U)

, V

B(V)

-V

S(V)

,

V

B(W)

- V

S(W)

- - 420 uA

Fault Output Voltage V

FOHVSC

= 0V, VFO Circuit: 4.7kΩ to 5V Pull-up 4.5 - - V

V

FOLVSC

= 1V, VFO Circuit: 4.7kΩ to 5V Pull-up - - 1.1 V

PWM Input Frequency f

PWMTC

≤ 100°C, TJ ≤ 125°C - 15 - kHz

Allowable Input Signal
Blanking Time Considering
Leg Arm-Short

t

dead

-20°C ≤ TC ≤ 100°C 3 - - us

Short Circuit Trip Level V

SC(ref)TJ

= 25°, VCC = 15V (Note 4) 0.45 0.51 0.56 V

Sensing Voltage
of IGBT Current

V

SEN

-20°C ≤ TC ≤ 100°C, @ RSC = 82 Ω and
I

C

= 10A (Note Fig. 7)

0.37 0.45 0.56 V

Supply Circuit Under­Voltage Protection

UV

CCDTJ

≤ 125°C Detection Level 11.5 12 12.5 V

UV

CCR

Reset Level 12 12.5 13 V

UV

BSD

Detection Level 7.3 9.0 10.8 V

UV

BSR

Reset Level 8.6 10.3 12 V

Fault-Out Pulse Width t

FODVCC

= 15V, C(sc) = 1V

C

FOD

= 33nF (Note 5)

1.4 1.8 2.0 ms

ON Threshold Voltage V

IN(ON)

High-Side Applied between IN

(UH)

, IN

(VH)

,

IN

(WH)

- COM

(H)

--0.8V

OFF Threshold Voltage V

IN(OFF)

3.0 - - V

ON Threshold Voltage V

IN(ON)

Low-Side Applied between IN

(UL)

, IN

(VL)

,

IN

(WL)

- COM

(L)

--0.8V

OFF Threshold Voltage V

IN(OFF)

3.0 - - V

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Fig. 7. Relationship between Sensing Resistor and SC Trip Current
for Short-Circuit Protection
(I

SC

= 82

××××

Rating Current(10A) / RSC)

10 20 30 40 50 60 70 80 90

5

10

15

20

25

30

35

40

45

50

55

60

65

SC Trip Current I

SC

[A]

Sensing Resistor RSC [Ω]

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Mechanical Characteris tics and Ratings

Fig. 8. Flatness Measurement Position of The Ceramic Substrate

Note

6. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction.

7. Avoid one side tightening stress. Fig.9 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to

be damaged.

Fig. 9. Mounting Screws Torque Order (1 →→→→ 2 →→→→ 3 →→→→ 4)

Item Condition

Limits

Units

Min. Typ. Max.

Mounting Torque Mounting Screw: M3

(Note 6 and 7)

Recommended 10kg•cm 8 10 12 Kg•cm

Recommended 0.98N•m 0.78 0.98 1.17 N•m
Ceramic Flatness (Note Fig. 8) 0 - +100 um
Weight -56-g

4

1

2222

3

4

1

2222

3

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Recommended Operating Conditions

ICs Internal Structure and Input/Output Conditions

Note

1. One LVIC drives three Sense-IGBTs and can do short-circuit current protection also. Three sense emitters are commonly connected to RSC terminal to detect
short-circuit current. Low-side part of the inverter consists of three sense-IGBTs

2. One HVIC drives one normal-IGBT. High-side part of the inverter consists of three normal-IGBTs

3. Each IC has under voltage detection and protection function.

4. The logic input is compatible with standard CMOS or LSTTL outputs.

5. RPCP coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each
SPM gating input pin.

6. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.

Fig. 10.

Item Symbol Condition

Value

Unit

Min. Typ. Max.

Supply Voltage V

PN

Applied between P - N - 300 400 V

Control Supply Voltage V

CC

Applied between V

CC(H)

- COM

(H)

,

V

CC(L)

- COM

(L)

13.5 15 16.5 V

High-Side Bias Voltage V

BS

Applied between V

B(U)

- V

S(U)

, V

B(V)

- V

S(V)

,

V

B(W)

- V

S(W)

13.5 15 16.5 V

Blanking Time for Preventing
Arm-short

t

dead

For Each Input Signal 3 - - us

PWM Input Signal f

PWMTC

≤ 100°C, TJ ≤ 125°C - 15 - kHz

Input ON Threshold Voltage V

IN(ON)

Applied between UIN,VIN, WIN - COM 0 ~ 0.65 V

Input OFF Threshold Voltage V

IN(OFF)

Applied between UIN,VIN, WIN - COM 4 ~ 5.5 V

LEVEL
SHIFT

HVIC

HVICHVIC

HVIC

UV

DETECT

PULSE
FILTER

R
R
S Q

IN

ININ

IN

(UH,VH,WH)

(UH,VH,WH)(UH,VH,WH)

(UH,VH,WH)

COM

COMCOM

COM

VS

VSVS

VS

(UH,VH,WH)

(UH,VH,WH)(UH,VH,WH)

(UH,VH,WH)

VCC

VCCVCC

VCC

(UH,VH,WH)

(UH,VH,WH)(UH,VH,WH)

(UH,VH,WH)

15V Line

15V Line15V Line

15V Line

UV

PROTECTION

SC

PROTECTION

TIME

DELAY

SC

LATCH_UP

IN

ININ

IN

(UL,VL,WL)

(UL,VL,WL)(UL,VL,WL)

(UL,VL,WL)

PULSE

GENERATOR

(HYSTERISIS)

BUFFER

OUTPUT

(UL,VL,WL)

SOFT_OFF
CONTROL

VCC

VCCVCC

VCC

(L)

(L)(L)

(L)

UV

DETECT

TIME

DELAY

BANDGAP

REFERENCE

FAULT OUTPUT

DURATION

VVVV

FO

FOFO

FO

UV

LATCH_UP

CCCC

FOD

FODFOD

FOD

SC

DETECTION

LVIC

LVICLVIC

LVIC

PPPP

VB

VBVB

VB

(UH,VH,WH)

(UH,VH,WH)(UH,VH,WH)

(UH,VH,WH)

5V Line

5V Line5V Line

5V Line

5V Line

5V Line5V Line

5V Line

R

P

C

PL

C

FOD

R

P

C

PH

NNNN

C

BSC

D

BS

R

BS

R

SC

C

SC

R

F

PULSE

GENERATOR

R

PF

C

PF

C

BP15

C

BS

U,V,W

U,V,WU,V,W

U,V,W

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Time Charts of SPMs Protective Function

P1 : Normal operation - IGBT ON and conducting current
P2 : Under voltage detection
P3 : IGBT gate interrupt
P4 : Fault signal generation
P5 : Under voltage reset
P6 : Normal operation - IGBT ON and conducting current

Fig. 11. Under-Voltage Protection (Low-side)

P1 : Normal operation - IGBT ON and conducting current
P2 : Under voltage detection
P3 : IGBT gate interrupt
P4 : No fault signal
P5 : Under voltage reset
P6 : Normal operation - IGBT ON and conducting current

Fig. 12. Under-Voltage Protection (High-side)

Internal IGBT

Gate-Emitter Voltage

Input Signal

Output Current

Fault Output Signal

Control Supply Voltage

P1

P2

P3

P4

P6

P5

UV

detect

UV

reset

Internal IGBT

Gate-Emitter Voltage

Input Signal

Output Current

Fault Output Signal

Control Supply Voltage

V

BS

P1

P2

P3

P4

P6

P5

UV

detect

UV

reset

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

P1 : Normal operation - IGBT ON and conducting currents
P2 : Short-circuit current detection
P3 : IGBT gate interrupt / Fault signal generation
P4 : IGBT is slowly turned off
P5 : IGBT OFF signal
P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation
P7 : IGBT OFF sta te
P8 : Fault-output reset and normal operation start

Fig. 13. Short-circuit Current Protection (Low-side Operation only)

Note

It would be recommended that by-pass capacitors for the gating input signals, IN

(XX)

should be placed on the SPM pins and on the both sides of CPU and SPM

for the fault output signal, VFO, as close as possible.

Fig. 14. Recommended CPU I/O Interface Circuit

Internal IGBT

Gate-Emitter Voltage

Input Signal

Output Current

Sensing Voltage

Fault Output Signal

P1

P2

P3

P4

P6

P5

P7

P8

SC Reference
Voltage (0.5V)

RC Filter Delay

SC Detection

CPU

COM

5V-Line

1.2nF0.47nF1nF

Ω

4.7k

Ω

4.7k

Ω

4.7k

,,

IN

(UL)IN(VL)

IN

(WL)

,,

IN

(UH)IN(VH)

IN

(WH)

V

FO

FPBL10SH60

Ω

100

Ω

100

Ω

100

1nF

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Fig. 15. Recommended Bootstrap Operation Circuit and Parameters

One-leg Diagram of FPBL10SH60

P

N

Inverter
Output

Vcc
IN
COM

VB
HO
VS

Vcc
IN
COM

OUT

15V-Line

20Ω

1000uF

0.1uF

220uF

0.1uF

One-leg Diagram of FPBL10SH60

P

N

Inverter
Output

Vcc
IN
COM

VB
HO
VS

Vcc
IN
COM

OUT

15V-Line

20Ω

1000uF

0.1uF

220uF

0.1uF

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Note

1. RPCPL/RPCPH coupling at each SPM input is recommended in order to prevent input signals’ oscillation and it should be as close as possible to each SPM input
pin.

2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is
possible.

3. VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7kΩ resistance. Please
refer to Fig. 14.

4. C

SP15

of around 7 times larger than bootstrap capacitor CBS is recommended.

5. VFO output pulse width should be determined by connecting an external capacitor(C

FOD

) between C

FOD

(pin7) and COM

(L)

(pin2). (Example : if C

FOD

= 5.6 nF,

then tFO = 300 µs (typ.)) Please refer to the note 5 for calculation method.

6. Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ resistance (other RC coupling circuits at each input may be needed
depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board). Approximately a 0.22~2nF by-pass capacitor
should be used across each power supply connection terminals.

7. To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible.

8. In the short-circuit protection circui t, plea se select th e RFCSC time constant in the range 3~4 µs. RF should be at least 30 times larger than RSC. (Recommended
Example: RSC = 56 Ω, RF = 3.9kΩ and CSC = 1nF)

9. Each capacitor should be mounted as close to the pins of the SPM as possible.

10.To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high frequency non­inductive capacitor of around 0.1~0.22 uF between the P&N pins is recommended.

11. Relays are used at almost every syste ms of electr ical equ ipmen ts of home app liances. In the se cases, there should be sufficient distance between the CPU and
the relays. It is recommended that the distance be 5cm at least

Fig. 16. Application Circuit

M

15V line

5V line

5V line

CPU

Gating UH

Gating VH

Gating WH

Gating UL

Gating VL

Gating WL

Fault

Vdc

RBSD

BS

C

BS

C

PH

R

P

C

PL

R

P

C

FOD

C

SC

R

F

R

SC

C

SP15

C

BPF

R

S

C

SPC15

C

BSC

CBSC

BSC

CBSC

BSC

RBSD

BS

RBSD

BS

RPR

P

CPHC

PH

RSR

S

RSRSRSR

S

C

DCS

RPRPR

P

C

PL

C

PL

C

PF

WV U N

(14) (15) (16) (17) P

(1) V

CC(L)

(2) COM

(L)

(3) IN

(UL)

(4) IN

(VL)

(5) IN

(WL)

(6) V

FO

(7) C

FOD

(8) C

SC

(12) NC

(11) NC

(13)

V

B(U)

(29)

COM

(H)

(22)

IN

(UH)

(27)

V

S(U)

(30)

V

CC(UH)

(28)

V

B(V)

(25)

IN

(VH)

(23)

V

CC(VH)

(24)

V

S(V)

(26)

V

B(W)

(20)

IN

(WH)

(18)

V

CC(WH)

(19)

V

S(W)

(21)

(10) NC

(9) R

SC

V

CC

Wout

Uout

Vout

C

(SC)

C

(FOD)

V

(FO)

IN

(WL)

IN

(VL)

IN

(UL)

COM

(L)

Vcc

IN

COM

VB
HO
VS

Vcc

IN

COM

VB
HO
VS

Vcc

IN

COM

VB
HO
VS

+-

©2002 Fairchild Semiconductor Corporation

FPBL10SH60

Rev. B1, February 2002

Detailed Package Outline Drawin gs

ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E

2

CMOS™
EnSigna™
FACT™
FACT Quiet Series™

FAST

®

FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™

OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench

®

QFET™
QS™
QT Optoelectronics™
Quiet Series™
SLIENT SWITCHER

®

SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TruTranslation™
TinyLogic™
UHC™
UltraFET

®

VCX™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:

©2002 Fairchild Semiconductor Corporation Rev. H4

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

STAR*POWER is used under license