Datasheet FDMC86102LZ Datasheet (Fairchild)

FDMC86102LZ

G

S

S

S

D
D

D

D

Bottom

D

D

D

D

S

S

S

G

Top

Pin 1

MLP 3.3x3.3

5

6

7

8

4

3

2

1

N-Channel Power Trench® MOSFET

100 V, 22 A, 24 mΩ

Features

 Max r
 Max r
 HBM ESD protection level > 6 KV typical (Note 4)

 100% UIL Tested
 RoHS Compliant

= 24 mΩ at VGS = 10 V, ID = 6.5 A

DS(on)

= 35 mΩ at VGS = 4.5 V, ID = 5.5 A

DS(on)

General Description

This N-Channel logic Level MOSFETs are produced using
Fairchild Semiconductor‘s advanced Power Trench
that has been special tailored to minimize the on-state
resistance and yet maintain superior switching performance.
G-S zener has been added to enhance ESD voltage level.

Application

 DC - DC Switching

April 2011

®

process

FDMC86102LZ N-Channel Power Trench

®

MOSFET

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DS

V

GS

I

D

E

AS

P

D

, T

T

J

STG

Drain to Source Voltage 100 V
Gate to Source Voltage ±20 V
Drain Current -Continuous (Package limited) TC = 25 °C 22

-Continuous (Silicon limited) T

-Continuous T

-Pulsed 30
Single Pulse Avalanche Energy (Note 3) 84 mJ
Power Dissipation TC = 25 °C 41
Power Dissipation T
Operating and Storage Junction Temperature Range -55 to +150 °C

= 25 °C unless otherwise noted

A

= 25 °C 29

C

= 25 °C (Note 1a) 7

A

= 25 °C (Note 1a) 2.3

A

A

W

Thermal Characteristics

R

θJC

R

θJA

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDMC86102Z FDMC86102LZ Power 33 13 ’’ 12 mm 3000 units

©2011 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FDMC86102LZ Rev. C

Thermal Resistance, Junction to Case 3
Thermal Resistance, Junction to Ambient (Note 1a) 53

°C/W

FDMC86102LZ N-Channel Power Trench

Electrical Characteristics T

= 25 °C unless otherwise noted

J

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

BV

ΔBV
ΔT

I

DSS

I

GSS

DSS

DSS
J

Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 V
Breakdown Voltage Temperature

Coefficient
Zero Gate Voltage Drain Current VDS = 80 V, V
Gate to Source Leakage Current VGS = ±20 V, V

I

= 250 μA, referenced to 25 °C 71 mV/°C

D

= 0 V 1 μA

GS

= 0 V ±10 μA

DS

On Characteristics

V

GS(th)

ΔV
ΔT

r

DS(on)

g

FS

GS(th)

J

Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 1.0 1.6 2.2 V
Gate to Source Threshold Voltage

Temperature Coefficient

Static Drain to Source On Resistance

I

= 250 μA, referenced to 25 °C -6 mV/°C

D

V

= 10 V, ID = 6.5 A 19 24

GS

= 4.5 V, ID = 5.5 A 25 35

GS

= 10 V , ID = 6.5 A, TJ = 125 °C 31 40

V

GS

Forward Transconductance VDS = 5 V, ID = 6.5 A 24 S

Dynamic Characteristics

C

iss

C

oss

C

rss

R

g

Input Capacitance
Output Capacitance 181 240 pF
Reverse Transfer Capacitance 9 15 pF

= 50 V, VGS = 0 V,

V

DS

f = 1 MHz

Gate Resistance 0.4 Ω

969 1290 pF

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q
Q
Q
Q

g(TOT)
g(TOT)
gs
gd

Turn-On Delay Time
Rise Time 2.3 10 ns
Turn-Off Delay Time 19 35 ns

= 50 V, ID = 6.5 A,

V

DD

V

= 10 V, R

GS

GEN

= 6 Ω

Fall Time 2.5 10 ns
Total Gate Charge V
Total Gate Charge V
Total Gate Charge 2.4 nC

= 0 V to 10 V

GS

= 0 V to 4.5 V 7.6 11 nC

GS

VDD = 50 V,
I

= 6.5 A

D

Gate to Drain “Miller” Charge 2.5 nC

7.1 15 ns

15.3 22 nC

mΩV

®

MOSFET

Drain-Source Diode Characteristics

V

= 0 V, IS = 6.5 A (Note 2) 0.80 1.3

V

SD

t

rr

Q

rr

NOTES:

1. R

is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. boar d of FR-4 ma terial . R

θJA

the user's board design.

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.

3. Starting T

4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied.

©2011 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com
FDMC86102LZ Rev. C

Source to Drain Diode Forward Voltage
Reverse Recovery Time

Reverse Recovery Charge 40 64 nC

a.

53 °C/W when mounted on a

2

pad of 2 oz copper

1 in

= 25 °C; N-ch: L = 1 mH, IAS = 13 A, VDD = 90 V, VGS = 10 V.

J

GS

= 0 V, IS = 2 A (Note 2) 0.72 1.2

V

GS

= 6.5 A, di/dt = 100 A/μs

I

F

θJC

42 67 ns

is guaranteed by design while R

125 °C/W when mounted on

b.

a minimum pad of 2 oz copper

is determined by

θCA

V

FDMC86102LZ N-Channel Power Trench

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0

5

10

15

20

25

30

VGS = 3.5 V

VGS = 2.5 V

PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX

VGS = 3 V

VGS = 4.5 V

VGS = 10 V

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

0 5 10 15 20 25 30

0

1

2

3

4

5

6

7

8

V

GS

= 3 V

VGS = 2.5 V

PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTA NCE

I

D

, DRAIN CURRENT (A)

V

GS

= 4.5 V

VGS = 3.5 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

ID = 6.5 A
V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESIST ANCE

T

J

, JUNCTION TEMPERATURE (

o

C)

246810

0

20

40

60

80

100

TJ = 125 oC

ID = 6.5 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VOLTA GE (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX

1.0 1.5 2.0 2.5 3.0 3.5 4.0

0

5

10

15

20

25

30

TJ = 150 oC

V

DS

= 5 V

PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

30

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics T

Figure 1.

On-Region Characteristics Figure 2.

= 25 °C unless otherwise noted

J

Norma l i z e d O n - Resistance

vs Drain Current and Gate Voltage

®

MOSFET

Fig u r e 3. Norm a l ized O n - Resist a n c e

vs Junction Temperature

©2011 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com
FDMC86102LZ Rev. C

Figure 5. Transfer Characteristics

Figure 4.

On-Resis tance vs Gate to

Source Voltage

Figure 6.

Source to Drain Diode

Forward Voltage vs Source Current

FDMC86102LZ N-Channel Power Trench

0 4 8 12 16

0

2

4

6

8

10

ID = 6.5 A

VDD = 50 V

V

DD

= 25 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 75 V

0.1 1 10 100

1

10

100

1000

5000

f = 1 MHz
V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

0.001 0.01 0.1 1 10 20

1

10

50

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

5

10

15

20

25

30

Limited by Package

V

GS

= 4.5 V

R

θJC

= 3.0 oC/W

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

C

, CASE TEMPERATURE (

o

C)

0 4 8 121620242832

10

-9

10

-8

10

-7

10

-6

10

-5

10

-4

10

-3

10

-2

10

-1

V

DS

= 0 V

TJ = 25 oC

TJ = 125 oC

V

GS

,

GATE TO SOURCE VOLTAGE (V)

I

g

, GATE LEAKAGE CURRENT (A)

0.01 0.1 1 10 100 500

0.005

0.01

0.1

1

10

50

10 s

100 us

10 ms

DC

1 s

100 ms

1 ms

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AR E A IS
LIMITED BY r

DS(on)

SINGLE PULSE
T

J

= MAX RATED

R

θJA

= 125

o

C/W

T

A

= 25

o

C

Typical Characteristics T

Figure 7.

Gate Charge Characteristics Figure 8.

= 25 °C unless otherwise noted

J

Capacitance vs Drain

to Source Voltage

®

MOSFET

Figure 9.

Unc l a m p e d I ndu c t i v e

Switching Capability

©2011 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com
FDMC86102LZ Rev. C

Fig ure 11. G ate L eak age C urre nt vs

Gate to Source Voltage

Figure 10.

Ma xim um C ont inu ous Dra in

Current vs Case Temperature

Figure 12.

Forward Bias Safe

Operating Area

FDMC86102LZ N-Channel Power Trench

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.5

1

10

100

1000

2000

P

(PK)

, PEAK TRANSIENT POWER (W)

SINGLE PULSE
R

θJA

= 125 oC/W

T

A

= 25 oC

t, PULSE WIDTH (sec)

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.0005

0.001

0.01

0.1

1

2

SINGLE PULSE
R

θJA

= 125 oC/W

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t1/t

2

PEAK TJ = PDM x Z

θJA

x R

θJA

+ T

A

Typical Characteristics T

Figure 13. Single Pulse Maximum Power Dissipation

= 25 °C unless otherwise noted

J

®

MOSFET

Figure 14.

©2011 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com
FDMC86102LZ Rev. C

Junction-to-Ambient Transient Thermal Response Curve

Dimensional Outline and Pad Layout

B . D IMENSIONS ARE IN MILLIM ETERS.
C. DIME NSIONS AND TO LERANCES PER

A. DOE S NOT CO NFO RM TO JED EC

REGIS T RATION MO- 2 29

ASME Y14.5 M, 1994

0.10 CAB

0.05

C

TOP VIEW

BOT TO M VIEW

RE COM M ENDED L AND PA T T ERN

0.10 C

0.08 C

B

A

3.30

3.30

0.05

0.00

0.10 C

2X

2X

0.8 MAX

S ID E VIEW

SEATING

PLANE

0.10 C

PIN #1 IDENT

(0.20)

8

5

1.95

0.65

E. DR AWING FILE NAME : MLP08Srev1

PIN#1 QUADRANT

0.40

0.30

41

(8X)

D. L AND PATT ERN REC O MM ENDATION IS

BASED ON FSC DESIGN ONLY

2.32

2.22

0.55

0.45

(4X)

1.15

0.30

2.05

1.95

0.35

R0.15

0.79

FDMC86102LZ N-Channel Power Trench

®

MOSFET

©2011 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com
FDMC86102LZ Rev. C

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tm

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The following includes registered and unregistered tradema rks and service marks, owned by Fair child Semiconductor and/ or its global subsidiaries, and is no t
intended to be an exhaustive list of all such trademarks.

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QS™
Quiet Series™
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Saving our world, 1mW/W/kW at a time™
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PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.

Datasheet contains preliminary data; supplement ary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.

Datasheet contains final specifications. Fairchild Semiconduct or reserves the right to
make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fai r child
Semiconductor. The datashe et is for reference information only.

Rev. I54