RF PC Cards
Pocket PC and PDAs with Communication
Capabilities
Description
The FAN5902 is a high-efficiency, low-noise,
synchronous, step-down DC-to-DC converter designed
for powering the radio frequency power amplifiers
(RFPA) in 3G mobile handsets and other mobile
applications. It provides up to 800mA of output current
over an input voltage range of 2.7V to 5.5V. The output
voltage can be dynamically adjusted from 0.4V up to
3.4V, proportional to an analog input voltage ranging
from 0.2V to 1.7V provided by an external DAC. This
allows supplying the RFPA with the voltage level that
provides optimum Power Added Efficiency (PAE).
An integrated bypass FET automatically switches on
when the battery voltage drops too close to the output
voltage (when V
transition is controlled by a slew rate controller to limit
the inrush current and reduce the RFPA gain deviation.
The FAN5902 offers fast transition times, allowing
changes to the output voltage in less than 20µs.
The FAN5902 operates at 6MHz, enabling the use of a
small, low-value inductor of 470nH. A current-mode
control loop with fast transient response ensures
excellent line and load regulation.
The FAN5902 improves the RFPA power efficiency and
increases the talk/connection time in 3G handsets.
The FAN5902 is available in a 12-lead MLP package
and 12-bump WLCSP.
OUT=VBAT
-250mV). The bypass
Important
For complete performance specifications and
datasheet, please contact a Fairchild Semiconductor
sales representative.
Ordering Information
Part Number
FAN5902MPX -40 to +85°C
FAN5902UCX -40 to +85°C
For Fairchild’s definition of Eco Status, please vis it: http://www.fairchildsemi.com/company/green/rohs_green.html.
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VIN
TJ Junction Temperature -40 +125 °C
T
STG
TL Lead Soldering Temperature (10 Seconds) +260 °C
θJC Thermal Resistance, Junction to Tab
θJC Thermal Resistance, Junction to Case
1. Refer to θJA data below.
AVIN, PVIN -0.3 6.0
Voltage On Any Other Pin -0.3 AV
IN
+0.3
V
Storage Temperature -65 +150 °C
(1)
MLP Package 5 °C/W
(1)
WLCSP Package 30 °C/W
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Min. Typ. Max. Unit
VCC
V
OUT
I
OUT
CIN
C
OUT
TA
TJ
Notes:
2. A high input capacitor value is required for limiting input voltage drop during bypass transitions or during large
3. Refer to application note AN-6087 for more details.
Dissipation Ratings
Molded Leadless Package (MLP) 49ºC/W
Wafer-Level Chip-Scale Package (WLCSP) 110ºC/W
Notes:
4. Thermal Resistance, Junction-to-Ambient, measured according to JEDEC 2S2P PCB (and zero air flow). θJA for
5. Maximum power dissipation is a function of T
Supply Voltage Range 2.7 5.5 V
Output Voltage Range 0.4 V
Output Current 20 800 mA
L
Inductor 0.47 µH
Input Capacitor
Output Capacitor
(2)
10 µF
(2)
2.2 4.7 10.0 µF
V
IN
Operating Ambient Temperature Range -40 +85 °C
Operating Junction Temperature Range -40 +125 °C
output voltage transitions. Ensure the input capacitor value is greater than the output capacitor’s. See the inrush current specifications below.
(4)
Package θ
(4)
JA
(5)
2050mW 21mW/ºC
(5)
900mW 9mW/ºC
Power Rating
at T
≤ 25°C
A
(5)
Derating Factor
> TA=25ºC
JEDEC 1S0P PCB (and zero air flow) = 210°C/W.
, θJA, and TA. The maximum allowable power dissipation at any
NOTES:
A. CONFORMS TO JEDEC MO-229
VARIATION WFED-2.
B. DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS
BASED ON IPC 7351 DESIGN GUIDELINES
E. LANDPATTERN EXTENSION TO INCLUDE
CENTER PAD TABS IS OPTIONAL
F. FILENAME AND REV: MKT-MLP12DREV1
Figure 9: 3x3.5mm 12-Lead MLP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Pl ease note the revision and/or date on t he drawing and contact a Fairchild Semiconductor representative t o verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
DATUM C, THE SEATING PLANE, IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
F
FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
F. BALL COMPOSITION: Sn95.5Ag3.9Cu0.6
SAC405 ALLOY
(Y)+/-.018
0.50
12
BOTTOM VIEW
D
C
B
A
3
G. DRAWING FILENAME: MKT-UC012AArev2
Figure 10. 12-Bump WLCSP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Pl ease note the revision and/or date on t he drawing and contact a Fairchild Semiconductor representative t o verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: