The EM84502 Mouse Controller is specially designed to control PS/2 mouse device.This single chip can
interface three key-switches and four photo-couples direct to 8042. EM84502 can receive command and echo
status or data format which are compatible with IBM PS/2 mode mouse. Key debouncing circuit is provided
to prevent false entry and improve the accuracy.
In the conventional mouse, a great number of noises are generated when the grid is partially closed or opened.
These noise are usually mistaken for movement signals by conventional mouse controller and the cursor of the
dispaly screen is thus moved frequently up and down or back and forth. This will consumes a great amount of
energy.The EM84502 PS/2 mouse controller provides noise immunity circuits to eliminate these noise
in order to reduce energy consumption.
FEATURES
• Being compatiable with PS/2 mouse mode.
• Built-in noise immunity circuit.
• Low power dissipation.
• RC oscillation.
• Three key-switches and four photo-couples inputs.
• Both key-press and key-release debounce interval 12 ms.
• Through three key-switches input, EM84502 can exert seven different output.
• The motion detector of the EM84502 could sense 8 m/sec maximun with 200 DPI wheels.
EM84502
PS/2 MOUSE CONTROLLER
PS/2 MOUSE CONTROLLER
EM84502
APPLICATIONS
• Optical mouse or pen-mouse.
• Mechanical mouse or pen-mouse.
• Optomechanical mouse or pen-mouse.
• Mechanical track ball.
• Optomechanical track ball.
PIN ASSIGNMENT
EM84502AP
V
DD
OP
OSC.OUT
CLK
DATA
VSS
R
EM84502BP
V
DD
OP
NC
NC
OSC.OUT
CLK
DATA
VSS
EM84502AM
1
2
3
4
5
6
7
OSCR
14
Y2
13
Y1
12
X2
11
X1
10
L
9
M
8
V
OSC.OUT
CLK
DATA
VSS
OP
DD
1
2
3
4
5
6
7
R
OSCR
14
Y2
13
Y1
12
X2
11
X1
10
L
9
M
8
EM84502BM*
1
16
2
3
4
5
6
7
8
OSCR
15
Y2
14
Y1
13
X2
12
X1
11
L
10
M
9
R
V
OP
NC
NC
OSC.OUT
CLK
DATA
VSS
DD
1
16
2
3
4
5
6
7
8
OSCR
15
Y2
14
Y1
13
X2
12
X1
11
L
10
M
9
R
* (Under developed)
* This specification are subject to be changed without notice.
8.3.2001
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FUNCTIONAL BLOCK DIAGRAM
T
OP
D
X1
X2
Y1
Y2
L
M
R
OSCR
OSC OU
I
E
M
M
N
T
M
O
O
E
U
T
I
C
N
I
S
T
IT
O
E
O
Y
N
R
D
E
B
O
U
N
C
E
COUNTER
TIMING
CONTROLLER
SYSTEM
CLOCK
GENERATOR
D
A
T
A
PIN DESCRIPTIONS
Symbol I/OFunction
C
O
N
V
E
R
T
E
R
DATA
PS/2 MOUSE CONTROLLER
EM84502
D
C
E
O
C
M
O
M
D
A
E
N
R
D
I/O
DATA
CLK
V
DD
Power
OPIX, Y inputs.
Floating : Comparator input.
GND : Schmitt trigger input.
Short to OSC OUT : Testing Mode.
OSCOUTOClock output.
CLKI/O8042 auxiliary port CLK line.
DATAI/O8042 auxiliary port DATA line.
V
SS
Ground
RIThree key-switches exert seven different combinations totally. Both key-pressed
Mand key-released signals will be sent accomplanied with horizontal and vertical
Lstate. The status of the key-switches will be preserved, whenever the value of
horizontal or vertical counters will present at DATA. And the debounce interval
for both key-press and key-release is 12 ms.
X1IFour photo-couple signals denote UP, DOWN, LEFT, and RIGHT state.
X2During the scaning period, as long as the photo-couples change their states, the
Y1value of vertical or horizontal counter will increase or decrease accordingly.
Y2
OSCRI30 Kohm ±5% pull low for 35 KHz oscillation.
FUNCTION DESCRIPTIONS
A) Operating mode
There are four operating modes in PS/2 mouse:
i). Reset Mode:
In this mode a self-test is initiated during power-on or by a Reset command. After reset signal, PS/2
mouse will send:
1). Completion code AA & ID code 00.
* This specification are subject to be changed without notice.
7Y data overflow; 1 = overflow
20-7X data ( D0 - D7 )
30-7Y data ( D0 - D7 )
C) PS/2 mouse Data Transmission:
i). EM84502 generates the clocking signal when sending data to and receiving data from the system.
ii). The system requests EM84502 receive system data output by forcing the DATA line to an inactive
level and allowing CLK line to go to an active level.
iii). Data transmission frame:
* This specification are subject to be changed without notice.
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PS/2 MOUSE CONTROLLER
BitFunction
1Start bit ( always 0 )
2-9Data bits ( D0 - D7 )
10Parity bit ( odd parity )
11Stop bit ( always 1 )
iv). Data Output ( data from EM84502 to system ):
If CLK is low ( inhibit status ) , data is no transmission.
If CLK is high and DATA is low ( request-to-send ), data is updated. Data is received from the system
and no transmission are started by EM84502 until CLK and DATA both high. If CLK and DATA are both
high, the transmission is ready. DATA is valid prior to the falling edge of CLK and beyond the rising edge
of CLK. During transmission, EM84502 check for line contention by checking for an inactive level on CLK
at intervals not to exceed 100u sec. Contention occurs when the system lowers CLK to inhibit EM84502
output after EM84502 has started a transmission. If this occurs before the rising edge of the tenth clock,
EM84502 internal store its data in its buffer and returns DATA and CLK to an active level. If the contention
does not occur by the tenth clock, the transmission is complete.
Following a transmission, the system inhibits EM84502 by holding CLK low until it can service the input
or until the system receives a request to send a response from EM84502.
EM84502
v). Data Input ( from system to EM84502 ):
System first check if EM84502 is transmitting data. If EM84502 is transmitting, the system can override
the output forcing CLK to an inactive level prior to the tenth clock. If EM84502 transmission is beyond
the tenth clock, the system receives the data. If EM84502 is not transmitting or if the system choose to
override the output, the system force CLK to an inactive level for a period of not less than 100µ sec while
preparing for output. When the system is ready to output start bit (0), it allows CLK go to active level. If
request-to-send is detected, EM84502 clocks 11 bits. Following the tenth clock EM84502 checks for
an active level on the DATA line, and if found, force DATA low , and clock once more. If occurs framing
error, EM84502 continue to clock until DATA is high, then clocks the line control bit and request a
Resend. When the system sends out a command or data transmission that requires a response, the system
waits for EM84502 to response before sending its next output.
D). PS/2 Mouse Error Handling:
i).A Resend command ( FE ) following receipt of an invalid input or any input with incorrect parity.
ii). If two invalid input are received in succession, an error code of hex FC send to the system.
iii). The counter accumulators are cleared after receiving any command except “Resend”.
iv). EM84501 receives a Resend command ( FE ), it transmit its last packet of data.
v). In the stream mode “Resend” is received by EM84502 following a 3-byte data packet transmission
to the system. EM84502 resend the 3-byte data packet prior to clearing the counter.
vi). A response is sent within 25 ms if
* This specification are subject to be changed without notice.
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PS/2 MOUSE CONTROLLER
a). The system requires a response
b).An error is detected in the transmission
vii). When a command requiring a response is issued by the system ,another command should not be issue
until either the response is received or 25ms has passed.
E). PS/2 Mouse Commands Description:
There are 16 valid commands that transmits between the system and EM84502. The “FA” code is always the
first response to any valid input received from the system other than a Set Wrap Mode or Resend command.
The following table list the commands:
i). Any time EM84502 receives an invalid command, it returns a Resend command to the system.
ii). When EM84502 receives a Resend command, it retransmits its last packet of data. If the last packet was
a Resend command, it transmits the packet just prior to the Resend command.
iii). In stream mode, if a Resend command is received by EM84502 immediately following a 3-byte data
packet transmission to the system.
* This specification are subject to be changed without notice.
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PS/2 MOUSE CONTROLLER
c). Set Default ( F6 )
The command reinitializes all conditions to the power-on defaults.
d). Disable ( F5 )
This command is used in the stream mode to stop transmissions from EM84502.
e). Enable ( F4 )
Begins transmissions, if in stream mode.
f). Set Sampling Rate ( F3,XX )
In the stream mode, this command sets the sampling rate to the value indicated by byte hex XX,
shown in following:
Second byte XXSample Rate
0A10/sec
1420/sec
2840/sec
3C60/sec
5080/sec
64100/sec
C8200/sec
EM84502
g). Read Device Type ( F2 )
EM84502 always echoes “ FA,00 “ following this command.
h). Set Remote Mode ( F0 )
Data value are reported only in response to a Read Data command.
i). Set Wrap Mode ( EE )
Wrap mode remains until Reset ( FF ) or Reset Wrap Mode( EC ) is received.
j). Reset Wrap Mode ( EC )
EM84502 returns to the previous mode of operation after receiving this command.
k). Read Data ( EB )
This command is executed in either remote or stream mode. The data is transmitted even if there has been
no movement since the last report or the button status is unchanged. Following a Read Data command,
the registers are cleared after a data transmission.
l). Set Stream Mode ( EA )
This command sets EM84502 in stream mode.
m). Status Request ( E9 )
When this command is issued by the system, EM84502 respond with a 3-byte status report as follows:
ByteBitDescription
101 = Right button pressed
11 = Middle button pressed
21 = Left button pressed
* This specification are subject to be changed without notice.
EM84502 provides four resolutions selected by the second byte of this command as follows:
Second Byte XXResolution
008 dot/count
014 dot/count
022 dot/count
031 dot/count
EM84502
o). Set Autospeed ( E7 )
At the end of a sample interval in the stream mode, the current X and Y data values are converted new values.
The sign bits are not involved in this conversion. The conversion is only in stream mode. The relationship
between the input and output count follows:
InputOuput
00
11
21
33
46
59
N(≥6 )2.0*N
p).Reset Autospeed ( E6 )
This command restore normal speed.
F) Testing mode
Whenever OPT is connected to OSC OUT, the chip will enter buyer's testing mode. The X direction output
signals of comparators will present to L and M pin. Pressing "R" key can toggle the output from X direction
to Y direction.
ABSOLUTE MAXIMUM RATINGS
ParameterSym.RatingsUnit
Temperature under biasT
Storage temperature rangeT
Input voltageV
Output voltageV
OPR
STR
IN
O
* This specification are subject to be changed without notice.
Comparator input(500µA)
CLK, DATA postive-goingVt+3.2-3.8V
threshold voltage
CLK, DATA negative-goingVt -1.2-1.9V
threshold voltage
Low input voltage, other pinsVail--1.5V
High input voltage, other pinsVaih3.5--V
L, M, R input currentImi16.6-50µA
(pull low resistor Vin=5V)
PS/2 mouse mode DATA, CLK input CurrentIdc0.56-1.86mA
(pull up resistor)(VIN=0V)
PS/2 mouse mode DATA, CLK low output voltageVprl--0.4V
(Iprl=-2mA)
L, M, R, X1, X2, Y1, Y2 input leakage currentIil0-1.0µA
(Vin=0V)
* All voltages in above table are compared with VSS.
* All parameters in above table are tested under VDD=5V.
* CLK & DATA output gates are open drains that connect to pull up resistors.
* X1, X2,Y1,T2 Input Impedance
MAX.
TYP.
MIN.
16.0K
15.0K
14.0K
13.0K
12.0K
11.0K
10.0.K
9.0K
8.0K
7.0K
6.0K
5.0K
4.0K
3.0K
2.0K
1.0K
0
10.0M
1.0
2.0
VOLTS (LIN)
3.0
* This specification are subject to be changed without notice.
Mouse Sample DATA fromTmdc-14.3-us
CLK rising Edge
System CLK Active TimeTsca-42.9-us
System CLK Inactive TimeTsci-42.9-us
Time from DATA Transition to Falling Edge of CLKTsdc-14.3-us
Time from rising Edge of CLK to DATA TransitionTscd-28.6-us
Time to mouse Inhibit after the 11th CLK toTpi0-50us
ensure mouse does not start another Transmission
EM84502
PS. The AC timings are measured under using 35 KHz system clock signal.
TIMING DIAGRAM
(1) Photo-couples pulse width :
X1 (Y1)
X2 (Y2)
10th
CLK
Tf
11th
CLK
Stop
Bit
(2) PS/2 Mouse
(A) Receiving DATA
CLK
DATA
Inhibit
><
Tmca
><
Tmdc
Start
Bit
Tr
1st
CLK
2nd
CLK
9th
CLK
><
Tmci
• • • • • • • • • • • •• • • • • • •
Bit0 -Bit7
Parity
Bit
•••••
Line
Control
Bit
* This specification are subject to be changed without notice.