Page 1
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
GENERAL DESCRIPTION
EM19100 is an 8-bit CMOS A/D converter for video use. The adoption of a 2-step parallel system achieves low
consumption at a maximum conversion speed of 20 MSPS typical.
FEATURES
• 20MSPS maximum conversion speed
• Build-in sampling and hold circuit
• Internal self-bias reference voltage
• 90mW power dissipation at 20MSPS
• +5V single power supply
• Available in 24 pin SOP
• Series
EM19100M for 300 mil SOP
EM19100S for 209 mil SOP
EM19100
EM19100
APPLICATION
TV,VCR digital systems and a wide range of fields where high speed A/D conversion is required.
PIN ASSIGNMENT
EM19100
DVSS
DVDD
CLK
OE
1
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
11
12
DVSS
24
VRB
23
VRBS
22
AVSS
21
AVSS
20
VIN
19
AVDD
18
VRT
17
VRTS
16
AVDD
15
AVDD
14
DVDD
13
FUNCTIONAL BLOCK DIAGRAM
DVSS
1
/OE
DVSS
2
D0
3
D1
4
Lower data
D2
D3
D4
D5
D6
D7
DVDD
CLK DVDD
latches
5
6
7
8
Upper data
latches
9
10
11
Clock generator
12
Lower encoder
(4bit)
Lower encoder
(4bit)
Upper encoder
(4bit)
Comparators with
Comparators with
Comparators with
Reference voltage
Lower
S/ H (4bit)
Lower
S/ H (4bit)
Upper
S/ H (4bit)
24
VRB
23
VRBS
22
21
AVSS
20
AVSS
VIN
19
AVDD
18
17
VRT
VRTS
16
AVDD
15
14
AVDD
13
* This specification are subject to be changed without notice.
1.26.1996
1
Page 2
OUTPUT CODING
Step Analog Input (V) Digital Output Code Conditions
0 0.607815 00000000 VRB=0.6V
1 0.607815~0.6156250 00000001 VRT=2.6V
2 0.6156250~0.6234375 00000010 1LSB=7.8125mV
.... .... ....
124 1.6000000~1.6078125 10000000
125 1.6078125~1.6156250 10000001
.... .... ....
254 2.5843750~2.5921875 11111110
255 2.5921875~ 11111111
Clock
EM19100
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
Analog input
Data output
N
N-3
ABSOLUTE MAXIMUM RATINGS (T
=25°C)
A
N+1
N-2
N+2
N-1
N+3
N
N+4
N+1
Items Sym. Rating Unit
Supply voltage V
Operating temperature T
Input voltage V
Ref, Input voltage V
DD
OPR
IN
RT,VRB
7V
-20 to +65 °C
V
to V
SS
DD
V
to V
SS
DD
V
V
(FC=20MPS,VDD=5V,VRB=0.5V,VRT=2.5V,Ta=25 deg.)
Parameter Sym. Conditions Min. Typ. Max. Unit
Maximum Conversion Speed F
Supply current I
Reference pin current I
C
DD
REF
Vin=0.6V to 2.6V fin=1kHz ramp 20 MSPS
FC=20MSPS NTSC ramp wave input 12 17 mA
5.7 8.0 9.1 mA
Analog input bandwidth BW 10 MHz
Analog input capacitance C
Reference resistance R
Internal bias V
VRT-V
Offset Voltage E
E
Digital input voltage V
Digital input current I
IN
REF
RB
OT
OB
IH
V
IL
IH
I
IL
VIN=1.5V+0.07Vrms 11 pF
220 250 350 Ω
Short VRB and V
Short VRT and V
RB
RBS
RTS
0.55 0.6 0.65 V
1.9 2.0 2.1
-10 -35 -60 mV
01545
4.0 V
VDD=max. VIH=V
DD
VIL=0V 5
1.0
5uA
* This specification are subject to be changed without notice.
1.26.1996
2
Page 3
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
Parameter Sym. Conditions Min. Typ. Max. Unit
Digital output current I
Digital output current I
OH
I
OL
OZH
OE=VSS,VOH=VDD-0.5V -1.1 mA
VDD=min. VOL=0.4V 3.7
OE=VDD,V
OH=VDD
16 uA
VOL=0V 16
Output data delay T
DL
18 30 ns
Integral nonlinearity EL FC=20MSPS VIN=0.6V to 2.6V 0.5 1.3 LSB
Differential nonlinearity ED FC=20MSPS VIN=0.6V to 2.6V ±0.3 ±0.5 LSB
Differential gain error DG NTSC 40 IRE mod ramp,
FC=14.3MSPS 1.0 %
Differential phase error D
Aperture jitter t
Sampling delay t
P
AJ
DS
0.5 deg
30 ps
4ns
Timing
EM19100
Analog input
External clock
Upper comparators
block
Upper data
Lower reference
voltage
Lower comparators
A block
Vi(1) Vi(3)
S(1) C( 1)
MD(0)
RV(0)
S(1)
Vi(2)
S(2) C(2)
MD(1)
RV(1)
H(1) C(1)
S(3)
S(3)
MD(2)
RV(2)
C(3)
H(3)
S(4)
Vi(4)
C(4)
MD(3)
RV(3)
C(3)
Lower data A
Lower comparators
B block
Lower data B
Digital output
H(0)
LD(-2) LD( 0)
OUT(-2)
LD(-1)
C(0) S(2)
* This specification are subject to be changed without notice.
OUT(-1)
H(2)
LD(1)
C(2) S(4) H(4)
OUT(0)
LD(2)
OUT(1)
1.26.1996
3
Page 4
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
Timing explanation
EM19100 is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower
comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT-VRB/16 is
constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through
the reference supply to the lower data. V
voltage top) and VRB(Reference voltage bottom).
This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the
following operating modes which are respectively indicated on the timing chart with S, H, C symbols. That is
input sampling (auto zero) mode, input hold mode and comparison mode.
The operation of respective parts is as indicated in the chart. For instance input voltage Vi(1) is sampled with the
falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The
upper comparators block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously
the reference supply generates the lower reference voltage RV(1) that corresponded to the upper results. The
lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and
LD(1) are combined and output as Out(1) with the rising edge the 3rd clock. Accordingly there is a 2.5 clock delay
from the analog input sampling point to the digital data output.
RTS
and V
pins serve for the self generation of V
RBS
(Reference
RT
EM19100
Application Note
VDD,V
SS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the
respective GND’s.
Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However
it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When
driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by
inserting a resistance of about 100Ω in series between the amplifier output and A/D input.
Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate
it from other circuits
Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting V
and V
, VRB and VRBS, the self bias function that generates VRT=2.6V and VRB=0.6V, is activated.
RTS
Timing
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and
* This specification are subject to be changed without notice.
1.26.1996
RT
4
Page 5
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
with the following rising edge. The delay from the clock rising edge to the data output is about 18ns.
OE pin
EM19100
By connecting OE to GND output mode is obtained. By connecting to V
high impedance is obtained.
DD
About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up
due to the voltage difference between AVDD and DVDD pins when power is ON.
* This specification are subject to be changed without notice.
1.26.1996
5
Page 6
Application Circuit
EM19100
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
U2
U2
* This specification are subject to be changed without notice.
U3
1.26.1996
6
Loading...