The CXR702080 is a CMOS 32-bit microcomputer
integrating on a single chip an A/D converter, serial
interface, timer, bus interface unit, DMA controller,
memory stick interface, and as well as basic
configurations like a 32-bit RISC CPU, ROM, RAM,
and I/O port.
This also provides the idle/sleep/stop functions that
enable lower power consumption.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E01701A22-PS
Page 2
A0
to A23D0to D15
16
24
CS0
to CS7RDWE
8
LWR/LB
UWR/UB
WAIT
MA0
to MA18
19
EXTERNAL BUS
MD0
to MD7
8
MCS0,
MCS1
2
MRD
MWE
DACK0
DREQ0
DACK1
DREQ1
CT0ED0
CT0ED1
CT1ED0
CT1ED1
CT2ED0
CT2ED1
CXR702080
4
PORT O
8
PORT N
V
SS
V
DD
RST
EXTAL
XTAL
XOUT
TEX
TX
TXOUT
TDI
TMS
TCK
RTCK
TRST
TDO
to INT9
INT0
MSINS
BUS INTERFACE UNIT
DMAC (CH0)
DMAC (CH1)
DMAC (CH2)
DMAC (CH3)
16-BIT CAPTURE TIMER (CH0)
16-BIT CAPTURE TIMER (CH1)
SYSTEM CONTROLLER
16-BIT CAPTURE TIMER (CH2)
CLOCK GENERATOR/
3
PORT M
7
PORT L
8
PORT K
8
PORT J
8
CPU CORE
PORT I
ARM7TDMI
RAM
256K BYTES
16K BYTES
ROM
6
1
∗
1
∗
10
INTERRUPT CONTROLLER
3
WATCHDOG TIMER
TOKEI PRESCALER
4
PORT H
6
PORT G
6
PORT F
8
PORT E
4
PORT D
SS
REF
DD
Block Diagram
AV
AV
AV
A/D CONVERTER
4
AN0
to AN3
RAM
SERIAL INTERFACE
SI0
SCS0
SERIAL INTERFACE
UNIT (CH0)
SI1
SO0
SCK0
SCS1
UNIT (CH1)
SERIAL INTERFACE
SI2
SO1
SCK1
SCS2
2
∗
2
UART (CH0)
UNIT (CH2)
SO2
TxD0
RxD0
SCK2
2
∗
2
UART (CH1)
TxD1
RxD1
– 2 –
2
∗
MEMORY STICK INTERFACE
MSBS
MSDIO
EC0
MSIDR
MSSCLK
1
∗
8
8-BIT TIMER/COUNTER (CH0)
8-BIT TIMER (CH1)
T1
EC2
8-BIT TIMER/COUNTER (CH2)
8-BIT TIMER (CH3)
T3
8-BIT TIMER (CH4)
8-BIT TIMER (CH5)
BEEP
PORT C
PORT B
PORT A
8-BIT TIMER (CH6)
8-BIT TIMER (CH7)
6
8
6
The number of causes of interrupts generated from the module is as shown. But the number of causes input to the interrupt controller differs from the shown becauses of OR.
A part of the interrupt signals generated from UART, MEMORY STICK INTERFACE is input to the interrupt controller via DMA depending on applications.
I/O can be specified in
1-bit units.
Pull-up resistor can be
Chip select output for external S bus
(4 pins)
incorporated through
program in 1-bit units.
(6 pins)
Chip select output for external M bus.
(Port B)
8-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in 1-bit units.
(8 pins)
(Port C)
6-bit I/O port.
I/O can be specified in 1-bit units.
Pull-up resistor can be incorporated through program in 1-bit units.
(6 pins)
(Port D)
4-bit open drain port. Lower 2 bits are for output; upper 2 bits are for I/O.
(4mA drive)
Upper 2 bits can be specified in 1-bit units.
(4 pins)
Read signal output for external S bus.
Write strobe signal output for D0 to
D7.
Write strobe signal output for D8 to
D15.
Strobe signal output indicates
access to D0 to D7.
Strobe signal output indicates
access to D8 to D15.
Read signal output for external M bus.
Write signal output for external M bus.
Write signal output for external S bus.
Chip select output for external M bus.
Transfer request acknowledge signal output from DMA controller (CH0).
Transfer request input to DMA controller (CH0).
Transfer request acknowledge signal output from DMA controller (CH1).
Transfer request input to DMA controller (CH1).
Memory stick interface data I/O direction monitor.
Memory stick interface bus state output.
Memory stick interface clock output.
Memory stick interface data I/O direction monitor.
MSINS
TEST0
TEST1
TEST2
TDI
Input
Input
Input
Input
Input
Memory stick interface card detection.
Test. (Connect to Vss.)
Data input for JTAG boundary scanning test.
– 8 –
Page 9
CXR702080
Symbol
TMS
TRST
TCK
RTCK
TDO
EXTAL
XTAL
XOUT/CKO
TEX
TX
RST
NC
AVDD
AVREF
AVSS
VDD
VSS
I/O
Input
Input
Input
Output
Output
Input
Output
Output / Output
Input
Output
I/O
Input
Functions
Test mode control input for JTAG boundary scanning test.
Reset input for JTAG boundary scanning test.
Clock input for JTAG boundary scanning test.
Clock output for JTAG boundary scanning test.
Data output for JTAG boundary scanning test.
Oscillation connector of main oscillation.
(When a clock is supplied externally, input it to EXTAL; opposite phase
clock should be input to XTAL.)
Main oscillation output.
System clock output.
Oscillation connector of main oscillation.
(When a clock is supplied externally, input it to TEX; opposite phase
clock should be input to TX.)
System reset.
NC. (Leave this pin open or connect to Vss.)
Positive power supply for A/D converter.
Reference voltage input for A/D converter.
GND for A/D converter.
Positive power supply (Connect all twelve VDD pins to positive power supply.)
GND (Connect all twelve Vss pins to GND)
– 9 –
Page 10
I/O Circuit Format for Pins
PinCircuit formatAfter a reset
CXR702080
Port A data
Port A direction
"0" after a reset
PA0/WAIT
PA1/CS2
to
PA4/CS5
Pull-up resistor
"0" after a reset
Internal data bus
Port A
function select
"0" after a reset
Port A direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
RD
Port A data
RD
MPX
CS2 to CS5
S bus pin active
MPX
WAIT
Input data
latch
MPX
MPX
Input data
latch
Hi-Z
IP
Hi-Z
IP
PA5/MCS1
Port A
function select
"0" after a reset
Port A direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
MCS1
(M bus unused: CS7)
Port A data
RD
MPX
– 10 –
MPX
Input data
latch
Hi-Z
IP
Page 11
CXR702080
PinCircuit formatAfter a reset
Port B data
Port B direction
"0" after a reset
PB0 to PB7Hi-Z
Internal data bus
PC0 to PC5
Internal data bus
Pull-up resistor
"0" after a reset
RD
Port C data
Port C direction
"0" after a reset
Pull-up resistor
"0" after a reset
RD
MPX
MPX
Input data
latch
Input data
latch
IP
Hi-Z
IP
PD0
PD1
PD2
PD3
Internal data bus
Port D data
Port D
read select
"0" after a reset
Internal data bus
Port D data
RD
RD
MPX
– 11 –
Input data
latch
Hi-Z
Hi-Z
IP
Page 12
CXR702080
PinCircuit formatAfter a reset
Port E data
Port E direction
"0" after a reset
PE0/INT0
to
PE7/INT7
PF0/EC0
PF2/EC2
Pull-up resistor
"0" after a reset
Internal data bus
Port F direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
RD
Port F data
RD
MPX
INT0 to INT7
MPX
EC0, EC2
Input data
latch
Input data
latch
Hi-Z
IP
CMOS
Schmitt input
Hi-Z
IP
CMOS
Schmitt input
PF1/T1
PF3/T3
PF4/BEEP
PF5/TXOUT
Port F
function select
"0" after a reset
Port F direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
T1, T3, BEEP , TXOUT
Port F data
RD
MPX
– 12 –
MPX
Input data
latch
Hi-Z
IP
Page 13
PinCircuit formatAfter a reset
Port G data
Port G direction
PG0/CT0ED0
PG1/CT0ED1
PG2/CT1ED0
PG3/CT1ED1
"0" after a reset
Pull-up resistor
"0" after a reset
PG4/CT2ED0
PG5/CT2ED1
Internal data bus
RD
CT0ED0, CT0ED1
CT1ED0, CT1ED1
CT2ED0, CT2ED1
TxD0, TxD1
MPX
Input data
latch
IP
CMOS
Schmitt input
CXR702080
Hi-Z
PH0/TxD0
PH2/TxD1
Port H
function select
"0" after a reset
Port H direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
Port H direction
"0" after a reset
Port H data
RD
Port H data
MPX
MPX
Input data
latch
Hi-Z
IP
PH1/RxD0
PH3/RxD1
Pull-up resistor
"0" after a reset
Internal data bus
RD
MPX
RxD0, RxD1
– 13 –
Input data
latch
Hi-Z
IP
CMOS
Schmitt input
Page 14
CXR702080
PinCircuit formatAfter a reset
MD0 to MD7
MPX
MPX
Hi-Z
PI0/MD0
to
Port I data
Port I
function select
"1" after a reset
M bus output enable
Port I direction
"0" after a reset
PI7/MD7
Pull-up resistor
"0" after a reset
Internal data bus
RD
Port J data
MPX
MD0 to MD7
D0 to D7
Input data
latch
MPX
IP
PJ0/D0
to
PJ7/D7
PK0/D8
to
PK7/D15
Port J
function select
"1" after a reset
Port J direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
Port K
function select
"1" after a reset
Port K direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
S bus output enable
RD
Port K data
S bus output enable
RD
MPX
D0 to D7
D8 to D15
MPX
MPX
Input data
latch
MPX
MPX
Input data
latch
Hi-Z
IP
Hi-Z
IP
D8 to D15
– 14 –
Page 15
CXR702080
PinCircuit formatAfter a reset
A1 to A8
A1 to A8
MA18/A0
MA1/A9
to
MA8/A16
PL0/MA9/A17
to
PL6/MA15/A23
S bus pin active
MA18
A0
S bus/M bus select
MA1 to MA8
A9 to A16
S bus/M bus select
MA9 to MA15
A17 to A23
Port L data
S bus/M bus select
Port L
function select
"1" after a reset
S bus pin high impedance
Port L direction
MPX
MPX
Low
Low
Low
MPX
Low
MA0
MA16
MA17
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
RD
MA0
MA16, MA17
MPX
– 15 –
Input data
latch
IP
Low
Low
Page 16
CXR702080
PinCircuit formatAfter a reset
Analog input select
("1" after a reset)
AN0
PM0/AN1
to
PM2/AN3
PN0/SCK0
PN4/SCK1
Internal data bus
Port N
function select
"0" after a reset
Port N direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
Analog input select
("0" after a reset)
Port N data
SCKEN0, SCKEN1
RD
AN0
RD
"1" after a reset
AN1, AN2, AN3
SCK0, SCK1
MPX
SCK0, SCK1
Input data
latch
Port M
function select
MPX
MPX
Input data
latch
IP
CMOS
Scmitt input
Hi-Z
IP
Hi-Z
Hi-Z
IP
PN1/SO0
PN5/SO1
Port N
function select
"0" after a reset
Port N direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
Port N data
SOEN0, SOEN1
RD
SO0, SO1
MPX
– 16 –
MPX
MPX
Input data
latch
Hi-Z
IP
Page 17
CXR702080
PinCircuit formatAfter a reset
Port N data
Port N direction
"0" after a reset
PN2/SI0
PN6/SI1
PN3/SCS0/INT8
PN7/SCS1/INT9
Pull-up resistor
"0" after a reset
Internal data bus
Port N direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
RD
Port N data
RD
MPX
SI0, SI1
MPX
SCS0, SCS1
INT8, INT9
Input data
latch
Input data
latch
Hi-Z
IP
Hi-Z
IP
CMOS
Schmitt input
PO0/SCK2
Port O
function select
"0" after a reset
Port O direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
Port O data
RD
SCK2
SCKEN2
MPX
SCK2
– 17 –
MPX
MPX
Input data
latch
Hi-Z
IP
CMOS
Schmitt input
Page 18
CXR702080
PinCircuit formatAfter a reset
SO2
MPX
MPX
Hi-Z
PO1/SO2
Port O data
Port O
functon select
"0" after a reset
SOEN2
Port O direction
"0" after a reset
Pull-up resistor
"0" after a reset
PO2/SI2
Internal data bus
Port O direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
RD
Port O data
RD
Port O data
MPX
MPX
SI2
Input data
latch
Input data
latch
IP
Hi-Z
IP
PO3/SCS2
Port O direction
"0" after a reset
Pull-up resistor
"0" after a reset
Internal data bus
RD
MPX
SCS2
– 18 –
Input data
latch
Hi-Z
IP
CMOS
Schmitt input
Page 19
CXR702080
PinCircuit formatAfter a reset
CS0, CS1
CS0
CS1
S bus pin active
RD
High
RD
LWR/LB
UWR/UB
MRD
MWE/WE
S bus pin active
LWR, UWR
LB, UB
16-bit SRAM
access method select
S bus pin active
MRD
16-bit SRAM
access method select
MWE
WE
High
MPX
High
High
MPX
High
MCS0
DACK0
DACK1
DREQ0
DREQ1
MCS0
(M bus unused: CS6)
DACK0, DACK1
– 19 –
High
High
DREQ0, DREQ1IP
Hi-Z
Page 20
CXR702080
PinCircuit formatAfter a reset
MSDIR
MSBS
MSSCLK
MSDIO
MSINS
XOUT/CKO
MSDIR, MSBS, MSSCLK
MSDIO (output data)
MSDIO output enable
MSDIO (input data)
System clock
XTAL
Clock output enable
Output clock select
CMOS
Schmitt input
MPX
Low
Hi-Z
IP
MSINSIP
Hi-Z
Oscillation
output
EXTAL
XTAL
TEX
TX
EXTAL
XTAL
TEX
TX
• Diagram shows circuit
IP
IP
configuration during oscillation.
• Feedback resistor is removed
during stop mode, and XTAL is
driven at “H” level.
• Diagram shows circuit
configuration during oscillation.
• Feedback resistor is removed
during stop mode, and TEX is
driven at “L” level; TX at “H” level.
Oscillation
Oscillation
– 20 –
Page 21
CXR702080
PinCircuit formatAfter a reset
CMOS
Schmitt input
RST
TDI
TMS
TCK
TRST
IP
Internal reset signal
RSTWD
(from watchdog timer)
Pull-up
Pull-up
IP
IP
TDI, TMS, TCK
(to CPU core)
TRST
(to CPU core)
Pull-down
RTCK
TDO
TEST0
TEST1
TEST2
RTCK
TDO
TDO output enable
High
Low
IP
IP
TEST0, TEST1
(to test circuit)
TEST2
(to test circuit)
Hi-Z
Pull-down
– 21 –
Page 22
CXR702080
Absolute Maximum Ratings(Vss = 0V reference)
Item
Symbol
VDD
AVDD
Rating
–0.3 to +4.6
AVSS to +4.6
∗1
Unit
V
V
Remarks
Supply voltage
AVSS
AVREF
Input voltage
Output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
∗1
AVDD and VDD must be the same voltage.
∗2
VIN and VOUT must not exceed VDD + 0.3V.
VIN
VOUT
IOHΣIOH
IOLΣIOL
Topr
Tstg
PD
–0.3 to +0.3
AVSS to +4.6
–0.3 to +4.6
–0.3 to +4.6
–5
–40
10
80
–40 to +85
–55 to +150
380
∗2
∗2
V
V
V
V
mA
mA
mA
mA
°C
°C
mW
Output (value per pin)
Total for all output pins
Output (value per pin)
Total for all output pins
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation
should be conducted under the recommended operating conditions. Exceeding these conditions may
adversely affect the reliability of the LSI.
PN6, PO1, PO2, DREQ0, DREQ1, MSDIO, TDI, TMS, TRST, TCK and TEST0 to TEST2).
∗3
Each pin of EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1,
SCK0 to SCK2, SCS0 to SCS2, INT8, INT9, MSINS and RST.
∗4
Specified only during external clock input.
– 22 –
Page 23
CXR702080
Electrical Characteristics
DC Characteristics (VDD = 2.7 to 3.6V)(Topr = –40 to +85°C, Vss = 0V reference)
Item
High level
output
voltage
Low level
output
voltage
Symbol
VOH
VOL
Pins
PA to PC, PE to PL, PN, PO,
T1, T3, TxD0, TxD1, MCS0,
MCS1, MA0 to MA18,
MD0 to MD7, MRD, MWE,
CS0 to CS5, A0 to A23,
D0 to D15, RD, LWR, LB,
UWR, UB, WE, RST
BEEP, TXOUT, SCK0 to SCK2,
SO0 to SO2, DACK0, DACK1,
MSDIR, MSBS, MSSCLK,
MSDIO, RTCK, TDO, XOUT,
CKO
PA to PC, PE to PL, PN, PO,
T1, T3, TxD0, TxD1, MCS0,
MCS1, MA0 to MA18,
MD0 to MD7, MRD, MWE,
CS0 to CS5, A0 to A23,
D0 to D15, RD, LWR, LB,
UWR, UB, WE, RST
PD, BEEP, TXOUT,
SCK0 to SCK2, SO0 to SO2,
DACK0, DACK1, MSDIR,
MSBS, MSSCLK, MSDIO,
RTCK, TDO , XOUT, CK O
Conditions
IOH = –0.5mA
IOH = –4mA
IOL = 1mA
IOL = 4mA
Min.
VDD – 0.4
VDD – 0.4
Typ.
Max.
0.4
0.4
Unit
V
V
V
V
IIHE
VIH = 3.6V
0.1
10
EXTAL
IILE
IIHT
VIL = 0.4V
VIH = 3.6V
–0.1
0.1
–10
10
TEX
Input
current
IILT
IIH
TRST
PA to PC, PE to PL, PN, PO,
WAIT, INT0 to INT9, EC0,
VIL = 0.4V
VIH = 3.6V
–0.1
20
100
–10
240
EC2, CT0ED0, CT0ED1,
IIL
CT1ED0, CT1ED1, CT2ED0,
CT2ED1, RxD0, RxD1,
VIL = Vss
–20
–50
–120
MD0 to MD7, D0 to D15,
SCK0 to SCK2, SI0 to SI2,
SCS0 to SCS2
TDI, TMS, TCK
∗1
PA to PC, PE to PL, PN, PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1,
∗1
VIL = Vss
–20
–100
–240
CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2 and SCS0 to
SCS2 pins specify the input current when the pull-up resistor is selected, and specify leakage current
when non-resistor is selected.
µA
µA
µA
µA
µA
µA
µA
– 23 –
Page 24
CXR702080
Item
I/O leakage
current
Symbol
IZH
IZL
IDD1
Pins
PD2, PD3, PM, AN0 to AN3,
DREQ0, DREQ1, MSDIO,
MSINS, PA to PC, PE to PL,
PN, PO, WAIT, INT0 to INT9,
EC0, EC2, CT0ED0, CT0ED1,
CT1ED0, CT1ED1, CT2ED0,
CT2ED1, RxD0, RxD1,
MD0 to MD7, D0 to D15,
SCK0 to SCK2, SI0 to SI2,
SCS0 to SCS2
PD2, PD3, PM, AN0 to AN3,
DREQ0, DREQ1, MSDIO,
MSINS, PA to PC, PE to PL,
PN, PO, WAIT, INT0 to INT9,
EC0, EC2, CT0ED0, CT0ED1,
CT1ED0, CT1ED1, CT2ED0,
CT2ED1, RxD0, RxD1,
MD0 to MD7, D0 to D15,
SCK0 to SCK2, SI0 to SI2,
SCS0 to SCS2
∗1
Conditions
VI = 3.6V
VI = 0V
Main execution mode
18.432MHz crystal
oscillation (C1 = C2 = 10pF)
Min.Typ.Max.
10
–10
43
Unit
µA
µA
mA
Supply
current
Input
capacity
∗2
IDDI1
IDDS1
IDDS2
CIN
VDD
PA to PC, PD2, PD3, PE to PO,
WAIT, INT0 to INT9, EC0,
EC2, CT0ED0, CT0ED1,
CT1ED0, CT1ED1, CT2ED0,
CT2ED1, RxD0, RxD1,
MD0 to MD7, D0 to D15,
AN0 to AN3, SCK0 to SCK2,
SI0 to SI2, SCS0 to SCS2,
MSDIO, EXTAL, TEX, RST,
TEST0
PA to PC, PE to PL, PN, PO, WAIT, INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1,
CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2 and SCS0 to
SCS2 pins specify the input current when the pull-up resistor is selected, and specify leakage current
when non-resistor is selected.
∗2
When all output pins are left open and XOUT/CKO = “L” (POSL register SLCKO bit = “00” or “01”).
– 24 –
Page 25
CXR702080
AC Characteristics
(1) Clock timing(Topr = –40 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Main oscillation input clock
frequency
Main oscillation input clock
pulse width
Main oscillation input clock
rise time, fall time
Sub oscillation input clock
frequency
Event count input clock
pulse width
Event count input clock
rise time, fall time
Symbol
fEX
tXL,
tXH
tCR,
tCF
fTEX
tEH,
tEL
tER,
tEF
Pins
XTAL
EXTAL
XTAL
EXTAL
XTAL
EXTAL
TEX
TX
EC0
EC2
EC0
EC2
Conditions
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig. 1, Fig. 2
External clock drive
Fig. 2
32kHz clock applied condition
Fig. 3
Fig. 3
Note) fPS4 is fSRC/16 (MHz) for output fSRC of main oscillation circuit.
1/fEX
EXTAL
XTAL
Min.
1
22.5
2/fPS4
Typ.
32.768
0.9VDD
0.4V
Max.
20
100/fEX
1
Unit
MHz
ns
ns
kHz
µs
ms
Crystal oscillation
Ceramic oscillation
C
EC0
EC2
EXTAL
1
t
XH
Fig. 1. Clock timing
External clock
XTAL
C2
EXTALXTAL
74HC04
Fig. 2. System clock applied condition
t
EH
t
EF
Fig. 3. Event count input timing
CRtXLtCF
t
32kHz clock applied condition
Crystal oscillation
TEX
1
C
t
EL
TX
C2
0.7V
0.2V
t
ER
DD
DD
– 25 –
Page 26
CXR702080
(2) Serial transfer (CH0, CH1, CH2)(Topr = –40 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
SCS ↓ → SCK
delay time
SCS ↑ → SCK
float delay time
SCS ↓ → SO delay time
SCS ↑ → SO
float delay time
SCS high level width
SCK interval time
SCK cycle time
SCK high, low
pulse width
Input setup time
(for SCK ↑)
SI input hold time
(for SCK ↑)
SCK ↓ → SO delay time
Symbol
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKINT
tKCY
tKH
tKL
tSIK
tKSI
tKSO
Pins
SCK0
SCK1
SCK2
SCK0
SCK1
SCK2
SO0
SO1
SO2
SO0
SO1
SO2
SCS0
SCS1
SCS2
SCK0
SCK0
SCK1
SCK2
SCK0
SCK1
SCK2
SI0
SI1
SI2
SI0
SI1
SI2
SO0
SO1
SO2
Conditions
External star t transfer mode
Input mode (SCKOE = “1”)
Output mode
External star t transfer mode
(SCK = output mode,
SCKOE = “1”)
Notes) 1. The load condition for the SCK output mode and SO output delay time is 50pF.
2. fSIO is fSRC/2 (MHz) for output fSRC of main oscillation circuit. As for fSCK and fSYS, see the following.
Serial clock selection
∗1
PS3
∗1
PS4
PS5
PS6
∗2
PS7
∗2
PS8
fSCK (MHz)
fSRC/8
fSRC/16
fSRC/32
fSRC/64
fSRC/128
fSRC/256
Serial clock frequency division ratio
No frequency division
2 frequency division
4 frequency division
16 frequency division
∗1
CH1, CH2 only ∗2 CH0 only
– 26 –
fSCK (MHz)
No
fSRC/2
fSRC/4
fSRC/16
Page 27
WHCS
t
CXR702080
SCS0
SCS1
SCS2
SCK0
SCK1
SCK2
SI0
SI1
SI2
0.2VDD
tDCSK
tKL
tSIK
Input
data
tKCY
tKSI
tKH
0.7V
0.2VDD
0.7VDD
tDCSKF
0.7VDD
0.2VDD
DD
SO0
SO1
SO2
SCK0
SCK1
SCK2
tDCSO
tKSO
0.7VDD
Output data
0.2VDD
tKINT
n byten + 1 byte
Fig. 4. Serial transfer CH0, CH1, CH2 timing
tDCSOF
0.7VDD
0.2VDD
– 27 –
Page 28
CXR702080
(3) Serial transfer (memory stick)(Topr = –40 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
MSSCLK
cycle time
MSSCLK
high, low pulse width
MSBS
output delay time
MSDIO
output delay time
MSDIO
input setup time
MSDIO
input hold time
MSDIR
output delay time
Notes) 1. The load condition is 26pF.
2. fMSCK is as follows for output fSRC of main oscillation circuit.
Shift clock frequency division ratio
No frequency division
Symbol
tKCY
tKH
tKL
tBSD
tDIOD
tDIOS
tDIOH
tDIRD
Pins
MSSCLK
MSSCLK
MSBS
MSDIO
MSDIO
MSDIO
MSDIR
fMSCK (MHz)
fSRC
Conditions
For MSSCLK ↓
For MSSCLK ↓
For MSSCLK ↑
For MSSCLK ↑
For MSSCLK ↓
Min.
MSCK
1000/f
500/fMSCK – 5
18
5
Max.
10
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
2 frequency division
4 frequency division
8 frequency division
fSRC/2
fSRC/4
fSRC/8
– 28 –
Page 29
MSSCLK
0.7V
DD
0.2VDD
tKLtKH
CXR702080
tKCY
MSBS
MSDIO (output)
MSDIO (input)
MSDIR
tBSD
Bus state output
tDIOD
tDIOS
Output data
Input data
tDIOH
Serial data I/O direction output
tDIRD
Fig. 5. Memory stick transfer timing
– 29 –
Page 30
(4) A/D converter characteristics
(Topr = –40 to +85°C, VDD = 2.7 to 3.6V, VDD = AVDD, Vss = AVss = 0V reference)
CXR702080
Item
Symbol
Pins
Conditions
Resolution
Absolute error
Conversion time
Sampling time
Reference input voltage
Analog input voltage
tCONV
tSAMP
VREF
VIAN
AVREF
AN0 to AN3
VDD = AVDD = 2.7V
Note) fPS4 is fSRC/16 (MHz) for output fSRC of main oscillation circuit.
Conversion time indicates the time required from conversion start to ADC interruption request
occurrence when 1 channel is selected. This includes sampling time.
FFh
FEh
Absolute error
Min.
19/fPS4
AVDD – 0.3
0
Typ.
5/fPS4
Max.
8
±3
20/fPS4
AVDD
AVREF
Unit
Bits
LSB
µs
µs
V
V
Digital conversion value
01h
00h
Analog input
AV
REF
Fig. 6. Definition of A/D converter terms
(5) Interruption and reset input(Topr = –40 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)