Page 1
Description
The CXP913040 is a CMOS 16-bit microcomputer
integrating on a single chip an A/D converter, serial
interface with an incorporated buffer RAM, highprecision timing pattern generation function, pulse
cycle measurement circuit, PWM generator, generalpurpose prescaler, vertical sync separation circuit,
and a measurement circuit which measures the
signals of capstan FG, drum FG/PG, reel FG and
other servo systems with high precision, as well as
basic configurations like a 16-bit CPU, ROM, RAM,
and I/O port.
This LSI also provides sleep/stop modes that enable
lower power consumption.
Features
• An efficient instruction set as a controller
— Direct addressing, numerous abbreviated forms, multiplication and division instructions
• Instruction sets for C language and RTOS
— Highly quadratic instruction system, general-purpose register of 16-bit × 8-pin × 16-bank configuration
• Minimum instruction cycle time 100ns at 20MHz operation
• Incorporated ROM capacity 160K bytes
• Incorporated RAM capacity 6144 bytes
• Peripheral functions
— A/D converter 8-bit 12-channel successive approximation system, automatic
scanning function, 8-stage (soft) + 4-stage (hard) FIFO for
conversion results (Conversion time: 20µs at 20MHz)
— Serial interface Buffer RAM (128 bytes, supports high-speed transfer mode),
3 channels
— Timers 8-bit timer/counter + 8-bit timer (with timing output), 1 channel
16-bit capture timer/counter (with timing output), 1 channel
16-bit timer, 4 channels
— High-precision timing pattern generator PPG for 27 pins, 42 stages (max.)
PPG for 16 pins, 16 stages (max.)
RTG for 5 pins, 3 channels
— PWM/DA gate output PWM for 14 bits, 2 channels
(Repetitive frequency of 39.1kHz, 20MHz)
DA gate pulse for 14 bits, 2 channels
— Servo input control Capstan FG, drum FG/PG, reel FG
— VSYNC separator
— FRC capture unit 24-bit and 8-stage FIFO
— PWM output 14 bits, 2 channels
— General-purpose prescaler 10 bits, 1 channel
— Pulse cycle measurement circuit 1 channel with mask input
• General-purpose I/O 80 pins
(max.; when all multi-purpose pins are used as general-purpose I/O.)
• Interruption 28 factors, 28 vectors, multi-interruption and priority selection
possible
• Standby mode Sleep/stop
• Package 100-pin plastic LQFP
• Piggy/evaluation chip CXP913000 100-pin ceramic LQFP
CXP913040
CMOS 16-bit Single Chip Microcomputer
– 1 –
E96X05-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
100 pin LQFP (Plastic)
Structure
Silicon gate CMOS IC
For the availability of this product, please contact the sales office.
Page 2
– 2 –
CXP913040
Vss
V
DD
CLOCK
GENERATOR/
SYSTEM
CONTROLLER
RAM
6144 BYTES
SPC900
CPU CORE
FIFO
FRC
CAPTURE UNIT
5
10
4
SERIAL INTERFACE UNIT
(CH0)
RAM
8-BIT TIMER/COUNTER 0
8-BIT TIMER 1
V SYNC SEPARATOR
PULSE MEASURE UNIT
SERVO INPUT
CONTROL
CAPSTAN
DRUM
REEL
4
3
REAL-TIME
PULSE
GENERATOR
NMI
INT0
RST
8
PORT A
8
PORT B
8
PORT C
8
PORT D
PORT E
4
4
PORT F
PORT G
8
PORT H
PORT I
EXTAL
XTAL
PRESCALER
14-BIT PWM/DA GENERATOR
(× 2ch)
SERIAL INTERFACE UNIT
(CH1)
CH0
8
PORT J
RTO0
to
RTO4
PPO100
to
PPO109
16-BIT TIMER (× 4ch)
PROGRAMMABLE
PATTERN
GENERATOR
RAM(CH1)
CH1 CH2
FIFO
FIFO
A/D
CONVERTER
4
2
INT1
INT2
12
19
PPO000
to
PPO018
PROGRAMMABLE PRESCALER
PROGRAMMABLE
PATTERN
GENERATOR
RAM(CH0)
4
INTERRUPT CONTROLLER
2
SERIAL INTERFACE UNIT
(CH2)
16-BIT CAPTURE TIMER/COUNTER
RAM
RAM
2
AN0
to
AN11
AV
SS
AV
REF
AV
DD
14-BIT PWM GENERATOR (× 2ch)
8
2
6
4
4
2
2
PMSK
PMI
PWM3
PWM2
DA1
PWM0
EXI1
EXI0
RFG1
RFG0
CFG
SYNC1
SYNC0
T2
CINT
T1
EC0
SCK2
SO2
SI2
SCK1
SO1
SI1
CS1
DA0
PWM1
XOUT
(OSCO)
PCK/OSCI
PO
DPG
DFG
EC2
SCK0
SO0
SI0
CS0
CS2
ROM
160K BYTES
3
Block Diagram
Page 3
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CXP913040
Pin Configuration (Top View)
PB4/PPO012
PB5/PPO013
PB6/PPO014
PB7/PPO015
PC0/PPO016
PC1/PPO017
PC2/PPO018
PC3/RTO0
PC4/RTO1
PC5/RTO2
PC6/RTO3
PC7/RTO4
VSS
PD0/KS0
PD1/KS1
PD2/KS2
PD3/KS3
PD4/KS4
PD5/KS5
PD6/KS6
PD7/KS7
PE0
PE1
PE2
PE3
AV
SS
AN3
AN2
AN1
PI7/AN0
VSS
PI6/XOUT
PI5/OSCO
PI4/PCK/OSCI
PI3/CS2/PO
PI2/SCK2
PI1/SO2
PI0/SI2
SCK0
SO0
SI0
CS0
PH7/CFG
PH6/DFG
PH5/DPG
PH4/PMSK
PH3/SYNC1
PH2/SYNC0/PMI
PH1/EXI1
PH0/EXI0
PB3/PPO011
PB2/PPO010
PB1/PPO009/PPO109
PB0/PPO008/PPO108
PA7/PPO007/PPO107
PA6/PPO006/PPO106
PA5/PPO005/PPO105
PA4/PPO004/PPO104
PA3/PPO003/PPO103
PA2/PPO002/PPO102
PA1/PPO001/PPO101
PA0/PPO000/PPO100
V
SS
V
DD
V
DD
PJ7/AN11/KS15
PJ6/AN10/KS14
PJ5/AN9/KS13
PJ4/AN8/KS12
PJ3/AN7/KS11
PJ2/AN6/KS10
PJ1/AN5/KS9
PJ0/AN4/KS8
AV
DD
AV
REF
PE4
PE5
PE6
PE7
PF0/EC0/INT0
PF1/EC2/INT1
PF2/CS1/NMI/CINT
PF3/SI1/INT2
PF4/SO1
PF5/SCK1
PF6/T1
PF7/T2
RST
V
SS
XTAL
EXTAL
V
DD
PG0/PWM0
PG1/PWM1
PG2/PWM2
PG3/PWM3
PG4/DA0
PG5/DA1
PG6/RFG0
PG7/RFG1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
76
77
78
79
80
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
81
82
83
84
88
87
86
85
89
90
100
99
98
97
96
95
94
91
92
93
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
Note) 1. Vss (Pins 13, 39, 70 and 88) must be connected to GND.
2. VDD (Pins 42, 86 and 87) must be connected to VDD.
Page 4
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CXP913040
Output /
Real time output /
Real time output
Output /
Real time output /
Real time output
Output /
Real time output
Output /
Real time output
Output /
Real time output
I/O
I/O
(Port A)
8-bit output port. Data is
gated with PPO0 and PPO1
contents by OR-gate and
they are output. (8 pins)
(Port B)
8-bit output port. Data is
gated with PPO0 and
PPO1 contents by ORgate and they are output.
(8 pins)
(Port C)
8-bit I/O port. I/O can be
specified by bit unit.
Data is gated with PPO0
or RTO contents by ORgate and they are output.
(8 pins)
(Port D)
8-bit I/O port. I/O can be specified by bit unit.
Standby release input function can also be specified by bit unit.
Can drive 12mA sink current when VDD = 5V.
(8 pins)
(Port E)
8-bit I/O port. I/O can be specified by bit unit.
Can drive 12mA sink current when VDD = 5V.
(8 pins)
(Port F)
8-bit port.
Lower 4 bits
are for input;
upper 4 bits
are for output.
(8 pins)
Programmable pattern generator (PPG0,
PPG1) output. Functions as high-precision
real-time pulse output port.
(PPG0 19 pins, PPG1 10 pins)
Real-time pulse generator (RTG) output.
Functions as high-precision real-time
pulse output port.
(5 pins)
Symbol I/O Functions
PA0/PPO000
/PPO100
to
PA7/PPO007
/PPO107
PB0/PPO008
/PPO108
PB1/PPO009
/PPO109
PB2/PPO010
to
PB7/PPO015
PC0/PPO016
to
PC2/PPO018
PC3/RTO0
to
PC7/RTO4
PD0 to PD7
PE0 to PE7
PF0/EC0/
INT0
Input / Input /
Input
Input / Input /
Input
Input / Input /
Input / Input
Input / Input /
Input
PF1/EC2/
INT1
PF2/CS1/
NMI/CINT
PF3/SI1/INT2
PF4/SO1
PF5/SCK1
PF6/T1
PF7/T2
Output / Output
Output / I/O
Output / Output
Output / Output
Pin Description
External event input for
timer/counter.
(2 pins)
Serial data (CH1) input.
Serial data (CH1) output.
Serial data (CH1) I/O.
8-bit timer/counter output.
16-bit capture timer/counter output.
Input to request external
interruption. Active at the
falling edge.
Serial chip
select (CH1)
input.
Input to request external
interruption. Active at the
falling edge.
(2 pins)
Input to request
non-maskable
interruption. Active
at the falling edge.
External capture
input for 16-bit
timer/counter.
Page 5
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CXP913040
PG0/PWM0
PG1/PWM1
PG2/PWM2
PG3/PWM3
PG4/DA0
PG5/DA1
PG6/RFG0
PG7/RFG1
PH0/EXI0
PH1/EXI1
PH2/
SYNC0/PMI
PH3/SYNC1
PH4/PMSK
PH5/DPG
PH6/DFG
PH7/CFG
SCK0
SO0
SI0
CS0
PI0/SI2
PI1/SO2
PI2/SCK2
PI3/CS2/PO
PI4/PCK/
OSCI
PI5/OSCO
PI6/XOUT
PI7/AN0
AN1 to AN3
PJ0/AN4
to
PJ7/AN11
Output / Output
Output / Output
Output / Output
Output / Output
Output / Output
Output / Output
Input / Input
Input / Input
Input / Input
Input / Input
Input / Input /
Input
Input / Input
Input / Input
Input / Input
Input / Input
Input / Input
I/O
Output
Input
Input
I/O / Input
I/O / Output
I/O / I/O
I/O / Input / Output
Input / Input /
Input
Input / Output
Input / Output
Input / Input
Input
I/O / Input
14-bit PWM output.
(4 pins)
DA gate pulse output.
(2 pins)
Reel FG input.
(2 pins)
External input for FRC capture unit.
(2 pins)
Composite sync signal
input.
(2 pins)
Mask input for pulse cycle measurement circuit.
Drum PG input.
Drum FG input.
Capstan FG input.
Serial data (CH2) input.
Serial data (CH2) output.
Serial clock (CH2) I/O.
General-purpose
prescaler external clock input.
Clock output from clock generator or general-purpose
prescaler.
Serial clock (CH0) I/O.
Serial data (CH0) output.
Serial data (CH0) input.
Serial chip select (CH0) input.
Pulse input for pulse cycle
measurement circuit.
(Port G)
8-bit port.
Lower 6 bits
are for output;
upper 2 bits
are for input.
(8 pins)
(Port H)
8-bit input
port.
(8 pins)
(Port I)
8-bit port.
Lower 4 bits
are for I/O;
upper 4 bits
are for input.
Lower 4 bits
can be
specified by
bit unit.
(8 pins)
(Port J)
8-bit I/O port. I/O can be
specified by bit unit.
Standby release input
function can also be
specified by bit unit.
(8 pins)
Analog input for A/D converter.
(12 pins)
Symbol I/O Functions
Connects a crystal for generalpurpose prescaler clock
oscillation. (Mask option)
General-purpose prescaler output.
Serial chip select (CH2) input.
Page 6
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CXP913040
EXTAL
XTAL
RST
AVDD
AVREF
AVSS
VDD
VSS
Input
Output
I/O
Input
Connects a crystal for system clock oscillation. When the clock is
supplied externally, input it to EXTAL and input an opposite phase
clock to XTAL.
System reset. Active at "L" level.
Positive power supply for A/D converter.
Reference voltage input for A/D converter.
A/D converter GND.
Positive power supply. All three VDD pins must be connected to the
positive power supply.
GND. All four VSS pins must be connected to GND.
Symbol I/O Functions
Page 7
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CXP913040
10 pins
Hi-Z
Hi-Z
When reset
PA0/PPO000/
PPO100
to
PA7/PPO007/
PPO107
PB0/PPO008/
PPO108
to
PB1/PPO009/
PPO109
PC0/PPO016
to
PC2/PPO018
PC3/RTO0
to
PC7/RTO4
Hi-Z
PD0/KS0
to
PD7/KS7
PPO0 data
Data bus
Output becomes active from Hi-Z by
writing data to port register.
Port A or
Port B data
RD
PPO1 data
PPO0 data
Data bus
Output becomes active from Hi-Z by
writing data to port register.
Port B data
RD
PPO0 or RTO data
Data bus
RD (Port C)
Port C direction
Port C data
Input protection
circuit
IP
(Every bit)
A
"0" when reset
Data bus
RD
Port D direction
Port D data
IP
(Every bit)
∗
Standby release
"0" when reset
Port D standby
release data
Edge detection
∗
Large current drive transistor
6 pins
Hi-Z
PB2/PPO010
to
PB7/PPO015
I/O Circuit Format for Pins
Port A
Port B
Pin
Circuit format
8 pins
8 pins
Port B
Port C
Port D
Page 8
– 8 –
CXP913040
8 pins
Hi-Z
Hi-Z
When reset
PE0 to PE7
PF2/CS1/
NMI/CINT
Hi-Z
PF4/SO1
Data bus
RD
Port E direction
Port E data
IP
(Every bit)
∗
"0" when reset
∗
Large current drive transistor
IP
RD (Port F)
Data bus
Schmitt trigger input
Interrupt circuit and
timer/counter or SIO
IP
RD (Port F)
Schmitt trigger input
Port F function selection
Interrupt circuit
Timer/counter or SIO
Data bus
"0" when reset
MPX
Data bus
RD (Port F)
A
A
AAA
Port F function
selection
SO1 from SIO
"0" when reset
Hi-Z control
Port F data
3 pins
Hi-Z
PF0/EC0/INT0
PF1/EC2/INT1
PF3/SI1/INT2
Port E
Pin
Circuit format
1 pin
1 pin
Port F
Port F
Port F
A
Page 9
– 9 –
CXP913040
1 pin
Hi-Z
Hi-Z
When reset
PF5/SCK1
PG6/RFG0
PG7/RFG1
Hi-Z
PH0/EXI0
PH1/EXI1
PH2/SYNC0/PMI
PH3/SYNC1
PH4/PMSK
PH5/DPG
PH6/DFG
PH7/CFG
MPX
Data bus
RD (Port F)
Port F function
selection
Internal serial clock from SIO
"0" when reset
Hi-Z control
Port F data
IP
SIO
Schmitt trigger input
MPX
Data bus
RD (Port F)
A
Port F function
selection
Timer/counter
"0" when reset
Port F data
"1" when reset
MPX
Data bus
RD (Port G)
Port G function
selection
DA gate output or PWM output
"0" when reset
Hi-Z control
Port G data
IP
RD (Port G)
Data bus
Servo circuit
Schmitt trigger input
IP
RD (Port H)
Data bus
Servo circuit
Note) PH2/SYNC0/PMI and PH3/SYNC1 can select CMOS Schmitt trigger input or
TTL Schmitt trigger input with the mask option.
Schmitt trigger input
2 pins
"H" level
Hi-Z
PF6/T1
PF7/T2
PG0/PWM0
PG1/PWM1
PG2/PWM2
PG3/PWM3
PG4/DA0
PG5/DA1
Port F
Pin
Circuit format
2 pins
8 pins
Port F
Port G
6 pins
Port G
Port H
AA
Page 10
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CXP913040
2 pins
Hi-Z
Hi-Z
When reset
CS0
SI0
PI0/SI2
Hi-Z
PI1/SO2
PI2/SCK2
IP
SIO
Schmitt trigger input
SO0 output enable
SO0 from SIO
SCK0 output enable
Internal serial clock from SIO
IP
External serial clock to SIO
Schmitt trigger input
Data bus
RD (Port I)
Port I direction
Port I data
IP
(Every bit)
"0" when reset
SIO
Schmitt trigger input
MPX
Port I data
IP
Data bus
RD (Port I)
Port I function
selection
A
MPX
Schmitt trigger input
SIO
"0" when reset
SIO
Port I direction
"0" when reset
Note) Only PI2 is Schmitt trigger input.
SIO (PI2 only)
1 pin
Hi-Z
Hi-Z
SO0
SCK0
Pin
Circuit format
1 pin
2 pins
1 pin
Port I
Port I
A
Page 11
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CXP913040
Hi-Z
Oscillation
Hi-Z
When reset
PI3/CS2/PO
PI4/PCK/OSCI
PI5/OSCO
Hi-Z
PI6/XOUT
MPX
Port I data
IP
Data bus
RD (Port I)
Port I direction
Port I function
selection
General-purpose prescaler
"0" when reset
"0" when reset
Schmitt trigger input
SIO
IP
OSCI
OSCO
Port I function
selection
"0" when reset
General-purpose prescaler
MPX
IP
Data bus
RD (Port I)
Port I function
selection
Clock generator
General-purpose prescaler
"0" when reset
Pin
Circuit format
2 pins
1 pin
1 pin
Port I
Port I
Port I
Fig. 1.
IP
RD (Port I)
Data bus
General-purpose prescaler
PI4/PCK
or PI5
Note) The circuit format in Fig. 1 or Fig. 2 can be selected with the mask option.
Fig. 2.
Page 12
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CXP913040
Hi-Z
Oscillation
When reset
AN1 to AN3
PI7/AN0
EXTAL
XTAL
Port J data
IP
Data bus
RD (Port J)
Port J direction
Port J input selection
"0" when reset
"0" when reset
Input multiplexer
A/D converter
Standby release
Hi-Z
PJ0/AN4/KS8
to
PJ7/AN11/KS15
"L" level
RST
IP
A/D converter
Input multiplexer
Hi-Z
IP
A/D converter
Input multiplexer
Port I function selection
"0" when reset
Data bus
RD (Port I)
IP
Schmitt trigger input
Pull-up resistor
Mask option
OP
Emulator (CXP913000 only)
Pin
Circuit format
2 pins
1 pin
3 pins
Port J
1 pin
8 pins
Port I
EXTAL
XTAL
IP
Stop signal
• Diagram shows circuit
composition during
oscillation.
• Feedback resistor is
removed during
stop mode.
Page 13
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CXP913040
∗1
AVDD and VDD must be the same voltage.
∗2
VIN and VOUT must not exceed VDD + 0.3V.
∗3
N-ch transistors of PD and PE output ports are the large current drive transistors.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may
adversely affect the reliability of the LSI.
Supply voltage
Input voltage
Output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
VDD
AVDD
AVSS
VIN
VOUT
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
–0.3 to +7.0
AVss to +7.0
∗1
–0.3 to +0.3
–0.3 to +7.0
∗2
–0.3 to +7.0
∗2
–5
–50
15
20
130
–20 to +75
–55 to +150
380
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
Total for all output pins
All pins excluding large current output pins
Large current output pins
∗3
Total for all output pins
Item Symbol Rating Unit Remarks
Absolute Maximum Ratings (VSS = 0V reference)
Page 14
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CXP913040
Analog voltage
High level input
voltage
Low level input
voltage
Operating temperature
Supply voltage
5.5
5.5
5.5
5.5
VDD
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.2VDD
0.8
0.4
+75
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
Item Symbol Min. Max. Unit Remarks
2.7
2.7
2.5
2.7
0.7VDD
0.8VDD
2.2
VDD – 0.4
0
0
0
–0.3
–20
AVDD
VIH
VIHS
VIHTS
VIHEX
VIL
VILS
VILTS
VILEX
Topr
Guaranteed operation range for high-speed
mode (1/2 frequency dividing clock)
Guaranteed operation range for low-speed
mode (1/16 frequency dividing clock)
Guaranteed data hold range during stop mode
∗1
∗2
CMOS Schmitt trigger input
∗3
TTL Schmitt trigger input
∗4, ∗7
EXTAL
∗5
∗2
∗2, ∗6
CMOS Schmitt trigger input
∗3
TTL Schmitt trigger input
∗4, ∗7
EXTAL
VDD
∗1
AVDD and VDD must be the same voltage.
∗2
PC, PD, PE, PI1, PI3 to PI7, PJ for normal input port
∗3
CS0, SI0, SCK0, RST, PF0/EC0/INT0, PF1/EC2/INT1, PF2/CS1/NMI/CINT, PF3/SI1/INT2, PF5/SCK1,
PG6/RFG0, PG7/RFG1, PH (PH2 and PH3 when CMOS Schmitt trigger input is selected with the mask
option), PI0/SI2, PI2/SCK2.
∗4
PH2 and PH3 (when TTL Schmitt trigger input is selected with the mask option).
∗5
Specified only during external clock input.
∗6
When the supply voltage (VDD) is within the range of 2.7 to 3.6V.
∗7
When the supply voltage (VDD) is within the range of 4.5 to 5.5V.
Recommended Operating Conditions
(VSS = 0V reference)
Page 15
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CXP913040
(Ta = –20 to +75°C, VSS = 0V reference)DC Characteristics
Item
High level
output
voltage
VOH
PA to PE,
PF6 to PF7,
PG0 to PG5,
PI0, PI3, PI6, PJ
PF4, PF5, PI1,
PI2, SO0, SCK0
PA to PC,
PF4 to PF7,
PG0 to PG5,
PI0 to PI3,
PI6, PJ,
SO0, SCK0,
RST
∗1
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 2.7V, IOH = –0.15mA
VDD = 2.7V, IOH = –0.5mA
VDD = 4.5V, IOH = –4.0mA
VDD = 3.0V, IOH = –4.0mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 2.7V, IOL = 1.2mA
VDD = 2.7V, IOL = 1.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 2.7V, IOL = 5.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 3.6V, VIH = 3.6V
VDD = 5.5V, VIL = 0.4V
VDD = 3.6V, VIL = 0.3V
VDD = 5.5V, VIL = 0.4V
VDD = 3.6V, VIL = 0.3V
20MHz crystal oscillation
(C1 = C2 = 10pF),
VDD = 5V ± 10%
20MHz crystal oscillation
(C1 = C2 = 10pF),
VDD = 3.3V ± 0.3V
20MHz crystal oscillation
(C1 = C2 = 10pF),
VDD = 5V ± 10%, Sleep mode
20MHz crystal oscillation
(C1 = C2 = 10pF),
VDD = 3.3V ± 0.3V, Sleep mode
VDD = 5.5V, Stop mode
VDD = 3.6V, Stop mode
Clock 1MHz
0V for all pins excluding
measured pins
4.0
3.5
2.4
2.0
3.6
2.0
0.5
0.3
–0.5
–0.3
–1.5
–0.9
40
22
8
4.5
10
0.4
0.6
0.3
0.5
1.5
1.0
40
20
–40
–20
–400
–200
65
40
14
8
10
10
20
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
µA
µA
pF
PD, PE
EXTAL
RST
∗2
PA to PJ,
AN1 to AN3,
CS0, SI0, SO0,
SCK0, RST
∗2
VDD, VSS
Pins other
than VDD, VSS,
AVDD, AVSS
VOL
IIHE
IILE
IILR
IIZ
IDD
∗4
IDDS1
∗5
IDDS2
CIN
Low level
output
voltage
Input current
I/O leakage
current
Supply
current
∗3
Input
capacitance
Symbol Pin Conditions Min. Typ. Max. Unit
VDD = 5.5V, VI = 0, 5.5V
VDD = 3.6V, VI = 0, 3.6V
±10
±10
µA
µA
Page 16
– 16 –
CXP913040
∗1
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock
control register (CLC: 0002FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
EXTAL
t
XH tXLtCF tCR
0.4V
V
DD – 0.4V
1/fc
A
External clock
EXTAL
XTAL
74HC04
A
EXTAL
XTAL
Crystal oscillation
PF0/EC0
PF1/EC2
t
EH tELtEF tER
0.2VDD
0.8VDD
AC Characteristics
(1) Clock timing
System clock
frequency
System clock input
pulse width
System clock input
rise time, fall time
Event count input
clock pulse width
Event count input
clock rise time,
fall time
fC
tXH,
tXL
tCR,
tCF
tEH,
tEL
tER,
tEF
XTAL,
EXTAL
EXTAL
EXTAL
PF0/EC0,
PF1/EC2
PF0/EC0,
PF1/EC2
Item Symbol Pin Conditions Unit
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig. 1, Fig. 2
External clock drive
Fig. 3
Fig. 3
Min.
1
1
20
20
tsys + 50
∗1
tsys + 100
∗1
20
20
200
200
20
20
MHz
MHz
ns
ns
ns
ns
ns
ns
ms
ms
Max.
(Ta = –20 to +75°C, VSS = 0V reference)
Fig. 1. Clock timing
Fig. 3. Event count clock timing
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
Fig. 2. Clock applied conditions
∗1
RST is specified only in evaluation mode.
∗2
In RST, the input current is specified when pull-up resistor is selected; the leakage current is specified when
no resistor is selected.
∗3
When all output pins are open.
∗4
When the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh) are set to "00"
and the LSI is operated in high-speed mode (1/2 frequency dividing clock).
∗5
When the clock generator output is not selected at PI6.
AA
AAA
Page 17
– 17 –
CXP913040
Chip select transfer
mode
(SCK = output mode)
Chip select transfer
mode
(SCK = output mode)
Chip select transfer
mode
Chip select transfer
mode
Chip select transfer
mode
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
tsys + 100
tsys + 100
2tsys + 200
2tsys + 200
16000/fc
16000/fc
tsys + 100
tsys + 100
8000/fc – 50
8000/fc – 75
100
100
200 – tsys
200 – tsys
tsys + 100
tsys + 100
tsys + 100
tsys + 100
2tsys + 100
2tsys + 125
8000/fc – 50
8000/fc – 75
tsys + 200
tsys + 250
tsys + 200
tsys + 250
tsys + 200
tsys + 250
tsys + 200
tsys + 250
tsys + 100
tsys + 150
50
100
(2) Serial interface (CH0, CH1, CH2) (Ta = –20 to +75°C, VSS = 0V reference)
Item
CS ↓ → SCK
delay time
CS ↑ → SCK
float delay time
CS ↓ → SO
delay time
CS ↑ → SO
float delay time
CS
high level width
SCK
cycle time
SCK high,
low level width
SI input setup time
(for SCK ↑)
SI input hold time
(for SCK ↑)
SCK ↓ → SO
delay time
Minimum interval
time
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH,
tKL
tSIK
tKSI
tKSO
tINT
SCK0,
SCK1,
SCK2
SO0,
SO1,
SO2
SO0,
SO1
SO2
CS0,
CS1
CS2
SCK0,
SCK1
SCK2
SCK0,
SCK1,
SCK2
SCK0,
SCK1,
SCK2
SI0,
SI1,
SI2
SI0,
SI1,
SI2
SO0,
SO1,
SO2
SCK0,
SCK1,
SCK2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol Pin Min Max. UnitConditions
Page 18
– 18 –
CXP913040
Fig. 4. Serial interface CH0, CH1, CH2 timing
tKSI
CS0
CS1
CS2
SCK0
SCK1
SCK2
0.2V
DD
0.8VDD
tWHCS
tDCSK tDCSKF
0.8VDD
0.2VDD
tKCY
tKL tKH
0.8VDD
0.2VDD
SI0
SI1
SI2
t
SIK
tDCSO tKSO tDCSOF
0.8VDD
0.2VDD
SO0
SO1
SO2
SCK0
SCK1
SCK2
0.8VDD
tINT
Input data
Output data
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock
control register CLC (address: 0002FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK output mode, SO output delay time is 150pF when VDD = 5.0V ± 10% and
100pF when VDD = 3.0V ±10%.
Page 19
– 19 –
CXP913040
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = AVDD = AVREF = 2.7 to 5.5V, VSS = AVSS = 0V reference)
Analog input
Linearity error
V
FTVZT
00h
01h
FEh
FFh
Digital conversion value
Ta = 25°C
Operation
mode
Sleep mode
Stop mode
VDD = AVDD = 5.0V
VDD = AVDD = 3.0V
VDD = AVDD = 5.0V
VDD = AVDD = 3.0V
VDD = AVDD = 5.0V
VDD = AVDD = 3.0V
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
–10
–10
4935
2955
200tsys
14tsys
0.9AVDD
0
10
5
4975
2985
0.65
0.45
8
±1.5
±1.5
50
35
5015
3015
AVDD
AVREF
1.2
0.8
10
10
Bits
LSB
mV
mV
µs
µs
V
V
mA
µA
Item
Resolution
Linearity error
Zero transition
voltage
Full-scale
transition voltage
Conversion time
Sampling time
Reference input voltage
Analog input
voltage
AVREF current
VZT
∗1
VFT
∗2
tCONV
tSAMP
VREF
VIAN
IREF
IREFS
AVREF
AN0
to
AN11
AVREF
Symbol Pin Min. Typ. Max.
Unit
Conditions
∗1
VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa.
∗2
VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa.
Note) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock
control register (CLC: 0002FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits =
"11")
Fig. 5. Definition of A/D converter terms
Page 20
– 20 –
CXP913040
External interruption high,
low level width
Reset input low level width
NMI
INT0
INT1
INT2
PD0 to PD7
RST
1
6tsys
∗1
µs
µs
Item Symbol Pin Conditions Min. Max. Unit
tIH,
tIL
tRSL
(4) Interruption and reset input (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference)
0.2VDD
0.8VDD
tIH tIL
NMI
INT0
INT1
INT2
PD0 to PD7
PJ0 to PJ7
(During standby release input)
(Falling edge)
Fig. 6. Interruption input timing
tRSL
0.2VDD
RST
Fig. 7. RST input timing
∗1
tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock
control register (CLC: 0002FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Page 21
– 21 –
CXP913040
External clock input
PCK
tR = tF = 6ns
External clock input
PCK
tR = tF = 6ns
VDD = 5.0V ±10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
33
33
(5) General-purpose prescaler
Item
fPCK
tWH,
tWL
tR,
tF
tPLH
tPHL
tTLH
tTHL
PCK
PCK
PCK
PO
PO
MHz
ns
ns
ns
ns
ns
ns
Symbol Pin Min.
80
130
60
90
50
100
20
40
Typ.
12
12
200
200
130
220
100
150
100
280
40
80
Max. UnitConditions
External clock
input frequency
External clock
input pulse width
External clock
input rise time,
fall time
Prescaler output
delay time
(for PCK ↑)
Prescaler output
rise time, fall time
Note) PO pin load condition: 50pF
Fig. 8. General-purpose prescaler timing
PCK
PO
1/f
PCK
tWH tF
0.2VDD
0.8VDD
tWL
0.5VDD
tR
0.2VDD
0.8VDD
0.5VDD
tPLH
tTLH tTHL
tPHL
(Ta = –20 to +75°C, Vss = 0V reference)
Page 22
– 22 –
CXP913040
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
VDD = 5.0V ± 10%
VDD = 3.0V ± 10%
(6) Other (Ta = –20 to +75°C, VSS = 0V reference)
Item
tCFH,
tCFL
tDFH,
tDFL
tDPW
tDPR
tRFH,
tRFL
tEIH,
tEIL
tPIH,
tPIL
tPMW
tPMR
tTLH
tTHL
CFG
DFG
DPG
DPG
RFG0
RFG1
EXI0
EXI1
PMI
PMSK
PMSK
XOUT
When tsys
= 2000/fc
When the
load is
50pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol Pin Min.
50
100
20
40
Typ.
100
280
40
80
Max. UnitConditions
CFG input high,
low level width
DFG input high,
low level width
DPG minimum
pulse width
DPG minimum
removal time
RFG input high,
low level width
EXI input high,
low level width
PMI input high,
low level width
PMSK minimum
pulse width
PMSK minimum
removal time
XOUT output rise
time, fall time
tsys +200
tsys +200
1000/fc +200
1000/fc +200
50
50
50
50
tsys +200
tsys +200
tsys +200
tsys +200
tsys +200
tsys +200
tsys +200
tsys +200
tsys +200
tsys +200
Note) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock
control register (CLC: 0002FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits =
"11")
Page 23
– 23 –
CXP913040
Fig. 9. Other timing
0.8VDD
CFG
tCFH tCFL
DFG
tDFH tDFL
RFG0
RFG1
tRFH tRFL
0.8VDD
tDPR tDPW tDPR
DPG
0.2VDD
0.8VDD
0.2VDD
EXI0
EXI1
tEIH tEIL
0.8VDD
0.2VDD
0.8VDD
0.2VDD
PMI
tPIH tPIL
0.8VDD
tPMR tPMW tPMR
PMSK
0.8V
DD
0.2VDD
XOUT
0.8V
DD
0.2VDD
tTLH tTHL
Page 24
– 24 –
CXP913040
Appendix
Fig. 10. Recommended oscillation circuit
C2C1
A
EXTAL
XTAL
Main clock
C
2C1
A
OSCI
OSCO
General-purpose prescaler clock
Mask option
Manufacturer
RIVER ELETEC
CORPORATION
KINSEKI LTD.
Model
HC-49/U03
HC-49/U (-S)
fc (MHz)
12
16
20
12
16
20
10
10 10
10
C1 (pF) C2 (pF) C1 (pF) C2 (pF)
4 4
4 4
Main clock
General-purpose prescaler clock
EXTAL system operating voltage
∗1
Reset pin pull-up resistor
PH2 input format
PH3 input format
PI4/PI5 pin format
2.7 to 5.5V
Non-existent
CMOS Schmitt trigger
CMOS Schmitt trigger
Oscillation circuit
4.5 to 5.5V
Existent
TTL Schmitt trigger
TTL Schmitt trigger
Input pin
Item Selection
∗1
Select 4.5V to 5.5V when this LSI is used with a supply voltage range of 4.5V to 5.5V.
Note 1) Use the general-purpose prescaler clock at 12MHz or less.
Note 2) Crystals and capacitors should be placed near the LSI and wiring should be as short as possible.
Mask option table
AAA
AA
Page 25
– 25 –
CXP913040
1/2 frequency dividing mode
1/4 frequency dividing mode
1/8 frequency dividing mode
1/16 frequency dividing mode
Sleep mode
1/2 frequency dividing mode
1/4 frequency dividing mode
1/8 frequency dividing mode
1/16 frequency dividing mode
Sleep mode
2 3 4 5 6
50
40
30
25
20
15
10
8
6
5
4
3
V
DD – Supply voltage [V]
I
DD
– Supply current [mA]
IDD vs. VDD
(fc = 20MHz, Ta = 25°C, Typical)
0 5 10 15 20
fc – System clock [MHz]
IDD vs. fC
(VDD = 5V, Ta = 25°C, Typical)
I
DD
– Supply current [mA]
40.00
38.00
36.00
34.00
32.00
30.00
28.00
26.00
24.00
22.00
20.00
18.00
16.00
14.00
12.00
10.00
8.00
6.00
4.00
2.00
0.00
Example of Representative Characteristics
Page 26
– 26 –
CXP913040
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42 ALLOY
PACKAGE STRUCTURE
DETAIL A
LQFP-100P-L01
LQFP100-P-1414
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗ 14.0 ± 0.1
75
51
50
26
25
1
76
0.5
0.18 – 0.03
+ 0.08
(0.22)
A
1.5 – 0.1
+ 0.2
0.127 – 0.02
+ 0.05
0.5 ± 0.2
(15.0)
0° to 10°
0.1 ± 0.1
0.5 ± 0.2
100
0.1
NOTE: Dimension “∗” does not include mold protrusion.
0.8g
0.13
M
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