Datasheet CXP87948, CXP87940 Datasheet (Sony)

CXP87940/87948

CMOS 8-bit Single Chip Microcomputer

Description

The CXP87940/87948 is a CMOS 8-bit single chip
microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuit, PWM
output, VISS/VASS circuit, 32kHz timer/counter,
remote control reception circuit, VSYNC separator and
the measurement circuit which measures signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port.

Also the CXP87940/87948 provides sleep/stop
functions which enable to lower power consumption.

Features

• A wide instruction set (213 instructions) which covers various types of data

— 16-bit operation/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation (4.5V to 5.5V)

122µs at 32kHz operation (2.7V to 5.5V)

• Incorporated ROM capacity 40K bytes (CXP87940), 48K bytes (CXP87948)

• Incorporated RAM capacity 1376 bytes

• Peripheral functions

— A/D converter 8 bits, 12 channels, successive approximation method

(Conversion time of 20.0µs at 16MHz)

— Serial Interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel

Incorporated 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
Incorporated two-wire 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,

32kHz timer/counter

— High-precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable

RTG: 5 pins, 2 channels

— PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency of 62kHz at 16MHz)

DA gate pulse output: 13 bits, 4 channels
— Servo input control Capstan FG, drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14 bits
— VISS/VASS circuit Pulse duty auto detection circuit
— Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO

• Interruption 22 factors, 15 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 100-pin plastic QFP

• Piggyback/evaluator CXP87800 100-pin ceramic PQFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Structure

Silicon gate CMOS IC

100 pin QFP (PIastic)

– 1 –

E96X01-PS

CXP87940/87948

Vss

V

DD

MP
RST
XTAL

EXTAL
TX
TEX

INT2

2

INT1/NMI

INT0

PA0 to PA7

PB0 to PB7

PC0 to PC7

8

PORT A8PORT B8PORT C

CLOCK

GENERATOR/

SYSTEM CONTROL

SPC700

CPU CORE

PD0 to PD7

PE0 to PE1

PE2 to PE7

2

8

PORT D

6

PORT E

RAM

1376 BYTES

ROM

40K/48K BYTES

INTERRUPT CONTROLLER

PF4 to PF7

PF0 to PF3

4

PG0 to PG7

PH0 to PH7

4

PORT F8PORT G8PORT H7PORT I

32kHz

PRESCALER/

TIME BASE TIMER

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

PI1 to PI7

REALTIME

2

PJ0 to PJ7
8

PORT J

CH1

PULSE

CH0

GENERATOR

RAM

PATTERN

GENERATOR

PROGRAMMABLE

5

19

RTO3 to RTO7

PPO0 to PPO18

2

AVss

AV

REF

AV

DD

A/D CONVERTER

12

AN0 to AN11

Block Diagram

FIFO

(CH2)

SERIAL

INTERFACE UNIT

CS0

SCL1

SCL0

SDA0

SDA1

RAM

(CH0)

SERIAL

SERIAL

INTERFACE UNIT

SO0

SCK0

SI1

SI0

2

FIFO

(CH1)

INTERFACE UNIT

SO1

8 BIT TIMER 1

8 BIT TIMER/COUNTER 0

EC

SCK1

TO/DDO

2

2

SERVO INPUT

VSYNC SEPARATOR

DRUM

CAPSTAN

DFG

CFG

EXI1

EXI0

SYNC1

SYNC0

– 2 –

3

CONTROL

CTL

DPG

PBCTL

FIFO

VISS/VASS

REMOCON INPUT

RMC

14 BIT PWM GENERATOR

PWM

4

2

12 BIT PWM GENERATOR CH1

12 BIT PWM GENERATOR CH0

ADJ

DAB1

DAA1

DAB0

DAA0

PWM1

PWM0

CKOUT

Pin Assignment (Top View)

PB7/PPO15

PB6/PPO14

PA2/PPO2

PA1/PPO1

PA0/PPO0

PA5/PPO5

PA4/PPO4

PA3/PPO3

NC

PA7/PPO7

PA6/PPO6

DD

V

SS

V

TX

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/DDO/ADJ

CXP87940/87948

PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10

PB1/PPO9

PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3

PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4

PD3/SDA1
PD2/SDA0

PD1/SCL1
PD0/SCL0

10

11
12
13
14
15
16
17
18
19
20

21

22

23

24

25

26

27

28
29
30

100

99

98

1

2
3
4

5
6
7
8
9

32

31

33

97

34

96

35

95

36

94

37

93

38

92

39

91

40

90

41

89

42

88

43

87

44

86

45

85

46

47

84

48

83

82

49

81

50

80

78
77
76
75
74

70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

79

73
72
71

PI6/SO1
PI7/SI1
PE0/INT0/CKOUT
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AVDD
AVREF
AVSS
PF4/AN8

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

SS

V

XTAL

CS0

EXTAL

SI0

Note) 1. NC (Pin 90) is always connected to VDD.

2. Vss (Pins 41 and 88) are both connected to GND.

3. MP (Pin 39) is always connected to GND.

– 3 –

SO0

SCK0

PF7/AN11

PF5/AN9

PF6/AN10

Pin Description

Symbol I/O Description

(Port A)

PA0/PPO0

to

PA7/PPO7

Output/
Real-time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)

PB0/PPO8

to

PB7/PPO15

Output/
Real-time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

CXP87940/87948

Programmable pattern generator (PPG)
output.
Functions as high-precision real-time
pulse output port.
PB0 and PB2 can be 3-state controlled
with PPG.
(19 pins)

PC0/PPO16

to

PC2/PPO18

PC3/RTO3

to

PC7/RTO7
PD0/SCL0

PD1/SCL1
PD2/SDA0

PD3/SDA1
PD4 to PD7

PE0/INT0/
CKOUT

PE1/EC/INT2

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0

I/O/
Real-time
output

I/O/
Real-time
output

I/O

Input/Input/Output

Input/Input/Input

Output/Output
Output/Output
Output/Output
Output/Output
Output/Output

(Port C)
8-bit I/O port. I/O can be set
in a unit of single bits.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)

Real-time pulse generator (RTG) output.
Functions as high-precision real-time
pulse output port. PC3 can be 3-state
controlled with RTG. (5 pins)

(Port D)
8-bit I/O port. I/O can be set in a unit of
single bits for upper 4 bits.
Can drive 12mA sink current.
Lower 4-bit output is N-ch open drain.
(8 pins)

Input to request external
interruption.
Active at the falling edge.

(Port E)
8-bit port.

External event
input for
timer/counter.

Input to request external interruption.
Active at the falling edge.

Lower 2 bits
are for inputs;
upper 6 bits

PWM outputs.
(2 pins)

are for outputs.
(8 pins)

DA gate pulse outputs.
(4 pins)

Serial clock (CH2) I/O.
(2 pins)

Serial data (CH2) I/O.
(2 pins)

System clock
frequency dividing
output.

PE7/DAB1
AN0 to AN3
PF0/AN4

to

PF3/AN7
PF4/AN8

to

PF7/AN11
SCK0
SO0
SI0
CS0

Output/Output
Input

Input/Input

Output/Input

I/O
Ouput
Input
Input

Analog inputs to A/D converter. (12 pins)
(Port F)

8-bit port. Lower 4 bits are for inputs; upper 4 bits are for
outputs.
Lower 4 bits also serve as standby release input pin.
(8 pins)

Serial clock (CH0) I/O.
Serial data (CH0) output.
Serial data (CH0) input.
Serial chip select (CH0) input.

– 4 –

Symbol I/O Description

CXP87940/87948

PG0/CFG
PG1/DFG
PG2/DPG

PG3/PBCTL
PG4/SYNC0

PG5/SYNC1
PG6/EXI0
PG7/EXI1

PH0 to PH7

PI1/RMC
PI2/PWM
PI3/TO/

DDO/ADJ
PI4/INT1/

NMI
PI5/SCK1

Input/Input
Input/Input
Input/Input

Input/Input
Input/Input

Input/Input
Input/Input
Input/Input

Output

I/O/Input
I/O/Output
I/O/Output/

Output/Output
I/O/Input/Input
I/O/I/O

Capstan FG input.
Drum FG input.
Drum PG input.

(Port G)
8-bit input port.
(8 pins)

Playback CTL pulse input.
External event input for timer/counter.

Composite sync signal input.
(2 pins)

External input to FRC capture unit.
(2 pins)

(Port H)
8-bit output port. N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)

Remote control reception circuit input.
14-bit PWM output.

(Port I)
7-bit I/O port.
I/O port can be
set in a unit of
single bits.
(7 pins)

Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output.

Input to request external interruption and
non-maskable interruption. Active at the falling edge.

Serial clock (CH1) I/O.
PI6/SO1
PI7/SI1

PJ0 to PJ7

EXTAL
XTAL
TEX
TX

RST
MP
AVDD
AVREF
AVss
VDD
NC
Vss

I/O/Output
I/O/Input

I/O

Input
Output
Input
Output

Input
Input

Input

Serial data (CH1) output.

Serial data (CH1) input.

(Port J)
8-bit I/O port. I/O and standby release input function can be set in a
unit of single bits.

Connects a crystal oscillator for system clock. When supplying the
external clock, input the external clock to EXTAL and input the
opposite phase clock to XTAL .

Connects a crystal oscillator for 32kHz timer/counter clock. The 32kHz
crystal oscillator is inserted between TEX and TX. When used as event
input, connect the clock source to TEX and leave TX open.

System reset; active at Low level.
Test mode input. Always connect to GND.
Positive power supply of A/D converter.
Reference voltage input of A/D converter.
GND of A/D converter.
Positive power supply. Connect VDD pin to VDD.
No connected. Connect to VDD in normal operation.
GND. Connect both Vss pins to GND.

– 5 –

A

Input/Output Circuit Formats for Pins

CXP87940/87948

Pin

PA0 /PPO0

to

PA7/PPO7
PB4/PPO12

to

PB7/PPO15

12 pins

PB0/PPO8
PB2/PPO10

Port A
Port B

Data bus

PPO data

Ports A, B data

RD (Ports A, B)

PPO8, PPO10 data

PB0, PB2 data

Circuit format

Output becomes active from high
impedance by data writing to port register.

When reset

Hi-Z

Hi-Z

2 pins

PB1/PPO9
PB3/PPO11

2 pins

Data bus

RD (Port B)

PPO9, PPO11 data

PPG control
status register
bit 0
3-state control selection

AA

PPO9, PPO11 data

PB1, PB3 data

Data bus

RD (Port B)

Output becomes active from high
impedance by data writing to port register.

Hi-Z

Output becomes active from high
impedance by data writing to port register.

– 6 –

CXP87940/87948

AAA

AAA

A

AAA

AAA

AAA

PC0/PPO16

to

PC2/PPO18
PC5/RTO5

to

PC7/RTO7

6 pins

Port C

Data bus

PPO, RTO data

Port C data

Port C direction

“0” when reset

RD (Port C)

RTO3 data

PC3 data

Circuit format

When resetPin

Input
protection
circuit

Hi-Z

IP

PC3/RTO3

1 pin

PC4/RTO4

1 pin

PC3 direction

“0” when reset

Data bus

RD (Port C)

RTO4 data

RTG interruption
control register

AAA

bit 7
3-state control selection

“0” when reset

RTO4 data

PC4 data

PC4 direction

“0” when reset

Data bus

RD (PortC)

Hi-Z

IP

Hi-Z

IP

RTO data is OR-gate data of CH0 and CH1.

– 7 –

CXP87940/87948

PD0/SCL0
PD1/SCL1
PD2/SDA0
PD3/SDA1

4 pins

Port D

SCL, SDA

Serial interface CH2
output enable

Port D data

Data bus

RD (Port D)

SCL, SDA
(Serial interface CH2 circuit)

Port D

Circuit format

∗

IP

Schmitt input

BUS SW

To another serial CH2 pin

∗

Large current 12mA

When resetPin

Hi-Z

PD4 to PD7

4 pins

PE0/INT0/
CKOUT

1 pin

Port D data

Port D direction

“0” when reset

Data bus

Port E

Data bus

Interruption circuit

RD (Port D)

ESL0

Port E selection

ESL1

RD (Port E)

PS1
PS2
PS3

10
11

01

MPX

∗

IP

∗

Large current 12mA

IP

Hi-Z

Hi-Z

– 8 –

CXP87940/87948

PE1/EC/INT2

1 pin

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

Port E

Port E

Data bus

DA gate output,
PWM output

Hi-Z control

Port/DA output
selection

“0” when reset

IP

Port E data

RD (Port E)

Circuit format

RD (Port E)

MPX

When resetPin

Data bus

Hi-Z

Interruption circuit/
event counter

Hi-Z

PE6/DAB0
PE7/DAB1

2 pins

AN0 to AN3

4 pins

Port E

Hi-Z control

Data bus

DA gate output

Port E data

Port/DA output
selection

“1” when reset

RD (Port E)

Input multiplexer

IP

MPX

High level

Hi-Z

A/D converter

– 9 –

CXP87940/87948

PF0/AN4

to

PF3/AN7

4 pins

PF4/AN8

to

PF7/AN11

4 pins

PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1

Port F

Port F

Data bus

Port G

Circuit format

Input multiplexer

IP

RD (Port F)

Port F data

RD
(Port F)

Note) For PG4/SYNC0, PG5/SYNC1, CMOS Schmitt input and TTL Schmitt
input can be selected with the mask option.

Port/AD
selection

“0” when reset

Schmitt input

IP

A/D converter

RD (Port G)

A/D converter

Data bus

IP

Input multiplexer

Servo input

Data bus

When resetPin

Hi-Z

Hi-Z

Hi-Z

8 pins

PH0 to PH7

8 pins

Port H

Data bus

Port H data

RD (Port H)

∗

∗

Large current 12mA

Medium drive voltage 12V

Hi-Z

– 10 –

CXP87940/87948

A

A

AAA

PI2/PWM
PI3/TO/
DDO/ADJ

2 pins

PI1/RMC
PI4/INT1/NMI
PI7/SI1

3 pins

Port I

Port I

PI2...14-bit PWM
PI3...Timer/counter,
CTL duty detection circuit,
32kHz timer

Port I direction
“0” when reset

Data bus

RD (Port I)

Data bus

PI1...Remote control circuit
PI4...Interruption circuit
PI7...Serial interface CH1

Port I function
selection

“0” when reset

Port I data

Port I data

Port I direction
“0” when reset

RD (Port I)

Circuit format

MPX

Schmitt input

When resetPin

Hi-Z

IP

IP

Hi-Z

PI5/SCK1
PI6/SO1

2 pins

PJ0 to PJ7

Port I

Data bus

Port J

Port I function
selection

“0” when reset

Serial interface
CH1

Port I data

Port I direction
“0” when reset

RD (Port I)

Data bus

Standby release

MPX

Serial interface CH1

Port J data

Port J direction

“0” when reset

RD
(PortJ)

Edge detection

MPX

A

Hi-Z

IP

PI6 is not Schmitt input.

IP

Hi-Z

8 pins

Data bus

RD (Port J direction)

– 11 –

CXP87940/87948

CS0
SI0

2 pins

SO0

1 pin

SCK0

1 pin

Serial interface CH0

Serial interface CH0

Circuit format

Schmitt input

IP

SO0

SO0 output enable

SCK0

SCK0 output enable
SCK0

CS0

Serial interface CH0

SIO

Schmitt input

When resetPin

Hi-Z

Hi-Z

IP

Hi-Z

EXTAL
XTAL

2 pins

TEX
TX

2 pins

RST

1 pin

EXTAL

XTAL

TEX

TX

Mask option

• Shows the circuit

IP

32kHz
timer/counter

IP

Pull-up resistor

Schmitt input

OP

IP

composition during
oscillation.

• Feedback resistor is removed
during stop mode and XTAL
becomes High level.

• Shows the circuit
composition during
oscillation.

• Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs Low level and
TX pin outputs High level.

Oscillation

Oscillation

Low level

– 12 –

CXP87940/87948

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Symbol Unit Unit

–0.3 to +7.0

AVss to +7.0

–0.3 to +0.3

AVss to +7.0

–0.3 to +7.0
–0.3 to +7.0

–0.3 to +15.0

–5

–50

15

∗1

∗1
∗2
∗2

Supply voltage

Input voltage
Output voltage
Medium drive output voltage
High level output current
High level total output current

VDD
AVDD
AVSS
AVREF
VIN
VOUT
VOUTP
IOH
∑IOH

IOL

Low level output current

IOLC

Low level total output current
Operating temperature
Storage temperature

Allowable power dissipation

∗1

AVDD and AVREF should not exceed VDD + 0.3V.

∗2

VIN and VOUT should not exceed VDD + 0.3V.

∗3

The large current output ports are the pins of the port D (PD) and Port H (PH).

∑IOL
Topr
Tstg
PD

20

130

–20 to +75

–55 to +150

600

V
V
V
V
V
V

V
mA
mA

mA
mA

mA

°C
°C

mW

Port H pin

Total of output pins
Ports excluding large current output

(value per pin)
Large current output port (value per pin∗3)
Total of output pins

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding those conditions may adversely
affect the reliability of the LSI.

– 13 –

CXP87940/87948

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

Supply voltage

Analog voltage

High level
input voltage

Low level
input voltage

Operating temperature

VDD

AVDD
VIH

VIHS

VIHTS
VIHEX
VIL
VILS
VILTS
VILEX
Topr

4.5

3.5

2.7

2.0

4.5

0.7VDD

0.8VDD

2.2

VDD – 0.4

0
0
0

–0.3

–20

5.5

5.5

5.5

5.5

5.5
VDD
VDD

5.5

5.5

VDD + 0.3

0.3VDD

0.2VDD

0.8

0.4
+75

Guaranteed operation range for 1/2 and 1/4

V

frequency dividing modes
Guaranteed operation range for 1/16 frequency

V

dividing mode or during sleep mode
Guaranteed operation range by TEX clock

V

Guaranteed data hold range during stop

V

mode

∗1

V

Includes the serial CH2 input

V

CMOS Schmitt input∗3and PE0/INT0 pin

V

CMOS Schmitt input

V

TTL Schmitt input

V

EXTAL pin∗5and TEX pin

V

Includes the serial CH2 input

V

CMOS Schmitt input∗3and PE0/INT0 pin

V

TTL Schmitt input

V

EXTAL pin∗5and TEX pin

V

∗7

∗4

∗4

∗2

∗6

∗2

∗6

°C

∗1

AVDD and VDD should be set to the same voltage.

∗2

Normal input port (PC, PD4 to PD7, PF0 to PF3, PG, PI and PJ), MP pin

∗3

SCK0, RST, EC/INT2, RMC, INT1/NMI, SCK1 and SI1

∗4

PG4 and PG5 (When TTL Schmitt input is selected with mask option)

∗5

Specifies only when the external clock is input.

∗6

Specifies only when the external event count clock is input.

∗7

CS0, SI0, and PG (For PG4 and PG5, when CMOS Schmitt input is selected with mask option.)

– 14 –

Electrical Characteristics

CXP87940/87948

DC Characteristics (VDD = 4.5 to 5.5V)

Item Symbol Pins Conditions Min.

High level
output voltage

VOH

PA to PC,
PD4 to PD7,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0

Low level
output voltage

VOL

PD, PH
PD0 to PD3

(SCL0, CSL1
SDA0, SDA1)

IIHE

EXTAL

IILE

Input current

IIHT

TEX

IILT

∗1

IILR

RST

PA to PG,

I/O leakage
current

IIZ

PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST

Open drain
output leakage
current (in N-CH
Tr off state)

ILOH

PH

PD0 to PD3

Serial interface
CH2 bus switch
connection
impedance

RBS

SCL0: SCL1

SDA0: SDA1
(in output Tr off
state)

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA

VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA

VDD = 4.5V, IOL = 12.0mA
VDD = 4.5V, IOL = 3.0mA
VDD = 4.5V, IOL = 6.0mA

VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V

VDD = 5.5V,
VIL = 0.4V

VDD = 5.5V,
VI = 0, 5.5V

∗1

VDD = 5.5V
VOH = 12V

VDD = 5.5V
VOH = 5.5V

VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V

(Ta = –20 to +75°C, Vss = 0V reference)

Typ.

4.0

3.5

0.5

–0.5

0.1
–0.1
–1.5

Max. Unit

V
V

0.4

0.6

1.5

0.4

0.6
40

–40

10

–10

–400

±10

50

10

120

V
V

V
V

V
µA
µA
µA
µA
µA

µA

µA

µA

Ω

– 15 –

CXP87940/87948

Item Symbol Pins Conditions

1/2 frequency dividing clock operation

IDD1

VDD = 5.5V, 16MHz crystal
oscillation (C1 = C2 = 16pF)

VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)

Sleep mode

VDD = 5.5V, 16MHz crystal

Supply
current

∗2

IDD2

IDDS1

VDD

oscillation (C1 = C2 = 16pF)

IDDS2

VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)

Stop mode

IDDS3

VDD = 5.5V, termination of 16MHz
and 32kHz crystal oscillation

PC, PD,
PE0, PE1,
PF, PG,
PI1 to PI7,

Input
capacity

CIN

PJ, CS0,
SI0, SCK0,
AN0 to AN3,

Clock 1MHz
0V for all pins excluding measured
pins

EXTAL,
XTAL, TEX,
TX, MP,
RST

Min.

Typ. Max. Unit

36

60

2.8

10

10

50

100

8

30

10

20

mA

µA

mA

µA

µA

pF

∗1

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.

∗2

When all output pins are open.

– 16 –

A

A

A

AC Characteristics
(1) Clock timing

CXP87940/87948

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions UnitMin. Typ.

System clock frequency
System clock input

pulse width
System clock input

rise and fall times
Event count input clock

pulse width
Event count input clock

rise and fall times
System clock frequency
Event count input clock

pulse width
Event count input clock

rise and fall times

∗1

tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper 2 bits

(CPU clock selection).

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

fC

tTL,
tTH

tTR,
tTF

XTAL
EXTAL

XTAL
EXTAL

XTAL
EXTAL

EC

EC
TEX

TX
TEX

TEX

Fig. 1,
Fig. 2

Fig. 1,
Fig. 2 (External clock drive)

Fig. 1, Fig. 2
(External clock drive)

Fig. 3

Fig. 3

Fig. 2 VDD = 2.7 to 5.5V
(32kHz clock applied condition)

Fig. 3

Fig. 3

1

28

4tsys

10

∗1

32.768

Max.

16

200

20

20

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

MHz

ns

ns

ns

ns

kHz

µs

ms

Fig. 1. Clock timing

EXTAL

Fig. 2. Clock applied condition

Crystal oscillation
Ceramic oscillation

EXTAL

AA

C

1 C2

Fig. 3. Event count clock timing

TEX
EC

XTAL

1/fc

t

XH tXLtCF tCR

32kHz clock applied condition

External clock

EXTAL

AA

74HC04

XTAL

crystal oscillation

TEX

AA

C

1 C2

DD – 0.4V

V

0.4V

TX

0.8VDD

0.2VDD

t

EH tELtEF tER

tTH tTLtTF tTR

– 17 –

CXP87940/87948

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

CS0 ↓ → SCK0
delay time

CS0 ↑ → SCK0
floating delay time

CS0 ↓ → SO0
delay time

CS0 ↓ → SO0
floating delay time

CS0
High level width

SCK0
cycle time

SCK0
High and Low level widths

SI0 input setup time
(for SCK0 ↑)

SI0 input hold time
(for SCK0 ↑)

SCK0 ↓ → SO0 delay time

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0

SCK0

SO0

SO0

CS0

SCK0

SCK0

SI0

SI0

SO0

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode
Input mode

Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc – 100

–tsys + 100

200

2tsys + 100

100

Max. UnitCondition

tsys + 200

tsys + 200

tsys + 200

tsys + 200

2tsys + 200

100

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper

2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.

– 18 –

Fig. 4. Serial transfer CH0 timing

CS0

DD

0.2V

CXP87940/87948

tWHCS

0.8VDD

tKCY

SCK0

SI0

tDCSK tDCSKF

tKL tKH

0.8VDD

0.2VDD

tSIK

tKSI

0.8VDD

Input

data

0.2VDD

0.8VDD

SO0

t

DCSO tKSO tDCSOF

Output

data

– 19 –

DD

0.8V

0.2VDD

CXP87940/87948

Serial transfer (CH1) (SIO mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Min. Max. UnitCondition

SCK1 cycle time

SCK1 High and Low
level widths

SI1 input setup time
(for SCK1 ↑)

SI1 input hold time
(for SCK1 ↑)

SCK1 ↓ → SO1 delay time

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK1

SCK1

SI1

SI1

SO1

Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode

2tsys + 200

16000/fc

tsys +100

8000/fc – 50

100
200

tsys + 200

100

tsys + 200

100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper

2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Fig. 5. Serial transfer CH1 timing (SIO mode)

SCK1

SI1

tKL tKH

tSIK tKSI

Input data

tKSO

KCY

t

0.8VDD

0.2V

DD

0.8VDD

0.2VDD

SO1

0.8VDD
Output data

0.2VDD

– 20 –

CXP87940/87948

Serial transfer (CH1) (Special mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit
SO1 cycle time
SI1 data setup time

SI1 data hold time

∗1

tLCY is specified only when serial mode register (CH1) (SIOM1: 05FZH) lower 2 bits (SO1 clock selection)

tLCY
tLSU

tLHD

SO1
SI1

SI1
SI1

∗1

104 µs

2
2

µs
µs

are set at 104µs.

Note) The load of SO1 pin is 50pF + 1TTL.

Fig. 6. Serial transfer CH1 timing (Special mode)

SO1

SI1

tLCY

Start bit Output data bit

tLCY/2

LCY

t

tLSU tLHD

Input

data bit

0.5VDD

0.8VDD

0.2VDD

– 21 –

CXP87940/87948

Serial transfer (CH2) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

SCL0, SCL1 clock frequency
Bus-free time before starting transfer

Hold time for starting transfer
Clock Low level width

Clock High level width
Setup time for repeated transfers

Data hold time

Data setup time

SDA0, SCL0, SDA1, SCL1 rise time

SDA0, SCL0, SDA1, SCL1 fall time

Setup time for transfer completion

Symbol Pin Condition Min. Max. Unit

fSLC

tBUF

tHD; STA
tLOW

tHIGH
tSU; STA

tHD; DAT

tSU; DAT

tR

tF

tSU; STO

SCL0, SCL1
SDA0, SCL1

SDA0, SCL1
SDA0, SCL1

SDA1, SCL1
SCL0, SCL1
SCL0, SCL1
SDA0, SCL0

SDA0, SCL1
SDA0, SCL0

SDA1, SCL1
SDA0, SCL0

SDA1, SCL1
SDA0, SCL0

SDA1, SCL1
SDA0, SCL0

SDA1, SCL1
SDA0, SCL0

SDA1, SCL1

2.6

1.0

1.0

1.0

1.0

∗1

0

100

1.6

400

300

300

kHz

µs

µs
µs

µs
µs

µs

ns

ns

ns

µs

∗1

The SCL0, SCL1 fall time (300ns Max.) is not included in the data hold time.

Fig. 7. Serial transfer CH2 timing

SDA0
SDA1

SCL0
SCL1

t

BUF

tHD; STA

SP

tLOW

tFtR

tSU; DATtHIGHtHD; DAT

Fig. 8. Device recommended circuit

Device

RS RS RS RS RP RP

SDA0
(or SDA1)
SCL0
(or SCL1)

Device

tSU; STA

tHD; STA

t

SU; STO

PSt

• A pull-up resistor (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).

• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the

spike noise caused by CRT flashover.

– 22 –

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit

CXP87940/87948

Resolution
Linearity error
Absolute error
Conversion time
Sampling time
Reference input voltage
Analog input voltage

tCONV
tSAMP

VREF
VIAN

AVREF
AN0 to AN11

IREF

AVREF current

AVREF

IREFS

Fig. 9. Definitions of A/D converter terms

FFH
FEH

8

Ta = 25°C

±1±2LSB
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V

160/fADC

12/fADC

AVDD – 0.5

Operation mode

∗1

∗1

AVDD

0

0.6

AVREF

1.0

Sleep mode
Stop mode

10 µA
32kHz operation mode

∗1

fADC indicates the below values due to the peripheral
clock control register (PCC: 05F8H) bit 3 and clock control
register (CLC: 00FEH) upper 2 bits.

Bits

LSB

µs
µs

V
V

mA

Digital conversion value

01H
00

H

Linearity error

Analog input

PCC bit 3

CLC upper 2 bits

00 (φ = fEX/2)
01 (φ = fEX/4)
11 (φ = fEX/16)

0 (φ/2 selection) 1 (φ selection)

fADC = fc/2
fADC = fc/4
fADC = fc/16

fADC = fc
fADC = fc/2
fADC = fc/8

– 23 –

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit

INT0

External interruption
High and Low level widths

tIH
tIL

INT1
INT2
NMI
PJ0 to PJ7

1

µs

CXP87940/87948

Reset input Low level width

Fig. 10. Interruption input timing

INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)

Fig. 11. RST input timing

RST

tRSL

RST

0.2VDD

32/fc

tIH tIL

0.8VDD

tRSL

µs

0.2VDD

(5) Others

Item

CFG input
High and Low level widths

DFG input
High and Low level widths

DPG minimum pulse width
DPG minimum

removal time
PBCTL input

High and Low level widths
EXI input

High and Low level widths

Note 1) tFRC = 1000/fc [ns]
Note 2) tsys indicates three values according to the contents of the clock control register (CLC: 00FEH)

upper 2 bits (CPU clock selection).

Symbol Pins Min.

tCFH
tCFL

tDFH
tDFL

tDPW
trem
tCTH

tCTL
tEIH

tEIL

CFG

DFG
DPG
DPG

PBCTL
EXI0

EXI1

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Conditions

tsys = 2000/fc

tsys = 2000/fc

24tFRC + 200

16tFRC + 200

8tFRC + 200

16tFRC + 200

8tFRC + 200 + tsys

8tFRC + 200 + tsys

Max. Unit

ns

ns

ns
ns

ns

ns

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

– 24 –

Fig. 12. Other timings

CXP87940/87948

tCFH tCFL

CFG

DFG

DPG

0.8VDD

0.2VDD

tDFH tDFL

0.8VDD

0.2VDD

tDPW trem

trem

0.8VDD

PBCTL

EXI0
EXI1

tCTH tCTL

0.8VDD

0.2VDD

tEIH tEIL

0.8VDD

0.2VDD

– 25 –

Appendix

A

A

Fig. 13. Recommended oscillation circuit for SPC 700 series

CXP87940/87948

Manufacturer

RIVER
ELETEC
CO., LTD.

KINSEKI LTD.

(i)

EXTAL

AAA

C

1

HC-49/U03

HC-49/U (-S)

XTAL

Model

Rd

C2

fc (MHz)

8.00

10.00

12.00

16.00

8.00

10.00

12.00

(ii)

TEX

AAA

1 C2

C

C1 (pF) C2 (pF)

10

5

16
16
12

10

5

16
16
12

TX

Rd

Rd (Ω)

0

0

Circuit

example

(i)

(i)

16.00

P3

Mask option table

Item

Reset pin pull-up resistor
Input circuit format

∗1

The input circuit format can be selected for PG4/SYNC0 and PG5/SYNC1, respectively.

∗1

Non-existent

C-MOS Schmitt

32.768kHz

Content

12
30

Existent

TTL Schmitt

12

18

470k

(ii)

– 26 –

Characteristics Curve

CXP87940/87948

(fc = 16MHz, Ta = 25°C, Typical)

10

1

0.1

– Supply current [mA]

DD

I

0.01

(10µA)

3.0 4.0 5.0 6.02.5

IDD vs. VDD

3.5 4.5 5.5

VDD – Supply voltage [V]

1/2 dividing mode
1/4 dividing mode

1/16 dividing mode

Sleep mode

32kHz mode
(instruction)

32kHz
Sleep mode

(VDD = 5.0V, Ta = 25°C, Typical)

40

30

20

– Supply current [mA]

DD

I

10

0

0

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

Sleep mode

51015

fc – System clock [MHz]

– 27 –

Package Outline Unit: mm

100PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

+ 0.4

17.9 ± 0.4

14.0 – 0.01

CXP87940/87948

+ 0.1

0.15 – 0.05

15.8 ± 0.4

A

0.65

SONY CODE
EIAJ CODE

JEDEC CODE

0° to 15°

±0.12

DETAIL A

QFP-100P-L01
∗QFP100-P-1420-A

M

0.15

(16.3)

0.8 ± 0.2

2.75 – 0.15

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL
PACKAGE WEIGHT

EPOXY RESIN
SOLDER PLATING

COPPER / 42 ALLOY

1.4g

+ 0.35

– 28 –