Datasheet CXP974F096 Datasheet (Sony)

Page 1
CMOS 16-bit Single Chip Microcomputer
Description
The CXP974F096 is a CMOS 16-bit microcomputer integrating on a single chip an A/D converter, serial interface, I2C bus interface, timer, PWM output circuit, programmable pattern generator, remote control receive circuit, parallel interface, FLASH ROM interface, and as well as basic configurations like a 16-bit CPU, FLASH EEPROM, RAM, and I/O port.
This LSI also provides the sleep/stop functions that enable lower power consumption.
Features
An efficient instruction set as a controller
— Direct addressing, numerous abbreviated forms,
multiplication and division instructions
Instruction sets for C language and RTOS
— Highly quadratic instruction system, general-
purpose register of 16-bit × 8-pin × 16-bank configuration
Minimum instruction cycle 58.8ns at 34MHz operation (3.0 to 3.6V)
66.7ns at 30MHz operation (2.7 to 3.6V)
Incorporated FLASH EEPROM capacity 384K bytes
Incorporated RAM capacity 23.5K bytes
Peripheral functions
— A/D converter 8-bit 12-analog input, successive approximation system,
3-stage FIFO (Conversion time: 1.55µs at 40MHz)
— Serial interface Asynchronous serial interface (UART)
128-byte buffer RAM, 3 channels
— I2C bus interface 64-byte buffer RAM
(supports master/slave and automatic transfer mode)
— Timers 8-bit timer/counter, 2 channels (with timing output)
16-bit capture timer/counter (with timing output) 16-bit timer, 4 channels, watchdog timer
— PWM output circuit 14-bit PWM, 4 channels
(2-channel of binary output switch function by PPG) — Programmable pattern generator 16-bit output, 64-byte buffer RAM, 1 channel — Remote control receive circuit 8-bit pulse measurement counter, 10-stage FIFO — Parallel interface External register interface (8-bit parallel bus), 4-chip select
Interruption 33 factors, 33 vectors, multi-interruption and priority selection possible
Standby mode Sleep/stop
Package 100-pin plastic QFP
100-pin plastic LQFP
Piggy/evaluation chip CXP971000
Mask ROM CXP974096 Structure
Silicon gate CMOS IC
– 1 –
E00Z18-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP974F096
100 pin QFP (Plastic) 100 pin LQFP (Plastic)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
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CXP974F096
Block Diagram
PA0 to PA7
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE7
PF0 to PF5
PF6, PF7
PH0, PH1,
PH6, PH7
PI0 to PI7
PJ0 to PJ7
SCS0
SO0
SI0
SCK0
SI1
SCS1
SCK1
SO1
SCS2
SO2
SI2
SCK2
T1
PWM0
EC0
RMC
PORT A
16-BIT CAPTURE
TIMER/COUNTER (CH2)
BUFFER
RAM
I
2
C BUS
INTERFACE
UNIT
BUFFER
RAM
SERIAL
INTERFACE
UNIT (CH2)
BUFFER
RAM
SERIAL
INTERFACE
UNIT (CH1)
BUFFER
RAM
SERIAL
INTERFACE
UNIT (CH0)
8
8 20
PORT B
8
PORT C
8
PORT D
8
PG4 to PG74PH2 to PH5
4
PORT E
8
PORT F
6
2
PG0 to PG34
4
PORT G
PK0 to PK4 5
PK5 to PK62
PORT K
PORT HPORT IPORT J
8
8
SPC970
CPU CORE
CLOCK GENERATOR/
SYSTEM CONTROLLER
FLASH
EEPROM
384K
BYTES
RAM
23.5K
BYTES
PWM1
PWM2
PWM3
T2
PRESCALER/
TIME-BASE TIMER
EC2
CINT
SCL
SDA
TxD
RxD
INT0
to INT7
KS0
to KS19
NMI
RST
EXTAL VPP
XTAL
V
DD
VSS
16
A/D
CONVERTER
12
8
REMOCON
FIFO
2CH 14-BIT PWM (PPG)
2CH 14-BIT PWM
4CH 16-BIT TIMER
UART
INTERRUPT CONTROLLER
AN0
to AN11
PPO00
to PPO15
16
D0 to D7
A0 to A15
ADTEN
ADTRG
XCS3
XCS2
XCS1
XCS0
XRD
XWR
AVSS
AVREF
AVDD
8-BIT TIMER/COUNTER (CH0)
8-BIT TIMER (CH1)
2
4
2
3
2
PROGRAMABLE
PATTEERN
GENERATOR
EXT. REGISTERS
INTERFACE
BUFFER RAM FIFO
WATCHDOG TIMER
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CXP974F096
Pin Assignment 1 (Top View) 100-pin QFP package
31 32 33 34 35 36 37 38 39 404142 43 44 45
46
47
48 49 50
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81828384858687888990919293949596979899
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PE7/INT7/CINT
PF0/EC0
PF1/EC2
PF2/SCS1/NMI
PF3/SI1
PF4/SO1
PF5/SCK1
PF6/T1
PF7/T2
RST
V
SS
XTAL
EXTAL
V
DD
PG0/PWM0
PG1/PWM1
PG2/PWM2
PG3/PWM3
PG4/SCS0
PG5/SI0
PH0/SDA PK6/TETA PK5/TETB PK4/ADTRG PK3/ADTEN PK2 PK1 PK0 AV
DD
AVREF AVSS PJ7/AN11/KS11 PJ6/AN10/KS10 PJ5/AN9/KS9 PJ4/AN8/KS8 PJ3/AN7/KS7 PJ2/AN6/KS6 PJ1/AN5/KS5 PJ0/AN4/KS4 PI7/AN3/KS3 PI6/AN2/KS2 PI5/AN1/KS1 PI4/AN0/KS0 Vss PI3/SCK2
51
52
53
54
55
56
PI2/SO2 PI1/SI2 PI0/SCS2 PG7/SCK0 PG6/SO0
PB2/PPO02/A10 PB3/PPO03/A11 PB4/PPO04/A12 PB5/PPO05/A13 PB6/PPO06/A14 PB7/PPO07/A15
PC0/PPO08 PC1/PPO09 PC2/PPO10
PC3/PPO11 PC4/PPO12/XCS3 PC5/PPO13/XCS2 PC6/PPO14/XCS1 PC7/PPO15/XCS0
V
SS
PD0/D0/KS12 PD1/D1/KS13 PD2/D2/KS14 PD3/D3/KS15 PD4/D4/KS16 PD5/D5/KS17 PD6/D6/KS18 PD7/D7/KS19
PE0/INT0
25 26 27 28 29
PE1/INT1 PE2/INT2 PE3/INT3 PE4/INT4 PE5/INT5
30
PE6/INT6
PB1/PPO01/A9
PB0/PPO00/A8
PA7/A7
PA6/A6
PA5/A5
PA4/A4
PA3/A3
PA2/A2
PA1/A1
PA0/A0
VSSVDD
VPP
PH7/XRD
PH6/XWR
PH5/TETC
PH4/RMC
PH3/TxD
PH2/RxD
PH1/SCL
100
Note) 1. VPP (Pin 88) must be connected to NC for Mask ROM.
2. Vss and AVss (Pins 15, 41, 57, 70 and 90) must be connected to GND.
3. VDD and AVDD (Pins 44, 72 and 89) must be connected to VDD. – 4 –
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CXP974F096
Pin Assignment 2 (Top View) 100-pin LQFP package
31 32 33 34 35 36 37 38 39 404142 43 44 45
46
47
48 49 50
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81828384858687888990919293949596979899
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PE7/INT7/CINT
PF0/EC0
PF1/EC2
PF2/SCS1/NMI
PF3/SI1
PF4/SO1
PF5/SCK1
PF6/T1
PF7/T2
RST
V
SS
XTAL
EXTAL
V
DD
PG0/PWM0
PG1/PWM1
PG2/PWM2
PG3/PWM3
PG4/SCS0
PG5/SI0
PH0/SDA
PK6/TETA
PK5/TETB
PK4/ADTRG PK3/ADTEN PK2 PK1 PK0 AV
DD
AVREF AVSS PJ7/AN11/KS11 PJ6/AN10/KS10 PJ5/AN9/KS9 PJ4/AN8/KS8 PJ3/AN7/KS7 PJ2/AN6/KS6 PJ1/AN5/KS5 PJ0/AN4/KS4 PI7/AN3/KS3 PI6/AN2/KS2 PI5/AN1/KS1 PI4/AN0/KS0 Vss PI3/SCK2
51
52
53
54
55
56
PI2/SO2 PI1/SI2 PI0/SCS2
PB4/PPO04/A12 PB5/PPO05/A13 PB6/PPO06/A14 PB7/PPO07/A15
PC0/PPO08 PC1/PPO09 PC2/PPO10
PC3/PPO11 PC4/PPO12/XCS3 PC5/PPO13/XCS2 PC6/PPO14/XCS1 PC7/PPO15/XCS0
V
SS
PD0/D0/KS12 PD1/D1/KS13 PD2/D2/KS14 PD3/D3/KS15 PD4/D4/KS16 PD5/D5/KS17 PD6/D6/KS18 PD7/D7/KS19
PE0/INT0
25
26
27 28 29
PE1/INT1 PE2/INT2 PE3/INT3
30
PE4/INT4
PE5/INT5
PE6/INT6
PB1/PPO01/A9
PB2/PPO02/A10
PB3/PPO03/A11
PB0/PPO00/A8
PA7/A7
PA6/A6
PA5/A5
PA4/A4
PA3/A3
PA2/A2
PA1/A1
PA0/A0
V
SS
VDD
VPP
PH7/XRD
PH6/XWR
PH5/TETC
PH4/RMC
PH3/TxD
PH2/RxD
PH1/SCL
100
PG7/SCK0
PG6/SO0
Note) 1. VPP (Pin 86) must be connected to NC for Mask ROM.
2. Vss and AVss (Pins 13, 39, 55, 68 and 88) must be connected to GND.
3. VDD and AVDD (Pins 42, 70 and 87) must be connected to VDD. – 5 –
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CXP974F096
Pin Functions
Symbol
I/O
Functions
PA0/A0 to PA7/A7
PB0/PPO00/ A8 to PB7/PPO07/ A15
PC0/PPO08 to PC3/PPO11
PC4/PPO12/ XCS3 to PC7/PPO15/ XCS0
PD0/D0/ KS12 to PD7/D7/ KS19
PE0/INT0 to PE6/INT6
PE7/INT7/ CINT
PF0/EC0 PF1/EC2
PF2/SCS1/ NMI
PF3/SI1 PF4/SO1 PF5/SCK1 PF6/T1 PF7/T2
PG0/PWM0 to PG1/PWM1
PG2/PWM2 PG3/PWM3
PG4/SCS0 PG5/SI0 PG6/SO0 PG7/SCK0
Output / Output
Output / Output / Output
I/O / Output
I/O / Output / Output
I/O / I/O / Input
I/O / Input I/O / Input /
Input Input / Input Input / Input /
Input Input / Input Input / Output Input / I/O Output / Output Output / Output
Output / Output
Output / Output I/O / Input
I/O / Input I/O / Output I/O / I/O
(Port A) 8-bit output port. (8 pins)
(Port B) 8-bit output port. PPO value and OR output. (8 pins)
(Port C) 8-bit I/O port. I/O can be specified in 1-bit units. PPO value and OR output. (8 pins)
(Port D) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins)
(Port E) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins)
(Port F) 8-bit port. Lower 6 bits are for input; upper 2 bits are for output. (8 pins)
(Port G) 8-bit port. Lower 4 bits are for output; upper 4 bits are for I/O. Upper 4 bits can be specified in 1-bit units. (8 pins)
External register interface address bus port output data value and OR output. (8 pins)
Programmable pattern generator outputs. (16 pins)
External register interface data bus. (8 pins)
External interrupt inputs. (8 pins)
External event inputs for 8-bit timer/counter. (2 pins)
Serial chip select (CH1) input.
Serial data (CH1) input. Serial data (CH1) output. Serial clock (CH1) I/O. 8-bit timer/counter output. 16-bit capture timer/counter timing output. 14-bit PWM output with output value switch
control by programmable pattern generator. (2 pins)
14-bit PWM output. (2 pins)
Serial chip select (CH0) input. Serial data (CH0) input. Serial data (CH0) output. Serial clock (CH0) I/O.
External register interface address bus. Address width can be extended in 1-bit units. (8 pins)
External register interface chip select signal. Chip select signal output function can be selected in 1-bit units. (4 pins)
External capture input for 16-bit capture timer/counter.
Standby release input function can be specified in 1-bit units. (8 pins)
Non-maskable external interrupt input.
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CXP974F096
Symbol
I/O
Functions PH0/SDA PH1/SCL
PH2/RxD
PH3/TxD
PH4/RMC PH5/TETC PH6/XWR PH7/XRD PI0/SCS2 PI1/SI2 PI2/SO2 PI3/SCK2 PI4/AN0/
KS0 to PI7/AN3/ KS3
PJ0/AN4/ KS4 to PJ7/AN11/ KS11
PK0 to PK2 PK3/ADTEN PK4/ADTRG
PK5/TETB PK6/TETA EXTAL XTAL RST
AVDD
AVREF AVss
VPP VDD Vss
Output / I/O Output / I/O
I/O / Input
I/O / Output
I/O / Input I/O / Input Output / Output Output / Output I/O / Input I/O / Input I/O / Output I/O / I/O
I/O / Input / Input
I/O / Input / Input
I/O I/O / Input I/O / Input
Output / Input Output / Input Input
Input
Input
(Port H) 8-bit port. Lower 2 bits are for large current N-ch open drain outputs; medium 4 bits are for I/O; upper 2 bits are for output. Medium 4 bits can be specified in 1-bit units. (8 pins)
(Port I) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins)
(Port J) 8-bit I/O port. I/O can be specified in 1-bit units. (8 pins)
(Port K) 7-bit port. Lower 5 bits are for I/O; upper 2 bits are for output. Lower 5 bits can be specified in 1-bit units. (7 pins)
Connects a crystal for main clock oscillation. (When the clock is supplied externally, input it to EXTAL and input an opposite phase clock to XTAL.)
System reset. Active at "L" level. Positive power supply for A/D converter. (Must be the same voltage with
VDD.) Reference voltage input for A/D converter. (Must be the same voltage with
VDD.) GND for A/D converter. Positive power supply for FLASH EEPROM rewrite. Positive power supply. (Connect both VDD pins to positive power supply.) GND (Connect all four Vss pins to GND.)
I2C bus interface data I/O. I2C bus interface clock I/O. UART reception data input. (common with data
reception during on-board rewrite boot mode) UART transmission data output. (common with
data transmission during on-board rewrite boot mode)
Remote control signal input. On-board rewrite boot mode setting. (Total 3 pins) External register interface write signal. External register interface read signal. Serial chip select (CH2) input. Serial data (CH2) input. Serial data (CH2) output. Serial clock (CH2) I/O.
Analog input for A/D converter. (12 pins)
A/D converter operation enable input by external trigger.
External trigger input for A/D converter. On-board rewrite boot mode setting.
(Total 3 pins)
Standby release input function can be specified in 1-bit units. (12 pins)
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CXP974F096
I/O Circuit Format for Pins
Pin Circuit format After a reset
PA0/A0 to PA7/A7
Hi-Z
PB0/PPO00/A8 to PB7/PPO07/ A15
Hi-Z
PC0/PPO08 to PC3/PPO11
Hi-Z
A0 to A7
RD
PA register
PA register write
(Undefined after a reset)
Reset
Internal data bus
QS
R
A8 to A15
PPO00 to PPO07
RD
PB register
PB register write
Address width setting
(Undefined after a reset)
("0" after a reset)
Reset
Internal data bus
QS
R
1
MPX
0
PPO08 to PPO11
RD
PC register
Input protection circuit
("0" after a reset)
Internal data bus
PCD register
("0" after a reset)
IP
Page 8
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CXP974F096
PC4/PPO12/ XCS3 to PC7/PPO15/ XCS0
Hi-Z
PD0/D0/KS12 to PD7/D7/ KS19
Hi-Z
PE0/INT0 to PE7/INT7/ CINT
Hi-Z
XCS3 to XCS0
PPO12 to PPO15
XCS output setting
1
MPX
0
RD
PC register
PCD register
Internal data bus
("0" after a reset)
("0" after a reset)
("0" after a reset)
IP
RD
PD register
PDD register
External register I/F
External register I/F
WR (external register area)
Internal data bus
Internal data bus
Internal data bus
External register operation enable
Standby release
("0" after a reset)
("0" after a reset)
RD (external register area)
External register operation enable
IP
CLR
CLR
Large current drive
5mA (V
DD = 2.7 to 3.6V)
RD
PE register
PED register
Internal data bus
INT0 to INT7/CINT
(Undefined after a reset)
("0" after a reset)
CMOS Schmitt input
IP
Pin Circuit format After a reset
Page 9
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CXP974F096
PF0/EC0 PF1/EC2
Hi-Z
PF2/SCS1/ NMI
Hi-Z
PF3/SI1
Hi-Z
PF4/SO1
Hi-Z
PF5/SCK1
Hi-Z
Internal data bus
EC0, EC2
RD
CMOS Schmitt input
IP
PFSL register
("0" after a reset) NMI input enable
("0" after a reset)
Internal data bus
RD
CMOS Schmitt input
SCS1
NMI
IP
PFSL register
("0" after a reset)
Internal data bus
RD
CMOS Schmitt input
SI1
IP
RD
PFSL register
("0" after a reset)
SO1 output enable
SO1
Internal data bus
IP
RD
CMOS Schmitt input
PFSL register
("0" after a reset)
SCK1 output enable
SCK1
Internal data bus
IP
SCK1
Pin Circuit format After a reset
Page 10
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CXP974F096
PF6/T1
"H" level
PF7/T2
"H" level ("H" level at ON resistance of pull-up transistor by a reset.)
PG0/PWM0 to PG3/PWM3
Hi-Z
T1
RD
PFSL register
("1" after a reset)
("0" after a reset)
Internal data bus
1
0
MPX
PF register
PF register write
Reset
QS
R
T2
RD
PFSL register
("1" after a reset)
("0" after a reset)
Internal data bus
1
0
MPX
PF register
Pull-up transistor
approximately 150k (VDD = 2.7 to 3.6V)
PG register write
Reset
QS
R
PWM0 to PWM3
RD
PGSL register
(Undefined after a reset)
("0" after a reset) Internal data bus
1
0
MPX
PG register
Pin Circuit format After a reset
Page 11
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CXP974F096
PG4/SCS0
Hi-Z
PG5/SI0
Hi-Z
PG6/SO0
Hi-Z
RD
PGD register
PGSL register
Internal data bus
SCS0
("0" after a reset)
PG register
(Undefined after a reset)
("0" after a reset)
IP
CMOS Schmitt input
RD
PGD register
PGSL register
Internal data bus
SI0
("0" after a reset)
PG register
(Undefined after a reset)
("0" after a reset)
IP
CMOS Schmitt input
RD
PG register
PGSL register
Internal data bus
(Undefined after a reset)
("0" after a reset)
PGD register
("0" after a reset)
SO0 output enable
SO0
IP
1 MPX 0
1 MPX 0
Pin Circuit format After a reset
Page 12
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CXP974F096
PG7/SCK0
Hi-Z
PH0/SDA PH1/SCL
Hi-Z
PH2/RxD
Hi-Z
RD
PG register
PGSL register
Internal data bus
(Undefined after a reset)
("0" after a reset)
PGD register
("0" after a reset)
SCK0 output enable
CMOS Schmitt input
SCK0
SCK0
IP
1
MPX
0
1
MPX
0
CMOS Schmitt input
RD
PHSL register
Internal data bus
("0" after a reset)
PH register
("1" after a reset)
SDA, SCL
SDA, SCL
IP
1
MPX
0
Large current drive
5mA (VDD = 2.7 to 3.6V)
CMOS Schmitt input
RD
PHL register
PHD register
Internal data bus
RxD
(Undefined after a reset)
("0" after a reset)
IP
Pin Circuit format After a reset
Page 13
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CXP974F096
PH3/TxD
Hi-Z
PH4/RMC
Hi-Z
PH5/TETC
Hi-Z
PH6/XWR PH7/XRD
Hi-Z
RD
PH register
Internal data bus
(Undefined after a reset)
PHD register
("0" after a reset)
TxD output enable
TxD
IP
1
MPX
0
CMOS Schmitt input
RD
PH register
PHD register
Internal data bus
RMC
(Undefined after a reset)
("0" after a reset)
IP
CMOS Schmitt input
RD
PH register
PHD register
Internal data bus
(Undefined after a reset)
("0" after a reset)
IP
XWR, XRD
RD
PH register
PH register write
PHSL register
(Undefined after a reset)
("0" after a reset)
Reset
Internal data bus
QS
R
1
MPX
0
Pin Circuit format After a reset
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CXP974F096
PI0/SCS2
Hi-Z
PI1/SI2
Hi-Z
PI2/SO2
Hi-Z
RD
PID register
PISL register
Internal data bus
SCS2
("0" after a reset)
PI register
(Undefined after a reset)
("0" after a reset)
IP
CMOS Schmitt input
RD
PID register
PISL register
Internal data bus
SI2
("0" after a reset)
PI register
(Undefined after a reset)
("0" after a reset)
IP
CMOS Schmitt input
RD
PI register
PISL register
Internal data bus
(Undefined after a reset)
("0" after a reset)
PID register
("0" after a reset)
SO2 output enable
SO2
IP
1
MPX
0
1
MPX
0
Pin Circuit format After a reset
Page 15
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CXP974F096
PI3/SCK2
Hi-Z
PI4/AN0/KS0 to PI7/AN3/ KS3
Hi-Z
PJ0/AN4/KS4 to PJ7/AN11/ KS11
Hi-Z
RD
PI register
PISL register
Internal data bus
(Undefined after a reset)
("0" after a reset)
PID register
("0" after a reset)
SCK2 output enable
CMOS Schmitt input
SCK2
SCK2
IP
1
MPX
0
1
MPX
0
RD
PID register
PISL register
Internal data bus
Standby release
A/D converter
("0" after a reset)
PI register
(Undefined after a reset)
("0" after a reset)
IP
Input multiplexer
RD
PJD register
PJSL register
Internal data bus
Standby release
A/D converter
("0" after a reset)
PJ register
(Undefined after a reset)
("0" after a reset)
IP
Input multiplexer
Pin Circuit format After a reset
Page 16
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CXP974F096
PK0 to PK2
Hi-Z
PK3/ADTEN PK4/ADTRG
Hi-Z
PK5/TETB
"H" level
PK6/TETA
"H" level ("H" level at ON resistance of pull-up transistor by a reset.)
RD
PK register
PKD register
Internal data bus
(Undefined after a reset)
("0" after a reset)
IP
RD
PK register
PKD register
Internal data bus
ADTEN, ADTRG
(Undefined after a reset)
("0" after a reset)
CMOS Schmitt input
IP
RD
("1" after a reset)
Internal data bus
PK register
PK register write
Reset
QS
R
RD
("1" after a reset)
Internal data bus
PK register
Pull-up transistor
approximately 150k (VDD = 2.7 to 3.6V)
Pin Circuit format After a reset
Page 17
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CXP974F096
XTAL EXTAL
Oscillation
RST
"L" level
(during a reset)
Oscillation stop control
Timing generator
Diagram shows circuit configuration during oscillation.
Feedback resistor is reoved during standby stop mode,
and XTAL is driven at "H" level.
IPEXTAL
XTAL
Pull-up transistor
approximately 30k (VDD = 2.7 to 3.6V)
IP
RST
Mask option
CMOS Schmitt input
OP
Internal reset circuit
Pin Circuit format After a reset
Page 18
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CXP974F096
Absolute Maximum Ratings (Vss = 0V reference)
Item
Supply voltage
Input voltage Output voltage High level output current High level total output current
Low level output current
Low level total output current Operating temperature Storage temperature
Allowable power dissipation
VDD AVDD AVREF AVSS VIN VOUT IOH ΣIOH
IOL
IOLC ΣIOL
Topr Tstg
PD
–0.3 to +4.6
AVSS to +4.6
1
AVSS to +4.6
1
0.3 to +0.3
0.3 to +4.6
2
0.3 to +4.6
2
5.0
50
15.0
20.0 130
30 to +85
55 to +150
600 380
V V V V V
V mA mA
mA
mA mA
°C °C
mW
Output (value per pin) Total for all output pins All pins excluding large
current output pins (value per pin)
Large current output pins
3
(value per pin) Total for all output pins
QFP-100P-L01 LQFP-100P-L01
Symbol Rating Unit Remarks
1
AVDD and AVREF must be the same voltage with VDD.
2
VIN and VOUT excluding PH0 and PH1 must not exceed VDD + 0.3V.
3
The large current drive transistor is N-ch transistor of PD and PH0, PH1.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
Page 19
– 19 –
CXP974F096
Item
Supply voltage
VDD
AVDD
AVREF VIH VIHS VIHEX VIL VILS VILEX Topr
Tpwe
High level input voltage
Low level input voltage
Symbol Min.
2.7
2.0
2.7
2.7
0.7V
DD
0.8V
DD
V
DD – 0.4
0 0
0.3
30
0
3.6
3.6
3.6
3.6 VDD V
DD
V
DD + 0.2
0.2VDD
0.2VDD
0.4 +85
+50
V
V V V V V V V V
°C °C
Guaranteed data hold range during stop mode
112
CMOS Schmitt input
3
EXTAL
4
CMOS Schmitt input
3
EXTAL
4
Recommended operating range of FLASH EEPROM rewrite operation
Max. Unit Remarks
1
AVDD and AVREF must be the same voltage with VDD.
2
PC, PD, PF4, PG6, PH3, PI2, PI4 to PI7, PJ, PK0 to PK2, PWE for normal input port.
3
RST, PE, PF0 to PF3, PF5, PG4, PG5, PG7, PH0 to PH2, PH4, PH5, PI0, PI1, PI3, PK3 and PK4.
4
Specified only during self-oscillation.
Recommended Operating Conditions (Vss = 0V reference)
Operating temperature
Page 20
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CXP974F096
Electrical Characteristics
DC Characteristics 1 (Topr = –30 to +85°C, Vss = 0V reference)
Item
Symbol
Pins Conditions
Min.
Typ. Max. Unit
VDD = 3.0V, IOH = –0.15mA VDD = 2.7V, IOH = –0.15mA VDD = 3.0V, IOH = –0.5mA VDD = 2.7V, IOH = –0.5mA
VDD = 3.0V, I
OH = –1.5mA
V
DD = 2.7V, IOH = –1.5mA
IOL = 1.2mA
IOL = 1.6mA
IOL = 2.0mA
IOL = 3.0mA IOL = 5.0mA
VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIL = 0.3V
VDD = 3.6V, VI = 0, 3.6V
V
DD = 3.6V, VIH = 3.6V
V
OH
VOL
IIHE IILE IILR
IIZ
ILOH
High level output voltage
Low level output voltage
Input current
I/O leakage current
Open drain output leakage current (N-ch Tr. off-state)
PD to PE, PF6, PF7, PG0 to PG5, PH2, PH4, PH5, PI to PJ, PK0 to PK6
PA to PC, PF4, PF5, PG6, PG7, PH3, PH6, PH7, PI2, PI3
PE, PF6, PF7, PG0 to PG5, PH2, PH4, PH5, PI0, PI1, PI4 to PI7, PJ, PK0 to PK6
PA to PC, PF4, PF5, PG6, PG7, PH3, PH6, PH7, PI2, PI3
PD, PH0, PH1
EXTAL
RST
1
PA to PJ, PK0 to PK6, RST
1
PH0, PH1
2.70
2.40
2.30
2.00
2.30
2.00
0.3
0.30.9
0.30
0.50
0.30
0.50
1.00 61
61
250
±31
31
V
V
V
V
V
V
V
V µA µA µA
µA
µA
1
RST specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected.
Page 21
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CXP974F096
Item Symbol Pins Conditions
Min.
Typ. Max. Unit
Clock 1MHz, 0V for all pins excluding measured pins
Clock 1MHz, 0V for all pins excluding measured pins
Clock 1MHz, 0V for all pins excluding measured pins
CIN
COUT
C
I/O
Input capacitance
Output capacitance
I/O capacitance
PF0 to PF3, EXTAL, RST
PA to PB, PF6, PF7, PG0 to PG3, PH6, PH7, PK5, PK6, XTAL
PC to PE, PF4, PF5, PG4 to PG7, PH0 to PH5, PI to PJ, PK0 to PK4
10
10
10
20
20
20
pF
pF
pF
I/O Capacitance
Item Symbol Pins Conditions
Min.
Typ. Max. Unit
VDD = 3.3 ± 0.3V, fEX = fsrc = 40MHz, External clock operation A/D off state, PLL off state
VDD = 3.3 ± 0.3V, fEX = fsrc = 40MHz, External clock operation A/D off state, PLL off state, sleep mode
VDD = 3.6V, stop mode
2
IDD1
2
IDDS2
IDDS3
Supply current
1
VDD, VSS
VDD
, VSS
VDD
, VSS
65
26
75
30
500 350 100
mA
mA
µA
DC Characteristics 2 (Topr = –30 to +85°C, Vss = 0V reference)
85°C or less 75°C or less 50°C or less
1
When all output pins are open.
2
When the upper two bits (PCK1, PCK0) of the clock control register (CLC: 0002FEh) are set to "00" and the LSI is operated in high-speed mode (1/2 frequency dividing clock).
Page 22
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CXP974F096
AC Characteristics
(1) Clock timing (Topr = –30 to +85°C, VDD = 2.7 to 3.6 V, Vss = 0V reference)
Item
Main clock base oscillation frequency
Main clock base oscillation input pulse width
Main clock base oscillation input rise time, fall time
Main clock duty
EXTAL, XTAL
EXTAL, XTAL
EXTAL, XTAL
XTAL
fEX = 40.0MHz Fig.1, Fig.2 External clock drive
fEX = 33.86MHz Fig.1, Fig.2 External clock drive
fEX = 20.0MHz Fig.1, Fig.2 External clock drive
fEX = 40.0MHz Fig.1, Fig.2 External clock drive
fEX = 33.86MHz Fig.1, Fig.2 External clock drive
fEX = 20.0MHz Fig.1, Fig.2 External clock drive
Fig.1, Fig.2 1/2 VDD point
9.5
9.5
9.5
9.5
9.5
9.5
4.0
4.0
11
40
34.5
31.0
35.5
32.5
38.5
35.0
8.5
10.5
14
60
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
%
Symbol Pins Conditions Min. Max.
50
Typ. Unit
Note) tsys indicates the four values below according to the upper two bits (PCK1, PCK0) of the clock control
register (CLC: 0002FEh). tsys [ns] = 2/fEX (PCK1, PCK0 = 00), 4/fEX (PCK1, PCK0 = 01), 8/fEX (PCK1, PCK0 = 10, 16/fEX (PCK1, PCK0 = 11)
fEX
tXH tXL tXH tXL
t
XH
tXL tXR
tXF tXR
tXF tXR
tXF
duty
VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V
Fig.1, Fig.2
Fig.1, Fig.2 –30 to +75°C
Fig.1, Fig.2
30 to +50°C
Page 23
23
CXP974F096
EXTAL XTAL
1/fEX
tXH tXF tXL tXR
VDD – 0.4V
0.4V
XTAL
duty = tx/tEX; tEX = 1/fEX
tEX
tX
1/2VDD
Fig. 2. Oscillator connection and clock applied conditions
EXTAL XTAL
(iii)
Oscillator connection example of main oscillation circuit
Connection example (1) of external clock
Connection example (2) of external clock
EXTAL XTAL
(ii)(i)
EXTAL XTAL
Fig. 1. Clock timing
Page 24
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CXP974F096
Fig. 3. Event count input timing
EC0 EC2
tEH tEL
0.8VDD
0.2VDD
(2) Event count input (Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Event count input clock pulse width
tEH, tEL
EC0, EC2
Fig. 3
t
sys + 100
ns
Symbol Pins Conditions Min. Max. Unit
Fig. 4. Interruption input timing
0.2VDD
tIH
tIL
0.8VDD
NMI INT0 to INT7 KS0 to KS19
0.2VDD
RST
tRST
Fig. 5. Reset input timing
(3) Interruption and reset input (Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
External interruption high, low level width
t
IH,
t
IL
tRST
NMI, INT0 to INT7, KS0 to KS19
INT4 to INT7
RST
Main mode Sleep mode Fig. 4
Noise filter selected Fig. 4
Fig. 5
φ
PS4 PS6
ns
ns
tsys + 100
2tsys + 100 32/fEX + 100
128/fEX + 100
50/fEX
Reset input low level width
Symbol Pins Conditions Min. Max. Unit
Page 25
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CXP974F096
Conversion time
Sampling time
Reference input voltage Analog input voltage
AVREF current
tCONV
tSAMP
VREF
IREF
IREFS
AVREF
VDD = AVDD = AVREF = 3.0V
1
1
VDD = AVDD = AVREF
Linearity error Absolute error
Resolution
3.6
AVREF
2.1
1.7
12
34tsys 62tsys 10tsys 20tsys
2.7 0
Main mode
ADC off state
2
Stop mode
Item Symbol Pins Conditions Min. Typ. Max. Unit
Bits
(4) A/D converter characteristics
(Topr = –30 to +85°C, V
DD = AVDD = AVREF = 2.7 to 3.6V, Vss = AVss = 0V reference)
8
±1
LSB LSB
ns ns ns ns
V V
mA
mA
µA
±3
1.5
1.2
AVREF AN0 to AN11
Fig. 6. Definition of A/D converter terms
FFh
FEh
01h 00h
Analog input
Linearity error
Digital conversion value
FFh
(100h)
FEh
01h 00h
Analog input
Digital conversion value
Absolute error
AVREFVFT
2
VZT
1
1
VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa.
2
VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa.
Absolute error
1
When Bit 6 (ADCK) of A/D control status register (ADCS: 000132h) is specified to "1".
2
When Bit 5 (ADPC) of A/D control status register (ADCS: 000132h) is specified to "1".
Note) AV
DD and AVREF must be the same voltage with VDD.
VDD = 3.3 ± 0.3V fSRC = 40MHz
V
DD = 3.3 ± 0.3V
f
SRC = 20MHz
Page 26
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CXP974F096
SCK0, SCK1, SCK2
SCK0, SCK1, SCK2
SO0, SO1, SO2
SCS0, SCS1, SCS2
SCS0, SCS1, SCS2
SCK0, SCK1, SCK2
SCK0, SCK1, SCK2
SI0, SI1, SI2
SI0, SI1, SI2
SO0, SO1, SO2
SCK0, SCK1, SCK2
Note) The load condition for the SCK output mode and SO output delay time is 100pF.
(5) Serial transfer (CH0, CH1, CH2) (Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
CS ↓→SCK delay time
CS ↑→SCK float delay time
CS ↓→SO delay time
CS ↑→SO float delay time
CS high level width
SCK cycle time
SCK high, low pulse width
SI input data setup time (for SCK ↑)
SI input data hold time (for SCK ↑)
SCK ↓→SO delay time
Minimum interval time
tDCSK
tDSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH, tKL
tSIK
tKSI
tKSO
tINT
Symbol Pins Min.
2tsys + 150 2tsys + 160
100 110
2tsys + 200 2tsys + 210
16/fEX 16/fEX
tsys + 100 tsys + 110
8/fEX – 100 8/fEX – 110
100 110 200 210
2tsys + 100 2tsys + 110
100 110
3tsys + 100 3tsys + 110
8/fEX – 100 8/fEX – 110
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Max. UnitConditions
External start transfer mode (SCK = output
mode)
External start transfer mode
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V
V
DD = 3.3 ± 0.3V
V
DD = 3.0 ± 0.3V
VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V
V
DD = 3.3 ± 0.3V
V
DD = 3.0 ± 0.3V
VDD = 3.3 ± 0.3V VDD = 3.0 ± 0.3V VDD = 3.3 ± 0.3V V
DD = 3.0 ± 0.3V
tsys + 100 tsys + 110
1.5tsys + 200
1.5tsys + 210
1.5tsys + 200
1.5tsys + 210
1.5tsys + 200
1.5tsys + 210
1.5tsys + 200
1.5tsys + 210
ns ns ns ns ns ns ns ns ns ns
Page 27
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CXP974F096
SCK0 SCK1 SCK2
SI0 SI1 SI2
SO0 SO1 SO2
SCS0 SCS1 SCS2
SCK0 SCK1 SCK2
t
INT
0.8VDD
0.2VDD
0.8VDD
tDCSOF
0.2VDD
0.8VDD
tSIK tKSI
0.2VDD
0.8VDD
0.2VDD
0.8VDD
tKH
tDCSKF
tWHCS
tKL
tDCSK
tKCY
tKSO
Output data
Input data
tDCSO
Fig. 7. Serial transfer CH0, CH1, CH2 timing
Page 28
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CXP974F096
1
Due to the total capacitance of the bus.
(6) I2C bus (Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
SCK clock frequency Bus free time between stop
and start conditions Hold time under (resend)
start condition Hold time in SCL clock low
state Hold time in SCL clock high
state Setup time under (resend)
start condition Data hold time
Data setup time SCL, SDA signal output
rise time SCL, SDA signal output
fall time Setup time under stop
condition
SCL SDA SDA,
SCL SCL
SCL SDA,
SCL SDA,
SCL SDA,
SCL SDA,
SCL SDA,
SCL SDA,
SCL
tSCL tBUF
tHD;STA
tLow
tHigh
tSU;STA
tHD;DAT
tSU;DAT tRd,
tRc tFd,
tFc tSU;STO
400
0.9
300
300
1.3
0.6
1.3
0.6
0.6
0
100
20 + α
1
20 + α
1
0.6
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
100
1000
300
4.7
4.0
4.7
4.0
4.7
0
250
4.0
Item Symbol Pins
Min.
Standard mode High-speed mode
Max.Min. Max.
Unit
SDA
SCL
tBUF
tSU;DAT
tHD;STA
tSCL
tFd
tRd
tRc
tFc
tLow
tHD;STA
tHD;DAT tHigh
tSU;STA
tSU;STO
Fig. 8. I2C bus timing
Page 29
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CXP974F096
(7) Remote control reception (Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Remote control receive high, low level width
tRMC
RMC Main mode
PS5 selected PS7 selected PS9 selected
ns
128/fEX + 100 512/fEX + 100
2048/fEX + 100
Symbol Pins Conditions Typ. Max. Unit
0.8VDD
RMC
0.2VDD
tRMC tRMC
Fig. 9. Remote control signal input timing
Page 30
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CXP974F096
(8) External register interface (Vss = 0V reference)
Item
Symbol
Min. Max. Min. Max. Min. Max.
3.3 ± 0.3V
Topr = –20 to +75°C
3.3 ± 0.3V
Topr = –30 to +85°C
3.0 ± 0.3V
Topr = –30 to +85°C
Unit
Chip select pulse width 1
Chip select pulse width 2
Chip select pulse width 3
Chip select pulse width 4
Chip select pulse width 5
Chip select pulse width 6
Chip select pulse width 7
Read/write strobe pulse width 1
Read/write strobe pulse width 2
Read/write strobe pulse width 3
Address setting time 1
Address setting time 2
Address hold time Read data setting
request time Read data hold
request time Write data
setting time 1 Write data
setting time 2 Write data hold time
tCS1
tCS2
tCS3
tCS4
tCS5
tCS6
tCS7
tRW1
tRW2
tRW3
tAS1
tAS2
tAH
tDS1
tDH1
tDS2
tDS3
tDH2
1.5tsys
–20
2.5tsys
–20
2.5tsys
–20
3.5tsys
–20
2.5tsys
–20
3.5tsys
–20
4.5tsys
–20
tsys – 25
2tsys – 25
2tsys – 25
tsys/2
–25
1.5tsys
–25
tsys/2
–25
15
0
1.5tsys
–25
2.5tsys
–25
tsys/2
–25
1.5tsys
16.5tsys
32.5t
sys
33.5tsys
17.5
tsys
18.5tsys
34.5tsys
tsys
16
tsys
32tsys
t
sys/2
1.5tsys
1.5
tsys
16.5tsys
tsys/2
+30
1.5tsys
–20
2.5tsys
–20
2.5tsys
–20
3.5tsys
–20
2.5tsys
–20
3.5tsys
–20
4.5tsys
–20
tsys – 25
2tsys – 25
2tsys – 25
tsys/2
–25
1.5tsys
–25
tsys/2
–25
15
0
1.5tsys
–25
2.5tsys
–25
tsys/2
–25
1.5tsys
16.5tsys
32.5t
sys
33.5tsys
17.5
tsys
18.5tsys
34.5tsys
tsys
16
tsys
32tsys
t
sys/2
1.5tsys
1.5
tsys
16.5tsys
tsys/2
+30
1.5tsys
–30
2.5tsys
–30
2.5tsys
–30
3.5tsys
–30
2.5tsys
–30
3.5tsys
–30
4.5tsys
–30
tsys – 35
2tsys – 35
2tsys – 35
tsys/2
–35
1.5tsys
–35
tsys/2
–35
20
0
1.5tsys
–35
2.5tsys
–35
tsys/2
–35
1.5tsys
16.5tsys
32.5t
sys
33.5tsys
17.5
tsys
18.5tsys
34.5tsys
tsys
16
tsys
32tsys
t
sys/2
1.5tsys
1.5
tsys
16.5tsys
tsys/2
+30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 31
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CXP974F096
Read Timing
t1
t
CS1 tAH
tAS1 tRW1
t2
A15 to A0
XCS3 to XCS0
XRD
D7 to D0
tDS1 tDH1
Fig. 10. Byte read (without programmable wait)
tDS1 tDH1
tCS2 tAH
tAS1 tRW2
t1 t2 or tw t3 or tW + 1
A15 to A0
XCS3 to XCS0
XRD
D7 to D0
Fig. 11. Byte read (with programmable wait)
Page 32
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CXP974F096
tDS1 tDH1
tCS3
EVEN ADD. ODD ADD.
tAH
tAS1 tRW3
t1 t2 t3
A15 to A0
XCS3 to XCS0
XRD
D7 to D0
tDS1
Fig. 12. Word read (no strobe mode, without programmable wait)
tDS1 tDH1tDH1
tCS4
EVEN ADD. ODD ADD.
tAH
tAS1 tAH tAS1tRW1 tRW1
t1 t2 t3 t4
A15 to A0
XCS3 to XCS0
XRD
D7 to D0
tDS1
Fig. 13. Word read (strobe mode, without programmable wait)
Page 33
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CXP974F096
Write Timing
t1
t
CS5 tAH
tDS2
tAS2 tRW1
t2 t3
A15 to A0
XCS3 to XCS0
XWR
D7 to D0
tDH2
Fig. 14. Byte write (without programmable wait)
t1
t
CS6 tAH
tDS3
tAS2 tRW2
t2 t3 or tw t4 or tW + 1
A15 to A0
XCS3 to XCS0
XWR
D7 to D0
tDH2
Fig. 15. Byte write (with programmable wait)
Page 34
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CXP974F096
tDH2
tCS7
EVEN ADD. ODD ADD.
tAH
tAH tAS1tRW1 tRW1
t1 t2 t3 t4 t5
A15 to A0
XCS3 to XCS0
XWR
D7 to D0
tDS2 tDH2tDS2
Fig. 16. Word write (without programmable wait)
Page 35
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CXP974F096
EXTAL XTAL
C1 C2
Rd
EXTAL XTAL
C1 C2
Rd
EXTAL
(i) Main oscillation circuit (ii) Main oscillation circuit (iii) Main oscillation circuit
XTAL
C
1
C2
Rd
L
C3
Fig. 17. Recommended oscillation circuit
Appendix
SPC970 Series recommended oscillation circuit and oscillator
MURATA MFG CO., LTD.
RIVER ELETEC CO., LTD.
HC-49/U03
CSA6.00MG040 CSA8.00MTZ CSA10.0MTZ CSA12.0MTZ CSA16.00MXZ040 CSA20.00MXZ040 CSA24.00MXZ040 CST6.00MGW040
CST8.00MTW
CST10.0MTW
CST12.0MTW
CST16.00MXW0C3
6.0
8.0
10.0
12.0
16.0
20.0
24.0
6.0
8.0
10.0
12.0
16.0
6.0
8.0
10.0
12.0
100
30 30 30 15 10
7
100
30 30 30 15 18 15 10 10
100
30 30 30 15 10
7
100
30 30 30 15 18 15 10 10
0 0 0 0 0 0 0 0 0 0 0
0 560 330 330 220
(i)
(ii)
Indicates types with on-chip grounding capacitor (C
1, C2). CL: Load capacitor
(i)
CL = 13.5pF CL = 12pF CL = 9.5pF CL = 10pF
Manufacturer Model f
EX (MHz) C1 (pF) C2 (pF) Rd (Ω)
Circuit example
Remarks
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CXP974F096
Product List
Type Product name FLASH EEPROM capacitance RAM capacitance
Package
Main clock base oscillation frequency
Reset pin pull-up resistor
FLASH EEPROM incorporated version
CXP974F096Q-1, CXP974F096R-1
384K byte
23.5K byte
100-pin plastic QFP,
100-pin plastic LQFP
40MHz
Existent
6.0
8.0
10.0
12.0
16.0
20.0
24.0
28.0
32.0
36.0
40.0
6.0
12.0
16.0
28.0
40.0
15 15 10 12 12 12 12
1 3
3
1
36 (±20%) 20 (±20%) 10 (±20%) 10 (±20%)
5
15 15 10 12 12 12 12
1
0.01µF
0.01µF
0.01µF
36 (±20%) 20 (±20%) 10 (±20%) 10 (±20%)
5
5.6k
3.0k
1.8k
1.0k 470 390 200 100
0
0
0 0
0 0 0 0
CL = 16pF
CL = 12pF
(i)
(ii)
(iii)
Indicates types with on-chip grounding capacitor (C1, C2). CCR
∗∗∗
: Surface mounted type ceramic
oscillator
CL: Load capacitor
(i)
C3 = 10pF, L = 2.7µH
C3 = 5pF, L = 2.7µH
C3 = 3pF, L = 3.3µH
KINSEKI LTD.
HC-49/U-S
HC-49/U
TDK Corporation
CCR6.0MC5
CCR12.0MSC5
CCR16.0MSC6
CCR28.0MSC6
CCR40.0MS6
Manufacturer Model fEX (MHz) C1 (pF) C2 (pF) Rd (Ω)
Circuit example
Remarks
Page 37
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CXP974F096
Notes on PK6 Usage
FLASH EEPROM incorporated PK6 is also used as flash mode setting function. Note the followings:
1. "H" is output to PK6 during a reset. That is driven at comparatively high impedance (approximately 150kΩ), and take care that VOH should not fall under 0.7VDD by the partial pressure with external circuit load impedance.
2. When using software reset functions, PK6 may not rise enough during a reset. Switching PK6 to "H" output prior to software reset execution or connecting pull-up resistor is recommended.
Mask ROM and piggy/evaluation chip do not have flash mode setting function. Considering that FLASH EEPROM incorporated type is used, above countermeasure should be performed.
Keep PK6 above 0.7VDD during this period.
RST
PK6
Flash mode
Normal operation
Limits on Usage of FLASH EEPROM incorporated Type
The main clock doubler circuit is not guaranteed to operate.
Page 38
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CXP974F096
Characteristics Curve
60
66
72
54 48 42 36 30 24
18
6 0
2.1 2.4 2.7 3.33 3.6 3.9
12
60
66
72
54 48 42 36 30 24 18 12
6
2.1 2.4 2.7 3 3.3 3.6 3.9
0
60
66
72
54 48 42 36 30 24 18 12
6
010203040
0
60
66
72
54 48 42 36 30 24 18 12
6
10 20 30 40
0
0
IDD – Supply current [mA]
VDD – Supply voltage [V]
IDD vs. VDD
(fEX = 40MHz, Topr = 25°C, Typical)
IDD – Supply current [mA]
VDD – Supply voltage [V]
IDD vs. VDD
(fEX = 40MHz, Topr = 25°C, Typical)
IDD – Supply current [mA]
fEX – Main clock base oscillation frequency [MHz]
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
IDD – Supply current [mA]
fEX – Main clock base oscillation frequency [MHz]
IDD vs. fEX
(VDD = 3V, Topr = 25°C, Typical)
Sleep mode (1/2 frequency dividing mode)
Sleep mode (1/4 frequency dividing mode)
Sleep mode (1/8 frequency dividing mode)
Sleep mode (1/16 frequency dividing mode)
1/4 frequency dividing mode
1/2 frequency dividing mode
1/8 frequency dividing mode
1/16 frequency dividing mode
1/4 frequency dividing mode
1/2 frequency dividing mode
1/8 frequency dividing mode
1/16 frequency dividing mode
Sleep mode (1/2 frequency dividing mode)
Sleep mode (1/4 frequency dividing mode)
Sleep mode (1/8 frequency dividing mode)
Sleep mode (1/16 frequency dividing mode)
Page 39
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CXP974F096
Package Outline Unit: mm
SONY CODE EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREA TMENT
LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
23.9 ± 0.4
QFP-100P-L01
100PIN QFP (PLASTIC)
20.0 – 0.1
+ 0.4
0.15 – 0.05
+ 0.1
15.8
±
0.4
17.9
±
0.4
14.0
– 0.1
+ 0.4
2.75 – 0.15
+ 0.35
A
0.65 M
0.13
QFP100-P-1420
1.7g
1
100
81
80 51
50
31
30
0.3 – 0.1
+ 0.15
DETAIL A
0˚ to 10˚
0.8
±
0.2
(16.3)
0.15
0.1 – 0.05
+ 0.2
LEAD SPECIFICATIONS
ITEM LEAD MATERIAL ALLOY 42 LEAD TREATMENT Sn-Pb 10% LEAD TREATMENT THICKNESS 5-18µm
SPEC.
Page 40
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CXP974F096
Package Outline Unit: mm
100PIN LQFP (PLASTIC)
25
26
51
50
75
76
1
100
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREA TMENT LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42 / COPPER ALLOY
PACKAGE STRUCTURE
DETAIL A
LQFP-100P-L01
P-LQFP100-14x14-0.5
16.0 ± 0.2
14.0 ± 0.1
0.5 b
(0.22)
A
1.5 – 0.1
+ 0.2
0.5
±
0.2
(15.0)
0˚ to 10˚
0.1 ± 0.1
0.5
±
0.2
0.1
NOTE: Dimension "" does not include mold protrusion.
0.7g
0.13
M
b = 0.18 – 0.03
( 0.18 )
(0.127)
+ 0.08
0.127 – 0.02
+ 0.05
DETAIL B
B
Sony Corporation
LEAD SPECIFICATIONS
ITEM LEAD MATERIAL ALLOY 42 LEAD TREATMENT Sn-Pb 10% LEAD TREATMENT THICKNESS 5-18µm
SPEC.
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