Datasheet CXP811P24 Datasheet (Sony)

CXP811P24

CMOS 8-bit Single Chip Microcomputer

Description

The CXP811P24 is a CMOS 8-bit microcomputer
which consists of A/D converter, serial interface,
timer/counter, time base timer, PWM output, as well
as basic configurations like 8-bit CPU, PROM, RAM
and I/O port. They are integrated into a single chip.

Also the CXP811P24 provides power-on reset
function, sleep/stop function which enables to lower
power consumption .

The CXP811P24 is the PROM-incorporated version
of the CXP81120/81124 with built-in mask ROM.
This provides the additional feature of being able to
write directly into the program. Thus, it is most suitable
for evaluation use during system development and
for small-quantity production.

Features

• A wide instruction set (213 instructions) which covers various types of data

— 16-bit operation/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz (4.5 to 5.5V)

333ns at 12MHz (3.0 to 5.5V)

• Incorporated PROM capacity 24K bytes

• Incorporated RAM capacity 832 bytes

• Peripheral functions

— A/D converter 8-bit, 8-channel, successive approximation system

(Conversion time: 20µs at 16MHz)

— Serial interface Incorporated buffer RAM (1 to 32 bytes auto transfer), 1 channel

Incorporated 8-bit and 8-stage FIFO

(1 to 8 bytes auto transfer), 1 channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer
— PWM output 12 bits, 2 channels

• Interruption 10 factors, 10 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 64-pin plastic QFP/LQFP

64 pin LQFP (Plastic)64 pin QFP (Plastic)

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94X40A69-PS

CXP811P24

Vss
V

DD

MP

RST

XTAL

EXTAL

PA0 to PA7
8

PB0 to PB7
8

PORT A

CLOCK

GENERATOR/

SYSTEM CONTROL

SPC700

CPU CORE

PORT B

PC0 to PC7
8

PORT C

RAM

832 BYTES

PROM

24K BYTES

PD0 to PD7

PE0 to PE1
2

8

PORT D

PE2 to PE3

PF0 to PF3

4

2

PORT E

PF4 to PF7

PG3 to PG4

PG5 to PG7

2

4

PORT F

PRESCALER/

3

PORT G

TIME BASE TIMER

REF

DD

INT2
INT1

INT0

AVss

AV

AV

RAM

BUFFER

A/D CONVERTER

8

AN0 to AN7

(CH0)

SERIAL

INTERFACE UNIT

SI0

CS0

SO0

FIFO

SERIAL

INTERFACE UNIT

SI1

SO1

SCK0

INTERRUPT CONTROLLER

2

(CH1)

SCK1

8BIT TIMER 1

8BIT TIMER/COUNTER 0

EC

TO

12BIT PWM GENERATOR CH1

12BIT PWM GENERATOR CH0

PWM1

PWM0

Block Diagram

– 2 –

Pin Configuration (Top View) 64-pin QFP

PA0

PA1

PA2

PA3

SS

V

DD

V

Vpp

PA4

PA5

PA6

PA7

PG3/TO

PG4

CXP811P24

PB7
PB6
PB5
PB4
PB3
PB2

PB1
PB0
PC7
PC6
PC5

PC4
PC3
PC2
PC1

PC0
PD7
PD6
PD5

10
11
12
13
14
15
16
17

18

19

62

61

60

63

64

1

2
3
4

5
6
7
8
9

59

58

57

56

55

54

53

52

51

50
49
48
47
46
45
44
43

42
41

40

39

38

37

36
35
34
33

PG5/SCK1
PG6/SO1
PG7/SI1/INT1

PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PF0/AN0
PF1/AN1
PF2/AN2
PF3/AN3
PF4/AN4
PF5/AN5
PF6/AN6
PF7/AN7
AV

DD

AVREF
AV

SS

SCK0

20

PD4

21

PD3

22

PD2

23

24

PD1

PD0

25

MP

26

XTAL

27

EXTAL

28

SS

V

29

30

RST

CS0

SI0

SO0

32

31

Note) 1. Vpp (Pin 58) is always connected to VDD.

2. Vss (Pins 28 and 60) are both connected to GND.

3. MP (Pin 25) is always connected to GND.

– 3 –

Pin Configuration (Top View) 64-pin LQFP

PB7

PB6

PA0

PA1

PA2

PA3

SS

V

DD

V

Vpp

PA4

PA5

PA6

PA7

PG3/TO

PG4

CXP811P24

PG5/SCK1

PB5
PB4
PB3
PB2
PB1
PB0

PC7
PC6
PC5
PC4
PC3

PC2
PC1

PC0
PD7

PD6

10
11
12
13
14
15
16

62

19

61

20

PD3

60

21

PD2

PD1

63

64

1

2
3
4

5
6
7
8
9

18

17

PD4

PD5

59

22

PD0

58

23

MP

57

24

56

25

XTAL

EXTAL

55

26

SS

V

54

27

53

28

RST

52

29

CS0

SI0

51

30

50

31

SO0

49

32

SCK0

SS

AV

48
47
46
45

44
43
42
41

40
39
38

37
36
35
34
33

PG6/SO1
PG7/SI1/INT1
PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PF0/AN0

PF1/AN1
PF2/AN2

PF3/AN3
PF4/AN4
PF5/AN5

PF6/AN6
PF7/AN7
AV

DD

AVREF

Note) 1. Vpp (Pin 56) is always connected to VDD.

2. Vss (Pins 26 and 58) are both connected to GND.

3. MP (Pin 23) is always connected to GND.

– 4 –

Pin Description

CXP811P24

Symbol

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0/INT0

PE1/EC/
INT2

PE2/PWM0
PE3/PWM1

I/O Description

(Port A)

Output

8-bit output port.
(8 pins)

(Port B)

Output

8-bit output port.
(8 pins)

(Port C)

I/O

8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port D)

I/O

8-bit I/O port. I/O and function as standby release input can be set in a unit
of single bits.
(8 pins)

Input/Input

Input/Input/
Input

Output/Output

(Port E)
4-bit port.
Lower 2 bits are for input;
upper 2 bits are for
output.
(4 pins)

Input to request external interruption.
Active at the falling edge. (2 pins)

External event
input for
timer/counter.

12-bit PWM output. (2 pins)

Output/Output

PF0/AN0

to

PF3/AN3
PF4/AN4

to

PF7/AN7
SCK0
SO0
SI0
CS0
PG3/TO
PG4
PG5/SCK1
PG6/SO1

PG7/SI1/
INT1

EXTAL
XTAL

RST

Input/Input

Output/Input

I/O
Output
Input
Input
Output/Output
Output
I/O/I/O
I/O/Output

I/O/Input/
Input

Input
Output

I/O

(Port F)
8-bit port. Lower 4 bits are for input; upper
4 bits are for output.
Lower 4 bits also serve as standby release

Analog input to A/D

converter. (8 pins)
input.
(8 pins)

Serial clock (CH0) I/O.
Serial data (CH0) output.
Serial data (CH0) input.
Serial intreface (CH0) chip select input.

Timer/counter rectangular wave output.
(Port G)
5-bit port. Lower 2 bits
are for output; upper
3 bits are for I/O.
I/O port can be set in a
unit of single bits.
(5 pins)

Serial clock (CH1) I/O.

Serial data (CH1) output.

Serial data (CH1)
input.

Input to request external
interruption. Active at the
falling edge.

Connects a crystal oscillator for system clock. When supplying the
external clock, input the external clock to EXTAL pin and input opposite
phase clock to XTAL pin.

System reset; active at Low level. RST pin is I/O pin, which outputs Low level
by incorporated power-on reset function when power turns on.

– 5 –

CXP811P24

Symbol

Vpp

MP
AVDD

AVREF
AVSS
VDD
VSS

I/O Description

Power supply for built-in PROM writing.
Connect to VDD for normal operation.

Input

Test mode pin.
Always connect to GND.

Positive power supply of A/D converter.

Input

Reference voltage input of A/D converter.
GND of A/D converter.
Positive power supply.
GND. Connect both VSS pins to GND.

– 6 –

Input/Output Circuit Formats for Pins

CXP811P24

Pin

PA0 to PA7
PB0 to PB7

16 pins

PC0 to PC7

Port A
Port B

Data bus

Port C

Data bus

Ports A, B

RD (Ports A, B)

Port C data

Port C direction

“0” when reset

Circuit format When reset

Hi-Z

Output becomes active from high impedance
by data writing to port register.

Input protection
circuit

IP

Hi-Z

8 pins

PD0 to PD7

8 pins

PE0/INT0

1 pin

Port D

Port E

Port E

RD (Port C)

Port D data

Port D direction

“0” when reset

Data bus

RD (Port D)

Standby release

Edge detection

Schmitt input

IP

Schmitt input

IP

Hi-Z

INT0

Hi-Z

Data bus

RD (Port E)

PE1/EC/INT2

1 pin

IP

EC/INT2

Hi-Z

Data bus

RD (Port E)

– 7 –

CXP811P24

A

A

AAA

Pin

PE2/PWM0
PE3/PWM1

2 pins

PF0/AN0

to

PF3/AN3

4 pins

Port E

PWM

Hi-Z control

Port E data

Port E function selection

“0” when reset

Data bus

RD (Port E)

Port F

Circuit format When reset

MPX

A
A

Input multiplexer

IP

RD (Port F)

Edge detection

A/D converter

Data bus

Standby release

Hi-Z

Hi-Z

PF4/AN4

to

PF7/AN7

4 pins

PG3/TO

1 pin

Port F

Data bus

Port G

Port F data

RD (Port F)

Port G function
selection

“0” when reset

From timer counter

Port G data

“1” when reset

Port F function
selection

“0” when reset

MPX

IP

Input multiplexer

Hi-Z

A/D converter

High level

– 8 –

CXP811P24

A

Pin

PG4

1 pin

PG5/SCK1
PG6/SO1

2 pins

Port G

Port G

Data bus

Port G data

“1” when reset

Port G funciton
selection

“0” when reset

SCK1 out, SO1

Serial clock 1/data 1
output enable

Port G data

Port G direction

“0” when reset

RD (Port G)

Circuit format When reset

MPX

A

SCK1 in

MPX

∗

1

PG6 is not schmitt input

IP

∗

1

High level

Hi-Z

PG7/SI1/INT1

1 pin

CS0
SI0

2 pins

SO0

1 pin

Port G

Data bus

SO0

Serial data 0
output enable

Port G data

Port G direction

“0” when reset

RD (Port G)

INT1

SI1

Schmitt input

IP

Schmitt input

CS0
SI0

Hi-Z

IP

Hi-Z

Hi-Z

– 9 –

CXP811P24

Pin

SCK0

1 pin

EXTAL
XTAL

2 pins

RST

EXTAL

XTAL

SCK0 out

Serial clock 0
output enable

Circuit format When reset

IP

SCK0 in

Schmitt input

• Diagram shows the
circuit composition

IP

Pull-up resistor

Schmitt input

IP

From power-on reset circuit

during oscillation.

• Feedback resistor is
removed during stop.
XTAL becomes High
level.

Hi-Z

Oscillation

Low level

1 pin

MP

1 pin

IP

Test mode

Hi-Z

– 10 –

CXP811P24

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Rating Unit Remarks

VDD
Vpp

Supply voltage

AVDD
AVSS

AVREF
Input voltage
Output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature

Allowable power dissipation

∗1

VIN and VOUT should not exceed VDD + 0.3V. (CS0 and SI0 excluded.)

VIN

VOUT

IOH

∑IOH

IOL

∑IOL

Topr

Tstg

PD

–0.3 to +7.0

–0.3 to +13.0

AVSS to +7.0

–0.3 to +0.3

AVSS to +7.0

–0.3 to +7.0
–0.3 to +7.0

–5

–50

15

130

–10 to +75

–55 to +150

600
380

∗1
∗1

V
V
V
V
V

V

V
mA
mA
mA
mA

°C

°C
mW
mW

Incorporated PROM

Total of output pins

Total of output pins

QFP-64P-L01
LQFP-64P-L01

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding those conditions may adversely
affect the reliability of the LSI.

– 11 –

CXP811P24

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

VDD

3.0

2.7

5.5

5.5

Supply voltage

Analog voltage

High level
input voltage

Vpp
AVDD
VIH

VIHS

VIHEX

2.5
Vpp = VDD

3.0

0.7VDD

0.8VDD

VDD – 0.4

5.5

5.5
VDD
VDD

5.5

VDD + 0.3

0.3VDD

VIL
Low level
input voltage

VILS

VILEX
Operating temperature

∗1

AVDD should be the same voltage as VDD.

∗2

Normal input port (PC, PD, PF0 to PF3, and PG6 pins), MP pin.

∗3

SCK0, RST, INT0, EC/INT2, SCK1 and SI1/INT1 pins

∗4

CS0 and SI0 pins

∗5

Specified only when the external clock is input.

∗6

In case of 3.0 to 3.6V supply voltage (VDD).

∗7

In case of 4.5 to 5.5V supply voltage (VDD).

∗8

Vpp and VDD should be set to the same voltage.

Topr

0

0

–0.3

–10

0.2VDD

0.2VDD

0.4

+75

Guaranteed operation range for 1/2 and

V

1/4 frequency dividing mode
Guaranteed operation range for 1/16

V

frequency dividing mode
Guaranteed data hold range during stop

V

mode

∗8

V

∗1

V

∗2

V

CMOS Schmitt input

V

CMOS Schmitt input

V

EXTAL pin

V

∗2, ∗7

V

∗2, ∗6

V

CMOS Schmitt input

V

EXTAL pin

V

∗5

∗5

∗3
∗4

∗3, ∗4

°C

– 12 –

CXP811P24

DC Characteristics

Supply voltage (VDD = 4.5 to 5.5V) (Ta = –10 to +75°C, Vss = 0V reference)

Item Symbol Pin Condition Min.

High level
output voltage

Low level
output voltage

Input current

VOH

VOL

IIHE
IILE
IILR

PA to PE,
PF4 to PF7,
SO, SCK,
RST
(VOL only)
PG3 to PG7

EXTAL

RST

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 0.4V

PA to PG,
I/O leakage
current

IIZ

MP,

CS, SI, SO,

VDD = 5.5V,
VI = 0, 5.5V

SCK, RST

1/2 frequency dividing mode

IDD1

VDD = 5 ± 0.5V,
16MHz crystal oscillation
(C1 = C2 = 15pF)

Sleep mode

Supply
current

∗1

IDDS1

VDD

VDD = 5 ± 0.5V,
16MHz crystal oscillation
(C1 = C2 = 15pF)

4.0

3.5

0.5
–0.5
–1.5

Typ.

Max. Unit

0.4

0.6
40

–40

–400

±10

20 40

15

V
V
V

V
µA
µA
µA

µA

mA

mA

IDDS3

Input capacity

∗1

When all output pins are open.

CIN

PC, PD,
PE0, PE1,
PF,
PG5 to PG7,
RST, CS0,
SI0, SCK0,
EXTAL

Stop mode

VDD = 5.5V, termination of
16MHz oscillation

Clock 1MHz
0V other than the measured pins

30 µA

10 20 pF

– 13 –

DC Characteristics

CXP811P24

Supply voltage (VDD = 3.0 to 3.6V)

Item Symbol Pin Condition Min.

High level
output voltage

Low level
output voltage

Input current

VOH

VOL

IIHE
IILE
IILR

PA to PE,
PF4 to PF7,
SO, SCK,
RST
(VOL only)
PG3 to PG7

EXTAL

RST

VDD = 3.0V, IOH = –0.15mA
VDD = 3.0V, IOH = –0.5mA
VDD = 3.0V, IOL = 1.2mA
VDD = 3.0V, IOL = 1.6mA
VDD = 3.6V, VIH = 3.6V
VDD = 3.6V, VIL = 0.3V
VDD = 3.6V, VIL = 0.3V

PA to PG,
I/O leakage
current

IIZ

MP,

CS, SI, SO,

VDD = 3.6V,
VI = 0, 3.6V

SCK, RST

1/2 frequency dividing mode

IDD2

VDD = 3.3 ± 0.3V,
12MHz crystal oscillation
(C1 = C2 = 15pF)

Sleep mode

Supply
current

∗1

IDDS2

VDD

VDD = 3.3 ± 0.3V,
12MHz crystal oscillation
(C1 = C2 = 15pF)

(Ta = –10 to +75°C, Vss = 0V reference)

Typ.

2.7

2.3

0.3
–0.3
–0.9

10 20

0.5 2.5

Max. Unit

V
V

0.3

0.5
20

–20

–200

±10

V

V
µA
µA
µA

µA

mA

mA

IDDS3

Input capacity

∗1

When all output pins are open.

CIN

PC, PD,
PE0, PE1,
PF,
PG5 to PG7,
RST, CS0,
SI0, SCK0,
EXTAL

Stop mode

VDD = 5.5V, termination of
12MHz oscillation

Clock 1MHz
0V other than the measured pins

30 µA

10 20 pF

– 14 –

A

A

AC Characteristics

CXP811P24

(1) Clock timing

Item Symbol Pin Condition Unit

System clock frequency

System clock
input pulse width

System clock input
rise and fall times

Event count input clock
pulse width

Event count input clock
rise and fall times

∗

1

tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits

(CPU clock selection).

fC

tXL,
tXH

tCR,
tCF

tEL,
tEH

tER,
tEF

XTAL
EXTAL

XTAL
EXTAL

EXTAL

EC

EC

(Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)

Fig. 1,
Fig. 2

Fig. 1,
Fig. 2 (External clock drive)

Fig. 1, Fig. 2
(External clock drive)

Fig. 3

Fig. 3

VDD = 4.5 to 5.5V

VDD = 4.5 to 5.5V

Min.

1
1

28

37.5

4tsys

Max.

16
12

200

∗1

20

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Fig. 1. Clock timing

1/fc

MHz

ns

ns

ns

ms

EXTAL

Fig. 2. Clock applied condition

Crystal oscillation
Ceramic oscillation

EXTAL

C

1 C2

Fig. 3. Event count clock timing

EC

t

XH tXLtCF tCR

AA

XTAL

External clock

EXTAL

AA

74HC04

V

DD – 0.4V (VDD = 4.5 to 5.5V)

VDD – 0.3V

0.4V (VDD = 4.5 to 5.5V)

0.3V

XTAL

0.8VDD

0.2VDD

EH tELtEF tER

t

– 15 –

CXP811P24

(2) Serial transfer (CH0) (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

CS ↓→SCK
delay time

CS ↑→SCK
floating delay time

CS ↓→SO
delay time

CS ↓→SO
floating delay time

CS
high level width

SCK
cycle time

SCK
high and low level widths

SI input setup time
(for SCK ↑)

SI input hold time
(for SCK ↑)

SCK ↓→SO delay time

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0

SCK0

SO0

SO0

CS0

SCK0

SCK0

SI0

SI0

SO0

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode
Input mode

Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

tsys + 200

2tsys + 200

8000/fc

tsys + 100

8000/fc – 100

–tsys + 100

200

2tsys + 100

100

Max. UnitCondition

tsys + 200

tsys + 200

tsys + 200

tsys + 200

2tsys + 200

100

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns

Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper

2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0, and SO0, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

– 16 –

CXP811P24

Serial transfer (CH0) (Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)

Item

CS ↓→SCK
delay time

CS ↑→SCK
floating delay time

CS ↓→SO
delay time

CS ↓→SO
floating delay time

CS
high level width

SCK
cycle time

SCK
high and low level widths

SI input setup time
(for SCK ↑)

SI input hold time
(for SCK ↑)

SCK ↓→SO delay time

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0

SCK0

SO0

SO0

CS0

SCK0

SCK0

SI0

SI0

SO0

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode
Input mode

Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

tsys + 200

2tsys + 200

8000/fc

tsys + 100

8000/fc – 150

–tsys + 100

200

2tsys + 100

100

Max. UnitCondition

tsys + 250

tsys + 200

tsys + 250

tsys + 200

2tsys + 250

125

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns

Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper

2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0, and SO0, respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.

– 17 –

Fig. 4. Serial transfer timing (CH0)

CXP811P24

tWHCS

CSO

SCK0

DD

0.2V

tKCY

tDCSK tDCSKF

tKL tKH

0.8VDD

0.2VDD

tSIK

tKSI

0.8VDD

0.8VDD

SI0

SO0

t

DCSO tKSO

Input data

Output data

0.8VDD

0.2VDD

tDCSOF

0.8V

DD

0.2VDD

– 18 –

CXP811P24

Serial transfer (CH1) (SIO mode) (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Min. Max. UnitCondition

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(for SCK1 ↑)

SI1 input hold time
(for SCK1 ↑)

SCK1 ↓→SO1 delay time

Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper

2 bits (CPU clock selection).

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK1

SCK1

SI1

SI1

SO1

Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode

2tsys + 200

16000/fc

tsys + 100

8000/fc – 50

100
200

tsys + 200

100

tsys + 200

100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Serial transfer (CH1) (SIO mode) (Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)

Item Symbol Pin Min. Max. UnitCondition

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(for SCK1 ↑)

SI1 input hold time
(for SCK1 ↑)

SCK1 ↓→SO1 delay time

Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper

2 bits (CPU clock selection).

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK1

SCK1

SI1

SI1

SO1

Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode

2tsys + 200

16000/fc

tsys + 100

8000/fc – 150

100
200

tsys + 200

100

tsys + 250

125

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.

– 19 –

Fig. 5. Serial transfer CH1 timing (SIO mode)

tKL tKH

KCY

t

CXP811P24

SCK1

SI1

SO1

tKSO

tSIK tKSI

Input data

0.8VDD

0.2VDD

Output data

0.8VDD

DD

0.2V

0.8VDD

0.2VDD

– 20 –

Serial transfer (CH1) (Special mode) (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit

CXP811P24

SO1 cycle time
SI1 data setup time

SI1 data hold time

∗1

tLCY is specified only when serial mode register (CH1) (SIOM1: 01FAH) lower 2 bits (SO1 clock selection) is

tLCY
tLSU

tLHD

SO1
SI1

SI1
SI1

∗1

104 µs

2
2

µs
µs

set at 104µs according to the system clock frequency.

Note) The load of SO1 pin is 50pF + 1TTL.

Serial transfer (CH1) (Special mode) (Ta = –10 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit
SO1 cycle time
SI1 data setup time

SI1 data hold time

∗1

tLCY is specified only when serial mode register (CH1) (SIOM1: 01FAH) lower 2 bits (SO1 clock selection) is

tLCY
tLSU

tLHD

SO1
SI1

SI1
SI1

∗1

104 µs

2
2

µs
µs

set at 104µs according to the system clock frequency.

Note) The load of SO1 pin is 50pF.

Fig. 6. Serial transfer CH1 timing (Special mode)

tLCY

SO1

SI1

Start bit

tLCY

Output data bit

tLCY/2

tLSU tLHD

Input

data bit

0.5VDD

0.8VDD

0.2VDD

– 21 –

CXP811P24

(3) A/D converter characteristics

Item Symbol Pin Condition Min. Typ. Max.

Resolution
Linearity error

Absolute error
Conversion time

Sampling time
Reference input voltage
Analog input voltage

AVREF current

A/D converter characteristics

tCONV
tSAMP

VREF
VIAN

IREF

(Ta = –10 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference)

Item Symbol Pin Condition Min. Typ. Max.

(Ta = –10 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)

Unit

Only for A/D converter
operation

8

±1

Bits

LSB

Ta = 25°C

AVREF
AN0 to AN7

VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V

VDD = AVDD = 4.5 to 5.5V

Operating mode
AVREF = 4.0 to 5.5V

160/fADC

12/fADC

∗1

∗1

AVDD – 0.5

0

0.6

±2

AVDD

AVREF

1.0

LSB

µs
µs

V
V

mA

AVREF

Sleep mode
Stop mode

10

µA

Unit

Resolution
Linearity error

Absolute error
Conversion time

Sampling time
Reference input voltage
Analog input voltage

AVREF current

tCONV
tSAMP

VREF
VIAN

IREF

AVREF
AN0 to AN7

AVREF

Fig. 7. Definitions of A/D converter terms

FFH
FEH

Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF = 3.3V
VSS = AVSS = 0V

VDD = AVDD = 3.0 to 3.6V

Operating mode
AVREF = 2.7 to 3.6V

Sleep mode
Stop mode

160/fADC

12/fADC

∗1

∗1

AVDD – 0.3

0

0.4

8

±1

±2

AVDD

AVREF

0.7

10

Bits

LSB

LSB

µs
µs

V
V

mA

µA

Digital conversion value

01H
00H

Analog input

Linearity error

∗

1

The value of fADC is as follows by interruption selection/
ADC operation clock selection register (MSC: 01FFH)
bit 0 (ADCCK).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc

V

FTVZT

– 22 –

(4) Interruption, reset input (Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Max. Unit

INT0
External interruption
high and low level widths

tIH
tIL

INT1

INT2

1

µs

PJ0 to PJ7

CXP811P24

Reset input low level width

Fig. 8. Interruption input timing

INT0
INT1
INT2
PD0 to PD7
(During standby release input)
(Falling edge)

Fig. 9. Reset input timing

RST

tRSL

RST

tIH tIL

0.8VDD

tRSL

0.2VDD

32/fc

µs

0.2VDD

(5) Power-on reset

Item Symbol Pin Condition Min. Max. Unit
Power supply rising time
Power supply cut-off time

Fig. 10. Power-on reset

DD

V

The power supply should be turned on smoothly.

(Ta = –10 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)

tR

Power-on reset

VDD

tOFF

3.0V

0.2V

tR tOFF

Repetitive power-on reset

0.05
1

30 ms

ms

0.2V

– 23 –

Appendix

A

Fig. 11. SPC700 Series recommended oscillation circuit

Main clock

CXP811P24

EXTAL

AA

C

1 C2

Manufacturer Model fc (MHz) C1 (pF) C2 (pF) Rd(Ω)

RIVER ELETEC
CO., LTD.

KINSEKI LTD.

Mask Option Table

XTAL

Rd

HC-49/U03

HC-49/U (-S)

8.00

10.00

12.00

16.00

8.00

10.00

12.00

16.00

10

5

22 (15)

15
12

10

5

22 (15)

15
12

0

0

Circuit

example

(i)

(i)

Item Content CXP811P24R-1- CXP811P24Q-1­Reset pin pull-up resistor
Power-on reset circuit

Writing to EPROM

See the “How to write the program into OTP, FLASH, EPROM” for reference.

Non-existent/existent
Non-existent/existent

Existent
Existent

Existent
Existent

– 24 –

Characteristics Curve

CXP811P24

(fc = 16MHz, Ta = 25°C, Typical)

10

1.0

– Supply current [mA]

DD

I

0.1

234567

IDD vs. VDD

VDD – Supply voltage [V]

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

Sleep mode

(VDD = 5.0V, Ta = 25°C, Typical)

20

15

10

– Supply current [mA]

DD

I

5

1 5 10 15

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

Sleep mode

fc – System clock [MHz]

(fc = 12MHz, Ta = 25°C, Typical)

10

1.0

– Supply current [mA]

DD

I

0.1

234567

IDD vs. VDD

VDD – Supply voltage [V]

1/2 dividing mode
1/4 dividing mode

1/16 dividing mode

Sleep mode

(VDD = 3.3V, Ta = 25°C, Typical)

20

15

10

– Supply current [mA]

DD

I

5

1 5 10 15

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode
Sleep mode

fc – System clock [MHz]

– 25 –

Package Outline Unit: mm

CXP811P24

64PIN QFP(PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

51

52

64

1

1.0

0.4 – 0.1

+ 0.15

33

32

+ 0.4

14.0 – 0.1

17.9 ± 0.4

20

19

± 0.12

+ 0.35

2.75 – 0.15

M

+ 0.1

0.15 – 0.05

+ 0.2

0.1 – 0.05

0.15

16.3

0.8 ± 0.2

SONY CODE
EIAJ CODE
JEDEC CODE

QFP–64P–L01

QFP064–P–1420

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS

EPOXY RESIN
SOLDER/PALLADIUM

42/COPPER ALLOY

1.5g

PLATING

– 26 –

12.0 ± 0.2

∗ 10.0 ± 0.1

CXP811P24

64PIN LQFP (PLASTIC)

49

64

0.5 ± 0.08

SONY CODE
EIAJ CODE
JEDEC CODE

48

1

0° to 10°

0.18 – 0.03

0.1 ± 0.1

DETAIL A

LQFP-64P-L01
LQFP064-P-1010

+ 0.08

33

0.5 ± 0.2

32

(11.0)

A

17

(0.22)

16

+ 0.2

1.5 – 0.1

0.127 – 0.02

0.5 ± 0.2

+ 0.05

0.1

NOTE: Dimension “∗” does not include mold protrusion.

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS

EPOXY RESIN
SOLDER/PALLADIUM

42/COPPER ALLOY

0.3g

PLATING

– 27 –