Page 1
CMOS 4-bit Single Chip Microcomputer
Description
CXP5076/5078 is a CMOS 4-bit microcomputer
which consists of 4-bit CPU, ROM, RAM, I/O port,
8-bit timer, 8-bit timer/counter, 18-bit time base
timer, 8-bit serial I/O, vector interruption, power on
reset function, liquid crystal displayer (LCD)
controller/driver, D/A conversion 14-bit PWM output
port, a remote control reception circuit with noise
eliminating circuit, 3-bit A/D converters, a 32kHz
timer/event counter and a power supply voltage
detection reset function. They are integrated into a
single chip with the standby function, etc. which are
to be operated at a low power consumption.
Features
• Instruction cycle 1.9µs/4.19MHz
122 µs/32kHz
(Possible to select with the program)
• ROM capacity 8192 × 8 bits (CXP5078)
6144 × 8 bits (CXP5076)
• RAM capacity 448 × 4 bits (Including stack, display area)
• 43 general purpose I/O ports
• 8 high current output ports
• LCD controller/driver (Possible to direct drive)
— Possible to select with the program the segment output of 16 to 32
— Possible to select with the program the duty of static, 1/2, 1/3 and 1/4
— Possible to select with the program the bias of 1/2, 1/3
• 14-bit PWM output for D/A conversion
• Remote control reception circuit
• 3-bit A/D converter (8 channels per circuit)
• 32kHz timer/event counter
• Power supply voltage detection reset function
• Low voltage operation (2.5V) ..... when operating in 122µs/32kHz
• Rich wake-up function
• 8-bit/4-bit variable serial I/O
• Arithmetic and logical operations possible between the entire ROM area, I/O area and the accumulator by
means of the memory mapped I/O
• 8-bit timer, 8-bit timer/event counter and 18-bit time base timer, independently controlled
• 2 kinds of power down modes of sleep and stop
• Power on reset circuit (mask option)
• Provided with 80 pin plastic QFP
• Provided with 80 pin piggyback QFP (CXP5070)
Structure
Silicon gate CMOS IC
– 1 –
E88037A78-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP5076/5078
80 pin QFP (Plastic)
For the availability of this product, please contact the sales office.
Page 2
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CXP5076/5078
Block Diagram
PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I
44 44
(Common with A/D
converter analog input)
(Input and output is
possible by bit unit)
(Common with segment
output S27 to S24)
(Common with segment
output S31 to S28)
(Common with segment
output S19 to S16)
(Common with segment
output S23 to S20)
(Common with A/D
converter analog input)
(Input and output is
possible by port unit)
44 4
(Input and output is
possible by port unit)
448 × 4
bits
Resister
Data memory
Stack
Data memory
ALU
Accumulator
Flag
Timer (8)
Sub time (8)
Timer/Counter (8)
Serial I/O (8)
Interrupt control
Program
counter (13)
Program
memory
8192 × 8 bits
(CXP5078)
8144 × 8 bits
(CXP5076)
PWM (14)
A/D Converter
Remote control
receiving
Instruction control
Time base timer (18)
Clock control
32kHz timer/
event counter
Port X Port Y
LCD controller/
driver
16 16 4
VL
VLC1
VLC2
VLC3
EXTAL
XTAL
TEX
TX
(Common with serial I/O)
(Common with
port C, port D,
port G, port H)
SEG16 to SEG31
SEG0 to SEG15
COM0 to COM3
PX2/SI
PX1/SO
PX0/SC
PY3/EC
PY2/WP
PY1/PWM
PY0
INT
V
DD
V
SS
RST
V
REF
RMC
Page 3
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CXP5076/5078
Pin Configuration (Top View)
PG1/SEG18
PG2/SEG17
PG3/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
COM0
V
LC1
PD1/SEG30
PD0/SEG31
PY3/EC
PY2/WP
PE2
PE1
PE0
PF3
PF2
PF1
PF0
PA3
PA1
PA0
PX2/SI
PX1/SO
PX0/SC
NC
PB3/AD7
PB2/AD6
V
LC2
V
LC3
V
L
RMC
INT
XTAL
EXTAL
RST
NC
V
DD
AD0/PI0
AD1/PI1
AD2/PI2
AD3/PI3
AD4/PB0
AD5/PB1
NC
PG0/SEG19
PH3/SEG20
PH1/SEG22
PH0/SEG23
V
REF
TEX
TX
V
SS
PC3/SEG24
PC2/SEG25
PC1/SEG26
PC0/SEG27
PD3/SEG28
PD2/SEG29
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
PA2
PY0
PE3
PY1/PWM
PH2/SEG21
Note) Do not make any connections to NC pins.
Page 4
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CXP5076/5078
Pin Description
Symbol Name I/O Equivalent Circuit Description
Supply voltage
Grounding
voltage
Clock input
Clock output
Reset
External
interrupt
Remote control
input
Port X2
Serial input
Port X1
Serial output
—
—
I
O
I/O
I
I
I
I/O
Positive voltage supply pin
GND pin
Clock oscillation circuit input pin.
Connect the crystal oscillator or
ceramic resonator between the EXTAL
and XTAL. When using as the
external clock input, connect the clock
oscillation source to the EXTAL pin
and open the XTAL pin.
Clock oscillation circuit output pin
Serves as the incorporated power-on
reset circuit output pin.
When inputting a reset signal from the
outside, provide 2 instruction cycles or
longer of an "L" level (0V).
Serves the interrupt input pin.
Permits the selection with a program
of the edge and the level modes.
Remote control receiver input pin
Doubles as a serial interface (8 bits)
input pin and as bit "2" (input) of port X.
Doubles as a serial interface (8 bits)
output pin and as bit "1" (input) of
port X. (SO output possible to inhibit
with the program.)
EXTAL
XTAL
P
N
PN
P
N
E
Mask option
(Note 2)
Data
Output Select
Disable
Standby
P
N
(Only during
tri-state output)
VDD
VSS
EXTAL
XTAL
RST
INT
RMC
PX2/SI
PX1/SO
Output pull-up resistor (P-ch Tr)
N-ch Tr output
Schmitt inverter input
See Note 2) for the output
circuit format.
Inverter input
Schmitt inverter input
Page 5
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CXP5076/5078
Symbol Name I/O Equivalent Circuit Description
Port X0
Serial clock
Port Y3
Event count
input
Port Y2
Wake-up
input
Port Y1
PWM
generator
output
Port Y0
Port A
Port B
Analog voltage
input
Port E
Port F
Port I
Analog voltage
input
I/O
I
I
O
O
I/O
I/O
I/O
I/O
I/O
(Note 2)
Data
Output Select
Disable
Standby
(Only during
tri-state output)
PX0/SC
PY3/EC
PY2/WP
PY1/PWM
PY0
PA0
to
PA3
PB0/AD4
to
PB3/AD7
PE0
to
PE3
PF0
to
PF3
PI0/AD0
to
PI3/AD3
See Note 2) for the output
circuit format.
Schmitt inverter input
(Note 2)
Data
Output Select
Disable
Standby
P
N
(Only during
tri-state output)
See Note 2) for the output
circuit format.
Inverter input
See Note 1) for the output
circuit format.
Schmitt inverter input
Doubles as shift clock input/output pin
for the serial interface and as bit "0"
(input) of port X.
Doubles as event counter (8 bits) input
pin and as bit "3" (input) of port Y.
Doubles as wake-up input pin to
release the standby state and as bit
"2" (input) of port Y.
Doubles as PWM generator (14 bits)
output pin and as bit "1" (output) of
port Y.
Output pin for bit "0" of port Y.
This 4-bit input/output port permits its
each individual bit to be programmed
to serve either as input or output. For
the output format, a tri-state and pullup resistor possible to be programmed,
and it is also used as the standby
resetting pin.
This 4-bit input/output port has the
functions that are equivalent to those
of port A. It is also used for A/D
converter input.
This 4-bit input/output port permits its
each individual port to be programmed
to serve either as input or output. For
the output format, a tri-state and pullup resistor possible to be programmed.
This 4-bit input/output port has the
functions that are equivalent to those
of port E.
This 4-bit input/output port has the
functions that are equivalent to those
of port E.
It is also used for A/D converter input.
(Note 1)
Data
Output Select
Disable
Page 6
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CXP5076/5078
Symbol Name I/O Equivalent Circuit Description
Port D
Segment
output
Port C
Segment
output
Port H
Segment
output
Port G
Segment
output
Segment
output
Common
output
Power supply
for LCD
Cut-off
output
O
O
O
O
O
O
—
O
Doubles as a 4-bit output port (For the
output format, the inverter and pull-up
resistor possible to be programmed.)
and as the segment signal output pin
for LCD.
Doubles as a 4-bit output port (The
output format is equivalent to port D.)
and as the segment signal output pin
for LCD.
Doubles as a 4-bit output port (The
output format is equivalent to port D.)
and as the segment signal output pin
for LCD. (Possible to designate in bit
units.)
Doubles as a 4-bit output port (The
output format is equivalent to port D.)
and as the segment signal output pin
for LCD.
Segment signal output pin for LCD
Common signal output pin for LCD
Bias power supply pin for LCD
Control pin which cuts off the current
input to the bias resistor for the
external LCD during standby.
P
N
Segment
(Note 3)
Data
Output Select
Standby
Port C, D, G, H
LCD/PORT
select
P
N
P
N
PD3/
SEG31
to
PD0/
SEG28
PC3/
SEG27
to
PC0/
SEG24
PH3/
SEG23
to
PH0/
SEG20
PG3/
SEG19
to
PG0/
SEG16
SEG0
to
SEG15
COM0
to
COM3
VLC1
to
VLC3
VL
The transfer gate input signal
is controlled based on 1/2, 1/3
bias method in advance.
See Note 3) for the output
circuit format.
Transfer gate output
The transfer gate input signal
is controlled based on 1/2, 1/3
bias methods in advance.
N
Page 7
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CXP5076/5078
Symbol Name I/O Equivalent Circuit Description
Wake-up
input
32kHz T/C
clock input
32kHz T/C
clock output
Reference
voltage input
I
I
O
I
It is the input pin to release the
standby mode, and release by "1".
Input pin for 32kHz timer clock
generation circuit. Connect the
32.768kHz crystal oscillator between
TEX and TX. When using as the
event clock input, connect the clock
oscillation source to the TEX pin,
open the TX pin.
Output of clock generation circuit
Reference voltage input for power
supply voltage resetting circuit.
Connect the zener diode normally.
WP
TEX
TX
VREF
TEX
TX
P
N
PN
Mask option
Schmitt inverter input
For all output ports, the output states of ports during standby possible to be programmed to the state holding
before standby or the change to the high impedance.
When the pull-up resistor output is selected, it becomes a pulled-up state even it is input port.
During standby, it is impossible to change to the high impedance of PY0 and PY1 in the inverter output state. To
change to the high impedance, select the pull-up resistor output, and then set to the high level output ("1" state).
Page 8
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CXP5076/5078
Note 1) Possible to select out of the following two ways for the output circuit format.
(port units: programmable)
(a) Inverter output
(b) Pull-up resistor output
Note 2) Possible to select out of the following two ways for the output circuit format.
(port units: programmable)
(a) Tri-state output
(b) Pull-up resistor output
Note 3) Possible to select out of the following two ways for the output circuit format.
(port units: programmable)
(a) Inverter output
(b) Pull-up resistor output
∗
As the output pull-up resistor is CMOS pull-up output of about 10kΩ, the pull-up resistor becomes OFF state
during "L" output.
Standby
Output Select
Data
P
P
∗
P
N
Standby
Output Select
Data
P
P
∗
P
N
Disable
Standby
Output Select
Data
P
P
∗
P
N
LCD/PORT
Select
Page 9
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CXP5076/5078
Absolute Maximum Ratings (Ta = –20 to +75°C, VSS = 0V)
Item
Power supply voltage
LCD bias voltage
Input voltage
Output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage tamperature
Allowable power dissipation
Symbol
VDD
VCL1,
VCL2,
VCL3
VIN
VOUT
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
Rating
–0.3 to +7.0
–0.3 to +7.0
∗1
–0.3 to +7.0
∗1
–0.3 to +7.0
∗1
–5
–50
15
20
100
–20 to +75
–55 to +150
600
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
Remarks
General purpose port∗2: per pin
Entire pins total
General purpose port∗2: per pin
High current port∗3: per pin
Entire pins total
∗1
VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V.
∗2
Specifies the output current of the general purpose I/O port PA to PI, SO, SC, PY0 and PY1.
∗3
The high current operation transistors are the N-ch transistors of the PC and PD ports.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operation conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Recommended Operating Condition (Vss = 0V)
Item
Power supply voltage
LCD bias voltage
High level input voltage
Low level input voltage
Operating temperature
Symbol Min.
Max.
4.5
2.5
VSS
0.7VDD
0.8VDD
VDD – 0.4
0
0
–0.3
–20
5.5
5.5
VDD
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.4
+75
Unit
V
V
V
V
V
V
V
V
V
°C
Remarks
Guaranteed range of operation by
EXTAL clock
Guaranteed range of operation by
TEX clock, guaranteed range of
data hold during STOP.
Liquid crystal power supply range
∗1
Hysteresis input
∗2
EXTAL pin
∗3
Hysteresis input
∗2
EXTAL pin
∗3
∗1
The optimum value is determined by the characteristics of the liquid crystal display element used.
∗2
The TEX pin when the counter mode is selected by each of INT, RMC, PX0, PX2, PY2, PY3, RST pins and
mask option.
∗3
Specified only during external clock input.
VDD
VCL1,VCL2,
VCL3
VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr
Page 10
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CXP5076/5078
Electrical Characteristics
DC characteristics (Ta = –20 to +75°C, Vss = 0V)
Item
High level
output voltage
Low level
output voltage
Input current
High impedance
I/O leakage
current
Common output
impedance
Segment output
impedance
Supply current
Input capacity
Symbol Pin
PA to PI
∗1
PX0, PX1
PY0, PY1
VL (VOL only)
RST (VOL only)
PC∗1, PD
∗1
EXTAL
TEX
∗4
RST
∗5
PA∗6, PB∗6, PE∗6,
PF∗6, PI∗6, PX0∗6,
PX1∗6, PX2∗8, PY0∗7,
PY1∗7, PY2∗8, PY3∗8,
INT∗8, RMC∗8,
RST∗5, TEX
∗4
COM0 to COM3
SEG0 to SEG15
SEG16 to SEG31
∗1
VDD
Other than VLC1 to
VLC3, COM0 to COM3,
SEG0 to SEG15,
SEG16 to SEG31∗1,
VSS, VDD pins
Unit
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
kΩ
kΩ
mA
µA
mA
µA
µA
µA
pF
Condition
VDD = 4.5V, IOH = –0.5mA
∗2
VDD = 4.5V, IOH = –1.0mA
∗2
VDD = 4.5V, IOH = –10µA
∗3
VDD = 4.5V, IOH = –200µA
∗3
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VI = 0, 5.5V
VDD = 5V
VLC1 = 3.75V
VLC2 = 2.5V
VLC3 = 1.25V
Entire output pins open
Crystal oscillation
(C1 = C2 = 22pF)
of VDD = 5.5V, 4.19MHz
Crystal oscillation
(C1 = C2 = 47pF)
of VDD = 3V, 32kHz
Sleep mode
VDD = 5.5V,
4.19MHz oscillation
VDD = 3V, 32kHz oscillation
Stop mode
VDD = 3V, 32kHz with T/C
VDD = 5.5V, 32kHz without T/C
(For mask option select
counter, Pin is fixed.)
Clock 1MHz
0V other than the measured pins
Max.
0.4
0.6
1.5
40
–40
10
–10
–400
±10
±10
5
15
20
250
12
200
40
10
20
Typ.
3
5
7
50
5
40
7
10
Min.
4.0
3.5
4.0
2.4
0.5
–0.5
0.1
–0.1
–1.5
VOH
VOL
IIHE
IILE
IIHT
IILT
IILR
IIL
IIZ
RCOM
RSEG
IDD1
IDD2
IDDSP1
IDDSP2
IDDS1
IDDS2
CIN
Page 11
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CXP5076/5078
AC characteristics
(1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
System clock frequency
System clock input pulse
width
System clock input rising
and falling times
System clock frequency
Event count clock input
pulse width
Event count clock input
rising and falling times
Event count input clock
input pulse width
Event count input clock
rising and falling times
Symbol Pin
XTAL
EXTAL
EXTAL
TEX
∗2
TX
EC
EC
TEX
∗3
TEX
∗3
Unit
MHz
ns
ns
kHz
µs
ms
µs
ms
Condition
Fig. 1, Fig. 2
Fig. 1, Fig. 2
(External clock drive)
VDD = 2.5 to 5.5V
Fig. 3
Fig. 4
Fig. 4
Fig. 4
Fig. 4
Max.
5
200
20
20
Typ.
32.768
Min.
1
90
tsys
∗1
+ 0.05
10
fc
tXL
tXH
tCR
tCF
fCS
tEL
tEH
tER
tEF
tTL
tTH
tTR
tTF
∗1
The PC, PD, PG and PH show when the combined pins are selected as the port, and SEG16 to SEG31
show when the combined pins are selected as the segment output.
∗2
It is when the respective pins of PA to PI, PX0 and PX1 select the tri-state output circuit, and PY0 and PY1
are when the inverter output circuit is selected.
∗3
It is when the respective pins of PA to PI, PX0, PX1, PY0 and PY1 select the pull-up resistor.
∗4
The TEX pin specifies the input current when the crystal oscillation is selected by the mask option, and
specifies the leakage current when the schmitt input is selected.
∗5
The RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗6
The respective pins of PA, PB, PE, PF, PI, PX0 and PX1 specify the input current when the pull-up resistor
is selected, and specify the leakage current when the port state during using the tri-state output circuit or
standby is selected at high impedance.
∗7
The respective pins of PY0 and PY1 specify the input current when the pull-up resistor is selected, and
specify the leakage current when the port state during standby is selected at high impedance.
∗8
The respective pins of PX2, PY2, PY3, INT and RMC only specify the leakage current.
∗1
tsys in the EXTAL input clock is 8/fc.
tsys in the TEX input clock is 4/fcs.
∗2
Specified when the crystal oscillation mode is selected by the mask option.
∗3
Specified when the counter mode is selected by the mask option.
Note) When adjusting the frequency accurately, there may be cases in which they may differ from Fig. 2.
Page 12
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CXP5076/5078
EXTAL
t
XH tXLtCF tCR
0.4V
V
DD – 0.4V
1/fc
Fig. 1. Clock timing
A
External clock
EXTAL
XTAL
OPEN
A
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
C
1 C2
Fig. 2. Clock applying condition
C1
A
Crystal oscillation
TEX
TX
C
2
Fig. 3. 32kHz clock applying condition
EC
TEX
t
EH
tTH
tEL
tTL
tEF
tTF
tER
tTR
0.2VDD
0.8VDD
Fig. 4. Event count clock timing
AAA
AA
AA
Page 13
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CXP5076/5078
(2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Serial transfer clock (SC)
cycle time
Serial transfer clock (SC)
high and low level widths
Serial data input setup
time (against SC ↑)
Serial data input hold
time (against SC ↑)
High data output delay
time from SC falling
∗3
High data output delay
time from SC falling
∗4
Low data output delay
time from SC falling
Symbol Pin
SC
SC
SI
SI
SO
SO
SO
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Condition
Input mode
Output mode
Input mode
Output mode
∗1
Output mode
∗2
SC input mode
SC output mode
SC input mode
SC output mode
Max.
tsys/8 + 0.5
tsys/8 + 1.6
tsys/8 + 0.5
Min.
tsys/4 + 1.42
2tsys
tsys/8 + 0.7
tsys – 0.1
tsys – 1.6
0.1
0.2
tsys/8 + 0.5
0.1
tKCY
tKH
tKL
tSIK
tKSI
tKSO
tKSO
tKSO
Notes) 1. tsys in the EXTAL input clock is 8/fc. (It is impossible to use in TEX input clock.)
2. The load of data output delay is 50pF + 1TTL.
∗1
It is specified when PX0/SC pin is selected to the tri-state output by the program.
∗2
It is specified when PX0/SC pin is selected to the pull-up resistance by the program.
As the tsys receives restriction by this item, take notice that it limits the upper limit of the system clock
frequency fc.
∗3
This item is specified when PX1/SO pin is selected to the tri-state output by the program.
∗4
This item is specified when PX1/SO pin is selected to the pull-up resistance by the program.
0.2VDD
0.8VDD
tKL tKH
SO
tKCY
tSIK
tKSI
0.2VDD
0.8VDD
tKSO
0.2VDD
0.8VDD
Output data
Input data
SI
SC
Fig. 5. Serial transfer timing
Page 14
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CXP5076/5078
(3) A/D converter (Ta = –20 to +75°C, Vss = 0V)
Analog input voltage
0.0 to 0.33V
0.82 to 1.29V
1.78 to 2.21V
2.69 to 3.06V
3.56 to 4.06V
4.62 to 5.0V
Pin
AD0
to
AD7
Condition
VDD = 5V
Digital conversion value
000
001
010
011
100
101
Note) The digital conversion value are the values when ABH address of the RAM file 1 in the program are read.
(4) Power Supply Voltage Detection Reset Function (Ta = –20 to + 75°C, Vss = 0V)
Item
Power supply voltage
detection reset function of
operation voltage range
Power supply voltage drop
detection function
Symbol Pin
VDD
VDD
Unit
V
V
Condition
Voltage range allowing system
operation (32kHz system
operation below VDD = 4.5V)
When VREF pin voltage is 3.3V
Flag set when voltage drops
System reset when voltage rises
Max.
5.5
4.2
Typ.
4.0
Min.
2.5
3.8
VLPOP
VPOP
The graph in Fig. 6 shows the relationship between the power supply voltage VDD and reference voltage VREF
of the power supply voltage detection reset function.
Note) The graph in Fig. 6 serves as guide to the function operation area obtained using average devices.
Individual adjustment is needed when Zener diodes, etc., are connected to the VREF pin.
5.5
2.5
0 1.6 5.0
VREF [V]
V
DD [V]
Fig. 6. Power supply voltage detection reset function chart
Page 15
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CXP5076/5078
Fig. 7. Interruption input timing
(5) Others (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
External interruption high and
low level widths
Reset input low level width
Wake-up input high level width
Wake-up input low level width
Symbol Pin
INT
RST
WP
PA0 to
PA3
Unit
µs
µs
ns
µs
ns
µs
Condition
During edge
detection mode
Stop mode
Sleep mode
Stop mode
Sleep mode
Max.Min.
tsys + 0.05
2tsys
∗1
500
tsys + 0.05
500
tsys + 0.05
tI1H, tI1L
tRSL
tWPH
tWPL
Note) tsys in the EXTAL input clock is 8/fc.
tsys in the TEX input clock is 4/fcs.
∗1
For resetting when operating in TEX input clock, hold the low level more than the oscillation stabilizing time
of EXTAL input clock.
tI1L tI1H
0.2VDD
0.8VDD
INT
(Rising edge)
tI1H tI1L
0.2VDD
0.8VDD
INT
(Falling edge)
Fig. 8. Reset input timing
tRSL
0.2VDD
RST
Fig. 9. Wake-up input timing
WP
tWPH
0.8VDD
Fig. 10. Wake-up input timing
tWPL
0.2VDD
PA0 to PA3
Page 16
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CXP5076/5078
Power on reset
∗
(Ta = –20 to +75°C, Vss = 0V)
Item
Power supply rising time
Power supply cut-off time
Symbol Pin
VDD
Unit
ms
ms
Condition
Power on reset
Repetitive power on reset
Max.
50
Min.
0.05
1
tR
tOFF
∗
Specifies only when power on reset function is selected.
VDD
tR
0.2V
4.5V
0.2V
tOFF
The power supply should rise smoothly.
Fig. 11. Power on reset
Page 17
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CXP5076/5078
Notes on Application
See Fig. 11, Additive capacity calculation chart, when using the crystal oscillator and select the appropriate
capacity.
Fig. 12. Crystal oscillation circuit additive capacity calculation chart
Note) The above chart shows a range in which the average quartz resonator has a relatively fast oscillation
rising edge and stable characteristics. The capacity should be selected to correspond to the
appropriate constant for each quartz resonator, should the frequency of the quartz resonator be
accurately adjusted.
Fig. 13 shows an example of a circuit which can accurately adjust the frequency. Used here a trimmer
capacitor.
Fig. 13. Frequency adjustment circuit
When using the A/D converter as the key input, it is recommended that the circuit structure shown in Fig. 14
be used.
VDD
AD
V
SS
8.2k
SW5SW4
3.3k
SW3
1.8k
SW2
1.2k
SW1
4.7k
(Resistance is all E12 series)
EXTAL XTAL
C1
C2
VDD
Rd
A
A
A
0.1 1 10 100
f – Crystal oscillation frequency [MHz]
50
100
150
200
C – Additive capacity [pF]
Ta = –20 to +75°C, VDD = 4.5 to 5.5V
EXTAL XTAL
C1 C2
C1 = C2 = C
5
Fig. 14. Recommended example of key circuit by A/D converter
A
A
A
Page 18
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CXP5076/5078
Package Outline Unit: mm
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-80P-L01
QFP080-P-1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
1.6g
23.9 ± 0.4
20.0 – 0.1
+ 0.4
1
80
65
64
41
40
25
24
0.8
0.35 – 0.1
+ 0.15
14.0 – 0.1
+ 0.4
17.9 ± 0.4
16.3
0.1 – 0.05
+ 0.2
2.75 – 0.15
+ 0.35
0.8 ± 0.2
0.15 – 0.05
+ 0.1
80PIN QFP (PLASTIC)
M
0.12
0.15
0° to 10°
DETAIL A
A
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