Datasheet CX28332-3x, CX28332-1x, CX28331-3x, CX28331-1x, CX28333-3x Datasheet (CONEX)

Advance Information

This document contains information on a product under development. The parametric information
contains target para me te rs that are subject to change.

CX28331/CX28332/CX28333

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

The CX28333 is a three-channel, E3/DS3/STS-1 fully-integrated Line Interface Unit
(LIU). It is configured via external pins and does not need a microprocessor interface.
Each channel has an independent equalizer on the receive side requiring no user
configuration. Also, each channel has a programmable transmit pulse shaper that can
be set to ensure that the cross-connect pulse mask requirement is met for transmit
cable length up to 450 feet. The CX28332 is a dual-channel, and the CX28331 is a
single-channel LIU with performance identical to the CX28333.

The CX28333 gives the user new economies of scale in concentrator applications
where three DS3 or STS-1 channels are concentrated into a single STS-3 channel. By
including three independent transceivers on a chip, significant external compo nents are
eliminated, with the exception of 1:1 coupling transformers, termination resistors, and
supply bypass capacitors.

NOTE: In this document, "i" is used to represent the number of channels:

i = 1 (CX28331), i = 2 (CX28332), and i = 3 (CX28333).

Functional Block Diagram

XOE
LBO

E3MODE

PDB

TPOS
TNEG

TCLK

TAIS

RLOOP

LLOOP

RPOS
RNEG

RCLK

RLOS

NOTE(S):

PDATA/

NDATA

ENCODER

TCLK

DATA

MUX

ENDECDIS

PDATA
NDATA

DECODER

The TX Monitor is only used with the 100-pin CX2833i-3X.

DATCLK

Pulse

Shaper

Clock/

Data

Recovery

DRIVER

P
N

ALOS

LINE

TX

Monitor

Receiver

TLINEP
TLINEM/N

TMONP
TMONM

TXMON
TMONTST

REFCLK

RLINEP
RLINEM/N

REQH

LIU #1

LIU #2

LIU #3

Distinguishing Features

• Can be used as a data transceiver
over a maximum of 900 feet of Type
734/728 coaxial cab le or equivalent
in an on-premise environment

• Programmable pulse filtering to meet
cross-connect pulse masks (ANSI
T1.102-1993)

• Meets jitter specifications of Bellcore
GR499, GR253, and TBR24 (with
external JAT).

• Large input dynamic range

• Alarms for coding violation and loss
of signal

• Full diagnostic loop back capability

• Uses a minimum of external
components

• Compatible with ITU-T G.703, G.823

• Independent power down mode per
channel

• Easily interfaced to the DS3/ E3
Framer IC (CX28342/3/4/6/8 and
CN8330)

• Selectable B3ZS/HDB3
encoding/decoding

• Superior inpu t rec ei v er sensitivity
(< 25 mV)

• Transmit monitor inputs (CX2833i-3x
series only)

Physical Characteristics

• 80- and 100-pin ETQFP package

• Single 3.3 V power supply

• 1 W maximum power dissipation
(CX28333)

• –40 °C to +85 °C temperature range

• 5 V-tolerant pi ns

• TTL digital pins

Applications

• Digital Cross-Connect Syst ems

•Routers

• ATM Switches

• Channelized Line Aggregation Units

• Test Equi pm e nt

• Channel Service Units

• Multiplexers

Data Sheet 100985A

June 2, 2000

CX28333EVM

NRZTX DATA and CLK in

CH1

NRZRX DATA and CLK out

F
R

NRZTX DATA and CLK in

A

CH2

M
E

NRZRX DATA and CLK out

R
S

NRZTX DATA and CLK in

I

CH3

D
E

NRZRX DATA and CLK out

Loss of Signal
Code Violation

CX28333

TX B3ZS/HDB3 analog out

CH1

RX B3ZS/HDB3 analog in
TX B3ZS/HDB3 analog out

CH2

RX B3ZS/HDB3 analog in
TX B3ZS/HDB3 analog out

CH3

RX B3ZS/HDB3 analog in

Clock Input
Control

L

I
N
E

S

I
D
E

100985_002

© 2000, Conexant Systems, Inc.

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100985A Conexant

Ordering Information

Model Number Package Description

CX28331-1x 80-Pin ETQFP Single-channel LIU

CX28332-1x 80-Pin ETQFP Dual-channel LIU
CX28333-1x 80-Pin ETQFP Triple-channel LIU
CX28331-3x 100-Pin ETQFP Single channel with Transmit Monitoring
CX28332-3x 100 -Pin ETQFP Dual channel with Transmit Monitoring
CX28333-3x 100-Pin ETQFP Triple channel with Transmit Monitoring

Revision History

Revision Level Date Description

A — May 5, 2000 Initial Release

Operating

Temperature

–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C

100985A Conexant

100985A Conexant

Table of Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

1.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

1.1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

2.0 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.1 AMI B3ZS/HDB 3 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.2 Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.3 Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.3.1 Transmit Pulse Mask Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.2.4 Alarm Indication Signal (AIS) Ge nerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.5 Transmit Monitor Block (CX2833i-3x Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.6 Jitter Generation (Intrinsic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.3.1 Receive Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.3.2 AGC/VGA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.3.3 Receive Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.3.4 The PLL Clock Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.3.5 Loss Of Signal (LOS) Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.3.6 B3ZS/HDB3 Decoder With Bipolar Violation Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.3.7 Data Squelching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.4 Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.4.1 Jitter Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.5 Additional CX28331/CX28332/CX28333 Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.5.1 Bias Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.5.2 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.5.3 Loopback Multiplexers (MUXes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.6 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

100985A Conexant v

Table of Contents CX28331/CX28332/CX28333

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.7.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.7.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.8 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.9 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

3.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 PCB Design Considerations for CX28331/CX28332/CX28333 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Power Sup ply and Grou nd Plane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.2 Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.3 Other Passive Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.4 IBIS Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.5 Recommended Vendors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.1 Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

B.1 Evaluation Module Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

vi Conexant 100985A

CX28331/CX28332/CX28333 List of Figures

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

List of Figures

Figure 1-1. CX28331-1x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Figure 1-2. CX28332-1x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-3. CX28333-1x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Figure 1-4. CX28331-3x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Figure 1-5. CX28332-3x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Figure 1-6. CX28333-3x Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Figure 2-1. Typical Application Of Single CX2833i Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2. Pulse Shaper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 2-3. Pulse Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-4. Transmit Pulse Mask for DS3 Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

Figure 2-5. Transmit Pulse Mask for STS-1 Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 2-6. Transmit Pulse Mask for E3 Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -7

Figure 2-7. AIS Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Figure 2-8. Minimum Jitter Tolerance Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

Figure 2-9. Maximum Jitter Transfer Curve Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Figure 2-10. CX2833i-1x Mechanical Drawing (80-Pin)—Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

Figure 2-11. CX2833i-3x Mechanical Drawing (100-Pin)—Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Figure 2-12. Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

Figure 3-1. Typical CX28333 Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Figure B-1. Recommended Schematic for the CX2833i-1x Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2

Figure B-2. Recommended Schematic for the CX2833i-3x Device (1 of 2) . . . . . . . . . . . . . . . . . . . . . . B-3

Figure B-3. Recommended Schematic for the CX2833i-3x Device (2 of 2) . . . . . . . . . . . . . . . . . . . . . . B-4

100985A Conexant vii

List of Figu res CX28331/CX28332/CX28333

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

viii Conexant 100985A

CX28331/CX28332/CX28333 List of Tables

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

List of Tables

Table 1-1. CX28331/CX28332/CX28333 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Table 1-2. CX2833i-3x Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

Table 2-1. DS3 Transmit Template Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

Table 2-2. STS-1 Transmit Template Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

Table 2-4. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Table 2-5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

Table 2-6. AC Characteristics (Logic Timing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

100985A Conexant ix

List of Tables CX28331/CX28332/CX28333

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

x Conexant 100985A

1

1.0 Pin Description

1.1 Pin Assignments

Figures 1-1 (CX28331-1x), 1-2 (CX28332-1x), and 1-3 (CX28333-1x) illustrate

pin assignments for the 80-pin Exposed Thin Quad Flat Package (ETQFP). See

Table 1-1 for the CX2833i-1x pin descriptions.

Figures 1-4 (CX28331-3x), 1-5 (CX28332-3x), and 1-6 (CX28333-3x)

illustrate pin assignments for the 100-pin ETQFP. The 100-pin package adds
more functionality, supporting new features such as Tr ansmit Monitoring and
Transmit Monitoring Status testing. See Table 1-2 for the CX2833i-3x pin
descriptions.

The input/output (I/O) column is coded as follows:

I = Input

O = Output

I/O = Bidirectional

P = Power

NOTE: All digital inputs and outputs contain 75 kΩ pull-down resistors.

When a channel is disabled (i.e., the PDx
receive and transmit analog circuitry powers down. Analog inputs (RLINE) are
ignored and analog outputs (TLINE) are high impedance. Digital inputs of a
powered-down channel are still active, but ignored. Overall noise on the device
can be lowered by not driving the digital inputs of a powered-down channel.

NOTE: When power is disconnected from the device, TLINE pins are low

impedance to ground if driven by more than one forward-bias diode
voltage (0.7 V) below ground. Additionally, driving TLINE, a
forward-bias diode voltage above the VGG pin, creates a low impedance
path from the TLINE pin to the VGG pin. Otherwise, the TLINE pins are
high impedance.

pin is tied low or not connected), a ll

100985A Conexant 1-1

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 1-1. CX28331-1x Pin Diagram

NC

GPD

RESET

VGG

VSS

NC

NC
VDD
VDD

NC

NC

VSS

TVSS

TLINEP

TLINEN

TVDD

RVDD
RLINEP
RLINEN

RVSS

VSS

NC
NC

VDD

RBIAS

77

78

79

80
1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

24

23

22

21

NC

NC

76

74

75

25

27

26

NC

NC

DVDDIO

73

CX28331-1x

28

NC

71

72

70

30

29

31

NC

69

32

NC

68

33

NC

NC

66

67

35

34

NC

65

36

NC

64

37

NC

63

38

NC

NC

61

62

40

39

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

DVDDC
ENDECDIS
PD
RLOOP
LLOOP
RNEG/RLCV
RPOS/RNRZ
RCLK
RLOS
TAIS
TCLK
TPOS/TNRZ
TNEG/NC
REFCLK
REQH
XOE
LBO
E3MODE
NC
DVSSC

NC

VDD

NC

NC

VSS

NC

NC

NC

NC

DVSSIO

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

100985_003

1-2 Conexant 100985A

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 1-2. CX28332-1x Pin Diagram

PD1

GPD

RESET

VGG

TVSS1
TLINE1P
TLINE1N

TVDD1

RVDD1
RLINE1P
RLINE1N

RVSS1

VSS

NC

NC
VDD
VDD

NC

NC
VSS

TVSS2
TLINE2P
TLINE2N

TVDD2

RBIAS

76

77

78

79

80
1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

25

24

23

22

21

LLOOP1

RLOOP1

74

75

27

26

DVDDIO

73

CX28332-1x

28

LBO1

72

29

XOE1

71

30

REQH1

70

31

RLOS1

RCLK1

RPOS1/RNRZ1

RNEG1/RLCV1

66

67

68

69

35

34

33

32

TNEG1/NC1

REFCLK1

64

65

37

36

TAIS1

TCLK1

TPOS1/TNRZ1

61

62

63

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

40

39

38

DVDDC
ENDECDIS
NC

NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
E3MODE

NC
DVSSC

1.1 Pin Assignments

RVDD2

RLINE2P

RVSS2

RLINE2N

PD2

LLOOP2

RLOOP2

LBO2

DVSSIO

XOE2

REQH2

RCLK2

RLOS2

RNEG2/RLCV2

RPOS2/RNRZ2

REFCLK2

TNEG2/NC2

TAIS2

TCLK2

TPOS2/TNRZ2

100985_004

100985A Conexant 1-3

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 1-3. CX28333-1x Pin Diagram

PD1

GPD

RESET

VGG

TVSS1

TLINE1P

TLINE1N

TVDD1

RVDD1
RLINE1P
RLINE1N

RVSS1

TVSS2

TLINE2P

TLINE2N

TVDD2

RVDD2
RLINE2P
RLINE2N

RVSS2

TVSS3

TLINE3P

TLINE3N

TVDD3

RBIAS

77

78

79

80
1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20

24

23

22

21

76

25

LLOOP1

RLOOP1

74

75

27

26

XOE1

LBO1

DVDDIO

73

28

REQH1

71

72

70

CX28333-1x

30

29

31

RLOS1

RCLK1

RPOS1/RNRZ1

RNEG1/RLCV1

66

67

68

69

35

34

33

32

TNEG1/NC1

REFCLK1

64

65

37

36

TAIS1

TCLK1

TPOS1/TNRZ1

61

62

63

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

40

39

38

DVDDC
ENDECDIS
PD2
RLOOP2
LLOOP2
RNEG2/RLCV2
RPOS2/RNRZ2
RCLK2
RLOS2
TAIS2
TCLK2
TPOS2/TNRZ2
TNEG2/NC2
REFCLK2
REQH2
XOE2
LBO2
E3MODE
NC
DVSSC

RVDD3

RLINE3P

RVSS3

RLINE3N

PD3

LLOOP3

RLOOP3

LBO3

DVSSIO

XOE3

REQH3

RCLK3

RLOS3

RNEG3/RLCV3

RPOS3/RNRZ3

REFCLK3

TNEG3/NC3

TAIS3

TCLK3

TPOS3/TNRZ3

100985_005

1-4 Conexant 100985A

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-1. CX2833i-1x Pin Definitions (1 of 6)

Pin #

Signal Name Description I/O/P Notes

CX28331-1x CX28332-1x CX28333-1x

Coaxial Line Pins

14 ——RLINEP Ch1 positive receive
— 66RLINE1P
15 ——RLINEN Ch1 negative receive
— 77RLINE1N
— 22 14 RLINE2P Ch2 positive receive

— 23 15 RLINE2N Ch2 negative receive

——22 RLINE3P Ch3 positive receive

——23 RLINE3N Ch3 negative receive

10 ——TLINEP Ch1 positive transmit
— 2 2 TLINE1P
11 ——TLINEN Ch1 negative transmit
— 33TLINE1N
— 18 10 TLINE2P Ch2 positive transmit

— 19 11 TLINE2N Ch2 negative transmit

data

data

data

data

data

data

data

data

data

data

1.1 Pin Assignments

I Differential inputs for each channel

from its respective receive coax
line. The RX expec ts balanced
differential inputs, usually achieved

I

using a 1:1 transfor mer.
The inputs are inte rnally DC biased
to 1.9 V.

I

I

I

I

O Differential, coax-driver balanced

outputs for pulse-shaped AMI
B3ZS/HDB3 enco ded waveforms
for each channel.

O

These pins should be connected to
the primary side of the 1:1

O

transformer through two
backmatch resistors (see Appendix

O

B).

——18 TLINE3P Ch3 positive transmit

data

——19 TLINE3N Ch3 negative transmit

data

O

O

100985A Conexant 1-5

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-1. CX2833i-1x Pin Definitions (2 of 6)

Pin #

Signal Name Description I/O/P Notes

CX28331-1x CX28332-1x CX28333-1x

Digital Data Pins

54 ——RPOS/

RNRZ

— 68 68 RPOS1/

RNRZ1

55 ——RNEG/

RLCV

— 69 69 RNEG1/

RLCV1

— 33 54 RPOS2/

RNRZ2

— 32 55 RNEG2/

RLCV2

——33 RPOS3/

RNRZ3

——32 RNEG3/

RLCV3

53 ——RCLK Receive clock Ch1 O Recov e red clock for each channel

— 67 67 RCLK1
— 34 53 RCLK2 Receive clock Ch2 O
——34 RCLK3 Receive clock Ch3 O

Ch1 receive Positive rail
or NRZ data

Ch1 receive Negative rail
or line code violation

Ch2 receive Positive rail
or NRZ data

Ch2 receive Negative rail
or line code violation

Ch3 receive Positive rail
or NRZ data

Ch3 receive Negative rail
or line code violation

O Resynchronized receive data

intended to be strobed out by the
corresponding RCLK.

When ENDECDIS = 1, these outputs
are positive and negative AMI data

O

(RPOS and RNEG).
When ENDECDIS = 0, these outputs

are decoded NRZ data (RNRZ) and
line code violation (RLCV). A l ine

O

code violation is in dicated when
RLCV = 1.

O

See notes on the ENDECDIS pin in

O

the Control Signals sect ion.

O

receiver, intended for strobing the
corresponding RDAT into the
following framer or logic.

49 ——TPOS/

TNRZ

— 63 63 TPOS1/

TNRZ1

48 ——TNEG/NCCh1 transmit Negative

— 64 64 TNEG1/

NC1

— 38 49 TPOS2/

TNRZ2

— 37 48 TNEG2/

NC2

——38 TPOS3/

TNRZ3

——37 TNEG3/

NC3

Ch1 transmit Positive
rail or NRZ data

rail or no connect data

Ch2 transmit Positive or
NRZ data

Ch2 transmit Negative
rail or no connect data

Ch3 transmit Positive or
NRZ data

Ch3 transmit Negative
rail or no connect data

I Synchronized transmit data

intended to be strobed in by the
corresponding TCLK.

When ENDECDIS = 1, these inputs

I

are expected to be positive and
negative AMI data (TPOS and
TNEG).

When ENDECDIS = 0, these inputs

I

are expected to be uncoded NRZ
data (TNRZ) and no connects (NC).

I

See notes on the ENDECDIS pin in
the Control Signals sect ion.

I

I

1-6 Conexant 100985A

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-1. CX2833i-1x Pin Definitions (3 of 6)

Pin #

Signal Name Description I/O/P Notes

CX28331-1x CX28332-1x CX28333-1x

50 ——TCLK Transmit clock Ch1 I Transmit bit clock input for strobing
— 62 62 TCLK1
— 39 50 TCLK2 T ra ns mit clock Ch2 I
——39 TCLK3 Transm it cl oc k Ch3 I
52 ——RLOS Loss of signal Ch1 O Loss Of Signal (LOS) indication for
— 66 66 RLOS1
— 35 52 RLOS2 Loss of signal Ch2 O
——35 RLOS3 Loss of signal Ch3 O

Control Signals

59 59 59 ENDECDIS Encoder/decoder

disable (for all channels)

51 ——TAIS Transmit Ch1 AIS mode

— 61 61 TAIS1
— 40 51 TAIS2 Transmit Ch2 AIS mode

——40 TAIS3 Transmit Ch3 AIS mode

enable

enable

enable

with transmit data into the CX2833i.

each channel, as determi ned by
insufficient pulse density. Signal
loss detected when RLOS = 1. An
LOS will be asse rte d w h en 175 ±75
0s occur in a row and deasserted
when the pulse density is between
28% and 33% (DS3/STS-1) (i.e., a
1s density).

I 1 = Dual rail pulse coded data

format. Input transmit data pins
TPOS, TNRZ, TNEG and NC are
interpreted as TPOS and TNEG
(encoded positive and negative rail
data). Output receive data pins
RPOS and RNRZ, and RNEG and
RLCV are interpreted as RPOS and
RNEG, with RPO S h a vi ng a positive
pulse in place of every positive AMI
pulse and RNEG havin g a negative
pulse in place of every negative AMI
pulse.
0 = NRZ format. Transmit data pins
TPOS and TNEG are interpreted as
TNRZ and NC (not connected).
Receive data pins RPOS and RNEG
are interpreted as RNRZ and RLCV.
In this mode, all lin e cod e viol ations
are reported as active high on
RLCV.

I Transmission of Alarm Indication

Signal (AIS) for a given chann el.
Replace transmit data with AIS
signal. The AMI form of AIS

I

supported is alternating 1s.

I

(+1, -1, +1, -1, +1, ...)
Looping takes precedence over AIS.
1 = AIS mode enabled
0 = AIS mode disabled

1.1 Pin Assignments

100985A Conexant 1-7

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-1. CX2833i-1x Pin Definitions (4 of 6)

Pin #

Signal Name Description I/O/P Notes

CX28331-1x CX28332-1x CX28333-1x

43 43 43 E3MODE E3MODE I When the pin is set to high, it

enables the E3 mode on al l
channels, in stea d of t he DS 3/S TS-1
mode. This also changes the pulse
shaper to E3 mode and overrides all
LBO pins. It also changes the
encoder/decoder from B3ZS mode
to HDB3 mode.
1 = E3 mode
0 = DS3/STS-1 mode

44 ——LBO Transm it lin e Ch1

— 72 72 LBO1
— 29 44 LBO2 Transmit line Ch2

——29 LBO3 Transmit line Ch3

build-out mode

build-out mode

build-out mode

56 ——LLOOP Local loopback enable

— 74 74 LLOOP1
— 27 56 LLOOP2 Local loopback enable

——27 LLOOP3 Local loopback enable

57 ——RLOOP Remote loopback enable
— 75 75 RLOOP1
— 26 57 RLOOP2 Remote loopback enable

——26 RLOOP3 Remote loopback enable

45 ——XOE Trans m it ou tpu t en able
— 71 71 XOE1
— 30 45 XOE2 Transmit output enable

Ch1

Ch2

Ch3

Ch1

Ch2

Ch3

Ch1

Ch2

I Line build-out mode per ch an ne l,

based on the length of cable on the
transmit side of the cross-connect
block. This bit is overridden and the

I

pulse shaper is disabled (no pulse
shaping) if E3MODE = 1.

I

1 = Inserts line build-out into the
transmit channel. U sually used
when the transmit cable is less than
350 feet in length.
0 = Line build-out bypassed (not
inserted). Usually used when the
transmit cable is grea ter than 350
feet in length.

I Local loopback enable per channel.

The transmit data is l ooped back
immediately from the encoder to
the decoder in place of the received

I

data.
1 = local loopback enabled

I

0 = local loopback disabled

I Remote loopback enable per

channel. The receive data, retimed
after clock recovery, is looped back
into the AMI generator in place of

I

the transmit data.
1 = remote loopback enabled

I

0 = remote loopback disabled

I Transmit output enable per channel.

1 = transmit line output driver
enabled
0 = transmit output driver set to

I

high impedance state

——30 XOE3 Transmit output enable

Ch3

1-8 Conexant 100985A

I

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-1. CX2833i-1x Pin Definitions (5 of 6)

Pin #

Signal Name Description I/O/P Notes

CX28331-1x CX28332-1x CX28333-1x

46 ——REQH Ch1 Receive High EQ
— 70 70 REQH1
— 31 46 REQH2 Ch2 Receive High EQ

——31 REQH3 Ch3 Receive High EQ

Gain Enable

Gain Enable

Gain Enable

Power/Ground

1.1 Pin Assignments

I The equalizer in the CX2833i has

two gain settings. The higher gain
setting is designed to optimally
equalize a nominally-shaped (meets
the pulse template), pulse-driven
DS3 or STS-1 wavefor m that is

I

driven through 0–900 feet of cable.
Square-shaped pulses such as E3
or DS3-HIGH require less
high-frequency gain and should use
the low EQ gain setting.

REQH = 1 high EQ gain
(DS3/STS-1 modes)

REQH = 0 low EQ gain (E3/DS3
Square Modes)

(1)

per channel (3.3 V).

per channel.

channel (3.3 V).

Connect to 3.3 V power.

per channel.

Connect to groun d.

(3.3 V).

P 5 V supply for 5 V-tolerant, digital

pad ESD diodes. No static power is
drawn from pin.

12 ——TVDD TX power Ch1 P Power pins for transmit circuitry

— 4 4 TVDD1
— 20 12 TVDD2 TX power Ch2 P
——20 TVDD3 TX power Ch3 P

9 ——TVSS TX ground Ch1 P Ground pins for transmit circuitry
— 1 1 TVSS1
— 17 9 TVSS2 TX ground Ch2 P
——17 TVSS3 TX ground Ch3 P
13 ——RVDD RX power Ch1 P Power pins for receive circuitry per
— 5 5 RVDD1
— 21 13 RVDD2 RX power Ch2 P
——21 RVDD3 RX power Ch3 P
16 ——RVSS RX ground Ch1 P Ground pins for receive circuitry
— 8 8 RVSS1
— 24 16 RVSS2 RX ground Ch2 P
——24 RVSS3 RX ground Ch3 P

60 60 60 DVDDC Digital core power P Dig it a l core power for all ch annels

41 41 41 D VSSC Digi tal core ground P Digital core gr ound for all channels.
79 79 79 VGG

5 V/3.3 V ESD pin

73 73 73 DVDDIO Digital I/O power P Connect to 3.3 V digital power.
28 28 28 DVSSIO Digi tal ground P Digital gr ound.

100985A Conexant 1-9

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-1. CX2833i-1x Pin Definitions (6 of 6)

Pin #

Signal Name Description I/O/P Notes

CX28331-1x CX28332-1x CX28333-1x

4, 5, 20, 21 12, 13 — VD D Power P Connect to 3.3 V power.
1, 8, 17, 24 9, 16 — VSS Ground P Connect to ground.

Miscellaneous

58 ——PD Power down for Ch1 I Power down tr ansceiver channel
— 76 76 PD1
— 25 58 PD2 Power down for Ch2 I
——25 PD3

47 ——REFCLK Reference cl ock for Ch1 I Reference clock from off-chip.
— 65 65 REFCLK1
— 36 47 REFCLK2 Reference clock for Ch2 I
——36 REFCLK3 Reference clock for Ch3 I

Power down for Ch3 I

80 80 80 RBIAS Bias resistor O A 12.1 kΩ ± 1% resistor tied from

0 = Power down channel (o ff)
1 = Channel active (on)
Note: A special power-down mode
exists when all three PDBs are set
low. Th is special mode shut s off the
entire chip (including biasing). This
is useful for static Idd testi ng.

This clock should b e set to one of
the following:

• E3 rate (34.368 MHz)

• DS3 rate (44.736 MHz)

• STS-1 rate (51.84 MHz)

The clock rate should correspond to
the mode of operation that has been
chosen for the channel.

this pin to ground provides the
current reference to the entire

(2)

chip.

78 78 78 Reset Reset I/O Asynchronous reset (reset ent ire

device).

77 77 77 GPD Global Power down I/O Power down (Static Idd testing).

0 = Power down disable
1 = Power down active

2, 3, 6, 7, 18,

19, 22, 23,
25, 26, 27,
29, 30, 31,
32, 33, 34,
35, 36, 37,
38, 39, 40,
42, 61, 62,
63, 64, 65,
66, 67, 68,
69, 70, 71,
72, 74, 75,

76

NOTE(S):

(1)

This pin should be c onnected to 3.3 V in an all -3.3 V design.

(2)

Placing a capacitor from this pin to ground may result in instabilities.

3. All digital input pins contai n a 75 kΩ pull-down resistor from input to DVSS.

10, 11, 14,

15, 42,

44–58

42 NC No connect — Not connected.

1-10 Conexant 100985A

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 1-4. CX28331-3x Pin Diagram

VSS

RBIAS

VGG

RESET

GPDNCNCNCDVDDIONCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

9998979695949392919089888786858483828180797877

100

1

NC

2

NC

3

NC

4

NC

NC
NC

NC
NC
NC
NC

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

CX28331-3x

VDD
VDD

VSS

TVSS
TMONP
TLINEP

TLINEM
TMONM

TVDD
RVDD

RLINEP

RLINEM

RVSS

VSS

VDD

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DVDDC
ENDECDIS
PD
RLOOP
LLOOP
RNEG/RLCV
RPOS/RNRZ
RCLK
RLOS
NC
NC
NC
TAIS
TCLK
TPOS/TNRZ
TNEG/NC
TLOS
REFCLK
REQH
XOE
LBO
TMONTST
E3MODE
NC
DVSSC

1.1 Pin Assignments

VDD

NC

NC

NCNCNC

VSS

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

DVSSIO

100985_015

100985A Conexant 1-11

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 1-5. CX28332-3x Pin Diagram

TVSS1

RBIAS

VGG

RESET

GPD

PD1

RLOOP1

LLOOP1

DVDDIO

LBO1

XOE1

REQH1NCNCNCRNEG1/RLCV1

RPOS1/RNRZ1

RCLK1

RLOS1

REFCLK1

TLOS1

TNEG1/NC1

TPOS1/TNRZ1

TCLK1

TAIS1

TMON1P

TLINE1P

TLINE1M

TMON1M

TVDD1

RVDD1

RLINE1P

RLINE1M

RVSS1

VSS

NC
NC
NC

NC
VDD
VDD

NC

NC
VSS

TVSS2

TMON2P

TLINE2P

TLINE2M

TMON2M

TVDD2

9998979695949392919089888786858483828180797877

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

PD2

RVSS2

RVDD2

RLINE2P

RLINE2M

RLOOP2

DVSSIO

LLOOP2

CX28332-3x

NCNCNC

LBO2

XOE2

REQH2

RCLK2

RLOS2

REFCLK2

RNEG2/RLCV2

RPOS2/RNRZ2

TLOS2

TNEG2/NC2

TPOS2/TNRZ2

TAIS2

TCLK2

76

NC

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DVDDC
ENDECDIS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TMONTST
E3MODE
NC
DVSSC

100985_016

1-12 Conexant 100985A

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 1-6. CX28333-3x Pin Diagram

TVSS1

RBIAS

VGG

RESET

GPD

PD1

RLOOP1

LLOOP1

DVDDIO

LBO1

9998979695949392919089888786858483828180797877

100

TMON1P

TLINE1P

TLINE1M

TMON1M

TVDD1

RVDD1

RLINE1P

RLINE1M

RVSS1

TVSS2

TMON2P

TLINE2P

TLINE2M

TMON2M

TVDD2

RVDD2

RLINE2P

RLINE2M

RVSS2

TVSS3

TMON3P

TLINE3P

TLINE3M

TMON3M

TVDD3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

CX28333-3x

XOE1

REQH1NCNCNCRNEG1/RLCV1

RPOS1/RNRZ1

RCLK1

RLOS1

REFCLK1

TLOS1

TNEG1/NC1

TPOS1/TNRZ1

TCLK1

TAIS1

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1.1 Pin Assignments

DVDDC
ENDECDIS
PD2
RLOOP2
LLOOP2
RNEG2 / RLCV2
RPOS2 / RNRZ2
RCLK2
RLOS2
NC
NC
NC
TAIS2
TCLK2
TPOS2/TNRZ2
TNEG2/NC2
TLOS2
REFCLK2
REQH2
XOE2
LBO2
TMONTST
E3MODE
NC
DVSSC

RVDD3

RLINE3P

PD3

RVSS3

RLINE3M

DVSSIO

LLOOP3

RLOOP3

LBO3

XOE3

REQH3

NCNCNC

RCLK3

RLOS3

REFCLK3

RNEG3/RLCV3

RPOS3/RNRZ3

TLOS3

TNEG3/NC3

TPOS3/TNRZ3

TAIS3

TCLK3

NC

100985_006

100985A Conexant 1-13

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-2. CX2833i-3x Pin Definitions (1 of 8)

Pin #

Signal Name Description I/O/P Notes

CX28331-3x CX28332-3x CX28333-3x

Coaxial Line Pins

17 ——RLINEP Ch1 positive
— 77RLINE1P
18 ——RLINEM Ch1 negative
— 88RLINE1M
— 27 17 RLINE2P Ch2 positive

— 28 18 RLINE2M Ch2 negative

——27 RLINE3P Ch3 positive

——28 RLINE3M Ch3 negative

12 ——TLINEP Ch1 positive
— 22TLINE1P
13 ——TLINEM Ch1 negative
— 33TLINE1M
— 22 12 TLIN E2P Ch2 positive

— 23 13 TLINE2M Ch2 negative

receive data

receive data

receive data

receive data

receive data

receive data

transmit data

transmit data

transmit data

transmit data

I Differential inputs for each channel from its

respective receive coax line. The RX expects
balanced differential inputs, usually
achieved using a 1:1 transformer.

I

The inputs are internally DC bi ased to 1.9 V.

I

I

I

I

O Differential, coax-driver balanced outputs

for pulse-shaped AMI B3ZS/HDB3 encoded
waveforms for each channel.

O

These pins should be connected to the
primary side of the 1:1 transformer through
two backmatch resistors (see Ap pendix B).

O

O

——22 TLINE3P Ch3 positive

transmit data

——23 TLINE3 M Ch3 negative

transmit data

1-14 Conexant 100985A

O

O

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-2. CX2833i-3x Pin Definitions (2 of 8)

Pin #

Signal Name Description I/O/P Notes

CX28331-3x CX28332-3x CX28333-3x

Digital Data Pins

69 ——RPOS/

RNRZ

— 84 84 RPOS1/

RNRZ1

70 ——RNEG/

RLCV

— 85 85 RNEG1/

RLCV1

— 41 69 RPOS2/

RNRZ2

— 40 70 RNEG2/

RLCV2

Ch1 receive
Positive rail or
NRZ data

Ch1 receive
Negative rail or
line code
violation

Ch2 receive
Positive rail or
NRZ data

Ch2 receive
Negative rail or
line code
violation

1.1 Pin Assignments

O Resynchronized receive data intended to be

strobed out by the corresponding RCLK.
When ENDECDIS = 1, these outputs are

positive and negative A MI data (RPOS and
RNEG).

O

When ENDECDIS = 0, these outputs are
decoded NRZ data (RNRZ) and line code
violation (RLCV). A line code violati on is
indicated when RLCV = 1.

O

See notes on the ENDECDIS pin in the

O

Control Signals section.

——41 RPOS3/

RNRZ3

——40 RNEG3/

RLCV3

68 ——RCLK Receive clock

— 83 83 RCLK1
— 42 68 RCLK2 Receive clock

——42 RCLK3 Recei ve clock

Ch3 receive
Positive rail or
NRZ data

Ch3 receive
Negative rail or
line code
violation

Ch1

Ch2

Ch3

O

O

O Recov ered clock for each channel receiver,

intended for strobing the corresponding
RDAT into the following framer or logic.

O

O

100985A Conexant 1-15

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-2. CX2833i-3x Pin Definitions (3 of 8)

Pin #

Signal Name Description I/O/P Notes

CX28331-3x CX28332-3x CX28333-3x

61 ——TPOS/

TNRZ

— 78 78 TPOS1/

TNRZ1

60 ——TNEG/

NC

— 79 79 TNEG1/

NC1

— 47 61 TPOS2/

TNRZ2

— 46 60 TNEG2/

NC2

——47 TPOS3/

TNRZ3

——46 TNEG3/NC3 Ch3 transmit

62 ——TCLK Transmit clock
— 77 77 TCLK1

Ch1 transmit
Positive rail or
NRZ data

Ch1 transmit
Negative rail or
no connect data

Ch2 transmit
Positive or NRZ
data

Ch2 transmit
Negative data or
no connect data

Ch3 transmit
Positive or NRZ
data

Negative data or
no connect data

Ch1

I Synchronized tr ansmit data inte nded to be

strobed in by the corr esponding TCLK.

When ENDECDIS = 1, the se inputs are
expected to be positive and negative AMI

I

data (TPOS and TNEG).
When ENDECDIS = 0, the se inputs are

expected to be uncoded NRZ data (TNRZ)
and no connects (NC).

I

See notes on the ENDECDIS pin in the
Control Signal section.

I

I

I

I Transmit bit clock input for strobing with

transmit data into the CX283 3i .

— 48 62 TCLK2 Tr ansmit clock

Ch2

——48 TCLK3 Transmi t clock

Ch3

67 ——RLOS Loss of signal

— 82 82 RLOS1
— 43 67 RLOS2 Loss of sig n al

——43 RLOS3 Loss of signa l

Ch1

Ch2

Ch3

I

I

O Loss Of Signal (LOS) indication for each

channel, as determined by insufficient pulse
density. Signal loss detected when RLOS =

1. An LOS will be asserted when 175 ±75 0s

O

occur in a row and deasserted when the
pulse density is between 28% and 33%

O

(DS3/STS-1) (i.e., a 1s density).

1-16 Conexant 100985A

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-2. CX2833i-3x Pin Definitions (4 of 8)

Pin #

Signal Name Description I/O/P Notes

CX28331-3x CX28332-3x CX28333-3x

Control Signals

74 74 74 ENDECDIS Encoder/decoder

disable (for all
channels)

63 ——TAIS Transmit Ch1

— 76 76 TAIS1
— 49 63 TAIS2 Transmit Ch2

——49 TAIS3 Transmit Ch3

53 53 53 E3MODE E3MODE I When the pin is set to high, it enables the

55 ——LBO Transmit line

— 91 91 LBO1
— 34 55 LBO2 Transmit line

——34 LBO3 Transmit line

AIS mode enable

AIS mode enable

AIS mode enable

Ch1 build-o ut
mode

Ch2 build-o ut
mode

Ch3 build-o ut
mode

I 1 = Dual rail pu ls e cod e d d ata fo rmat. Input

transmit data pins TPOS, TNRZ, TNEG and
NC are interpreted as TPOS and TNEG
(encoded positive and negative rail data).
Output receive data pins RPOS and RNRZ,
and RNEG and RLCV are interpreted as
RPOS and RNEG, with RPOS having a
positive pulse in place of every positive AMI
pulse and RNEG having a negative pulse in
place of every negative AMI pulse.

0 = NRZ format. Transmit data pins TPOS
and TNEG are interpreted as TNRZ and NC
(not connected). Receive data pins RPOS
and RNEG are interpreted as RNRZ and
RLCV. In this mode, all line code violations
are reported as active high on RLCV.

I Transmission of Alarm Indication Signal

(AIS) for a given channel. Replace transmit
data with AIS signal. The AMI form of AIS
supported is alternating 1s.

I

—

I Line build-out mode per channel, based on

I

I

(+1, -1, +1, -1, +1, ...)
Looping takes precedence over AIS.
1 = AIS mode enabled
0 = AIS mode disabled

E3 mode on all channels, instead of the
DS3/STS-1 mode. Thi s also changes the
pulse shaper to E3 mode and overrides all
LBO pins. It also changes the
encoder/decoder from B3ZS mode to HDB3
mode.
1 = E3 mode
0 = DS3/STS-1 mode

the length of cable on t he transmit side of
the cross-connect block. This bit is
overridden and the pulse shaper is disabled
(no pulse shaping) if E3MO DE = 1.

1 = Inserts line build-out into the transmit
channel. Usually used when the transmit
cable is less than 350 f eet in length.

0 = Line build-out bypasse d (not inserted).
Usually used when the transmit cable is
greater than 350 feet in le ngth.

1.1 Pin Assignments

100985A Conexant 1-17

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-2. CX2833i-3x Pin Definitions (5 of 8)

Pin #

Signal Name Description I/O/P Notes

CX28331-3x CX28332-3x CX28333-3x

71 ——LLOOP Local loo pback
— 93 93 LLOOP1
— 32 71 LLOOP2 Local loopback

——32 LLOOP3 Local loopback

72 ——RLOOP Remote
— 94 94 RLOOP1

— 31 72 RLOOP2 Remote

——31 RLOOP3 Remote

56 ——XOE Transmit output
— 90 90 XOE1
— 35 56 XOE2 Transmit output

——35 XOE3 Transmit output

57 ——REQH Ch1 Receive
— 89 89 REQH1

— 36 57 REQH2 Ch2 Receive

——36 REQH3 Ch3 Receive

enable Ch1

enable Ch2

enable Ch3

loopback enable
Ch1

loopback enable
Ch2

loopback enable
Ch3

enable Ch1

enable Ch2

enable Ch3

High EQ Gain
Enable

High EQ Gain
Enable

High EQ Gain
Enable

I Local loopback enable per channel. The

transmit data is looped back immediately
from the encoder to the decoder in place of
the received data.

I

1 = local loopback enabled

I

0 = local loopback disabled

I Remote loopback enable p e r channel. The

receive data, retimed after clock recovery, is
looped back into the AMI generator in place
of the transmit data.

I

1 = remote loopback enabled
0 = remote loopback disabled

I

I Transmit output enable per channel.

1 = transmit line output driver enabled
0 = transmit output driver set to high

I

impedance state

I

I The equaliz er in the CX2 83 3i has two gain

settings. The higher gain setting is designed
to optimally equalize a nominally- s haped
(meets the pulse template), pulse-driven

I

DS3 or STS-1 wavefor m that is driv e n
through 0–900feet of cable.
Square-shaped pulses such as E3 or
DS3-HIGH requir e less high -fr equ ency gain

I

and should use the low EQ gain setting.
REQH = 1 high EQ gain (DS3/STS-1modes)
REQH = 0 low EQ gain (E3/DS3

Square Modes)

Power/Ground

15 ——TVDD TX power Ch1 P Power pins for t ransmit circuitry pe r

55TVDD1

— 25 15 TVDD2 TX power Ch2 P
——25 TVDD3 TX power Ch3 P

1-18 Conexant 100985A

channel (3.3 V).

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-2. CX2833i-3x Pin Definitions (6 of 8)

Pin #

Signal Name Description I/O/P Notes

CX28331-3x CX28332-3x CX28333-3x

10 ——TVSS TX ground Ch1 P Ground pins for transmit circuitry per
— 100 100 TVSS1
— 20 10 TVSS2 TX ground Ch2 P
——20 TVSS3 TX ground Ch3 P
16 ——RVDD RX power Ch1 P Power pins for receive circuitry per channel
— 6 6 RVDD1
— 26 16 RVDD2 RX power Ch2 P
——26 RVDD3 RX power Ch3 P
19 ——RVSS RX ground Ch1 P Gr ound pins for receive circuitry per
— 9 9 RVSS1
— 29 19 RVSS2 RX ground Ch2 P
——29 RVSS3 RX ground Ch3 P

75 75 75 DVDDC Digital core

power

channel.

(3.3 V).

Connect to 3.3 V power.

channel.

Connect to ground .

P Digital core power for all channels (3.3 V).

1.1 Pin Assignments

51 51 51 DVSSC Digital core

ground

98 98 98 VGG 5 V/3.3 V ESD

92 92 92 DVDDIO Digit al I/O power P Connect to 3.3 V digital power.

pin

(1)

P Digital core ground for all channels.

P 5 V suppl y for 5 V - to le ra nt, digital pad ESD

diodes. No static power is drawn from pi n.

33 33 33 DVSSIO Digital ground P Digital ground.

5, 6, 25, 26 15, 16 — VDD Power P Connect to 3.3 V power.

9, 20, 29,

100

73 —— PD Power down for

— 95 95 PD1
— 30 73 PD2 Power down for

——30 PD3 Power down for

10, 19 — VSS Ground P Connect to ground.

Miscellaneous

I Power down transceiver channel

Ch1

Ch2

Ch3

0 = Power down channel (off)
1 = Channel active (on)

I

Note: A special power-down mode exists
when all three P DBs are set low. This

I

special mod e shuts off the en tire chip
(including biasing). This is useful for static
Idd testing.

100985A Conexant 1-19

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-2. CX2833i-3x Pin Definitions (7 of 8)

Pin #

Signal Name Description I/O/P Notes

CX28331-3x CX28332-3x CX28333-3x

58 ——REFCLK Reference clock
— 81 81 REFCLK1
— 44 58 REFCLK2 Reference clock

——44 REFCLK3 Reference clock

99 80 99 RBIAS Bias resistor O A 12.1 kΩ ± 1% resistor tied from thi s pi n

97 97 97 Reset Reset I/O Asynchronous reset (reset entire device).
96 96 96 GPD Global Power

for Ch1

for Ch2

for Ch3

down

I Refere n ce cl o c k f r o m of f -chip.

This clock should be set to one of the
following:

I

I

I/O Power down (Static Idd testing).

• E3 rate (34.368 MHz)

• DS3 rate (44.736 MHz)

• STS-1 rate (51.84 MHz)

The clock rate should correspond to the
mode of operation that has been chosen for
the channel.

to ground provides the current reference to
the entire chip.

(2)

0 = Power down disable

1 = Power down active

11 ——TMONP Ch1 positive
— 11TMON1P
14 ——TMONM Ch1 negative

— 44TMON1M
— 21 11 TMON2P Ch2 positive

— 24 14 TMON2M Ch2 negative

input

input

input

input

I Transmit monitor input pins are no rmally

tied to their respective transmit line
outputs, i.e., (TMON1P

I

TMON1M

when the monitor inputs detect no signal.

I

TLOS outputs when TMONTST is high.
This is used to test board level functionality

I

downstream fro m the TLOS outputs.

⇒ TLINE1M).

Loss of signal outputs are active high

The TX monitor test pin will ass ert all

⇒ TLINE1P and

——21 TMON3P Ch3 positive

input

——24 TMON3M Ch3 negative

input

59 ——TLOS TX loss of s ignal

— 80 80 TLOS1
— 45 59 TLOS2 TX loss of si gnal

——45 TLOS3 TX loss of signal

54 54 54 TMONTST TX monitor test

1-20 Conexant 100985A

Ch1 Output

Ch2 Output

Ch3 Output

pin

I

I

O

O

O

I

CX28331/CX28332/CX28333 1.0 Pin Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Table 1-2. CX2833i-3x Pin Definitions (8 of 8)

Pin #

Signal Name Description I/O/P Notes

CX28331-3x CX28332-3x CX28333-3x

1–4, 7, 8,
21–24, 27,
28, 30–32,
34–50, 52,

64–66,
76–91,

93–95

NOTE(S):

(1)

This pin should be connected to 3.3 V in an all-3.3 V design.

(2)

Placing a capacitor from this pin to ground may result in instabilities.

3. All digital input pins contain a 75 kΩ pull-down resistor from input to DVSS.

11–14,

17–18,
37–39, 50,
52, 55–73,

86–88

37, 38, 39,
50, 64, 65,
66, 86, 87,

88

52 No connect — Not connected.

1.1 Pin Assignments

100985A Conexant 1-21

1.0 Pin Description CX28331/CX28332/CX28333

1.1 Pin Assignments Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

1-22 Conexant 100985A

2

2.0 Functional Description

2.1 Overview

CX28333 is a triple E3/DS3/STS-1 Line Interface Unit (LIU). It is the physical
layer interface betw een t he data fra mer (or other terminal-side equi pment) and the
electrical cable used for data transmission.

The CX28333 LIU consists of three independent data transceivers that can
operate over type 734/728 coaxial cable at the rates of 34.368 Mbps (E3), 44.736
Mbps (DS3), and 51.84 Mbps (STS-1). The transmit side takes an NRZ or
already-encoded dual rail input and encodes it into AMI B3ZS (for DS3/STS-1)
or HDB3 (for E3) analog waveforms to be transmitted o v er t he coaxial cab le. The
receiver side takes in the attenuated and distorted analog receive signal and
equalizes, slices, and resynchronizes the signal before decoding it to the NRZ
output or sending out a non-decoded dual rail.

CX28331 and CX28332 are single- and dual-E3/DS3/STS-1 LIUs,
respectively. In all respects, their performance and features are identical to the
CX28333.

The architecture of the CX2833i includes the following internal functions for
each channel:

Transmitter:

• AMI B3ZS/HDB3 encoder

• pulse shaper

• line driver

• Alarm Indication Signal (AIS) insertion

• transmit monitor

Receiver:

• receive sensitiv ity

• Automatic Gain Control (AGC)

• receive equalizer

• Clock Recovery circuit

• Loss Of Signal (LOS) detector

• B3ZS/HDB3 decoder with bipolar violation detector

• data squelching

100985A Conexant 2-1

2.0 Functional Description CX28331/CX28332/CX28333

2.1 Overview Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Additional Functions:

• bias generator

• power-on reset

• loopback MUXes

In addition, each channel has the ability to perform remote and local
loopbacks. Figure 2-1 illustrates a typical application using the CX2833i in a
channel.

External pins are provided to configure the various line rates and formats for
each channel.

The CX2833i is used as a data transceiver over a coaxial cable that is up to
900 feet long (or up to 450 feet from the DSX) in an on-premise environment
within any public or private networks which use these data rates.

Figure 2-1. Typical Application Of Single CX2833i Channel

TX

0–450 ft COAX

(type 734/728)

DSX

0–450 ft COAX

(type 734/728)

RX

RX

0–450 ft COAX

(type 734/728)

DSX

0–450 ft COAX

(type 734/728)

TX

100604_012

2-2 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.2 Transmitter

This section describes the det ailed operati on of the v arious b locks in the C X2833i
transmitter.

2.2.1 AMI B3ZS/HDB3 Encoder

ENDECDIS and the E3MODE pins configure the encoder mode.

When ENDECDIS = 0, the encoder is receiving non-encoded Nonreturn to
Zero (NRZ) data on the TNRZ (TPOS) pin alone, and the NC (no connect)
(TNEG) pin is ignored.

Data is encoded into a representation of a three-level B3ZS (E3MODE = 0) or
HDB3 (E3MODE = 1) signal (conforming to the coding rules as specified in

Appendix A) before goi ng on to the pulse shaper in th e form of tw o binary signals

representing the positive and negative three-level pulses.

When ENDECDIS = 1, the encoder is disabled. The encoder passes
already-encoded data over TPOS (TNRZ) and TNEG (NC) to the pulse shaper.

The transmit digital data is clocked into the chip via a rising TCLK edge,
which must be equa l to the symbol rate (lin e rate). A small dela y ad ded to the data
provides a certain amount of negative data hold time.

2.2.2 Pulse Shaper

The pulse shaper converts the two digital (clocked) positive and negative pulses
into a single analog three-le vel Alternate Mark In version (AMI) pulse. The pulses
are in Return to Zero (RZ) format, meaning that all positive and negative pulses
have a duration of the first half of the symbol period.

For the E3 rate (E3MODE = 1), the AMI pulse is a full-amplitude,
square-shaped pulse with very little slope.

2.2 Transmitter

Figure 2-2. Pulse Shaper

E3

Mode

100985A Conexant 2-3

Pulse

Shaper

LBO

Line Driver

+ Pulse – Pulse

LBO = 0

LBO = 1

100604_008

2.0 Functional Description CX28331/CX28332/CX28333

2.2 Transmitter Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

For DS3/STS-1 rates, a pulse-shaper block is used to shape the transmit
waveform and reduce its high-frequency energy content. This ensures that the
transmit pulse template i s met at the cross-connect block, which follows 0–450
feet of transmit-side coaxial cable.

2.2.3 Line Driver

The differential line dri v er takes the filtered transmit wa v eform, increases it to the
proper level, and drives it into the transmit magnetics. The two external discrete
back-matching resistors (36
an approximately 150
loss in the back-matching resistors.

Figure 2-3 illu strates the Pulse/Power template measureme nt points for the

various data rates.

Figure 2-3. Pulse Measurement Points

Ω) aid in line matching. The driver is presented with

Ω differential load. Driver gain accounts for the 6 dB gain

TX

RX

Pulse/Power Template for DS3/STS-1

0–450 ft COAX

(type 734/728)

Pulse/Power Template for E3

0–450 ft COAX

(type 734/728)

DSX

DSX

0–450 ft COAX

(type 734/728)

0–450 ft COAX

(type 734/728)

RX

TX

100604_013

2-4 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.2.3.1 Transmit Pulse Mask Templates

Figure 2-4. Transmit Pulse Mask for DS3 Rates

1.2

1

0.8

0.6

0.4

0.2

Normalized Pulse Amplitude

Transmit Pulse Mask for STS-1 Rates

2.2 Transmitter

0

0.2
1 0.5 0 0.5 1 1.5

Normalized Symbol Time

Table 2-1. DS3 Transmit Template Specifications

Time Axis Rang e (UI) Normalized Amplitude Equation

Upper Curve

–0.85 ≤ T ≤ –0.68 0.03
–0.68 ≤ T ≤ 0.36 0.03 + 0.5 {1 + sin [(pi / 2)(1 + T / 0.34)]}

0.36 ≤ T ≤ 1.4
Lower Curve

–0.85 ≤ T ≤ –0.36 –0.03
–0.36 ≤ T ≤ 0.36 –0.03 + 0.5{1 + sin[(pi / 2)(1 + T / 0.18)]}

0.08 + 0.407 e

–1.84(T – 0.36)

100985_014

0.36 ≤ T ≤ 1.4 0.03

100985A Conexant 2-5

2.0 Functional Description CX28331/CX28332/CX28333

2.2 Transmitter Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 2-5. Transmit Pulse Mask for STS-1 Rates

1.2

1

0.8

0.6

0.4

0.2

Normalized Pulse Amplitude

Transmit Pulse Mask for STS-1 Rates

0

0.2
1 0.5 0 0.5 1 1.5

Normalized Symbol Time

100985_014

Table 2-2. STS-1 Transmit Template Specifications

Time Axis Range (T) Normalized Amplitude Equation

Upper Curve

–0.85 ≤ T ≤ –0.68 0.03
–0.68 ≤ T ≤ 0.26 0.03 + 0.5{1 + sin [(pi / 2)(1 + T / 0.34)]}

0.26 ≤ T ≤ 1.4
Lower Curve

–0.85 ≤ T ≤ –0.38 –0.03
–0.38 ≤ T ≤ 0.36 –0.03 + 0.5{1 + sin[(pi / 2)(1 + T / 0.18)]}

0.36 ≤ T ≤ 1.4 0.03

0.1 + 0.61 e

–2.4(T – 0.26)

2-6 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 2-6. Transmit Pulse Mask for E3 Rate

Volts

Normalized

0.2

0.2

0.1

0.1

0.1

0.1

0.1

17 ns

14.55 ns

8.65 ns

12.1 ns

24.5 ns

29.1 ns
Time

2.2 Transmitter

100985_007

100985A Conexant 2-7

2.0 Functional Description CX28331/CX28332/CX28333

2.2 Transmitter Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.2.4 Alarm Indication Signal (AIS) Generator

When TAIS is asser ted, an AIS replaces the transmit data at TPOS and TNEG.
The E3 type of AIS signal (all 1s) is supported. In three- le vel si gnal form, this is a
continuously alternating positive and negative pulse stream, as if the transmit data
were a continuous string of logical 1s. Figure 2-7 illustrates the AIS signal.

The T AI S pin has the same data latenc y as the TX data pins and can be used to
replace single symbols within a data stream. When the encoder is disabled
(ENDECDIS = 1), the TAIS mode maintains the proper phase, based upon the
polarity of the last 1 received.

The AIS signal follows the same path as the TX data during remote or local
loopback.

Figure 2-7. AIS Signal

POSITIVE

PULSE

NEGATIVE

PULSE

TLINEP

(output voltage)

TLINEN

(output voltage)

8333_009

2.2.5 Transmit Monitor Block (CX2833i-3x Only)

The transmit monitor inputs (TMONP and TMONM) are designed to monitor t he
line driver outputs (TLINEP and TLINEM/N) for pulses and to assert a Loss Of
Signal (TLOS) indicator when no output pulse has been detected for 32 TCLK
periods. After TLOS is asserted, it will not deassert until a pulse is again
detected. The transmit monitor is an indepe ndent funct ion i n whi ch TMONP and
TMONM must be externally connec ted to TLINEP and TLINEM/N , respecti vel y.
A special pin (TMONTST) is available for testing board-level functionality
downstream from the TLOS outputs. When TMONST is high it will assert all
TLOS channel outputs. TL OS outputs ar e acti v e high w hen the monitor i nputs do
not detect a signal.

2-8 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.2.6 Jitter Generation (Intrinsic)

The CX2833i device meets the jitter generation requ ire m e nts for various rates
with large margins, with the condition that the input transmit clock (TCLK) is
jitter-free. Data rates and jitter generation requirements are defined in the
following docume nt s:

• E3 rate—ETSI TBR24, ITU-T 9.823

• DS3 rate—Bellcore Telecardia GR499, AT&T Accunet TR54014,

ITU-T 9.824

• STS-1 rate—Bellcore

Telecardia

2.2 Transmitter

GR253

100985A Conexant 2-9

2.0 Functional Description CX28331/CX28332/CX28333

2.3 Receiver Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.3 Receiver

This section describes the det ailed operati on of the v arious b locks in the C X2833i
receiver.

2.3.1 Receive Sensitivity

The receiver recovers data from the coaxial cable that is attenuated due to the
frequency-dependent characteristics of the cable. In addition, the receiver
compensates for the flat loss (across all frequencies) in the various electrical
components and the variation in transmitted signal power.

The CX2833i device is able to recover data that has been attenuated by a
maximum of 900 feet of coax having characteristics and attenuation consistent
with ANSI T1.102-1993, Annex C, Figure C.2. This approximates the
characteristics of AT&T type 734/728 cable; almost the same attenuation
characteristic is achieved by one-half the length of AT&T type 735 cable.

2.3.2 AGC/VGA Block

The Variable Gain Amplifier (VGA) receives the AMI input signal from the
coaxial cable. The VGA supplies flat gain (independent of frequency ) to make up
for various flat losses in the transmission channel and for loss at one-half the
symbol rate that cannot be made up by the equalizer. The VGA gain is controlled
by a feedback loop which senses the amplitude of the equalizer output, acting to
servo this amplitude for optimal slicing.

2.3.3 Receive Equalizer

The receive equalizer receives the differential signal from a VGA and acts to
boost the high frequency content of th e signal t o redu ce inter - symbol interf erence
(ISI) to the point that correct decisions can be made b y the slicer with a mi nimum
of jitter in the recovered data.

equivalent cable lengths) for cases where a square-shaped pulse (that does not
meet the DS3/STS-1 standards) is transmitted to the receiver. A square-shaped
input has a much larger high-frequency content and could have overshoots at the
EQ output high enough to cause bit errors. Setting REQH = 0 will lower the gain
and reduce the amount of overshoot.

The REQH pin is provided to allow lower amounts of equalization (shorter

2-10 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.3.4 The PLL Clock Recovery Circuit

The clock reco v ery circuit (RX PLL) e xt racts the e mbedded cl ock from the sliced
data and provides this clock and the retimed data to the decoder (data mode).
Upon startup (after the internal reset is deasserted), the RX PLL uses a reference
clock (REFCLK, running at the symbol rate) and a phase-frequency detector to
lock to the correct data rate (reference mode). During reference mode, the data
outputs are squelched (set to 0). The RX PLL is kept in reference mode until a
valid inpu t is det ect e d.

2.3.5 Loss Of Signal (LOS) Detector

The Receive Loss Of Signal (RLOS) is a digital function which monitors the
retimed data from the clock recovery block. The AMI data is checked for a
continuous run of zeroes. When a continuous run of 128 ± 1 consecutive zeroes
occurs, the RLOS signal is asserted. After the RLOS signal is asserted , a 1s count
is made on every block of 128 AMI symbols. The RLOS signal is deasserted
when the 1s count within a block of 128 symbols is at least:

B3ZS: Minimum 1s density = 39 ± 1 count out of 128 (~30.5%)

HDB3: Minimum 1s density = 29 ± 1 count out of 128 (~22.7%)

The RLOS detector will always monitor the cable-side RX inputs. The
detector is not affected by the state of remote or local looping.

2.3 Receiver

2.3.6 B3ZS/HDB3 Decoder With Bipolar Violation Detector

In the CX2833i device, when ENDECDIS = 0 (encoder/decoder enabled), the
decoder takes the output from the clock recovery circuit and decodes the data
(HDB3 or B3ZS) into a single retimed NRZ data signal. The data signal is then
sent out of the CX2833i over the RNRZ (RPOS) pin. Any detected Line Code
Violations (LCV) are sent out over the corresponding RLCV (RNEG) pin. The
RLCV pin is asserted for one symbol period at the time the violation appears on
the RX output pin (RNRZ).

The following shows data sequence criteria for LCV; violations are indicated
in bold text. A valid bipolar pulse is indicated by a B. A bipolar violation
(non-alternating positive or negative) pulse is indica t ed by a V.

• Excessive zeros: 0, 0, 0, 0 (HDB3) or 0, 0, 0 (B3ZS). These violations are

passed on as 0 data on the RNRZ pin.

• Bipolar violation: B, 0, V (i.e., +1, 0, +1 or -1, 0, -1 for HDB3) B, V

(B3ZS and HDB3). These violation s are passed on as 1 data on the RNRZ
pin.

• Coding violation: 0, 0, V (HDB3) or 0, V (B3ZS) with an even number of

Bs since the last valid 0 substitution V (follows coding rule). These
violations are passed on as 0 data on the RNRZ pin.

The even /odd co unter ( used to count the number of Bs bet w een Vs) will co unt
a bipolar violation as a B. A coding violation or a valid 0 substitution resets the
counter.

100985A Conexant 2-11

2.0 Functional Description CX28331/CX28332/CX28333

2.3 Receiver Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

When ENDECDIS = 1, the decoder is disabl ed, and the retimed slicer outputs
are sent out ov er RPOS (RNRZ) and RNEG (RLCV) pins. These outputs are then
decoded by the Framer or other downstream device. Line code violations are not
detected in this mode of operation. The decoder is configurable for either:

• E3 mode using HDB3 coding (E3MODE = 1)

• DS3/STS-1 mode using B 3ZS coding (E3MODE = 0)

The receiver digital data outputs are centered on the rising edge of RCLK
(see Section 2.9).

2.3.7 Data Squelching

A counter in the receiver keeps track of the number of consecutive symbol
periods without a vali d data pulse. Wh en 128 or more 0s i n a ro w ar e counte d, the
receiver assumes that it has lost the signal and resets itself to try and regain the
signal. While the receiv er is reacquiring the signal, the clock recovery block locks
to the reference clock and the data squelching is achie v ed by forcing the data bi ts
to zero. The data squelching is true in both NRZ and dual rail mode. When the
input signal has been properly amplified and equalized, the clock recovery PLL
will then switch to the incoming data.

2-12 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.4 Jitter Tolerance

The CX2833i receiver is able to tolerate a specified amount of high-frequency
jitter in the received signal while providing error-free operation (generally
defined as a bit error rate of less than 10

Figure 2-9) for ji tter tolerance are discussed in the following documents:

• E3 rate – ITU-T G.8 23 and ETSI TBR24 contain frequency mask s for input

jitter tolerance.

NOTE: To meet jitter transfer requireme nts for loop-timed operation, an external

jitter attenuator is required. The jitter attenuator le sse ns jitter from the
receive clock.

• DS3 rate – ITU-T G.823 and Bellcore GR499 specify jitter tolerance

frequency masks for Category I and Category II interfaces.

• STS-1 rate – Bellcore GR253 specifies a jitter tolerance. It is noted that the

STS-1 jitter tolerance differs from DS3 requirements only for Category II
interfaces.

2.4 Jitter Tolerance

-9

). The specifications (illustrated in

100985A Conexant 2-13

2.0 Functional Description CX28331/CX28332/CX28333

2.4 Jitter Tolerance Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 2-8. Minimum Jitter Tolerance Requirement

E3 Rate

1.0 UI

Input Jitter AmplitudeInput Jitter Amplitude

0.1 UI

100 Hz 1 kHz 10 kHz 100 kHz 1 MHz

Jitter Frequency

10 UI

1.0 UI

0.1 UI

DS3 / STS-1 Rates

10 Hz 100 Hz 10 kHz 100 kHz1 kHz

Jitter Frequency

STS-1

DS3 Category I

DS3 Category II

100604_014

2-14 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.4.1 Jitter Transfer

The receiver must meet ce rtain jitter t ransfer specifications between the input and
output jitter as a function of fre quency. These specifications are only intended to
be met with the use of a jitter att enuator. Because the CX2833i does not contain a
jitter attenuator, one will have to be supplied externally. For reference purposes,
the specifications are discussed in the following documents and shown in

Figure 2-9.

E3 rate—Assume the same as DS3.

DS3 rate—Bellcore GR499, section 7.3.2 and figures 7-3, 7-4, and 7-5,
defines and describes DS3 jitter transfer.

STS-1 rate—Bellcore GR253, section 5.6.2.1, defines and describes jitter
transfer for the STS-1 rate.

Figure 2-9. Maximum Jitter Transfer Curve Requirement

0.1 dB

2.4 Jitter Tolerance

Jitter Gain

–19.9 dB

STS-1 Category II

DS3 Category I

DS3 Category II

10 Hz 100 Hz 1 kHz 10 kHz 100 kHz

Jitter Frequency

(Note: All slopes are 20 dB/decade)

100985_012

100985A Conexant 2-15

2.0 Functional Description CX28331/CX28332/CX28333

2.5 Additional CX2833i Functions Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.5 Additional CX2833i Functions

2.5.1 Bias Generator

To achieve good isolation between the channels, each channel utilizes an
independent power and ground to both transmit and receive. Additionally, each
channel has its own band gap voltage reference. Because only one external
resistor for current generation exist s, only one band gap v o lt age can be used. The
band gap from Ch1 has been chosen for this task.

The 12.1 k
a tolerance of ±1%. This helps to keep tighter control on power dissipation and
circuit performance.

NOTE: Capacitance should be kept to a minimum on the RBIAS pin.

Ω external resistor from pin RBIAS to ground, is specified to have

2.5.2 Power-On Reset (POR)

A POR function is provided in the CX2833i device to ensure all of the resettable
digital logic and analog control lines are starting from a known state. This circuit
uses a fixed RC timer (~1
(after the RC timer has t i med-out ) b efor e r eset i s d easserted, which begins timing
after a minimum supply voltage is reached (see Table 2-4).

µs); additionally, 128 clocks from REFCLK are counted

2.5.3 Loopback Multiplexers (MUXes)

Two loopback MUXes per channel in the CX2833i allow for local loopback
(terminal or framer side), remote loopback (cable side), or both (the AIS signal
follows the same path as the transmit data during loopback). The RLOS signal
monitors the RX cable inputs irrespective of any loopback.

In remote loopback, set by asserting pin RLOOP high, the receive data
(retimed after clock rec overy but not decoded) loops back into the pulse shaper in
place of the transmit data. Additionally, this data sent out the RPOS, RNEG, and
RCLK pins.

In local loopback, set by asserting pin LLOOP, the transmit data loops back
immediately from the encoder out put to t he decode r input in plac e of the recei v ed
data. Additionally, this data is sent out the TLINEP and TLINEM/N pins.

2-16 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.6 Mechanical Specifications

Figure 2-10. CX2833i-1x Mechanical Drawing (80-Pin)—Dimensions

D

D

1

D

2

D

Pin #1

Ref. Mark

D1D

2

2.6 Mechanical Specific a tio ns

D

3

D

D

1

3

eb

TOP

A

2

A

A

1

L

L

DETAIL B

1

See DETAIL B

c

A
A

1

A

2

D
D

1

D

2

D

3

L
L

1

b
c
e
Coplanarity

Millimeters

Dim.

Min. Max. Min. Max.

1.20 MAX.

0.05

0.95

15.75

13.90

12.35 REF.

6.50 REF.

0.45

1.00 REF.

0.32 REF.

0.09

0.65 REF.

0.10 MAX.

Ref. 80-Pin ETQFP (GP00-D537)

BOTTOM

0.15

0.002

1.05

0.040

16.25

0.620

14.10

0.547

0.75

0.018

0.20

0.004

Inches

0.047 MAX.

0.006

0.041

0.640

0.555

0.486 REF.

0.256 REF.

0.030

0.039 REF.

0.013 REF.

0.008

0.026 REF.

0.004 MAX.

100985_008

100985A Conexant 2-17

2.0 Functional Description CX28331/CX28332/CX28333

2.6 Mechanical Specifications Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 2-11. CX2833i-3x Mechan ical Drawing (100-Pin)—Dimensions

D

D

Pin #1

Ref. Mark

1

D

2

D

3

D

D

D

1

2

eb

TOP

D

D

3

1

BOTTOM

A

A

A

1

2

DETAIL B

L

L

1

See DETAIL B

c

Millimeters

A
A

1

A

2

D
D

1

D

2

D

3

L
L

1

b
e
c
Coplanarity

Dim.

Min. Max. Min. Max.

1.20 MAX.

0.05

0.95

15.75

13.90

12.00 REF.

8.00 REF.

0.45

1.00 REF.

0.22 REF.

0.50 REF.

0.09

0.08 MAX.

Ref. 100-Pin ETQFP (GP00-D543)mm

0.15

1.05

16.25

14.10

0.75

0.20

0.047 MAX.

0.002

0.004

0.620

0.547

0.472 REF.

0.315 REF.

0.018

0.039 REF.

0.009 REF.

0.020 REF.

0.004

0.004 MAX.

Inches

0.006

0.041

0.640

0.555

0.006

0.008

100985_008a

2-18 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.7 Electrical Characteristics

2.7.1 Absolute Maximum Ratings

Table 2-3. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

DVDDC/
RVDD/
TVDD/
VDD

V

I

T

ST

T

VSOL

θ

JA

θ

JA

θ

Jc

FIT Failures in time @ 89,000

2.7 Electrical Characteristics

Power Supply Voltage –0.3 6 V

Voltage on Any Signal Pin –1.0 VGG + 0.3 V V
Storage Temperature –40 125 °C

— 220 °C

— 40

°

Vapor Phase Soldering
Temperature (1 min.)

Thermal Resistance (Still
air, socketed)

Thermal Resistance (Still
air, soldered)

——7.40

device hours, temperature
of 55 °C, 0 failures.

— 24

— 313 fits

°

°

C

/

W

C

/

W

C

/

W

NOTE(S):

1. Stresses above those listed as absolute maximum ratings may cause permanent damage
to the device. This is a stress rating only, and functional operation of the device at these or
any other conditions beyond those indicated in the ot her sections of this document is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

100985A Conexant 2-19

2.0 Functional Description CX28331/CX28332/CX28333

2.7 Electrical Chara c ter i stics Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.7.2 Recommended Operating Conditions

Table 2-4 specifies various operating conditions, power supplies, and the bias

resistor.

Table 2-4. Recommended Operating Conditions

Parameter Conditions Min Nom Max Unit

Power supply voltage DVDDC, RVDD, TVDD,

VDD

ESD voltage
Power dissipation

(CX28333)
Power dissipation

(CX28332)
Power dissipation

(CX28331)
External bias resistor Pin RBIAS to GND; ±1% 11.98 12.1 12.22

NOTE(S):

(1)

(1)

With 5 V logic inp ut, VGG should be tied to 5 V. Wit h 3.3 V lo gic inp ut, VGG sh ould be tied
to 3.3 V.

VGG 3.135 5 5.5 V
Total chip — 0.83 1.0 W

Total chip ——0.8 W

Total chip ——.450 W

3.135 3.3 3.465 V

Ω

k

2-20 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.8 DC Characteristics

Table 2-5. DC Characteristics

Parameter Conditions Min Nom Max Unit

Vih high threshold Digital inputs 2.0 — VGG + 0.3 V
V

low threshold Digital inputs –0.3 — 0.8 V

il

high threshold Digital outputs, Ioh = –4 mA 2.4 ——V

V

oh

V

low threshold Digital outputs, Iol = 4 mA —— 0.4 V

ol

I

LEAK

Input capacit a nce ———10 pF

0 V ≤ digital Vin ≤ VGG

–10 — 200 µA

2.8 DC Characteristics

Load capacitance Digital outputs —— 15 pF

NOTE(S):

1. The digital inputs of CX28 33i are TTL 5 V compliant. These inputs are di ode protected to DVDD IO and DVSSIO pins.
Additionally, all of the CX2833i digital inputs contain 75 k

2. The digital outputs of CX2833i are also TTL 5 V compliant. However, these outputs will not drive to 5 V, nor will they accept
5 V external pull-ups. The output is DVDDC (3.3 V).

Ω pull-down resi sto rs .

100985A Conexant 2-21

2.0 Functional Description CX28331/CX28332/CX28333

2.9 AC Characteristics Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2.9 AC Characteristics

Table 2-6. AC Characteristics (Logic Timing)

Parameter Conditions Min Nom Max Unit

Tosym, Tisym
RCLK and TCLK

Clock Duty Cy cle Tow i dth/Tosym, RCLK

Todelay ———3ns
Tisetup TPOS/TNRZ, TNEG,

Tihold TPOS/TNRZ, TNEG,

NOTE(S):

1. The description applies to the DS3, E3, and STS-1 clock rates and other parameters such
as pulse width, set-up time, hold time, and duty cycle.

2. The timing dia gram, illustra te d i n Figure 2-12, describes the logical relationship between
various clock and data signals, and parameter values.

E3
DS-3
STS-1

Tiwidth/Tisym, TCLK
Tiwidth/Tisym, REFCLK

TAIS

TAIS

— 29.10

22.35

19.29

45
40
40

4 ——ns

0 ——ns

— 55

— ns

ns
ns

%
60
60

%

%

2-22 Conexant 100985A

CX28331/CX28332/CX28333 2.0 Functional Description

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 2-12. Timing Diagram

DATA OUTPUTS

RCLK

RPOS/RNRZ,

RNEG/RLCV

DATA INPUTS

TCLK

Todelay

Tosym

Tisym

2.9 AC Characteristics

Towidth

Tiwidth

TPOS/TNRZ,
TNEG, TAIS,

Don't
Care

Tisetup Tihold

Valid Data

Don't

Care

100604_016

100985A Conexant 2-23

2.0 Functional Description CX28331/CX28332/CX28333

2.9 AC Characteristics Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

2-24 Conexant 100985A

3

3.0 Applications

The CX28331/CX28332/CX28333 can be used in a variety of applications.

Figure 3-1 illustrates an example of three DS3 lines being terminated by the
CX28333. The data and clock are extracted and passed on to the framer chip for
further data manipulation and user interface.

It is important to emp loy high-frequency design techni ques for the printed
board layout.

3.1 PCB Design Considerations for CX2833i

The CX28333 device is a triple LIU operating at frequencies up to 52.84 MHz.
The high-speed nature of the device calls for a careful design of the PCB using
this device. Some design considerations are outlined below.

3.1.1 Power Supply and Ground Plane

A unified power plane with properly placed capacitors of the correct size will
mitigate most power rail-related voltage transients. A properly placed bulk
capacitor, where the power enters the board, with noise-bypassing capacitors at
the power pins on the int egrated circui ts sho uld be adequ ate. The n oise-b yp assing
capacitors must be able to supply all the switching current.

Ferrite beads are used with power rails to filter the high-frequency noise. For
every design, noi se freque ncies and le v els ar e dif f erent. Th erefore, whether beads
are necessary, and the effective frequency where they should operate, is difficult
to determine. It is a good idea to provision for ferrite beads on the boards.

The board trace from the CX28333 power supply pin to the noise-bypassing
capacitor should be minimized. Additionally, ground connections from the
ground plane to the CX28333 ground pins and the noise-bypassing capacitor
ground pins should be minimized.

A unified ground plane is the best way to minimize ground impedance. Most
of the ground noise is produced b y t he return currents and po wer supply transients
during switching. This effect is minimized by reducing the ground plane
impedance.

100985A Conexant 3-1

3.0 Applications CX28331/CX28332/CX28333

3.1 PCB Design Considerations for CX2833i Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

3.1.2 Impedance Matching

It is critical that traces around the transformers and matching resistors be kept to a
minimum length and , i n the following cases, the trace impedance be matched to

Ω with a ±10% tolerance:

75

• The impedance from the BNC connector to the transformer

• The impedance fro m the transformer to the matching resistors

3.1.3 Other Passive Parts

The reference design uses the Pulse T3001 extended temperature range 1:1
transformer for the coupling of the BNC connector to the device.

The ferrite beads used to decouple the receive- and transmit-VDD pins on all
analog input VDD pins are type 2508056017Y0 from Fair-Rite Products
Corporation. The bulk capacitor used for where the power enters the board
should be a tantulum–type capacitor, th e recommended value and t ype is a 220
tantulum capacitor.

µf

3.1.4 IBIS Models

IBIS (Input/Output Buffer Interface Specification) models for the
CX28331/CX28332/CX28333- 1x and - 3 x ar e available from Conexant’s web site
(www.conexant.com).

3.1.5 Recommended Vendors

Product: Transformers Product: Ferrite Beads

America

Address:

Telo:
Fax:

Northern Asia

Telo:

Northern Europe

Telo:
Fax:

Pulse

Corporate Office
12220 World Trade Drive
San Diego, CA 92128
858-674-8100
858-674-8262

Pulse

3F-4, No. 81, Sec. 1
Hsin Tai Wu Road
Hsi-Chih
T a pe i Hsie n, T aiwa n
R.O.C.
886-2-26980228
886-2-26980948

Pulse

1S2 Huxley Road
The Surrey Research Park
Guildford, Surrey GU2 5RE
United Kingdom
44-1483-401700
44-1483-401701

Telo:
Web site:

Telo:
Fax:
E-mail:
Web site:

Fair-Rite Products Corp.

P.O. Box J
One Commercial Row
Wallkill, NY 12589
914-895-2055
www.Fair-Rite.com

Product: Crystals
Crystek Corp.

12730 Commonwea lth Drive
Fort Myers, FL 33913
800-237-3061
941-561-1025
[e-mail]
www.crystek.com

3-2 Conexant 100985A

CX28331/CX28332/CX28333 3.0 Applications

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure 3-1.

CX28333

TMONP

Framer

Framer

TPOS
TNEG
TCLK

Channel 1

RPOS
RNEG
RCLK

MODE BIAS RESET

TPOS
TNEG
TCLK

Channel 2

RPOS
RNEG
RCLK

MODE BIAS RESET

TX

TX

RX

RX

TLINEP

TLINEN

TMONM

RLINEP
RLINEN

TMONP
TLINEP

TLINEN

TMONM

RLINEP
RLINEN

31.6

31.6

37.4

37.4

31.6

31.6

37.4

37.4

W

W

W

W

W

W

W

W

3.1 PCB Design Considerations for CX2833i

Type 728, 734, 735

75

75

75

W

W

W

1:1

0.01µF

1:1

Type 728, 734, 735

1:1

Type 728, 734, 735

Type 728, 734, 735

75

W

0.01µF

1:1

TMONP

TX

RX

TLINEP

TLINEN

TMONM

RLINEP
RLINEN

RBIAS

TPOS
TNEG
TCLK

Framer

NOTE(S):

1. All transformers are part number T30 01 from Pulse Technology. See Recommended Vendors, Section 3.1.5.

2. TMONP and TMONM are only available on the CX 2833i-3x device and are denot ed by dotted lines.

Channel 2

RPOS
RNEG
RCLK

MODE BIAS RESET

MODE BIAS RESET

Mode/Status Pins

31.6

31.6

37.4

37.4

12.1K

W

1:1

W

W

0.01µF

W

W

1:1

Type 728, 734, 735

75

Type 728, 734, 735

75

W

W

100985_009

100985A Conexant 3-3

3.0 Applications CX28331/CX28332/CX28333

3.1 PCB Design Considerations for CX2833i Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

3-4 Conexant 100985A

A

Appendix A

A.1 Applicable Standards

The applicable standards documents are as follows:

• ANSI T1.102-1993 (DS3 and STS-1 standard)

• ANSI T1.404a-1996 (DS3 metallic interface)

• ITU Recommendation G.703 (DS3 and E3 standard)

• ITU Recommendation G.823 and G.824 (jitter and wander)

• Bellcore GR499, Issue 1, 12/89 (formerly TR-TSY-000499)

(DS3 and STS-1 requirements)

• Bellcore GR253, Issue 2, 12/91 (formerly TA-NWT-000253)
(STS-1 requirements and jitter)

• Bellcore TR-TSY-000191, Issue 1, 5/86 (AIS and LOS)

• ETSI TBR24 and TBR25 (E3 terminal equipment interface)

• ETSI ETS 300 686 and ETS 300 687 (E3 standard)

• AT&T Technical Reference TR54014, May 1992 (Accunet Interface

Specification for DS-3 jitter only)

100985A Conexant A-1

Appendix A CX28331/CX28332/CX28333

A.1 Applicable Standards Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

A-2 Conexant 100985A

B

Appendix B

B.1 Evaluation Module Schematic

100985A Conexant B-1

Appendix B CX28331/CX28332/CX28333

B.1 Evaluation Module Schematic Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure B-1. Recommended Schematic for the CX2833i-1x Device

689

+3_3V

510
4

11
12

3
2713
1

14

SW2

LBO2

PDB2

XOE2

LLOOP2

RLOOP2

TAIS2/TMUXA3

689

+3_3V

510
4

11

3

12
2713
1

14

SW1

LBO1

PDB1

XOE1

LLOOP1

RLOOP1

+3_3V

L17

CC

C11

0.1

TPOS1/TNRZ1

TNEG1/NC1

REFCLK

RLOS1

RCLK1

RPOS1/RNRZ1

RNEG1/RLCV1

REQH1/TMUXDAT

XOE1

LBO1

LLOOP1

RLOOP1

PDB1

TMUXIO2

TMUXIO1

C12

CC

0.1

2

J7

1

3

+5V

+3_3V

C4

CCCC

+3_3V+3_3V

L7

L11 L10

CC

0.01

C1

CC

CC

CC

R3

R1

R2

31.6

31.6

6

5

43

L1

1

T3001

PULSE

2

R4

37.4

5

6

L2

1

2

0.10.1

C5

CC

CC

R5

37.4

6

L3

T3001

PULSE

34

1

REQH2/TMUXA0

TAIS1/TMUXA2

REQH1/TMUXDAT

TCLK1

TAIS1/TMUXA2

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

CC

R13

12.1K

CC

R6

31.6

5

2

34

689
510

+3_3V

4

11

3

12
2713
1

14

SW3

LBO3

PDB3

LLOOP3

RLOOP3

+3_3V

L16

C10

CC

0.1

ENDECDIS

PDB2

RLOOP2

LLOOP2

RNEG2/RLCV2

RPOS2/RNRZ2

RCLK2

RLOS2

60

59

56

58

53

57

52

55

54

51

PDB2

DVDD

RCLK2

RLOS2

LLOOP2

RLOOP2

ENDECDIS

TAIS1/TMUXA2

TCLK1

RNEG2/RLCV2

RPOS2/RNRZ2

TPOS1/TNRZ1

TNEG1/NC1

REFCLK1
RLOS1
RCLK1

RPOS1/RNRZ1
RNEG1/RLCV1

REQH1/TMUXDAT
XOE1
LBO1

DVDD2

LLOOP1
RLOOP1

PDB1

TMUXIO2

TMUXIO1

VGG

RBIAS

L12

+3_3V

31.6

T3001

PULSE

CX28333

SOCKET

RVDD1

RVSS1

TLINE1M

TLINE1P

TVDD1

TVSS1

TVSS2

RLINE1M

RLINE1P

5

8

3

2

4

1

9

7

6

10

N1

CC

C6

C7

0.1

0.1

XOE3

TAIS3/TMUXA4

REQH3/TMUXA1

TCLK2

TAIS2/TMUXA3

TPOS2/TNRZ2

49

50

TCLK2

TPOS2/TNRZ2

TAIS2/TMUXA3

U1

80 ETQFP

TLINE2M

TLINE2P

TVDD2

11

12

CC

L13

TNEG2/NC2

48

TNEG2/NC2

RVDD2

13

+3_3V

+3_3V

REFCLK

REQH2/TMUXA0

47

46

45

REFCLK2

REQH2/TMUXA0

RLINE2M

RLINE2P

16

15

14

L4

SW4

XOE2

LBO2

44

LBO2

XOE2

E3MODE

RVSS2

TLINE3P

TVSS3

18

17

CC

R7

37.4

6

6

1

1

+3_3V

44

32

1

23

1

E3MODE

ENDECDIS

TMUXLAT

E3MODE

412843

42

DVSS

TMUXLAT

TLINE3M

TVDD3

19

20

L14

+3_3V

CC

0.01

C2

R8

5

5

2

2

2 Pin DIP Switch Setting

Pin 2 E3MODE 1=E3 mode is enabled 0=Disabled

Pin 1 ENDECDIS 1=Dual rail pulse coded data format

7

6

8

5

9

4
3

10
21211
1

SW5

REQH2/TMUXA0

DIGITAL GND

TCLK3

TNEG3/NC3

TPOS3/TNRZ3

TAIS3/TMUXA4

TAIS3/TMUXA4

40

TCLK3

39

TPOS3/TNRZ3

38

TNEG3/NC3

37

REFCLK3

36

RLOS3

35

RCLK3

34

RPOS3/RNRZ3

33

RNEG3/RLCV3

32

REQH3/TMUXA1

31

XOE3

30

LBO3

29

DVSS2
LLOOP3

27

RLOOP3

26

PDB3

25

RVSS3

24

RLINE3M

23

RLINE3P

22

RVDD3

21

CC

C8

CC

0.1

L15

+3_3V

CC

CC

37.4

31.6R931.6

43

34

5

6

6

5

L5

T3001

PULSE

1

2

2

1

Seven Position DIP Switch Settings for all Channels

DECODER AND E3 SELECTION

Position 1 PDB POWERDOWN (0=Powerdown 1=Active)

TAIS1/TMUXA2

TAIS2/TMUXA3

TAIS3/TMUXA4

REQH3/TMUXA1

REQH1/TMUXDAT

XOE3

REQH3/TMUXA1

RNEG3/RLCV3

RPOS3/RNRZ3

RCLK3

RLOS3

REFCLK

ANALOG GND

C9

0.1

CC

R10

43

T3001

PULSE

34

Position 2 RLOOP (1=Remote LPBK Enabled 0=Disabled)

Position 3 LLOOP (1=Local Loop Enabled 0=Disabled)

Position 4 LBO (1=TX CABLE less than 250ft 0=greater than 250ft)

Position 5 XOE (1=Transmitter Enabled 0=Disabled)

PDB3

RLOOP3

LLOOP3

LBO3

0.01

CCCCCC

37.4

R11

6

6

L6

1

1

Position 6 TAIS (1=Enable AIS operation 0=disable)

Position 7 REQH(1=Enable Equalization 0=Disable)

C3

37.4

R12

5

5

PULSE

2

34

2

34

TMUXLAT

+3_3V

SW9

REFCLK

CC

1/4

R17

42.2
C13

CC

87
OUT

Y1

GND

SOCKET

CH1_LOS

CR1

CCCCCC

R14

402

J8

J9

RLOS1

CH2_LOS

CR2

12

402

R15

J10

RLOS2

0.1

CH3_LOS

21

CR3

402

R16

RLOS3

+3_3V

14

VCC
NC

1

T3001

CHANNEL 1 TRANSMIT

BNC

CHANNEL 1 RECEIVE

BNC

J1

J2

CHANNEL 2 TRANSMIT

BNC

J3

CHANNEL 2 RECEIVE

BNC

J4

CHANNEL 3 TRANSMIT

BNC

J5

CHANNEL 3 RECEIVE

BNC

J6

100985_017

B-2 Conexant 100985A

CX28331/CX28332/CX28333 Appendix B

Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure B-2. Recommended Schematic for the CX2833i-3x Device (1 of 2)

PD2

RLOOP2

LLOOP2

LBO2

XOE2

TAIS2/TMUXA3

REQH2/TMUXA0

REQH1/TMUXDAT

TAIS 1/TMUXA2

XOE1

LBO1

LLOOP1

RLOOP1

J1 Channel 1 Transmit

PD1

LBO1

LLOOP1

XOE1

TAIS1/TMUXA2

PD1

RLOOP1

REQH1/TMUXDAT

141312111098

SW1

Chn 1

1234567

R23

+3.3V

1k

+3.3V

L16

bead

TNEG1/NC1

TPOS1/TNRZ1

RCLK1

RNEG1/RLCV1

RPOS1/RNRZ1

TCLK1

C11

0.1

L17

bead

+3.3V

TMUXIO1

TMUXIO2

XOE1

LBO1

LLOOP1

RLOOP1

PD1

TMUXIO2

TMUXIO1

1

J7

+5V

C1

0.01

R3

37.4

R4

37.4

31.6

R5

J3 Channel 2 Transmit

R6

52

L3

1 6

1

R1

31.6

R2

31.6

52

L1

1 6

1

52

L2

Pulse

3 4

2

2,3,4

Pulse

J2 Channel 1 Receive

T3001

1 6

3 4

1

2

2,3,4

T3001

RPOS1/RNRZ1

RNEG1/RLCV1

REQH1/TMUXDAT

C12

31.6

Pulse

T3001

3 4

2

2,3,4

RCLK1

0.1

TAIS1/TMUXA2

TCLK1

TAIS1

TNEG1/NC1

TPOS1/TNRZ1

76

TCLK1

77

TLOS1

78
79

REFCLK

RLOS1

+3.3V

+3.3V

+3.3V

TLOS1

80
81
82

RCLK1

83
84
85

N/C8

86

N/C9

87

N/C10

88
89

XOE1

90

LBO1

91
92
93
94

PD1

95

GPD

96
97

VGG

98

RBAIS

99

TVSS1

100

12.1K

R13

bead

L10

bead

+3.3V +3.3V

L11

L12

bead

C6

L13

C7

bead

C2

R7

37.4

L4

1 6

1

J4 Channel 2 Receive

ENDECDIS

C10

0.1

DVDDC

ENDECDIS

TPOS1/TNRZ1

TNEG1/NC1

REFCLK1

RLOS1

RPOS1/RNRZ1
RNEG1/RLCV1

REQH1

DVDDIO
LLOOP1
RLOOP1

RESET

TMON1P

TLINE1P

123456789

R52 0

C4

C5

0.1

0.1

0.01

R8

37.4

52

Pulse

3 4

2

2,3,4

PD2

T3001

RLOOP2

PD2

RLOOP2

TLINE1M

TMON1M

0

0.1

0.1

+3.3V

RNEG2/RLCV2

RPOS2/RNRZ2

LLOOP2

RNEG2/RLCV2

RPOS2/RNRZ2

LLOOP2

RNEG2/RLCV2

RPOS2/RNRZ2

TVDD1

RVDD1

RLINE1P

R53

J5 Channel 3 Transmit

PD2

RLOOP2

LLOOP2

LBO2

XOE2

TAIS 2/TMUXA3

REQH2/TMUXA0

141312111098

SW2

Chn 2

1234567

R22

1k

RCLK2

TCLK2

TPOS2/TNRZ2

TNEG2/NC2

RCLK2

RLOS2

TAIS2/TMUXA3

TLOS2

TCLK2

TPOS2/TNRZ2

TNEG2/NC2

N/C5

N/C6

N/C7

TAIS2

TCLK2

TLOS2

RCLK2

RLOS2

TNEG2/NC2

TPOS2/TNRZ2

U1

CX28333 DS3/E3/STS-1 LIU

RLINE1M

RVSS1

TVSS2

TMON2P

TLINE2P

TLINE2M

TMON2M

TVDD2

RVDD2

RLINE2P

101112131415161718192021222324

0

R18 0

R19

31.6

R9

31.6

R10

52

L5

Pulse

T3001

1 6

3 4

1

2

2,3,4

+3.3V

REFCLK

REQH2/TMUXA0

REFCLK2

RLINE2M

XOE2

REQH2

RVSS2

J21

1

LBO2

XOE2

TVSS3

R20 0

LBO2

TMON3P

TMUXLAT

E3MODE

TMUXLAT

NC11

E3MODE

TMONTST

TLINE3P

TLINE3M

TMON3M

R21 0

51525354555657585960616263646566676869707172737475

DVSSC

N/C4

50

TAIS3

49

TCLK3

48

TPOS3/TNRZ3

47

TNEG3/NC3

46

TLOS3

45

REFCLK3

44

RLOS3

43

RCLK3

42

RPOS3/RNRZ3

41

RNEG3/RLCV3

40

N/C3

39

N/C2

38

N/C1

37

REQH3

36

XOE3

35

LBO3

34

DVSSIO

33

LLOOP3

32

RLOOP3

31

PD3

30

RVSS3

29

RLINE3M

28

RLINE3P

27

RVDD3

26

TVDD3

25

0.1

0.1
C9

C8

bead

L14

+3.3V

+3.3V

L15

R24

1k

TCLK3

TPOS3/TNRZ3

TCLK3

TAIS3/TMUXA4

TPOS3/TNRZ3

bead

+3.3V

J6 Channel 3 Receive

4

3

1

2

E3MODE

ENDECDIS

E3MODE

TNEG3/NC3

TNEG3/NC3

TLOS3

REFCLK

C3

37.4

R11

L6

1 6

1

SW4

RCLK3

RPOS3/RNRZ3

RNEG3/RLCV3

RLOS3

RCLK3

RPOS3/RNRZ3

RNEG3/RLCV3

0.01

37.4

R12

52

T3001

Pulse

3 4

2

2,3,4

REQH3/TMUXA1

XOE3

B.1 Evaluation Module Schematic

REQH1/TMUXDAT

TAIS 3/TMUXA4

REQH2/TMUXA0

REQH3/TMUXA1

TAIS 1/TMUXA2

TAIS 2/TMUXA3

12111098

+3.3V

Chn 3

+3.3V

LBO3

LLOOP3

RLOOP3

PD3

12345

R36

1k

RLOOP3

LLOOP3

LBO3

PD3

LLOOP3

LBO3

PD3

RLOOP3

141312111098

1234567

R25

1k

7

SW7

6

XOE3

TAIS3/TMUXA4

REQH3/TMUXA1

REQH3/TMUXA1

TAIS3/TMUXA4

XOE3

SW3

CH1_TLOS

CH2_TLOS

CR60

CR61

402

R60

R61

JP9

JP10

1 2

1 2

TLOS1

TLOS2

CH1_RLOS

CH2_RLOS

CR1

CR2

402

R14

R15

JP6

JP7

1 2

1 2

RLOS1

RLOS2

CR62

402

R62

JP11

CR3

402

R16

JP8

CH3_TLOS

Red Led

402

1 2

TLOS3

CH3_RLOS

Red Led

402

1 2

RLOS3

+3.3V

Conexant Systems

9868 Scranton Road

SW9

TMUXLAT

SW10

C13

Note: All capacitors are in Microfarads

San Diego,Ca 92121

1 4

1 4

TMUXIO1

.1

Socket

Y1

CX 28333 (LIU) w/Jitter Attenuator Circuit

Title

+3.3V

2 3

+3.3V

2 3

REFCLK

REFCLK

R17

141

Vcc

7 8

Gnd Out

NC

Notes: Seven Position Dip switch for all Channels (SW1,2,3)

Position 2 RLOOP# ( 0 = RLPBK Disable 1 = RLPBK Enable)

Position 3 LLOOP# ( 0 = LPBK Disable 1 = LPBK Enable)

Position 4 LBO# ( 0 = Tx Cable > 250ft 1 = Tx Cable < 250ft)

Position 1 PDB# ( 0 = Powerdown 1 = Active)

A

of

12

BT01-D630-

C

Size Document Number Rev

Date: Sheet

Reset Device

42.2

44.736/34.368/51.256Mhz +/- 20ppm

Position 7 REQH# ( 0 =EQ Disable 1 = EQ Enable)

Position 5 XOE# ( 0 = Tx Disable 1 = Tx Enable)

Position 6 TAIS# ( 0 =Tx AIS Disable 1 = Tx AIS Enable)

100985_010

100985A Conexant B-3

Appendix B CX28331/CX28332/CX28333

B.1 Evaluation Module Schematic Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit

Figure B-3. Recommended Schematic for the CX2833i-3x Device (2 of 2)

A

of

TCLK1

RCLK1

RPOS1/RNRZ1

TNEG1/NC1

TPOS1/TNRZ1

RNEG1/RLCV1

TCLK2

RCLK2

TPOS2/TNRZ2

RPOS2/RNRZ2

TNEG2/NC2

RNEG2/RLCV2

TCLK3

RCLK3

TPOS3/TNRZ3

RPOS3/RNRZ3

TNEG3/NC3

RNEG3/RLCV3

REFCLK

22

TCLK1

RCLK1

TPOS1/TNRZ1

RPOS1/RNRZ1

123456789

JP3

DJATCLK1

DJATPOS1

123456789

JP2

123456789

JP1

TCLK2

RCLK2

TPOS2/TNRZ2

RPOS2/RNRZ2

TNEG2/NC2

TNEG1/NC1

RNEG1/RLCV1

101112131415161718192021222324

DJATCLK2

DJATPOS2

DJATNEG1

DJATNEG2

101112131415161718192021222324

101112131415161718192021222324

TCLK3

RCLK3

RNEG2/RLCV2

DJATCLK3

TPOS3/TNRZ3

RPOS3/RNRZ3

TNEG3/NC3

DJATPOS3

DJATNEG3

+3.3V

REFCLK

RNEG3/RLCV3

J14

8

101214161820222426

TAIS 2/TMUXA3

TAIS 3/TMUXA4

TAIS 1/TMUXA2

REQH1/TMUXDAT

REQH3/TMUXA1

TAIS3/TMUXA4

TAIS2/TMUXA3

TAIS1/TMUXA2

REQH3/TMUXA1

REQH2/TMUXA0

TMUXIO2

XOE1

RLOOP2

XOE2

RLOOP3

XOE3

E3MODE

TMUXIO2

J15

1

330

R28

C15

0.1

+3.3V

RLOOP1

E3MODE

XOE1

246

28

J13

27

135791113151719212325272931333537

PD1

LBO1

LLOOP1

PD1 RLOOP1

LBO1

REQH1/TMUXDAT

LLOOP1

REQH2/TMUXA0

TMUXLAT

RLOOP2

XOE2

RLOOP3

XOE3

REQH2/TMUXA0

TMUXLAT

8

10121416182022242628303234363840424446485052545658

PD2

LBO2

PD3

LLOOP2

LLOOP3

TAIS 2/TMUXA3

TAIS 1/TMUXA2

PD2

LBO2

PD3

LLOOP2

TAIS 1/TMUXA2

TAIS 2/TMUXA3

39

414345474951535557

LBO3

REQH3/TMUXA1

REQH1/TMUXDAT

TAIS 3/TMUXA4

LBO3

LLOOP3

TAIS3/TMUXA4

REQH3/TMUXA1

REQH1/TMUXDAT

60

59

CHANNEL3_STATUS

CHANNEL1_STATUS

CHANNEL2_STATUS

J22

Red - Banana - Jack

J24

Blue Banana - Jack

+5VSRC

12

Optional external 3.3V Supply

JP5

C23

0.1

+3.3V

10

25V

+

Please remove JP3 when in

use

C22

JP4

1 2

used for heat sink

1 square inch copper plane

U2

LT1086-3.3

GND

VIN VOUT

1

3 2

+5V

C21

220

330

R40

0.1

C20

CR13

Green Led

Conexant Systems

J23

Black- Banana - Jack

9868 Scranton Road

San Diego,Ca 92121

CX 28333 (LIU) w/Jitter Attenuator Evualation Module

BT01-D630-

C

Title

Size Document Number Rev

Date: Sheet

TMUXIO1

Header

Header

Header

TMUXIO1

1

330

R27

C14

+3.3V

246

J12

135791113151719212325

TMUXLAT

TMUXLAT

0.1

REQH2/TMUXA0

25

25

25

J2012345678

910

TDI

TCK

TMS

TDO

109
110
111
112
113

RNEG3/RLCV3

DJATCLK1

DJATCLK3

RNEG2/RLCV2

RNEG1/RLCV1

114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

VCO2

D14

C26

10

DIODE

+3.3V

RCLK3

1Meg

R26

DJATCLK2

RCLK1

RCLK2

NC/74
NC/75
NC/76
NC/77
NC/78
VCO2

VCCIO_6
NC/79
NC/80
NC/81
NC/82
NC/83
NC/84
NC/85

VCCI_3

GND_11

RCLK3

GND_12

RSTN

GND_13
GND_14

VCCI_4

DJATCK2

RNEG3
RCLK1

DJATCK1

GND_15

RCLK2

DJATCK3
NC/86
NC/87
NC/88

RNEG2

NC/89

RNEG1

VCCIO_7

TDO

108

107

106

105

104

103

TDO

NC/73

NC/72

NC/71

NC/70

GND_10

RPOS3

RPOS2

GND_1

TDI

NC/1

NC/2

123456789

TDI

RPOS3/RNRZ3

RPOS2/RNRZ2

102

NC/69

NC/3

VCO1

TCK

CHANNEL1_STATUS

101

1009998979695949392919089888786858483828180797877767574

NC/68

NC/67

NC/4

NC/5

101112131415161718192021222324252627282930313233343536

RPOS1/RNRZ1

NC/66

RPOS1

NC/65

NC/64

NC/6

DJATNEG2

DJATNEG2

NC/63

U3

GND_2

VCCIO_5

NC/7

NC/62

NC/61

DJATNEG3

DJATPOS2

DJATNEG3

DJATPOS2

VCO1

STATUS1

144 Pin - TQFP

GND_3

STATUS3

CHANNEL3_STATUS

DJATPOS3

TCK

NC/60

NC/59

ConexantConexant

DJATPOS3

TMS

NC/8

TMS

NC/58

NC/57

NC/9

NC/10

NC/56

NC/55

GND_9

JitterJitter

AttenuatorAttenuator

VCCIO_1

DJATNEG1

DJATPOS1

DJATNEG1

DJATPOS1

NC/54

STATUS2

CHANNEL2_STATUS

NC/53

NC/52

NC/51

NC/50

NC/11

NC/12

NC/13

NC/14

NC/49

NC/15

NC/48

VCCIO_4

GND_4

NC/16

73

NC/47

NC/17

VCCIO_3

NC/18

NC/46
NC/45
NC/44
NC/43
NC/42
NC/41
NC/40
NC/39
GND_8
NC/38
NC/37
NC/36
NC/35
GND_7
VCCI_2
GND_6
NC/34
NC/33
VCO3
NC/32
GND_5
VCCI_1
VCCIO_2
NC/31
NC/30
NC/29
NC/28
NC/27
NC/26
NC/25
NC/24
NC/23
NC/22
NC/21
NC/20
NC/19

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

+3.3V

Y2

VCO3

C16

R32

C28

.1

1Meg

DJATCLK1

7 8

C17

R33

+3.3V

VCO DIJITCK1

0.1

1Meg

VCO1_CNTRL

.1

141

Y3

VCO2_CNTRL

0.1

C18

R34

VCO2

C27

141

VCO1_CNTRL

0.1

VCO1

1Meg

DJATCLK2

7 8

0.1

C19

R35

VCO2_CNTRL

VCO DIJITCK2

1Meg

C29

.1

+3.3V

DJATCLK3

141

Y4

VCO DIJITCK3

7 8

VCO3_CNTRL

0.1

C25

R38

0.1
1Meg

C24

R37

1Meg

VCO3_CNTRL

VCO3

100985_011

B-4 Conexant 100985A

0.0

Sales

Offi

ces

Further Information:

[e-mail]
1-800-854-8099 (North America)
33-14-906-3980 (International)

Web Site

www.conexant.com

World Headquarters

Conexant Systems, Inc.
4311 Jamboree Road,
P.O. Box C
Newport Beach, CA 92658-8902
Phone: [phone]
Fax: [phone]

U.S. Florida/So uth Ameri ca

Phone: [phone]
Fax: [phone]

U.S. Los Angeles

Phone: [phone]
Fax: [phone]

U.S. Mid-Atlantic

Phone: [phone]
Fax: [phone]

U.S. North Central

Phone: [phone]
Fax: [phone]

U.S. Northeast

Phone: [phone]
Fax: [phone]

U.S. Northwest/Pacific West

Phone: [phone]
Fax: [phone]

U.S. South Central

Phone: [phone]
Fax: [phone]

U.S. Southeast

Phone: [phone]
Fax: [phone]

U.S. Southwest

Phone: [phone]
Fax: [phone]

APAC Headquarters

Conexant Systems Singapore,
Pte. Ltd.
1 Kim Seng Promenade
Great World City
#09-01 East Tower
Singapore 237994
Phone: [phone]
Fax: [phone]

Australia

Phone: [phone]
Fax: [phone]

Hong Kong

Phone: [phone]
Fax: [phone]

India

Phone: [phone]
Fax: [phone]

Korea

Phone: [phone]
Fax: [phone]

Europe Headquarters

Conexant Systems France
Les Taissounieres B1
1681 Route des Dolines
BP 283
06905 Sophia Antipolis Cedex
France
Phone: [phone]
Fax: [phone]

Europe Central

Phone: [phone]
Fax: [phone]

Europe Mediterranean

Phone: [phone]
Fax: [phone]

Europe North

Phone: [phone]
Fax: [phone]

Europe South

Phone: [phone]
Fax: [phone]

Middle East Headquarters

Conexant Systems
Commercial (Israel) Ltd.
P.O. Box 12660
Herzlia 46733, Israel
Phone: [phone]
Fax: [phone]

Japan Headquarters

Conexant Systems Japan Co., Ltd.
Shimomoto Building
1-46-3 Hatsudai,
Shibuya-ku, Tokyo
151-0061 Japan
Phone: [phone]
Fax: [phone]

Taiwan Headquar ters

Conexant Systems, Taiwan Co., Ltd.
Room 2808
International Trade Building
333 Keelung Road, Section 1
Taipei 110, Taiwan, ROC
Phone: [phone]
Fax: [phone]

China

Phone: [phone]
Fax: [phone]