Datasheet CA3160T, CA3160E, CA3160AE Datasheet (Harris Semiconductor)

Semiconductor

CA3160, CA3160A

September 1998 File Number 976.3

4MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output

The CA3160A and CA3160 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip.TheCA3160seriesare
frequency compensated versions of the popular CA3130
series.

Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common-mode input voltage capability
down to 0.5V below the negative supply terminal, an
important attribute in single supply applications.

A complementary symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.

The CA3160 Series circuits operate at supply voltages
ranging from 5V to 16V, or ±2.5V to ±8V when using split
supplies, and have terminals for adjustment of offset voltage
for applications requiring offset null capability. Terminal
provisions are also made to permit strobing of the output
stage.

The CA3160A offers superior input characteristics over
those of the CA3160.

Ordering Information

TEMP.

PART NUMBER

CA3160AE -55 to 125 8 Ld PDIP E8.3
CA3160E -55 to 125 8 Ld PDIP E8.3
CA3160T -55 to 125 8 Pin Metal Can T8.C

RANGE (oC) PACKAGE

PKG.

NO.

Features

• MOSFET Input Stage Provides:

- Very High Z

- Very Low I

= 1.5TΩ (1.5 x 1012Ω) (Typ)

I

. . . . . . . . . . . . . 5pA (Typ) at 15V Operation

I

. . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation

• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be Swung

0.5V Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either (or
Both) Supply Rails

Applications

• Ground Referenced Single Supply Amplifiers

• Fast Sample Hold Amplifiers

• Long Duration Timers/Monostables

• High Input Impedance Wideband Amplifiers

• Voltage Followers (e.g., Follower for Single Supply
D/A Converter)

• Wien-Bridge Oscillators

• Voltage Controlled Oscillators

• Photo Diode Sensor Amplifiers

Pinouts

CA3160

(METAL CAN)

TOP VIEW

COMPENSATION

OFFSET

NULL

INV.

INPUT

NON-INV.

INPUT

1

2

3

CA3160

TOP VIEW

TAB

8

-

+

4
V- AND CASE

(PDIP)

STROBESUPPLEMENTARY

7

5

V+

OUTPUT

6

OFFSET
NULL

OFFSET NULL

NON-INV.

NOTE: CA3160 Series devices have an on-chip frequency
compensation network. Supplementary phase compensation or
frequency roll-off (if desired) can be connected externally between
Terminals 1 and 8.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

INV.

INPUT

INPUT

1
2

-

+

3

V-

4

8

STROBE

7

V+

6

OUTPUT

5

OFFSET NULL

© Harris Corporation 1998

Copyright

CA3160, CA3160A

Absolute Maximum Ratings Thermal Information

Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . +16V

Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .8V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)

Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Output Short Circuit Duration (Note 2). . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

2. Short Circuit may be applied to ground or to either supply.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . 110 N/A

Metal Can Package . . . . . . . . . . . . . . . 170 85

Maximum Junction Temperature (Metal Can). . . . . . . . . . . . . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

Electrical Specifications T

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage |VIO|VS = ±7.5V - 6 15 - 2 5 mV
Input Offset Current |IIO|VS = ±7.5V - 0.5 30 - 0.5 20 pA
Input Current I
Large-Signal Voltage Gain A

Common-Mode Rejection Ratio CMRR 70 90 - 80 95 - dB
Common-Mode Input-Voltage Range V
Power-Supply Rejection Ratio PSRR ∆VIO/∆VS, VS = ±7.5V - 32 320 - 32 150 µV/V
Maximum Output Voltage VOM+RL = 2kΩ 12 13.3 - 12 13.3 - V

Maximum Output Current IOM+VO = 0V (Source) 12 22 45 12 22 45 mA

Supply Current (Note 3) I+ VO = 7.5V, R L = ∞ - 10 15 - 10 15 mA

Input Offset Voltage Temperature Drift ∆VIO/∆T-8--6-µV/oC

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

A

CA3160 CA3160A

VS = ±7.5V - 5 50 - 5 30 pA

I

VO = 10V

OL

lCR

VOM- - 0.002 0.01 - 0.002 0.01 V
VOM+RL = ∞ 14.99 15 - 14.99 15 - V
VOM- - 0 0.01 - 0 0.01 V

IOM-VO = 15V (Sink) 12 20 45 12 20 45 mA

VO = 0V, R L = ∞ -23-23mA

, RL = 2kΩ 50 320 - 50 320 - kV/V

P-P

94 110 - 94 110 - dB

0 -0.5 to 12 10 0 -0.5 to 12 10 V

UNITSMIN TYP MAX MIN TYP MAX

Electrical Specifications For Design Guidance, V

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or

Input Resistance R
Input Capacitance C
Equivalent Input Noise Voltage e

Equivalent Input Noise Voltage e

= ±7.5V, TA = 25oC, Unless Otherwise Specified

SUPPLY

Terminals 4 and 1

I

f = 1MHz 4.3 4.3 pF

I

BW = 0.2MHz RS = 1MΩ 40 40 µV

N

RS = 10MΩ 50 50 µV

RS = 100Ω 1kHz 72 72 nV/√Hz

N

10kHz 30 30 nV/√Hz

2

CA3160 CA3160A

UNITSTYP TYP

±22 ±22 mV

1.5 1.5 TΩ

CA3160, CA3160A

Electrical Specifications For Design Guidance, V

= ±7.5V, TA = 25oC, Unless Otherwise Specified (Continued)

SUPPLY

CA3160 CA3160A

PARAMETER SYMBOL TEST CONDITIONS

Unity Gain Crossover Frequency f

T

4 4 MHz

UNITSTYP TYP

Slew Rate SR 10 10 V/µs
Transient Response Rise and Fall Time t

CL = 25pF, RL = 2kΩ, (Voltage Follower) 0.09 0.09 µs

r

Overshoot OS 10 10 %

Settling Time t

Electrical Specifications For Design Guidance, V+ = +5V, V- = 0V, T

CL= 25pF, RL=2kΩ, (Voltage F ollow er)

S

To <0.1%, VIN = 4V

A

P-P

= 25oC, Unless Otherwise Specified

1.8 1.8 µs

CA3160 CA3160A

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage V
Input Offset Current I
Input Current I

IO

IO

l

62mV

0.1 0.1 pA
22pA

UNITSTYP TYP

Common-Mode Rejection Ratio CMRR 80 90 dB
Large Signal Voltage Gain A

OL

VO = 4V

, RL = 5kΩ 100 100 kV/V

P-P

100 100 dB

Common-Mode Input Voltage Range V

lCR

0 to 2.8 0 to 2.8 V

Supply Current I+ VO = 5V, RL = ∞ 300 300 µA

VO = 2.5V, RL = ∞ 500 500 µA

Power Supply Rejection Ratio PSRR ∆VIO/∆V+ 200 200 µV/V

NOTE:

3. ICC typically increases by 1.5mA/MHz during operation.

Block Diagram

+

3

INPUT

2

-

OFFSET

NULL

200µA 1.35mA 200µA

BIAS CKT.

A

≈

A

≈5X

V

COMPENSATION

(WHEN DESIRED)

V

6000X

C

C

7

8mA
(NOTE 4)

0mA
(NOTE 5)

V+

NOTES:

4. Totalsupply voltage (for indicated voltage
gains) = 15V with input terminals biased so
that Terminal 6 potential is +7.5V above
Terminal 4.

5. Total supply voltage (for indicated voltage
gains) = 15V with output terminal driven to
either supply rail.

OUTPUT

A

≈30X

V

815

STROBE

6

V-

4

3

Schematic Diagram

BIAS CURRENT “CURRENT SOURCE

CA3160, CA3160A

CURRENT SOURCE

FOR Q

AND Q

6

7

LOAD” FOR Q

V+

7

11

Q

Z

1

8.3V

R

1

40kΩ

R

5kΩ

NON-INV.

INPUT

INV. INPUT

2kΩ

30
pF

Q

Q

3

Q

5

OUTPUT
STAGE

11

Q

Q

12

STROBING

8

OUTPUT

6

4815

Q

1

D

1

D

2

D

3

D

4

2

INPUT STAGE

D

5

3

+

2

-

R

1kΩ

1kΩ

2

Q

4

Q

6

3

Q

9

R

5

OFFSET NULL

SECOND
STAGE

7

SUPPLEMENTARY
COMP IF DESIRED

Q

R

4

1kΩ

10

R
1kΩ

D

6

D

6

Q

7

NOTE: Diodes D5 Through D7 Provide Gate Oxide Protection For MOSFET Input Stage.

Application Information

Circuit Description

Refer to the Block Diagram of the CA3160 series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3160 series circuits are
ideal for single supply operation. Three class A amplifier
stages, having the individual gain capability and current
consumption shown in the Block Diagram provide the total
gain of the CA3160. A biasing circuit provides two potentials
for common use in the first and second stages. Terminals 8
and 1 can be used to supplement the internal phase
compensation network if additional phase compensation or
frequency roll-off is desired. Terminals 8 and 4 can also be
used to strobe the output stage into a low quiescent current
state. When Terminal 8 is tied to the negative supply rail
(Terminal 4) by mechanical or electrical means, the output
potential at Terminal 6 essentially rises to the positive supply­rail potential at Terminal 7. This condition of essentially zero
current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load

resistance presented to the amplifier is very high (e.g., when
the amplifier output is used to drive MOS digital circuits in
comparator applications).

Input Stage - The circuit of the CA3160 is shown in the
Schematic Diagram. It consists of a differential-input stage
using PMOS field-effect transistors (Q
mirror-pair of bipolar transistors (Q
resistors together with resistors R

, Q7) working into a

6

) functioning as load

9,Q10

through R6. The mirror-

3

pair transistors also function as a differential-to-single-ended
converter to provide base drive to the second-stage bipolar
transistor (Q

). Offset nulling, when desired, can be effected

11

by connecting a 100,000Ω potentiometer across Terminals 1
and 5 and the potentiometer slider arm to Terminal 4.
Cascode-connected PMOS transistors Q

, Q4, are the

2

constant-current source for the input stage. The biasing circuit
for the constant-current source is subsequently described.
The small diodes D

through D7provide gate-oxide protection

5

against high-voltage transients, including static electricity
during handling for Q

and Q7.

6

Second-Stage - Most of the voltage gain in the CA3160 is
provided by the second amplifier stage, consisting of bipolar

4

CA3160, CA3160A

transistor Q11 and its cascode-connected load resistance
provided by PMOS transistors Q

and Q5. The source of bias

3

potentials for these PMOS transistors is described later. Miller
Effectcompensation (roll off) is accomplished bymeans of the
30pF capacitor and 2kΩ resistor connected between the base
and collector of transistor Q

. These internal components

11

provide sufficient compensation for unity gain operation in
most applications. However, additional compensation, if
desired, may be used between Terminals 1 and 8.

Bias-Source Circuit - At total supply voltages , some what
above8.3V, resistor R

and zener diode Z1serve to establish a

2

voltage of 8.3V across the series-connected circuit, consisting
of resistor R
A tap at the junction of resistor R
gate-bias potential of about 4.5V for PMOS transistors Q
Q

with respect to Terminal 7. A potential of about 2.2V is

5

developed across diode-connected PMOS transistor Q

, diodes D1through D4, and PMOS transistor Q1.

1

and diode D4 provides a

1

with

1

4

and

respect to Terminal 7 to provide gate bias for PMOS transistors
Q

and Q3. It should be noted that Q1 is “mirror-connected” to

2

both Q
be identical, the approximately 200µA current in Q
a similar current in Q

and Q3. Since transistors Q1, Q2, Q3 are designed to

2

and Q3 as constant-current sources for

2

establishes

1

both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V,zener diode

Z

becomes nonconductive and the potential, dev eloped

1

across series-connected R

, D1 - D4, and Q1, varies directly

1

with variations in supply voltage. Consequently, the gate bias
for Q

, Q5 and Q2, Q3 varies in accordance with supply-

4

voltage variations. This variation results in deterioration of the
power-supply-rejection ratio (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about

4.5V results in seriously degraded performance.
Output Stage - The output stage consists of a drain-loaded

inverting amplifier using CMOS transistors operating in the
Class A mode. When operating into very high resistance loads,
the output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier,its gain is
dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 17. Typical op amp
loads are readily driven by the output stage. Because large­signal excursions are non-linear , requiring feedbac k for good
wavef orm reproduction, transient dela ys may be encountered.
As a voltage follower,the amplifier can achieve0.01% accuracy
levels, including the negativ e supply r ail.

Offset Nulling

Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer's total range.

Input Current Variation with Common Mode Input
Voltage

As shown in the Electrical Specifications, the input current for
the CA3160 Series Op Amps is typically 5pA at T

= 25oC

A

when Terminals 2 and 3 are at a common-mode potential of
+7.5V with respect to negative supply Terminal 4. Figure 23
contains data showing the variation of input current as a
function of common-mode input voltage at T

=25oC. These

A

data show that circuit designers can advantageously exploit
these characteristics to design circuits which typically require
an input current of less than 1pA, provided the common-mode
input voltage does not exceed 2V. As previously noted, the
input current is essentially the result of the leakage current
through the gate-protection diodes in the input circuit and,
therefore, a function of the applied voltage . Although the finite
resistance of the glass terminal-to-case insulator of the metal
can package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate­protection network functions as if it is connected to Terminal 4
potential, and the metal can case of the CA3160 is also
internally tied to T erminal 4, input Terminal 3 is essentially
“guarded” from spurious leakage currents.

Input-Current Variation with Temperature

The input current of the CA3160 Series circuits is typically 5pA

o

at 25

C. The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor junction device,including op
amps with a junction-FET input stage, the leakage current
approximately doubles for every 10

o

C increase in temperature.
Figure 24 provides data on the typical variation of input bias
current as a function of temperature in the CA3160.

In applications requiring the lowest practical input current and
incremental increases in current because of “warm-up” effects,
it is suggested that an appropriate heat sink be used with the
CA3160. In addition, when “sinking” or “sourcing” significant
output current the chip temperature increases, causing an
increase in the input current. In such cases, heat-sinking can
also very markedly reduce and stabilize input current variations.

Input Offset Voltage (VIO) Variation with DC Bias
vs Device Operating Life

It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magnitude
of the change is increased at high temperatures. Users of the
CA3160 should be alert to the possible impacts of this effect if
the application of the device involves extended operation at
high temperatures with a significant differential DC bias voltage
applied across Terminals 2 and 3. Figure 25 shows typical data
pertinent to shifts in offset voltage encountered with CA3160
devices in metal can packages during life testing. At lo wer
temperatures (metal can and plastic) for example at 85
change in voltage is considerably less. In typical linear
applications where the differential voltage is small and
symmetrical, these incremental changes are of about the same

o

C, this

5

CA3160, CA3160A

magnitude as those encountered in an operational amplifier
employing a bipolar transistor input stage. The 2V diff erential
voltage example represents conditions when the amplifier
output state is “toggled”, e.g., as in comparator applications.

Power Supply Considerations

Because the CA3160 is very useful in single supply
applications, it is pertinent to review some considerations
relating to power supply current consumption under both
single and dual supply service. Figures 1A and 1B show the
CA3160 connected for both dual and single supply operation.

Dual-supply operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q
increasingly positive with respect to ground, current flow
through Q

(from the negative supply) to the load is

12

increased and current flow through Q
supply) decreases correspondingly.When the gate terminals
of Q

and Q12 are driven increasingly negative with respect

8

to ground, current flow through Q
flow through Q

is decreased accordingly.

12

Single supply operation: Initially, let it be assumed that the
value of R

is very high (or disconnected), and that the input-

L

terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage-drops
across Q

and Q12are of equal magnitude. Figure 18 shows

8

typical quiescent supply-current vs supply voltage for the
CA3160 operated under these conditions.

Since the output stage is operating as a Class A amplifier, the
supply current will remain constant under dynamic operating
conditions as long as the transistors are operated in the linear
portion of their voltage-transfer characteristics (see Figure 17).
If either Q

or Q12 are swung out of their linear regions toward

8

cutoff (a non-linear region), there will be a corresponding
reduction in supply-current. In the extreme case, e.g., with
Terminal 8 swung down to ground potential (or tied to ground),
NMOS transistor Q

is completely cut off and the supply

12

current to series connected transistors Q
essentially to zero. The two preceding stages in the CA3160,
howev er, continue to draw modest supply-current (see the
lower curve in Figure 18) ev en though the output stage is
strobed off. Figure 1A shows a dual-supply arrangement for the
output stage that can also be strobed off, assuming R
pulling the potential of Terminal 8 down to that of Terminal 4.

Let it now-be assumed that a load resistance of nominal value
(e.g., 2kΩ) is connected between Terminal 6 and ground in the
circuit of Figure 1B. Let it further be assumed again that the
input-terminal bias (T erminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q
must now supply quiescent current to both RL and transistor
Q

, it should be apparent that under these conditions the

12

supply current must increase as an inverse function of the R
magnitude. Figure 20 shows the voltage-drop across PMOS
transistor Q

as a function of load current at several supply

8

and Q12 are driven

8

(from the positive

8

is increased and current

8

, Q12 goes

8

= ∞, by

L

8

L

voltages.Figure 17 shows the voltagetransfercharacteristics of
the output stage for sev eral values of load resistance.

Wideband Noise

Fromthe standpoint of low-noise performance considerations,
the use of the CA3160 is most advantageous in applications
where in the source resistance of the input signal is on the
order of 1MΩ or more. In this case, the total input-referred
noise voltage is typically only 40µV when the test circuit
amplifier of Figure 2 is operated at a total supply voltage of
15V. This value of total input-referred noise remains
essentially constant, even though the v alue of source
resistance is raised by an order of magnitude. This
characteristic is due to the fact that reactance of the input
capacitance becomes a significant factor in shunting the
source resistance. It should be noted, however, that for values
of source resistance very much greater than 1MΩ, the total
noise voltage generated can be dominated by the thermal
noise contributions of both the feedback and source resistors.

7

3

2

FIGURE 1A. DUAL POWER SUPPLY OPERATION

3

2

FIGURE 1B. SINGLE POWER SUPPLY OPERATION

FIGURE 1. CA3160 OUTPUT STAGE IN DUAL AND SINGLE

+

CA3160

-

8

+

CA3160

-

8

POWER SUPPLY OPERATION

V+

Q

8

OUTPUT

Q

STAGE

12

4

NEGATIVE

V-

SUPPLY

V+

7

Q

8

OUTPUT

Q

STAGE

12

4

6

R

L

6

R

L

6

CA3160, CA3160A

+7.5V

BW (3dB) = 200kHz
TOTAL NOISE VOLTAGE
(INPUT REFERRED = 40µV (TYP)

FIGURE 2. TESTCIRCUIT AMPLIFIER (30dB GAIN) USED FOR

Typical Performance Curves

BW (-3dB) = 4MHz
SR = 10V/µs

R

1MΩ

S

3

2

+

CA3160

-

7

4

-7.5V

0.01

µF

6

WIDEBAND NOISE MEASUREMENTS

+7.5V

+

CA3160

-

2kΩ

0.1µF

7

4

-7.5V

0.01

µF

6

10kΩ

3

2

0.01µF

0.01µF

NOISE
VOLTAGE
OUTPUT

30.1kΩ

1kΩ

2kΩ

25pF
SIMULATED
LOAD
CAPACITANCE

FIGURE 3A.

Top Trace: Output

Bottom Trace: Input

Top Trace: Output Signal

Center Trace: Difference Signal 5mV/Div.

Bottom Trace: Input Signal

FIGURE 3B. SMALL SIGNAL RESPONSE FIGURE 3C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING

SETTLING TIME

FIGURE 3. DUAL SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS

7

CA3160, CA3160A

Typical Applications

V olta ge Followers

Operational amplifiers with very high input resistances, like
the CA3160, are particularly suited to service as voltage
followers. Figure 3 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the CA3160
in a split-supply configuration.

A voltage follow er, operated from a single supply, is sho wn in
Figure 4 together with related waveforms.This follower circuit
is linear over a wide dynamic range, as illustr ated by the
reproduction of the output waveform in Figure 4B with input­signal ramping. The waveforms in Figure 4C show that the
follower does not lose its input-to-output phase-sense, even
though the input is being swung 7.5V below ground potential.
This unique characteristic is an important attribute in both
operational amplifier and comparator applications. Figure 4C
also shows the manner in which the COS/MOS output stage
permits the output signal to swing down to the negative
supply-rail potential (i.e., ground in the case shown). The
digital-to-analog converter (DAC) circuit, described in the
followingsection, illustrates the practical use of the CA3160 in
a single supply voltage follow er application.

9-Bit CMOS DA C

A typical circuit of a 9-bit Digital-to-Analog Converter (DAC) (see
Note6) is shown in Figure 5. This system combines the concepts
of multiple-switch CMOS lCs, a low-cost ladder netw ork of
discrete metal-oxide-film resistors, a CA3160 op amp connected
as a follower,and an inexpensivemonolithic regulator in a simple
single power-supply arrangement. An additional feature of the
DAC is that it is readily interf aced with CMOS input logic , e.g.,
10V logic levels are used in the circuit of Figure 5.

The circuit uses an R/2R voltage-ladder network, with the output­potential obtained directly by terminating the ladder arms at
either the positive or the negative pow er supply terminal. Each
CD4007A contains three inverters,each inverter functioning as a
single-pole double-throw switch to terminate an arm of the R/2R
network at either the positive or negative power-supply terminal.
The resistor ladder is an assembly of 1% tolerance metal-oxide
film resistors. The five arms requiring the highest accuracy are
assembled with series and parallel combinations of 806,000Ω
resistors from the same manufacturing lot.

A single 15V supply provides a positive bus f or the CA3160
follower amplifier and f eeds the CA3085 v oltage regulator . A
“scale-adjust” function is provided by the regulator output control,
set to a nominal 10V level in this system. The line-v oltage
regulation (approximately 0.2%) permits a 9-bit accuracy to be
maintained with variations of sever al volts in the supply. The
flexibility afforded b y the CMOS building b loc ks simplifies the
design of DAC systems tailored to particular needs.

NOTE:

6. “Digital-to-AnalogConversion Using the Harris CD4007A
COS/MOS lC”, Application Note AN6080.

+15V

0.01µF

5

2kΩ

0.1µF

7

6

4

OFFSET
ADJUST

3

10kΩ

BW (-3dB) = 4MHz
SR = 10V/µs

FIGURE 4B. OUTPUT WAVEFORMWITH GROUND REFERENCE

SINE WAVE INPUT

FIGURE 4C. OUTPUT SIGNAL WITH INPUT SIGNAL RAMPING

FIGURE 4. SINGLE SUPPLYVOLTAGE FOLLOWERWITH

ASSOCIATED WAVEFORMS. (e.g., FOR USE IN
SINGLE SUPPLYD/A CONVERTER; SEE FIGURE 9
IN AN6080)

+

CA3160

-

2

1

FIGURE 4A.

Top Trace: Output

Bottom Trace: Input

8

CA3160, CA3160A

Error-Amplifier in Regulated Power Supplies

The CA3160 is an ideal choice for error-amplifier ser vice in
regulated power supplies since it can function as an error­amplifier when the regulated output voltage is required to
approach zero.

The circuit shown in Figure 6 uses a CA3160 as an error
amplifier in a continuously adjustable 1A power supply. One
of the key features of this circuit is its ability to regulate down
to the vicinity of 0V with only one DC power supply input.

An RC networ k, connected between the base of the output
drive transistor and the input voltage, prevents “turn-on
overshoot”, a condition typical of many operational
amplifier regulator circuits. As the amplifier becomes
operational, this RC network ceases to have any influence
on the regulator performance.

Precision Voltage-Controlled Oscillator

The circuit diagram of a precision voltage-controlled oscillator is
shown in Figure 7. The oscillator operates with a tracking error
in the order of 0.02% and a temperature coefficient of

o

0.01%/

C. A multivibrator (A1) generates pulses of constant

10V LOGIC INPUTS

amplitude (V) and width (T2). Since the output (Terminal 6) of
A

(a CA3130) can swing within about 10mV of either supply-

1

rail, the output pulse amplitude (V) is essentially equal to V+.
The average output v oltage (E
non-inverting Input terminal of comparator A
network R
conditions such that E

, C2. Comparator A2 operates to establish circuit

3

= V1. This circuit condition is

AVG

= V T2/T1) is applied to the

AVG

via an integrating

2

accomplished by feedingan output signal from T erminal6 of A
through R4, D4 to the inverting terminal (Terminal 2) of A1,
thereby adjusting the multivibrator interval, T

.

3

Voltmeter With High Input Resistance

The voltmeter circuit shown in Figure 8 illustrates an
application in which a number of the CA3160 characteristics
are exploited. Range-switch SW
and output circuitry to permit selection of the proper output
voltage for feedback to Terminal 2 via 10kΩ current-limiting
resistor. The circuit is powered by a single 8.4V mercury
battery. With zero input signal, the circuit consumes
somewhat less than 500µA plus the meter current required
to indicate a given voltage. Thus, at full scale input, the total
supply current rises to slightly more than 1500µA.

is ganged between input

1

2

+10.010V

+15V

+

2µF
25V

-

103

12

1%

+10.010V

8

22.1K
1%

1K

3.83K
1%

14
11

2

REGULATED

VOLTAGE

ADJUST

6

CD4007A

“SWITCHES”

13

8

100K
1%

806K1%750K

103

1 12

806K

5

1%

806K1%806K

1%

1%

REQUIRED

BIT

RATIO-MATCH

1 Standard
2 ±0.1%
3 ±0.2%
4 ±0.4%
5 ±0.8%

6 - 9 ±1% ABS.

6

CD4007A

“SWITCHES”

13

8

(2)
806K

1%

PARALLELED

RESISTORS

OUTPUT

1
5

LOAD

(4)
806K

1%

LSB MSB

987 654 321
6

CD4007A

“SWITCHES”

13

9

8

7
4

VOLTAGE

REGULATOR

2

3

1
5

806K1%402K1%200K

806K
1%

62

1

CA3085

6

7

4

0.001µF

103

12

(8)
806K

1%

+15V

7

4

100K

OFFSET

NULL

CA3160

5

2K

0.1µF

6

+

-

1

10K

3

VOLTAGE
FOLLOWER

2

FIGURE 5. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3160

9

40V INPUT

+

2.4kΩ

1W

TURN

ON

DELAY

0.2µF

CA3160, CA3160A

2N6385

3

POWER DARLINGTON

SHORT-CIRCUIT CURRENT
LIMIT ADJUSTMENT

2

1Ω

10kΩ

1kΩ

OUTPUT
0V TO 35V
AT 1A

100kΩ

+

100µF

25V

-

CA3086

10 11 2 1

93

8

64

-

Hum and Noise Output <250µV

+15V

R

5

100K

100K

100K

3

R

6

C

1

500pF

2

1.5kΩ

1W

2.2kΩ

+

5µF

-

57

62kΩ

12 14

13

1kΩ

; Regulation (No Load to Full Load) <0.005%; Input Regulation <0.01%/V

RMS

1

2N2102

7

2kΩ

100kΩ50kΩ

6

10kΩ

CA3160

5

1

4.7kΩ

+

-

8

4

1kΩ

1N914

2N2102

3

2

10kΩ

FIGURE 6. VOLTAGE REGULATOR CIRCUIT (0.1V TO 35V AT 1A)

T

V

D

+

MULTI­VIBRATOR
CA3130

-

D

3

D

4

2

D

1

2

T

3

T

1

+15V

7

4

R

1

182K

D

- D5 = 1N914

1

R

10K

VCO CONTROL VOLTAGE (V

f

O

10K

0.1
µF

6

2

D

5

(0V - 10V)

(SENSITIVITY = 1kHz/V)

1M

2

E

= V T2/T

AVG

R

3

1M

C

0.01µF

3 4

2

R

3K

0.01µF

-

1

COMP ARATOR

CA3160

+

4

)

I

1

100K

FIGURE 7. VOLTAGE CONTROLLED OSCILLATOR

56pF 43kΩ

8.2kΩ

0.01µF

+15V

7

5

R

7

+

100µF

-

-

6

0.01µF

Function Generator

A function generator having a wide tuning range is shown in
Figure 9. The adjustment range, in excess of 1,000,000/1, is
accomplished by a single potentiometer. Three operational
amplifiers are utilized: a CA3160 as a voltage follower, a
CA3080 as a high speed comparator, and a second

10

CA3080A as a programmable current source. Three variable
capacitors C
between 500kHz and 1MHz. Capacitors C
trimmer potentiometer in series with C

, C2, and C3 shape the triangular signal

1

, C5, and the

4

maintain essentially

5

constant (+10%) amplitude up to 1MHz.

SW

INPUT

1A

300V
100V

30V
10V

3V

1V
300V
100V

30V
10V

100MΩ

1.02
MΩ

300V
100V

30V
10V

3V

1V
300V
100V

30V
10V

SW

1B

9.9kΩ

22MΩ

CA3160, CA3160A

BATTERY

TEST

OFF ON

3 POSITION
SLIDE SWITCH

+9V

BATTERY

+

CA3160

-

5

9.1kΩ

7

6

4

SW

0.001µF

ADJUST

3

2

1

100kΩ

ZERO

10kΩ

300V

1C

300mV
100mV

100V

30V
10V

3V
1V

30mV
10mV

BATTERY

2.7kΩ

820Ω

9kΩ

900Ω

100Ω

3V CAL.

500Ω

200Ω

1V CAL.

300V
100V

30V
10V

3V

1V
300mV
100mV

30mV
10mV

+

-

SW

500
µF

0-1mA

1D

M

20pF

8.2kΩ

VOLTAGE-CONTROLLED

CURRENT SOURCE

1kΩ

1kΩ

2MΩ

SYMMETRY

-7.5V

100kΩ

MAX FREQ
SET

+7.5V

10kΩ

6.2kΩ

FIGURE 8. HIGH INPUT RESISTANCE DC VOLTMETER

CENTERING

430pF

10kΩ

4 - 60pF

HIGH FREQ

LEVEL

ADJUST

100kΩ

C

4

3

2

+7.5V

+7.5V

7

+

CA3080A

-

5

500Ω

FREQ

ADJUST

6

4

-7.5V

4.7kΩ

EXTERNAL
SWEEPING INPUT

MIN FREQ.SET

500Ω

0.9 - 7pF
C

1

6.2kΩ

10-80pF
C

2

-7.5V

BUFFER

VOLTAGE FOLLOWER

+7.5V

HIGH
FREQ.
SHAPE

4 - 60pF
C

3

3

2

7

+

CA3160

-

4

0.1µF

-7.5V

-7.5V +7.5V

0.1µF

6 2

2kΩ

FIGURE 9A. 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR: 1Hz to 1MHz

6.8MΩ

3

THRESHOLD

DETECTOR

30kΩ

5

-

CA3080

+

10kΩ

50kΩ

C

5

15 - 115pF

+7.5V

7

6

-7.5V

2-1N914

11

CA3160, CA3160A

NOTE: Asquarewave signal modulates the external sweepinginput
toproduce1Hzand 1MHz, showing the 1,000,000/1 frequency range
of the Function Generator.

FIGURE 9B. TWO-TONE OUTPUT SIGNAL FROM THE

FUNCTION GENERATOR

FIGURE 9. 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR: 1Hz to 1MHz

+15V

7

+
CA3130

-

4

+15V

STEP HEIGHT

ADJUST
4 - 60pF

8.2kΩ

6

8

MULTIVIBRATOR RETRACE INHIBIT

1N914

CHARGE

COMMUTATING

NETWORK

100

kΩ

100

kΩ

100

kΩ

15 - 115pF

FREQ

ADJUST

1MΩ

3

2

MULTIVIBRATOR

NOTE: The bottom trace is the sweeping signal and the top trace is
theactual generator output. The center trace displays the 1MHz signal
via delayed oscilloscope triggering of the upper swept output signal.

FIGURE 9C. TRIPLE-TRACEOF THE FUNCTION GENERATOR

SWEEPING TO 1MHz

470pF

2

-

CA3160

3

+

INTEGRATOR

7

5.1kΩ

+15V

6 3

2kΩ

4

10kΩ

+15V

STAIRCASE
OUTPUT

1.5
MΩ

1N914

+15V

7

+

CA3130

2

-

8

4

HYSTERESIS SWITCH

+15mV TO +10V

51kΩ

6

FIGURE 10A. STAIRCASE GENERATOR CIRCUIT

Staircase Generator

Figure 10 shows a staircase generator circuit utilizing three
CMOS operational amplifiers. Two CA3130s are used; one
as a multivibrator, the other as a hysteresis switch. The third
amplifier, a CA3160, is used as a linear staircase generator.

Picoammeter Circuit

Figure 11 is a current-to-voltage converter configuration
utilizing a CA3160 and CA3140 to provide a picoampere

12

100kΩ

meter for 13pA full scale meter deflection. By placing
Terminals 2 and 4 of the CA3160 at ground potential, the
CA3160 input is operated in the “guarded mode”. Under this
operating condition, even slight leakage resistance present
between Terminals 3 and 2 or between Terminals 3 and 4
would result in zero voltage across this leakage resistance,
thus substantially reducing the leakage current.

If the CA3160 is operated with the same voltage on input
Terminals 3 and 2 as on Terminal 4, a further reduction in the

CA3160, CA3160A

input current to the less than one picoampere level can be
achieved as shown in Figure 23.

To further enhance the stability of this circuit, the CA3160
can be operated with its output (Terminal 6) near ground,
thus markedly reducing the dissipation by reducing the
supply current to the device.

The CA3140 stage serves as a X100 gain stage to provide
the required plus and minus output swing for the meter and
feedback network. A 100-to-1 voltage divider network
consisting of a 9.9kΩ resistor in series with a 100Ω resistor
sets the voltage at the 10GΩ resistor (in series with Terminal

3) to ±30mV full-scale deflection. This 30mV signal results
from ±3V appearing at the top of the voltage divider network
which also drives the meter circuitry.

By utilizing a switching technique in the meter circuit and in
the 9.9kΩ and 100Ω network similar to that used in voltmeter
circuit shown in Figure 8, a current range of 3pA to 1nA full
scale can be handled with the single 10GΩ resistor.

STAIRCASE

OUTPUT

2V STEPS

COMPARATOR

OSCILLATOR

Top Trace: Staircase Output 2V Steps

Center Trace: Comparator

Bottom Trace: Oscillator

FIGURE 10B. STAIRCASE GENERATOR WAVEFORM

FIGURE 10. STAIRCASE GENERATOR CIRCUIT

6

10kΩ

560kΩ

-15V

10GΩ

10pF

2

3

0.1µF

1MΩ

-

CA3140

+

-15V

7

4

+15V

6

9.9kΩ

100Ω

5.6kΩ

500Ω

500-0-500µA

M

10MΩ

3

2

100kΩ

+15V

7

+

CA3160

-

5

1

9.1kΩ

0.1µF

4

FIGURE 11. CURRENT-TO-VOLTAGE CONVERTER TO PROVIDE A PICOAMMETER WITH ±3pA FULL SCALE DEFLECTION

1MΩ

30pF

OFFSET

VOLTAGE

ADJUST

+15V

3

2

100kΩ

7

+
CA3160

-

5

1

9.1kΩ

4

100kΩ

0.1µF

8

6

8.2kΩ

1N914

0.1µF

2

3

27kΩ

500µA

-

CA3080A

+

+15V

0.1µF
39kΩ

7

6

100kΩ

4

5

DROOP

ZERO

ADJUST

1MΩ

39kΩ

8.2Ω

0.1µF

2200pF

2

3

+15V

-

CA3140
+

0.1µF

7

6

4

STROBE INPUT

2kΩ

SAMPLE =

HOLD =

15V

0V

FIGURE 12A. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V

13

SAMPLED

OUTPUT

INPUT

SIGNAL

CA3160, CA3160A

SAMPLED

OUTPUT

0V-

INPUT 0V-

SAMPLING

PULSES

Top Trace: Sampled Output

Center Trace: Input Signal

Bottom Trace: Sampling Pulses

FIGURE 12B. SAMPLE AND HOLD WAVEFORM

FIGURE 12. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V

Single Supply Sample-and-Hold System

Figure 12 shows a single supply sample-and-hold system
using a CA3160 to provide a high input impedance and an
input voltage range of 0V to 10V. The output from the input
buffer integrator network is coupled to a CA3080A. The
CA3080A functions as a strobeable current source for the
CA3140 output integrator and storage capacitor. The
CA3140 was chosen because of its low output impedance
and constant gain-bandwidth product. Pulse “droop” during
the hold interval can be reduced to zero by adjusting the
100kΩ bias-voltage potentiometer on the positive input of
the CA3140. This zero adjustment sets the CA3080A output
voltage at its zero current position. In this sample-and-hold
circuit it is essential that the amplifier bias current be
reduced to zero to minimize output signal current during the
hold mode. Even with 320mV at the amplifier bias circuit
terminal (5) at least 1100pA of output current will be
available.

Wien Bridge Oscillator

A simple, single supply Wien Bridge oscillator using a
CA3160 is shown in Figure 13. A pair of parallel-connected
1N914 diodes comprise the gain-setting network which
standardizes the output voltage at approximately 1.1V. The
500Ω potentiometer is adjusted so that the oscillator will
always start and the oscillation will be maintained.
Increasing the amplitude of the voltage may lower the
threshold level for starting and for sustaining the oscillation,
but will introduce more distortion.

SAMPLING

PULSES

Top Trace: Sampled Output

Center Trace: Input Signal

Bottom Trace: Sampling Pulses

FIGURE 12C. SAMPLE AND HOLD WAVEFORM

+15V

0.1

7

µF

6

OUTPUT
f = 100kHz
2% THD AT 1.1V

P-P

-

4

2kΩ

2-1N914

0.01µF
680Ω

500Ω

R

100kΩ

R

100kΩ

f =

R

3

1

51pF

2

C

1

10-80
pF

π √(R

2

51kΩ

C

2

1

|| R2) C1 R3 C

1

+

3

CA3160

2

2

FIGURE 13. SINGLE SUPPLY WEIN BRIDGE OSCILLATOR

Operation with Output Stage Power Booster

The current sourcing and sinking capability of the CA3160
output stage is easily supplemented to provide power-boost
capability. In the circuit of Figure 14, three CMOS transistor­pairs in a single CA3600 lC arrayare shown parallel-connected
with the output stage in the CA3160. In the Class A mode of
CA3600E shown, a typical device consumes 20mA of supply
current at 15V operation. This arrangement boosts the current­handling capability of the CA3160 output stage by about 2.5X.

The amplifier circuit in Figure 14 employs feedback to
establish a closed-loop gain of 20dB. The typical large­signal-bandwidth (-3dB) is 190kHz.

14

CA3160, CA3160A

+15V

2

Q

P2

Q

N2

Q

P3

1

500µF

12

5

Q

N3

INPUT

2kΩ

1µF

A = 20dB
LARGE SIGNAL
BW (-3dB) = 190kHz

1µF

-

680kΩ

0.01µF

1MΩ

+

7

+

3

CA3160

-

2

20kΩ

8

4

6

CA3600

6

14 11

Q

P1

13

3 10

8

Q

N1

7 4 9

FIGURE 14. CMOS TRANSIST OR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3160

Typical Performance Curves

50Ω
100mW
AT 10%
THD

120

100

80

60

40

20

OPEN LOOP VOLTAGE GAIN (dB)

0

VS = ±7.5V
T

= 25oC

A

φ OL

CL = 30pF

R

= 2kΩ

L

1

10

10210310410510610710

FREQUENCY (Hz)

0
50
100
150
200

8

FIGURE 15. OPEN LOOP VOLTAGEGAIN AND PHASE SHIFT

vs FREQUENCY

150

RL = 2kΩ

140

130

120

110

OPEN LOOP PHASE (DEGREES)

100

90

OPEN LOOP VOLTAGE GAIN (dB)

80

-100 -50 0 50 100

FIGURE 16. OPEN LOOP GAIN vs TEMPERATURE

TEMPERATURE (oC)

15

CA3160, CA3160A

Typical Performance Curves

17.5

15

12.5

10

7.5

5

2.5

OUTPUT VOLTAGE [TERMS. 4 AND 6] (V)

0

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5

GATE VOLTAGE [TERMINALS 4 AND 8] (V)

RL = 5kΩ

2kΩ
1kΩ
500Ω

(Continued)

V+ = 15V, V- = 0V
T

= 25oC

A

FIGURE 17. VOLTAGE TRANSFER CHARACTERISTICS OF

CMOS OUTPUT STAGE

14

VO = V+ / 2
V- = 0

12

10

8

6

TA = -55oC

o

25

o

125

C
C

15.0
TA = 25oC

R

= ∞

L

V- = 0

12.5

10.0

7.5

5.0

2.5

QUIESCENT SUPPLY CURRENT (mA)

0

6 8 10 12 14 16 18

POSITIVE SUPPLY VOLTAGE (V)

BALANCED

VO = V+/2

HIGH VO = V+

OR LOW V

O

= V-

FIGURE 18. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

50

) (V)

8

10

0.1

V- = 0V
T

= 25oC

A

1

V+ = 15V

10V

5V

4

2

QUIESCENT SUPPLY CURRENT (mA)

0

0 2 4 6 8 10 12 14 16 18

POSITIVE SUPPLY VOLTAGE (V)

FIGURE 19. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

50

V- = 0V

= 25oC

T

A

10

1

0.1

TRANSISTOR (Q12) (V)

0.01

0.001

0.001 0.01 0.1 1 10 100

VOLTAGE DROP ACROSS NMOS OUTPUT STAGE

MAGNITUDE OF LOAD CURRENT (mA)

V+ = 15V

10V

5V

TRANSISTOR (Q

0.01

0.001

0.001 0.01 0.1 1 10 100

VOLTAGE DROP ACROSS PMOS OUTPUT STAGE

MAGNITUDE OF LOAD CURRENT (mA)

FIGURE 20. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR

(Q8) vs LOAD CURRENT

(nV/√Hz)

N

E

1000

100

10

1

1

1

10

2

10

FREQUENCY (Hz)

3

10

TA = 25oC

= ±7.5V

V

S

4

10

10

5

FIGURE 21. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR

(Q12) vs LOAD CURRENT

16

FIGURE 22. EQUIVALENT NOISE VOLTAGE vs FREQUENCY

CA3160, CA3160A

Typical Performance Curves

10

TA = 25oC

7.5

5

PA

INPUT VOLTAGE (V)

2.5

0

-101234567
INPUT CURRENT (pA)

(Continued)

2

3

V

IN

CA3160

4

V+

4000

VS = ±7.5V

1000

15V

TO

5V

7

6

8

0V

TO

-10V

V-

100

INPUT CURRENT (pA)

10

1

-80 -60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (

o

C)

FIGURE 23. INPUT CURRENT vs COMMON MODE VOLTAGE FIGURE 24. INPUT CURRENT vs TEMPERATURE

7

6

5

TA = 125oC FOR
METAL CAN PACKAGES

4

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V

OUTPUT STAGE TOGGLED

3

2

OFFSET VOLTAGE SHIFT (mV)

1

0

500

0

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V

OUTPUT VOLTAGE = V+ / 2

1000 1500 2000 2500 3000 3500 4000

TIME (HOURS)

FIGURE 25. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE

17