Datasheet 74AC00SJ, 74AC00SCX, 74AC00SC, 74AC00PC, 74AC00MTCX Datasheet (Fairchild Semiconductor)
...Page 1
© 1999 Fairchild Semiconductor Corporation DS009911 www.fairchildsemi.com
November 1988
Revised November 1999
74AC00 • 74ACT00 Quad 2-Input NAND Gate
74AC00 • 74ACT00
Quad 2-Input NAND Gate
General Description
The AC/ACT00 contains four 2-input NAND gates.
Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT00 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering form. (PC not available in Tape and Reel.)
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74AC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ Type II, 5.3mm Wide
74AC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT00SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
74ACT00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ Type II, 5.3mm Wide
74ACT00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT00PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
A
n
, B
n
Inputs
O
n
Outputs
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74AC00 • 74ACT00
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and ou tput/inp ut loadi ng varia bles. Fairchild does no t
recommend operat ion of FACT circuits outside da t abook specifications.
DC Electrical Characteristics for AC
Note 2: All outputs loaded; thresholds on input assoc iat ed with output under tes t.
Note 3: I
IN
and ICC @ 3.0V are guaranteed to be less than or equa l to th e respective limit @ 5.5V VCC.
Note 4: Maximum test duratio n 2. 0 ms, one output loaded at a time.
Supply Voltage (VCC) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= VCC + 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC + 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= VCC + 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
Junction Temperature (T
J
)
PDIP 140°C
Supply Voltage (V
CC
)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (V
I
) 0V to V
CC
Output Voltage (VO) 0V to V
CC
Operating Temperature (TA) −40°C to +85°C
Minimum Input Edge Rate (∆V/∆t)
AC Devices
V
IN
from 30% to 70% of V
CC
VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
TA = +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC − 0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC − 0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
5.5 5.49 5.4 5.4
VIN = V
IL
or V
IH
3.0 2.56 2.46 IOH = −12 mA
4.5 3.86 3.76 V I
OH
= −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
VIN = VIL or V
IH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µAVI = VCC, GND
(Note 3) Leakage Current
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 4) 5.5 −75 mA V
OHD
= 3.85V Min
ICC Maximum Quiescent Supply Current 5.5 2.0 20.0 µAVIN = VCC or GND
(Note 3)
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74AC00 • 74ACT00
DC Electrical Characteristics for ACT
Note 5: All outputs loaded; thres holds on input associate d w it h output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
Note 8: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol Parameter
V
CC
TA = +25°C TA = −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8
V
V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or V
CC
− 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4
VI
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
VIN = V
IL
or V
IH
4.5 3.86 3.76
V
IOH = −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 5)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1
VI
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
VIN = V
IL
or V
IH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 5)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µAVI = VCC, GND
Leakage Current
I
CCT
Maximum ICC/Input 5.5 0.6 1.5 mA VI = VCC − 2.1V
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 6) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 2.0 20.0 µA
VIN = V
CC
Supply Current or GND
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF CL = 50 pF
Units
(Note 7) Min Typ Max Min Max
t
PLH
Propagation Delay 3.3 2.0 7.0 9.5 2.0 10.0
ns
5.0 1.5 6.0 8.0 1.5 8.5
t
PHL
Propagation Delay 3.3 1.5 5.5 8.0 1.0 8.5
ns
5.0 1.5 4.5 6.5 1.0 7.0
V
CC
TA = +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
CL = 50 pF CL = 50 pF
Units
(Note 8) Min Typ Max Min Max
t
PLH
Propagation Delay 5.0 1.5 5.5 9.0 1.0 9.5 ns
t
PHL
Propagation Delay 5.0 1.5 4.0 7.0 1.0 8.0 ns
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF VCC = Open
C
PD
Power Dissipation Capacitance 30.0 pF VCC = 5.0V
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74AC00 • 74ACT00
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
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74AC00 • 74ACT00
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOIC), EIAJ Type II, 5.3mm Wide
Package Number M14D
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74AC00 • 74ACT00
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide
Package Number MTC14
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74AC00 • 74ACT00 Quad 2-Input NAND Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.3 00” Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the
user.
2. A critical compo nent in any com ponen t of a life s upp ort
device or system whose failure to perform can be reasonably expected to cause the failure of the l ife support
device or system, or to affect its safety or effectiveness.
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