Datasheet 74ABTL3205BB Datasheet (Philips)

INTEGRATED CIRCUITS

74ABTL3205

10-bit BTL transceiver with registers

Product specification 1995 Jun 16




Philips Semiconductors Product specification

ns

ns

74ABTL320510-bit BTL transceiver with registers

FEA TURES

•10-bit BTL transceiver

•Drives heavily loaded backplanes with equivalent load

impedances down to 10 ohms

•High drive 100mA BTL open collector drivers on B-port

•Allows incident wave switching in heavily loaded backplane buses

•Reduced BTL voltage swing produces less noise and reduces

power consumption

•Built-in precision band-gap reference provides accurate receiver

thresholds and improved noise immunity

•Compatible with IEEE Futurebus+ or proprietary BTL backplanes

•Controlled output ramp and multiple GND pins minimize ground

bounce

•Tight output skew (0.5nsec typical)

•Glitch-free power up/down operation

•Low I

current

CC

•Supports live insertion

•High density packaging

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

DESCRIPTION

This transceiver is a 10 bit bidirectional transceiver and is intended
to provide the electrical interface to a high performance wired-OR
bus.

The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port insure very good margins by limiting
the switching threshold to a narrow region centered at 1.55V .

The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading (<6pF) by placing an internal series
diode on the drivers. BTL also provides incident wave switching, a
necessity for high performance backplanes.

To support live insertion, OEB is held Low during power on/off cycles
to insure glitch free B port drivers. Proper bias for B port drivers
during live insertion is provided by the BIAS V pin when at a 5V level
while V
reverse bias the BTL driver series Schottky diode, and also bias the
B port output pins to a voltage between 1.62V and 2.1V . This bias
function is in accordance with IEEE BTL standard 1194.1. If live
insertion is not a requirement, the BIAS V pin should be tied to a
V

The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package. The LOGIC V
internally to minimize noise and may be externally decoupled
separately or simply tied together.

This transceiver function is intended to operate in a half-duplex
mode. Low current in standby mode is obtained by powering down
unused circuitry. Likewise, transmit circuitry is powered down when
in receive mode and receive circuitry is powered down while in
transmit mode.

is Low. The BIAS V pin is a low current input which will

CC

pin.

CC

and BUS VCC pins are also isolated

CC

QUICK REFERENCE DATA

SYMBOL PARAMETER TYPICAL UNIT

t

PLH

t

PHL

t

PLH

t

PHL

C

I

I

OB

OL

CC

Propagation delay 3.3
An to Bn 3.7

Propagation delay 3.6
Bn to An 3.5

Output capacitance (B0 - B8) only) 6 pF
Output current (B0 - B8) only) 100 mA

Standby 1

Supply current

An to Bn 7
Bn to An 18

mA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

52-PIN PQFP –40°C to +85°C 74ABTL3205 BB 74ABTL3205 BB SOT379-1

1995 Jun 16 853-1802 15352

2

Philips Semiconductors Product specification

74ABTL320510-bit BTL transceiver with registers

PIN CONFIGURATION

TTL Gnd

TTL GND

TTL GND

AClk2

TTL GND

TTL GND

CC

AClkin

TTL Gnd

AClk1

1
2

A0
A1

3
4

A2

5
6

A3

7
8
9

A4

10

A5

11
12

A6

13

14 15 16 17 18 19 20

A7

TTL Gnd

V

CC

BG V

49505152

APAR

BG GND

BiasV

OEA1

OEA2

464748

21 22 23 24 25 26

AFP

Power Up

OEB

M/S

Mode

IEA

Recmode

V

434445 404142

CC

V

Transmode

CC

BUS GND

BUS GND

BClk1

B7

39
38
37
36
35
34
33
32
31
30
29
28
27

BUS GND
B0

B1

BUS GND
B2
B3
BUS GND

BClk2

BUS GND
B4
B5
BUS GND
B6

SA00138

PIN DESCRIPTION

SYMBOL FUNCTION ASSERTION I/O LOGIC

OEA1 Output enable data receiver group 1 Low Input TTL
OEA2 Output enable data receiver group 2 Low Input TTL
OEB Output enable data transmitter Low Input TTL
IEA Output enable clock and framepulse receiver Low Input TTL
M/S Master/Slave select:

L: Master, enable clock transmitter
H: Slave, disable clock transmitter

Mode

Low: Data through mode
High: Registered data mode

Power Up Power up mode, held low during power up to

Low Input TTL

disable clock and data transmitters
Recmode Enables receiver High Input TTL
Tranmode Enables transmitter High Input TTL
AClk1 Clock or data path I/O TTL
AClkln

IEA = H → Input for busclock

IEA = L → Output for busclock
A0..A3 data group 1 I/O TTL
AClk2 Clock or data path I/O TTL
AFPIn Alternate data path Output TTL
APAR Alternate data path Input TTL
A4..A7 data group 2 I/O TTL
BClk1 Clock or data path I/O BTL
B0..B3 data group 1 I/O BTL
BClk2 Clock or data path I/O BTL
B4..B7 data group 2 I/O BTL

Input TTL

Input TTL

I/O TTL

1995 Jun 16

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Philips Semiconductors Product specification

74ABTL320510-bit BTL transceiver with registers

LOGIC DIAGRAM

ACLKin

I/O

OUT

I/O

I/O

IN

I/O

I/O

ACLK1

ACLK2

AFP

APAR

A0-A3

A4-A7

DCQ

DCQ

DCQ

BCLK1

BCLK2

B0-B3

B4

-B7

I/O

I/O

I/O

I/O

IN

IN

IN

IN

IN

IN

IN

IN

IN

1995 Jun 16

IEA

OEB

/S

M

OEA1

OEA2

RECMODE

MODE

TRANMODE

POWERUP

Definition for the MUX:

Low High

SA00139

4

Philips Semiconductors Product specification

to

to

to

to

to

to

to

to

to

to

to

to

to

to

74ABTL320510-bit BTL transceiver with registers

FUNCTION TABLE

MODE

An to Bn

(REGISTERED)

AN to Bn

(THROUGH)

B0-B3

to

A0-A3

(THROUGH)

B4-B7

to

A4-A7

(THROUGH)

ACLK1
BCLK1

ACLK2
BCLK2

BCLK1
ACLK1

BCLK2
ACLK2

APAR

BCLK2
BCLK2

AFPIn

BCLK1

ACLKin

An Bn

I O ° X X X X H H L X H X H L H H
h O ° X X X X H H L X H X H L H H
L O X X X X X H H L X X X L L H H
H O X X X X X H H L X X X L L H H

O L X X X X X L X H X X X X H L L
O H X X X X X L X H X X X X H L L
O L X X X X X X L H X X X X H L L
O H X X X X X X L H X X X X H L L

X X X L X O X H X X X X L X X H H
X X X H X O X H X X X X L X X H H
X X X X L X O X H H X X L L X H H
X X X X H X O X H H X X L L X H H
X X X O X L X L X X X X X X H L X
X X X O X H X L X X X X X X H L X
X X X X O X L X L X X X X X H L X
X X X X O X H X L X X X X X H L X
X X ° X X X X X X L I X H H X H H
X X ° X X X X X X L h X H H X H H
X X X X X X L X X X X L X X H L X
X X X X X X H X X X X L X X H L X
X X O X X L X H H L O L H H L H H
X X O X X H X H H L O L H H L H H

ACLKinACLK1ACLK2BCLK1BCLK

2

OEA1 OEA2 OEB APAR IEA M/S MODE

INPUTS

REC

MODE

TRAN

MODE

POWER

UP

MODE

An to Bn

(REGISTERED)

AN to Bn

(THROUGH)

B0-B3

to

A0-A3

(THROUGH)

B4-B7

to

A4-A7

(THROUGH)

ACLK1
BCLK1

ACLK2
BCLK2

BCLK1
ACLK1

BCLK2
ACLK2

APAR

BCLK2
BCLK2

AFPIn

BCLK1

ACLKin

OUTPUTS

An Bn

Input H* X X X X X X

Input L X X X X X X

Input H* X X X X X X

Input L X X X X X X

H Input Input X X X X X
L Input Input X X X X X
H Input Input X X X X X
L Input Input X X X X X

X X X Input X H* X X
X X X Input X L X X
X X X X Input X H* X
X X X X Input X L X
X X X H X Input X X
X X X L X Input X X
X X X X H X Input X
X X X X L X Input X
X X Input X X X H* X
X X Input X X X L X
X X X X X X Input H*
X X X X X X Input L
X X H X X Input X X
X X L X X Input X X

ACLK

ACLK1 ACLK2 BCLK1 BCLK2

in

AF
Pin

NOTES:

H = High voltage level
L = Low voltage level
h = High voltage level one set-up time prior to

Low to High ACLKin transition

l = Low voltage level one set-up time prior to

Low to High ACLKin transition

° = Low to High transition

Z = High impedance (off) state
H* = Goes to level of pull-up voltage
X = Don’t care
O = Output

1995 Jun 16

5

Philips Semiconductors Product specification

VINInput voltage

I

Current applied to output in Low output state

74ABTL320510-bit BTL transceiver with registers

LOGIC SYMBOL (IEEE/IEC)

Recmode
Transmode
Powerup
OEA1
OEA2
OEB
IEA

/S

M
MODE

EN1
EN2
EN3
EN4
EN5
EN6

6C7

&

EN8

AClk1
AClkIn

A0
A1

A2

A3

AClk2
AFP

APAR

A4

A5

A6

A7

1
4

1

7D53

17D 3

17D 3

17D 3

2 5
4

7D

27D 3

27D 3

27D 3

27D 3

8

BClk1

B0

B1

B2

B3

BClk2

B4

B5

B6

B7

SA00140

ABSOLUTE MAXIMUM RA TINGS

Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted, these limits are over the operating free-air temperature range.

SYMBOL

V

CC

I

IN

V

OUT

OUT

T

amb

T

STG

Supply voltage –0.5 to +7.0 V

p

Input current –18 to +5 mA
Voltage applied to output in High output state –0.5 to +V

pp

p

Operating free-air temperature range –40 to +85 °C
Storage temperature –65 to +150 °C

PARAMETER RATING UNIT

TTL Signals –1.2 to +7.0 V
BTL Signals –1.2 to +5.5 V

p

A0 - A8 48 mA
B0 - B8 200 mA

CC

/v

1995 Jun 16

6

Philips Semiconductors Product specification

1

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

BTL

VIKIn ut clam voltage

BTL

IILLow-level in ut current

74ABTL320510-bit BTL transceiver with registers

DC ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range unless otherwise noted.

LIMITS

MIN TYP

I

OH

I

OFF

V

OH

High level output current BTL

Power-off output current BTL

High-level output voltage TTL

VCC = MAX, VIL = MAX,
VIH = MIN, VOH = 1.9V

VCC = 0.0V, VIL = MAX,
VIH = MIN, VOH = 1.9V

VCC = MIN, VIL = MAX,
VIH = MIN, IOH = –3mA

VCC = MIN to MAX,

4

4

2.5 2.85 3.4 V

VIL = MAX, VIH = MIN,
I

= –10µA

OH

VCC = MIN, VIL = MAX,
VIH = MIN, IOL = 24mA

VCC = MIN, VIL = MAX,
VIH = MIN, IOL = 100mA

VCC = MIN, VIL = MAX,
VIH = MIN, IOL = 4mA

IK

0.75 1.0 1.10 V

0.5 0.7 V

VCC = MAX,
VI = 0.5V or 5.5V

VCC = MAX, VI = 2.7V,
Bn = AIn = 0V

VCC = MAX, VI = 1.9V 0.1 100 µΑ
VCC = MAX, VI = 3.5V

5

100 mA

VCC = MAX 1 3 mA
VCC = MAX

Mode = Low
VCC = MAX

Mode = High
VCC = MAX 18 25 mA

VCC = MAX 29 43 mA

V

I

I

I

IH

I

OZH

I

OZL

I

OS

I

CC

OL

TTL

Low-level output voltage

p

p

Input current at maximum
input voltage

TTL VCC = MIN, II = I
BTL VCC = MIN, II = –18mA 0.8 –1.2 V

TTL

TTL

High-level input current

p

TTL VCC = MAX, VI = 0.5V 0.1 –20 µΑ

BTL VCC = MAX, VI = 0.75V 0.1 –100 µΑ
Off-state output current TTL VCC = MAX, VO = 2.7V 0.1 50 µΑ
Off-state output current TTL VCC = MAX, VO = 0.5V 20 –50 µΑ
Short-circuit output

3

current

TTL VCC = MAX, VO = 0.0V –60 130 –150 mA

Recmode Low

Tranmode Low

Recmode Low

Tranmode High

Supply current (total)

Recmode Low

Tranmode High

Recmode High
Tranmode Low

Recmode High

Tranmode High

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

= 5V, T

CC

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I

4. Due to test equipment limitations, actual test conditions are V

5. For B port input voltage between 3 and 5 volts I

tests should be performed last.

OS

will be greater than 100µA, but the parts will continue to function normally.

IH

= 1.8V and VIL = 1.3V for the B side.

IH

TTL signals CLKin, CLK-1/CLK-OUT, CLK-2/FP-OUT, /FP-IN, /PARITY t,A0..A7, OEB, MASTER/SLAVE, MODE, OEA1, OEA2
BTL signals CLK1BTL, CLK2BTL, B0..B7

2

MAX

0.5 100 µA

10 100 µA

VCC – 1.1 V

0.35 0.5 V

0.8 –1.2 V

0.1 ±50 µΑ

0.1 20 µΑ

7 12 mA

13 21 mA

1995 Jun 16

7

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

I

Bias in DC current

gy

Waveform 2

ns

gy

Waveform 2

ns

gy

Waveform 2

ns

gy

Waveform 2

ns

gy

Waveform 2

ns

Waveform 1, 2

ns

Waveform 4, 5

ns

74ABTL320510-bit BTL transceiver with registers

LIVE INSERTION SPECIFICA TIONS

LIMITS

MIN NOM MAX

V

BIASV

BIASV

Ǹ

Bn

AC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PLZ

t

PHZ

t

PLZ

t

TLH

t

THL

tSK(p)

NOTES:

1. |t

PN

HL. Skew times are valid only under same test conditions (temperature, V

2. t

SK

duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).

Bias pin DC current VCC = 0 to 5.25V, Bn = 0 to 2.0 V 4.5 5.5 V

VCC = 0 to 4.75 V, Bn = 0 to 2.0V,

p

Bias V = 4.5 to 5.5V
VCC = 4.5 to 5.5V, Bn = 0 to 2.0 V,

Bias V = 4.5 to 5.5V

1 mA

10 µA

Bus voltage during prebias B0 – B8 = 0V, Bias V = 5.0V 1.62 2.1 V

A PORT LIMITS

TEST

CONDITION

= +25°C

amb

VCC = 5V

C

= 50pF, CL = 500Ω

L

T

= –40°C to +85°C

amb

VCC = 5V ± 10%

C

= 50pF, CL = 500Ω

L

UNIT

T

MIN TYP MAX MIN MAX

Propagation delay
Bn to An

Propagation delay,
BCLK1 to ACLK1

Propagation delay
BCLK1 to ACLKin

Propagation delay
BCLK2 to ACLK2

Propagation delay
BCLK2 to AFP

Output Enable time
OEA1, OEA2, IEA to An

Output Disable time
OEA1, OEA2, IEA to An

Output transition time, An Port
10% to 90%, 90% to 10%

– t

2

PLH| MAX

Pulse skew
|t

PHL

Test Circuit and

Waveforms

Waveform 3 2.0 ns

2.0 3.6 6.5 2.0

1.8 3.5 6.1 1.8

7.3

6.7

2.0 3.8 6.5 2.0 7.3

1.8 3.6 6.1 1.8 6.7

2.0 3.7 6.5 2.0 7.3

1.8 3.7 6.1 1.8 6.7

2.0 3.7 6.5 2.0 7.3

1.8 3.9 6.1 1.8 6.7

2.0 3.8 6.5 2.0 7.3

1.8 3.9 6.1 1.8 6.7

2.0 3.8 6.5 2.0 7.3

1.8 2.5 6.1 1.8 6.7

1.6 2.5 5.6 1.4 5.7

2.0 3.3 7.8 1.8 8.2

3.0

1.7

7.0

4.0

ns

actual – tPM actual| for any data input to output path compared to any other data input to output path where N and M are either LH or

, loading, etc.).

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

CC

1995 Jun 16

8

Philips Semiconductors Product specification

gy

Waveform 2

5.7

ns

gy

Waveform 1, 2

ns

gy

Waveform 1, 2

ns

gy

Waveform 2

ns

gy

Waveform 2

ns

Waveform 1, 2

ns

TLH

Transition time, Bn Port

Test Circuit and

SYMBOL

PARAMETER

UNIT

Waveform 6

ns

Waveform 6

ns

74ABTL320510-bit BTL transceiver with registers

AC ELECTRICAL CHARACTERISTICS

B PORT LIMITS

T

= +25°C

SYMBOL PARAMETER

TEST

CONDITION

amb

VCC = 5V

C

= 30pF, RU = 18.5Ω

D

MIN TYP MAX MIN MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

TLH

t

THL

tSK(p)

Propagation delay
An to Bn

Propagation delay,
ACLKin to Bn

Propagation delay
ACLKin to BCLK2

Propagation delay
ACLK1 to BCLK1

Propagation delay
ACLK2 to BCLK2

Enable/disable time
OEB to Bn or BCLK2

Transition time, Bn Port Test Circuit and
(1.3V to 1.8V)

Pulse skew2
|t

– t

PHL

PLH| MAX

Waveforms

Waveform 3 2.0 ns

1.0 3.3 4.7 1.0

1.0 2.7 4.5 1.0

2.0 4.6 5.9 2.0 6.3

2.0 4.5 5.9 2.0 6.3

2.0 4.6 7.3 2.0 7.6

2.0 4.5 7.3 2.0 7.6

1.0 3.2 4.7 1.0 5.1

1.0 2.9 4.5 1.0 4.7

1.0 3.1 5.7 1.0 6.0

1.0 3.1 5.5 1.0 5.6

1.0 3.8 6.8 1.0 7.6

1.0 3.4 6.4 1.0 6.9

1.0 2.5 1.0 3.0

0.6 2.0 0.6 2.5

NOTES:

actual – tPM actual| for any data input to output path compared to any other data input to output path where N and M are either LH or

1. |t

PN

HL. Skew times are valid only under same test conditions (temperature, V

(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

2. t

SK

duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).

, loading, etc.).

CC

T

= –40°C to +85°C

amb

VCC = 5V ± 10%

C

= 30pF, RU = 18.5Ω

L

UNIT

ns

AC SETUP REQUIREMENTS

ts(H)
ts(L)

th(H)

th(L)

Setup time
An to ACLKin

Hold time
An to ACLKin

TEST

CONDITION

LIMITS

T

= +25°C

amb

VCC = 5V

T

= –40°C to +85°C

amb

VCC = 5V ± 10%

CL = 50pF (A side) / CD = 30pF (B side)

RL = 500Ω (A side) / RU = 18.5Ω (B side)

MIN TYP MIN MAX

1.9 2.0

1.3 1.5

1.8 2.3

2.0 2.0

1995 Jun 16

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Philips Semiconductors Product specification

74ABTL320510-bit BTL transceiver with registers

AC WAVEFORMS

VM = 1.55V for Bn, VM = 1.5V for all others

OEAn

An

V

M

t

PLH

V

M

V

M

t

PHL

V

M

SA00141

Waveform 1. Propagation Delay for Data or

Output Enable to Output

An, Bn

Bn, An

V

M

t

PHL

V

M

V

M

t

PLH

Waveform 2. Propagation Delay for Data to Output

V

M

SA00142

OEA

An

V

M

t

PZH

V

M

t

PHZ

–0.3V

V

V

M

OH

0V

SA00144

Waveform 4. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

OEA

An

V

M

t

PZL

V

M

t

PLZ

V

M

VOL +0.3V

SA00145

Waveform 5. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

An, Bn

An, Bn

V

M

tSK(0)

Waveform 3. Output Skews

V

M

SA00143

An
or
Bn

ACLKin

VMV

tS(H) th(H)

Waveform 6. Data Setup and Hold Times

V

V

M

M

(L)

t

S

V

M

M

(L)

t

h

V

M

SA00349

1995 Jun 16

10

Philips Semiconductors Product specification

74ABTL320510-bit BTL transceiver with registers

TEST CIRCUIT AND WAVEFORMS

V

CC

BIAS V

V

PULSE

GENERATOR

IN

D.U.T.

R

T

Test Circuit for 3-State Outputs on A Port

SWITCH POSITION

TEST SWITCH
t

, t

PZL

V

D.U.T.

closed
open

CC

PULSE

GENERATOR

V

IN

PLZ

All other

BIAS V

R

T

V

OUT

C

L

2.0V (for R

2.1V (for RU = 16.5Ω)

V

OUT

= 9Ω)

U

R

C

U

D

R

L

R

L

7.0V

t

90%

NEGATIVE
PULSE

POSITIVE
PULSE

10%

W

V

M

10% 10%

t

(tF)

THL

(tR)t

t

TLH

90% 90%

V

M

t

W

V

M

V

M

90%

10%

t

TLH
THL

AMP (V)

LOW V

(tR)
(tF)

AMP (V)

LOW V

VM = 1.55V for Bn or Bn, VM = 1.5V for all others

Input Pulse Definition

ABTL

Amplitude Low V Rep. Rate t

INPUT PULSE REQUIREMENTS

W

t

TLHtTHL

A Port 3.0V 0.0V 1MHz 500ns 2.5ns 2.5ns
B Port 2.0V 1.0V 1MHz 500ns 2.5ns 2.5ns

Test Circuit for Outputs on B Port

DEFINITIONS

R

= Load resistor; see AC CHARACTERISTICS for value.

L

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

generators.

OUT

of pulse

CD = Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

RU = Pull up resistor;

see AC CHARACTERISTICS for value.

SA00146

1995 Jun 16

11

Philips Semiconductors Product specification

74ABTL320510-bit BTL transceiver with registers

QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm SOT379-1

1995 Jun 16

12

Philips Semiconductors Product specification

74ABTL320510-bit BTL transceiver with registers

NOTES

1995 Jun 16

13

Philips Semiconductors Product specification

74ABTL320510-bit BTL transceiver with registers

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 2000

All rights reserved. Printed in U.S.A.

Date of release: 01-00

Document order number: 9397 750 06827

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1995 Jun 16

14