Page 1
INTEGRATED CIRCUITS
74ABT16260/74ABTH16260
12-bit to 24-bit multiplexed D-type latches
(3-State)
Product specification
Supersedes data of 1996 Nov 20
IC23 Data Handbook
1998 Feb 10
Page 2
Philips Semiconductors Product specification
C
pF
ns
12-bit to 24-bit multiplexed D-type latches (3-State)
FEATURES
•ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model (C = 200pF, R = 0).
•Latch-up performance exceeds 500mA per JEDEC Standard
JESD-17.
•Distributed V
switching noise.
and GND pin configuration minimizes high-speed
CC
•Flow-through architecture optimizes PCB layout.
•High-drive outputs (–32mA I
, 64mA IOL).
OH
•74ABTH16260 incorporates bus-hold inputs which eliminate the
need for external pull-up resistors.
•Package options:
– 56-pin plastic Shrink Small-Outline Package (SSOP)
– 56-pin plastic Thin Shrink Small-Outline Package (TSSOP)
DESCRIPTION
The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed
D-type latch used in applications where two separate data paths
must be multiplexed onto, or demultiplexed from, a single data path.
Typical applications include multiplexing and/or demultiplexing of
address and data information in microprocessor or bus-interface
applications. This device is alto useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B
, and OEA) inputs control the bus transceiver functions. The
OE2B
OE1B
and OE2B control signals also allow bank control in the A to
B direction.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ABTH incorporates the bus hold feature. The 74ABT does
not include bus hold feature. Both parts are available in 56-pin
SSOP and TSSOP.
74ABT16260
74ABTH16260
,
should be tied to VCC through a pull-up resistor;
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
nAx to nBx nBx to nAx
Input capacitance VI = 0 V or V
Output capacitance V
Total supply current Outputs disabled 100 µA
CONDITIONS
T
= 25°C; GND = 0V
amb
p
= 50
L
CC
= 0 V or 5.0 V 6 pF
I/O
TYPICAL UNIT
2.8
2.5
4 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16260 DL BT16260 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16260 DGG BT16260 DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16260 DL BH16260 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16260 DGG BH16260 DGG SOT364-1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21 An Data inputs/outputs (A)
23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42 1Bn Data inputs/outputs (B1)
6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43 2Bn Data inputs/outputs (B2)
1, 29, 56 OEA, OE1B, OE2B Output enable input (active low)
2, 27, 30, 55 LE1B, LE2B, LEA1B, LEA2B Latch enable inputs
1998 Feb 10 853-2048-18945
2
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Philips Semiconductors Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
PIN CONFIGURATION
1
2
LE1B
2B3
3
GND
4
2B2
5
2B1
6
V
7
CC
A1
8
A2
9
A3
10
GND
11
12 45
13
A6
14
A7
15
A8
16
A9
17
GND
18 39
19 38
A10
20
21
A12
22
V
CC
23
1B1
24
1B2
25 32
26 31 1B41B3
27 30 LEA1BLE2B
28 29SEL OE1B
OE2B
56OEA
55
LEA2B
54
2B4
53
GND
52
2B5
51
2B6
50
V
CC
2B7
49
2B8
48
47
2B9
46
GND
2B10A4
2B11
44A5
2B12
43
1B12
42
1B11
41
1B10
40
GND
1B9
37A11
1B8
36
1B7
V
35
CC
34
1B6
33
1B5
GNDGND
FUNCTION TABLES
B to A (OEB = H)
1B 2B SEL LE1B LE2B OEA A
H X H H X L H
L X H H X L L
X X H L X L A0
X H L X H L H
X L L X H L L
X X L X L L A0
X X X X X H Z
A to B (OEA = H)
A LEA1B LEA2B OE1B OE2B 1B 2B
H H H L L H H
L H H L L L L
H H L L L H 2B0
L H L L L L 2B0
H L H L L 1B0 H
L L H L L 1B0 L
X L L L L 1B0 2B0
X X X H H Z Z
X X X L H Active Z
X X X H L Z Active
X X X L L Active Active
74ABT16260
74ABTH16260
INPUTS OUTPUT
INPUTS OUTPUT
1998 Feb 10
SA00435
3
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Philips Semiconductors Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
LOGIC DIAGRAM (POSITIVE LOGIC)
2
LE1B
27
LE2B
30
LEA1B
55
LEA2B
56
OE2B
29
OE1B
1
OEA
28
SEL
G1
8
A1
1
1
74ABT16260
74ABTH16260
C1
1D
23
1B1
C1
1D
C1
1D
C1
1D
TO 11 OTHER CHANNELS
6
SA00436
2B1
1998 Feb 10
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
SYMBOL
PARAMETER
UNIT
12-bit to 24-bit multiplexed D-type latches (3-State)
74ABT16260
74ABTH16260
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise specified)
V
CC
V
I
V
O
I
O
I
IK
I
OK
T
stg
NOTES:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability .
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Supply voltage range –0.5 7 V
Input voltage range see Note 2 –0.5 7 V
Voltage range applied to any output in the high state or power-off state –0.5 5.5 V
Current into any output in the low state 128 mA
Input clamp current VI < 0 –18 mA
Output clamp current VO < 0 –50 mA
Maximum power dissipation at T
= 55°C (in still air) see Note 3 1.4 W
amb
Storage temperature range –65 +150 °C
1
LIMITS
MIN MAX
RECOMMENDED OPERATING CONDITIONS
1
LIMITS
MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
Supply voltage 4.5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
CC
High-level output current –32 mA
Low-level output current 64 mA
∆t∆/v Input transition rise or fall rate Outputs enabled 10 ns/V
∆t∆/V
T
amb
Power-up ramp rate 200 µs/V
CC
Operating free-air temperature –40 +85 °C
NOTE:
1. Unused or floating inputs must be held high or low .
V
1998 Feb 10
5
Page 6
Philips Semiconductors Product specification
I
g
ICCQuiescent su ly current
mA
12-bit to 24-bit multiplexed D-type latches (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
SYMBOL PARAMETER TEST CONDITIONS
Min Typ Max Min Max
V
V
V
Input clamp voltage VCC = 4.5V; IIK = –18mA –0.8 –1.2 –1.2 V
IK
VCC = 4.5V; IOH = –3mA; VI = VIL or V
High-level output voltage
OH
VCC = 5.0V; IOH = –3mA; VI = VIL or V
VCC = 4.5V; IOH = –32mA; VI = VIL or V
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
OL
I
Input leakage current
I
VCC = 5.5V; VI = VCC or GND
IH
IH
IH
IH
Control
pins
VCC = 5.5V; VI = VCC or GND Data pins ±3 ±5 µA
I
HOLD
Bus Hold current
VCC = 4.5V; VI = 0.8V
VCC = 4.5V; VI = 2.0V
A or B
ports
–75 –75
VCC = 5.5V; VI = 0 to 5.5V ±500 ±500
I
OFF
IPU/I
I
OZH
I
OZL
I
CEX
Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
Power-up/down 3-State
PD
output current
3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
I
O
Output current
1
pp
VCC = 2.0V; VO = 0.5V;
VI = GND or VCC; VOE = V
CC
IH
IH
CC
VCC = 5.5V; VO = 2.5V –50 –100 –225 –50 –225 mA
VCC = 5.5V; Outputs High, VI = GND or V
VCC = 5.5V; Outputs Low, VI = GND or V
CC
CC
VCC = 5.5V; Outputs 3-State;
VI = GND or V
∆I
Additional supply current per
CC
input pin
2
Outputs enabled, one input at 3.4V , other
inputs at VCC or GND; VCC = 5.5V
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
3. This is the bus hold minimum overdrive current required to force the input to the opposite logic state.
= +25°C
amb
2.5 2.9 2.5 V
3.0 3.4 3.0 V
2.0 2.4 2.0 V
0.42 0.55 0.55 V
±0.01 ±1 ±1 µA
75 75
±60 ±200 ±200 µA
1.0 10 10 µA
–1.0 –10 –10 µA
50 50 µA
0.2 1.5 1.5
8 19 19
0.1 1.0 1.0
0.1 1.5 1.5 mA
or GND.
CC
74ABT16260
74ABTH16260
T
= –40°C
amb
to +85°C
UNIT
µA
1998 Feb 10
6
Page 7
Philips Semiconductors Product specification
SYMBOL
UNIT
A or B
B or A
LE
A or B
t
t
OE
A or B
OE
A or B
SYMBOL
PARAMETER
UNIT
12-bit to 24-bit multiplexed D-type latches (3-State)
AC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VCC = 5V, T
FROM (INPUT) TO (OUTPUT) MIN TYP MAX MIN MAX
t
PLH
t
PHL
t
PLH
t
PHL
PLH
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
SEL (B1) A 1.3 3.2 4.6 1.3 5.3 ns
SEL (B2) A 1.1 2.8 4.9 1.1 6 ns
SEL (B1) A 1.5 3.0 4.4 1.5 4.4 ns
SEL (B2) A 1.6 2.6 5.1 1.6 5.9 ns
1 2.8 4.8 1 5.6 ns
1 2.5 5 1 5.9 ns
1.1 3.2 4.9 1.1 5.8 ns
1.1 3.2 4.9 1.1 5.3 ns
1 2.9 4.7 1 5.7 ns
1.6 2.2 5.1 1.6 5.8 ns
2.2 4.1 5.4 2.2 6.4 ns
1.3 3.2 4.4 1.3 4.8 ns
= 25°C T
amb
74ABT16260
74ABTH16260
= –40°C to +85°C
amb
AC SETUP CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted)
t
w
t
su
t
h
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high 3.3 3.3 ns
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓ 1.5 1.5 ns
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓ 1 1 ns
VCC = 5V, T
= 25°C T
amb
= –40°C to +85°C
amb
MIN MAX MIN MAX
1998 Feb 10
7
Page 8
Philips Semiconductors Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
AC WAVEFORMS
VM = 1.5V for all waveforms
The outputs are measured one at a time with one transition per measurement.
t
w
INPUT
V
M
V
M
SA00437
Figure 1. Pulse duration
3V
INPUT
OUTPUT
OUTPUT
t
t
V
PLH
PHL
M
V
V
V
M
V
M
V
M
0V
V
V
V
V
SA00438
OH
OL
OH
OL
t
PHL
M
t
PLH
M
All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10MHz, Z
= 50Ω, tr ≤ 2.5ns, tf ≤ 2.5ns.
O
Figure 2. Propagation delay times;
inverting and non-inverting outputs
3V
0V
TIMING INPUT
DATA INPUT
OUTPUT
CONTROL
OUTPUT
WAVEFORM 1
S1 AT 7V
OUTPUT
WAVEFORM 2
S1 AT OPEN
Waveform 1 is for an output with internal conditions such that the
output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the
output is high except when disabled by the output control.
74ABT16260
74ABTH16260
V
M
t
su
V
M
Figure 3. Setup and hold times
V
M
t
PZL
t
PZH
V
M
Figure 4. Enable and disable times;
low- and high-level enabling
t
h
V
M
t
PLZ
V
M
t
VOL + 0.3V
PHZ
VOH – 0.3V
3V
0V
3V
V
M
0V
SA00439
3V
0V
3.5V
V
OL
V
OH
≈0V
SA00440
TEST LOAD CIRCUIT
FROM OUTPUT UNDER TEST
(INCLUDES PROBE AND
JIG CAPACITANCE)
1998 Feb 10
CL = 50pF
500Ω
Load Circuit for Outputs
7V
500Ω
S1
GND
Figure 5. Test load circuit
8
OPEN
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7V
Open
SA00441
Page 9
Philips Semiconductors Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ABT16260
74ABTH16260
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1
1998 Feb 10
9
Page 10
Philips Semiconductors Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ABT16260
74ABTH16260
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1
1998 Feb 10
10
Page 11
Philips Semiconductors Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
NOTES
74ABT16260
74ABTH16260
1998 Feb 10
11
Page 12
Philips Semiconductors Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74ABT16260
74ABTH16260
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-03339
1998 Feb 10
12
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