Datasheet 74ABTH16841ADL, 74ABTH16841ADGG, 74ABT16841ADL, 74ABT16841ADGG Datasheet (Philips)

INTEGRATED CIRCUITS

74ABT16841A
74ABTH16841A

20-bit bus interface latch (3-State)

Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook

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1998 Feb 27

Philips Semiconductors Product specification

Quiescent supply current

20-bit bus interface latch (3-State)

FEA TURES

•High speed parallel latches

•Live insertion/extraction permitted

•Extra data width for wide address/data paths or buses carrying

parity

•Power-up 3-State

•74ABTH16841A incorporates bus-hold data inputs which

eliminate the need for external pull-up resistors to hold unused
inputs

•Power-up reset

•Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per Jedec Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

QUICK REFERENCE DATA

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

I

CCL

IN

Propagation delay
nDx to nQx

Input capacitance VI = 0V or V
Output capacitance VO = 0V or VCC; 3-State 7 pF

pp

74ABT16841A

74ABTH16841A

DESCRIPTION

The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.

The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.

Data appears on the bus when the Output Enable (nOE
When nOE

Two options are available, 74ABT16841A which does not have the
bus-hold feature and 74ABTH16841A which incorporates the
bus-hold feature.

is High the output is in the High-impedance state.

CONDITIONS

T

= 25°C; GND = 0V

amb

CL = 50pF; VCC = 5V

CC

Outputs disabled; VCC = 5.5V 500 µA

Outputs LOW; VCC = 5.5V 10 mA

) is Low.

TYPICAL UNIT

3.1

2.2
4 pF

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16841A DL BT16841A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16841A DGG BT16841A DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16841A DL BH16841A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16841A DGG BH16841A DGG SOT364-1

PIN DESCRIPTION

55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30

2, 3, 5, 6, 8, 9, 10, 12, 13, 14

15, 16, 17, 19, 20, 21, 23, 24, 26, 27

4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)

1998 Feb 27 853-1797 19025

PIN NUMBER SYMBOL FUNCTION

1D0 – 1D9
2D0 – 2D9

1Q0 – 1Q9
2Q0 – 2Q9

1, 28 1OE, 2OE Output enable inputs (active-Low)

56, 29 1LE, 2LE Latch enable inputs (active rising edge)

7, 22, 35, 50 V

CC

2

Data inputs

Data outputs

Positive supply voltage

Philips Semiconductors Product specification

OPERATING MODE

20-bit bus interface latch (3-State)

PIN CONFIGURATION

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

SA00076

1LE
1D0
1D1
GND
1D2
1D3
V

CC

1D4
1D5
1D6
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
V

CC

2D6
2D7
GND
2D8

2D9

2LE

1D8 1D9

1Q8 1Q9

2D8 2D9

2Q8 2Q9

1OE

GND

V

GND

GND

V

GND

2OE

LOGIC SYMBOL

55 54 52 51 49 48 47 45 44 43

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7

56

1LE

1

1OE

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

2 3 5 6 8 9 10 12 13 14

42 41 40 38 37 36 34 33 31 30

2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7

29

2LE

28

2OE

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

1Q0
1Q1

1Q2
1Q3

CC

1Q4
1Q5
1Q6

1Q7
1Q8
1Q9
2Q0
2Q1
2Q2

2Q3
2Q4

2Q5

CC

2Q6
2Q7

2Q8
2Q9

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

74ABT16841A

74ABTH16841A

LOGIC SYMBOL (IEEE/IEC)

1

1OE

56

1LE

28

2OE

29

2LE

55

1D0

54

1D1

52

1D2

51

1D3

49

1D4

48

1D5

47

1D6

45

1D7

44

1D8

43

1D9

42

2D0

41

2D1

40

2D2

38

2D3

37

2D4

36

2D5

34

2D6

33

2D7

31

2D8

30

2D9

FUNCTION TABLE

INPUTS OUTPUTS

nOE nLE nDx nQ0 – nQ9

L

H

L
L

L

H X X Z High impedance

L L X NC Hold

H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low LE

transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low LE

transition
↓ = High-to-Low LE transition
NC= No change
X = Don’t care
Z = High impedance “off” state

L

H

H

↓

l

↓

h

1D

3D

EN2
C1
EN4
C3

2 ∇

4 ∇

L

H

L

H

2

1Q0

3

1Q1

5

1Q2

6

1Q3

8

1Q4

9

1Q5

10

1Q6

12

1Q7

13

1Q8

14

1Q9

15

2Q0

16

2Q1

17

2Q2

19

2Q3

20

2Q4

21

2Q5

23

2Q6

24

2Q7

26

2Q8

27

2Q9

SH00081

Transparent

Latched

1998 Feb 27

15 16 17 19 20 21 23 24 26 27

SH00023

3

Philips Semiconductors Product specification

I

DC output current

mA

SYMBOL

PARAMETER

UNIT

20-bit bus interface latch (3-State)

74ABT16841A

74ABTH16841A

LOGIC DIAGRAM

nD0

D

LQ

nLE

nOE

ABSOLUTE MAXIMUM RA TINGS

SYMBOL

V

I

V

I

OK

V

OUT

OUT

T

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC supply voltage –0.5 to +7.0 V

CC

DC input diode current VI < 0 –18 mA

IK

DC input voltage

I

DC output diode current VO < 0 –50 mA
DC output voltage

Storage temperature range –65 to 150 °C

stg

nD1

D

LQ LQ LQ LQ LQ LQ LQ LQ LQ

nQ0

nQ1

nD2

nD3

D

D

nQ2

nQ3

nD4

nD5

D

D

nQ4

nQ5

nD6

nD7

D

D

nQ6

nQ7

nD8

nD9

D

D

nQ8

SH00024

1, 2

PARAMETER CONDITIONS RATING UNIT

3

3

Output in Off or High state –0.5 to +5.5 V

–1.2 to +7.0 V

Output in Low state 128

p

Output in High state –64

nQ9

RECOMMENDED OPERATING CONDITIONS

1998 Feb 27

LIMITS

Min Max

V

V

V

V

I

OH

I

OL

DC supply voltage 4.5 5.5 V

CC

Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level Input voltage 0.8 V

IL

High-level output current –32 mA
Low-level output current 64 mA

CC

V

∆t/∆v Input transition rise or fall rate 0 5 ns/V

T

amb

Operating free-air temperature range –40 +85 °C

4

Philips Semiconductors Product specification

In ut leakage current

µ

I

74ABT16841A

CC I CC

µ

I

t

5

74ABTH16841A

Data ins

5

B

6

74ABTH16841A

20-bit bus interface latch (3-State)

74ABTH16841A

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

V

V

V

V

Input clamp voltage VCC = 4.5V; IIK = -18mA –0.9 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = -3mA; VI = VIL or V

High-level output voltage

OH

VCC = 5.0V; IOH = -3mA; VI = VIL or V
VCC = 4.5V; IOH = -32mA; VI = VIL or V

Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

OL

Power-up output voltage

RST

I

p

3

VCC = 5.5V; IO = 1mA; VI = GND or V
V

= 5.5V; V

= V

or GND ±0.01 ±1 ±1.0

IH
IH

IH

IH

CC

VCC = 5.5V; VI = VCC or GND Control pins ±0.01 ±1 ±1 µA

I

nput leakage curren

I

VCC = 5.5V; VI = V
VCC = 5.5V; VI = 0

CC

p

VCC = 4.5V; VI = 0.8V 35 35

I

HOLD

us Hold current inputs

VCC = 4.5V; VI = 2.0V –75 –75
VCC = 5.5V; VI = 0 to 5.5V ±800

I

OFF

I

PU/PD

I

OZH

I

OZL

I

CEX

I

CCH

I

CCL

I

CCZ

∆I

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
Power-up/down 3-State

output current

4

3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V

I

O

Output current

1

Quiescent supply current

Additional supply current per

CC

input pin

2

VCC = 2.1V; VO = 0.5V; VI = GND or VCC;
V

= Don’t care

OE

IH
IH

CC

VCC = 5.5V; VO = 2.5V –50 –70 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or V
VCC = 5.5V; Outputs Low, VI = GND or V
VCC = 5.5V; Outputs 3-State; VI = GND or V

CC

CC

CC

VCC = 5.5V; one input at 3.4V, other inputs at
V

or GND

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V
transition time of up to 100µsec is permitted.

5. Unused pins at V

6. This is the bus hold overdrive current required to force the input to the opposite logic state.

or GND.

CC

between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a

CC

T

= +25°C

amb

Min Typ Max Min Max

2.5 2.9 2.5 V

3.0 3.4 3.0 V

2.0 2.4 2.0 V

0.42 0.55 0.55 V

0.13 0.55 0.55 V

0.01 1 1 µA
–2 –3 –5 µA

±5.0 ±50 ±50 µA

5.0 10 10 µA

–5.0 –10 –10 µA

5.0 50 50 µA

0.5 1 1 mA
10 19 19 mA

0.5 1 1 mA

0.2 1 1 mA

74ABT16841A

T

= -40°C

amb

to +85°C

UNIT

µA

A

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

1998 Feb 27

Propagation delay
nDx to nQx

Propagation delay
nLE to nQx

Output enable time
to High and Low level

Output disable time
from High and Low level

LIMITS

T

= +25oC

amb

VCC = +5.0V

T

= -40 to +85oC

amb

VCC = +5.0V ±0.5V

UNIT

MIN TYP MAX MIN MAX

2

1
4

5
4

5

1.1

1.5

1.5

1.0

1.2

1.2

1.8

1.5

3.1

2.2

2.5

2.1

2.4

2.2

3.0

2.5

4.1

3.1

3.3

2.8

3.2

2.9

4.0

3.2

1.1

1.5

1.5

1.0

1.2

1.2

1.8

1.5

4.9

3.6

3.7

3.1

4.0

3.6

4.9

3.7

ns

ns

ns

ns

5

Philips Semiconductors Product specification

20-bit bus interface latch (3-State)

74ABT16841A

74ABTH16841A

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

T

= +25oC

SYMBOL PARAMETER WAVEFORM

amb

VCC = +5.0V

Min Typ Min Max

ts(H)
ts(L)

th(H)
th(L)

Setup time, High or Low
nDx to nLE

Hold time, High or Low
nDx to nLE

3

3

2.0

1.0

2.0

2.0

1.0

0.4

–0.3
–0.7

tw(H) nLE pulse width High 1 2.9 1.9 2.9 ns

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

3.0V or V

CC

whichever
is less

0V

V

OH

V

OL

SA00078

nQx

nLE

V

M

tw(H)

t

PHL

V

M

V

M

V

M

t

PLH

V

M

Waveform 1. Propagation Delay, Latch Enable Input to

Output, and Enable Pulse Width

nOE

V

nQx

Waveform 4. 3–State Output Enable Time to High Level

and Output Disable Time from High Level

M

t

T

VCC = +5.0V ±0.5V

PZH

= -40 to +85oC

amb

2.0

1.0

2.0

2.0

V

M

t

PHZ

V

M

V

OH

V

Y

UNIT

ns

ns

3.0V or V
whichever
is less

0V

0V

SH00007

CC

nDx INPUT

nQx OUTPUT

V

M

t

PLH

V

M

t

PHL

V

M

V

M

Waveform 2. Propagation Delay for Data to Outputs

nDx

nLE

V

M

M

ts(H)

NOTE: The shaded areas indicate when the input is

permitted to change for predictable output performance.

(H)

t

h

V

M

V

V

M

M

t

(L)

s

V

M

V

Waveform 3. Data Setup and Hold Times

t

h

(L)

3.0V or V
whichever
is less

0V

3.0V or V
whichever
is less

0V

SA00079

3.0V or V
whichever
is less

0V

3.0V or V
whichever
is less

0V

SA00080

3.0V or V

CC

nOE

CC

nQx

CC

V

M

t

PZL

V

M

t

PLZ

V

M

whichever
is less

0V

3.0V or V

CC

V

X

0V

V

OL

SH00008

Waveform 5. 3–State Output Enable Time to Low Level and

Output Disable Time from Low Level

CC

CC

1998 Feb 27

6

Philips Semiconductors Product specification

20-bit bus interface latch (3-State)

TEST CIRCUIT AND WAVEFORM

V

CC

V

PULSE

GENERATOR

IN

R

D.U.T.

T

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t
t

PLZ
PZL

closed
closed

All other open

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

V

OUT

C

L

OUT

74ABT16841A

74ABTH16841A

t

90%

7.0V
NEGATIVE

R

L

R

L

PULSE

POSITIVE
PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

W

V

M

(tF)

(tR)t

V

M

t

W

VM = 1.5V

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

of

Amplitude Rep. Rate t

74ABT/H16 3.0V 1MHz 500ns 2.5ns 2.5ns

W

90%

10%

t

R

t

TLH

THL

AMP (V)

0V

(tR)

(tF)

AMP (V)

0V

t

F

SA00018

1998 Feb 27

7

Philips Semiconductors Product specification

20-bit bus interface latch (3-State)

74ABT16841A

74ABTH16841A

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

1998 Feb 27

8

Philips Semiconductors Product specification

20-bit bus interface latch (3-State)

74ABT16841A

74ABTH16841A

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

1998 Feb 27

9

Philips Semiconductors Product specification

20-bit bus interface latch (3-State)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74ABT16841A

74ABTH16841A

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 05-96
Document order number: 9397-750-03506

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

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