Datasheet 74ABTH16821ADL, 74ABTH16821ADGG, 74ABT16821ADL, 74ABT16821ADGG Datasheet (Philips)

INTEGRATED CIRCUITS

74ABT16821A
74ABTH16821A

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook

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1998 Feb 27

Philips Semiconductors Product specification

Quiescent supply current

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

FEA TURES

•20-bit positive-edge triggered register

•Multiple V

•Live insertion/extraction permitted

•Power-up reset

•Power-up 3-State

•74ABTH16821A incorporates bus-hold data inputs which

eliminate the need for external pull-up resistors to hold unused
inputs

•Output capability: +64mA/-32mA

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

and GND pins minimize switching noise

CC

74ABT16821A

74ABTH16821A

DESCRIPTION

The 74ABT16821A high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.

The 74ABT16821A has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE

Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.

The active Low Output Enable (nOE
independent of the register operation. When nOE
the register appears at the outputs. When nOE
are in high impedance “off” state, which means they will neither drive
nor load the bus.

Two options are available, 74ABT16821A which does not have the
bus-hold feature and 74ABTH16821A which incorporates the
bus-hold feature.

) control gates.

) controls all ten 3-State buffers

is Low, the data in

is High, the outputs

QUICK REFERENCE DATA

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

I

CCL

IN

Propagation delay
nCP to nQx

Input capacitance VI = 0V or V
Output capacitance VO = 0V or VCC; 3-State 7 pF

pp

CONDITIONS

T

= 25°C; GND = 0V

amb

CL = 50pF; VCC = 5V

CC

Outputs disabled; VCC = 5.5V 500 µA

Outputs LOW; VCC = 5.5V 10 mA

TYPICAL UNIT

2.4

2.0
3 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16821A DL BT16821A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16821A DGG BT16821A DGG SOT364-1
56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16821A DL BH16821A DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16821A DGG BH16821A DGG SOT364-1

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

55, 54, 52, 51, 49, 48, 47, 45, 44, 43,

42, 41, 40, 38, 37, 36, 34, 33, 31, 30

2, 3, 5, 6, 8, 9, 10, 12, 13, 14,

15, 16, 17, 19, 20, 21, 23, 24, 26, 27

1, 28 1OE, 2OE Output enable inputs (active-Low)

56, 29 1CP, 2CP Clock pulse inputs (active rising edge)

4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)

7, 22, 35, 50 V

1D0 - 1D9
2D0 - 2D9

1Q0 - 1Q9
2Q0 - 2Q9

CC

Data inputs

Data outputs

Positive supply voltage

ns

1998 Feb 27 853-1796 19026

2

Philips Semiconductors Product specification

INTERNAL

OPERATING

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

PIN CONFIGURATION

GND

GND

GND

GND

LOGIC SYMBOL

56 54 52 51 49 48 47 45 44 43

1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7

1CP

56

1OE

1

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

2 3 5 6 8 9 10 12 13 14

42 41 40 38 37 36 34 33 31 30

2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7

29

2CP

28

2OE

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

1
2

1Q0

3

1Q1

4
5

1Q2

6

1Q3

7

V

CC

8

1Q4

9

1Q5

10

1Q6

11
12

1Q7

13

1Q8

14

1Q9

15

2Q0

16

2Q1

17

2Q2

18
19

2Q3

20

2Q4

21

2Q5

22

V

CC

23

2Q6

24

2Q7

25
26

2Q8

27

2Q9

28 29

2OE

561OE
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30

SH00001

1CP
1D0
1D1
GND
1D2
1D3
V

CC

1D4
1D5
1D6
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
V

CC

2D6
2D7
GND
2D8
2D9
2CP

1D8 1D9

1Q8 1Q9

2D8 2D9

2Q8 2Q9

74ABT16821A

74ABTH16821A

LOGIC SYMBOL (IEEE/IEC)

1

1OE

56

1CP

28

2OE

29

2CP

55

1D0

54

1D1

52

1D2

51

1D3

49

1D4

48

1D5

47

1D6

45

1D7

44

1D8

43

1D9

42

2D0

41

2D1

40

2D2

38

2D3

37

2D4

36

2D5

34

2D6

33

2D7

31

2D8

30

2D9

FUNCTION TABLE

INPUTS

nOE nCP nDx

L

↑

L
L ↑ X NC NC Hold

H
H

H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High

clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High

clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low to High clock transition

= Not a Low-to-High clock transition

↑

l

↑

h

↑

X

Dn

↑

EN2

C1

EN4

C3

1D

3D

INTERNAL
REGISTER

L

H

NC

Dn

2 ∇

4 ∇

OUTPUTS
nQ0 - nQ9

L

H

Z
Z

2

1Q0

3

1Q1

5

1Q2

6

1Q3

8

1Q4

9

1Q5

10

1Q6

12

1Q7

13

1Q8

14

1Q9

15

2Q0

16

2Q1

17

2Q2

19

2Q3

20

2Q4

21

2Q5

23

2Q6

24

2Q7

26

2Q8

27

2Q9

SH00003

OPERATING

MODE

Load and read

register

Disable
outputs

1998 Feb 27

15 16 17 19 20 21 23 24 26 27

SH00002

3

Philips Semiconductors Product specification

I

DC out ut current

mA

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

LOGIC DIAGRAM

nD0

D

CP Q

nCP

nOE

nQ0

nD1

D

CP Q

nQ1

nD2

D

CP Q

nD3

D

CPQ

nQ2

nQ3

nD4

D

CP Q

nQ4

nD5

D

CPQ

nQ5

nD6

D

CP Q

nQ6

74ABT16821A

74ABTH16821A

nD7

D

CPQ

nD8

D

CPQ

nQ7

nQ8

nD9

D

CPQ

nQ9

SH00004

ABSOLUTE MAXIMUM RA TINGS

SYMBOL

V

CC

I

IK

V

I

I

OK

V

OUT

OUT

T

stg

DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage

p

Storage temperature range –65 to 150 °C

PARAMETER CONDITIONS RATING UNIT

3

3

1, 2

–1.2 to +7.0 V

Output in Off or High state –0.5 to +5.5 V

Output in Low state 128

Output in High state –64

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

MIN MAX

V

CC

V

V

V

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 10 ns/V

T

amb

DC supply voltage 4.5 5.5 V
Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level Input voltage 0.8 V

IL

High-level output current –32 mA
Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

CC

V

1998 Feb 27

4

Philips Semiconductors Product specification

IIIn ut leakage current

V

CC

V

I

V

CC

GND

±0.01

±1.0

±1.0

µA

74ABTH16821A

Data pins

5

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS T

V

V

V

V

Input clamp voltage VCC = 4.5V; IIK = -18mA –0.9 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = -3mA; VI = VIL or V

High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or V

OH

VCC = 4.5V; IOH = -32mA; VI = VIL or V

Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V

OL

Power-up output voltage

RST

p

3

VCC = 5.5V; IO = 1mA; VI = GND or V

=

;

= 5.5V

=

=

or

IH

IH

IH

IH

CC

VCC = 5.5V; VI = VCC or GND Control pins ±0.01 ±1 ±1 µA

Input leakage current

I

I

74ABTH16821A

VCC = 5.5V; VI = V
VCC = 5.5V; VI = 0

CC

p

VCC = 4.5V; VI = 0.8V 35 35

I

HOLD

Bus Hold current inputs
74ABTH16821A

VCC = 4.5V; VI = 2.0V –75 –75
VCC = 5.5V; VI = 0 to 5.5V ±800

I

OFF

I

PU/PD

I

OZH

I

OZL

I

CEX

I

CCH

I

CCL

I

CCZ

∆I

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
Power-up/down 3-State

output current

4

3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output High leakage

current

I

O

Output current

1

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

Additional supply current

CC

per input pin

2

VCC = 2.1V; VO = 0.5V; VI = GND or VCC;
VOE = Don’t care

IH

IH

VCC = 5.5V; VO = 5.5V; VI = GND or V

CC

VCC = 5.5V; VO = 2.5V –50 –90 –180 –50 –180 mA
VCC = 5.5V; Outputs High, VI = GND or V

VCC = 5.5V; Outputs 3-State; VI = GND or V

CC

CC

CC

VCC = 5.5V; one input at 3.4V, other inputs at
VCC or GND

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V
time of up to 100µsec is permitted.

between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V a transition

CC

5. This is the bus hold overdrive current required to force the input to the opposite logic state.

= +25°C

amb

Min Typ Max Min Max

2.5 2.9 2.5 V

3.0 3.4 3.0 V

2.0 2.4 2.0 V

0.36 0.55 0.55 V

0.13 0.55 0.55 V

0.01 1 1 µA

±5.0 ±50 ±50 µA

1.0 10 10 µA

–1.0 –10 –10 µA

5.0 50 50 µA

0.5 1 1 mA

0.5 1 1 mA

0.25 1.5 1.5 mA

74ABTH16821A

LIMITS

–1 –3 –5 µA

10 19 19 mA

74ABT16821A

T

= -40°C

amb

to +85°C

UNIT

µA

1998 Feb 27

5

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

ts(H)
ts(L)

th(H)
th(L)

tw(H)
tw(L)

Maximum clock frequency 1 160 250 160 MHz
Propagation delay

nCP to nQx
Output enable time

to High and Low level
Output disable time

from High and Low level

Setup time, High or Low
nDx to nCP

Hold time, High or Low
nDx to nCP

nCP pulse width
High or Low

1
3

4
3

4

2

2

1

74ABT16821A

74ABTH16821A

LIMITS

T

= -40 to

T

= +25oC

amb

VCC = +5.0V

MIN TYP MAX MIN MAX

1.3

1.1

1.4

1.2

1.6

1.3

2.4

2.0

2.5

2.3

3.2

2.3

3.3

2.6

3.3

3.0

4.1

3.1

LIMITS

T

= +25oC

amb

VCC = +5.0V

MIN TYP MIN MAX

1.8

1.8

1.0

1.0

2.5

2.5

1.2

–0.9

0.8

–1.0

0.8

1.0

amb

+85oC

V

= +5.0V ±0.5V

CC

1.3

1.1

1.4

1.2

1.6

1.3

T

= -40 to +85oC

amb

VCC = +5.0V ±0.5V

1.8

1.8

1.0

1.0

2.5

2.5

3.7

3.0

4.1

3.7

4.8

3.3

UNIT

ns

ns

ns

UNIT

ns

ns

ns

AC WAVEFORMS

1/f

MAX

nCP

nQx

nDx

CP

V

M

tw(H)

t

PH

V

M

L

tw(L)

V

M

V

M

t

PLH

V

M

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock frequency

V

V

M

M

th(H)ts(H)

V

M

V

V

M

M

th(L)ts(L)

V

M

Waveform 2. Data Setup and Hold Times

3.0V or V
whichever
is less

0V

V

OH

V

OL

SH00005

3.0V or V
whichever
is less

0V

3.0V or V
whichever
is less

0V

SH00006

3.0V or V

CC

nOE

nQx

V

M

t

PZH

V

M

t

PHZ

V

OH

V

V

M

Y

whichever
is less

0V

0V

SH00007

CC

Waveform 3. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

3.0V or V

CC

CC

CC

nOE

nQx

V

M

t

PZL

V

M

t

PLZ

V

M

whichever
is less

0V

3.0V or V

CC

V

X

0V

V

OL

SH00008

Waveform 4. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

1998 Feb 27

6

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

TEST CIRCUIT AND WAVEFORM

V

CC

PULSE

GENERATOR

V

IN

R

D.U.T.

T

V

OUT

C

L

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t
t

PLZ
PZL

closed
closed

All other open

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.
C

= Load capacitance includes jig and probe capacitance;

L

see AC CHARACTERISTICS for value.

RT = Termination resistance should be equal to Z

pulse generators.

R

R

OUT

of

74ABT16821A

74ABTH16821A

t

90%

7.0V
NEGATIVE

L

L

PULSE

POSITIVE
PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

W

V

M

(tF)

(tR)t

V

M

t

W

VM = 1.5V

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

Amplitude Rep. Rate t

W

74ABT/H16 3.0V 1MHz 500ns 2.5ns 2.5ns

90%

10%

t

R

t

TLH

THL

AMP (V)

0V

(tR)

(tF)

AMP (V)

0V

t

F

SA00018

1998 Feb 27

7

Philips Semiconductors Preliminary specification

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

74ABT16821A

74ABTH16821A

1998 Feb 27

8

Philips Semiconductors Preliminary specification

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

74ABT16821A

74ABTH16821A

1998 Feb 27

9

Philips Semiconductors Product specification

20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74ABT16821A

74ABTH16821A

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 05-96
Document order number: 9397-750-03501

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

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