Datasheet 74ABTH16374BDL, 74ABTH16374BDGG, 74ABT16374BDL, 74ABT16374BDGG Datasheet (Philips)

INTEGRATED CIRCUITS

74ABT16374B
74ABTH16374B

16-bit D-type flip-flop;
positive-edge trigger (3-State)

Product specification
Supersedes data of 1995 Sep 28
IC23 Data Handbook

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1998 Feb 27

Philips Semiconductors Product specification

Quiescent su ly current

16-bit D-type flip-flop; positive-edge trigger
(3-State)

FEA TURES

•Two 8-bit positive edge triggered registers

•Live insertion/extraction permitted

•Power-up 3-State

•Power-up reset

•Multiple V

and GND pins minimize switching noise

CC

•3-State output buffers

•74ABTH16373B incorporates bus-hold data inputs which

eliminate the need for external pull-up resistors to hold unused
inputs

•Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

•Output capability: +64mA/–32mA

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

DESCRIPTION

The 74ABT16374B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.

The 74ABT16374B has two 8-bit, edge triggered registers, with each
register coupled to eight 3-State output buffers. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE

Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-Low Output Enable (nOE
its register independent of the clock operation.

When nOE
register. When nOE is High, the outputs for that register are in the
High-impedance “OFF” state, which means they will neither drive
nor load the bus.

Two options are available, 74ABT16374B which does not have the
bus-hold feature and 74ABTH16374B which incorporates the
bus-hold feature.

) control gates.

is Low, the stored data appears at the outputs for that

74ABT16374B

74ABTH16374B

) controls all eight 3-State buffers for

QUICK REFERENCE DATA

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

I

CCL

Propagation delay
nCP to nQx

Input capacitance VI = 0V or V

IN

Output capacitance VO = 0V or VCC; 3-State 7 pF

pp

CL = 50pF; VCC = 5V

Outputs disabled; VCC = 5.5V 500 µA
Outputs Low; VCC = 5.5V 8 mA

CONDITIONS

T

= 25°C; GND = 0V

amb

CC

TYPICAL UNIT

2.6

2.2
4 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

48-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16374B DL BT16374B DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16374B DGG BT16374B DGG SOT362-1
48-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16374B DL BH16374B DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16374B DGG BH16374B DGG SOT362-1

ns

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26

2, 3, 5, 6, 8, 9, 11, 12

13, 14, 16, 17, 19, 20, 22, 23

4, 10, 15, 21, 28, 34, 39, 45 GND Ground (0V)

1998 Feb 27 853-1752 19027

1D0 – 1D7
2D0 – 2D7

1Q0 – 1Q7
2Q0 – 2Q7

1, 24 1OE, 2OE

48, 25 1CP, 2CP

7, 18, 31, 42 V

CC

Data inputs

Data outputs

Output enable
inputs (active-Low)

Clock pulse inputs
(active rising edge)

Positive supply
voltage

LOGIC SYMBOL

48

25
24

2

1

47 46 44 43

1D0 1D1 1D2 1D3

1CP
1OE

1Q0 1Q1 1Q2651Q3

32

36 35 33 32

2D02D21 2D2 2D3

2CP
2OE

2Q0 2Q1 2Q2 2Q3

1413 1716

41 40 38 37

1D4 1D5 1D6 1D7

1Q4 1Q5 1Q6

30 29 27 26

2D4 2D5 2D6 2D7

2Q4 2Q5 2Q6 2Q7

98

2019 2322

SH00078

1Q7

1211

Philips Semiconductors Product specification

16-bit D-type flip-flop; positive-edge trigger
(3-State)

LOGIC SYMBOL (IEEE/IEC)

1OE

1CP

2OE

2CP

1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0

2D1
2D2
2D3
2D4
2D5
2D6
2D7

1
48
24
25

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27

1EN

2EN

1D

2D

C1

C2

1 ∇

2 ∇

2
3
5
6
8

9
11
12
13
14
16
17
19
20
22
2326

SH00077

1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0

2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7

PIN CONFIGURATION

1

1OE

2

1Q0

1Q1

3

GND

4

1Q2

5
6

1Q3

7

V

CC

8

1Q4
1Q5

9

GND

10

1Q6

11

1Q7

12

2Q0

13

2Q1

14

GND

15
16

2Q2
2Q3

17
18

V

CC

2Q4

19
20

2Q5

21

GND

22

2Q6

23

2Q7

24

2OE

74ABT16374B

74ABTH16374B

48

1CP

47

1D0
1D1

46

GND

45

1D2

44
43

1D3

42

V

CC

41

1D4
1D5

40

GND

39

1D6

38

1D7

37

2D0

36

2D1

35

GND

34
33

2D2
2D3

32
31

V

CC

2D4

30
29

2D5

28

GND

27

2D6

26

2D7

25

2CP

SA00326

LOGIC DIAGRAM

nD0

nCP

nOE

D

CP Q

nQ0

nD1

nD2

D

CP Q

nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7

D

CP Q

nD3

D

CP Q

nD4

D

CP Q

nD5

D

CP Q

nD6

D

CP Q

nD7

D

CP Q

SA00327

1998 Feb 27

3

Philips Semiconductors Product specification

OPERATING MODE

I

DC output current

mA

SYMBOL

PARAMETER

UNIT

16-bit D-type flip-flop; positive-edge trigger
(3-State)

74ABT16374B

74ABTH16374B

FUNCTION TABLE

INPUTS

nOE nCP nDx

L
L

L ↑ X NC NC Hold

H
H

H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low E transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition

= Not a Low-to-High clock transition

↑

↑
↑

↑
↑

l

h

X

nDx

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

CC

I

IK

V

I

OK

V

OUT

OUT

T

stg

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC supply voltage –0.5 to +7.0 V
DC input diode current VI < 0 –18 mA
DC input voltage

I

DC output diode current VO < 0 –50 mA
DC output voltage

Storage temperature range –65 to 150 °C

PARAMETER CONDITIONS RATING UNIT

3

3

p

INTERNAL
REGISTER

L
H

NC

nDx

1, 2

OUTPUTS

nQ0 – nQ7

L

H

Z
Z

output in Off or High state –0.5 to +5.5 V

output in Low state 128

output in High state –64

Load and read register

Disable outputs

–1.2 to +7.0 V

RECOMMENDED OPERATING CONDITIONS

1998 Feb 27

LIMITS

MIN MAX

V

CC

V

V

V

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 10 ns/V

T

amb

DC supply voltage 4.5 5.5 V
Input voltage 0 V

I

High-level input voltage 2.0 V

IH

Low-level Input voltage 0.8 V

IL

High-level output current –32 mA
Low-level output current 64 mA

Operating free-air temperature range –40 +85 °C

4

CC

V

Philips Semiconductors Product specification

I

t

I

g

V

V

V

GND

0.01±1±1µA

I

74ABT16374B

CC I CC

µ

In ut leakage current

Data pins

5

6

74ABTH16374B

16-bit D-type flip-flop; positive-edge trigger
(3-State)

DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS T

MIN TYP MAX MIN MAX

V

V

OH

V

OL

V

RST

I

Input clamp voltage VCC = 4.5V; IIK = –18mA –0.9 –1.2 –1.2 V

IK

VCC = 4.5V; IOH = –3mA; VI = VIL or V

High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or V

VCC = 4.5V; IOH = –32mA; VI = VIL or V
Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or V
Power-up output voltage

I

nput leakage curren

3

VCC = 5.5V; IO = 1mA; VI = GND or V

;

= 5.5V;

CC

=

I

CC

VCC = 5.5V; VI = VCC or

I

p

74ABTH16374B VCC = 5.5V; VI = V

GND

CC

VCC = 5.5V; VI = 0

or

IH
IH

IH

IH

CC

Control pins ±0.01 ±1 ±1

p

VCC = 4.5V; VI = 0.8V 50 50

I

HOLD

Bus Hold current inputs
74ABTH16374B

VCC = 4.5V; VI = 2.0V –75 –75

VCC = 5.5V; VI = 0 to 5.5V ±800

I

OFF

I

PU/PD

I

OZH

I

OZL

I

CEX

I

I

CCH

I

CCL

I

CCZ

∆I

∆I

O

CC

CC

Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA
Power-up/down 3-State

output current

4

3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or V
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or V
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or V
Output current

1

Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or V

VCC = 2.1V; VO = 0.5V;

VI = GND or VCC; VOE = GND

IH
IH

CC

VCC = 5.5V; VO = 2.5V –50 –70 –180 –50 –180 mA

VCC = 5.5V; Outputs High, VI = GND or V

CC
CC

VCC = 5.5V; Outputs 3-State;

Additional supply current
per input pin

2

74ABT16374B
Additional supply current

per input pin

2

74ABTH16374B

VI = GND or V

VCC = 5.5V; one input at 3.4V, other inputs at

V

or GND

CC

VCC = 5.5V; one input at 3.4V, other inputs at

VCC or GND

CC

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any V
transition time of up to 100µsec is permitted.

5. Unused pins at V

6. This is the bus hold overdrive current required to force the input to the opposite logic state.

or GND.

CC

between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a

CC

= +25°C

amb

2.5 2.9 2.5

3.0 3.4 3.0

2.0 2.4 2.0

0.42 0.55 0.55 V

0.13 0.55 0.55 V

0.01 1 1
–1 –3 –5

±5.0 ±50 ±50 µA

0.5 10 10 µA

–0.5 –10 –10 µA

5.0 50 50 µA

0.5 2 2 mA
8 19 19 mA

0.5 2 2 mA

5 100 100 µA

0.5 1.5 1.5 mA

74ABTH16374B

LIMITS

74ABT16374B

T

= –40°C

amb

to +85°C

UNIT

V

µA

µA

1998 Feb 27

5

Philips Semiconductors Product specification

16-bit D-type flip-flop; positive-edge trigger
(3-State)

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

SYMBOL PARAMETER WAVEFORM

ts(H)
t

(L)

s

th(H)
th(L)

tw(H)
tw(L)

Maximum clock frequency 1 180 260 MHz
Propagation delay

nCP to nQx
Output enable time

to High and Low level
Output disable time

from High and Low level

Setup time, High or Low
nDx to nCP

Hold time, High or Low
nDx to nCP

nCP pulse width
High or Low

1
3

4
3

4

2

2

1

74ABT16374B

74ABTH16374B

LIMITS

T

= +25°C

amb

VCC = +5.0V

MIN TYP MAX MIN MAX

1.7

1.4

1.3

1.3

1.9

1.7

2.6

2.2

2.4

2.3

3.1

2.6

T

= +25°C

amb

VCC = +5.0V

4.0

3.4

3.7

3.4

4.6

4.0

MIN TYP MIN

1.0

1.0

1.0

1.0

2.8

2.8

0.3

0.1

–0.1
–0.3

1.2

1.5

LIMITS

T

= –40 to +85°C

amb

VCC = +5.0V ±0.5V

1.7

1.4

1.3

1.3

1.9

1.7

T

= –40 to +85°C

amb

VCC = +5.0V ±0.5V

1.0

1.0

1.0

1.0

2.8

2.8

4.7

3.9

4.7

4.6

5.5

4.4

UNIT

ns

ns

ns

UNIT

ns

ns

ns

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

1/f

MAX

nCP

nQx

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

VM VM VM

tw(H) tw(L)

t

PHL

VM VM

t

PLH

SA00328

nDx

nCP

NOTE: The shaded areas indicate when the input is permitted to

change for predictable output performance.

V

V

M

M

t

(H) th(H) ts(L) th(L)

s

V

M

V

MVM

Waveform 2. Data Setup and Hold Times

V

M

SA00329

1998 Feb 27

6

Philips Semiconductors Product specification

16-bit D-type flip-flop; positive-edge trigger
(3-State)

OE

V

M

t

PZH

nQx

Waveform 3. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

TEST CIRCUIT AND WAVEFORM

V

PULSE

GENERATOR

IN

R

T

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t

PLZ

t

PZL

All other open

closed
closed

V

V

M

V

D.U.T.

CC

M

t

PHZ

V

OUT

V

OH

VOH –0.3V

0V

SH00079

7.0V

R

L

C

L

R

L

74ABT16374B

74ABTH16374B

OE

nQx

Waveform 4. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

90%

NEGATIVE
PULSE

POSITIVE
PULSE

10%

V

M

t

PZL

V

M

10% 10%

(tF)

t

THL

t

(tR)t

TLH

90% 90%

V

M

V

M

t

PLZ

V

M

t

W

V

M

V

M

t

W

90%

10%

VOL + 0.3V
V

t

TLH

THL

OL

SH00080

0V

(tR)

(tF)

0V

VM = 1.5V

Input Pulse Definition

AMP (V)

AMP (V)

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.
C

= Load capacitance includes jig and probe capacitance;

L

see AC CHARACTERISTICS for value.

RT = Termination resistance should be equal to Z

pulse generators.

1998 Feb 27

OUT

of

FAMILY

INPUT PULSE REQUIREMENTS

Amplitude Rep. Rate t

t

W

t

R

F

74ABT/H16 3.0V 1MHz 500ns 2.5ns 2.5ns

SA00018

7

Philips Semiconductors Product specification

Dual octal D-type flip-flop;
positive-edge trigger (3-State)

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1

74ABT16374B

74ABTH16374B

1998 Feb 27

8

Philips Semiconductors Product specification

Dual octal D-type flip-flop;
positive-edge trigger (3-State)

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1

74ABT16374B

74ABTH16374B

1998 Feb 27

9

Philips Semiconductors Product specification

16-bit D-type flip-flop; positive-edge trigger
(3-State)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74ABT16374B

74ABTH16374B

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 05-96
Document order number: 9397-750-03492

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yyyy mmm dd

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