Daewoo CP775 Service Manual

Service Manual

59 Cm STEREO Colour Television

CHASSIS : CP-775

MODEL :2594ST

Specifications

CRT 25” : A59EAK071X11 (PHILIPS)

System TF : PAL - B/G for West Europe, NTSC-3.58 / 4.43 (Play back)

Main Voltage 230V AC, 50Hz

Power Consumption Stand-by mode : 10 Watts

Normal operating mode : 25” = 75 Watts

Sound output 5 + 5 Watts, 10 % THD at RF 60 % mod. (1 ) Speaker 12W 4 ohm x 2 EA Antenna 75 ohm unbalanced input Impedance Tuning system VS( voltage synthesis ) tuning Tuner 3303KHC (TF, TA, TK, TI Model)

BAND I : CH2 - CH4 BAND III : CH5 - CH12 CABLE BAND : S1’ - S3’ , S1 - S20 HYPER BAND : S21 - S41 BAND IV, V : CH21 - CH69

DT2-IV17D (TU Model )

BAND IV, V : CH21 - CH69 Number of 70 programs program Aux. Terminal 21 pin EURO-SCART jack ( AV input, TV output, RGB input )

21 pin EURO-SCART jack ( AV input, S-VHS input ) RCA type AV input jack

Headphone jack (3.5 mm ) Remote controller R-28B03 or R-35D05 with 2 “AA” type batteries Teletext 8 pages memory TOP & FLOF

- West option :English, German/Dutch/Flemish, French, Italian, Spanish/Portuguese, Swedish/Finnish/Danish, Czech/Slovak

- East option : Polish, Czech/Slovak, Rumanian, Hungarian, Servo-croat, German/Dutch/Flemish, French, Italian

- Turkish option : Turkish, English, German/Dutch/Flemish, French, Italian, Spanish/Portuguese, Swedish/Finnish/Danish

- Cyrillic option: Russian, Lettish/Lithuanian, Estonian, Ukranian, Czech/Slovak, Servo-croat, English

OSD language -East,West,Turkish Version : English,French,German,Italian,Spanish

-Cyrillic Version : Russian, English, German

21 PIN EURO-SCART

PIN Signal Designation Matching Value

1 Audio Out(linked with 3) 0.5Vrms,lmp<1 (RF 60% MOD) 2 Audio In(linked with 6) 0.5Vrms,lmp>10 3 Audio Out(linked with 1) 0.5Vrms,lmp<1 (RF 60% MOD) 4 Audio Earth 5 Blue Earth 6 Audio in (linked with 2) 0.5Vrms,lmp>10 7 Blue in 0.7Vpp 3 ,lmp75 8 Slow(Function) Switching TV:0-2V,PERI:9.5-12V,lmp>10

9 Green Earth 10 NC 11 Green In 0.7Vpp 3 ,lmp75 12 NC 13 Red Earth 14 NC 15 Red In, C In 0.7Vpp 3 ,lmp75 16 Rapid(Blanking) switching Logic 0:0-0.4V,Logic 1:1-3V,Imp 75 17 Video Earth 18 Rapid Blanking Earth 19 Video Out 1Vpp 3 ,lmp75 20 Video In, Y In 1Vpp 3 ,lmp75 21 Common Earth

20 18 16 14 12 10 8 6 4 2

21 19 17 15 13 11 9 7 5 3 1

Safety Instruction

WARNING: Only competent service personnel may carry out work involving the testing or repair of

this equipment.

X-RAY RADIATION PRECAUTION

1. Excessive high voltage can produce potentially hazardous X-RAY RADIATION.To avoid such hazards, the high voltage must not exceed the specified limit. The nominal value of the high voltage of this receiver is 26 at max beam current. The high voltage must not, under any circumstances, exceed 29.5 (25"), 30 (28"). Each time a receiver requires servicing, the high voltage should be checked. It is important to use an accurate and reliable high voltage meter.

SAFETY PRECAUTION

1. Potentials of high voltage are present when this receiver is operating. Operation of the receiver outside the cabinet or with the back board removed involves a shock hazard from the receiver.

1) Servicing should not be attempted by anyone who is not thoroughly familiar with the precautions necessary when working on highvoltage equipment.

2) Discharge the high potential of the picture tube before handling the tube. The picture tube is highly evacuated and if broken, glass fragments will be violently expelled.

2. The only source of X-RAY Radiation in this TV receiver is the picture tube.For continued X-RAY RADIATION protection,the replacement tube must be exactly the same type tube as specified in the parts list.

2. If any Fuse in this TV receiver is blown, replace it with the FUSE specified in the Replacement Parts List.

3. When replacing a high wattage resistor(oxide metal film resistor)in circuit board, keep the resistor 10mm away from circuit board.

4. Keep wires away from high voltage or high temperature components.

5. This receiver must operate under AC230 volts, 50Hz. NEVER connect to DC supply or any other power or frequency.

PRODUCT SAFETY NOTICE

Many electrical and mechanical parts in this have special safety-related characteristics. These characteristics are often passed unnoticed by a visual inspection and the X-RAY RADIATION protection afforded by them cannot necessarily be obtained by using replacement components rated for higher voltage,wattage,etc. Replacement parts which have these special safety characteristics are identified in this manual and its supplements, electrical components having such features are

identified by designated symbol on the parts list. Before replacing any of these components, read the parts list in this manual carefully. The use of substitute replacement parts which do not have the same safety characteristics as specified in the parts list may create X-RAY Radiation.

SIF ADJUSTMENT

1. APPARATUS CONNECTION & PRESETTING

* CONNECTION

1) Connect H-out of LSW-480 to X-axis of the oscilloscope and V-out of LSW-480 to Y-axis of the oscilloscope.

2) Connect the sweep signal output to TP1.

3) Set ATTENUATOR of LSW-480 to 20dB.

4) Supply 12V D.C. voltage(B+) to TP3.

5) Supply 3V D.C. voltage(B+) to TP4.

6) Connect the test point of LSW-480 to TP2.

7) Adjust L109(AFT COIL) so that the P marker point is located on the reference level.

* PRESET

1) Oscilloscope Scaling a) Put the scale of X and Y of the oscilloscope

to D.C. level

b) Set the horizontal time display to X-Y.

c) Put the horizontal axis (x) to 1V / div. and the

vertical axis (Y) to 2V / div.

2) LSW-480 MARKER FREQ. SETTING

fp(n+1)

31.9fs33.4fc34.47

fp-2

36.9fp38.9

fs(n-1)

40.4

PIF SWEEP MAKER (LSW-480) GENERATOR

OUTPUT

TP1 (TUNER IF) TP3 (TUNER B+)

DC POWER SUPPLY

(+12V)

H-OUTPUT V-OUTPUT

FROM TP

TP2 (I603 #12) TP3 (I603 #3)

- Connection For SIF Adjustment -

OSCILLOSCOPE

X Y

DC POWER SUPPLY

(+3V)

P (38.9 MHZ)

IC Description

DW5255S*(Micro-controller & West/East Teletext Decoder)

(1) General Description

The TDA5255 contains a slicer for VPS and TTX, an accelerating acquisition hardware module, a display generator for “LEVEL 1” TTX data and a 8 bit u-controller running at 333 nsec cycle time. The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX acquisition , transfers data to/from the external memory interface and receives/transmits data via I2C and UART user interfaces. The Slicer combined with dedicated hardware stores TTX data in a VBI 1Kbyte buffer. The u-controller firmware does the total acquisition task ( hamming- and parity -checks, page search and evaluation of header control bits) once per field.

(2) Feature

•

Acquisition:

- feature selection via special function register

- simultaneous reception of TTX and VPS

- fixed framing code for VPS and TTX

- programmable framing code window for TTX

- Acquisition during VBI

- direct access to VBI RAM buffer

- Acquisition of packets x/26, x/27, 8/30 (firmware)

- assistance of all relevant checks (firmware)

- 1-bit framing-code error tolerance (switchable)

•

. Display:

- features selectable via special function register

- 50/60 Hz display

- level 1 serial attribute display pages

- blanking and contrast reduction output

- 8 direct addressable display pages

- 12 x 10 character matrix

- 96 character ROM (standard G0 character set)

- 143 national option characters for 11 languages

- 288 characters for X/26 display

- 64 block mosaic graphic characters

- 32 free addressable characters for OSD in expanded character ROM + 32 inside OSD box

- double height (TOP/BOTTOM)

- conceal/reveal

- transparent foreground/background -inside/outside of a box

- cursor (colour changes from foreground to background colour)

- flash (flash rate 1s)

- programmable horizontal und vertical sync delay

- hardware assisted fast display page erase

- full screen background colour in outer screen

•

Synchronization:

display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS) with startstop-oscillator or display synchronization to sandcastle or Horizontal Sync and Vertical Sync with external clock independent clock systems for acquisition, display and controller

•

Controller:

- 8 bit configuration

- 18 MHz internal clock

- 0.33 us instruction cycle

- eight 16-bit data pointer registers (DPTR)

- two 16-bit timers

- watchdog timer

- serial interface (UART)

- 256 bytes on-chip RAM

- 1 Kbyte on-chip extended RAM (access via MOVX)

- 8 Kbyte on-chip ACQ-buffer-RAM (access via MOVX)

- 6 channel 8-bit pulse width modulation unit

- 2 channel 14-bit pulse width modulation unit

- 4 multiplexed ADC inputs with 8-bit resolution

- one 8-bit I/O port with open drain output and optional I2C emulation

- two 8-bit multifunctional I/O ports

- one 4-bit port working as digital or analog inputs

- one 2-bit I/O port with optional address latch enable function

•

P-SDIP 52 package

•

5 V supply voltage

(3) Block Diagram

Pin Name Symbol Description

1 P3.1 SYS SECAM-L’ OUT for switching SAW filter L9461

- SECAM-L’ : H

- SECAM- L : L

2 P0.7/Open Drain BUSSTOP I2C BUS STOP IN for Computer controlled

alignment in Factory ( Active Low )

3 P0.6/Open Drain SDA Serial data IN/OUT for I2C 4 P0.5/Open Drain SCL Serial clock IN/OUT for I2C 5 P0.4/Open Drain OPTION #5 #6 Teletext

6 P0.3/Open Drain OPTION H H West Teletext

L H East Teletext

H L Turkish Teletext 7 P0.2/Open Drain OPTION #7 #8 #17 Tuning / Sound System 8 P0.1/Open Drain OPTION L H H B/G (2-G, NICAM)

H H H B/G, D/K (2-C, NICAM)

L L H I/I (NICAM)

H L H I (UHF only, NICAM)

H H L L/L’ B/G (2-C, NICAM)

L H L B/G L/L’ (2-C, NICAM) 9 P0.0/Open Drain LED LED drive OUT

- Stand-by mode : H

- Operating mode : L ( IR reception : pulse )

10 VSS VSS ground 11 VCC VCC Power Supply 12 XTAL1 OSCIN Input to inverting osc. Amplifier 13 XTAL2 OSCOUT Output of inverting osc. Amplifier 14 P4.0/ALE Not Used 15 RESET RST RESET IN (ACTIVE LOW) 16 P1.7/14BIT PWM VT TUNING VOLTAGE OUT 17 P1.6/14BIT PWM OPTION TUNING SYSTEM 18 P1.5/14BIT PWM F/SW F/SW IDENT IN for stopping OSD

display in RGB mode

- H : TV /AV mode

- L : RGB mode

19 P1.4/14BIT PWM OPTION ATS OPTION H : ON

L : OFF 20 P1.3/14BIT PWM MUTE AUDIO MUTE OUT 21 P1.2/14BIT PWM GND GND 22 P1.1/8BIT PWM Not Used 23 P1.0/8BIT PWM Not Used

Pin Name Symbol Description

24 VSSA VSSA Analog GND for Slicer 25 FIL3 FIL3 PLL Loop Filter I/O for Phase Shifting

26 FIL2 FIL2 PLL Loop Filter I/O for TTX Slicing 27 FIL1 FIL1 PLL Loop Filter I/O for VPS Slicing 28 VCCA VCCA Analog Supply for Slicer 29 IREF IREF Reference Current for Slicer PLLs 30 CVBS CVBS CVBS IN 31 P2.3/8 bit ADC Not Used 32 P2.2/8 bit ADC AGC IF AGC INPUT for Auto Tuning System 33 P2.1/8 bit ADC KS Local KEY SCAN IN 34 P2.0/8 bit ADC S/SW S/SW IDENT IN for Automatic

switching between TV/AV mode

- H : AV / RGB mode

- L : TV mode 35 VSS VSS-OSD VSS Ground 36 P3.3/INT1 IR REMOTE IR IN 37 VDD VCC-OSD VDD Power Supply 38 LCIN OSCIN-OSD LCIN CLOCK IN for OSD 39 LCOUT LCOUT CLOCK OUT for OSD 40 P3.7/TXT I/O BL BAND VHF-L OUT ( Active High ) 41 P3.6/RXD BH BAND VHF-H OUT ( Active High ) 42 P3.5/T1 BU BAND UHF OUT ( Active High ) 43 P3.4/T0 POWER POWER CONTROL OUT 44 P3.2/INT0 Not Used 45 HS/SC HSYNC HOR. SYNC. IN (Active High) 46 P4.7/VS VSYNC VERT. SYNC. IN (Active High) 47 R R RED OUT 48 G G GREEN OUT 49 B B BLUE OUT 50 BLANK BL BLANK OUT 51 COR COR Not Used

(CONTRAST REDUCTION OUT)

52 P3.0 T1C2/PWM1 EVEN/ODD EVEN/ODD OUT for non-interlacing

in TTX mode

CAT24C08P (E2PROM)

(1) Typical Features

•

IC Bus compatible

•

Low power CMOS Technology

•

16 Byte page write Buffer

•

Self-Timed Write cycle with Auto-Clear

•

100,000 program/Erase cycles

•

100 Year Data Retention

•

Optional High Endurance Device Available

(2) Description

The CAT24C08P is a 8K bit serial CMOS E2PROM internally organized as 1024x8bits. The CAT 24C08P features a 16 byte page write buffer.

(3) Block Diagram

EXTERNAL

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

Vcc Vgg

D OUT

AKC

WORD ADDRESS

BUFFERS

SDA

TEST

SEL

A0 A1 A2

START/STOP

(4) Pin Description

PIN SYMBOL DESCRIPTION

1-3 A0, A1, A2 Device Address lnputs

4 Vss Ground 5 SDA Serial Data/Address 6 SCL Serial Clock 7 TEST Connect to Vss 8 Vcc +5V Power supply

LOGIC

CONTROL

LOGIC

STATE COUNTERS SLAVE

ADDRESS COMPARATORS

XDEC

DATE IN STORAGE

HIGH VOLTAGE/

TIMING CONTROL

TDA8375A (Single chip TV Processor for Negative modulation IF )

(1) General Description

The TDA8375A is I2C-bus controlled single chip TV processors which are intended to be applied in PAL/NTSC television receiver. The IC is mounted in a S-DIL 56 envelope.

(2) Feature

•

- Vision IF amplifier with high sensitivity and good figures for differential phase and gain

- PLL demodulator with high linearity offering the possibility for (single standard) intercarrier stereo audio application .

- Alignment PLL via I2C

- [TDA8375A] Multistandard IF with negative and positive modulation, switchable via I2C

•

Video

- Integrated luminance delay line

- Integrated chroma trap and bandpass filters (auto calibrated)

- Asymmetrical peaking circuit in the luminance channel

- Black stretching of non standard CVBS or luminance signals

•

Colour

- SECAM interface for application with SECAM add-on TDA8395.

•

RGB

- RGB control (brightness, contrast, saturation)

- Black current stabilization and white point adjustment

•

Input / Output

- Flexible video source select with CVBS input for the internal signal and two external video inputs(one switchable for CVBS or Y/C).

- The output signal of the video source select is externally available ( also as CVBS when Y/C input is used).

- External audio input.

- Linear RGB input with fast blanking.

•

Synchronization and Deflection

- Horizontal synchronization with two control loops and alignment free horizontal oscillator.

- Slow start and slow stop of the horizontal drive output to enable low stress start-up and switch-off from the line circuit at nominal line supply voltage.

- Vertical count-down circuit for stable behavior with provisions for non-standard signals.

- Vertical geometry control.

- Vertical drive optimized for DC coupled vertical output stages.

•

Control

- Full I2C bus control, as well for customer controls as for factory alignment.

- All automatic controls have an option for forced mode.

•

Power consumption

- Low power consumption (900 mW at 8.0 Volts).

•

Packaging

- SDIL-56 (Shrinked Dual In Line, 56 pins).

(3) Block Diagram

No Name Description

1 SOUND IF INPUT not used. 2 EXT AUDIO INPUT not used. 3 VCO REF FILTER The IF VCO tuned circuit is applied to these pin.

4 Its resonance frequency must be two times the IF-frequency and in between a

range of 64-120MHz. This range is suitable for the IF standards as 33.4, 38.9, 45.75 and 58.75MHz. The VCO frequency can be adjusted by I2C bus so a fixed coil can be used.

5 PLL LOOP FILTER The PLL loopfilter is a first order filter with R=390 ohm and C = 100nF in

series to ground. The loopfilter bandwidth is 60kHz and is optimal for both fast catching and sufficient video suppression for optimal sound performance. Sound performance can theoretically be improved by adding a small capacitor (approx.0- 4.7nF) between pin 5 and ground. This however must be evaluated further because the normal video signal response should not be effected.

6 IF VIDEO OUTPUT Although the video output impedance is low it is recommended to avoid

high frequency current in the output due to for instance sound trap filters. This can be achieved by means of an emitter follower at the video output with

a 1 resistor in series with the base. 7 BUS INPUT : SCL Serial clock line 8 BUS INPUT : SDA Serial data line 9 BANDGAP The bandgap circuit provides a very stable and temperature independent

DECOUPLING reference voltage.

This reference voltage (6.7V) ensures optimal performance of the TDA8375

and is used in almost all functional circuit blocks. 10 CHROMA INPUT The supplied C S-VHS input burst amplitude should be nominally 300mVpp

(assumed is a colour bar signal with 75% saturation and with chroma/burst

ratio of 2.2/1 ). The C S-VHS input is internally clamped to 4V via 50 .

The external AC coupling capacitor with 50 forms a high pass filter.

A recommended coupling capacitor is 1 nF; the high pass filter cut off

frequency is then approximately 3KHz. 11 Y/CVBS INPUT The Y S-VHS signal of 1Vpp ( inclusive sync amplitude) is AC coupled to pin11. 12 MAIN The TDA8375 has a main supply pin 12 and a horizontal supply pin 37. Both

37 POSITIVE SUPPLY pins have to be supplied simultaneously.

Notice that the IC has not been designed to use this pin 37 as start pin.

(pin 37 supplies the horizontal oscillator, PHI-1 and PHl-2)

(pin 12 supplies the rest of the circuits in the IC)

The nominal supply voltage is 8V. With min/max values of 7.2-8.8V.

Also in stand-by condition the IC must be supplied with 8V.

A voltage detection circuit is connected to both pins.

- pin12 if V12 <6.8V than a power on reset, POR, is generated. The Hout output is disabled immediate.

- pin37 if V37 <5.8V than the horizontal output is disabled immediate.

No Name Description

13 INT CVBS INPUT It is recommended that the CVBS1 int and CVBS2 ext input amplitudes are 17 EXT CVBS INPUT 1 Vpp (inclusive sync amplitude).

This, because the noise detector switches the 1 loop to slow mode (i.e. auto 1mode when FOA, FOB = 0,0) when noise level exceeds

100mVrms (i.e. at S/N of 20dB). 14 GROUND All internal circuits are connected to this ground pin 14. 15 AUDIO OUTPUT not used. 16 DECOUPLING Voltage variations at pin 16, which can be due to external leakage current or

FILTER TUNING crosstalk from interference sources, should be less than 50mV to ensure that

tuning of filters/delay cells remains correct. 18 BLACK CURRENT For correct operation of the loop CURRENT information is supplied to the

INPUT black current input pin.

19 BLUE OUTPUT The RGB outputs are supplied to the video output stages from pins 21, 20 20 GREEN OUTPUT and 19 respectively. 21 RED OUTPUT For nominal signals (i.e. CVBS/S-VHS, -(R-Y)/- (R-Y), TXT inputs) and for

nominal control settings, then the RGB output Signal amplitudes is

typically 2VBLACK_WHITE. 22 V-GUARD INPUT/ Vertical Guard

BEAM CURRENT With this function, the correct working of the vertical deflection can be LIMITER monitored. If the vertical deflection fails, the RGB outputs are blanked to

prevent damage to the picture tube.

Beam current limitinq

The beam current limiting function is realised by reducing the contrast (and

finally the brightness) when the beam current reaches s too high level. The

circuit falls apart in two functions:

- Average beam current limiting (ABL): reacting on the average content of the picture

- Peak white limiting (PWL): reacting on high local peaks in the RGB signal.

23 RED INPUT The Rin, Gin, Bin input signals (nominal signal amplitude of 700mV) are 24 GREEN INPUT AC coupled to pin 23, 24 and 25 respectively. 25 BLUE INPUT Clamping action occurs during burstkey period.

26 RGB INSERTION The table below a survey is given of the three modes which can be selected

SWITCH INPUT with a voltage on RGB insertion switch input pin ;

Vpin26 I2C function Selected RGB signal

0.9V-3V IE1=0 RGB(internal) IE1=1 Rin,Gin,Bin

(fast insertion on pin23,24,25)

> 4V IE1=X OSD can be inserted at the RGBout pins

27 LUMINANCE INPUT An nominal input signal amplitude of 1 Vblack-white MUST be DC coupled

to the luminance input pin 27. The pin is internally AC coupled to the luminance clamp via a capacitor of 50pF; clamping action occurs during burstkey period.

28 LUMINANCE The luminance output signal is approximately l V black-white with typical

OUTPUT output impedance of 25O ohm.

No Name Description

29 B-Y OUTPUT The maximum output impedance of pins 29 and 30 is 500 when PAL/NTSC 30 R-Y OUTPUT signals are identified. When SECAM is identified by the SECAM add-on and

no PAL/NTSC is already identified by the ASM, then the ASM sets the

-(B-Y)/-(R-Y) output switch open (via DEMSW). This enables the -(B-Y)/-(R-Y) outputs of the TDA8395 to be directly connected to pins 29 and 3O respectively.

31 B-Y INPUT The -(B-Y),-(R-Y) output signals (supplied from baseband delay line) are AC 32 R-Y INPUT coupled, via a coupling capacitor of 10nF or greater, to the -(B-Y)/-(R-Y) inputs;

both inputs are clamped during burstkey period.

33 SECAM REF The SECAM reference output is directly connected to pin l of the TDA8395 for

OUTPUT SECAM decoding ; it also can be used as a reference for comb filter applications.

34 X-TAL 3.58 To ensure correct operation of both: 35 X-TAL 4.43 - colour processing internal circuits,

- sync calibration internal circuits, it is only allowed to have 3.6MHz Xtals on pin34: both 4.4MHz,3.6MHz Xtals are allowed on pin 35. If pin 35 is not used: then it is left open in application (also XA,XB=O,1 ).

36 LOOP FILTER One of the important aspects of the PLL is the 1oop filter connected to pin 36;

BURST PHASE it influences the dynamic performance of the loop. DETECTOR

38 CVBS OUTPUT The output amplitude is 1Vpp (transfer gain ratio between CVBS1int or

CVBS2ext or CVBS3ext/Ys-vhs and CVBSout is 1). The maximum output impedance is 250 ohm.

39 BLACK PEAK For the correct working of the black stretcher an external time constant should

HOLD CAPACITOR be added at the black peak hold capacitor input.

40 HOR OUTPUT This open collector output is meant to drive the horizontal output stage.

The output is active low, i.e. the line transistor should conduct during the low period of the output.

41 SANDCASTLE Pin 41 is a combined input/output pin.

OUTPUT/ The pin provides a three level sandcastle pulse. FLYBACK INPUT Both burstkey pulse and vertical blanking pulse are always available, the line

blanking pulse is only present when the external flyback pulse is fed to this pin. The line flyback pulse, fed to this pin is used for two functions:

- input signal for the PHI-2 1oop and

- RGB line blanking. (without flyback pulse blanking occurs only during the

burstkey pulse) To ensure correct working of the delay line and SECAM add-on, the output should not be loaded with more than:

- Sandcastle input delay line TDA 4665

- Sandcastle input SECAM add-on TDA 8395

42 PHI-2 FILTER / The loopfilter is a first order filter.

FLASH PROTECT This pin requires a capacitor (C) only.

A flash protection becomes active when this pin is forced >6V. The horizontal drive is switched-off immediately. Once the voltage is <6V the horizontal drive is switched-on again via the slow start procedure.

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