Cypress Semiconductor CY7C43686-7AC, CY7C43686-15AC, CY7C43686-10AC, CY7C43646-7AC, CY7C43646-15AC Datasheet

1K/4K/16K x36/x18x2 Tri Bus FIFO

Features

• High-speed, low-power , first-in first-out (FIFO) memo­ries w/ three indepen dent po rts (one bidire cti onal x36,
and two unidirectional x18)

• 1K x36/x18x2 (CY7C43646)

• 4K x36/x18x2 (CY7C43666)

• 16K x36/x18x2 (CY7C43686)

• 0.35-micron CMOS for optimum speed/power

• High speed 133-MHz operati on (7.5-ns read /write cyc le
times)

•Low power

—I

= 100 mA

CC

= 10 mA

—I

SB

Logic Block Diagram

CY7C43646
CY7C43666

CY7C43686

• Fully asynchronous and simultaneous read and write
operation permitted

• Mailbox bypass register for each FIFO

• Parallel and Serial Programmable Almost Full and
Almost Empty flags

• Retransmit function

• Standar d or FW FT mod e user selectable

• Partial Reset

• Big or Little Endian f ormat for word or byte bus sizes

• 128-pin TQFP packaging

• Easily expandable in width and depth

CLKA

CSA

W/RA

ENA

MBA

RT2

MRS1

PRS1

FFA/IRA

AFA

SPM

FS0/SD

FS1/SEN

A

0−35

EFA/ORA

AEA

MBF2

Port A
Control
Logic

FIFO1,
Mail1
Reset
Logic

Input

Register

Programmable
Flag Offset
Registers

Output

Register

Write
Pointer

Read
Pointer

Mail1
Register

1K/4K/16K

x36
Dual Ported
Memory

Status
Flag Logic

Status
Flag Logic

256/512/1K
4K/16K x36
Dual Ported
Memory

Mail2
Register

Read
Pointer

Timing
Mode

Write
Pointer

Input

Bus Matching

Output

Bus Matching

Output

Input

Register

MBF1

B

0−17

CLKB

Register

Port B
Control
Logic

Common
Port Logic
(B and C)

FIFO2,
Mail2
Reset
Logic

Port C
Control
Logic

RENB
CSB
SIZEB
MBB
RTI

EFB/ORB
AEB

BE

BE/FWFT

FFC/IRC
AFC

MRS2

PRS2

C

0−17

CLKC
WENC

SIZEC
MBC

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 28, 2000

Pin Configuration

W/RA

ENA

CLKA

GND

A
A
A
A

V

A
A

GND

A
A
A
A
A
A
A

BE/FWFT

GND

A

V

A
A
A
A

GND

A
A
A
A
A

RT2

A

GND

A
A

CY7C43646
CY7C43666
CY7C43686

TQFP

Top View

CSB

GND

MBF2

AEA

AFA

VCCPRS1

EFA/ORA

FFA/IRA

CSA

128

127

126

125

124

123

1
2
3

122

121

MBA

120

MRS1

119

FS0/SD

118

CLKC

117

GND

116

FS1/SEN

115

MRS2

114

MBB

113

112

VCCMBF1

111

4
5

35

6

34

7

33
32

8
9

CC

10

31

11

30

12

29

13
14

28

15

27
26

16

25

17

24

18
19

23

20
21

22

22

CC

23

21

24

20

25

19

26

18

27
28

17

29

16

30

15

31

14

32

13

33
34

12

35
36

11

37

10

38

CY7C43646
CY7C43666
CY7C43686

39404142434445464748495051525354555657585960616263

9

5

A6A7A8A

GND

2

A

A3A4A

CC

V

SPM

0

1

1

B

A0A

GND

AEB

110

AFC

109

EFB/ORB

108

FFC/IRC

107

106

105

WENC

104

102
101
100

RENB

103

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

72
71
70
69
68
67
66
65

CLKB
PRS2
V

CC

C

17

C

16

C

15

C

14

GND
MBC
C

13

C

12

C

11

C

10

C

9

C

8

RT1
C

7

C

6

SIZEB
GND
C

5

C

4

C

3

C

2

C

1

C

0

GND
B

17

B

16

SIZEC

V

CC

B

15

B

14

B

13

B

12

GND
B

11

B

10

64

7

6

B

B5B4B3B2B

GND

B9B8B

CC

V

2

CY7C43646
CY7C43666
CY7C43686

Functional Description

The CY7C436X6 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports clock fr equencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be input and
output in 36-bit, 18-bit, or 9-bit f ormats wit h a choice of Big or
Little Endian configurations.

The CY7C436X6 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transf ers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are in­dependent of one another and can be asynchronous or coin­cident. The enables for each port are arranged to provide a
simple bidi rectional i nterfac e between microproces sors and/or
buses with synchronous control.

Communicat ion betw een ea ch port may b ypa ss the FIF Os vi a
two mailbox registers. The mailbox registers’ width matches
the selected P o rt B bus width. Each mailbo x registe r has a flag
(MBF1

and MBF2) to signal when new mail has been stored.

Two kinds of reset are available on the CY7C436X6: Master
Reset and P artial Reset. Mast er Reset init iali zes t he read and
write pointers to the first location of the memory array, config­ures the FIFO for Big or Little Endian byte arrangement and
selects serial f lag programmi ng, parallel flag programming , or
one of the three possible default flag offset settings, 8, 16, or

64. Each FIFO has its own independent Master Reset pin,
MRS1 and MRS2.

Partial Reset also sets the read and write pointers to the first
location of the mem ory. Unlike Master Reset, any settings ex­isting prior to P artial Reset ( i.e., pr ogr amming method a nd par­tial flag default offsets) are retained. Partial Reset is useful
since it permits fl ushing of the FI FO memory witho ut chang in g
any configuration settings. Each FIFO has its own, indepen­dent Partial Reset pin, PRS1

The CY7C436X6 have two modes of operation: In the CY
Standard Mode, the first word writt en to an empty FIFO is de­posited into the memory array. A read operation is required to
access that word (along with all other words residing in mem­ory). In the First-Word Fall-Through Mode (FWFT), the first
long-word ( 36-bit-wide) written t o an empty FIFO appears au-

and PRS2.

tomatically on the outputs, no read operation required (never­theless, accessing subsequent words does necessitate a for­mal read request). The state of the BE/FWFT
operation det ermines th e mod e in use.

Each FIFO has a combined Empty/Output Ready flag (EFA
ORA and EFB
(FFA

/IRA and FFC/IRC). The E F and FF functions are select­ed in the CY Standard Mode. EF
ory is full or not. The IR and OR functions are selected in the
First-Wo rd Fall-Thr ough Mode . IR i ndica tes whet her or not the
FIFO has av ailable m em ory locations. OR shows whether the
FIFO has data available for reading or not. It marks the pres­ence of valid data on the outputs. (See footnote #24)

Each FIFO has a programmable Alm ost Empty flag (AEA
AEB

) and a programmable Almost Full flag (AFA and AFC).

AEA

and AEB indic ate when a sele cted num ber of w ords writ­ten to FIFO memory achieve a predetermined “almost empty
state.” AFA
words written t o the m emory achieve a predet ermined “almost
full sta te.” (See footnote #47)

IRA, IRC, AFA
that w rit es da ta in to its array. ORA, ORB, AE A
synchronized to the port clock that reads data from its array.
Programmabl e offs et f or AEA
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA
64 locations from the full boundary. All these choi ces are m ade
using the FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider
data paths. Such a width expansi on requires no additional ex­ternal components.

If at any tim e the FIFO is not ac tive ly perf orming a funct ion, the
chip will automatically power down. During the power-down
state, suppl y current consumption (I
ating any operation (by activating control inputs) will immed i­ately take the device out of the power-down state.

The CY7C436X6 are characterized for operation from 0°C to
70°C commercial, and from –40°C to 85°C industrial. Input
ESD protection is greater than 2001V, and latch-up is prevented by
the use of guard rings.

/ORB) and a combined Full/Input Ready flag

indicates whether the mem-

and AFC indicate when a selected number of

, and AFC are synchronized to the port clock

, AEB, AFA, and AFC are loaded

and AFC threshold can be set at 8, 16, or

CC

pin during F IFO

and

, and AEB are

and AEB

) is at a minimum. Initi-

/

Selectio n Gu ide

CY7C43646/66/86

Maximum Frequency (MHz) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enabl e Hold ( ns) 0 0 0
Maximum Flag Delay (ns) 6 8 8
Active Power Supply

Current (I

Density 1K x 36 4K x 36 16K x 36
Package 128 TQFP 128 TQFP 128 TQFP

CC1

) (mA)

Commercial 100 100 100
Industrial 100

CY7C43646 CY7C43666 CY7C43686

-7

3

CY7C43646/66/86

-10

CY7C43646/66/86

-15

CY7C43646
CY7C43666
CY7C43686

Pin Definitions

Signal Name Description I/O Function

A

0–35

AEA

AEB

AFA

AFC

B

0–17

BE/FWFT

C

0–17

CLKA Port A Clock I CLKA is a continuous clock t hat synchr onizes al l data t ransf ers thr ough P ort A and can

CLKB Port B Clock I CLKB is a continuous clock t hat synchr onizes al l data t ransf ers thr ough P ort B and can

CLKC P ort C Clock I CLKC is a con tinuous clock that sync hronizes all dat a trans fers through Port C and can

CSA

CSB

EFA

/ORA Port A Empty/

EFB

/ORB Port B

ENA Port A Enable I ENA must be HIGH to enable a LO W - to-HIGH t ransi tion of CLKA to read or write data

ENB Port B Enable I ENB must be HIGH to enable a LO W - to-HIGH t ransi tion of CLKB to read or write data

Port A Data I/O 36-bit bidirect ional data port for side A.
Port A Almost

Empty Flag

O Programmab le Almost Empt y flag synchronized to CLKA. It i s LOW when the numb er

of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2. (See footnote #47.)

Port B Almost
Empty Flag

O Programmab le Almost Empt y flag syn chronized to CLKB. It is LOW when the number

of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1. (See footnote #47.)

Port A Almost
Full Flag

O Programmab le Almost Full fl ag synchronized to CLKA. It is LOW when the number of

empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1. (See f ootnote #47.)

Port C Almost
Full Flag

O Programmab le Almost Full flag synchronized to CLKC . It is LOW when the number of

empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset

register, Y2. (See f ootnote #47.)
Port B Data O 18-bit output data port for port B.
Big Endian/

First-Word Fall­Through Select

I This is a dual-purpose pin. During Master Reset, a HIG H on BE will selec t Big Endian

operation. In thi s case, depe nding on the bus size, the most signi ficant byt e or word on

Port A is transf erred to P ort B first fo r A-to-B data flow. For data flowing from P ort C to

Port A, the first word/ byte written to Port C will come out as the most significant wo rd/

byte on Port A. On the other hand a LOW on BE will selec t Li ttle Endian oper ation. In

this case, the least sig nif icant byte or word on Port A is tr ansferred to Port B first f or A

to B data flow . Simila rly , t he first word/b yte written into P ort C will come out as the least

significant wo rd/byt e on P ort A for C-t o-A data flow. After Master Reset, this p in select s

the timing mode. A HIGH on FWFT

selects CY Standard Mode, a LOW selects First­Word Fall-Throu gh Mod e. Once the timing mode has been selected, the le vel on this
pin must be static throughout dev ice operation.

Port B Data I 18-bit input data port for port C.

be asynchronous or coincident to CLKB. FFA
synchronized to the LOW-t o-HIGH transition of CLKA.

be asynchronous or coincident to CLKA. EFB
the LOW-to-HIGH transit ion of CLKB.

be asynchronous or coincident to CLKA. FFC
the LOW-to-HIGH transit ion of CLKC.

Port A Chip
Select

Port B Chip
Select

ICSA must be LOW to enable a LOW- to HIGH transition of CLKA to read or write on

Port A. The A

outputs are in the high-impedance state when CSA is HIGH.

0−35

ICSB must be LOW to enable a LOW- to HIGH transition of CLKB to read or write on

Port B. The B

outputs are in the high- impedance state when CSB is HIGH.

0–17

O This is a dual-function pin. In the CY Standard Mode, the EFA function is sel ected. EFA
Output Ready
Flag

indicates whether or not the FIFO2 memory is empty. In the FWFT Mode, the ORA
function is selected. ORA indicat es the presence of valid data on A
able for reading. EFA

/ORA is synchronized to the LOW-to-HIGH tra nsition of CLKA.

(See footnot e #24.)

O This is a dual-funct ion pin. In the CY Standard Mode, the EFB function is selected. EFB
Empty/Output
Ready Flag

indicates whether or not the FIFO1 memory is empty. In the FWFT Mode, the ORB
function is selected. ORB indicat es the presence of valid data on B
able for reading. EFB

/ORB is synchronized t o the LOW -t o-HIGH transition of CLKB.

(See footnot e #24.)

on Port A.

on Port B.

/IRA, EFA/ORA , A FA, and AEA are all

/ORB and AEB are all synchronized to

/IRC, and AFC are all synchronized to

outputs, avail-

0−35

outputs, avail-

0–17

4

CY7C43646
CY7C43666
CY7C43686

Pin Definitions

Signal Name Description I/O Function

FFA

/IRA Port A Full/Input

/IRC Port C Full/Input

FFC

FS1/SEN

FS0/SD Flag Offset

MBA P ort A Ma i lbox

MBB P ort B Ma i lbox

MBC Port C Mailbox

MBF1

MBF2

MRS1

MRS2

PRS1

PRS2

(continued)

Ready Flag

Ready Flag

Flag Offset
Select 1/Serial
Enable

Select 0/Serial
Data

Select

Select

Select
Mail1 Register

Flag

Mail2 Register
Flag

FIFO1 Master
Reset

FIFO2 Master
Reset

FIFO1 Partial
Reset

FIFO2 Partial
Reset

O This is a dual-fun ction pin . In the CY Standar d Mode, the FFA function is selected . FF A

indicates whether or not t he FIFO1 me mory is full. In t he FWFT mode , the IRA function
is selected. IRA indicat es whether or not there is space av ailable f or writing to the FIFO1
memory. FFA

O This is a dual-funct ion pin. In the CY Standard Mode , the FFC functio n is selected. FFC

indicates whether or not the FIFO2 memory i s full. In the FWFT mod e, the IRC functi on
is selected. IRC indicat es whether or not there is space available f or writing to the FIFO2
memory. FFC

I FS1/SEN and FS0/SD are dual-purpose input s used for flag offset register prog ram-

ming. During Master Reset, FS1/SEN
offset program ming method. Three offs et register progr amming methods are a vailab le:
automatically load one of three preset values (8, 16, or 64), parallel l oad from Port A,

I

or serial load. When serial load is selected for flag offset register programming, FS1/
SEN

is used as an enab le synchron ous to the LO W- to-HIGH tr ansition of CLKA. When
FS1/SEN
and Y registers . The numbe r of bi t writes r equi red t o progr am t he off set re gister s is 3 2
for the CY7C43626, 36 for the CY7C43636, 40 for the CY7C43646, 48 for the
CY7C43666, and 56 for the CY7C43686. The first bit write stores the Y-register MSB
and the last bit write stores the X-r egister LSB.

I A HIGH lev el on MBA chooses a mai lbox register for a Port A read or write operation.

When a read operatio n is perf ormed on Port A, a HIGH le v el on MBA select s data from
the Mail2 register for output and a LOW level selects FIFO2 output r egister data for
output. When a write operation is performed on Port A, a High level on MBA wil l write
the data into Mail 1 register, while a Low l evel will write the data into FIFO 1.

I A HIGH lev el on MBB chooses a mail box regi ster for a Port B read operation. When a

read operation is per formed on Port B, a HIGH level on MBB selects data from the
Mail1 register f or out put and a LO W l evel sel ects F IFO1 output regis ter dat a f o r o utput.

I When a write operat ion is perf ormed on Port C , a HIGH level o n M BC wri tes data into

Mail2 register, and a LOW level writes into FIFO2.

OMBF1 is set LOW by a LOW-to-HI G H tr ansition of CLKA that writes data to the Mail 1

register. Writes to the Mail1 register are inhibited whil e MBF1
HIGH by a LOW -t o-HIGH transit ion of CLKB when a Port B read is selected and MBB
is HIGH. MBF1

OMBF2 is set LOW by a LOW-to-HI G H tr ansition of CLKB that writes data to the Mail 2

register. Writes to the Mail2 register are inhibited whil e MBF2
HIGH by a LOW -t o-HIGH transit ion of CLKA when a Port A read is selected and MBA
is HIGH. MBF2

I A LOW on this pin initiali zes the FIFO1 read and write pointers to the first location of

memory and sets the P ort B output register to al l zeroes . A LOW puls e on MRS1
the programmi ng method (serial or parallel ) and one of three p rogrammab le flag def ault
offsets f or FIFO1. It al so confi gures Port B for bus si z e and endian arran gement . F our
LOW-to-HIGH transi tions of CLKA and four LO W-to-HIGH transitions of CLKB must
occur while MRS1

I A LOW on this pin initiali zes the FIFO2 read and write pointers to the first location of

memory and sets the P ort A output register to al l zeroes . A LOW puls e on MRS2
one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transi­tions of CLKA and four LOW-to-HIGH transitio ns of CLKB must occur while MRS2
LOW.

I A LOW on this pin initiali zes the FIFO1 read and write pointers to the first location of

memory and sets the Port B output register to all zeroes . During Partial Reset, the
currently selected bus siz e, endian arrangement, program ming method (serial or par­allel), and progr am m able flag sett ings are all retained.

I A LOW on this pin initiali zes the FIFO2 read and write pointers to the first location of

memory and sets the Port A output register to all zeroes . During Partial Reset, the
currently selected bus siz e, endian arrangement, program ming method (serial or par­allel), and progr am m able flag sett ings are all retained.

/IRA is synchroniz ed to the LOW-to-HIGH transit ion of CLKA.

/IRC is synchroniz ed to t he LOW- to- HIGH transition of CLKB.

and FS0/SD , together with SPM, sel ect the flag

is LOW, a rising edge on CLKA load the bit pr esent on FS0/SD into the X

is LOW. MBF1 is set

is set HIGH following either a Master or Partial Reset of FIFO1.

is LOW. MBF2 is set

is set HIGH following either a Master or Partial Reset of FIFO2.

selects

is LOW.

selects

is

5

CY7C43646
CY7C43666
CY7C43686

Pin Definitions

(continued)

Signal Name Description I/O Function

RENB Port B Read

Enable

RT1

FIFO1
Retransmit

I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on

Port B.

I A LOW strobe on this pin will retransmit data on FIFO1. This is achieved by bringing

the read point er back to loca tion zero . The user will still need to perform re ad operations
to retransmit the dat a. Retransmit func ti on applies to CY standard mode only.

RT2

FIFO2
Retransmit

I A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing

the read point er back to loca tion zero . The user will still need to perform re ad operations
to retransmit the dat a. Retransmit func ti on applies to CY standard mode only.

SIZEB Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW

on this pin when BM is HIGH s elects w ord (18-bi t) b us si z e. SIZEB work s with BM and
BE to select the bus siz e and end ian arrang ement f or Port B. The lev el of SIZEB must
be static throughout device operation.

SIZEC Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port C. A LOW

on this pin when BM i s HIG H sele cts w ord (18-bit ) bus si ze. SIZEC w orks with BM and
BE to select the bus si z e and endian arrange ment f or P ort B. The le v el of SIZEC must
be static throughout device operation.

SPM

W/RA

WENC Port C Write

Serial
Programming

Port A Write/
Read
Select

Enable

I A LOW on this pin se lects serial p rogrammin g of partial flag offs ets. A HIGH on t his pin

selects paral lel programming or default offsets (8, 16, or 64).

I A HIGH selects a write operation and a LOW selects a read operation on Port A for a

LOW-to-HIGH trans it ion of CLKA. The A
when W/RA

is HIGH.

outputs are in the high-impedance state

0−35

I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on

Port C.

Maximum Ratings

[1]

(Abov e which the useful lif e m ay be impaired. For user guide­lines, not tested.)

Storage Temperature .......................................−65

°

C to +150°C

Ambient Temperature with

Power Applied....................................................−55

°

C to +125°C

Supply Voltage to Ground Potential..................−0.5V to +7.0V

DC Voltage Applied to Outp uts
in High Z State

DC Input Voltage

Notes:

1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute­maximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

3. Op erating V

[2]

..........................................−0.5V to V

[2]

.......................................−0.5V to V

Range for -7 speed is 5.0V ±0.25V.

CC

CC
CC

+0.5V
+0.5V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage ....................... .. ............ .. ....>2001V

(per MIL-STD-883, Method 3015)

Latch -U p Cu rre n t.............. .......... ......... .......... .......... . >200mA

Operating Range

Ambient

Range

Temperature

Commercial 0°C to +70°C 5.0V±0.5V
Industrial

−40°

C to +85°C 5.0V±0.5V

[3]

V

CC

6

CY7C43646
CY7C43666
CY7C43686

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZL

I

OZH

[4]

I

CC1

[5]

I

SB

Capacitance

Output HIGH Voltage VCC = 4.5V., IOH = −4.0 mA 2.4 V
Output LOW Voltage VCC = 4.5V., IOL = 8.0 mA 0.5 V
Input HIGH Voltage 2.0 V
Input LOW Voltage
Input Leakage Current V
Output OFF, High Z

= Max. −10 +10 µA

CC

VSS < VO< V

CC

Current
Active Power Supply

Current
Average Standby

Current

[6]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Input Capacitance TA = 25°C, f = 1 MHz ,

V

= 5.0V

Output Capacitance 8 pF

CC

AC Test Loads and Waveforms (-10 & -15)

7C43646/66/86

UnitMin. Max.

V

µA

−0.5

−10

CC

0.8 V

+10

Com’l 100 mA
Ind 100 mA
Com’l 10 mA
Ind 10 mA

4 pF

5V

OUTPUT

INCLUDING

=30 pF

C

L

JIG AND

SCOPE

R1=1.1 K

Ω

R2=680

ALL INPUT PULSES

3.0V

Ω

GND

≤

3ns

90%

10%

90%

10%

3

ns

≤

AC Test Loads and Waveforms (-7)

VCC/2

50Ω

I/O

Notes:

4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.

5. All inputs = V

6. Tested initially and after any design or process changes that may affect these parameters.

– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.

CC

= 

Ω

3.0V

GND

≤

3ns

ALL INPUT PULSES

90%

10%

90%

10%

3

ns

≤

7

CY7C43646
CY7C43666
CY7C43686

Switching Characteristics

Over the Operating Range

7C43646/

66/86

-7

7C43646/

66/86

-10

7C43646/

66/86

-15

Parameter Description

f

S

t

CLK

t

CLKH

t

CLKL

t

DS

Clock Frequency, CLKA,CLKB, or CLKC 133 100 67 MHz
Clock Cycle Time, CLKA,CLKB, or CLKC 7.5 10 15 ns
Pulse Duration, CLKA,CLKB, or CLKC HIGH 3.5 4 6 ns
Pulse Duration, CLKA,CLKB, or CLKC LOW 3.5 4 6 ns
Set-Up Time, A

CLKB↑, and C
Set-Up Time, CSA, W/RA, ENA, and MBA bef ore

before CLKA↑ B

0–35

before C LKC↑

0–17

0–17

before

3 4 5 ns

3 4 5 ns

CLKA↑; RENB and MBB before CLKB↑ and WENC

t

ENS

t

RSTS

t

FSS

t

BES

t

SPMS

t

SDS

t

SENS

t

FWS

t

DH

and MBC before CLKC↑
Set-Up Time, MRS1, MRS2, PRS1, or PRS2 LOW

before C LKA↑ or CL K B↑

[7]

Set-Up Time, FS0 and FS1 b ef ore MRS1 and MRS2

2.5 4 5 ns

6 7 7.5 ns

HIGH
Set-Up Time, BE/FWFT before MRS1 and MRS2

5 7 7.5 ns

HIGH
Set-Up Time, SPM before MRS1 and MRS2 HI GH 5 7 7.5 ns
Set-Up Time, FS0/SD before CLKA↑ 3 4 5 ns
Set-Up Time, FS1/SEN before CLKA↑ 3 4 5 ns
Set-Up Time, FWFT before CLKA↑ 0 0 0 ns
Hold Time, A

and C

0–17

Hold Time, CSA, W/RA , ENA, and MBA before

before CLKA ↑ B

0–35

before CLKC↑

before CLKB↑,

0–17

0 0 0 ns

0 0 0 ns

CLKA↑ RENB and MBB before CLKB↑ and WENC

t

ENH

t

RSTH

t

FSH

t

BEH

t

SPMH

t

SDH

t

SENH

t

SPH

[8]

t

SKEW1

[8]

t

SKEW2

t

A

t

WFF

Notes:

7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

8. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

and MBC before CLKC↑
Hold Time, MRS1, MRS2, PRS1, or PRS2 LO W after

CLKA↑ or CLKB↑

[7]

Hold Time, FS0 and FS1 after MRS1 and MRS2

1 2 4 ns

1 1 2 ns

HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 1 1 2 ns
Hold Time, SPM after MRS1 and MRS2 HIGH 1 1 2 ns
Hold Time, FS0/SD after CLKA↑ 0 0 0 ns
Hold Time, FS1/SEN after CLKA↑ 0 0 0 ns
Hold Time, FS1/SEN HIGH after MRS1 and MRS2

0 1 2 ns

HIGH
Ske w Time between CLKA↑ and CLKB↑ for EFA/

ORA, EFB

/ORB, FFA/IRA, and FFC/IRC

Ske w Time between CLKA↑ and CLKB↑ for AEA,
AEB

, AFA, AFC

Access Time, CLKA↑ to A

and CLKB↑ to B

0–35

0–17

Propagation Delay Time, CLKA↑ to FFA/IRA and
CLKB↑ to FFC

/IRC

5 5 7.5 ns

7 8 12 ns

1 6 1 8 3 10 ns
1 6 1 8 2 8 ns

UnitMin. Max. Min. Max. Min. Max.

8

CY7C43646
CY7C43666
CY7C43686

Switching Characteristics

Over the Operating Range (continued)

Parameter Description

Propagation Delay Time, CLKA↑ to EFA/ORA and

t

REF

CLKB↑ to EFB

/ORB

Propagation Delay Time , CLKA↑ to AEA and CLKB↑

t

PAE

to AEB
Propagation Dela y Time, CLKA↑ to A FA and CLKC↑

t

PAF

to AFC
Propagation Delay Time, CLKA↑ to MBF1 LOW or

MBF2

HIGH and CLKB↑ to MBF2 LOW or MBF1

t

PMF

t

PMR

HIGH
Propagation Delay Time, CLKA↑ to B

CLKB↑ to A

0–35

[10]

Propagation Delay Time, MBA to A

t

MDV

MBB to B

0–17

Valid

Propagation Delay Time, MRS1 or PRS1 LOW to
AEB

LOW, AFA HIGH, FFA/IRA LOW, EFB/ORB

t

RSF

LOW and MBF1
AEA

LOW, AFC HIGH, FFC/IRC LOW, EFA/ORA

LOW and MBF2

HIGH and MRS2 or PRS2 LOW to
HIGH

Enable Ti me, CSA or W/RA LO W to A

t

EN

CSB LOW and RENB HIGH to B
Disable Time, CSA or W/RA HIGH to A

t

DIS

t

PRT

t

RTR

Notes:

9. Writing data to the Mail1 register when the B

10. Writing data to the Mail2 register when the A

at High Impedance
Retransmit Pulse Width 60 60 60 ns
Retransmit recovery Time 90 90 90 ns

Impedance and CSB

HIGH or RENB LOW to B

outputs are active and MBB is HIGH.

0–17

outputs are active and MBA is HIGH.

0–35

0–17

0–17

Valid and

0–35

0–35

Active

0–35

[9]

and

Active a nd

at High

0–17

7C43646/

66/86

-7

7C43646/

66/86

-10

7C43646/

66/86

-15
UnitMin. Max. Min. Max. Min. Max.

1 6 1 8 1 8 ns

1 6 1 8 1 8 ns

1 6 1 8 1 8 ns

0 6 0 8 0 12 ns

1 7 2 11 3 12 ns

1 6 2 9 3 11 ns

1 6 1 10 1 15 ns

1 5 2 8 2 10 ns

1 5 1 6 1 8 ns

9

Switching Waveforms

FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight

CLKA

CLKB

t

RSTS

MRS1

BE/FWFT

SPM

FS1/SEN,
FS0/SD

FFA

/IRA

EFB

/ORB

t

RSF

t

RSF

t

BES

t

SPMS

t

FSS

[11, 12]

t

RSTH

t

BEH

t

SPMH

t

FSH

t

FWS

CY7C43646
CY7C43666
CY7C43686

t

WFF

t

RSF

AEB

t

AFA

RSF

t

RSF

MBF1

Notes:

11. PRS1

12. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than the case where BE/FWFT is LOW.

and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.

10

CY7C43646
CY7C43666
CY7C43686

Switching Waveforms

(continued)

FIFO2 Master Reset Loading X1 and Y1 with a Preset Value of Eight

CLKC

CLKA

t

RSTS

MRS2

BE/FWFT

SPM

FS1/SEN,
FS0,SD

FFC

/IRC

EFA

/ORA

t

RSF

t

RSF

t

RSF

AEA

t

AFC

RSF

t

BES

t

SPMS

t

FSS

[13, 14]

t

RSTS

t

BEH

t

SPMH

t

FSH

t

FWS

t

WFF

t

RSF

MBF2

Notes:

13. PRS2

14. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than the case where BE/FWFT is LOW.

and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.

11

CY7C43646
CY7C43666
CY7C43686

Switching Waveforms

(continued)

FIFO1 Partial Reset (CY Standard and FWFT Modes)

CLKA

CLKB

t

RSTS

PRS1

t

RSF

FFA/IRA

t

EFB

/ORB

RSF

t

RSF

AEB

t

RSF

AFA

t

RSF

MBF1

[12, 15]

t

RSTH

t

WFF

FIFO2 Partial Reset (CY Standard and FWFT Modes)

CLKC

CLKA

t

RSTS

PRS2

t

RSF

FFC/IRC

t

EFA

/ORA

RSF

t

RSF

AEA

t

RSF

AFC

t

RSF

MBF1

Notes:

15. MRS1

16. MRS2 must be HIGH during Partial Reset.

must be HIGH during Partial Reset.

[14, 16]

t

RSTH

t

WFF

12