Cypress Semiconductor CY7C43684-7AC, CY7C43684-15AC, CY7C43684-10AC, CY7C43664-7AC, CY7C43664-15AC Datasheet
...
Synchronous FIFO w/ Bus Matching
Features
• High-speed, low- power , Bidirectional, First-In First -Out
(FIFO) memories w/ bus matching capabilities
• 1Kx36x2 (CY7C43644 )
• 4Kx36x2 (CY7C43664 )
• 16Kx36x2 (CY7C43684)
• 0.35-micron CMOS for optimum speed/power
• High-speed 133-MHz oper ation (7.5 ns read/wr ite cycl e
times)
• Low power
= 100 mA
—I
CC
= 10 mA
—I
SB
Logic Block Diagram
CY7C43644
CY7C43664
CY7C43684
1K/4K x36 x2 Bidirectional
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass reg ister for eac h FIFO
• Par allel and Serial Pro gram m able Almost-Full and
Almost-Empty flags
• Ret ra n smit func tion
• Standard or FWFT mode user selectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A
0–35
EFA/ORA
AEA
Port A
Control
Logic
FIFO1,
Mail 1
Reset
Logic
36
Input
Register
Programmable
Flag Offset
Registers
Output
Register
Write
Pointer
Write
Pointer
Mail 1
Register
1K/4K/16K
x36
Dual Ported
Memory
Status
Flag Logic
Status
Flag Logic
256/512/1K
4K/16K x36
Dual Ported
Memory
Read
Pointer
Timing
Mode
Read
Pointer
MBF1
CLKB
CSB
Port B
Control
Output
Register
Bus Matching
Logic
36
FIFO1,
Mail 1
Reset
Logic
Input
Register
W/RB
ENB
MBB
RTI
BE
BM
SIZE
EFB/ORB
AEB
B
0–35
BE/FWFT
FFB/IRB
AFB
MRS2
PRS2
MBF2
Cypress Semiconductor Corporation
Mail 2
Register
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 28, 2000
Pin Configuration
W/RA
ENA
CLKA
GND
A
A
A
A
V
A
A
GND
A
A
A
A
A
A
A
BE/FWFT
GND
A
V
A
A
A
A
GND
A
A
A
A
A
RT2
A
GND
A
A
CY7C43644
CY7C43664
CY7C43684
TQFP
Top View
AEA
AFA
MBF2
FS0/SD
MRS1
123
122
121
MBA
120
119
118
VCCPRS1
EFA/ORA
FFA/IRA
CSA
128
127
126
125
1
2
3
124
GND
117
GND
116
FS1/SEN
115
MRS2
114
MBB
113
112
VCCMBF1
111
AEB
110
4
5
35
6
34
33
7
32
8
9
CC
10
31
11
30
12
29
13
14
28
15
27
26
16
25
17
24
18
19
23
20
21
22
22
CC
23
21
24
20
25
19
26
18
27
28
17
29
16
30
15
31
14
32
13
33
34
12
35
36
11
37
10
38
CY7C43644
CY7C43664
CY7C43684
39404142434445464748495051525354555657585960616263
5
6A7A8A9
A
GND
2
A
A3A4A
CC
V
SPM
0
0A1
A
B
GND
AFB
109
GND
FFB/IRB
CSB
ENB
107
106
105
W/RB
104
102
101
100
103
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
CLKB
PRS2
V
CC
B
35
B
34
B
33
B
32
GND
GND
B
31
B
30
B
29
B
28
B
27
B
26
RT1
B
25
B
24
BM
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
SIZE
V
CC
B
15
B
14
B
13
B
12
GND
B
11
B
10
EFB/ORB
108
64
7
6
5B4B3B2B1
B
B
GND
B9B8B
CC
V
2
CY7C43644
CY7C43664
CY7C43684
Functional Description
The CY7C436X4 is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports clock fr equencies up to 133 MHz and has read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be input and
output in 36-bit, 18-bit, or 9-bit f ormats wit h a choice of Big or
Little Endian configurations.
The CY7C436X4 is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data tr ansfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a
simple bidi rectional i nterfac e between microproces sors and/or
buses with synchronous control.
Communicat ion betw een ea ch port may b ypa ss the FIF Os vi a
two mailbox registers. The mailbox registers’ width matches
the selected P o rt B bus width. Each mailbo x registe r has a flag
(MBF1
and MBF2) to signal when new mail has been stored.
Two kinds of reset are available on the CY7C436X4: Master
Reset and P artial Reset. Mast er Reset init iali zes t he read and
write pointers to the first location of the memory array, configures the FIFO for Big or Little Endian byte arrangement and
selects serial f lag programmi ng, parallel flag pr ogramming, or
one of the three possible default flag offset settings, 8, 16, or
64. Each FIFO has its own independent Master Reset pin,
MRS1
and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the mem ory. Unlike Master Rese t, any settings existing prior to P artial Reset ( i.e., pr ogr amming method a nd partial flag default offsets) are retained. Partial Reset is useful
since it permits fl ushing of the FI FO memory witho ut chang in g
any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1
The CY7C436X4 have two modes of operation: In the CY
Standard Mode, the first word writt en to an empty FIFO is deposited into the memory array. A read operation is required to
access that word (along with all other words residing in memory). In the First-Word Fall-Through Mode (FWFT), the first
long-word ( 36-bit wide) written to an empty FIFO appears au-
and PRS2.
tomatically on the outputs, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/FWFT
operation det ermines th e mod e in use.
Each FIFO has a combined Empty/Output Ready flag (EFA
ORA and EFB
(FFA
/IRA and FFB/IRB). The EF and FF func tions are selected
in the CY Standard mode. EF
is full or not. The IR and OR functions are sele cted in the First Word F all -Through mode . IR indicates whet her or not the FIFO
has av ail able memory locations. OR shows whet her the FIFO
has data availab le for readi ng or not. It marks the presence of
valid data on the outputs.(See footnote #22)
Each FIFO has a programmable Alm ost Empty flag (AEA
AEB
) and a programmable Almost Full flag (AFA and AFB).
AEA
and AEB indic ate when a sele cted num ber of w ords written to FIFO memory achieve a predetermined “almost empty
state.” AFA
words written t o the m emory achieve a predet ermined “almost
full sta te.”(See footnote #44)
IRA, IRB, AFA
writes data into its array. ORA, ORB, AEA
chronized to th e port clock that reads data from its array. Programmable of fset f or AEA
in parallel using Port A or in serial via the SD input. Three
default offset settings are also provided. The AEA
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AFA
64 locations from the full boundary. All these choi ces are made
using the FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If at any time the FI FO is not actively performing a
function, the chip will automatically power down. During the
power-down state, supply current consumption (I
minimum. Init iating a ny oper ati on (b y act iv ati ng con trol inputs )
will immediately take the device out of t he power-down st ate.
Retransmit feature is a vailable on these devices.
The CY7C436X4 are characterized for operation from 0
°C commercial, and from -40°
70
ESD protection is gr eater than 2001V, and latch -up is pr evented by the use of guard rings.
/ORB) and a combined Full/Input Ready flag
indicates whether the memory
and AFB indicate when a selected number of
, and AFB are synchroni zed to the port clock that
, AEB, AFA, and AFB can be loa ded
and AFB threshold can be set at 8, 16, or
C to 85
pin during F IFO
and
, and AEB are syn-
and AEB
) is at a
CC
°
°C industrial
C to
. Input
/
Selectio n Gu ide
CY7C43644/64/84
Maximum Frequency (MHz) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enabl e Hold ( ns) 0 0 0
Maximum Flag Delay (ns) 6 8 8
Active Power Supply
Current (I
Density 1K x 36 x2 4K x 36 x2 16K x 3 6 x 2
Package 128 TQFP 128 TQFP 128 TQFP
CC1
) (mA)
Commercial 100 100 100
Industrial 100
–7
CY7C43644 CY7C43664 CY7C43684
3
CY7C43644/64/84
–10
CY7C43644/64/84
15
−
CY7C43644
CY7C43664
CY7C43684
Pin Definitions
Signal Name Description I/O Function
A
0–35
AEA
AEB
AFA
AFB
B
0–35
BE/FWFT
BM Bus Match
CLKA Port A Clock I CLKA is a continuous clock t hat synchr onizes al l data t ransf ers thr ough P ort A and can
CLKB Port B Clock I CLKB is a continuous clock t hat synchr onizes al l data t ransf ers thr ough P ort B and can
CSA
CSB
EFA
/ORA Port A Empty/
EFB
/ORB Port B Empty/
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
Port A Data I/O 36-bit bidirect ional data port for side A.
Port A Almost
Empty Flag
Port B Almost
Empty Flag
Port A Almost
Full Flag
Port B Almost
Full Flag
Port B Data I/O 36-bit bidirect ional data port for side B.
Big Endian/
First-Word FallThrough Select
Select (Port A)
Port A Chip
Select
Port B Chip
Select
Output Ready
Flag
Output Ready
Flag
O Programmab le Almost Empty flag sy nchronized to CLKA. It i s LOW whe n the number
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2. (See footnote #44.)
O Programmab le Almost Empty flag syn chronized to CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1. (See footnote #44.)
O Programmab le Almost Full fl ag synchronized to CLKA. It i s LOW when the number of
empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1. (See footnote #44.)
O Programmab le Almost Full flag synchronized to CLKB. It is LOW when the number of
empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2. (See footnote #.)
I This is a dual-purpose pin. During Master Reset, a HIG H on BE will selec t Big Endian
operation. In thi s case, depe nding on the bus size, the most signi ficant byt e or word on
Port A is transferred to P ort B first for A-to-B data flow. For data flowing from Port B to
Port A the first word/byte written to Port B will come out as the most significant word/
byte on Port A. A LO W on BE will select Litt le Endian ope rati on. In th is case , the leas t
significant byte or word on Port A is tran s ferred to P o rt B fi rst fo r A-to-B d a ta flow.
Similarly , the fist word/byte written into P ort B will come out as the least significan t word/
byte on Po rt A for B-to-A data flow . After Master Reset, this pin selec ts the timing mode.
A HIGH on FWFT
mode. Once the timing mode has been selected, the level on this pin must be static
throughout device operation.
I A HIGH on this pin enables either b yte or wor d bus widt h on P ort B, depe nding on the
state of SIZE. A LOW select s long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM m ust be static
throughout device operation.
be asynchronous or coincident to CLKB. FFA
synchronized to the LOW-t o-HIGH transition of CLKA.
be asynchronous or coincident to CLKA. FFB
synchronized to the LOW-t o-HIGH transition of CLKB.
ICSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A
ICSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B
O This is a dual-function pin. In the CY Standard mode, the EFA
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicat es the presence o f valid data on A
able for reading. EFA
(See footnot e #22.)
O This is a dual-funct ion pin. In the CY Standard mode, the EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicat es the presence o f valid data on B
able for reading. EFB
(See footnot e #22.)
on Port A.
on Port B.
selects CY St andard mode , a LOW se lects Fi rst- W ord Fall-Through
outputs are in the high-im pedance state when CSA is HIGH.
0–35
outputs are in the high- impedance state when CSB is HIGH.
0–35
/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
/ORB is synchronized t o the LOW-to-HIGH transiti on of CLKB.
/IRA, EFA/ORA , A FA, and AEA are all
/IRB, EFB /ORB, AFB, and AEB are all
function is selected. EFA
outputs, avail-
0–35
function is selected. EFB
outputs, avail-
0–35
4
CY7C43644
CY7C43664
CY7C43684
Pin Definitions
Signal Name Description I/O Function
/IRA Port A Full/Input
FFA
/IRB Port B Full/Input
FFB
FS1/SEN
FS0/SD Flag Offset
MBA P ort A Mailbox
MBB P ort B Mailbox
MBF1
MBF2
MRS1
MRS2
PRS1
PRS2
(continued)
Ready Flag
Ready Flag
Flag Offset
Select 1/Serial
Enable
Select 0/Serial
Data
Select
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
FIFO2 Master
Reset
FIFO1 Partial
Reset
FIFO2 Partial
Reset
O This is a dual-fun ction pin . In the CY Standar d mode, the FFA function is selected . FF A
indicates whether or not t he FIFO1 me mory is full. In t he FWFT mode , the IRA function
is selected. IRA indicat es whether or not there is space av ailable f or writing to the FIFO1
memory. FFA
O This is a dual-function pin. In the CY Standard mode, the FFB functio n is selected. FFB
indicates whether or not t he FIFO2 me mory is full. In t he FWFT mode , the IRB function
is selected. IRB indicat es whether or not there is space av ailable f or writing to the FIFO2
memory. FFB
I FS1/SEN
ming. During Master Reset, FS1/SEN
offset program ming method. Three offs et register progr amming methods are a vailab le:
automatically load one of three preset values (8, 16, or 64), parallel load f rom Port A,
I
or serial load. When serial load is selected for flag offset register pro gramming, FS1/
SEN
is used as an enab le synchron ous to the LO W- to-HIGH tr ansition of CLKA. When
FS1/SEN
and Y registers . The numbe r of bi t writes r equi red t o progr am t he off set re gister s is 4 0
for the CY7C43644, 48 for the CY7C43664, and 56 for the CY7C43684. The first bit
write stores the Y-register MSB and the last bit write stores the X-registe r LSB.
I A HIGH lev el on MBA chooses a mai lbox regis ter for a Port A read or write operation.
When a read operatio n is perf ormed on Port A, a HIGH le v el on MBA select s data from
the Mail2 register for output and a LOW lev el selects FIFO2 output register data fo r
output. When a write oper ati on is p erf ormed on Port A, a HIGH lev el on M BA wil l write
the data into Mail 1 register. While a LOW level will write the data into FIFO1.
I A HIGH lev el on MBB chooses a mai lbox regis ter for a Port B read or write operation.
When a read operatio n is perf ormed on Port B, a HIGH lev el on MBB select s data from
the Mail1 register for output and a LOW lev el selects FIFO1 output register data fo r
output. When a write oper ati on is per f ormed on Port B, a HIGH l ev e l on MBB wil l write
the data into Mail 2 register, while a LO W level will write the data into FIFO2.
OMBF1 is set LOW by a LOW-to-HI GH transition of CLKA that writes data to th e Mail1
register. Writes to the Mail1 register are inhibited whil e MBF1
HIGH by a LOW -t o-HIGH transition of CLKB when a Port B read is select ed and MBB
is HIGH. MBF1
OMBF2 is set LOW by a LOW-to-HI GH transition of CLKB that writes data to th e Mail2
register. Writes to the Mail2 register are inhibited whil e MBF2
HIGH by a LOW -t o-HIGH transition of CLKA when a Port A read is select ed and MBA
is HIGH. MBF2
I A LOW on this pin initiali zes the FIFO1 read and write pointers to the first locati on of
memory and sets the P ort B output register to al l zeroes . A LOW puls e on MRS1
the programmi ng method (serial or parallel ) and one of three p rogrammab le flag def ault
offsets f or FIFO1. It al so confi gures Port B for bus siz e and endian arr angem ent. F o ur
LOW-to-HIGH transitions of CLKA and four LO W-to-HIGH transitions of CLKB must
occur while MRS1
I A LOW on this pin initiali zes the FIFO2 read and write pointers to the first locati on of
memory and sets the P ort A output register to al l zeroes . A LOW puls e on MRS2
one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-t o-HIGH transitions of CLKB must occur while MRS2
LOW.
I A LOW on this pin initiali zes the FIFO1 read and write pointers to the first locati on of
memory and sets the Port B output register to all zeroes. Duri ng Partial Reset, the
currently selected bus size, endian arrangement, program ming method (serial or parallel), and progr am m able flag sett ings are all retained.
I A LOW on this pin initiali zes the FIFO2 read and write pointers to the first locati on of
memory and sets the Port A output register to all zeroes. Duri ng Partial Reset, the
currently selected bus size, endian arrangement, program ming method (serial or parallel), and progr am m able flag sett ings are all retained.
/IRA is synchroniz ed to the LOW-to-HIGH transition of CLKA.
/IRB is synchronized to the LOW -to-HIGH transition of CLKB.
and FS0/SD are dual-purpose input s used for flag off set register program-
and FS0/SD , together with SPM, sel ect the flag
is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X
is set HIGH following either a Master or Partial Reset of FIFO1.
is set HIGH following either a Master or Partial Reset of FIFO2.
is LOW.
is LOW. MBF1 is set
is LOW. MBF2 is set
selects
selects
is
5
CY7C43644
CY7C43664
CY7C43684
Pin Definitions
(continued)
Signal Name Description I/O Function
RT1 Retransmit
FIFO1
I A LOW strob e on t his pi n will r etransmi t the d ata on FI FO1. Th is is achie ved by bri nging
the read point er back to loca tion zero . The user will still need to perform re ad operations
to retransmit the dat a. Retransmit func ti on applies to CY standard mode only.
RT2
Retransmit
FIFO2
I A LOW strobe on this pin will retransmit data on FIFO2. This is achieved by bringing
the read point er back to loca tion zero . The user will still need to perform re ad operations
to retransmit the dat a. Retransmit func ti on applies to CY standard mode only.
SIZE Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW
on this pin when BM is HIGH selec ts word (18-bit) bus size. SI ZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must
be static throughout device operation.
SPM
W/RA
W/
RB Port B Write/
Maximum Ratings
(Abov e which the useful lif e m ay be impaired. For user guidelines, not tested.)
Storage Temperature ............. .......... ... .........–65
Ambient Temperature with
Power Applied ...............................................–55
Supply Voltage to Gr o u nd Potent ia l ..... ......... . –0.5V to +7.0V
DC Voltage Applied to Outp uts
in High Z State
DC Input Voltage
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Op erating V
Serial
Programming
Port A Write/
Read
Select
I A LOW on this pin se lects serial p rogrammin g of partial flag offs ets. A HIGH on t his pin
selects paral lel programming or default offsets (8, 16, or 64).
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a
LOW-to-HIGH trans it ion of CLKA. The A
when W/RA
I A LOW selects a write operation and a HIGH sel ects a read operation on P ort B f or a
Read
Select
[1]
[2]
......................................–0.5V to VCC+0.5V
[2]
...................................–0.5V to VCC+0.5V
Range for -7 speed is 5.0V ±0.25V.
CC
LOW-to-HIGH transition of CLKB. The B
when W
/RB is LOW.
°
C to +150°C
°
C to +125°C
is HIGH.
outputs are in the high-impedance state
0–35
outputs are in the high-impedance state
0–35
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........... .. ............ .. ................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .....................................................>200 mA
Operating Range
Ambient
Range
Temperature
Commercial 0°C to +70°C 5.0V ± 0.5V
Industrial –40°C to +85°C 5.0V ± 0.5V
[3]
V
CC
6
CY7C43644
CY7C43664
CY7C43684
Electrical Characteristics
Over the Operating Range
Parameter Description T est Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZL
I
OZH
[4]
I
CC1
[5]
I
SB
Capacitance
Output HIGH Voltage VCC = 4.5V,
I
= –4.0 mA
OH
Output LOW Voltage VCC = 4.5V,
I
= 8.0 mA
OL
Input HIGH Volt a g e 2.0 V
Input LOW Voltage –0.5 0.8 V
Input Leakage Current V
Output OFF, High Z
= Max. –10 +10 µA
CC
VSS < VO< V
Current
Active Power Supply
Current
Av erage Standby
Current
[6]
Parameter Description Test Conditions Max. Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz ,
V
= 5.0V
Output Capacitance 8 pF
CC
CY7C43644/64/84
2.4 V
0.5 V
CC
–10 +10
Com’l 100 mA
Ind 100 mA
Com’l 10 mA
Ind 10 mA
4 pF
CC
UnitMin. Max.
V
µA
AC Test Loads and Waveforms (-10 & -15)
5V
OUTPUT
INCLUDING
R1=1.1K
CL=30 pF
JIG AND
SCOPE
Ω
R2=680
ALL INPUT PULSES
3.0V
Ω
GND
≤
3ns
90%
10%
90%
10%
3
ns
≤
AC Test Loads and Waveforms (-7)
VCC/2
50Ω
3.0V
GND
I/O
Notes:
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
5. All inputs = V
6. Tested initially and after any design or process changes that may affect these parameters.
– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
CC
=
Ω
≤
3ns
ALL INPUT PULSES
90%
10%
90%
10%
3
ns
≤
7
CY7C43644
CY7C43664
CY7C43684
Switching Characteristics
Over the Operating Range
Parameter Description
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
Clock Frequency, CLKA or CLKB 133 100 67 MHz
Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
Set-Up Time, A
before CLKB↑
before CLKA↑ and B
0–35
Set-Up Time, CSA, W/R A, ENA, and MBA before
CLKA↑; CSB
, W/RB, ENB, and MBB before
CLKB↑
t
RSTS
t
FSS
t
BES
t
SPMS
t
SDS
t
SENS
t
FWS
t
DH
t
ENH
t
RSTH
t
FSH
t
BEH
t
SPMH
t
SDH
t
SENH
t
SPH
Set-Up Time, MRS1, MRS2, PRS1, or PRS2 LOW
before CLKA↑ or CLKB↑
[7]
Set-Up Time, FS0 and FS1 before MRS1 and
MRS2
HIGH
Set-Up Time, BE/FWFT before MRS1 and MRS2
HIGH
Set-Up Time, SPM befor e MRS1 and MRS2 HIGH 5 7 7.5 ns
Set-Up Time, FS0/SD before CLKA↑ 3 4 5 ns
Set-Up Time, FS1/SEN before CLKA↑ 3 4 5 ns
Set-Up Time, BE/FWFT before CLKA↑ 0 0 0 ns
Hold Time, A
CLKB↑
after CLK A↑ and B
0–35
Hold Time, CSA, W/RA, ENA, and MBA after
CLKA↑; CSB
Hold Time, MRS1, MRS2, PRS1, or PRS2 LOW
after CLKA↑ or CLKB↑
, W/RB, ENB, and MBB a fter CLKB↑
[7]
Hold Time, FS0 and FS1 after MRS1 and MRS2
HIGH
Hold Time, BE/FWFT after MRS1 and M RS2
HIGH
Hold Time, SPM after MRS1 and MRS2 HIGH 1 1 2 ns
Hold Time, FS0/SD after CLKA↑ 0 0 0 ns
Hold Time, FS1/SEN after CLKA↑ 0 0 0 ns
Hold Time, FS1/SEN HI GH after MRS1 and MRS2
HIGH
[8]
t
SKEW1
t
SKEW2
t
A
t
WFF
t
REF
Skew Time between CLKA↑ and CLKB↑ fo r E FA/
ORA, EFB
[8]
Skew Time betwe en CLKA↑ and CLKB↑ for AEA,
AEB
/ORB, FFA/IRA, and FFB/IRB
, AFA, AF B
Access Time, CLKA↑ to A
B
0–35
Propagation Delay Time, CLKA↑ to FFA/IRA and
CLKB↑ to FFB
/IRB
Propagation Dela y Time, CLKA↑ to EF A/ORA and
CLKB↑ to EFB
/ORB
and CLKB↑ to
0–35
0–35
0–35
after
CY7C43644/
64/84
–7
CY7C43644/
64/84
–10
CY7C43644/
64/84
–15
UnitMin. Max. Min. Max. Min. Max.
3 4 5 ns
3 4 5 ns
2.5 4 5 ns
6 7 7.5 ns
5 7 7.5 ns
0 0 0 ns
0 0 0 ns
1 2 4 ns
1 1 2 ns
1 1 2 ns
0 1 2 ns
5 5 7.5 ns
7 8 12 ns
1 6 1 8 3 10 ns
1 6 1 8 2 8 ns
1 6 1 8 1 8 ns
8
CY7C43644
CY7C43664
CY7C43684
Switching Characteristics
Over the Operating Range (continued)
CY7C43644/
64/84
–7
CY7C43644/
64/84
–10
CY7C43644/
64/84
–15
Parameter Description
t
PAE
Propagation Delay Time, CLKA↑ to AEA and
1 6 1 8 1 8 ns
CLKB↑ to AEB
t
PAF
t
PMF
Propagation Delay Time, CLKA↑ to AFA and
CLKB↑ to AFB
Propagation Dela y Time, CLKA↑ to MBF1 LOW or
MBF2
HIGH and CLKB↑ to MBF2 LOW or MBF1
1 6 1 8 1 8 ns
0 6 0 8 0 12 ns
HIGH
t
PMR
t
MDV
t
RSF
t
EN
t
DIS
Propagation Delay Time, CLKA↑ to B
CLKB↑ to A
0–35
[10]
Propagation De lay Time , MBA to A
MBB to B
0–35
Valid
Propagation Dela y Time, MRS1 or PRS1 LO W to
AEB
LOW, AFA HIGH, FFA/IRA LOW, EFB/ORB
LOW and MBF1
to AEA
LOW, AFB HIGH, FFB/IRB LOW, EFA/
ORA LOW and MBF2
HIGH and MRS2 or PRS2 LOW
HIGH
Enable Time, CSA or W/RA LOW to A
and CSB
LOW and W/RB HIGH to B
Disable Time, CSA or W/RA HIGH to A
Impedance a nd CSB
HIGH or W/RB LOW to B
at High Impedance
t
PRT
t
RTR
Notes:
7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
8. Ske w time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
9. Writing data to the Mail1 register when the B
10. Writing data to the Mail2 register when the A
Retransmit Pulse W idt h 60 60 60 ns
Retransmit recovery Time 90 90 90 ns
outputs are active and MBB is HIGH.
0–35
outputs are active and MBA is HIGH.
0–35
0–35
Valid and
0–35
0–35
0–35
0–35
[9]
and
Active
Active
at High
0–35
1 7 2 11 3 12 ns
1 6 2 9 3 11 ns
1 6 1 10 1 15 ns
1 5 2 8 2 10 ns
1 5 1 6 1 8 ns
UnitMin. Max. Min. Max. Min. Max.
9
Switching Waveforms
FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
CLKB
t
RSTS
[11, 12]
t
RSTH
CY7C43644
CY7C43664
CY7C43684
MRS1
t
BES
BE/FWFT
t
SPMS
SPM
t
FSS
FS1/SEN,
FS0/SD
FFA
/IRA
EFB
/ORB
t
t
t
RSF
RSF
RSF
AEB
t
RSF
AFA
t
RSF
MBF1
Notes:
11. Master Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
12. PRS1
must be HIGH during Master Reset.
BE
t
BEH
t
SPMH
t
FSH
t
FWS
FWFT
t
WFF
10
CY7C43644
CY7C43664
CY7C43684
Switching Waveforms
FIFO1 Partial Reset (CY Stan dard and FW FT Mo des)
(continued)
[13, 14]
CLKA
CLKB
t
RSTS
t
RSTH
PRS1
t
RSF
FFA/IRA
t
RSF
EFB
/ORB
t
RSF
AEB
t
RSF
AFA
t
RSF
MBF1
Parallel Program ming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
[15]
t
WFF
CLKA
, MRS2
MRS1
SPM
t
FSS
t
FSS
t
t
FSH
FSH
FS1/SEN,
FS0/SD
FFA/
IRA
t
WFF
t
ENS
t
ENH
ENA
t
DH
DS
AEB Offset (X1)
AFB
Offset (Y2)
A
0 − 35
t
AFA Offset (Y1)
CLKB
FFB
/IRB
Notes:
13. Partial Reset is performed in the same manner for FIFO2.
14. MRS1
15. CSA=LOW, W/ RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
16. t
must be HIGH during Partial Reset.
is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
SKEW1
edge of CLKA and rising edge of CLKB is less than t
, then FFB/IRB may transition HIGH one cycle later than shown.
SKEW1
AEA
t
SKEW1
Offset (X2)
[16]
First Word to FIFO1
t
WFF
11
CY7C43644
CY7C43664
CY7C43684
Switching Waveforms
(continued)
Serial Programming of the Almost -Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
[17]
CLKA
MRS1
,
MRS2
t
FSS
t
FSH
SPM
FFA/IRA
t
FSS
t
SPH
t
SENS
t
SENH
t
FS1/SEN
FS0/SD
[18]
t
SDS
AFA Offset (Y1) MSB
t
SDH
t
SDS
AEA Offset (X2) LSB
CLKB
FFB/
IRB
SENS
t
SENH
t
SKEW1
t
SDH
[16]
t
WFF
t
WFF
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
t
t
CLKH
CLK
t
CLKL
CLKA
FFA/IRA
HIGH
t
ENS
t
ENH
CSA
t
t
ENH
ENS
W/RA
t
t
ENH
ENS
MBA
t
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
ENH
ENA
t
t
DS
DH
A
0–35
Notes:
17. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
18. Programmable offsets are written serially to the SD input in the order AFA
19. Written to FIFO1.
W1
[19]
offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).
W2
[19]
12
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