Compaq Deskpro 4000, Deskpro 6000 Technical Reference Manual

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Technical Reference Guide

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Deskpro 4000 and 6000 Personal Computers featurin

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Technical Reference Guide

NOTICE

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Technical Reference Guide

Compaq Deskpro 4000 and 6000 Personal Computers f eaturing the Pentium I I Processor

First Edi tion - Octobe r 1997

Document Number DSK-113A/1097

for

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October1997

Technical Reference Guide

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition –- October1997

Technical Reference Guide

CHAPTER 1 INTRODUCTION.............................................................................................................

1.1 ABOUT THIS GUIDE........................................................................................................... 1-1

1.1.1 USING THIS GUIDE..................................................................................................... 1-1

1.1.2 ADDITIONAL INFORMATION SOURCES.................................................................. 1-1

1.2 NOT ATIONAL CONVENTIONS..........................................................................................1-2

1.2.1 VALUES........................................................................................................................ 1-2

1.2.2 RANGES........................................................................................................................ 1-2

1.2.3 SIGNAL LABELS.......................................................................................................... 1-2

1.2.4 REGISTER NOTATION AND USAGE ......................................................................... 1-2

1.2.5 BIT NOTATION............................................................................................................ 1-2

1.3 C OMMON ACRONYMS AND ABBREVIATIONS.............................................................. 1-3

CHAPTER 2 SYSTE M OVERVIEW .....................................................................................................

2.1 INTRODUCTION..................................................................................................................2-1

2.2 FEATURES...........................................................................................................................2-2

2.2.1 STANDARD FEATURES..............................................................................................2-2

2.2.2 SERIES DIFFERENCES................................................................................................ 2-3

2.2.3 OPTIONS.......................................................................................................................2-3

2.3 MECHANICAL DESIGN...................................................................................................... 2-4

2.3.1 CABINET LAYOUTS.................................................................................................... 2-4

2.3.2 CHASSIS LAYOUTS..................................................................................................... 2-6

2.3.3 SYSTEM BOARD LAYOUTS....................................................................................... 2-7

2.4 SYSTEM ARCHITECTURE..................................................................................................2-8

2.4.1 PENTIUM II PROCESSOR.......................................................................................... 2-10

2.4.2 MEMORY.................................................................................................................... 2-10

2.4.3 SUPPORT CHIPSET.................................................................................................... 2-11

2.4.4 NETWORK INTERFACE............................................................................................2-11

2.4.5 GRAPHICS SUBSYSTEM ........................................................................................... 2-12

2.4.6 MASS STORAGE........................................................................................................ 2-12

2.4.7 SERIAL AND PARALLEL INTERFACES .................................................................. 2-12

2.4.8 UNIVERSAL SERIAL BUS INTERFACE................................................................... 2-13

2.5 SPECIFICATIONS.............................................................................................................. 2-14

CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM........................................................................

3.1 INTRODUCTION..................................................................................................................3-1

3.2 PENT IUM II-BASED PROCESSOR/MEMORY SUBSYSTEM ........................................... 3-2

3.2.1 PENTIUM II PROCESSOR............................................................................................ 3-3

3.2.2 SYSTEM MEMORY......................................................................................................3-6

3.2.3 SUBSYSTEM CONFIGURATION...............................................................................3-10

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October1997

iii

Technical Reference Guide

CHAPTER 4 SYSTEM SUPPORT.........................................................................................................

4.1 INTRODUCTION..................................................................................................................4-1

4.2 PCI BUS OVERVIEW ........................................................................................................... 4-2

4.2.1 PCI CONNECTOR ......................................................................................................... 4-3

4.2.2 PCI BUS MASTER ARBITRATION..............................................................................4-4

4.2.3 PCI BUS TRANSACTIONS...........................................................................................4-5

4.2.4 OPTION ROM MAPPING ............................................................................................. 4-8

4.2.5 PCI INTERRUPT MAPPING.........................................................................................4-9

4.2.6 PCI CONFIGURATION............................................................................................... 4-10

4.3 AGP BUS OVERVIEW ....................................................................................................... 4-11

4.3.1 AGP CONFIGURATION............................................................................................. 4-12

4.4 ISA BUS OVERVIEW......................................................................................................... 4-13

4.4.1 ISA CONNECTOR ...................................................................................................... 4-14

4.4.2 ISA BUS TRANSACTIONS......................................................................................... 4-15

4.4.3 DIRECT MEMORY ACCESS......................................................................................4-17

4.4.4 INTERRUPTS.............................................................................................................. 4-20

4.4.5 INTERVAL TIMER ..................................................................................................... 4-24

4.4.6 ISA CONFIGURATION............................................................................................... 4-24

4.5 SYSTEM CLOCK DISTRIBUTION.................................................................................... 4-25

4.6 REAL-T I ME C LOCK AND C ONFIGURATION MEMORY............................................... 4-26

4.6.1 CONFIGURATION MEMORY BYTE DEFINITI ONS ................................................ 4-27

4.7 I / O MAP AND REGI ST E R ACCESSING............................................................................ 4-43

4.7.1 SYSTEM I/O MAP ......................................................................................................4-43

4.7.2 87307 I/O CONTROLLER CONFIGURATION........................................................... 4-44

4.8 SYST EM MANAGEMENT SUPPORT ............................................................................... 4-46

4.8.1 FLASH ROM WRITE PROTECT................................................................................ 4-47

4.8.2 PASSWORD PROTECTION........................................................................................ 4-47

4.8.3 I/O SECURITY............................................................................................................4-48

4.8.4 USER SECURITY........................................................................................................ 4-48

4.8.5 TEMPERATURE SENSING........................................................................................ 4-49

4.8.6 COVER LOCK............................................................................................................. 4-49

4.8.7 COVER REMOVAL SENSOR ..................................................................................... 4-50

4.8.8 POWER MANAGEMENT ........................................................................................... 4-51

CHAPTER 5 INPUT/OUTPUT INTERFACES.....................................................................................

5.1 INTRODUCTION..................................................................................................................5-1

5.2 ENHANCED

IDE INTERFACE ............................................................................................ 5-1

5.2.1 IDE PROGRAMMING................................................................................................... 5-1

5.2.2 IDE CONNECT OR ........................................................................................................ 5-8

5.3 DISKETTE DRIVE INTERFACE..........................................................................................5-9

5.3.1 DISKETTE DRIVE PROGRAMMING........................................................................ 5-10

5.3.2 DISKETTE DRIVE CONNECTOR.............................................................................. 5-13

5.4 SERIAL INTERFACES....................................................................................................... 5-14

5.4.1 RS-232 INTERFACE ................................................................................................... 5-14

5.4.2 IrDA INTERFACE....................................................................................................... 5-15

5.4.3 SERIAL INTERFACE PROGRAMMING....................................................................5-16

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition –- October1997

Technical Reference Guide

5.5 PARALLEL INTERFACE................................................................................................... 5-21

5.5.1 STANDARD PARALLEL PORT MODE..................................................................... 5-21

5.5.2 ENHANCED PARALLEL PORT MODE..................................................................... 5-22

5.5.3 EXTENDED C APABILIT IES PORT MODE............................................................... 5-22

5.5.4 PARALLEL INTERFACE PROGRAMMING.............................................................. 5-23

5.5.5 PARALLEL INTERFACE CONNECT OR ................................................................... 5-27

5.6 KEYBOARD/POINTING DEVICE INTERFACE ............................................................... 5-28

5.6.1 KEYBOARD INTERFACE OPERATION ................................................................... 5-28

5.6.2 POINTING DEVICE INTERFACE OPERATION.......................................................5-30

5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING ......................... 5-30

5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR ................................ 5-34

5.7 ETHERNET INTERFACE...................................................................................................5-35

5.7.1 NIC CONFIGURATION/CONTROL ........................................................................... 5-36

5.7.2 NIC CONNECTORS....................................................................................................5-36

5.8 UNIVERSAL SERIAL BUS INTERFACE........................................................................... 5-37

5.8.1 USB CONFIGURATION..............................................................................................5-37

5.8.2 USB CONTROL...........................................................................................................5-38

5.8.3 USB CONNECTOR ..................................................................................................... 5-38

5.9 ULTRA SCSI ADAPTE R .................................................................................................... 5-39

5.9.1 SCSI CONNECTOR S ................................................................................................. 5-40

CHAPTER 6 AUDIO SUBSYSTEM ......................................................................................................

6.1 INTRODUCTION..................................................................................................................6-1

6.2 FUNCTI ONAL DESC RIPT ION............................................................................................. 6-2

6.2.1 PCM AUDIO PROCESSING..........................................................................................6-4

6.2.2 FM SYNTHESIS AUDIO PROCESSING....................................................................... 6-7

6.3 AUDIO SUBSYSTEM PROGRAMMING .............................................................................6-8

6.3.1 CONFIGURATION........................................................................................................ 6-8

6.3.2 CONTROL..................................................................................................................... 6-9

6.4 SPECIFICATIONS .............................................................................................................. 6-11

CHAPTER 7 POWER SUPPLY AND DIST RIBUTION.......................................................................

7.1 INTRODUCTION..................................................................................................................7-1

7.2 POWE R SUPPLY ASSEMBLY/CONTROL .......................................................................... 7-1

7.2.1 POWER SUPPLY ASSE MB L Y..................................................................................... 7-2

7.2.2 POWER CONTROL.......................................................................................................7-3

7.3 POWER DISTRIBUTION...................................................................................................... 7-4

7.3.1 3.5/5/12 VDC DISTRIBUTION......................................................................................7-4

7.3.2 LOW VOLTAGE DISTRIBUTION................................................................................ 7-5

7.4 SI GNAL DIST RIBUTION..................................................................................................... 7-6

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October1997

Technical Reference Guide

CHAPTER 8 BIOS ROM .......................................................................................................................

8.1 INTRODUCTION..................................................................................................................8-1

8.2 BOOT FUNCTIONS.............................................................................................................. 8-2

8.2.1 BOOT BLOCK...............................................................................................................8-2

8.2.2 QUICKBOOT.................................................................................................................8-2

8.2.3 SILENTBOOT ............................................................................................................... 8-2

8.3 AC CESSING CONFIGURATION MEMORY ....................................................................... 8-3

8.3.1 ACCESSING CMOS...................................................................................................... 8-3

8.3.2 SETTING DEFAULT PARAMETERS.......................................................................... 8-3

8.3.3 ACCESSING CMOS FEATURE BITS........................................................................... 8-4

8.4 C LIE NT MANAGEMENT SUPPORT................................................................................... 8-5

8.4.1 SYSTEM ID................................................................................................................... 8-7

8.4.2 SYSTEM INFORMATION TABLE ............................................................................... 8-7

8.4.3 DRIVE FAULT PREDICTION.....................................................................................8-12

8.4.4 DIMM SUPPORT.........................................................................................................8-13

8.4.5 SECURITY FUNCTIONS............................................................................................ 8-15

8.4.6 ACCESSING CMOS FEATURE BITS......................................................................... 8-16

8.5 PNP SUPPORT.................................................................................................................... 8-17

8.6 POWE R MANAGEME NT SUPPORT ................................................................................. 8-18

APPENDIX A ERROR MESSAGES AND CODES...............................................................................

A.1 INTRODUCTION.................................................................................................................A-1

A.2 POWE R-ON MESSAGES..................................................................................................... A-1

A.3 BEE P C ODE MESSAGES.................................................................................................... A-1

A.4 POWE R-ON SELF T E ST (POST) MESSAGE S.................................................................... A-2

A.5 PROCE SSOR ERROR MESSAGES A.6 ME MORY ERROR MESSAGES (2

(1XX-XX

XX-XX

A.7 KE YBOARD ERROR MESSAGES (30 A.8 PRINT E R ERROR MESSAGES (4

XX-XX

A.9 VI DE O ( GRAPHICS) ERROR MESSAGES (5 A.10 DISKETTE DRIVE ERROR MESSAGES (6 A.11 SERIAL INTERFACE ERROR MESSAGES (11 A.12 MODEM COMMUNICATIONS ERROR MESSAGES (12 A.13 HARD DRIVE ERROR MESSAGES (17 A.14 HARD DRIVE ERROR MESSAGES (19 A.15 VIDEO (GRAPHICS) ERROR MESSAGES (24 A.16 AUDIO ERROR MESSAGES (3206A.17 NETWORK INTERFACE E RROR MESSAGES (60 A.18 SCSI INTERFACE E RROR MESSAGES (65 A.19 POINTING DEVICE INTERFACE ERROR MESSAGES (8601-

)....................................................................... A-3

) ........................................................................... A-4

)....................................................................... A-4

X-XX

)............................................................................ A-5

).......................................................... A-5

XX-XX

) ......................................................... A-6

XX-XX

)................................................... A-6

XX-XX

).................................... A-7

XX-XX

)............................................................... A-8

XX-XX

)............................................................... A-9

XX-XX

) .................................................... A-9

XX-XX

)......................................................................... A-10

) ........................................... A-10

XX-XX

, 66XX-XX, 67XX-XX) ....................... A-11

XX-XX

).............................. A-11

A.20 CEMM PRIVILEDGED OPS ERROR MESSAGES........................................................ A-12

A.21 CEMM EXCEPT I ON E RROR MESSAGES ................................................................... A-12

APPENDIX B ASCII CHARACTER SET .............................................................................................

B.1 INTRODUCTION..................................................................................................................B-1

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition –- October1997

Technical Reference Guide

APPENDIX C KEYB O ARD ...................................................................................................................

C.1 INTRODUCTION..................................................................................................................C-1

C.2 KEYSTROKE PROCESSING................................................................................................C-2

C.2.1 TRANSMISSIONS TO THE SYSTEM ..........................................................................C-3

C.2.2 KEYBOARD LAYOUTS...............................................................................................C-4

C.2.3 KEYS .............................................................................................................................C-7

C.2.4 KEYBOARD COMMANDS.........................................................................................C-10

C.2.5 SCAN CODES.............................................................................................................C-10

C.3 SCANNER DESCRIPTION.................................................................................................C-14

C.3.1 SCANNER OPERATION.............................................................................................C-15

C.3.2 SCANNER INTERFACE.............................................................................................C-18

C.3.3 SCANNER SPECIFICATIONS/REQUIREMENTS ...................................................... C-20

APPENDIX D MATROX MY ST IQUE GRAPHICS CARD .................................................................

D.1 INTRODUCTION.................................................................................................................D-1

D.2 FUNCTI ONAL DESC RIPT ION............................................................................................ D-2

D.3 DI SPLAY CONFIGURATIONS ........................................................................................... D-3

D.4 MONI T OR POWER MANAGEME NT C ONT ROL .............................................................. D-3

D.5 C ONNE C T ORS.................................................................................................................... D-4

APPENDIX E MATROX MILLENNIUM II GRAPH ICS CARD ........................................................

E.1 INTRODUCTION..................................................................................................................E-1

E.2 FUNCTIONAL DE SC RIPTI ON.............................................................................................E-2

E.3 DISPLAY CONFI GURATIONS ............................................................................................E-3

E.4 PROGRAMMING..................................................................................................................E-4

E.4.1 CONFIGURATION........................................................................................................ E-4

E.4.2 CONTROL..................................................................................................................... E-4

E.5 MONITOR POWER MANAGEMENT CONTROL ............................................................... E-6

E.6 CONNECTORS.....................................................................................................................E-6

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October1997

vii

Technical Reference Guide

LIST OF FIGURES

IGURE

2–1. C 2–2. C 2–3. C 2–4. D 2–5. M 2–6. S 2–7. S 2–8. P

3–1. P 3–2. P 3–3. S

4–1. PCI B 4–2. PCI B 4–3. T 4–4. PCI C 4–5. AGP B 4–6. ISA B 4–7. ISA E 4–8. M 4–9. C

5–1. 40-P 5–2. 34-P 5–3. S 5–4. S 5–5. IRDA I 5–6. P

OMPAQ DESKPRO ABINET LAYOUT ABINET LAYOUT ESKTOP CHASSIS LAYOUT

INITOWER CHASSIS LAYOUT YSTEM BOARD LAYOUT YSTEM ARCHITECTURE ENTIUM

ENTIUM ENTIUM

YSTEM MEMORY MAP

YPE

ONFIGURATION MEMORY MAP

ERIAL INTERFACES BLOCK DIAGRAM ERIAL INTERFACE CONNECTOR (MALE

ARALLEL INTERFACE CONNECTOR (FEMALE

II SEC C

II-B II P

US DEVICES AND FUNCTIONS

US CONNECTOR

0 C

ONFIGURATION CYCLE

ONFIGURATION SPACE MAP

US CONNECTOR

US BLOCK DIAGRAM

XPANSION CONNECTOR

ASKABLE INTERRUPT PROCESSING

IDE C

IN IN DISKETTE DRIVE CONNECTOR

NTERFACE CONNECTOR (FEMALE MINI

5–7. 8042-TO-K 5–8. K 5–9. E 5–10. E 5–11. E 5–12. U 5–13. SCSI A 5–14. U

EYBOARD OR POINTING DEVICE INTERFACE CONNECTOR THERNET INTERFACE BLOCK DIAGRAM

THERNET THERNET

NIVERSAL SERIAL BUS CONNECTOR (ONE OF TWO AS VIEWED FROM REAR OF CHASSIS

DAPTER

SCSI C

LTRA

4000 D , F , R

ARTRIDGE AND HEAT SINK

ASED PROCESSOR/MEMORY SUBSYSTEM ARCHITECTURE

ROCESSOR INTERNAL ARCHITECTURE

ESKTOP PERSONAL COMP UTER WITH MONITOR

RONT VIEW

EAR VIEW

, C

, B

.......................................................................................2-4

.........................................................................................2-5

, T

OP VIEW

, L

OMPONENT SIDE

LOCK DIAGRAM

..............................................................................2-6

EFT SIDE VIEW

................................................................2-6

.....................................................................2-7

........................................................................2-9

.................................................................. 2-10

............................................................3-3

.......................................................................................................3-9

.....................................................................................4-2

(5V T

)...................................................................................... 4-3

YPE

........................................................................................4-6

......................................................................................4-7

...................................................................................................4-11

................................................................................................4-13

..........................................................................................4-14

, B

LOCK DIAGRAM

.................................................... 4-20

......................................................................................4-26

ONNECTOR

. ................................................................................................. 5-8

.............................................................................. 5-13

............................................................................. 5-14

DB-9

AS VIEWED FROM REAR OF CHASSIS

-DIN-T

DB-25

EYBOARD TRANSMISS I ON OF CODE EDH

YPE AS VIEWED FROM REAR OF CHASSIS

AS VIEWED FROM REAR OF CHASSIS

, T

IMING DIAGRAM

............................................... 5-34

......................................................................... 5-35

AUI C

ONNECTOR

RJ-45 C

, B

LOCK DIAGRAM

ONNECTOR

(DB-15,

VIEWED FROM REAR

)........................................... 5-36

......................................................................................5-36

.................................................................................. 5-39

(50-

PIN, AS VIEWED FROM REAR OF CHASSIS

..........................2-1

...............................3-2

)........... 5-14

)5-15

).. 5-27

............................ 5-28

)... 5-38

)............................ 5-40

F F F F F F

F F F F

viii

6–1. A

IGURE IGURE IGURE IGURE IGURE IGURE

IGURE IGURE IGURE IGURE

6–2. A 6–3. DAC O 6–4. A 6–5. FM S 6–6. A

7–1. P 7–2. P 7–3. L 7–4. S

UDIO SUBSYSTEM BLOCK DIAGRAM NALOG SIGNAL SAMPLING/QUANTIZING

PERATION

UDIO SUBSYSTEM-TO

YNTHESIS PATCH

UDIO CAR-TO

OWER DISTRIBUTION AND CONTROL OWER CABLE DIAGRAM OW VOLTAGE SUPPLY, BLOCK DIAGRAM IGNAL DISTRIBUTION DIAGRAM

.............................................................................................................6-5

-ISA B

PCM A

......................................................................................................6-7

-ISA B

FM A

UDIO DATA FORMAT

..................................................................................................7-4

.......................................................................................7-6

Compaq Deskpro 4000 and 6000 Personal Computers featuring the Pentium II Processor

Firs t Edition –- October1997

................................................................................6-3

..........................................................................6-4

UDIO DATA FORMATS

/ B

YTE ORDERING

..............6-6

..........................................................6-7

, B

LOCK DIAGRAM

....................................................7-1

.........................................................................7-5

Technical Reference Guide

IGURE

C–1. K C–2. K

EYSTROKE PROCESSING ELEMENTS EYBOARD-TO-SYSTEM TRANSMISS I ON OF CODE 58H

C–3. U.S. E C–4. N

ATIONAL

C–5. U.S. E C–6. N

ATIONAL WINDOWS

C–7. U.S. E C–8. N C–9. S C–10. S

D–1. M D–2. M

ATIONAL WINDOWS

CANNER ELEMENTS

CANNER OPERA TION FLOW CHART

ATROX MYSTIQUE

ATROX MYSTIQUE GRAPHICS CARD BLOCK DIAGRAM

D–3. VGA M D–4. VGA P D–5. G

E–1. M E–2. M

RAPHICS MEMORY EXPANSION CONNECTORS

ATROX MILLENNIUM ATROX

E–3. VGA M E–4. G

RAPHICS MEMORY EXPANSION CONNECTORS

NGLISH

NGLISH WINDOWS

(101-KEY) K

(102-KEY) K

EYBOARD KEY POSITIONS

(101W-KEY) K

(102W-KEY) K

NGLISH WINDOWS

(101WE-KEY) K

(102WE-KEY) K

, B

LOCK DIAGRAM

PCI G

RAPHICS CARD LAYOUT (COMPAQ P/N

ONITOR CONNECTOR

ASS-THROUGH CONNECTOR

, (F

EMALE

II AGP G

MGA M

ONITOR CONNECTOR

ILLENNIUM GRAPHICS CARD BLOCK DIAGRAM

, (F

EMALE

, B

LOCK DIAGRAM

....................................................C-2

, T

IMING DIAGRAM

..........................C-3

.......................................................C-4

............................................................C-4

EYBOARD KEY POSITIONS

...................................C-5

........................................C-5

.................................C-6

......................................C-6

..........................................................................C-14

..............................................................................C-16

007412-001)............... D-1

.................................................... D-2

DB-15,

AS VIEWED FROM REAR

(VSFC) (26-P

IN HEADER

)......................................... D-4

). ........................... D-4

................................................................ D-5

RAPHICS CARD LAYOUT (COMPAQ P/N

007448-001)............ 1

........................................... 2

DB-15,

AS VIEWED FROM REAR

)................................. 6

..................................................................... 7

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October1997

Technical Reference Guide

1–1. A

ABLE

CRONYMS AND ABBREVIATIONS

LIST OF TABLES

.......................................................................................1-3

2–1. A

ABLE

2–2. S

ABLE

2–3. G

ABLE

2–4. E

ABLE

2–5. E

ABLE

2–6. P

ABLE

2–7. D

ABLE

2–8. 8X CD-ROM D

ABLE

2–9. S

ABLE

3–1. P

ABLE

3–2. P

ABLE

3–3. SW2 BUS/C

ABLE

3–4. SDRAM P

ABLE

3–5. SPD A

ABLE

3–6. H

ABLE

4–1. PCI B

ABLE

4–2. PCI B

ABLE

4–3. PCI D

ABLE

4–4. PCI F

ABLE

4–5. PCI D

ABLE

4–6. PCI/ISA B

ABLE

4–7. AGP B

ABLE

4–8. PCI/AGP B

ABLE

4–9. ISA E

ABLE

4–10. D

ABLE

4–11. DMA P

ABLE

4–12. DMA C

ABLE

4–13. M

ABLE

4–14. M

ABLE

4–15. I

ABLE

4–16. I

ABLE

4–17. C

ABLE

4–18. C

ABLE

4–19. S

ABLE

4–20. 87307 I/O C

ABLE

4–21. S

ABLE

RCHITECTURAL COMPARISON

UPPORT CHIPSETS

RAPHICS SUBSYSTEM COMPARISON NVIRONMENTAL SPECIFICATIONS LECTRICAL SPECIFICATIONS HYSICAL SPECIFICATIONS

ISKETTE DRIVE SPECIFICATIONS

TANDARD HARD DRIVE SPECIFICATIONS

ROCESSOR/MEMORY ARCHITECTURAL HIGHLIGHTS

ENTIUM

OST

YSTEM MANAGEMENT CONTROL REGISTERS

II M

ORE SPEED POSITIONS TO

ERFORMANCE TIMES

DDRESS MAP

/PCI B

RIDGE CONFIGURATION REGISTERS

US CONNECTOR PINOUT US MASTERING DEVICES EVICE CONFIGURATION ACCESS

UNCTION CONFIGURATION ACCES

EVICE IDENTIFICATION

RIDGE CONFIGURATION REGISTERS

US CONNECTOR PINOUT

RIDGE CONFIGURATION REGISTERS

XPANSION CONNECTOR PINOUT

EFAULT

ASKABLE INTERRUPT PRIORITIES AND ASSIGNMENTS

NTERVAL TIMER FUNCTIONS NTERVAL TIMER CONTROL REGISTERS

LOCK GENERATION AND DISTRIBUTION ONFIGURATION MEMORY

YSTEM

DMA C

AGE REGISTER ADDRESSES

ONTROLLER REGISTERS

ASKABLE INTERRUPT CONTROL REGISTERS

I/O MAP...........................................................................................................4-43

..........................................................................................................2-11

RIVE SPECIFICATIONS

ICROPROCESSOR BUS/CORE SPEED SWITCH SETTINGS

(SDRAM DIMM).................................................................................3-8

HANNEL ASSIGNMENTS

ONTROLLER PN

.............................................................................................2-8

................................................................................ 2-12

....................................................................................2-14

...........................................................................................2-14

...............................................................................................2-14

.....................................................................................2-15

................................................................................ 2-15

......................................................................... 2-16

GPIO A

SSIGNMENTS

............................................................................................3-6

(440LX, D

............................................................................................4-3

...........................................................................................4-4

................................................................................4-6

..............................................................................4-7

.............................................................................................4-8

(82371, F

.........................................................................................4-11

(440LX, F

............................................................................... 4-14

....................................................................... 4-17

................................................................................. 4-18

......................................................................................4-19

.................................................................. 4-21

.........................................................................................4-24

........................................................................... 4-24

........................................................................ 4-25

(CMOS) MAP....................................................................... 4-27

P S

TANDARD CONTROL REGISTERS

................................................................... 4-46

............................................................3-1

....................................3-5

...................................................3-5

0)................................... 3-10

EVICE

UNCTION

0).................................. 4-10

1) ............................... 4-12

.................................................... 4-21

........................................ 4-44

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition –- October1997

5–1. IDE PCI C

ABLE

5–2. IDE B

ABLE

5–3. IDE ATA C

ABLE

5–4. IDE C

ABLE

5–5. 40-P

ABLE

5–6. D

ABLE

5–7. D

ABLE

5–8. 34-P

ABLE

5–9. DB-9 S

ABLE

5–10. IRDA DIN C

ABLE

5–11. S

ABLE

5–12. S

ABLE

5–13. P

ABLE

5–14. P

ABLE

5–15. DB-25 P

ABLE

5–16. 8042-TO-K

ABLE

5–17. K

ABLE

5–18. CPU C

ABLE

5–19. K

ABLE

5–20. USB I

ABLE

5–21. USB C

ABLE

5–22. USB C

ABLE

5–23. U

ABLE

ONFIGURATION REGISTERS

US MASTER CONTROL REGISTERS

ONTROL REGISTERS

ONTROLLER COMMANDS

IDE C

IN ISKETTE DRIVE CONTROLLER CONFIGURATION REGISTERS ISKETTE DRIVE CONTROLLER REGISTERS

IN DISKETTE DRIVE CONNECTOR PINOUT

ERIAL INTERFACE CONFIGURATION REGISTERS ERIAL INTERFACE CONTROL REGISTERS ARALLEL INTERFACE CONFIGURATION REGISTERS ARALLEL INTERFACE CONTROL REGISTERS

EYBOARD/MOUSE INTERFACE CONFIGURATION REGISTERS

EYBOARD/POINTING DEVICE CONNECTOR PINOUT

LTRA

ONNECTOR PINOUT

ERIAL CONNECTOR PINOUT

ONNECTOR PINOUT

ARALLEL CONNECTOR PINOUT

EYBOARD COMMANDS

OMMANDS TO THE

NTERFACE CONFIGURATION REGISTERS

ONTROL REGISTERS ONNECTOR PINOUT

SCSI C

ONNECTOR PINOUT

8042...................................................................................... 5-32

.............................................................................................5-38

..............................................................................................5-38

................................................................................5-2

.............................................................................5-2

.........................................................................................5-3

..........................................................................................5-6

.......................................................................................5-8

....................................................................... 5-11

................................................................... 5-13

................................................................................... 5-14

....................................................................................5-15

.............................................................. 5-16

........................................................................ 5-17

......................................................... 5-23

................................................................... 5-24

.......................................................................... 5-27

.................................................................................. 5-29

........................................................ 5-34

................................................................. 5-37

....................................................................................5-40

Technical Reference Guide

............................................. 5-10

........................................... 5-30

6–1. A

ABLE

6–2. A

ABLE

6–3. C

ABLE

6–4. E

ABLE

6–5. FM S

ABLE

6–6. A

ABLE

7–1. P

ABLE

8–1.

ABLE

8–1. PNP BIOS F

ABLE

8–2. APM BIOS F

ABLE

A–1. P

ABLE

A–2. B

ABLE

A–3. P

ABLE

A–4. P

ABLE

A–5. M

ABLE

A–6. K

ABLE

A–7. P

ABLE

A–8. V

ABLE

A–9. D

ABLE

A–10. S

ABLE

A–11. S

ABLE

A–12. H

ABLE

A–13. H

ABLE

A–14. H

ABLE

A–15. A

ABLE

UDIO MODE DIFFERENCES UDIO SUBSYSTEM

OMPATIBILITY MODE AUDIO MIXER CONTROL REGISTER MAPPING

XTENDED MODE AUDIO MIXER CONTROL REGISTER MAPPING

YNTHESIZER CONTROL REGISTER MAPPING

UDIO SUBSYSTEM SPECIFICATIONS

OWER SUPPLY ASSEMBLY SPECIFICATIONS

P C

LIENT MANAGEMENT FUNCTIONS

OWER-ON MESSAGES

EEP CODE MESSAGES OWER-ON SELF TEST ROCESSOR ERROR MESSAGES

EMORY ERROR MESSAGES

EYBOARD ERROR MESSAGES

RINTER ERROR MESSAGES

IDEO (GRAPHICS ISKETTE DRIVE ERROR MESSAGES

ERIAL INTERFACE ERROR MESSAGES ERIAL INTERFACE ERROR MESSAGES

ARD DRIVE ERROR MESSAGES ARD DRIVE ERROR MESSAGES ARD DRIVE MESSAGES UDIO ERROR MESSAGES

I/O MAP..............................................................................................6-9

UNCTIONS

) E

...............................................................................................6-6

.....................................6-9

.......................................... 6-10

................................................................ 6-10

................................................................................. 6-11

........................................................................7-2

(INT15)................................................................. 8-5

.....................................................................................................8-17

(INT15) ..................................................................................... 8-19

..................................................................................................... A-1

(POST) M

ESSAGES

........................................................................ A-2

......................................................................................... A-3

............................................................................................. A-4

.......................................................................................... A-4

.............................................................................................. A-5

RROR MESSAGES

.............................................................................. A-5

.................................................................................. A-6

............................................................................. A-6

............................................................................. A-7

...................................................................................... A-8

...................................................................................... A-9

................................................................................................. A-9

............................................................................................. A-10

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October1997

Technical Reference Guide

A–16. N

ABLE

A–17. SCSI I

ABLE

A–18. P

ABLE

A–19. CEMM P

ABLE

A–20. CEMM E

ABLE

ETWORK INTERFACE ERROR MESSAGES

NTERFACE ERROR MESSAGES

OINTING DEVICE INTERFACE ERROR MESSAGES

RIVILEGED OPS ERROR MESSAGES

XCEPTION ERROR MESSAGES

...................................................................... A-10

............................................................................. A-11

........................................................... A-11

.................................................................. A-12

......................................................................... A-12

B–1. ASCII C

ABLE

C–1. K

ABLE

C–2. K

ABLE

C–3. S

ABLE

C–4. S

ABLE

C–5. S

ABLE

D–1. G

ABLE

D–2. M

ABLE

D–3. DB-15 M

ABLE

D–4. VGA P

ABLE

D–5. G

ABLE

E–1. E

ABLE

E–2. MGA 2064W PCI C

ABLE

E–3. S

ABLE

E–4. M

ABLE

E–5. DB-15 M

ABLE

E–6. G

ABLE

EYBOARD-TO-SYSTEM COMMANDS

EYBOARD SCAN CODES CANNER PERFORMANCE CHART CANNER CANNER SPECIFICATIONS

RAPHICS CONFIGURATION DISPLAY MODES

ONITOR POWER MANAGEMENT CONDITIONS

RAPHICS MEMORY EXPANSION CONNECTOR PINOUT

XTENDED

TANDARD

ONITOR POWER MANAGEMENT CONDITIONS

RAPHICS MEMORY EXPANSION CONNECTOR PINOUT

HARACTER SET

....................................................................................................B-1

.................................................................................................C-11

I/F S

.....................................................................................................C-18

IGNALS

...............................................................................................C-20

ONITOR CONNECTOR PINOUT

ASSTHROUGH CONNECTOR

VGA D

ONITOR CONNECTOR PINOUT

VGA M

ISPLAY MODES

ONFIGURATION SPACE REGISTERS

I/O M

ODE

APPING

...............................................................................C-10

.....................................................................................C-17

...................................................................... D-3

.................................................................. D-3

............................................................................. D-4

(VSFC) P

........................................................... D-4

INOUT

....................................................... D-5

.......................................................................................E-3

.......................................................E-4

...............................................................................E-4

...................................................................E-6

..............................................................................E-6

........................................................E-7

Compaq Deskpro 4000 and 6000 Personal Computers

xii

featuring the Pentium II Processor

Firs t Edition –- October1997

Chapter 1 INTRODUCTION

1. Chapter 1 INTRODUCTION

Technical Reference Guide

1.1

ABOUT THIS G UIDE

This guide provides technical information about the Compaq Deskpro 4000 and 6000 Personal Computers that employ the Pentium II Processor.

NOTE:

xxx (systems intr oduced September 1997). Pentium II-based systems introduced in July of 1997 (system board PCA # 006650-xxx) are mentioned in chapter 2 of this document but use an earlier system architecture that is discussed in detail in the Compaq Deskpro 4000/6000 Personal Computers Technical Reference Guide (document # 299A/0996, First Edition, September 1996).

This guide specifically covers systems employing system board PCA# 006627-

1.1.1 USING THIS G U ID E

This guide consists of chapters and appendices. The chapters primarily describe the hardware and firmware elements contained within the chassis and specifically deal with the system board and the power supply assembly. The appendices contain general information about standard peripheral devices such as the keyboard as well as separate audio or other interface cards, as well as other general information in tabular format.

1.1.2 ADDITIONAL INFORMATION SOURCES

This guide does not describe in detail other manufacturer’s components used in the product covered. For more information on individual commercial-off-the-shelf (COTS) components refer to the indicated manufacturers’ documentation. Hardcopy documentation sources:

♦ The Lotus/Intel/Microsoft Expanded Memory Specification, Ver. 4.0 ♦ PCI Local Bus Specification Revision 2.1 ♦ Extended Industry Standard Architecture Expansion Bus Technical Reference Guide,

p/n 130584, Second Edition, Compaq Computer Corporation

♦ Compaq Basic Input/Out System (BIOS) Technical Reference Guide

Doc.# 074A/0693, Fourth Edition, Compaq Computer Corporation

Online information sources:

♦ Compaq Computer Corporation: http://www.compaq.com ♦ Intel Corporation: http://www.intel.com ♦ National Semiconductor: http://www.national.com ♦ Matrox Graphics Inc.: http://www.matrox.com

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition - October1997

1-1

Chapter 1 Introduction

1.2 NOTATIONAL CONVENTIONS

1.2.1 VALUES

Hexadecimal values are indicated by the letter “h” following an alpha-numerical value. Binary values are indicated by the letter “b” following a value of ones and zeros. Memory addresses expressed as “SSSS:OOOO” (SSSS = 16-bit segment, OOOO = 16-bit offset) can be assumed as a hexadecimal value. Values that have no succeeding letter can be as sumed t o be decimal.

1.2.2 RANGES

Ranges or limits for a parameter are shown as a pair of values separated by two dots:

Example: Bits <7..4> = bits 7, 6, 5, and 4.

1.2.3 SIGNAL LABELS

Signal names are indicated using abbreviations, acronyms, or, if possible, the full signal name in all capital letters. Signals that are meant to be active low are indicated with a dash immediately following the name.

1.2.4 REGISTER NOTATION AND USAGE

This guide uses standard Intel naming conventions in discussing the microprocessor’s (CPU) internal registers. Registers that are accessed through programmable I/O using an indexing scheme are indicated using the following format:

03C5.17h

Index port Data port

In th e e xam ple above, reg ist er 03C5.17h i s accessed by writing the index port value 17h to the index address (03C4h), followed by a write to or a read from port 03C5h.

1.2.5 BIT NOTATION

Bit values are labeled with bit <0> representing the least-significant bit (LSb) and bit <7> representing the most-significant bit (MSb) of a byte. Bytes, words, double words, and quad words are typically shown with most-significant portions on the left or top and the leastsignificant portions on the right or bottom respectively.

Compaq Deskpro 4000 and 6000 Personal Computers

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Firs t Edition - October 1997

1.3 COMMON ACRONYMS AND ABBREVIATIONS

Table 1-1 lists the acronyms and abbreviations used in this guide.

Technical Reference Guide

Table 1–1.

Acronyms and Abbreviations

Table 1-1.

Acronyms and Abbreviations

Acronym/Abbreviation Descriptio n

A ampere AC alternating current ACPI Advanced Configuration and Power Interface A/D analog-to-digital AGP Accelerated graphics port API application programming interface APM advanced power management ASIC application-specific integrated circuit AT 1. attention (commands) 2. 286-based PC architecture ATA AT attachment (mode) AVI audio-video interleaved AVGA Advanced VGA BCD binary-coded decimal BIOS basic input/outp ut system bis second/new revision BitBLT bit block transfer BNC Bayonet Neill-Concelman (connector) bps or b/s bits per second BSP Bootstrap processor CAS column address strobe CD compact disk CD-ROM compact disk read-only memory CDS compct disk system CF carry flag CGA color graphics adapter Ch channel CLUT color look-up table (pallete) cm centimeter CMC cache/memory controller CMOS complimentary metal-oxide semiconductor (configuration memory) Cntlr controller codec compressor/decompressor CPQ Compaq CPU central processing unit CRT cathode ray tube CSM Compaq system management / Compaq server management DAA direct access arrangement DAC digital-to-analog converter db decibel DC direct current DCH DOS compatibility hole DDC Display Data Channel DF direction flag

Continued

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition - October1997

1-3

Chapter 1 Introduction

Table 1-1. Acronyms and Abbreviations

Acronym/Abbreviation Descriptio n

DIMM dual inline memory module DIN Deutche IndustriNorm (connector standard) DIP dual inline package DMA direct memory access dpi dots per inch DRAM dynamic random access memory DRQ data request EDID extended display identification data EDO extended data out (RAM type) EEPROM electrically eraseable PROM EGA enhanced graphics adapter EIA Electronic Industry Association EISA extended ISA EPP enhanced parallel port EIDE enhanced IDE ESCD Extended System Configuration Data (format) EV Environmental Variable (data) ExCA Exchangeable Card Architecture FIFO first in / first out FL flag (register) FM frequency modulation FPM fast page mode (RAM type) FPU Floating point unit (numeric or math coprocessor) ft foot GB gigabyte GND ground GPIO general purpose I/O GPOC general purpose open-collector GUI graphics user interface h hexadecimal HW hardware hex hexadecimal Hz hertz IDE integrated drive element IEEE Institute of Electrical and Electronic Engineers IF interrupt flag I/F interface in inch INT interrupt I/O input/output IPL initial program loader IrDA Infra Red Data Association IRQ interrupt request ISA industry standard architecture JEDEC Joint Electron Device Engineering Council Kb / KB kilobits / kilobytes (x 1024 bits / x 1024 bytes) Kb/s kilobits per second kg kilogram KHz kilohertz kv kilovolt

Continued

Compaq Deskpro 4000 and 6000 Personal Computers

1-4

featuring the Pentium II Processor

Firs t Edition - October 1997

Technical Reference Guide

Table 1-1. Acronyms and Abbreviations

Acronym/Abbreviation Descriptio n

lb pound LCD liquid crystal display LED light-emitting diode LIF low insertion force (socket) LSI large scale integration LSb / LSB least significant bit / least significant byte LUN logical unit (SCSI) MMX multimedia extensions MPEG Motion Picture Experts Group ms millisecond MSb / MSB most significant bit / most significant byte mux multiplex MVA motion video acceleration MVW motion video window

NIC network interface card/controller NiCad nickel cadmium NiMH nickel-metal hydride NMI non-maskable interrupt ns nanosecond NT nested task flag NTSC National Television Standards Committee NVRAM non-volatile random access memory OEM original equipment manufacturer OS operating system PAL 1. programmable array logic 2. phase altering line PC personal computer PCI peripheral component interconnect PCM pulse code modulation PCMCIA Personal Computer Memory Card International Association PF parity flag PIN personal identification number POST power-on self test PROM programmable read-only memory PTR pointer RAM random access memory RAS row address strobe rcvr receiver RF resume flag RGB red/green/blue RH Relative humidity RMS root mean square ROM read-only memory RPM revolutions per minute RTC real time clock R/W read/write

variable parameter/value

Continued

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition - October1997

1-5

Chapter 1 Introduction

Table 1-1. Acronyms and Abbreviations

Acronym/Abbreviation Descriptio n

SCSI small co mput er system interface SDRAM Synchronous Dynamic RAM SEC Single Edge-Connector SECAM sequential colour avec memoire (sequential color with memory) SF sign flag SGRAM Synchronous Graphics RAM SIMM single in-line memory module SIT system inform ation table SMI system m anagement interrupt SMM system management mode SMRAM system m anagement RAM SPD serial presence detect SPP standard parallel port SRAM static RAM STN super twist pneumatic SVGA super VGA SW software TAD telephone answering device TAM telephone answering machine TCP tape carrier package TF trap flag TFT thin-film transistor TIA Telecommunications Information Administration TPE twisted pair ethernet TPI track per inch TTL transistor-transistor logic TV television TX transmit UART universal asynchronous receiver/transmitter us / µs microsecond USB Universal Serial Bus UTP unshielded twisted pair Vvolt VESA Video Electronic Standards Association VGA video graphics adapter vib vibrato VLSI very large scale integration VRAM Video RAM Wwatt WRAM Windows RAM ZF zero flag ZIF zero insertion force (socket)

Continued

Compaq Deskpro 4000 and 6000 Personal Computers

1-6

featuring the Pentium II Processor

Firs t Edition - October 1997

Chapter 2 SYSTEM OVERVIEW

Technical Reference Guide

2.1

Chapter 2 SYSTEM O VERVIEW

INTRODUCTION

The Compaq Deskpro 4000 and 6000 Series Personal Computers (Figure 2-1) based on the Pentium II microprocessor include minitower and desktop models designed with an emphasis on speed, storage capacity, and multimedia compatibility to meet the requirements of the business environment. These models feature architectures incorporating the PCI and ISA busses. All models are easily upgradeable and expanda ble to keep pace with th e n eeds of the business environment.

Figure 2–1. Compaq Deskpro 4000 Desktop and Minitower Personal Computers with Monitors

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October 1997

2-1

Chapter 2 System Overview

2.2 FEATURES

This section describes the standard and distinguishing features.

2.2.1 STANDARD FEATURES

The following standard features are included on all models:

♦ Pentium II pr ocessor ♦ 32-/64-MB unbuffered SDRAM ♦ 3.5 in ch , 1. 44-MB diskette drive ♦ Hard drive fault prediction ♦ Serial interfaces (2) ♦ Parallel interface ♦ Acceler ated graphics por t ( AGP) int erface ♦ Universal serial bus interfaces (2) ♦ 10/100 MHz (auto-sensing) network interface controller ♦ IrDA interface ♦ Three or four PC I connect ors ♦ T hree I S A connectors ♦ Compaq Space Saver keyboard w/Windows support ♦ Compaq PS/2-type mouse ♦ APM 1.2 power mana gemen t suppor t ♦ Smart Cover Lock ♦ Plug ’n Play compatible (with ESCD support)

The supported Intelligent Manageability features are listed below:

Configuration Management

Remote ROM Flash RAM Type Data ECC RAM Fault Prediction Memory Change Alert Remote Security DMI BIOS SMART II Hard Drive Ownership Tag Remote Wakeup Asset Tag Monitor Fault Diag. Config. Cntrl. Hardware Remote Shutdown Sys. Serial # UATA Integrity Log. Setup Password Replicated Setup Sys. Manuf./Model Proactive Backup Power-On Password ACPI-Ready Sys. Board Rev. Level Thermal Sensor QuickLock/QuickBlank Dual-State Power Sw. ROM rev. Diskette Boot Cntrl. Failsafe Boot Bloc k ROM Hard Drive Type Data Diskette Write Cntrl.

Asset Management

Monitor Type Data I/O Port En/Dis. Cntrl. Compaq Insight Ed itio n Cable Lock Provision

Fault Management

Security Management

The Intelligent Manageability features provide support for DMI 2.0, Compaq Insight Manager, and Management Solutions Partners.

Compaq Deskpro 4000 and 6000 Personal Computers

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featuring the Pentium II Processor

Firs t Edition - October 1997

2.2.2 SERIES DIFFERENCES

The differences between the Pentium II-based Compaq Deskpro 4000 and th e Pentium II-based Compaq 6000 Series Personal Computers are listed below:

Deskpro 4000 Deskpro 6000

Hard drive interface: EIDE SCSI Graphics Solution: Matrox 1064-SG Matrox Millennium-II

Technical Reference Guide

NOTE:

no. 006650-101.

The di ffe rences listed above do not apply to syst e ms based on system board P CA

2.2.3 EXPANSION OPTIONS

Options for expanding the memory of Compaq Deskpro 4000/6000 Series Personal Computers include:

♦ Memory: 8- MB SDRAM DIMM

16-MB SDRAM DIMM 32-MB SDRAM DIMM 64 MB SDRAM DIMM 128 MB SDRAM DIMM

♦ Gr a p hics: 2-MB SGRAM Module (for Matrox Mystique Graph ics Card)

4-/12-MB WRAM Upgrade Modules (for Matrox Millennium II

Graphics Card)

Compaq Deskpro Computers are easily upgraded and enhanced with peripher a l devices designed to meet PCI and ISA standards. The Compaq Deskpro Personal Computers are compatible with peripherals design for Plug ’n Play operation.

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October 1997

2-3

Chapter 2 System Overview

2.3 MECHANICAL DESIGN

The Compaq Deskpro 4000 Series features two formfactors; desktop and minitower. Thi s section illustrates the layouts used by these two formfactors. In addition, this section includes the layouts of the system boards.

2.3.1 CABINET LAYOUTS

Desktop

1 2 3

Item Function

1 Power Switch 2 Power-On Light 3 Hard Drive Activity Light 4 1/3 Height Internal Drive Bay (3.5” Drive) 5 1.44 MB Diskette Drive (3.5” Drive) 6 ½ Height Drive Bay (3.5” or 5.25” Drive)

2 3

Minitower

Figure 2–2.

Compaq Deskpro 4000 and 6000 Personal Computers

2-4

Cabinet Layout, Front View

featuring the Pentium II Processor

Firs t Edition - October 1997

1 3 5 7

11 13 15 17

Technical Reference Guide

4 6

2 4

12 14 16 18

6 1412 16 18

Desktop

Item Function

1 Smart Cover Lock scre ws 2 Line Voltage Select Switch 3 AC Line In Connector 4 SCSI connector 5 Parallel connector 6 Nework inteface controller link/activity LEDs 7 Network Interface Controller (AUI) connector 8 Network Interface Controller (RJ-45) connector

9 Serial InfraRed connector 10 Universal Serial Bus Port 1 connector 11 Universal Serial Bus Port 2 connector 12 Serial (A) connector 13 Serial (B) connector 14 Keyboard connector 15 Mouse connector 16 Headphones output connector 17 Mic input connector 18 Line output connector 19 Line input connector

9 11 13

15 17 19

Minitower

Figure 2–3. Cabinet Layout, Rear View

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October 1997

2-5

Chapter 2 System Overview

2.3.2 CHASSIS LAYOUTS

PCI Slot 2

Slots On Riser Card,

System Board

Figure 2–4.

Power Supply

Cover Lock Solenoid

PCI Combo Slot 3

PCI Slot 1 ISA Slot 2

ISA Slot 1

Rear View

Desktop Chassis Layout, Top View

Back

Front

Cover Lock Solenoid

Power Supply

Drive Bays

Back

ISA Slot 3 ISA Slot 2

Slots On Riser Card,

Rear View @90°

Figure 2–5.

Compaq Deskpro 4000 and 6000 Personal Computers

2-6

PCI Slot 4 PCI Slot 3

PCI Slot 2

PCI Slot 1 ISA Slot 1

Minitower Chassis La yout, Left Side Vi ew

featuring the Pentium II Processor

Firs t Edition - October 1997

Front

System Board

2.3.3 SYSTEM BOARD LAYOUTS

Technical Reference Guide

1 3

2 7

8159

System Board p/n 006650-xxx [1]

Item Function

1 Top: Line In (audio) connector Bottom: Line Out (audio) connector 2 Top: Mic In (audio) connector Bottom: Headphones Out (audio) connector 3 Top: Mouse I/F connector Bottom: Keyboard I/F connector 4 Top: Serial I/F (B) connector Bottom: Serial I/F (A) connector 5 Top: Universal Serial Bus (port 2) connector Bottom: Universal Serial Bus (port 1) connector 6 InfraRed I/F connector 7 Network Interface connector (RJ-45) 8 Header for AUI network interface connector 9 Top: Parallel I/F connector Bottom: SCSI connector 10 AGP connector 11 SCSI connector 12 CD-ROM audio input connector 13 Power switch/LED header 14 Power supply connector 15 IDE connector (secondary, CD-ROM drive (if installed)) 16 Diskette drive connector 17 IDE connector (primary, hard drive (4000 models)) 18 Alternate fan header (for upgrade processors w/integrated fan) 19 Battery replacement header 20 Pentium II SEC cartridge (in processor slot) 21 DIMM sockets 22 Bus/core ratio select DIP switch 23 Battery 24 Riser (backplane) card sot 25 SI MM sockets 26 Network I/F upgrade connector 27 Frequency select DIP switch 28 Network I/F connector (BNC)

NOTES:

[1] Board p/n 006650-xxx shown he re for identification only. See note at beginning of chapter 1.

23 16

System Board p/n 006627-xxx

12 13

16 17 18 19

Figure 2–6.

System Board Layout, Component Side

Compaq Deskpro 4000 and 6000 Personal Computers

featuring the Pentium II Processor

Firs t Edition – October 1997

2-7

Chapter 2 System Overview

2.4 SYSTEM ARCHITECTURE

Figure 2-7 shows the architecture of the Compaq Deskpro 4000 and 6000 Series Personal Computers based on the Pentium II processor and matched with a support chipset that is complimentary in design. Both minitower and desktop systems share the same basic architecture, which utilizes three main buses: the Host bus, the Peripheral Component Interconnect (PCI) bus, and the In dustry Standard Archit ecture (ISA) bus.

The Host bus provides high performance support for CPU, cache and system memory accesses, and operates at 66 MHz. The PCI bus provides support for the graph i cs subsystem, the EIDE controllers, and expan sion devices designed for high performance. The PCI bus operates at 33 MHz. The ISA bus provides a standard 8-MHz int erface for the input/output (I/O) devices such as the keyboard, diskette drive, serial and parallel interfaces, as well as the addition of 16- or 8bit expansion devices.

These systems a lso incl u d e Accel erated Graphics Port ( AGP) support . T he AGP interface provides a 66-MHz synchronous coupling with th e Host bus for AGP-type graph i cs ada pt er s. The Deskpro 6000 models come standard with a Matrox Millennium-II AGP gra phics board installed.

The Host/PCI and PCI/ISA bridge functions are handled by the specific support chipset matched with the microprocessor employed. The support chipset also provides memory controller and data buffering functions as well as bus control and arbitration functions.

The I/O port functions and diskette drive controller are integrated into the National PC87307 I/O Controller. This component also includes the real time clock and battery-backed configuration memory (CMOS).

Table 2-1 lists the key differences between the Dekspro 4000 and 6000 systems.

Table 2–1.

Architectural Comparison

Table 2-1

Architectur al Com par is on

CD-ROM Type (if installed) 24x CD-ROM (IDE) 24x CD-ROM (IDE) System Memory Standard installed: Expandable to: Active Hard Drive Interface: EIDE SCSI Graphics Subsystem: Matrox MGA-1064SG-based

Deskpro 4000 Deskpro 6000

32 MB

384 MB

PCI Card

w/2 MB SGRAM

32/64 MB

384 MB

Matrox Millennium-II

AGP Card

w/4 MB WRAM

The following subsections provide a description of the key functions and subsystems.

Compaq Deskpro 4000 and 6000 Personal Computers

2-8

featuring the Pentium II Processor

Firs t Edition - October 1997

Pentium II

)

(2)

]

Processor

Technical Reference Guide

64-Bit Host Bus

Audio

NIC

I/F

IDE

Hard Drive

32-Bit AGP Bus

AGP Connector

Graphics

Cntlr. Card

PCI Connector 1

Audio

Subsystem

Pri.

IDE I/F

Sec.

IDE I/F

440LX

(North

Bridge)

PIIX4

(South

Bridge)

64-Bit Mem. Bus

PCI Connectors 2-4 [1

32-Bit PCI Bus 0

USB

I/F (2)

16-Bit ISA Bus

System Memory

Ultra SCSI

Controller

BIOS ROM

and Buffers

ISA Connectors (3

Ultra SCSI Hard Drive

PC 87307 I/O Controller

Keyboard/

Mouse I/F

[1] Only three PCI connectors on desktop.

Diskette

I/F

Serial

I/F

Parallel

I/F

Deskpro 6000 onlyDeskpro 4000 only

IrDA

I/F

Power

Supply

Figure 2–7. System Archit ectur e, Block di agram

Compaq Deskpro 4000 and 6000 Personal Computers

2-9

featuring the Pentium II Processor

Firs t Edition – October 1997

Chapter 2 System Overview

2.4.1 PENTIUM II PROCESSOR

The Pentium II processor consists of microprocessor and secondary cache components contained in a singl e edge connector (SEC) cartridge (Figur e 2-8).

Heat Sink

Microprocessor

Figure 2–8.

The microprocessor of the Pentium II is backward-compatible with software written for the Pentium MMX, Pentium Pro, Pentium , and x86 mi croprocessors. The Pent i um II microprocessor includes performance enhancements for multi-byte processing. The secondary cache, being in close proximity to the microprocessor, operates more efficiently than secondary caches located on the system board. A heat sink is attached to the Pentium II SEC cartridge. Passive cooling is used on most models. All minitower models utilize an auxiliary fan for processor cooling.

2.4.2 MEMORY

The system board provides three 168-pin DIMM sockets. Depending on model either 16 or 32 megabytes of SDRAM are installed. System memory can be expanded up to 384 megabytes using 8-, 16-, 32-, 64-, and 128-MB DIMMs. Parit y is not used although ECC (including ECC error logging and aler t ing) and EDO memory are supported.

The system ROM utilizes a flash ROM component that contains the BIOS and stores PCI, ESCD, and EV data. The BIOS is updateable by remote or local flashing of the ROM, which includes boot bloc k ROM support .

Single Edge Connector

Secondary Cache

Pentium II SEC Cartridge and Heat Sink

Thermal Plate

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2.4.3 SUPPORT CHIPSET

Table 2-2 lists the chipsets used on the system board and the functions provided by each.

Technical Reference Guide

Table 2–2.

Support Chipsets

Table 2-2.

Support Chipsets

Function Component Type Subfunctions

Host/PCI (North) Bridge 82440LX System Controller

PCI/ISA (South) Bridge 82371 EIDE Controller

I/O Controller 87307 Keyboard I/F

Audio Controller ES1869 ADC

SCSI Controller AIC-7860 SCSI Adapter Network I/F Controller TLAN 3.1 Ethernet I/F

Data Buffer

Host/AGP Bridge

DMA Controll er

Interrupt Controller

Timer/Counter NMI Registers

Reset Control Reg.

USB I/F

Diskette I/F

Serial I/F

IrDA I/F

Parallel I/F

RTC/CMOS Mem.

GPIO Ports

FM Synthesizer

DAC

2.4.4 NETWORK INTERFACE

This system includes a network interface controller (NIC) integrated on th e system board. The NIC is based on the Texas Instruments TLAN3.1 component and provides direct, auto-sensing support for 10BaseT and 100BaseTX LANs. Using an optional ada pt er , connection to a 10Base2 system is possible. Network status indicators are provided on the rear of the chassis.

The NIC supports the Magic Packet method of waking up the system from a powered-down state.

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Chapter 2 System Overview

2.4.5 GRAPHICS SUBSYS TEM

Two types of graphics controllers are used, depending on series. Table 2-3 outlines the key differences between the grap hics su bsystems.

Table 2–3.

Graphics Controller Matrox MGA 1064SG-

Graphics Memory Standard installed: Expandable to: Maximum Resolution w/ standard mem. w/ max. mem.

Graphics Subsystem Comparison

The Deskpro 4000 system features a PCI graphics card that is based on the Matrox MGA1064SG graphics accelerat or. The card includes two mega bytes of SGRAM a s stan dar d and can be expanded to four megabytes by adding a 2-MB SGRAM module.

The Deskpro 6000 system features an AGP graphi cs card tha t i s based on the Matrox MGA2164W graphics accelerat or. This card i nclu d es four megabytes of WRAM as sta ndard a nd can be expanded to 8 or 16 megabytes by adding a 4- or 12-MB WRAM module respectively. Other levels of WRAM expansion may be possible using Matrox WRAM expansion modules.

2.4.6 MASS STORAGE

Table 2-3.

Graphics Subsystem Comparison

Deskpro 4000 Deskpro 6000

based PCI Card

2 MB SGRAM 4 MB SGRAM

1280x1024 w/256 colors 1600x1200 w/256 colors

Matrox Millennium-II

AGP Card

4 MB WRAM

16 MB WRAM

1600x1200 w/65K colors

1600x1200 w/16M colors

All models include a 3.5 inch 1.44-MB diskette drive or an LS-120 drive installed. The Deskpro 4000 comes standard with a hard drive employing an IDE int er face th a t suppor t s UDMA mode 2 (33 MB/s). Master/slave drive selection is determined using the cable-select method, eliminating the need to move jumpers when re-configuring dr i ves. The Deskpro 6000 includes a har d drive using an Ultra SCSI interface. The mass storage drive bay mounting capacity is determined by the form factor (refer to Section 2.3, Mechanical Design).

2.4.7 SERIAL AND PARALLEL INTERFACES

All models include two serial ports (including one infrared (IrDa) port) and one parallel port available at the rear of the unit chassis. The serial and parallel interfaces are provided by the PC87307 I/O Controller component. Each serial port uses 16550/16450-compatible logic and is compliant with the RS-232-C standard at baud rates up to 115,200. The parallel interface is Enhanced Parallel Port (EPP1.9) and Enhanced Capability Port (ECP) compatible, and supports bi-directional data transfers.

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2.4.8 UNIVERSAL SERIAL BUS INTERFACE

Two Universal Serial Bus (USB) ports are included to provide a high speed interface for future systems and/or peripherals. Th e USB operates at 12 Mbps and provides hot plugging/ unplugging (Plug ’n Play) functionality.

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Chapter 2 System Overview

2.5 SPECIFICATIONS

This section includes the environmental, electrical, and physical specifications for the Compaq DESKPRO 4000/6000 Series Personal Comput er s.

Table 2–4.

Environmental Specifications

Table 2-4.

Environmental Specifications

Parameter Operating Nonoperating

Air Temperature 50 Shock 2.0 g for 11 ms half-sine pulse 30.0 g for 11 ms half-sine pulse Vibration 1 G for 5-200 Hz sinusoidal N/A Humidity 80% RH @ 36 Maximum Altitude 10,000 ft (3048 m) 50,000 ft (15,240 m)

Table 2–5.

Electrical Specifications

to 95o F (10o to 35o C) -40o to 140o F (-20o to 60o C)

C (no hard drive) 95% RH @ 36o C

Table 2-5.

Electrical Specifications

Parameter Domestic International

Input Line Voltage: Nominal: Maximum: Input Line Frequency Range: Nominal: Maximum: Power Supply: Maximum Continuous Power: Desktop: Minitower: Maximum Peak Power: Maximum Line Current Draw:

100 - 120 VAC

90 - 135 VAC

50 - 60 Hz 47 - 63 Hz

200 watts 280 watts ??? watts

5.0 A

200 - 240 VAC 180 - 265 VAC

50 - 60 Hz 47 - 63 Hz

200 watts 280 watts ??? watts

3.0 A

Table 2–6.

Physical Specifications

Physical Specific ations

Parameter Desktop Minitower

Height 5.0 in (12.7 cm) 16.69 in (42.39 cm) Width 17.69 in (44.93 cm) 7.3 in (18.54 cm) Depth 15.75 in (38.0 cm) 18.56 in (47.14 cm) Weight 17.2 lb (7.49 kg) 34.0 lb (15.40 kg)

NOTE:

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Table 2-6.

Table 2–7. Diskette Drive Specifications

Table 2-7.

Diskette Drive S pec ifications

Paramemter Measurement

Media Type 3.5 in 1.44 MB/720 KB diskette Height 1/3 Bytes per Sector 512 Secto rs per T rack: High Density Low Density Tracks p er Side: High Density Low Density Read/Write Heads 2 Average Access Time: Track-to-Track (high/low) Average (high/low) Settling Time Latency Average

80 80

3 ms/3 ms

94 ms/94ms

15 ms

100 ms

Technical Reference Guide

Table 2–8. 8x CD-ROM Drive Specifications

Table 2-8.

24x CD-ROM Drive Spec ifications

Paramemter Measurement

Media Type Mode 1,2, Mixed Mode, CD-DA,

Center Hole Diameter 15 mm Disc Diameter 8/12 cm Disc Thickness 1.2 mm Track Pitch 1.6 um Laser Beam Divergence Output Power Typr Wave Length Average Access Time: Random Full Stroke Audio Output Level 0.7 Vrms Cache Buffer 128 KB (min) Data Transfer Time Sustaiined Startup Time

Photo CD, Cdi , CD-XA

53.5 +/- 1.5

53.6 0.14 mW

790 +/- 25 nm

150 ms 350 ms

3600 KB/s

7 secs (nom)

GaAs

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Chapter 2 System Overview

Table 2–9. Standard Hard Drive Specifications

Parameter 2.1 GB 2.4 GB 3.2 GB 4.3 GB

Interface Type; SCSI EIDE EIDE SCSI Cache Buffer: 448K 128K 128K 512K Cable Select: Yes Yes N/A N/A Transfer Rate (max): 33 MB/s 33 MB/s 20 MB/s 20 MB/s Access Ti me Single Track: Average: Full Stroke: Disk RPM: 5400 5400 5400 7200 EDMA Mode Support (max): Mode 2 Mode 2 Mode 2 M ode 2 PIO Mode Support (max): Mode 4 Mode 4 Mode 4 Mode 4 Power Mode Commands: Yes Yes Yes Yes Drive Fault Prediction: SMART II SMART II SMART II SMART II

Table 2-9.

Standard Hard Drive Spec ifications

1.2 ms

8.5 ms

1.5 ms

2.5 ms

10.0 ms

20.0 ms

2.5 ms

10.0 ms

20.0 ms

1.0 ms

8.0 ms

18.0 ms

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Chapter 3 PROCESSOR/ MEMORY SUBSYSTEM

Technical Reference Guide

3.1

Chapter 3 PROCESSOR/MEMORY SUB S YSTEM

INTRODUCTION

This chapter describes the processor/cache memory subsystem of the Compaq Deskpro 4000 and 6000 Series of Personal Computers featuring the Pentium II microprocessor.

This chapter includes the following topics: ♦ Pentium II-based processor/memory subsystem [3.2] page 3-2

Table 3-1 lists the highl i ghts of the processor/memory architecture.

Table 3–1.

Processor Pentium II 233, 266, or 300 MHz Host Bus Speed 66 MHz Support Chipset 82440LX System Memory Type: Speed: Standard amount installed: Expandable to:

Processor/Memory Architectural Highlights

Table 3-1.

Processor/Memory

Architectur al Highlights

Unbuffered SDRAM

66 MHz

32 or 64 MB SDRAM

384 MB

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Chapter 3 Processor/Memory Subsystem

3.2 PENTIUM II-BASED PROCESSOR/MEMORY SUBSYSTEM

The processor/memory subsystem in Pentium II-based systems features an Intel Penti um II processor, an 82440LX system controller, and either 32 or 64 m egabytes of system memory (Figure 3-1).

Pentium II Processor

System Memory

PCI

Cntl

64-Bit Mem. Data Bus

Mem. Addr.

J12

32-MB

DIMM

J11

DIMM

64-Bit Host Bus

Controller

(440LX)

J10

DIMM

32-Bit PCI Bus

Optional module

Figure 3–1.

Pentium II-Based Processor/Memory Subsystem Architecture

The Pentium II SEC cartridge is mounted in a special processor slot that facilitates easy changin g/ upgrading. T he 440LX controller provides the Host/PCI bridge functions and controls data transfers with system memory over the 64-bit memory data bus. The system memory comes with 32 or 64 megabytes of SDRAM expandable to 384 megabytes.

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3.2.1 PENTIUM II PROCESSOR

The Pentium II processor is packaged in a Single Edge Connector (SEC) cartridge that contains the microprocessor and secondary (L2) cache (Figure 3-2). The cartridge installs into a specific processor slot on the system board, allowing easy replacing/upgrading of the processor/cache memory complex.

Pentium II SEC Cartrid ge

Microprocessor

Technical Reference Guide

Figure 3–2.

Dual-ALU

CPU w/MMX

Branch

Prediction

(Mounted in Edge Connector)

Pentium II Processor Internal Architecture

32-KB

L1 Cache

Dual Pipeline Math Coproc.

512-KB

L2 Cache

The microprocessor of the Pentium II is backward compatible with software written for the Pentium Pro, Pen t i u m MMX, Penti u m , and ea rlier g eneration x86 microprocessors. The microprocessor includes a dual-ALU CPU, branch prediction logic, dual-pipeline math coprocessor, and a 32-KB primary (L1) cache that is split into two 16-KB 4-way, set-associative caches for handling code and data separately. Out-of-order instruction processing first supported by the Pentium Pro is retained and multi-byte processing enhancements have been added.

The Pentium II SEC cart ridge includes 512 kilobytes of SRAM for the secondary (L2) cache. Accesses with the L2 cache occur at Host bus speed, although the close proximity of the cache provid es higher efficiency than caches located on the system board.

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Chapter 3 Processor/Memory Subsystem

3.2.1.1 MMX Technology

The CPU of the Pentium II supports 57 additional instructions for acceleratin g multimedia and communications applications. Such applications often involve compute-intensive loops that, while taking up only a small percent of the application code, can take up as much as 90 percent of CPU execution time. The MMX logic, using a p a rallel processing technique called Single Instruction-Multiple Data (SIMD), processes 64 bits of data at a time.

The MMX instru ct i on s are designed to take a dvantage of th e du a l-pipeli ne CPU as well as hel p the programmer in avoiding branches in code. Types of operations where performance is enhanced include video playback, 3D imaging, and file printing. Specific applications that benefit fr om MMX t echnol ogy include 2D/3D gr aphi cs, audio, speech recognition, video codecs, and data compression .

The MMX tech nology is compatible with current operating systems, although future operating systems, like the application software, may become customized to take advantage of MMX benefits.

NOTE:

integrated math coprocessor. Programmers should avoid the mixing of MMX and floating point code, which would reduce performance.

MMX operations utilize a portion of the floating point registers of the

3.2.1.2 PROCESSOR CHANGING/UPGRADING

The Pentium II SEC cartridge design allows for easy changing and/or upgrading of the microprocessor/ca che compl ex . In changing the SEC cart rid g e, two key area s s hould be considered: thermal characteristics and operating speed.

Thermal Considerations

The factory-installed SEC cartridge includes a passive heat sink attached with clips. Forced cooling of the processor by a secondary fan (located in the front of the unit and connected to header E100) is used only in minitower models. A thermister, l ocated on the heat sink and conn ected to system boa rd h eader P15 detects when th e p rocessor has reached the caution temperature level. The processor also has an internal sensor that will shut down the microprocessor if the temperature reaches 135°C.

The system board includes a header (E101) that allows the connection of a cooling fan that may be integrated onto some upgrade SEC cartridges, depending on source.

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Processor Speed Selection

The Pentium II-based system board includes a six-position DIP switch (SW1), of which four positions are used to select the bus-to-core frequency of the Pentium II. Table 3-2 shows the possible switch configurations for this system and the resultant core (or processing) frequency.

Table 3–2.

Pentium II Microprocessor Bus/Core Speed Switch Settings

Table 3-2.

Pentium II M ic r opr oc es s or

Bus/Core Speed Swit c h S ettings

DIP SW1 Settings 2 3 4 5 [1]

0 1 0 0 66 166 1 0 0 1 60 180 1 0 0 0 66 200 1 1 0 1 60 210 1 1 0 0 66 233 0 0 1 1 60 240 0 0 1 0 66 266 0 1 1 1 60 270 0 1 1 0 66 300 1 0 1 1 60 300 1 0 1 0 66 333 1 1 1 1 60 330 1 1 1 0 66 366

NOTES:

Shipping configurations are unshaded. [1] 0 = Switch Closed (On), 1 = Switch Open (Off)

Host Bus

Speed (MHz) Core Speed (MHz)

The status of SW1(2-4, 5) is readable through general-pur pose I/O (GPIO) port 78h bits <3..0>, allowing BIOS and/or diagnostic software to check an installed microprocessor with the switch configuration. Table 3-3 shows the switch position-to-GPIO-to-I/O port 78h input wiring.

Table 3–3

. SW2 Bus/Core Speed Positions to GPIO Assignments

Table 3-3.

SW1 Bus/Core S peed P os itions

to GPIO A s s ignm ents

Switch Position Signal Name GPIO Number I/O Port 78h

SW1-2 CFG_IGNNE 11 bit <1> SW1-3 CFG_INTR 10 bit <0> SW1-4 CFG_A20M 13 bit <3> SW1-5 CFG_SPD60 12 bit <2>

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Chapter 3 Processor/Memory Subsystem

3.2.2 SYSTEM MEMORY

The system board contains three 168-pin DIMM sockets for system memory. This system is designed for u si ng SDRAM DIMMs. As sh i p p ed fr om t he factory the sta ndard configur ation may be 32 or 64 megabytes installed. The addition of 8-, 16-, or 32-, 64-, or 128-MB DIMMs allows the expansion of system memory up to a maximum of 384 megabytes. Single or double-sided DIMMs may be used. Pari t y is n ot i m p l em ented in thi s system.

The system memory uses the following RAS line assignments:

RAS#0 DIMM 1, Bank A RAS#1 DIMM 1, Bank B RAS#2 DIMM 2, Bank A RAS#3 DIMM 2, Bank B RAS#4 DIMM 3, Bank A RAS#5 DIMM 3, Bank B

The performance times of the SDRAM is listed as follows:

Table 3–4.

SDRAM Performance Times

Table 3-4.

SDRAM Performance Times

Parameter CAS Latency = 3 CLKs CAS Latency = 2 CLKs

Burst Read Page Hit: 9-1-1-1

Read Row Miss 10-1-1-1 10-1-1-1 Read Page Miss 13-1-1-1 10-1-1-1 Bk-to-Bk Burst Reads (Pg Hit ) Write Page Hit 3 3 Write Row Miss 6 6 Write Page Miss 9 9 Posted Write 3-1-1-1 3-1-1-1 Write Retire Rate from Posted Write Buffer

SLD = Speculative Lead Disable SSRE = SDRAM Speculative Read Enable

9-1-1-1, 1-1-1-1 (SLD=0, SSRE = 1)

10-1-1-1, 1-1-1-1 (SLD=0, SSRE = 1)

10-1-1-1

8-1-1-1, 2-1-1-1 (SLD=0, SSRE=1) 9-1-1-1, 2-1-1-1 (SLD=0, SSRE=1)

-1-1-1 -1-1-1

8-1-1-1 9-1-1-1

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3.2.2.1 Memory Changing/Expansion

The system memory can be changed and/or expanded by installing appropriate 168-pin DIMM types. In expanding the standard memory using modules from third party suppliers the following DIMM type is recommended:

latency (CL) 2 or 3 with a data access time (clock-to-data out) of 9.0 ns or less @ CL=2 and CL=3

. The memory may also be expanded using EDO memory, although slightly lower

performance may be experienced. T he EDO DIMMs must be of the following type:

unbuffered EDO RAM

The 440LX features programmable drive strength of the memory bus signals to compensate for differences in DIMM module loading. The 440LX does, however, exhibit limitations on DIMM slot configurations, depending on the installed DIMM’s complement of SDRAM chips.

using SDRAM chips wit h a bandwidth of x4 (four bits) are not supported. Some combinations of DIMMs using x8 and x32 SDRAM c hi ps a r e also not supported.

unsupported configuration will cause the BIOS to generate an error message (#213), correctable by moving the DIMMs to one of the supported configurations listed in the table below.

Configuration # DIMM Slot J10 [1] DIMM Slot J11 DIMM Slot J12 [2]

1x8x8x8 2x8x32x8 3 x32 x8 x8 4x32x32x8 5 x32 x32 x32 6 None x32 X8 7 x32 None X8

NOTES:

To determine SDRAM chip bandwidth, divide 64 by the number of RAM chips on one side of the DIMM (valid divisor will be 2 or multiples of 4; round down for ECC DIMMs).

66-MHz (or faster) unbuffered SDRAM supporting CAS

Technical Reference Guide

50/60 ns

DIMMs

[1] Slot closest to edge of board. [2] Slot closest to 440LX (located under SEC cartridge).

The BIOS supports the use of ECC memory, complete with error logging and alerting. To obtain the full ben efit of ECC m em ory the system must be loaded exclusi vely with EC C DIMMs ( not mixed) since the 440LX cannot enable ECC DIMMs indi vidual y.

Access to the DIMM’s EE PROM is t hrough an I

C-type bus interface using BIOS call INT 15, AX-E827h (discussed in Chapter 8, “BIOS ROM”). The system can be configured using a mixture of SDRAM, EDO RAM, and ECC RAM of different speeds, although doing so will cause the BIOS to configure the system to the weakest (slowest) DIMM type installed. . If the BIOS finds an installed module that is not supported then the memory controller is programmed to indicate empty rows as appropriate.

All DIMMs, regar dless of RAM type, must compl y with JEDEC serial presence detect (SPD) specification revision 1.0 or later. The RAM type (as well as other information) is detected durin g power-up by the system BIOS using the SPD method, which reads the EEPROM on each DIMM to obtain identification data such as the type and operating parameters. This system also provides support for 256-byte EEPROMs to include additional Compaq-added features such as the part number, serial number, and error logging. The SPD format as supported in this system is shown in Table 3-5.

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Chapter 3 Processor/Memory Subsystem

Table 3–5. SPD Addr ess Map ( SDRAM DIMM)

SPD Address Map (SDRAM DIMM)

Byte Description Notes Byte Description Notes

0 No. of Bytes Written Into EEPROM [1] 62 SPD Revision [7] 1 Total Bytes (#) In EEPROM [2] 63 Checksum Bytes 0-62 2 Memory Type 64-71 JEP-106E ID Code [8] 3 No. of Row Addresses On DIMM [3] 72 DIMM OEM Location [8] 4 No. of Column Addresses On DIMM 73-90 OEM’s Part Number [8] 5 No. of Module Banks On DIMM 91, 92 OEM’s Rev. Code [8] 6, 7 Data Width of Module 93, 94 Manufacture Date [8] 8 Voltage Interface Standard of DIMM 95-98 OEM’s Assembly S/N [8] 9 Cycletime @ Max CAS Latency (CL) [4] 99-125 OEM Specific Data [8] 10 Access From Clock [4] 126, 127 Reserved 11 Config. Type (Parity, Nonparity, etc.) 128-135 Sys. Integrator’s ID [9] 12 Refresh Rate/Type [4] [5] 136-150 Sys. Integrator’s P/N [9] 13 Width, Primary DRAM 151-152 Sys. Integrator’s D/C [9] 14 Error Checking Data Width 153-165 Sys. Integrator’s S/N [9] 15 Min. Clock Delay [6] 166 Chksm Bytes 128-165 [9] 16 Burst Lengths Supported 167-189 Top Level Sys. S/N [9] 17 No. of Banks For Each Mem. Device [4] 190-221 Avaiable for use [9] 18 CAS Latencies Supported [4] 222 Chksm Bytes 167-221 [9] 19 CS# Latency [4] 223-253 Available for use [9] 20 Write Latency [4] 254 Chksm Bytes 223-253 [9] 21 DIMM Attributes 255 Chksm Byes 0-128 [9] 22 Memory Device Attributes 23 Min. Clock Cycle Time at CL X-1 [7] 24 Max. Acc. Time From CLK at CL X-1 [7] 25 Min. Clock Cycle Time at CL X-2 [7] 26 Max. Acc. Time From CLK at CL X-2 [7] 27 Min. Row Precharge Time [7] 28 Min. Row Active To Row Active Delay [7] 29 Min. RAS to CAS Delay [7] 30, 31 Reserved

32..61 Superset Data For Future Use

NOTES:

[1] Programmed as 128 bytes by the DIMM’s OEM [2] Must be programmed to 256 bytes. [3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be re-sent as highest order CAS# address. [4] Refer to memory manufacturer’s datasheet [5] MSb is Self Refresh flag. If set (1), assembly supports self refresh. [6] Back-to-back random column addresses. [7] Field format proposed to JEDEC but not defined as standard at publication time. [8] Field specified as optional by JEDEC but required by this system. [9] Field format proposed to JEDEC. This system requires that the DIMM’s EEPROM have this space available for reads/writes.

Table 3-5.

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3.2.2.2 System Memory Map

(

)

(

)

Figure 3-3 shows the system memory map.

Technical Reference Guide

Host,

PCI Area

Host, PCI,

ISA Area

DOS Compatibility

Area

FFFF FFFFh FFFC 0000h

FFFB FFFFh

8100 0000h

80FF FFFFh

8000 0000h

7FFF FFFFh

1000 0000h

FFDF FFFFh

1000 0000h

0FFF FFFFh

0400 0000h

03FF FFFFh

0100 0000h

00FF FFFFh

0010 0000h

000F FFFFh

000F 0000h

000E FFFFh

000E 0000h

000D FFFFh

000C 8000h

000C 6800h

000C 6000h

000C 5FFFh

000C 0000h

000B FFFFh

000A 0000h

0009 FFFFh

High BIOS Area

256 KB

PCI Memory

(2130 MB)

ISA Memory-Mapped

Device s (16 MB)

PCI Memory

(1792 MB)

Cacheable in L1

(192 MB)

Extended Memory

(48 MB)

Extended Memory

15 MB

Upper BIOS Area

(64 KB)

Lower BIOS Area

(64 KB)

Unused 96 KB

Graphics ROM

(6 KB)

Unused 2 KB

Graphics ROM

(24 KB)

Graphics/SMM Area

(128 KB)

4 GB

64 MB

16 MB

1 MB

960 KB

896 KB

800 KB

792 KB

768 KB

640 KB

Base Memory

(640 KB)

0000 0000h

NOTE: All locations in the 384 megabytes of system memory are cacheable in the L2 cache.

Figure 3–3.

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System Memory Map

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Chapter 3 Processor/Memory Subsystem

3.2.3 SUB S YSTEM CONFIGURATION

The 440LX component provides the configuration function for the processor/memory subsystem. Table 3-9 lists the configuration registers used for setting and checking such parameters as memory control and PCI bus operation. These registers reside in the PCI Configuration Space and accessed using the methods described in Chapter 4, section 4.2.

Table 3–6.

Host/PCI Bridge Configuration Registers (440LX, Device 0)

Table 3-9.

Host/PCI B r idge Configuration Registers ( 82440LX , Device 0)

PCI Config. Addr. Register

00, 01h Vender ID 8086h 6A, 6Bh DRAM Control Reg. 00h 02, 03h Device ID 7180h 6C..6Fh Memory Buffer Strength 55h 04, 05h Command 0006h 70h Multi-Transaction Timer 00h 06, 07h Status 0290h 71h CPU Latency Timer 10h 08h Revision ID -- 72h SMRAM Control 02h

09..0Bh Class Code -- 90h Error Command 00h 0Dh L atency Timer 00 h 91h Error Status Register 0 00h 0Eh Header Type 00h 92h Error Status Register 1 00h

10..13h Aperture Base Config. 08h 93h Reset Control 00h 50, 51h PAC Config. Reg. 00h A0..A3h AGP Capability Identifier N/A 53h Data Buffer Control 83h A4..A7h AGP Status N/A

55..56h DRAM Row Type 00h A8..ABh AGP Command 00h 57h DRAM Control 01h B0..B3h AGP Control 00h 58h DRAM Timing 00h B4h Aperture Size 0000h

59..5Fh PAM 0..6 Registers 00h B8..BBh Aperture Translation Table 0000h

60..67h DRAM Row Boundary 01h BCh Aperture I/F Timer 00h 68h Fixed DRAM Hole 00h BDh Low Priority Timer 00h

NOTES:

Refer to Intel Inc. documentation for detailed description of registers. Assume unmarked locations/gaps as reserved.

Device 1 (virtual PCI/PCI bridge for AGP) of the 440LX is not used in the Deskpro 4000 system but is accessed during POST to configure the DOS compatibility area for usage by the graphics controller.

Reset Value

PCI Config. Addr. Register

Reset Value

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Chapter 4 SYSTEM SUPPORT

4. Chapter 4 SYSTEM SUPPORT

Technical Reference Guide

4.1

INTRODUCTION

This chapter covers subjects dealing with basic system architecture and covers the following topics:

♦ PCI bus overview (4.2) page 4-2 ♦ AGP bus overview (4.3) page 4-11 ♦ ISA bus overview (4.4) page 4-13 ♦ System clock distribution (4.5) page 4-25 ♦ Real-time clock and configuration memory (4.6)page 4-26 ♦ I/O map an d register accessing (4. 7) page 4-43 ♦ System management (4.8) pa ge 4-46

This chapter covers functions provided by off-the-shelf chipsets and therefore describes only basic aspects of these functions as well as information unique to the Compaq Deskpro 4000/6000 Personal Computers. For detailed information on specific components, refer to the applicable manufacturer’s documentation.

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Chapter 4 System Support

4.2 PCI BUS OVERVIEW

NOTE:

This section describes the PCI bus in general and highlights bus implementation in this particular system. For detailed information regarding PCI bus operation, refer to the PCI Local Bus Specification Revision 2.1.

This system implements a 32-bit Peripheral Component In t er conn ect (PCI) bus. The PCI bus uses a shared address/data bus design. On the first clock cycle of a PCI bus transaction the bus carries address information. On subsequent cycles, the bus carries data. PCI transactions occur synchronously with the Host bus at a rate of up to 33 MHz, depending on the speed of the microprocessor used. All I/O transactions involve the PCI bus. All ISA transactions involving the microprocessor, cache, and memory also involve the PCI bus. Memory cycles will involve the PCI if the access is initiated by a device or subsystem other than the microprocessor.

The PCI bus handles address/data transfers through the identification of devices and functions on the bus (Figure 4-1). A device is defined as a component or slot that resides on the PCI bus. A function is defined as the end source or target of the bus transaction. A device (component or slot) may contain one or more functions (i.e., in this system the PCI/ISA Bridge function, EIDE controller function, USB function, and ACPI function are contained within the South Bridge component).

Host Bus

PCI Connector Slot 4

PCI Connector Slot 3

Host/PCI

Bridge Function

PCI/ISA Bridge

Function

Minitower only

Figure 4–1.

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PCI Bus Devices and Functions

PCI/AGP

Bridge Function

EIDE Cntlr.

Function

ISA Bus

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32-Bit PCI Bus

USB

Function

PCI Connector Slot 2

PCI Connector Slot 1

ACPI Cntlr.

Function

NIC

Function

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4.2.1 PCI CONNECTOR

Technical Reference Guide

B94

A94

Figure 4–2.

Table 4–1.

A62

PCI Bus Connector (32-Bit Type)

PCI Bus Connector Pinout

B1B62

Table 4-1.

PCI Bus Connector P inout

Pin B Signal A Signal Pin B Signal A Signal Pin B Signal A Signal

01 -12 VDC TRST- 32 AD17 AD16 63 Reserved GND 02 TCK +12 VDC 33 C/BE2- +3.3 VDC 64 GND C/BE7- 03 GND TMS 34 GND FRAME- 65 C/BE6- C/BE5- 04 TDO TDI 35 IRDY- GND 66 C/BE4- +5 VDC 05 +5 VDC +5 VDC 36 +3.3 VDC TRDY- 67 GND PAR64 06 +5 VDC INTA- 37 DEVSEL- GND 68 AD63 AD62 07 INTB- INTC- 38 GND STOP- 69 AD61 GND 08 INTD- +5 VDC 39 LOCK- +3.3 VDC 70 +5 VDC AD60 09 PRSNT1- Reserved 40 PERR- SDONE 71 AD59 AD58 10 RSVD +5 VDC 41 +3.3 VDC SBO- 72 AD57 GND 11 PRSNT2- Reserved 42 SERR- GND 73 GND AD56 12 GND GND 43 +3.3 VDC PAR 74 AD55 AD54 13 GND GND 44 C/BE1- AD15 75 AD53 +5 VDC 14 RSVD Reserved 45 AD14 +3.3 VDC 76 GND AD52 15 GND RST- 46 GND AD13 77 AD51 AD50 16 CLK +5 VDC 47 AD12 AD11 78 AD49 GND 17 GND GNT- 48 AD10 GND 79 +5 VDC AD48 18 REQ- GND 49 GND AD09 80 AD47 AD46 19 +5 VDC Reserved 50 Key Key 81 AD45 GND 20 AD31 AD30 51 Key Key 82 GND AD44 21 AD29 +3.3 VDC 52 AD08 C/BE0- 83 AD43 AD42 22 GND AD28 53 AD07 +3.3 VDC 84 AD41 +5 VDC 23 AD27 AD26 54 +3.3 VDC AD06 85 GND AD40 24 AD25 GND 55 AD05 AD04 86 AD39 AD38 25 +3.3 VDC AD24 56 AD03 GND 87 AD37 GND 26 C/BE3- IDSEL 57 GND AD02 88 +5 VDC AD36 27 AD23 +3.3 VDC 58 AD01 AD00 89 AD35 AD34 28 GND AD22 59 +5 VDC +5 VDC 90 AD33 GND 29 AD21 AD20 60 ACK64- REQ64- 91 GND AD32 30 AD19 GND 61 +5 VDC +5 VDC 92 Reserved Reserved 31 +3.3 VDC AD18 62 +5 VDC +5 VDC 93 Reserved GND

-- -- -- -- -- -- 94 GND Reserved

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Chapter 4 System Support

4.2.2 PCI BUS MASTER ARBITRATION

The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has been granted control of the bus for the purpose of initiating a transaction. A target is a device that is the recipient of a transaction. Request (REQ), Grant (GNT), and FRAME signals are used by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI bus (and does not already own it), the PCI device asserts it’s REQn signal to the PCI bus arbiter (a function of the system controller component). If the bus is available, the arbiter asserts the GNTn signal to the requesting device, which then asserts FRAME and conducts the address phase of the transaction with a target. If the PCI device already owns the bus, a request is not needed and the device can simply assert FRAME and conduct the tra nsaction. Table 4-1 shows the grant and request signals assignments for the devices on the PCI bus.

Table 4–2.

PCI Bus Mastering Devices

Table 4-2.

PCI Bus Mast er ing Dev ic es

REQ/GNT Line Device

REQ0/GNT0 PCI Connector Slot 1 and Slot3 [1] REQ1/GNT1 PCI Connector Slot 2 REQ2/GNT2 SCSI Controller REQ3/GNT3 Network I/F Controller REQ4/GNT4 PCI Connector Slot 4

NOTES: [1] These devices share the REQ/GNT signals through additional logic.

PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm specified by the PCI specification. The bus parking policy allows for the current PCI bus owner (excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted by another agent . Note th a t most CPU-to-DRAM a nd AGP-to-DRAM a ccesses ca n occur concurrently with PCI traffic, therefore reducing the need for the Host/PCI bridge to compete for PCI bus ownership.

The PCI bus arbiter of the 440LX includes a Multi-Transaction Timer (MTT) that provides additional control for bus agents that perform fragmented accesses or have real-time access requirements. The MTT allows the use of lower-cost peripherals (by the reduction of data buffering) for multimedia applications such as video capture, serial bus, and RAID SCSI controllers.

The 440LX and the 82371 support the passive release mechanism, which reduces PCI bus latency caused by an ISA initiator owning the bus for long periods of time.

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4.2.3 PCI BUS TRANSACTIONS

The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling both address and data transfers. A bus transaction consists of an address cycle and one or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is realized during burst modes in which a transaction with contiguous memory locations requires that only one address cycle be conducted and subsequent data cycles are completed using autoincremented addr es s i ng. F our types of address cycles can t ake place on the PCI bus ; I/O, memory, configuration, and special. Address decoding is distributed (left up to each device on the PCI bus).

4.2.3.1 I/O and Memory Cycles

For I/O and memory cycles, a standard 32-bit addr ess decode (AD31..0) for byte-level addressing is handled by the appropriate PCI device. For memory addressing, PCI devices decode the AD31. .2 li nes for d wor d -level a d d ressi ng and check the AD1, 0 lin es for burst (li nearincrementing) mode. In burst mode, subsequent data phases are conducted a dword at a time with addressing assumed to increment accordingly (four bytes at a time).

Technical Reference Guide

4.2.3.2 Configuration Cycles

Devices on the PCI bus must comply with PCI protocol that allows configuration of that device by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus specification Rev. 2.1) is employed. This method uses two 32-bit registers for initiating a configuration cycle for accessing the configuration space of a PCI device. The configuration address register ( C ONFIG_ ADDRESS) a t 0 C F8h holds a value th a t specifies the PCI bus, PCI device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at 0CFCh contains the configuration data.

PCI Configuration Address Register I/O Port 0CF8h, R/W, (32-bit access only)

Bit Function Bit Function

31 Configuration Enable

0 = Disabled 1 = Enable

30..24 Reserved - read/write 0s

23..16 Bus Number. Selects PCI bus

15..11 PC I Device Number. Se lects PCI device for access

10..8 Function Number. Selects function of selected PCI device.

7..2 Register Index. Specifies config. reg. 1,0 Configuration Cycle Type ID.

00 = Type 0 01 = Type 1

PCI Configuration Data Register I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)

31..0 Configuration Data.

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Figure 4-3 shows how the loading of 0CF8h results in a Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11> determines which one of the AD31..11 lines is to be asserted high for the IDSEL signal, which acts as a “chip select” function for the PCI device to be configured.

Resul ts in:

AD31..0

w/Type 0

Config. Cycle

3130 24 23

Reserved

IDSEL (only one signal line asserted)

16 15 11 10 8 721 0

Bus

Number

Device

Number

Function

Number

11 10 8

Function

Number

Index

721 0

Index

0 0

Figure 4–3. Type 0 Configuration Cycle

Type 0 configuration cycles are used for configuring devices on PCI bus # 0. Type 1 configuration cycles (reg. 0CF8h bits <1,0> = 01b) are passed on to PCI bus # 1 (if present). Table 4-3 shows the standard configuration of device numbers and IDSEL connections for components a nd slots r esi d i ng on a PC I bus.

Table 4–3. PCI Device Configuration Access

Table 4-3.

PCI Component Configuration Access

PCI Component

440LX (North Bridge) 0 AD11 PCI Connector (slot 1) 12 AD23 PCI Connector (slot 2) 13 AD24 PCI Connector (slot 3) 14 AD25 PCI Connector (slot 4) [2] 18 AD29 SCSI Controller 15 AD26 Network Interface Controller 16 AD27 82371 (South Bridge) 20 AD31

NOTES

[1] CF8h bits <15..11> [2] Minitower only

Device No. [1]

IDSEL

Wired to:

The function number (CF8h, bits <10..8>) is used to select a particular function within a multifunction device as shown in Table 4-4.

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Technical Reference Guide

Table 4–4. PCI Function Configuration Acces

Table 4-4.

PCI Function Configurat ion Access

PCI Function Device No. Function No.

Host/PCI Bridge (440LX) 0 0 PCI/AGP Bridge (440LX) 0 1 PCI/ISA Bridge (82371) 20 0 IDE Interface (82371) 20 1 USB Interface (82371) 20 2 ACPI Cntlr. (82371) 20 3

The register index (CF8h, bits <7..2>)identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (see Figure 4-4), of which the first 64 bytes comprise the configuration space header.

24 23 16 15 8 7 0

Index

FCh

Device-Specific Area

40h 3Ch

0Ch 08h 04h

00h

Configuration

Space

Header

Data required by PCI protocol

Base Address Registers and Exp. ROM Address

BIST

Header Type

Status

Device ID

Latency Timer

Not required

Interrupt LineInterrupt PinMin_GNTMin_Lat

Cache Line Size

Revisi on IDClass Code

Command

Vender ID

Figure 4–4. PCI Configuration Space Map

Each PCI device is identified with a vender ID (assigned to the vender by the PCI Special Interest Group) and a device ID (assigned by the vender). The device and vender IDs for the devices used in these systems are listed in Table 4-5.

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Table 4–5. PCI Device Identification

PCI Device Vender ID Device ID

North Bridge (Intel 440LX PAC) Host/PCI Bridge (Function 0): PCI/AGP Bridge (Function 1): South Bridge (Intel 82371 PIIX4) PCI/ISA Bridge (Function 0): EIDE Controller (Function 1): USB I/F (Function 2): ACPI Cntlr (Function 3): Network Interface Controller 0E11h B011h SCSI Controller 9004h 6078h

4.2.3.3 Special Cycles

There are two types of special cycles that may occur on the PCI bus. The first type is initiated by the host and is used to perform the following functions: Shutdown, Flush, Halt, Write Back, Flush Acknowledge, Branch Trace Message, and Stop/Grant. These cycles start like all other PCI cycles and terminate with a master abort.

Table 4-5.

PCI Device Ident ification

8086h 8086h

8086h 8086h 8086h 8086h

7180h 7181h

7110h 7111h 7112h 7113h

The second type of special cycle is initiated by writing to 0CF8h, Bus # = all 0s, Device = all 1s, Function # all 1s, and Register = all 0s) and 0CFCh to generate a Type 0 configuration cycle. This type 0 cycle, however, does not assert any of the IDSEL lines and therefore results in a master a bort with FFFFh returned t o the microprocessor.

4.2.4 OPTION ROM MAPPING

During POST, t he PCI bus is scanned for devices that contain th eir own specific firmware in ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility area (refer to the system memory map shown in chapter 3).

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4.2.5 PCI INTERRUPT MAPPING

The PCI bus provides for four interrupt sign a l s; INTA-, INTB-, INTC-, a nd INTD-. These signals may be generated by on-board PCI devices or by devices installed in the PCI slots. In order to minimize latency, INTA-..INTD- signal routing from the slots to the system board is distributed evenly by the riser card (backplane) as shown below:

System Board PCI Slot 1 PCI Slot 2 PCI Slot 3 PCI Slot 4 [1]

INTA- INTD- INTB- INTC- INTA- [2] INTB- INTA- [3] INTC- INTD- INTBINTC- INTB- INTD- INTA- INTCINTD- INTC- INTA- [4] INTB- INTD-

Technical Reference Guide

NOTES:

[1] Minitower only [2] Shared with network interface controller [3] Shared with SCSI controller [4] Shared with USB controller

Interrupt s gener a ted by PCI devices can be configured to share the standard AT (IRQn) int er rupt lines. Two devices that share a single PCI interrupt must also share the corresponding AT interrupt. Example: If a PCI card is installed in slot 5 and wants to use INTA- then it must share INTA- as well as the corresponding AT interrupt with the on-board network interface controller.

Three PCI configuration registers are used to route the INTA-..INTD- signals to the IRQn signal lines (refer to section 4.3.4.1 for information on IRQn routing). The power up (default) configuration has PCI interrupt redirection disabled.

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4.2.6 PCI CONFIGURATION

PCI bus operations, especially those that involve ISA bus interaction, require the configuration of certain parameters such as PCI IRQ routing, top of memory accessable by ISA, SMI generation, and clock throttling characteristics. These parameters are handled by the PCI/ISA bridge function (PCI function #0) of the South Bridge component and configured th rough the PCI configuration space registers listed in Table 4-6. Configuration is provided by BIOS at power-up but re-configurable by software.

Table 4–6.

PCI/ISA Bridge Configuration Registers (82371, Function 0)

Table 4-6.

PCI/ISA B r idge Configuration Registers

(82371, Function 0)

PCI Config. Addr. Register

00, 01h Vender ID 8086h 63h PCI Interrupt Routing 80h 02, 03h Device ID 7111h 64h Serial Interrupt Control 04, 05h Command 69h Memory Map Control 02h 06, 07h Status 6A, 6Bh SERR-/PCI Cycle Retry 00h 08h Revision ID 76, 77h DMA Enable/Ch. Routing 09-0Bh Class Code 80h A12 Mask/X-Y Base Addr. 00h 0Eh Header Type 82h USB Passive Rel. Enable 00h 4Ch DMA Aliasing Control 00h 90, 91h DMA Channel Select 00h 4E-4Fh APIC/BIOS Control 0003h 92, 93h DMA 0-3 Base PTR 00h 60h PCI Interrupt Routing 80h 94, 95h DMA 4-7 Base PTR 00h 61h PCI Interrupt Routing 80h B0-B3h GPIO/Misc. Funct. Select 00h 62h PCI Interrupt Routing 80h CBh RTC/RAM Control 21h

NOTE: Assume unmarked locations/gaps as reserved.

Reset Value

PCI Config. Addr. Register

Reset Value

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4.3 AGP BUS OVERVIEW

The Accel erated Graphics Port ( AGP) bus i s specifically designed as a high-performance, economical interface for graph i cs a d a p t ers. The AGP bus is very similar to the PCI bus in operation but operates at Host/memory bus speed (i.e., in systems employing the Pentium II 233, 266, or 300 MHz processor the AGP bus operates at 66 MHz). Graphics adapters usi ng the AGP bus have dedicat ed pipelin ed a ccess to system memor y. The AGP bus is par t icular l y suited for 3D graphics adapters by providing a low-latency interface with system memory for storage of texture data, z-buffering, and alpha blending. The AGP graph ics adapt er utilizes its local frame buffer for display image refreshing.

Technical Reference Guide

B94

A94

Figure 4–5.

Table 4–7.

A21 A26

B21 B26

AGP Bus Connector

AGP Bus Connector Pinout

A66

Table 4-7.

AGP Bus Connect or P inout

Pin A Signal B Signal Pin A Signal B Signal Pin A Signal B Signal

01 +12 VDC OVRCNT- 23 (Key) (Key) 45 VDD3 VDD3 02 RSVD VDD 24 (Key) (Key) 46 TRDY- DEVSEL03 GND VDD 25 (Key) (Key) 47 STOP- NC 04 USBN USBF 26 PAD30 PAD31 48 PME- PERR05 GND GND 27 PAD28 PAD29 49 GND GND 06 INTA- INTB- 28 VDD3 VDD3 50 PAR SERR07 RESET CLK 29 PAD26 PAD27 51 PAD15 CBE108 GNT- REQ- 30 PAD24 PAD25 52 NC NC 09 VDD3 VDD3 31 GND GND 53 PAD13 PAD14 10 ST1 ST0 32 RSVD AD_STB1 54 PAD11 PAD12 11 RSVD ST2 33 CBE3- PAD23 55 GND GND 12 PIPE- RBF- 34 NC NC 56 PAD09 PAD10 13 GND GND 35 PAD22 PAD21 57 CBE0- PAD08 14 RSVD RSVD 36 PAD20 PAD19 58 NC NC 15 SBA1 SBA0 37 GND GND 59 RSVD AD_STB0 16 VDD3 VDD3 38 PAD18 PAD17 60 PAD06 PAD07 17 SBA3 SBA2 39 PAD16 CBE2- 61 GND GND 18 RSVD SB_STB 40 NC NC 62 PAD04 PAD05 19 GND GND 41 FRAME- IRDY- 63 PAD02 PAD03 20 SBA5 SBA4 42 RSVD RSVD 64 NC NC 21 SBA7 DBA6 43 GND GND 65 PAD00 PAD01 22 (Key) (Key) 44 RSVD RSVD 66 RSVD RSVD

B66

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4.3.1 AGP CONFIGURATION

AGP bus operations require the configuration of certain parameters involving system memory access by the AGP graph ics adapter. The AGP bus interface is configur ed as a PCI device integra t ed withi n the nort h bridge (82440LX, device 1) component. T he AGP function is, from the PCI bus perspective, treated essentially as a PCI/PCI-type bridge and configured through PCI configuration registers (Table 4-8). Configuration is accomplished by BIOS during POST.

NOTE:

Configuration of the AGP bus inter face i nvolves both device 0 and device 1 of the 82440LX. Device 0 registers (listed in Table 3-6) include functions that affect basic control of th e AGP. The configuration process of both devices occurs even if the AGP is not utilized.

Table 4–8.

PCI/AGP Brid g e Con fig uration Registers (82371, Function 1)

Table 4-8.

PCI/AGP B r idge Function Configurat ion Regis ters

(82440LX, Funct ion 1)

PCI Config. Addr. Register

00, 01h Vender ID 8086h 1Bh Sec. Master Latency Timer 00h 02, 03h Device ID 7181h 1Ch I/O Base Address F0h 04, 05h Command 0000h 1Dh I/O Limit Address 00h 06, 07h Status 02A0h 1E, 1Fh Sec. PCI/PCI Status 02A0h 08h Revision ID 00h 20, 21h Memory Base Address FFF0h 09-0Bh Class Code 22, 23h Memory Limit Address 0000h 0Eh Header Type 01h 24, 25h Prefetch Mem. Base Addr. FFF0h 18h Primary Bus Number 00h 26, 27h Prefetch Mem. Limit Addr. 0000h 19h Secondary Bus Number 00h 3E, 3Fh PCI/PCI Bridge Control 0000h 1Ah Subordinate Bus Number 00h -- -- --

NOTE:

Assume unmarked locations/gaps as reserved. Refer to Intel documentation for detailed register descriptions.

Reset Value

PCI Config. Addr. Register

Reset Value

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4.4 ISA BUS OVERVIEW

(2)

Technical Reference Guide

NOTE:

This section describes the ISA bus in general and highlights bus implementation in this particular system. For detailed information regarding ISA bus operation, refer to the Compaq Extended Industry Standard Architecture (EISA)

Technical Reference Guide.

The industr y standar d a rchitecture (ISA) bus provides an 8-/16-bit path for standard I/O peripherals as well as for optional devices that can be installed in the ISA expansion slots. Figure 4-5 shows the key functions and devices that reside on the ISA bus.

PCI Bus

Keyboard/

Mouse I/F

PCI/ISA

Bridge Function

8-/16-Bit ISA Bus

PC 87307B I/O Controller

Diskette

I/F

Serial I/F

BIOS ROM and Buffers

Parallel

I/F

IrDA

I/F

Audio

Controller

ISA Connectors (3)

System

Management

Controller

Figure 4–6.

ISA Bus Bl oc k Diagram

Both desktop and minitower systems provide three ISA connectors for accommodating ISA expansion cards.

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Chapter 4 System Support

4.4.1 ISA CONNECTOR

16-Bit ISA Connection

8-Bit ISA Connection

B1D1

Figure 4–7.

Table 4–9.

ISA Expansion Connector

ISA Expansion Connector Pinout

Table 4-9.

ISA Expansion Connector Pinout

16-Bit ISA Interface

8-Bit ISA Interface

Pin Signal Pin Signal P in Signal Pin Signal

B01 GND A01 I/O CHK- D01 M16- C01 SBHEB02 RESDRV A02 SD7 D02 I/O16- C02 LA23 B03 +5 VDC A03 SD6 D03 IRQ10 C03 LA22 B04 IRQ9 A04 SD5 D04 IRQ11 C04 LA21 B05 -5 VDC A05 SD4 D05 IRQ12 C05 LA20 B06 DRQ2 A06 SD3 D06 IRQ15 C06 LA19 B07 -12 VDC A07 SD2 D07 IRQ14 C07 LA18 B08 NOWS- A08 SD1 D08 DAK0- C08 LA17 B09 +12 VDC A09 SD0 D09 DRQ0 C09 MRDCB10 GND A10 BUSRDY D10 DAK5- C10 MWTCB11 SMWTC- A11 DMA D11 DRQ5 C11 SD8 B12 SMRDC- A12 SA19 D12 DAK6- C12 SD9 B13 IOWC- A13 SA18 D13 DRQ6 C13 SD10 B14 IORC- A14 SA17 D14 DAK7- C14 SD11 B15 DAK3- A15 SA16 D15 DRQ7 C15 SD12 B16 DRQ3 A16 SA15 D16 +5 VDC C16 SD13 B17 DAK1 A17 SA14 D17 GRAB- C17 SD14 B18 DRQ1 A18 SA13 D18 GND C18 SD15 B19 REFRESH- A19 SA12 B20 BCLK A20 SA11 B21 IRQ7 A21 SA10 B22 IRQ6 A22 SA9 B23 IRQ5 A23 SA8 B24 IRQ4 A24 SA7 B25 IRQ3 A25 SA6 B26 DAK2- A26 SA5 B27 T-C A27 SA4 B28 BALE A28 SA3 B29 +5 VDC A29 SA2 B30 OSC A30 SA1 B31 GND A31 SA0

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4.4.2 ISA BUS TRANS ACTIONS

The ISA bus supports 8- and 16-bit transfers at an 8-MHz rate. Devices limited to 8-bit transfers use the lower byte portion (data lines 7..0) while 16-bit transfers use the full bandwidth (data lines 15..0). Addressing is handled by two classifications of address signals: latched and latchable. Latched address signals ( SA19..0) select the specific byte within the 1-MB section of memory defined by address lines LA23..17. Latchable address lin es (LA23..17) provide a longer setup time for pre-chip selection or for pre-address decoding for high-speed memory and allow access to up to 16-MB of physical memory on the ISA bus. The SA19..17 signals ha ve the same values as the LA19..17 signals for all memory cycles. The I/O cycles use only the SA15..0 signals.

The key control signals are described as follows: ♦ MRDC- (Memory Read Cycle): MRDC- is active on all ISA memory reads accessing

memory from 000000h to FFFFFFh.

♦ SMEMR- (System Memory Read): SMEMR- i s a sserted by the PCI/ISA br i d g e to request an

ISA memory device to drive data onto the data lines for accesses below one megabyte. SMEMR- is a delayed version of MRDC-.

♦ MWTC- (Memory Write Cycle): MWTC- is active on all ISA memory write cycles accessing

memory from 000000h to FFFFFFh.

♦ SMEMW- (System Memor y Writ e): SMEMW- is asser t ed by the PCI/ I SA br idge to request

an I S A m emory device to accept data from the data lines for access below one megabyte. SMEMW- is a delayed version of MWTC-.

♦ IORC- (Input/Output Read Cycle): IORC- commands an ISA I/O device to drive data onto

the data lines.

♦ IOWC- (Input/Output Write Cycle): IOWC- commands an ISA I/O device to accept da ta

from the data lines.

♦ SBHE- (System Byte High Enable): SBHE- indicates that a byte is being transferred on the

upper half (D15..8) of the data lines.

♦ SA0- (System Address Bit <0>): This bit is the complement of SBHE- and indicates that a

byte is being transferred on the lower half (D7..0) of the data lines.

♦ M16- (16-bit Memory Cycle): M16- is asserted by 16-bit ISA devices to indicate 16-bit

memory cycle capability.

♦ IO16- (16-bit I/O Cycle): IO16- is asserted by 16-bit ISA devices to indicate 16-bit I/O cycle

transfer capability.

Technical Reference Guide

If the a ddress on the SA li nes is a bove one mega byt e , SMRD C- and SMWTC- will not be active. The MRDC- and MWTC- signals are active for memory accesses up to 16 megabytes and can be used by any device that uses the full 16-bit ISA bus. To request a 16-bit transfer, a device asserts either the M16- (memory) or IO16- (I/O) signal when the device is addressed.

When another device (such as a DMA d evice or another bus master ) t akes control of the ISA, the Bus Address Latch Enable (BALE) signal is held active for the duration of the operation. As a result , signals LA23..17 are always enabled and must be held stable for the duration of each bus cycle.

When the address changes, devices on the bus may decode the latchable address (LA23..17) lines and then latch them. This ar r a n gement allows devices to decode chip selects and M16- before the next cycle actually begins.

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Chapter 4 System Support

The following guidelines apply to optional ISA devices installed in the system: ♦ On bus lines that can be driven by a controller board, the driver should be able to sink a

minimum of 20 ma at 0.5 VDC and source 2 ma at 3.75 VDC.

♦ On bus lines that are driven in the low direction only (open collector), the driver should be

able to sink 20 ma at 0.5 VDC.

♦ The load on any logic li ne from a single bus s lot sh ould n ot ex ceed 2 .0 ma in the l ow state

(at 0.5 VDC) or 0.1 ma in the high state (at 3.75 VDC).

♦ The logic-high voltage at the bus ranges from 3.75 VDC to 5.5 VDC. The logic low voltage

ranges from 0 VDC to 0.8 VDC.

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4.4.3 DIRECT MEM O RY ACCES S

Direct Memory Access (DMA) is a m et hod by which an ISA device accesses system m em ory without involving the micr oprocessor. DMA is n or mally used to transfer blocks of data to or from an ISA I/O device. DMA reduces the amoun t of CPU int eraction s wit h memory, freeing th e CPU for other processing tasks.

Technical Reference Guide

NOTE:

This section descri bes DMA in gener a l . For detailed information regarding DMA operation, refer to the Compaq Extended Industry Standard Architecture (EISA) Technical Reference Guide. Note, however, that EISA enhancements as described in the referenced document ar e n ot supported in this (ISA only) system.

The South Bridge component i ncludes the equivalent of two 8237 DMA controllers cascaded together to provide eight DMA chann els. T a ble 4-10 lists th e default configuration of the DMA channels.

Table 4–10.

Default DMA Ch a nnel Assi g nment s

Table 4-10.

Default DMA Channel Assignments

DMA Channel Device ID

Controller 1 (byte transfers) 0 1 2 3 Controller 2 (word transfers) 4 5 6 7

Spare & ISA conn. pins D8, D9 Audio subsystem & ISA conn. pins B17, B18 Diskette drive & ISA conn. pins B6, B26 ECP LPT1 & ISA conn. pins B15, B16

Cascade for controller 1 Spare & ISA conn. pins D10, D11 Spare & ISA conn. pins D12, D13 Spare & ISA conn. pins. D14, D15

All cha nnels i n DMA controller 1 oper ate at a higher pr iority than those in controller 2 . Note that channel 4 is not available for use other than its cascading function for controller 1. The DMA controll er 2 can transfer words only on an even addr ess bound a ry. The DMA cont roller and page register define a 24-bit address that allows data transfers within the address space of the CPU. The DMA contr oll ers operate a t 8 MHz.

The DMA l ogi c is accessed throug h two types of I/O mapped registers; pa g e regist ers an d controller registers. The mapping is th e same regardless of the support chipset used.

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Chapter 4 System Support

4.4.3.1 Page Registers

The DMA pag e register con tain s the eight most significant bits of the 24-bit address and works in conjunction with the DMA controllers to define the complete (24-bit)address for the DMA channels. T able 4-11 lists th e page register port a ddresses.

Table 4–11.

DMA Page Register Ad dresses

Table 4-11.

DMA Channel Page Register I/O Port

Controller 1 (byte transfers) Ch 0 Ch 1 Ch 2 Ch 3 Controller 2 (word transfers) Ch 4 Ch 5 Ch 6 Ch 7 Refresh 08Fh [see note]

NOTE: The DMA memory page register for the refresh channel must be programmed with 00h for proper operation.

DMA Page Register Addr es s es

087h 083h 081h 082h

n/a 08Bh 089h 08Ah

The memory address is derived as follows:

24-Bit Address - Controller 1 (Byte Tran sfers) 8-Bit Page Register 8-Bit DMA Cont roller A23..A16 A15..A00

24-Bit Address - Controller 2 (Word Transfers) 8-Bit Page Register 16-Bit DMA Controller A23..A17 A16..A01, (A00 = 0)

Note that a d d ress lin e A16 fr om the DMA memor y page register is disabled when DMA controll er 2 is selected. Add ress line A00 is not con nected to DMA controller 2 a nd is al ways 0 when wor d -len g th t ransfers are selected.

By not connecting A00, the following applies:

♦ The size of the the block of data that can be moved or addressed is measured in 16-bits

(words) rather tha n 8-bits (bytes).

♦ The words must always be addressed on an even boundary.

DMA controll er 1 can move up to 64 Kbytes of data per DMA transfer. DMA cont roller 2 can move up to 64 Kwords (128 Kbytes) of data per DMA tra nsfer. Word DMA oper ations are only possible between 16-bit memory and 16-bit peripherals.

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The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit memory bus and the ISA bus. The refresh addr ess is provided on lines SA00 through SA08. Address lines LA23..17, SA18,19 are driven low.

The remaining address lines are in an undefined state during the refresh cycle. The refresh operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The refresh rate is 128 refresh cycles in 2.038 ms.

4.4.3.2 DMA Controller Registers

Table 4-12 lists th e DMA Cont roller Registers and their I/O port addresses. Note that there is a set of register s for each DMA contr oller.

Technical Reference Guide

Table 4–12.

DMA Contr oll er Registers

Table 4-12.

DMA Controller Regist er s

Status 008h 0D0h R Command 008h 0D0h W Mode 00Bh 0D6h W Write Single Mask Bit 00Ah 0D4h W Write All Mask Bits 00Fh 0DEh W Software DRQx Request 009h 0D2h W Base and Current Address - Ch 0 000h 0C0h W Current Address - Ch 0 000h 0C0h R Base and Current Word Count - Ch 0 001h 0C2h W Current Word Count - Ch 0 001h 0C2h R Base and Current Address - Ch 1 002h 0C4h W Current Address - Ch 1 002h 0C4h R Base and Current Word Count - Ch 1 003h 0C6h W Current Word Count - Ch 1 003h 0C6h R Base and Current Address - Ch 2 004h 0C8h W Current Address - Ch 2 004h 0C8h R Base and Current Word Count - Ch 2 005h 0CAh W Current Word Count - Ch 2 005h 0CAh R Base and Current Address - Ch 3 006h 0CCh W Current Address - Ch 3 006h 0CCh R Base and Current Word Count - Ch 3 007h 0CEh W Current Word Count - Ch 3 007h 0CEh R Temporary (Command) 00Dh 0DAh R Reset Pointer Flip-Flop (Command) 00Ch 0D8h W Master Reset (Command) 00Dh 0DAh W Reset Mask Register (Command) 00Eh 0DCh W

NOTE:

For a detailed description of the DMA registers, refer to the

Compaq EISA Technical Reference Guide

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Chapter 4 System Support

4.4.4 INTERRUPTS

The microprocessor uses two types of interrupts; maskable and nonmaskable. A maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI and CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor but may be inhibited by h ar dware or software means external to the microprocessor.

4.4.4.1 Maskable Interrupt s

The maskable interrupt is a hardware-generated signal used by peripheral functions within the system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-D (PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the interrupt (INTR) input to the microprocessor. The microprocessor halts execution to determine the source of the interrupt and then services the peripheral as appropriate.

ISA Peripherals

& SM Functions

PCI Peripherals

Figure 4–8.

The South Bridge component, which includes the equivalent of two 8259 interrupt controllers cascaded together, handles the standard AT-type (ISA) interrupt signals (IRQn). The South Brid g e also r eceives th e PCI inter rupt signal s ( P I RQA - ..PIRQD - ) from PCI d evi ces . Th e P C I interrupts can be configured by PCI Configuration Registers 55h..57h to share the standard ISA interrupts (IRQn). The power-up default configuration has the PIRQn disabled. Table 4-13 lists the standard source configuration for maskable interrupts and their priorities. If more than one interrupt is pending, the highest priority (lowest number) is processed first.

IRQ1,3..7,

9..12, 14,15

PIRQA-..D-

South Bridge Component

IRQ1,3..7

PCI IRQ

Routing

IRQ9..12, 14,15

Interrupt

Cntlr. 2

IRQ2

Maskable Interrupt Pr ocessing, Block Diagram

Interrupt

Cntlr. 1

INTR

Microprocessor

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Technical Reference Guide

Table 4–13. Maskable Interrupt Priorities and Assignments

Table 4-13.

Maskable Interrupt Priorities and Assignments

Priority Signal Label Source (Typical) Notes

1 IRQ0 Interval timer 1, counter 0 2 IRQ1 Keyboard 3 IRQ8- Real-time clock 4 IRQ9 Spare and ISA connector pin B04 5 IRQ10 Spare and ISA connector pin D03 6 IRQ11 Spare and ISA connector pin D04 7 IRQ12 Mouse and ISA connector pin D05 8 IRQ13 Coprocessor (math) 9 IRQ14 IDE primary I/F and ISA connector pin D07 10 IRQ15 IDE secondary I/F and ISA connector pin D06 11 IRQ3 Serial port (COM2) and ISA connector pin B25 12 IRQ4 Serial port (COM1) and ISA connector pin B24 13 IRQ5 Audi o subsystem and ISA connector pin B23 14 IRQ6 Diskette drive controller and ISA connector pin B22 15 IRQ7 Parallel port (LPT1)

-- IRQ2 NOT AVAILABLE (Cascade from interrupt controller 2)

NOTE:

[3] Alternate available interrupts: IRQ5, 9,10,11,14, or 15

Interrupt s gener a ted by PCI devices can be configured to share the standard AT (IRQn) int er rupt lines. Refer to section 4.2.5 “PCI Interrupt Mapping” for information on PCI interrupts.

Maskable Interrupt processing is controlled and monitored through standard AT-type I/Omapped registers. These registers ar e listed in Table 4-14.

Table 4–14. Maskable Interrupt Cont rol Registers

Table 4-14.

Maskable Interr upt Control Registers

I/O Port Register

020h Base Address, Int. Cntlr. 1 021h Initialization Command Word 2-4, Int. Cntlr. 1 0A0h Base Address, Int. Cntlr. 2 0A1h Initialization Command Word 2-4, Int. Cntlr. 2

The initialization and operation of the interrupt control registers follows standard AT-type protocol.

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Chapter 4 System Support

4.4.4.2 Non-Maskable Interrupts

Non-maskble interrupts cannot be masked (inhibited) within the microprocessor itself but may be maskable by software using logic external to the microprocessor. There are two nonmaskable interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable interrupts, with the SMI- having top priority over all interrupts including the NMI-.

NMI- Generation

The Non-Maskable Interrupt (NMI-) signa l can be generated by one of the following actions:

♦ Parity errors detected on the ISA bus (activating IOCHK-). ♦ Parity errors detected on a PCI bus (activating SERR- or PERR-). ♦ Microprocessor internal error (activating IERRA or IERRB)

The IOCHK-, SERR-, and PERR- signals are routed through the south bridge component, which in turn activates the NMI to the microprocessor.

The NMI Status Register at I/O port 061h contains NMI source and status data as follows:

NMI Status Register 61h

Bit Function

7 NMI Status:

0 = No NMI from system board parity error. 1 = NMI requested, read only

6 IOCHK- NMI:

0 = No NMI from IOCHK-

1 = IOCHK- is active (low), NMI requested, read only 5 Interval Timer 1, Counter 2 (Speaker) Status 4 Refresh Indicator (toggles with every refresh) 3 IOCHK- NMI Enable/Disable:

0 = NMI from IOCHK- enabled

1 = NMI from IOCHK- disabled and cleared (R/W) 2 System Board Parity Error (PERR/SERR) NMI Enable:

0 = Parity error NMI enabled

1 = Parity error NMI disabled and cleared (R/W) 1 Speaker Data (R/W) 0 Inteval Timer 1, Counter 2 Gate Signal (R/W)

0 = Counter 2 disabled

1 = Counter 2 enabled

Functions not related to NMI activity.

After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2> or <3> respectively.

The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal. Writing 80h to this register masks generation of the NMI-. Note that the lower six bits of register at I/O port 70h affect RTC operation and should be considered when changing NMI- generation status.

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Technical Reference Guide

SMI- Generation

The SMI- (System Management Interrupt) is typically used for power management functions. When power man agement is enabled, inactivity timers are monitored. When a timer times out, SMI- is asserted and invokes the microprocessor’s SMI handler. The SMI- handler works with the APM BIOS to service the SMI- accordi ng to th e cau se of th e timeout.

Although the SMI- is primarily used for power managment the interrupt is also employed for the QuickLock/QuickBlank functions as well.

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Chapter 4 System Support

4.4.5 INTERVAL TIMER

The interval timer generates pulses at software (programmable) intervals. A 8254-compatible timer is integrated into the South Bridge chip. The timer function provides three counters, the functions of which ar e listed in T able 4-15.

Table 4–15.

Interval Timer Functions

Table 4-15.

Interval Tim er Functions

Counter Function Gate Clock In Clock Out

0 System Clock Always on 1.193 MHz IRQ0 1 Refresh Always on 1.193 MHz Refresh Req. 2 Speaker Tone Port 61, bit<0> 1.193 MHz Speaker Input

The interval timer is controlled through the I/O mapped registers listed in Table 4-16.

Table 4–16.

Interval Timer Control Registers

Table 4-16.

Interval Timer Control Registers

I/O Port Register

040h Read or write value, counter 0 041h Read or write value, counter 1 042h Read or write value, counter 2 043h Control Word

Interval timer operation follows standard AT-type protocol. For a detailed description of timer registers and operation, refer to the Compaq Extended Industry Standard Architecture Expansion

Bus Technical Reference Guide.

4.4.6 ISA CONFIGURATION

The working relationship between the PCI and ISA buses requires that certain parameters be configured. The PC/ISA bridge function of the South Bridge component includes configuration registers to set parameters such as PCI IRQ routing and top-of-memory available to ISA/DMA devices. These parameters are programmed by BIOS during power-up, using registers listed previously in Table 4-6.

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4.5 SYSTEM CLOCK DISTRIBUTION

The system uses an IC Works W48C67 or compatible part for generation of most clock signals. Table 4-17 lists the clock signals and to which components they are distributed.

Technical Reference Guide

Table 4–17.

Clock Generation and Distribution

Table 4-17.

Clock Generation and Distribution

Signal Source Destination

66, 60 MHz (CPUCLK) [1] 48 MHz “ South Bridge, 87307 33, 30 MHz (PCICLK) [2] 20 MHz “ TLAN3.1 (NIC)

14.31818 MHz Crystal W48C67

14.31818 MHz W48C67 [3] South Bridge, ES1868. ISA slots 8 MHz (BCLK) [4] S. Bridge ISA slots 32 KHz Crystal 87307

NOTES:

[1] Depending on speed configuration (refer to Chapter 3, “Processor/Memory Subsystem”). [2] PCICLK = CPUCLK/ 2: 33 MHz if CPUCLK = 66 MHz, 30 MHz if CPUCL K = 60 MHz [3] Routed through buffer before destination. [4] BCLK = PCICLK/4: 8.33 MHz if PCICLK = 33 MHz, 7.5 MHz if PCICLK = 30 MHz

W48C67 Pentium II, North Bridge,

AGP connector

“ PCI Slots, South Bridge, TLAN,

SCSI controller

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Chapter 4 System Support

4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY

The Real-time clock (RTC) and configuration memory functions are provided by the PC87307 I/O controller. The RTC uses the first 14 of 256 bytes of configuration memory and is MC146818-compatible. As shown in the following figure, the 87307 controller provides 256 bytes of configuration memory, divided into two 128-byte banks. The RTC/configuration memory can be accessed using conventional OUT and IN assembly language instructions using I/O ports 70h/71h, alth ough th e suggested method is to use the INT15 AX=E823h BIOS call.

87307

Upper Config. Memory Area

(128 bytes)

Lower Config.

Memory Area

(114 bytes)

RTC Area (14 bytes)

FFh

80h 7Fh

0Eh 0Dh

00h

Figure 4–9.

NOTE:

Non-volatile (NVRAM) storage of PCI, ESCD, and Environmental Variable (EV) data

0Dh 0Ch 0Bh

0Ah

09h 08h 07h 06h 05h 04h 03h 02h 01h 00h

Year

Month

Date of Month

Day of Week

Hours (Alarm)

Hours (Timer) Minutes (Alarm) Minutes (Timer)

Seconds (Alarm) Seconds (Timer)

Configuration Memory Map

is provided by port i ons of the 256-KB system BIOS ROM component.

A 3-VDC battery is used for maintaining the RTC and configuration memory while the system is powered down. This battery is soldered on the system board and is designed to last from 5-7 years. Once expired, the soldered battery is by-passed by connecting a replacement battery (Compaq p/n 160274-001 or equivalent 4.5 VDC @ 660 ma alkaline battery) to header E50 (pins 9-12, and moving th e jumper from pins 1 and 2 to pins 2 and 3.

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4.6.1 CONFIGURATION MEM ORY BYTE DEFINITIONS

Table 4-18 lists the mapping of the configuration memory.

Technical Reference Guide

Table 4–18.

Configuration Memory (CMOS) Map

Table 4-18.

Configuration Memory ( CM OS) Map

Location Function Location Function

00-0Dh Real-rime clock 41h-44h Hoof Removal Time Stamp 0Eh Diagnostic status 45h Keyboard snoop byte 0Fh System reset code 46h Diskette drive status 10h Diskette drive type 47h Last IPL device 11h Reserved 48h-4Bh IPL priority 12h Hard drive type 4Ch-4Fh BVC priority 13h Security functions 51h ECC DIMM status 14h Equipment installed 52h Board revision (from boot block) 15h Base memory size, low byte/KB 53h SWSMI command 16h Base memory size, high byte/KB 54h SWSMI data 17h Extended memory, low byte/KB 55h APM command 18h Extended memory, high byte/KB 56h Erase-Ease keyboard byte 19h Hard drive 1, primary controller 57h-76H Saved CMOS location 10h-2Fh 1Ah Hard drive 2, primary controller 77h-7Fh Administrator password 1Bh Hard drive 1, secondary controller 80h ECMOS diagnostic byte 1Ch Hard drive 2, secondary controller 81h-82h Total super ext. memory tested good 1Dh Enhanced hard drive support 83h Microprocessor chip ID 1Eh Reserved 84h Microprocessor chip revision 1Fh Power management functions 85h Hood removal status byte 24h System board ID 86h Fast boot date 25h System architecture data 87h Fast boot status byte 26h Auxiliary peripheral configuration 8Dh-8Fh POST error logging 27h Speed control external drive 90h-91h Total super extended memory configured 28h Expanded/base mem. size, IRQ12 92h Miscellaneous configuration byte 29h Miscellaneous configuration 93h Miscellaneous PCI features 2Ah Hard drive timeout 94h ROM flash/power button status 2Bh System inactivity timeout 97h Asset/test prompt byte 2Ch Monitor timeout, Num Lock Cntrl 9Bh Ultra-33 DMA enable byte 2Dh Additional flags 9Ch Mode-2 Configuration 2Eh-2Fh Checksum o f locations 10h-2Dh 9Dh ESS audio configuration 30h-31h Total extended memory tested 9Eh ECP DMA configuration 32h Century 9Fh-AFh Serial number 33h Miscellaneous flags set by BIOS B0h-C3h Custom drive types 65, 66, 68, 15 34h International language C7h Serial port 1 address 35h APM status flags C8h Serial port 2 address 36h ECC POST test single bit C9h COM1/COM2 port configuration 37h-3Fh Power-on password DEh-DFh Checksum o f locations 90h to DDh 40h Miscellaneous Disk Bits E0h-FFh Client Management error log

NOTE: Assume unmarked gaps are reserved.

Default values (where applicable) are given for a standard system as shipped from the factory. The contents of configuration memory can be drained (cleared) by th e followin g procedure:

1. Disconnect AC power.

2. Remove jumper from pins 1 and 2 (or 2 and 3) of header E50 an d pl a ce on pins 5 and 6 for several seconds.

3. Replace jumper to original configuration.

4. Restore AC p ower connection.

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Chapter 4 System Support

RTC Control Register A, B y t e 0 Ah

Bit Function

7 Update in Progress. Read only.

0 = Time update will not occur before 2444 us 1 = Time update will occur within 2444 us

6..4 Divider Chain Control. R/W. 00x = Oscillator disabled. 010 = Normal operation (time base frequency = 32.768 KHz). 11x = Divider chain reset.

3..0 Periodic Interrupt Control. R/W. Specifies the periodic interrupt interval. 0000 = none 1000 = 3.90625 ms 0001 = 3.90625 ms 1001 = 7.8125 ms 0010 = 7.8125 ms 1010 = 15. 625 ms 0011 = 122.070 us 1011 = 31.25 ms 0100 = 244.141 us 1100 = 62.50 ms 0101 = 488.281 us 1101 = 125 ms 0110 = 976.562 us 1110 = 250 ms 0111 = 1.953125 ms 1111 = 500 ms

RTC Control Register B, Byte 0Bh

Bit Function

7 Time Update Enable/disable

0 = Normal operation, 1 = Disable time updating for time set

6 Periodic Interrupt Enable/Disable.

0 = Disable, 1 = Enable interval specified by Register A

5 Alarm Interrupt Enable/disable

0 = Disabled, 1 = Enabled

4 End-of-Update Interrupt Enable/Disable

0 = Disabled, 1 = Enabled

3 Reserved (read 0) 2 Time/Date Form a t Se le ct

0 = BCD format, 1 = Binary format

1 Time Mode

0 = 12-lhour mode, 1 = 24-hour mode

0 Automatic Daylight Savings Time Enable/Disable

0 = Disable 1 = Enable (Advance 1 hour on 1

Sunday in April, retreat 1 hour on last Sunday in October).

RTC Status Register C, Byte 0Ch

Bit Function

7 If set, interrupt output signal active (read only) 6 If set, indicates periodic interrupt flag 5 If set, indicates alarm interrupt 4 If set, indicates end-of-update interrupt

3..0 Res erved

RTC Status Register D, Byte 0Dh

Bit Function

7 RTC Power Status

0 = RTC has lost power 1 = RTC has not lost power

6..0 Res erved

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Configuration Byte 0Eh, Diagnostic Status

Default Value = 00h

This byte contains diagnostic status data.

Configuration Byt e 0 Fh, Sy stem Reset Code

Default Value = 00h

This byte contains the system reset code.

Configuration Byte 10h, Diskette Drive Type

Bit Function

7..4 Primary (Drive A) Diskette Drive Type

3..0 Secondary (Drive B) Diskette Drive Type

Valid values for bits <7..4> and bits <3..0>:

0000 = Not installed

0001 = 360-KB drive 0010 = 1.2-MB drive 0011 = 720-KB drive

0100 = 1.44-MB/1.25-MB drive 0110 = 2.88-MB drive

(all other values reserved)

Technical Reference Guide

Configuration Byte 12h, Hard Drive Type

Bit Function

7..4 Primary Controller 1, Hard Drive 1 Type: 0000 = none 1000 = Type 8 0001 = Type 1 1001 = Type 9 0010 = Type 2 1010 = Type 10 0011 = Type 3 1011 = Type 11 0100 = Type 4 1100 = Type 12 0101 = Type 5 1101 = Type 13 0110 = Type 6 1110 = Type 14 0111 = Type 7 1111 = other (use bytes 19h)

3..0 Primary Controller 1, Hard Drive 2 Type: 0000 = none 1000 = Type 8 0001 = Type 1 1001 = Type 9 0010 = Type 2 1010 = Type 10 0011 = Type 3 1011 = Type 11 0100 = Type 4 1100 = Type 12 0101 = Type 5 1101 = Type 13 0110 = Type 6 1110 = Type 14 0111 = Type 7 1111 = other (use bytes 1Ah)

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Chapter 4 System Support

Configuration Byte 13h, Security Functions

Default Value = 00h

Bit Function

7 Reserved 6 QuickBlank Enable After Standby:

0 = Disable 1 = Enable

5 Administrator Password:

0 = Not present 1 = Present

4 Reserved 3 Diskette Boot Enable:

0 = Enable 1 = Disable

2 QuickLock Enable:

0 = Disable 1 = Enable

1 Network Server Mode/Security Lock Override:

0 = Disable 1 = Enable

0 Password State (Set by BIOS at Power-up)

0 = Not set 1 = Set

Configuration Byte 14h, Equipment Installed

Default Value (standard configuration) = 03h

Bit Function

7,6 No. of Diskette Drives Installed:

00 = 1 drive 10 = 3 drives 01 = 2 drives 11 = 4 drives

5..2 Res erved

1 Coprocessor Present

0 = Coprocessor not installed 1 = Coprocessor installed

0 Diskette Drives Present

0 = No diskette drives installed 1 = Diskette drive(s) installed

Configuration Bytes 15h and 16h, Base Memory Size

Default Value = 280h

Bytes 15h and 16h hold a 16-bit value that specifies the base memory size in increments of 1-KB (1024) bytes. Valid base memory sizes are 512-KB and 640-KB.

Configuration Bytes 17h and 18h, Extended Memory Size

Bytes 17h and 18h hold a 16-bit value that specifies the extended memory size in increments of 1-KB (1024) byt es.

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Configuration Bytes 19h-1Ch, Hard Drive Types

Byte 19h contains the hard drive type for drive 1 of the primary controller if byte 12h bits <7..4> hold 1111b. Byte 1Ah contains the hard dr ive type for drive 2 of the primary controller if byte 12h bits <3..0> hold 1111b. Bytes1Bh and 1Ch contain the hard drive types for hard drives 1 and 2 of the secondary controller.

Configuration Byt e 1 Dh, Enhanced IDE Hard Drive Support

Default Value = F0h

Bit Function

7 EIDE - Drive C (83h) 6 EIDE - Drive D (82h) 5 EIDE - Drive E (81h) 4 EIDE - Drive F (80h)

3..0 Res erved

Values for bits <7..4> :

0 = Disable 1 = Enable for auto-configure

Configuration Byte 1Fh, Power Management Functions

Default Value = 00h

Bit Function

7..4 Res erved

3 Slow Processor Clock for Low Power Mode

0 = Processor runs at full speed 1 = Processor runs at slow speed

2 Reserved 1 Monitor Off Mode

0 = Turn monitor power off after 45 minutes in standby 1 = Leave monitor power on

0 Energy Saver Mode Indicator (Blinking LED)

0 = Disable 1 = Enable

Configuration Byt e 2 4 h, Sy st e m B oar d Ide nt i f i cation

Default Value = 7Eh

Configuration memory location 24h holds the system board ID.

Configuration Byte 25h, System Architecture Data

Default Value = 0Bh

Bit Function

7..4 Res erved

3 Unmapping of ROM:

0 = Allowed 1 = Not allowed

2 Reserved

1,0 Diagnostic Status Byte Address

00 = Memory locations 80C00000h-80C00004h 01 = I/O ports 878h-87Ch 11 = neither place

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Configuration Byte 26h, Auxiliary Peripheral Configuration

Default Value = 00h

Bit Function

7,6 I/O Delay Select

00 = 420 ns (default) 01 = 300 ns 10 = 2600 ns 11 = 540 ns

5 Alternative A20 Switching

0 = Disable port 92 mode 1 = Enable port 92 mode

4 Bi-directional Print Port Mode

0 = Disabled 1 = Enabled

3 Graphics Type

0 = Color 1 = Monochrome

2 Hard Drive Primary/Secondary Address Select:

0 = Primary 1 = Secondary

1 Diskette I/O Port

0 = Primary 1 = Secondary

0 Diskette I/O Port Enable

0 = Primary 1 = Secondary

Configuration Byte 27h, Speed Control/External Drive

Default Value = 00h

Bit Function

7 Boot Speed

0 = Max MHz 1 = Fast speed

6..0 Res erved

Configuration Byte 28h, Expanded and Base Memory, IRQ12 Select

Default Value = 00h

Bit Function

7 IRQ12 Select

0 = Mouse 1 = Expansion bus

6,5 Base Memory Size:

00 = 640 KB 01 = 512 KB 10 = 256 KB 11 = Invalid

4..0 Internal Compaq Memory: 00000 = None 00001 = 512 KB 00010 = 1 MB 00011 = 1.5 MB . . 11111 = 15.5 MB

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Configuration Byte 29h, Miscellaneous Configuration Data

Default Value = 00h

Bit Function

7..5 Res erved

4 Primary Hard Drive Enable (Non-PCI IDE Controllers)

0 = Disable 1 = Enable

3..0 Res erved

Configuration Byte 2Ah, Hard Drive Timeout

Default Value = 02h

Bit Function

7..5 Res erved

4..0 Hard Drive Timeout 00000 = Disabled 00001 = 1 minute 00010 = 2 minutes . . 10101 = 21 minutes

Technical Reference Guide

Configuration Byte 2Bh, System Inactivity Timeout

Default Value = 23h

Bit Function

7 Reserved

6,5 Power Conservation Boot

00 = Reserved 01 = PC on 10 = PC off 11 = Reserved

4..0 System Inactive Timeout. (Index to SIT system tim eout record) 00000 = Disabled

Configuration Byte 2Ch, ScreenSave and NUMLOCK Control

Default Value = 00h

Bit Function

7 Reserved 6 Numlock Control

0 = Numlock off at power on 1 = Numlock on at power on

5 Screen Blank Control:

0 = No screen blank 1 = Screen blank w/QuickLock

4..0 ScreenSave Timeout. (Index to SIT monitor timeout record) 000000 = Disabled

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Configuration Byt e 2 Dh, Additional Fla g s

Default Value = 00h

Bit Function

7..5 Res erved

4 Memory Test

0 = Test memory on power up only 1 = Test memory on warm boot

3 POST Error Handling (BIOS Defined)

0 = Display “Press F1 to Continue” on error 1 = Skip F1 message

2..0 Reserved

Configuration Byte 2Eh, 2Fh, Checksum

These bytes hold the checksum of bytes 10h to 2Dh.

Configuration Byte 30h, 31h, Total Extended Memory Tested

This location holds the amount of system memory that checked good during the POST.

Configuration Byte 32h, Century

This location holds the Century value in a binary coded decimal (BCD) format.

Configuration Byte 33h, Miscellaneous Flags

Default Value = 80h

Bit Function

7 Memory Above 640 KB

0 = No, 1 = Yes

6 Reserved 5 Weitek Numeric Coprocessor Present:

0 = Not installed, 1 = Installed

4 Standard Numeric Coprocessor Present:

0 = Not installed, 1 = Installed

3..0 Reserved

Configuration Byte 34h, International Language Support

Default Value = 00h

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Configuration Byte 35h, APM Status Flags

Default Value = 11h

Bit Function

7..6 Power Conservation State: 00 = Ready 01 = Standby 10 = Suspend 11 = Off

5,4 Reserved

3 32-bit Connection:

0 = Disconnected, 1 = Connected

2 16-bit Connection

0 = Disconnected, 1 = Connected

1 Real Mode Connection

0 = Disconnected, 1 = Connected

0 Power Management Enable:

0 = Disabled 1 = Enabled

Technical Reference Guide

Configuration Byt e 3 6 h, E CC PO ST T e st Si ng l e Bit E r r ors

Default Value = 01h

Bit Function

7 Row 7 Error Detect 6 Row 6 Error Detect 5 Row 5 Error Detect 4 Row 4 Error Detect 3 Row 3 Error Detect 2 Row 2 Error Detect 1 Row 1 Error Detect

0 Row 0 Error Detect 0 = No single bit error detected. 1 = Single bit error detected.

Configuration Byt e 3 7 h-3 Fh, Power -On Password

These eight locations hold the power-on password.

Configuration Byte 40h, Miscellaneous Disk Data

Configuration Bytes 41h-44h, Hood Removal Time Stamp

These four bytes record the time at which the hood of the system was removed: Byte 41h, month & day Byte 42h, year and month Byte 43h, min ut es an d seconds Byte 44h, removal flag and minutes

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Configuration Byte 45h, Keyboard Snoop Data

Default Value = xxh

Bit Function

7 Cntrl/F10 Key Status:

0 = Cntrl & F10 keys not pressed 1 = Cntrl & F10 keys pressed

6 F10 Key Status:

0 = F10 key not pressed 1 = F10 key pressed

5..1 Res erved 0 Key Pressed Flag:

0 = Key not pressed 1 = Key pressed

Configuration Byte 46h, Diskette/Hard Drive Status

Default Value = xxh

Bit Function

7,6 Reserved

5 Partition On HD:

0 = Not set, 1 = Set

4 Setup Disk:

0 = Not present, 1 = Present

3 ROMPAQ or DIAGS Diskette:

0 = Not present, 1 = Present

2 Boot Diskette in Drive A:

0 = No, 1 = Yes

1 Drive B: Present:

0 = Not present, 1 = Present

0 Drive A: Present:

0 = Not present, 1 = Present

Configuration Bytes 47h-4Fh, IPL Data

These bytes hold initial program load (IPL) data for boot purposes : Byte 47h, last IPL device Bytes 48h-4Bh, IPL priority Byte 4Ch-4Fh, BCV priorit y

Configuration Byte 51h, ECC Status Byte

Default Value = xxh

Bit Function

7 ECC Status for DIMM 3 6 ECC Status for DIMM 2 5 ECC Status for DIMM 1 4 ECC Status for DIMM 0

3..0 Reserved

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Configuration Byte 52h, Board Revision

This byte hol ds the boa rd revision as copi e d from the boot block s e c tor.

Configuration Byte 53h, 54h, SW SMI Command/Data Bytes

Configuration Byte 55h, APM Command Byte

Configuration Byte 56h, Miscellaneous Flags Byte

Bit Function

7 CAS Latency:

0 = 2, 1 = 3

6 IR Port Enable Flag:

0 = Disabled (COM2 config. for standard serial port) 1 = Enabled (COM2 config. for IrDA)

5 Warm Boot Enable Flag:

0 = Disable, 1 = Enable

4 POST Terse/Verbose Mode

0 = Verbose, 1 = Terse

3..1 Erase Ease Keyboard Mode:

000 = Backspace/Spacebar 001 = Spacebar/Backspace 010 = Spacebar/Spacebar 011-111 = Invalid

0 Configurable Power Supply:

0 = Power switch active 1 = Power switch inhibited

Technical Reference Guide

Configuration Byte 57h-76h, CMOS Copy

Configuration Byt e s 7 7 h-7 Fh, Admini st r a t or Password

Configuration Byte 80h, CMOS Diagnostic Flags Byte

Default Value = 00h. Set bit indicates function is valid.

Bit Function

7 CMOS Initialization (Set CMOS to Default) 6 Setup password locked 5 PnP should not reject SETs because Diags is active 4 Reserved 3 Manufacturing diagnostics diskette found 2 Invalid electronic serial number 1 Boot maintenance partition once 0 Invalid CMOS checksum

Configuration Byte 81h, 82h, Total Super Extended Memory Tested

This byte holds the value of the amount of extended system memory that tested good during POST. The am oun t is gi ven in 64-KB increment s.

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Chapter 4 System Support

Configuration Byte 83h, Microprocessor Identification

This byte holds the component ID and chip revision of the microprocessor.

Configuration Byte 84h, Microprocessor Revision

Configuration Byte 85h, Administration Mode

Bit Function

7,6 Reserved

5 ESCD Buffering:

0 = No buffering, 1 = ESCD buffered at F000h.

4 Hood Lock Enable:

0 = Disabled, 1 = Enabled 3 User Mode Flag 2 Administration Mode Flag 1 Level Support:

0 = Level 1, 1 = Level 2 0 Feature Support Bit

0 = Disabled, 1 = Enabled

Configuration Byte 86h, Fast Boot Date

Configuration Byte 87h, Fast Boot Select

Bit Function

7..3 2 1 0

Configuration Byte 88h, Fast Boot Date (Year/Century)

Configuration Byte 89h, APM Resume Timer

Bit <7> indicates the timer status: 0 = disabled, 1 = timer set.

Configuration Byt e 8 Ah- 8Fh, APM Re sume Timer

These bytes hold th e APM timer values: Byte 8Ah, minutes Byte 8Bh, hours Byte 8Ch, day Byte 8Dh, month Byte 8Eh, year Byte 8Fh, century

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Technical Reference Guide

Configuration Byte 90h, 91h, Total Super Extended Memory Configured

This byte holds the value of the amount of extended system memory that is configured. The amount is given in 64-KB incr ement s.

Configuration Byte 92h, Miscellaneous Configuration Byte

Default Value = 18h

Bit Function

7..5 Res erved 4 Diskette Write Control:

0 = Disable 1 = Enable

3..1 Res erved 0 Diskette Drive Swap Control:

0 = Don’t swap 1 = Swap drive A: and B:

Configuration Byte 93h, PCI Configuration Byte

Default Value = 00h

Bit Function

7 Onboard SCSI Status:

0 = Hidden 1 = Active

6 Onboard NIC Status:

0 = Hidden 1 = Active

5 Onboard USB Status:

0 = Hidden

1 = Active 3 Reserved 2 ISA Passive Release:

0 = Enabled

1 = Disabled 1 PCI Bus Master Enable

0 = Enabled

1 = Disabled 0 PCI VGA Palette Snoop

0 = Disable

1 = Enable

If palette snooping is enabled, then a primary PCI graphics card may share a common palette with the ISA graphics card. Palette snooping should only be enabled if all of the following conditions are met:

♦ An IS A card connect s to a PCI g rap hics ca rd t hrou g h the VESA connector. ♦ The ISA card is connected to a color monitor. ♦ The ISA card uses th e RAMDAC on the PCI card ♦ The palette snooping feature (sometimes called “RAMDAC shadowing”) on t he PCI car d i s

enabled and functioning properly.

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Configuration Byte 94h, ROM Flash/Power Button Status

Default Value = 00h

Bit Function

7..5 Res erved 4 ROM Flash In Progress (if set) 3 Reserved 2 Power Button Inhibited (ifset) 1 User-Forced Bootblock (if set) 0 ROM Flash In Progress (if set)

Configuration Byt e 9 7 h, Asset/Test Pr ompt B yt e

Default Value = 00h

Bit Function

7,6 Test Prompt:

01 = Fake F1 10 = Fake F2 11 = Fake F10

5..0 Asset Value

Configuration Byte 9Bh, Ultra-33 DMA Enable Byte

Default Value = 00h

Bit Function

7..4 Res erved 3 Secondary Slave Enabled for U-33 if Set 2 Secondary Master Enabled for U-33 if Set 1 Primary Slave Enabled for U-33 if Set 0 Primary Master Enabled for U-33 if Set

Configuration Byte 9Ch, Mode-2 Configuration Byte

Default Value = 1Ch

Bit Function

7,6 Reserved

5 Mode 2 Support

0 = Disable 1 = Enable

4 Secondary Hard Drive Controller

0 = Disable 1 = Enable

3,2 Secondary Hard Drive Controller IRQ

00 = IRQ10 01 = IRQ11 10 = IRQ12 11 = IRQ15

1,0 Reserved

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Configuration Byt e 9 Dh, ESS Audio Configuration Byte

Default Value = 12h

Bit Function

7 Reserved for Game Port Enable

6,5 Audio Address

00 = 22xh 01 = 23xh 10 = 24xh 11 = 25xh

4,3 DMA Channel

00 = Disabled 01 = DMA0 10 = DMA1 11 = DMA3

2,1 IRQ Select

00 = IRQ9 01 = IRQ5 10 = IRQ7 11 = IRQ10

0 ESS Audio Chip Enable

0 = Enabled 1 = Disabled

Technical Reference Guide

Configuration Byte 9Eh, ECP DMA Configuration Byte

Default Value = 03h

Bit Function

7..4 Res erved 3 SafeStart Control:

0 = Disable 1 = Enable

2..0 ECP DMA Channel

000 = Invalid 100 = Disabled All other values (001-011, 101-111) refer to channel no.

Configuration Byte 9Fh-AFh, Asset Tag Serial Number

Configuration Byt e s B0h-C3h; Custom Hard Drive Information

These bytes contain the number of cylinders, heads, and sectors per track for hard drives C, D, E, and F respectively. The mapping for each drive is as follows:

Drive 65 (C) Drive 66 (D) Drive 68 (E) Drive 15 (F) Function

B0h B5h BAh BFh No. of Cylinders, Low Byte B1h B6h BBh C0h No. of Cylinders, High Byte B2h B7h BCh C1h No. of Heads B3h B8h BDh C2h Max ECC Bytes B4h B9h BEh C3h No. of Sectors Per Track

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Configuration Byte C7h, C8h, Serial Ports 1 and 2 (Respectively) Configuration Bytes

Default Value = FEh, 7Dh

Bit Function

7..2 Base I/O Address (in packed format)

(Algorithm: [Addr. - 200h] / 8) (i.e., 3Fh = 3F8h, 1Fh = 2F8h, 00 = 200h)

1..0 Interrupt:

00 = Reserved 01 = IRQ3 10 = IRQ4 11 = Reserved

Configuration Byt e s CAh, DBh; Chassi s Serial Number

Configuration Byt e s DE h, DFh; Checksum of Locations 90h-DDh

Configuration Bytes E0h-FFh; Client Management Error Log

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4.7 I/O MAP AND REGISTER ACCESSING

4.7.1 SYSTEM I/O MAP

Technical Reference Guide

Table 4–19.

System I/O Map

Table 4-19.

System I/O Map

I/O Port Function

0000..000Fh DMA Controller 1

0020..0021h Interrupt Controller 1

0040..0043h Timer 1 0060h Keyboard Controller Data Byte 0061h NMI, Speaker Control 0064h Keyboard Controller Command/Status Byte 0070h NMI Enable, RTC Address 0071h RTC Data 0078h, 0079h General Purpose I/O Ports 1 & 2 (87307 I/O controller)

0080..008Fh DMA Page Registers 0092h Port A, Fast A20/Reset 00A0..00A1h Interrupt Controller 2 00B2h, 00B3h APM Control/Status Ports 00C0..00DFh DMA Controller 2 00E8, 00E9h GPIO Ports 1 and 2 (87307) 00F0h Math Coprocessor Busy Clear 015C, 015Dh 87307 I/O Controller Configuration Registers (Index, Data)

0170..0177h Hard Drive (IDE) Controller 2 01F0..01FFh Hard Drive (IDE) Controller 1

0201..024Fh Audio subsystem control (primary & secondary addresses)

0278..027Bh Parallel Port (LPT2) 02F8..02FFh Serial Port (COM2) 0300-030Fh Network interface controller

0371.. 0375h Diskette Drive Controller Alternate Addresses 0376h IDE Controller Alternate Address 0377h IDE Controller Alternate Address, Diskette Drive Controller Alternate Address

0378..037Fh Parallel Port (LPT1)

0388..038Bh FM synthesizer (alias addresses) 03B0..03DFh Graphics Controller 03E8..03EFh Serial Po rt (COM 3 ) 03F0..03F5h Diskette Drive Controller Primary Addresses 03F6, 03F7h Diskette Drive Controller Primary Addresses, Hard Drive Controller Primary Addresses 03F8..03FFh Serial Port (COM1) 04D0, 04D1h Master, Slave Edge/Level INTR Control Register 0C00, 0C01h PCI IRQ Mapping Index, Data 0C06, 0C07h Reserved - Compaq proprietary use only 0C50, 0C51h System Management Configuration Registers (Index, Data) 0C52h General Purpose Port 0C7Ch Machine ID 0C80, 0C81h Scan Chain High/Low Bytes 0C82h Auto Rev Data 0C83h Machine ID 0CD6h, 0CD7h Power Management Registers 0CF8h PCI Configuration Address (dword access) 0CFCh PCI Configuration Data (byte, word, or dword access) FF00..FF07h IDE Bus Master Register

NOTE: Assume unmarked gaps are reserved/unused.

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Chapter 4 System Support

4.7.2 87307 I/O CONTROLLER CONFIGURATION

The 87307 I/O controller contains various functions such as the keyboard/mouse interfaces, diskette interface, serial interfaces, and parallel interface. While the control of these interfaces uses standard AT-type I/O addressing, the configuration of these functions uses indexed ports unique to the 87307. In this system, hardware strappin g selects I/O addresses 015Ch and 015Dh at reset as the Index/Data ports for accessing the logical devices within t he 87307. The har dware strapping a l so places the 87307 into PnP mother board mode. The in tegr a t ed logical devices are listed as follows:

Table 4-20 lists the PnP standard control registers for the 87307.

Table 4–20.

87307 I/O Controller PnP Stan da rd Control Registers

Table 4-20.

87307 I/O Controller PnP Standard Cont r ol Regis ters

Index Function Reset Value

00h Set RD_DATA Port 00h 01h Serial Isolation 02h Configuration Control 03h Wake (CSN) 00h 04h Resource Data 05h Status 06h Card Select Number (CSN) 00h 07h Logical Device Select:

00h = 8042 Controller (Keyboard I/F) 01h = 8042 Controller (Mouse I/F) 02h = RTC/APC Configuration 03h = Diskette Controller 04h = Parallel Port 05h = UART 2 (Serial Port B / IrDA) 06h = UART 1 (Serial Port A) 07h = GPIO Ports

08h = Power Management 20h Super I/O ID Register (SID) A0h 21h SIO Configuration 1 Register 16h 22h SIO Configuration 1 Register 02h 23h Programmable Chip Select Configuration Index 00h 24h Programmable Chip Select Configuration Data 00h

NOTE:

For a detailed description of registers refer to appropriate National documentation.

00h

The configuration registers are accessed by writing the appropriate logical device’s number to index 07h and writing the desired offset to the index register. The data is then either written to or read from the data register.

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Technical Reference Guide

The 87307 I/O Controller provides 11 general purpose pins that can be individually configured as either inputs or outputs. These pins are mapped as two general purpose ports and utilized as shown bel ow.

GPIO Port 1 Data, I/O Addr. 078h, (87307 I/O Controller),

Bit Function

7 GPIO17 (not used) 6 GPIO16 (config. as input): Hood Lock Detect.

Read 0, no solenoid Read 1, solenoid

5 GPIO15 (config. as output): Hood Alarm Clear.

Write 0 to clear alarm.

4 GPIO14 (config. as input): Hood Removed Detect.

Read 0, cover has been removed Read 1, cover is secure

3..0 GPIO13-10 (config. as input): Bus/Core Ratio (see chapter 3)

GPIO Port 1 Direction/Output Type/PU Cntrl., I/O Addr. 079-07Bh, (87307 I/ O Controller)

GPIO Port 2 Data, I/O Addr. 07Ch, (87307 I/O Controller),

Bit Function

7..4 GPIO27..24 Not Available

3 GPIO23 (config. as input): Ring Detect

Read 0, no ring received Write 1, ring detected

2 GPIO22 (config. as output): NIC I/F Enable/Disable.

Write 0 to enable. Write 1 to disable.

1 GPIO21 (config. as output): SCSI Enable/Disable.

Write 0 for normal operation Write 1 for low power mode

0 GPIO20 (config. as output): Audio Enable/Disable.

Write 0 to enable. Write 1 to disable.

GPIO Port 2 Direction/Output Type/PU Cntrl., I/O Addr. 07D-07Fh, (87307 I/O Controller)

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Chapter 4 System Support

4.8 SYSTEM MANAGEMENT S UPPORT

This section describes the hardware support of functions involving security, safety, identification, and power consumption of the system. System management functions are handled largely by a custom Compaq ASIC. Most functions are controlled through registers (Table 4-21) accessed using the indexed method through I/O ports 0C50h (index) and 0C51h (Data).

Table 4–21.

System Management Control Registers

Table 4-21.

System Management Control Registers

Index Function

00h Identification 02h Temperature Status / Clear 03h Temperature Interrupt / SMI Enable 05h Power On LED Blink Control 12h General Purpose Open Collector (GPOC) Bits 13h Secured GPOC Bits 20h Power Button Control 21h SMI / SCI Source 22h SMI / SCI Mapping 30h REQ/GNT Control 80h Super I/O Security Control 81h Super I/O Index Address Low 82h Super I/O Index Address High 83h Super I/O Index Data 84h Super I/O Data Address Low 85h Super I/O Data Address High 86h Super I/O Write Block 0 87h Super I/O Write Block 1 88h Super I/O Write Block 2 89h Super I/O Write Block 3

The following subsections describe the system management functions. Any BIOS interaction required of these functions is described in Chapter 8, “BIOS” or in the Compaq BIOS Technical Reference G u ide.

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4.8.1 FLASH RO M WRITE PROTECT

The system BIOS firmware is contained in a flash ROM device that can be re-written with updated code if necessary. The ROM is write-protected with a Black Box* security feature. The Black Box feature uses the Administrator password to protect against unauthorized writes to the flash RO M . Du ring th e boot sequen c e , the BIO S ch ec ks for th e pre s e nce of the ROMPAQ diskette. If ROMPAQ is det ected a nd the password is locked into the Bla ck Box with the Protect Resources command, an Access Resources command followed by Administrator password entry must occur before the ROM can be flashed. If the Permanently Lock Resources command has been invoked, the power must be cycled befor e the ROM ca n be flas hed. The system ROM is write-protected as follows:

Technical Reference Guide

Start Addr. End

Addr. Data Type Protection C0000h EFFFFh Opt i on ROM Password write-protected F0000h F7FFFh System BIOS Pa ssword writ e-pr otected F8000h F9FFFh ESCD Never write-protected FA000h FFFFFh Boot Block Always wr ite-protected

The flashing functions are handled usin g the INT15 AX-E822h BIOS interface.

4.8.2 PASSWORD PROTECTION

When en abled, th e user is pr omp t ed to enter t he power-on password du rin g POST. If an incorrect entry is made, the system halts and does not boot. Th e Power-On pass word is store d in eight bytes at configuration memory locations 37h-3Fh. These locations are physically located within the 87307. At the time a new password is written into 37h-3Fh, the password is also written into Black Box* logic. The Black Box logic is used for power-on password protection support instead of the port 92 sequence used on other systems. The Black Box logic prevents inadvertent or un a uthorized access to the password bytes of the 87307 by m onit ori ng I/O ports 70/71h for access to the 37h-3Fh CMOS ran g e and inhibiting th e AEN signal to the 87307 if such access is detected. Slot 1 of the Black Box logic can be written to at runtime, allowing the user to change the power on password without cycling power and going th rough the F10 method. The Black Box password cannot be read.

The power-on password function can be disabled by setting DIP SW1 position 1 to on (closed).

The administrator password is stored in eight bytes at configuration memory locations 78h-7Fh. If the administrator password function is enabled, the user is prompted to enter the password before runn i ng F10-Setup or before booting from a ROMPAQ diskette. If an incorrect entry is made, the system halts and does not boot. The administr ator password i s als o s tor ed in the Bl ack Box* logic. Black Box logic acting as the sentry for the administrator password by preventing inadvertent or unauthorized writing to the Flash ROM.

Black Box logic is Compaq-proprietary and controlled exclusively through the BIOS ROM.

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4.8.3 I/O SECURITY

The 87307 I/O controller allows various I/O functions to be disabled through configuration registers. In addition, the configuration registers of the 87307 are further protected by Client Management (CM) logic (contained within a Compaq ASIC) that can be set (using BIOS call INT 15 AX=E829h) to block access to the 87307 configuration registers of the following functions:

♦ Diskette drive ♦ Serial port ♦ Parallel port

In blocking 87307 functions, the CM logic monitors ISA I/O cycles and can detect, thr ough index address-matching, when an attempt is made to access a function provided by the 87307. If the CM logi c has been set to block access, then ISA bus signal AE N or I OWC- , both which t he CM logic provides to the 87307, is disabled, effectively inhibiting the I/O access.

The USBcontroller can also be blocked from access by the CM logic. In this case the CM logic can be set to block the routing of the REQ/GNT signals to the USB controller, thereby disabling the interface.

4.8.4 USER SECURITY

The QuickLock feature allows, if enabled in F10-Setup through CMOS location 13h bit <2>, the user to lock the keyboard and mouse by invoking the and the SMI handler then takes the action required to lock the keyboard. If the QuickBlank feature is enabled at that time then the screen will be blanked as well. The user then must enter the power-on password to re-activate the keyboard and/or display .

NOTE:

functions are not considered power management features.

Although the SMI is used for initiating QuickLock/QuickBlank functions, these

Ctrl-Alt-L

keystrokes. This initiates an SMI

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4.8.5 TEM PERATURE SENSING

This system employs two sensors for monitoring the temperature inside the chassis. A thermister attached to the heat sink of the Pentium II SEC cartridge is used to detect the caution level. This thermister, connected to the system board through header P15, is part of sensing logic that provides input to a Compaq ASIC. The sensing logic is set to trip when 179.6 °F (82 °C) is reached. At that time the Compaq ASIC can generate an SMI (if so configured, see registers below) resulting in a warning to the user and/or the FAN being turned on.

The Pentium II processor contains a sensor utilized to detect a deadly condition. This sensor will activate when 135 °C is reached. At that time the processor will produce the THERMTRIPsignal. The assertion of THERMPTRIP- is recorded in a Compaq ASIC (see following registers) and also results in turning off the system’s clock generator, effectively shutting down the system.

The following two indexed registers are used by BIOS and available to software for controlling the temperature sense function.

I/O Port C51.02h, Temperature Status/Clear Register

Bit Function

7..2 Res erved 1 Temperature Deadly (RO)

0 = Normal 1 = Critical temperature detected

0 Reserved

NOTE: Bits 1,0 are cleared when read but will be instantly reset if condition remains.

Technical Reference Guide

I/O Port C51.03h, Temperature Interrupt/SMI Enable Register

Bit Function

7..3 Reserved 2 Temperature Deadly Shutdown Disable:

0 = Initiate shutdown w/deadly condition. 1 = Do not initiate shutdown.

1,0 Reserved

4.8.6 COVER LOCK

The chassis cover can be locked to prevent unauthorized personnel from removing the cover and changing the system hardware. The locking mechanism consists of a solenoid controlled by the GPOC regist er of CM logic in t he Compaq ASIC .

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4.8.7 COVER REMO VAL SENSOR

This system includes a cover removal indication function. The system can, upon power-up, notify th e user if the computer cover has been removed. The sensor consists of a plunger switch mounted on the backplane (riser card) that comes in contact with the chassis cover. When the cover is removed, the switch is activated and the battery-backed logic places a high at GPIO port 1bit <4>. This bit will remain set (whether or not the cover is replaced) until the system is powered up and t he user comp letes t he boot s equen ce s u cces s fu lly, a t which time the hood alarm bit <4> will be cleared. Through Setup, the user can set this function to one of three levels of support for a “hood removed” condition:

Level 0 - Hood removal indication is essentially disabled at this level. During POST, Bit <4> is cleared and no other action is taken by BIOS.

Level 1 - During POST the message “Th e comput er’s cover has been removed since the last system start up” is displayed and time stamps in CMOS and SIT are updated.

Level 2 - During POST the “The computer’s cover has been removed since the last system start up” message is displayed, time stamps in CMOS and SIT ar e updated, a nd user is prompted for administrator password.

NOTE:

If the user invokes Setup through F10 the administrator password is not

requested again.

The System Information Table (SIT) record format for the hood removal time stamp is as follows:

System Information Table, System Hood Removal Record (13h)

Byte Bit Function

00h 7-0 Record ID (13h) 01h 7-0 Length of record

02-05h

31-25 24-21 20-16 15-11

06h 7-0 Hood Removal Support Enable/Disable Byte Offset (0-255) 07h

08h 7..0 Hood Removal NOBOOT Enable/Disable Byte Offset (0-255) 09h

Hood Removal Time Stamp: Year (0-99, representing 1996-2095) Month (1-12) Day (1-31) Hours (0-23) Minutes (0-59)

10-5

Seconds (0-59)

4-0

Hood Removal Support Enable/Disable Bit Location: CMOS Type (0011b, use INT 15h for flat model CMOS)

7..4 Bit location (0000b)

3..0

Hood Removal NOBOOT Enable/Disable Bit Location: CMOS Type (0011b, use INT 15h for flat model CMOS)

7..4 Bit location (0001b)

3..0

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4.8.8 POWER MANAGEMENT

This system includes h a rdware support of Advanced Power Management (APM) firmware and software.

4.8.8.1 HARD DRIVE SPINDOWN CONTROL

The timeout parameter stored in the SIT record 04h and indexed through CMOS location 2Ah (bits <4..0>) represents the period of hard drive inactivity r equired to elapse before the hard drive is allowed to spin down. The timeout value is downloaded from CMOS to a timer on the hard drive. The timeout period can be set in incremental values of 0 (timeout disabled), 10, 15 (default), 20, 30, and 60 minutes. A timed-out and spun-down hard drive will automatically spin back up upon the next drive access. It is normal for the user to detect a certain amount of access latency in this situation.

4.8.8.2 MONITOR POWER CONTROL

Technical Reference Guide

The VESA display power management signaling protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals of the monitor i nterface to select a monitor’s power condition. This capability is dependent on the graphics controller employed in the system. For compliance to the monitor power control feature refer to the applicable appendix for the installed graphics controller card.

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Chapter 4 System Support

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Chapter 5 INPUT/OUTPUT INTERFACES

Technical Reference Guide

5.1

5.2

Chapter 5 INPUT/OUTPUT INTERFACES

INTRODUCTION

This chapter describes the system’s interfaces that provide input and output (I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The I/O interfaces are integra ted functions of the support chipset and the 87307 I/O controller. The following I/O interfaces are covered in this chapter:

♦ Enh a nced IDE (EIDE) interface (5.2) page 5-1 ♦ Diskette drive interface (5.3) page 5-9 ♦ Serial interfaces (5.4) page 5-14 ♦ Parallel interface (5.5) page 5-21 ♦ Keyboard/pointin g device interface (5.6) page 5-29 ♦ Eth ernet interface (5.7) page 5-35 ♦ Universal serial bus interface (5.8) page 5-37 ♦ SCSI interface (5.9) page 5-39

ENHANCED IDE INTERFACE

The enhanced IDE (EIDE) interface consists of primary and secondary controllers (integrated into the south bridge component) that can support IDE devices each. Devices that m ay connect to the IDE interface include hard drives, CD-ROM drives, power (writeable CD-ROM) drives, and 120-MB floptical drives.

Two 40-pin keyed IDE data connectors (one for each controller) are provided on the system board. Each connector can support two devices and can be configured independently for PIO modes 1-4, DMA modes 1-2, or Ultra DMA modes 0-2. In standard configur ations with an IDE drive the hard drive is attached to the primary connector and the CD-ROM (if installed) is attached to the secondary connector.

NOTE:

operated in UATA mode 2 off the same controller t he standard 40-conductor cable must be replaced with an 80-conductor cable (available as an option) is required. Running two drives in UATA mode 2 with the standard 40-conductor cable produces CRC errors (due to electrical crosstalk) that will cause the BIOS to switch to UATA mode 1 (25 MB/s).

Both controllers support UATA mode 2 (33 MB/s). If a second drive is to be

5.2.1 IDE PROGRAMMING

The IDE interface is configured as a PCI device and controlled through standard I/O mapped registers.

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Chapter 5 Input/Output Interfaces

5.2.1.1 IDE Configuration Registers

The IDE controller is in tegr a ted into the 82586 component and configured as a PCI device with bus mastering capability. Th e PCI configuration registers for the IDE controller function (PCI device #20, function #1) are listed in Table 5-1.

Table 5–1

. IDE PCI Configuration Registers

EIDE PCI Conf igur ation Registers (82586, Function 1)

PCI Conf. Addr. Register

00-01h Vender ID 8086h 24-3Fh Reserved 02-03h Device ID 7111h 40, 41h IDE Timing (Primary) 04-05h PCI Command 0000h 42, 43h IDE Timing (Secondary) 06-07h PCI Status 0000h 44h Slave IDE Timing 08h Revision ID 0Ah 45-47h Reserved 09h Programming 01h 48h UDMA Timing 0Ah Sub-Class 01h 49h Reserved 0Bh Base Class Code 80h 4A, 4Bh UDMA Timing 0Dh Master Latency Timer 0000h 4C-F7h Reserved 0Eh Header Type 80h F8-FBh Manufacturer’s ID 0F-1Fh Reserved 00h FC-FFh Reserved 20-23h BMIDE Base Address 00h -- -- --

NOTE:

Assume unmarked gaps are reserved and/or not used.

5.2.1.2 IDE Bus Master Con t rol Registers

The IDE interface can perform PCI bus master operations using the I/O mapped control registers listed in Table 5-2.

Table 5–2.

IDE Bus Master C on t rol Register s

Table 5-1.

Value

Reset

PCI Conf.

Addr. Register

Value

Reset

Table 5-2.

IDE Bus Mast er Control Registers

I/O Addr.

Offset

00h 2 Bus Master IDE Command (Primary) 00h 02h 2 Bus Master IDE Status (Primary) 00h 04h 4 Bus Master IDE Descriptor Ptr (Pri.) 0000 0000h

08h 2 Bus Master IDE Command (Secondary) 00h 0Ah 2 Bus Master IDE Status (Secondary) 00h 0Ch 4 Bus Master IDE Descriptor Ptr (Sec.) 0000 0000h

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Default

Value

Compaq Deskpro 4000, Deskpro 6000 Technical Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

NOTICE

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

ABOUT THIS G UIDE

1.2 NOTATIONAL CONVENTIONS

1.3 COMMON ACRONYMS AND ABBREVIATIONS

INTRODUCTION

2.2 FEATURES

2.3 MECHANICAL DESIGN

2.4 SYSTEM ARCHITECTURE

2.5 SPECIFICATIONS

INTRODUCTION

3.2 PENTIUM II-BASED PROCESSOR/MEMORY SUBSYSTEM

INTRODUCTION

4.2 PCI BUS OVERVIEW

4.3 AGP BUS OVERVIEW

4.4 ISA BUS OVERVIEW

4.5 SYSTEM CLOCK DISTRIBUTION

4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY

4.7 I/O MAP AND REGISTER ACCESSING

4.8 SYSTEM MANAGEMENT S UPPORT

INTRODUCTION

ENHANCED IDE INTERFACE