A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
PCB NO :
BOM P/N :
LA-9591P (DAA00005W10)
4319LK31L01
MODEL NAME :
VAUA0
GPIO MAP: 3.0
2 2
Goliad 14"
Haswell ULT
2013-05-17
REV : 1.0 (A00)
@ : Nopop Component
1@ : M/B SPI ROM
3 3
EMC@ : EMI, ESD and RF Component
SPI on M/B TAA
XDP@ : XDP Component
2@ : TAA/B SPI ROM
Vpro
1@/3@/4@/EMC@ 2@/3@/5@/EMC@
CONN@ : Connector Component
3@ : M/B for non support WWAN
non-Vpro
1@/EMC@ 2@/EMC@
4@ : M/B SPI 4M ROM Component
5@ : TAA/B SPI 4M ROM Component
7@ : M/B for Non-Vpro
4 4
MB PCB
MB PCB
Part Number
Part Number
DAA00005W10
DAA00005W10
Description
Description
PCB 0VN LA-9591P REV1 M/B
PCB 0VN LA-9591P REV1 M/B
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-9591P
LA-9591P
LA-9591P
1 58Friday, May 17, 2013
1 58Friday, May 17, 2013
1 58Friday, May 17, 2013
E
0.4
0.4
0.4
A
Goliad 14 Block Diagram
B
C
D
E
Memory BUS (DDR3L)
1 1
Mini-DP
eDP CONN
PAGE 22
DP
PAGE 27
eDP
1333/1600MHz
INTEL
DP
For MB/Dock
Video Switch
DP
IDT VMM2320
VGA
DOCKING
PORT
2 2
PAGE 34
DAI
DOCK_USB3.0[3]
SATA0
DOCK_USB2.0[0]
DOCK_USB2.0[5]
PCIE3 PCIE4
PAGE 21
HDMI CONN
PAGE 23
SD4.0
PAGE 30 PAGE 30
DP
HDMI
Intel Clarkville
I218LM
PAGE 28
3 3
LAN SWITCH
PI3L720
PAGE 28
Transformer
PAGE 35
Smart Card
RFID
RJ45
PAGE 35
4 4
A
PAGE 31 PAGE 31
TDA8034HN
Fingerprint
CONN
Pericom
PI3VDP12412
PAGE 27
Reduce Level
Shifter
PAGE 23
Card reader
O2 Micro OZ777FJ2LN
PCI Express BUS
PCIE6_L0
Full Mini CardWLAN+BT/
WWAN+mSATA
SATA3
USB2.0[6]USB2.0[2]
FP_USB
USH
BCM5882
USB2.0[4]
USH board
PAGE 29
FAN CONN
KB and TP CONN
B
DDI2
HASWELL ULT
DDI1
PCIE5_L0
SPI
Discrete TPM
AT97SC3204
PAGE 37 PAGE 37
PAGE 29
LPC
SMSC KBC
MEC5075
PAGE 38
DOCKED_LIO_EN
NX3DV221
USB20 Switch
PI3USB3102
USB3&2 Switch
SATA Conn60GHz
PAGE 6~17
W25Q64CVSSIQ
64M 4K sector
USB
USB2.0[7]
USB2.0[0]
DOCKED
USB2.0[5]
USB3.0[3]
HD Audio I/F
SATA1
W25Q32BVSSIQ
32M 4K sector
SMSC SIO
PAGE 7
Touch Screen
Conn
Trough eDP Cable
ECE5048
PAGE 36
BC BUS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
DDR3L-DIMM X2
BANK 0, 1, 2, 3
PAGE 33
PAGE 32
PAGE 25
PAGE 22
D
PAGE 18 19
USB2.0[3]
SW_USB2.0[0]
DOCK _USB2.0[0]
SW_USB2.0[5]
SW_USB3.0[3]
USB2.0[1]
USB3.0[1]
HDA Codec
ALC3226
PAGE 26
Trough eDP Cable
Camera
PAGE 22
Trough eDP Cable
SLGC55584A
USB POWER SHARE
USB3.0/2.0
DOCK _USB2.0[5]
DOCK_USB3.0[3]
USB3.0/2.0
PAGE 33
PAGE 33
PAGE 35
USB3.0[2]
IO/B
USB3.0/2.0+PS
PAGE 33
Free Fall sensor
PAGE 25
INT.Speaker
PAGE 26
Near Field
Communications con
Vol bottom SW
Combo Jack
DAI
To Docking side
IO/B
CPU XDP Port
PAGE 40
PAGE 9
Automatic Power
Dig. MIC
PAGE 22
Switch (APS)
WiFi ON/OFF
PAGE 9
PAGE 35
DC/DC Interface
PAGE 39
Power On/Off
SW & LED
PAGE 40
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block diagram
Block diagram
Block diagram
LA-9591P
LA-9591P
LA-9591P
2 58Friday, May 17, 2013
2 58Friday, May 17, 2013
2 58Friday, May 17, 2013
E
PAGE 20
IO/B
0.4
0.4
0.4
5
4
3
2
1
POWER STATES
State
D D
S0 (Full ON) / M0
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCIE
PCIE 1
PCIE 2
PCIE 3
PCIE 4
PCIE 5
PCIE 6 WWAN(PP/mSATA)
USB3.0
USB3.0 1
USB3.0 2
USB3.0 3
SATA
SATA 3
DESTINATION
JUSB3-->IO-->Right
JUSB1-->Rear left
JUSB2-->Rear Right//DOCK
LOM
WLAN (WiGi)
MMI (CARD READER)
C C
PM TABLE
power
plane
+3.3V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
+3.3V_SUS+5V_ALW +5V_RUN
+1.35V_MEM
+0.675V_DDR_VTT
+1.05V_RUN
+VCC_CORE
+3.3V_M +3.3V_M
+1.05V_M+3.3V_RUN
+1.05V_M
(M-OFF)
SATA 2
SATA 0
USB PORT#
State
0
1
S0
B B
S3
S5 S4/AC
S5 S4/AC don't exist
ON
ON
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFFOFF
HSW
ULT
2
3
4
5
JUSB1 // E-Dock 1
IO/ JUSB3
WLAN + BT
CAMERA
USH->SMART CARD
JUSB2 // E-Dock 2
NA
HDDSATA 1
DOCK
DESTINATION
need to update Power Status and
PM Table
6
7
0
WWAN
TOUCH
BIO
USH
A A
1
NA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-9591P
LA-9591P
LA-9591P
3 58Friday, May 17, 2013
3 58Friday, May 17, 2013
3 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
+1.05V_RUN
+3.3V_RUN
A_ON
PWRSHARE_EN#
ESATA_USB_PWR_EN#
TPS51212
(PU300)
G471
(U35)
D D
ADAPTER
EN_INVPWR
FDC654P
(Q2)
DOCKED
TPS22966
+1.05V_M
+5V_USB_
CHG_PWR
G471
(U35)
+USB_PWR
(U31)
+BL_PWR_SRC
MPHYP_PWR_EN
BATTERY +PWR_SRC
C C
+1.05V_RUN_VMM
CHARGER
+3.3V_RUN_VMM
ALWON
TPS51225
(PU100)
SI3456
(Q125) +1.05V_MOD_PHY
+5V_ALW
USB_SIDE_EN#
G471
+3.3V_ALW
RUN_ON
PCH_ALW_ON
AUX_EN_WOWL
MCARD_WWAN_PWREN
TPS22966
(U3)
TPS51622
(PU500)
B B
RT8207
(PU11)
A_ON
TPS22966
(U45)
SUS_ON
SIO_SLP_LAN#
3.3V_HDD_EN
TPS22966
(U22)
EN_LCDPWR
APL3512
(U9)
RUN_ON
RUN_ON
TPS22966
(U46)
RUN_ON
RUN_ON
TPS22966
(U18)
TPS22966
(U43)
(IO/B)
+USB_IO_PWR
+3.3V_ALW_PCH
H_VR_EN
SUS_ON
+VCC_CORE
A A
+1.35V_MEM
+0.675V_DDR_VTT
+5V_RUN
_AUDIO
0.675V_DDR_VTT_ON
+3.3V_M
+3.3V_WLAN
+3.3V_SUS
+3.3V_LAN
+3.3V_mSATA
_WWAN
+LCDVDD
+3.3V_HDD
+3.3V_CAM
+3.3V_RUN
3.3V_CAM_EN#
LP2301ALT1G
(Q3)
+5V_RUN
3.3V_TS_EN
LP2301ALT1G
(Q1)
+5V_TSP
+3.3V_RUN
_AUDIO
+1.05V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-9591P
LA-9591P
LA-9591P
4 58Friday, May 17, 2013
4 58Friday, May 17, 2013
4 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
SMBUS Address [0x9a]
B4
A3
B5
A4
MEM_SMBCLK
MEM_SMBDATA
SML0CLK
SML0DATA
2.2K
2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMDATA
+3.3V_ALW_PCH
AP2
AH1
D D
PCH
AN1
AK1
AU3AH3
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
1K
1K
2.2K
2.2K
4
+3.3V_ALW_PCH
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW
2N7002
2N7002
0ohm
0ohm
0ohm
0ohm
127
129
NFC_SMBCLK
NFC_SMBDATA
DOCKING
LAN_SMBCLK
LAN_SMBDATA
3
28
31
LOM
2
202
200
202
200
53
51
DIMMA
DIMMB
XDP
1
10K
NFC
10K
4
6
30
32
+3.3V_RUN
G Sensor
WWAN
2.2K
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
A50
B53
A49
B52
USH_SMBCLK
USH_SMBDAT
2.2K
2.2K
CARD_SMBCLK
CARD_SMBDAT
1E
B B
1E
MEC 5075
2B
2B
10K
B50
A47
CHARGER_SMBCLK
CHARGER_SMBDAT
1G
1G
10K
2.2K
2.2K
B7
A7
BAY_SMBDAT
BAY_SMBCLK
A A
2D
2D
2.2K
2.2K
B48
B49
GPU_SMBDAT
GPU_SMBCLK
4
2A
2A
5
+3.3V_ALW
100 ohm
100 ohm
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
7
BATTERY
6
CONN
M9
L9
USH
9
8
Charger
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SMbus Block diagram
SMbus Block diagram
SMbus Block diagram
LA-9591P
LA-9591P
LA-9591P
5 58Friday, May 17, 2013
5 58Friday, May 17, 2013
5 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
+RTC_CELL
330K_0402_1%
330K_0402_1%
12
RC1
RC1
D D
PCH_INTVRMEN
330K_0402_1%
330K_0402_1%
12
RC2@
RC2@
+3.3V_ALW_PCH
RC3@ 1K_0402_5%RC3@ 1K_0402_5%
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT)
HIGH = DISABLE
1 2
4
PCH_AZ_SDOUT
3
2
1
CC1
CC1
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
1 2
RC7 1M_0402_5%RC 7 1M_0402_5%
+RTC_CELL
C C
1
1
ME1@SHORT PADS~DME1@SHORT PADS~D
1 2
CC3 1U_0402_6.3V6KCC3 1U_0402_6.3V6K
2
2
CMOS_CLR1
1 2
1 2
RC8 20K_0402_5%RC8 20K_0402_5%
RC6 20K_0402_5%RC6 20K_0402_5%
1
CC4
CC4
CMOS place near DIMM
CMOS setting
1 2
18P_0402_50V8J
18P_0402_50V8J
CC2
CC2
1 2
18P_0402_50V8J
18P_0402_50V8J
1
CMOS1@SHORT PADS~DCM OS1@SHORT PADS~D
1 2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
12
Shunt Clear CMOS
Open
ME_CLR1
Keep CMOS
TPM setting
Shunt Clear ME RTC Registers
Open
B B
+1.05V_M
12
0_0603_5%
@
0_0603_5%
@
RC16
RC16
+1.05V_M_JTAG
RC17 51_0402_1%RC17 51_0402_1%
RC18 51_0402_1%RC18 51_0402_1%
RC20 51_0402_1%RC20 51_0402_1%
RC10@ 1K_0402_1%RC10@ 1K_0402_1%
RC22@ 51_0402_1%RC22@ 51_0402_1%
Keep ME RTC Registers
12
PCH_JTAG_TDI
12
PCH_JTAG_TDO
12
PCH_JTAG_TMS
12
PCH_JTAG_JTAGX
12
PCH_JTAG_TCK
HDA for Codec
1 2
RC4@ 0_0402_5 %RC4@ 0_0402_5%
YC1
YC1
32.768KHZ_12.5PF_Q13FC135000040
32.768KHZ_12.5PF_Q13FC135000040
PCH_RTCRST#<9>
PCH_AZ_CODEC_SDIN0<26>
ME_FWP<36>
RC9 1 K_0402_5%RC9 1 K_0402_5%
PCH_JTAG_TRST#<9>
PCH_JTAG_TCK<9>
PCH_JTAG_TDI<9>
PCH_JTAG_TDO<9>
PCH_JTAG_TMS<9>
PCH_JTAG_JTAGX<9>
PCH_AZ_CODEC_SDOUT<26>
PCH_AZ_CODEC_SYNC<26>
PCH_AZ_CODEC_RST#<26>
PCH_AZ_CODEC_BITCLK<26>
PCH_RTCX1PCH_RTCX1_R
10M_0402_5%
10M_0402_5%
12
RC5
RC5
PCH_RTCX2
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
1 2
PCH_AZ_SDOUT
PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
T3@ PAD~ DT3@ PAD~ D
T4@ PAD~ DT4@ PAD~ D
T5@ PAD~ DT5@ PAD~ D
1 2
RC23 33_0402_5%RC23 33_0402_5%
1 2
RC24 33_0402_5%RC24 33_0402_5%
1 2
RC25 33_0402_5%RC25 33_0402_5%
1 2
EMC@
EMC@
RC26 33_0402_5%
RC26 33_0402_5%
27P_0402_50V8J
27P_0402_50V8J
12
CC5@
CC5@
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER
AV7
INTVRMEN
AV6
SRTCRST
AU7
RTCRST
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN/I2S1_TXD
AV10
HDA_DOCK_RST/I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
PCH_AZ_SDOUT
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_BITCLK
UC1E
UC1E
HASWELL_MCP_E
HASWELL_MCP_E
RTC
RTC
JTAG
JTAG
5 OF 19
5 OF 19
HDD_DET#
mCARD_PCIE_SATA#
SATA_IREF
RSVD
RSVD
SATALED
Rev1p2
Rev1p2
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
A12
L11
K10
C12
U3
MPCIE_RST#
HDD_DET#
SATA_IREF
SATA_COMP
SATA_ACT#
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATAAUDIO
SATAAUDIO
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_RCOMP
SATA_PRX_DKTX_N0_C <34>
SATA_PRX_DKTX_P0_C <34>
SATA_PTX_DKRX_N0_C <34>
SATA_PTX_DKRX_P0_C <34>
SATA_PRX_DTX_N1_C <25>
SATA_PRX_DTX_P1_C <25>
SATA_PTX_DRX_N1_C <25>
SATA_PTX_DRX_P1_C <25>
SATA_PRX_MSATATX_N3 <31>
SATA_PRX_MSATATX_P3 <31>
SATA_PTX_MSATARX_N3 <31>
SATA_PTX_MSATARX_P3 <31>
MPCIE_RST# <12,31>
HDD_DET# <25>
PCH_GPIO36 <12>
MCARD_PCIE_SATA# <36>
RC14@ 0_0402_5%RC14@ 0_0402_5%
12
T1 @PAD~D T1 @PAD~D
T2 @PAD~D T2 @PAD~D
SATA_ACT# <40>
+PCH_ASATA3PLL
SATA Impedance Compensation
SATA_COMP
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
1 2
1 2
1 2
DOCK
SATA HDD
WWAN mSATA
+PCH_ASATA3PLL
RC193.01K_0402_1% RC193.01K_0402_1%
+3.3V_RUN
RC11100K _0402_5% RC11100K _0402_5%
RC1210K_0402_5% RC1210K_0402_5%
A A
Reserve for EMI
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/12)
CPU (1/12)
CPU (1/12)
LA-9591P
LA-9591P
LA-9591P
6 58Friday, May 17, 2013
6 58Friday, May 17, 2013
6 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
HASWELL_MCP_E
UC1G
UC1G
LPC_LAD0<29,36,37>
LPC_LAD1<29,36,37>
LPC_LAD2<29,36,37>
LPC_LAD3<29,36,37>
LPC_LFRAME#<29,36,37>
D D
+3.3V_M
1 2
R1 1K_0402_5%R1 1K_0402_5%
R2 1K_0402_5%R2 1K_0402_5%
SPI_WP#_SEL<36>
C C
SPI_CLK32
33_0402_5%
33_0402_5%
R45@
R45@
1 2
33P_0402_50V8J
33P_0402_50V8J
C85@
C85@
1 2
B B
PCI_CLK_LPC_0
PCI_CLK_LPC_1
PCH_SPI_DO2
1 2
PCH_SPI_DO3
PCH_SPI_CS0#
PCH_SPI_DIN
PCH_SPI_DO2
SPI_WP#_SEL
PCH_SPI_CS1# PCH_SPI_CS1#
PCH_SPI_DIN
PCH_SPI_DO2
SPI_WP#_SEL
1 2
1 2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3
R31@ 0_0402_5%R31@ 0_0402_5%
1 2
1 2
R41@ 33_0402_5%R41@ 33_0402_5%
R61@ 33_0402_5%R61@ 33_0402_5%
1 2
R8@ 0_0402_5%R8@ 0_0402_5%
1 2
R144@ 0_0402_5%R144@ 0_0402_5%
R154@ 33_0402_5%R154@ 33_0402_5%
1 2
1 2
R194@ 33_0402_5%R194@ 33_0402_5%
R23@ 0_0402_5%R23@ 0_0402_5%
SPI_CLK64
33_0402_5%
33_0402_5%
R57@
R57@
33P_0402_50V8J
33P_0402_50V8J
@
@
C76
C76
12
CC15@12P_0402_50V8J CC15@12P_0402_50V8J
12
CC14@12P_0402_50V8J CC14@12P_0402_50V8J
Reserve for EMI
A A
AU14
LAD0
AW12
LAD1
AY12
LAD2
AW11
LAD3
AV12
LFRAME
AA3
SPI_CLK
Y7
SPI_CS0
Y4
SPI_CS1
AC2
SPI_CS2
AA2
SPI_MOSI
AA4
SPI_MISO
Y6
SPI_IO2
AF1
SPI_IO3
SPI_PCH_CS0#_R
SPI_DIN64
12
12
SPI_PCH_DO2_64
SPI_PCH_CS1#_R
SPI_DIN32
SPI_PCH_DO2_32
WWAN (Mini Card 1)--->
HASWELL_MCP_E
LPC
LPC
SPI C-LINK
SPI C-LINK
10/100/1G LAN --->
WLAN (Mini Card 2)--->
MMI --->
4
SMBUS
SMBUS
SML1ALERT/PCHHOT/GPIO73
7 OF 19
7 OF 19
64Mb Flash ROM
U1 1@
U1 1@
1
/CS
2
DO(IO1)
/HOLD(IO3)
3
/WP(IO2)
4
GND
W25Q64FVSSIQ_SO8
W25Q64FVSSIQ_SO8
32Mb Flash ROM
U2 4@
U2 4@
1
/CS
2
DO/IO1
3
4
/HOLD/IO3
/WP/IO2
GND
W25Q32FVSSIQ_SO8
W25Q32FVSSIQ_SO8
SMBALERT/GPIO11
SML0ALERT/GPIO60
SML1DATA/GPIO74
VCC
CLK
DI(IO0)
VCC
CLK
DI/IO0
PCH_TPM_LPC_EN<29>
CLK_PCIE_LAN#<28>
CLK_PCIE_LAN<28>
LANCLK_REQ#<12,28>
CLK_PCIE_MINI2#<31>
CLK_PCIE_MINI2<31>
MINI2CLK_REQ#<12,31>
CLK_PCIE_MMI#<30>
CLK_PCIE_MMI<30>
MMICLK_REQ#<30>
CLK_PCIE_MINI1#<31>
CLK_PCIE_MINI1<31>
MINI1CLK_REQ#<12,31>
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK/GPIO75
CL_CLK
CL_DATA
CL_RST
Rev1p2
Rev1p2
+3.3V_M
8
7
SPI_PCH_DO3_64
6
SPI_CLK64
5
SPI_DO64
+3.3V_M
8
7
SPI_PCH_DO3_32
6
SPI_CLK32
5
SPI_DO32
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
AN2
PCH_SMB_ALERT#
AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
AL2
AN1
SML0CLK
AK1
SML0DATA
AU4
AU3
SML1_SMBCLK
AH3
SML1_SMBDATA
AF2
PCH_CL_CLK1
AD2
PCH_CL_DATA1
AF4
PCH_CL_RST1#
C51@
C51@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
1 2
R51@ 33_0402_5%R51@ 33_0402_5%
R71@ 33_0402_5%R71@ 33_0402_5%
1 2
1 2
R91@ 33_0402_5%R91@ 33_0402_5%
C64@
C64@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
R164@ 33_0402_5%R164@ 33_0402_5%
1 2
1 2
R204@ 33_0402_5%R204@ 33_0402_5%
R214@ 33_0402_5%R214@ 33_0402_5%
1 2
1 2
RC57 10K_0402_5%RC57 10K_0402_5%
1 2
RC56 10K_0402_5%RC56 10K_0402_5%
1 2
RC55 10K_0402_5%RC55 10K_0402_5%
3
PCH_GPIO73 <12>
SML1_SMBCLK <37>
SML1_SMBDATA <37>
PCH_CL_CLK1 <31>
PCH_CL_DATA1 <31>
PCH_CL_RST1# <31>
PCH_SPI_DO3
PCH_SPI_CLK
PCH_SPI_DO
PCH_SPI_DO3
PCH_SPI_CLK
PCH_SPI_DO
C43
C42
PCIECLK_REQ0#
U2
B41
A41
Y5
C41
B42
AD1
B38
C37
N1
A39
B39
U5
B37
A37
T2
PCI_CLK_LPC
SML0CLK
SML0DATA
UC1F
UC1F
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
1 2
RC58 EMC@ 22_0402_5%RC58 EMC@ 22_0402_5%
RC61 EMC@ 22_0402_5%RC61 EMC@ 22_0402_5%
1 2
RC63 EMC@ 22_0402_5%RC63 EMC@ 22_0402_5%
1 2
MEM_SMBCLK
MEM_SMBDATA
RC35@ 0_0402_5%RC35@ 0_0402_5%
RC33@ 0_0402_5%RC33@ 0_0402_5%
RC31@ 0_0402_5%RC31@ 0_0402_5%
RC29@ 0_0402_5%RC29@ 0_0402_5%
12
12
12
12
TAA Config
PCH_SPI_DO
PCH_SPI_DO
PCH_SPI_CLK
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_DIN
PCH_SPI_DIN
HASWELL_MCP_E
HASWELL_MCP_E
CLOCK
CLOCK
SIGNALS
SIGNALS
6 OF 19
6 OF 19
R112@ 33_0402_5%R112@ 33_0402_5%
R125@ 33_0402_5%R125@ 33_0402_5%
R132@ 33_0402_5%R132@ 33_0402_5%
R185@ 33_0402_5%R185@ 33_0402_5%
R102@ 0_0402_5%R102@ 0_0402_5%
R175@ 0_0402_5%R175@ 0_0402_5%
R222@ 33_0402_5%R222@ 33_0402_5%
R415@ 33_0402_5%R415@ 33_0402_5%
CLK_PCI_TPM_TCM <29>
CLK_PCI_5048 <36>
CLK_PCI_MEC <37>
+3.3V_RUN
6
5
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
3 4
QC1B
QC1B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
LAN_SMBCLK <28>
NFC_SMBCLK <20>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
DIFFCLK_BIASREF
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
Rev1p2
Rev1p2
2
2
1
QC1A
QC1A
LAN_SMBDATA <28>
NFC_SMBDATA <20>
TAA_DO64
TAA_DO32
TAA_CLK64
TAA_CLK32
TAA_CS0#_R
TAA_CS1#_R
TAA_DIN64
TAA_DIN32
A25
XTAL24_IN
B25
XTAL24_OUT
K21
M21
C26
CLK_BIASREF
C35
MCP_TESTLOW1
C34
MCP_TESTLOW2
AK8
MCP_TESTLOW3
AL8
MCP_TESTLOW4
AN15
AP15
PCI_CLK_LPC_1
B35
A35
DDR_XDP_WAN_SMBCLK <18,19,25,31,9>
DDR_XDP_WAN_SMBDAT <18,19,25,31,9>
PCH_SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0CLK
SML0DATA
+3.3V_M
JTAA1
JTAA1
2
112
4
334
6
556
8
TAA_DO3_64
778
10
TAA_DO3_32
9910
12
TAA_DO2_64
111112
14
TAA_DO2_32
131314
16
151516
18
171718
20
191920
22
G21G
24
G23G
ACES_50185-02041-001
ACES_50185-02041-001
CONN@
CONN@
1 2
RC40@ 0_0402_5%RC40@ 0_0402_5%
1M_0402_5%
1M_0402_5%
RC44
RC44
1 2
T6 @
T6 @
PAD~D
PAD~D
T7 @
T7 @
PAD~D
PAD~D
1 2
1 2
1 2
+3.3V_ALW_PCH
12
RC2710K_0402_5% RC2710K_0402_5%
12
RC282.2K_0402_5% RC282.2K_0402_5%
12
1 2
1 2
XTAL24_IN_R
RC65 @0_0402_5% RC65 @0_0402_5%
RC64 EMC_3@22_0402_5% RC64 EMC_3@22_0402_5%
RC66 EMC@22_0402_5% RC66 EMC@22_0402_5%
CLK_BIASREF
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
RC302.2K_0402_5% RC302.2K_0402_5%
RC362.2K_0402_5% RC362.2K_0402_5%
RC372.2K_0402_5% RC372.2K_0402_5%
12
RC381K_0402_5% RC381K_0402_5%
12
RC391K_0402_5% RC391K_0402_5%
1 2
R432@ 33_0402_5%R432@ 33_0402_5%
R485@ 33_0402_5%R485@ 33_0402_5%
1 2
1 2
R582@ 33_0402_5%R582@ 33_0402_5%
1 2
R595@ 33_0402_5%R595@ 33_0402_5%
18P_0402_50V8J
3
1
18P_0402_50V8J
4
YC2
YC2
24MHZ_12PF_X3G024000DC1H
24MHZ_12PF_X3G024000DC1H
2
18P_0402_50V8J
18P_0402_50V8J
PCI_CLK_LPCPCI_CLK_LPC_0
CLK_PCI_DOCK <34>
CLK_PCI_LPDEBUG <37>
1 2
1 2
1 2
1 2
1 2
1
CC7
CC7
12
CC6
CC6
12
+PCH_VCCACLKPLL
RC453.01K_0402_1% RC453.01K_0402_1%
RC4610K_0402_5% RC4610K_0402_5%
RC4710K_0402_5% RC4710K_0402_5%
RC5010K_0402_5% RC5010K_0402_5%
RC5210K_0402_5% RC5210K_0402_5%
PCH_SPI_DO3
PCH_SPI_DO3
PCH_SPI_DO2
PCH_SPI_DO2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/12)
CPU (2/12)
CPU (2/12)
LA-9591P
LA-9591P
LA-9591P
1
7 58Friday, May 17, 2013
7 58Friday, May 17, 2013
7 58Friday, May 17, 2013
0.4
0.4
0.4
5
HASWELL_MCP_E
D D
DDR_A_D[0..63]<18>
C C
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
UC1C
UC1C
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
HASWELL_MCP_E
DDR CHANNEL A
DDR CHANNEL A
4
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
3
UC1D
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
UC1D
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
DDR_B_D[0..63]<19>
AU37
M_CLK_DDR#0
AV37
M_CLK_DDR0
AW36
M_CLK_DDR#1
AY36
M_CLK_DDR1
AU43
DDR_CKE0_DIMMA
AW43
DDR_CKE1_DIMMA DDR_CKE2_DIMMB
AY42
AY43
AP33
DDR_CS0_DIMMA#
AR32
DDR_CS1_DIMMA# DDR_CS2_DIMMB#
AP32
AY34
DDR_A_RAS#
AW34
DDR_A_WE#
AU34
DDR_A_CAS#
AU35
DDR_A_BS0
AV35
DDR_A_BS1
AY41
DDR_A_BS2
AU36
DDR_A_MA0
AY37
DDR_A_MA1
AR38
DDR_A_MA2
AP36
DDR_A_MA3
AU39
DDR_A_MA4
AR36
DDR_A_MA5
AV40
DDR_A_MA6
AW39
DDR_A_MA7
AY39
DDR_A_MA8
AU40
DDR_A_MA9
AP35
DDR_A_MA10
AW41
DDR_A_MA11
AU41
DDR_A_MA12
AR35
DDR_A_MA13
AV42
DDR_A_MA14
AU42
DDR_A_MA15
AJ61
DDR_A_DQS#0
AN62
DDR_A_DQS#1
AM58
DDR_A_DQS#2
AM55
DDR_A_DQS#3
AV57
DDR_A_DQS#4
AV53
DDR_A_DQS#5
AL43
DDR_A_DQS#6
AL48
DDR_A_DQS#7
AJ62
DDR_A_DQS0
AN61
DDR_A_DQS1
AN58
DDR_A_DQS2
AN55
DDR_A_DQS3
AW57
DDR_A_DQS4
AW53
DDR_A_DQS5
AL42
DDR_A_DQS6
AL49
DDR_A_DQS7
AP49
AR51
AP51
M_CLK_DDR#0 <18>
M_CLK_DDR0 <18>
M_CLK_DDR#1 <18>
M_CLK_DDR1 <18>
DDR_CKE0_DIMMA < 18>
DDR_CKE1_DIMMA < 18>
DDR_CS0_DIMMA# <18>
DDR_CS1_DIMMA# <18>
DDR_A_RAS# <18>
DDR_A_WE# <18>
DDR_A_CAS# <18>
DDR_A_BS0 <18>
DDR_A_BS1 <18>
DDR_A_BS2 <18>
DDR_A_MA[0..15] <18>
DDR_A_DQS#[0..7] <18>
DDR_A_DQS[0..7] <18>
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
2
HASWELL_MCP_E
HASWELL_MCP_E
DDR CHANNEL B
DDR CHANNEL B
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
DDR_CKE3_DIMMB
DDR_CS3_DIMMB#
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
1
M_CLK_DDR#2 <19>
M_CLK_DDR2 <19>
M_CLK_DDR#3 <19>
M_CLK_DDR3 <19>
DDR_CKE2_DIMMB < 19>
DDR_CKE3_DIMMB < 19>
DDR_CS2_DIMMB# <19 >
DDR_CS3_DIMMB# <19 >
DDR_B_RAS# <19>
DDR_B_WE# <19>
DDR_B_CAS# <19>
DDR_B_BS0 <19>
DDR_B_BS1 <19>
DDR_B_BS2 <19>
DDR_B_MA[0..15] <19>
DDR_B_DQS#[0..7] <19>
DDR_B_DQS[0..7] <19>
Rev1p2
Rev1p2
3 OF 19
3 OF 19
A A
Rev1p2
4 OF 19
4 OF 19
Rev1p2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/12)
CPU (3/12)
CPU (3/12)
LA-9591P
LA-9591P
LA-9591P
1
8 58Friday, May 17, 2013
8 58Friday, May 17, 2013
8 58Friday, May 17, 2013
0.4
0.4
0.4
5
+3.3V_ALW_PCH
D D
C C
B B
A A
+PCH_VCCDSW3_3
+3.3V_RUN
PCH_JTAG_TDI<6>
+1.05V_VCCST
1 2
RC70 10K_0402_5%RC70 10K_040 2_5%
1 2
RC98 10K_0402_5%RC98 10K_040 2_5%
1 2
RC74@ 10K_0402_5%RC74@ 10K_0402_5%
RP12
RP12
4 5
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
1 2
RC136 10K_ 0402_5%RC136 10K_0402 _5%
1 2
RC81@ 8.2K_0402_5%RC81@ 8.2K_0402_5%
PCH_JTAG_TDO<6>
1 2
RC96 0_0402_5%
RC96 0_0402_5%
XDP@
XDP@
PCH_JTAG_TMS<6>
1 2
RC113@ 49.9_0402_1%RC113@ 49.9_0402_1%
1 2
RC114 62_0402_5%RC1 14 62_0402_5%
H_PROCHOT#
1
@
@
CC149
CC149
22P_0402_50V8J
22P_0402_50V8J
2
EMI request add
H_CPUPWRGD
10K_0402_5%
10K_0402_5%
12
RC115
RC115
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC115
ME_SUS_PWR_ACK
SUSACK#
SUS_STAT#/LPCPD#
PCH_BATLOW#
AC_PRESENT
PCH_PCIE_WAKE#
PCH_RSMRST#_R
ME_RESET#
TDI_XDP TDI_XDP_R
RUNPWROK<36,37>
H_CATERR#
H_PROCHOT#
PCH_AUDIO_EN <12>
ME_SUS_PWR_ACK<37>
CC41
XDP@CC41
XDP@
12
0.1U_0402_25V6
0.1U_0402_25V6
1 2
TDO_XDP
RC95 0_0402_5%
RC95 0_0402_5%
XDP@
XDP@
RUNPWROK
1 2
RC103 0_0402_5%
RC103 0_0402_5%
XDP@
XDP@
RUNPWROK
1 2
TMS_XDP
RC101 0_0402_5%
RC101 0_0402_5%
XDP@
XDP@
RUNPWROK
TRST#_XDP
RUNPWROK
PCH_JTAG_TRST#<6>
PCH_JTAG_JTAGX<6>
PLTRST_NFC#< 20>
PLTRST_USH#<29>
PLTRST_MMI#<30>
PLTRST_LAN#<28>
PLTRST_VMM2320#<21>
PCH_RSMRST#_Q<38>
+3.3V_RUN
SYS_PWROK<36>
RESET_OUT#< 15,37>
DDR3 COMPENSATION SIGNALS
12
SM_RCOMP0
RC125200_0402_1% RC125200_0402_1%
12
SM_RCOMP1
RC129121_0402_1% RC129121_0402_1%
12
SM_RCOMP2
RC133100_0402_1% RC133100_0402_1%
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
5
XDP_DBRESET#
RC76@ 8.2K_0402_5 %RC76@ 8.2K_0402_5 %
SUSACK#<36>
UC6
UC6
XDP@
XDP@
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
74CBTLV3126BQ_DHVQFN14_2P5X3
reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0
PCH_JTAG_TDO
PCH_JTAG_TCK
H_PROCHOT#<37,46,47,48>
DDR3_DRAMRST#_CPU<18>
H_CPUPWRGD
12
@
@
CC90
CC90
100P_0402_50V8J
100P_0402_50V8J
ESD request add
4
RC72@ 0_0402_5%RC72@ 0_0402_5%
12
ME_RESET#
1 2
RC86@ 0_0402_5%RC86@ 0_0402_5%
1 2
RC87@ 0_0402_5%RC87@ 0_0402_5%
1 2
RC88@ 0_0402_5%RC88@ 0_0402_5%
1 2
RC139@ 0_0402_5%RC139@ 0_0402_5%
1 2
RC89@ 0_0402_5%RC89@ 0_0402_5%
1 2
RC90@ 0_0402_5%RC90@ 0_0402_5%
1 2
RC91@ 0_0402_5%RC91@ 0_0402_5%
1 2
RC92@ 0_0402_5%RC92@ 0_0402_5%
1 2
RC93@ 0_0402_5%RC93@ 0_0402_5%
1 2
RC94@ 0_0402_5%RC94@ 0_0402_5%
SIO_PWRBTN#<37, 9>
AC_PRESENT<37>
SIO_SLP_S0#<37>
SIO_SLP_WLAN#<36>
1B
2B
3B
4B
GND
GND PAD
12
CPU_XDP_TRST#
RC135@ 0_0402_5% RC135@ 0_0402_5%
12
CPU_XDP_TCLK
RC97@ 0_0402_5% RC97@0_0402_ 5%
12
TDO_XDP
RC123 @0_0402_5% RC123 @0_0402_5%
12
TDI_XDP_R
RC104 @0_0402_5% RC104 @0_0402_5%
12
CPU_XDP_TCLK
RC124 @0_0402_5% RC124 @0_0402_5%
CPU_DETECT#<36>
PECI_EC<37>
1 2
RC117 56_0402_5%RC1 17 56_0402_5%
DDR_PG_CTRL<18>
H_PROCHOT#_R
4
1 2
+3.3V_RUN
1
B
2
A
3
CPU_XDP_TDO
6
CPU_XDP_TDI
8
CPU_XDP_TMS
11
CPU_XDP_TRST#
7
15
CPU_DETECT#
H_CATERR#
PECI_EC
H_CPUPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CC8@
CC8@
1 2
5
0.1U_0402_25V6
0.1U_0402_25V6
P
4
O
G
UC2@
UC2@
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
3
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK
PM_APWROK_R
PCH_PLTRST#
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
SIO_PWRBTN#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#
SIO_SLP_WLAN#
D61
PROC_DETECT
K61
CATERR
N62
PECI
K63
PROCHOT
C61
PROCPWRGD
AU60
SM_RCOMP0
AV60
SM_RCOMP1
AU61
SM_RCOMP2
AV15
SM_DRAMRST
AV61
SM_PG_CNTL1
SYS_RESET#
AK2
SUSACK
AC3
SYS_RESET
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST
AW6
RSMRST
AV4
SUSWARN/SUSPWRDNACK/GPIO30
AL7
PWRBTN
AJ8
ACPRESENT/GPIO31
AN4
BATLOW/GPIO72
AF3
SLP_S0
AM5
SLP_WLAN/GPIO29
UC1B
UC1B
PCH_DPWROK
ME_SUS_PWR_ACK_R
RESET_OUT#
UC1H
UC1H
HASWELL_MCP_E
HASWELL_MCP_E
MISC
MISC
THERMAL
THERMAL
PWR
PWR
DDR3
DDR3
3
1
PCH_PLTRST#
2
1 2
RC79 0_0402_5%@ RC79 0_0402_5%@
RC82 0_0402_5%@ RC82 0_0402_5%@
RC84@ 0_0402_5%RC84@ 0_0402_5%
H_VCCST_PWRGD<15>
DDR_XDP_WAN_SMBDAT<18,19,25,31,7>
DDR_XDP_WAN_SMBCLK<18,19,25,31,7>
2 OF 19
2 OF 19
PCH_RSMRST#_R
1 2
SUSACK#_R
1 2
SYS_PWROK_R
HASWELL_MCP_E
HASWELL_MCP_E
SYSTEM POWER MANAGEMENT
SYSTEM POWER MANAGEMENT
8 OF 19
8 OF 19
RC105 1K_0 402_5%
RC105 1K_0 402_5%
XDP@
XDP@
H_CPUPWRGD
SIO_PWRBTN#<37, 9>
CPU_PWR_DEBUG#<15>
SYS_PWROK
PCH_JTAG_TCK<6>
JTAG
JTAG
3
2
+3.3V_RUN
CC9@
CC9@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
5
P
B
4
O
A
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
+1.05V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
CC10
CC10
Place near JXDP1
RC5 need to close to JCPU1
1 2
RC106@ 1K_0 402_5%RC106@ 1K_0402_5%
RC107@ 0_0402 _5%RC107@ 0_0402_5%
RC108@ 0_0402 _5%RC108@ 0_0402_5%
RC110@ 0_0402 _5%RC110@ 0_0402_5%
RC111@ 0_0402 _5%RC111@ 0_0402_5%
RC112@ 0_0402 _5%RC112@ 0_0402_5%
RC142@ 0_0402 _5%RC142@ 0_0402_5%
PCH_PLTRST#_EC
UC3
UC3
DSWVRMEN
DPWROK
SLP_S4
SLP_S3
SLP_SUS
SLP_LAN
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
CC11
CC11
1 2
1 2
1 2
1 2
1 2
1 2
1 2
WAKE
SLP_A
Rev1p2
Rev1p2
AW7
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7
PCH_PLTRST#_EC <29,3 1,36,37>
SIO_SLP_A#
PM_APWROK
PM_APWROK<37>
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
SIO_SLP_LAN#
CPU_XDP_PREQ#
CPU_XDP_PRDY#
CFG0
CFG0<13>
CFG1
CFG1<13>
CFG2
CFG2<13>
CFG3
CFG3<13>
XDP_OBS0_R
XDP_OBS1_R
CFG4
CFG4<13>
CFG5
CFG5<13>
CFG6
CFG6<13>
CFG7
CFG7<13>
H_VCCST_PWRGD_XDP
CFD_PWRBTN#_XDP
CPU_PWR_DEBUG#_R
SYS_PWROK_XDP
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
PCH_JTAG_TCK_R
CPU_XDP_TCLK
PCH_DPWROK <36>
PCH_PCIE_WAKE# <37>
CLKRUN# < 12,29,36,37>
T10 @P AD~DT10 @PAD~D
SIO_SLP_S5# <37>
T11 @PAD~DT11 @PAD~D
T12@PAD~DT12@PAD~D
SIO_SLP_S4# <36,39,43>
SIO_SLP_S3# <36,39,43>
SIO_SLP_A# <36,39,44>
SIO_SLP_SUS# <36>
SIO_SLP_LAN# <28,36>
+1.05V_RUN
+3.3V_ALW_PCH
1K_0402_5%
1K_0402_5%
1
2
RC144@ 0_0402 _5%RC144@ 0_0402_5%
JXDP1
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
OBSDATA_A09OBSDATA_C0
OBSDATA_A111OBSDATA_C1
13
GND4
OBSDATA_A215OBSDATA_C2
OBSDATA_A317OBSDATA_C3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
OBSDATA_B027OBSDATA_D0
OBSDATA_B129OBSDATA_D1
31
GND10
OBSDATA_B233OBSDATA_D2
OBSDATA_B335OBSDATA_D3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
VCC_OBS_AB43VCC_OBS_CD
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
RC102
XDP@
RC102
XDP@
1 2
SYS_PWROK_XDP
0.1U_0402_25V6
0.1U_0402_25V6
12
CC48@
CC48@
J62
CPU_XDP_PRDY#
PRDY
K62
CPU_XDP_PREQ#
PREQ
E60
CPU_XDP_TCLK
PROC_TCK
E61
PROC_TMS
PROC_TRST
PROC_TDO
CPU_XDP_TMS
E59
CPU_XDP_TRST#
F63
CPU_XDP_TDI
PROC_TDI
F62
CPU_XDP_TDO
J60
XDP_OBS0_R
BPM#0
H60
XDP_OBS1_R
BPM#1
H61
XDP_OBS2_R
BPM#2
H62
XDP_OBS3_R
BPM#3
K59
XDP_OBS4_R
BPM#4
H63
XDP_OBS5_R
BPM#5
K60
XDP_OBS6_R
BPM#6
J61
XDP_OBS7_R
BPM#7
Rev1p2
Rev1p2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Place near JXDP1.47
T122 @PAD~D T122 @PAD~D
T126 @PAD~D T126 @PAD~D
T129 @PAD~D T129 @PAD~D
T130 @PAD~D T130 @PAD~D
T131 @PAD~D T131 @PAD~D
T132 @PAD~D T132 @PAD~D
2
+3.3V_ALW2
0.1U_0402_25V6
0.1U_0402_25V6
5
P
B
O
A
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
1 2
CC82@
CC82@
1 2
4
PM_APWROK_R
UC7
UC7
OBSFN_C0
OBSFN_C1
OBSFN_D0
OBSFN_D1
ITPCLK#/HOOK5
RESET#/HOOK6
DBR#/HOOK7
Place near JXDP1.48
XDP_DBRESET#
1
+RTC_CELL
330K_0402_1%
330K_0402_1%
RC73
RC73
1 2
DSWODVREN
330K_0402_1%
330K_0402_1%
RC78@
RC78@
1 2
DSWODVREN - ON DIE DSW VR ENABLE
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
JAPS1
JAPS1
PCH_PLTRST#_EC
+1.05V_RUN
12
RC280@51_0402_1% RC280@51_0402_1%
12
RC116
RC116
12
RC118@
RC118@
12
RC119@
RC119@
12
RC120@
RC120@
12
RC122
RC122
12
RC127
RC127
12
RC131
@
RC131
@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
CONN@
CONN@
ACES_50506-01841-P01
ACES_50506-01841-P01
+3.3V_RUN
+1.05V_RUN
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
+PCH_VCCDSW3_3
PCH_RTCRST#< 6>
POWER_SW#_M B<37,40>
+1.05V_RUN
2
GND1
4
CFG17
6
CFG16
8
GND3
10
CFG8
12
CFG9
14
GND5
16
CFG10
18
CFG11
20
GND7
22
CFG19
24
CFG18
26
GND9
28
CFG12
30
CFG13
32
GND11
34
CFG14
36
CFG15
38
GND13
40
42
44
46
XDP_RST#_R
48
XDP_DBRESET#
50
GND15
52
TDO_XDP
TD0
54
TRST#
TMS
GND17
CONN@SAMTE_BSH-030-01-L-D-A
CONN@SAMTE_BSH-030-01-L-D-A
TRST#_XDP
56
TDI_XDP
TDI
58
TMS_XDP
60
0.1U_0402_25V6
0.1U_0402_25V6
12
CC68
XDP@CC68
XDP@
RC99 1K_0402_5%
RC99 1K_0402_5%
XDP@
XDP@
CFG17 <13>
CFG16 <13>
CFG8 < 13>
CFG9 < 13>
CFG10 <13>
CFG11 <13>
CFG19 <13>
CFG18 <13>
CFG12 <13>
CFG13 <13>
CFG14 <13>
CFG15 <13>
RC109 1K_0402_5%
RC109 1K_0402_5%
XDP@
XDP@
1 2
TDO_XDP
XDP_DBRESET#
1K_0402_5%
1K_0402_5%
CPU_XDP_TMS
51_0402_1%
51_0402_1%
CPU_XDP_TDI
51_0402_1%
51_0402_1%
CPU_XDP_PREQ#
51_0402_1%
51_0402_1%
CPU_XDP_TDO
51_0402_1%
51_0402_1%
CPU_XDP_TCLK
51_0402_1%
51_0402_1%
CPU_XDP_TRST#
51_0402_1%
51_0402_1%
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
12
CFG3CFG3_R
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (4/12)
CPU (4/12)
CPU (4/12)
LA-9591P
LA-9591P
LA-9591P
1
9 58Friday, May 17, 2013
9 58Friday, May 17, 2013
9 58Friday, May 17, 2013
0.4
0.4
0.4
5
D D
4
HASWELL_MCP_E
UC1A
UC1A
HASWELL_MCP_E
3
2
1
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
Rev1p2
Rev1p2
DDPB_HPD
DDPC_HPD
EDP_HPD
Rev1p2
Rev1p2
C45
EDP_CPU_LANE_N0
B46
EDP_CPU_LANE_P0
A47
EDP_CPU_LANE_N1
B47
EDP_CPU_LANE_P1
C47
C46
A49
B49
A45
EDP_CPU_AUX#
B45
EDP_CPU_AUX
D20
EDP_COMP
A43
B9
CPU_DPB_CTRLCLK
C9
CPU_DPB_CTRLDAT
D9
CPU_DPC_CTRLCLK
D11
CPU_DPC_CTRLDAT
C5
CPU_DPB_AUX#
B6
CPU_DPC_AUX#
B5
CPU_DPB_AUX
A6
CPU_DPC_AUX
C8
DPB_HPD
A8
DPC_HPD
D6
EDP_CPU_LANE_N0 <22>
EDP_CPU_LANE_P0 <22>
EDP_CPU_LANE_N1 <22>
EDP_CPU_LANE_P1 <22>
EDP_CPU_AUX# <22>
EDP_CPU_AUX <22>
CPU_DPB_CTRLCLK <23>
CPU_DPB_CTRLDAT <23>
CPU_DPC_CTRLCLK <27>
CPU_DPC_CTRLDAT <27>
CPU_DPC_AUX# <27>
CPU_DPC_AUX <27>
DPB_HPD <23>
DPC_HPD <27>
RC158
RC158
EDP_CPU_HPD <22>
100K_0402_5%
100K_0402_5%
12
COMPENSATION PU FOR eDP
+VCCIOA_OUT
RP3
RP3
1
2
3
4 5
8
7
6
12
12
12
12
12
12
RC13424.9_0402_1% RC 13424.9_0402_1%
+3.3V_RUN
RC147100K_040 2_5% RC147100K _0402_5%
RC149100K_040 2_5% RC149100K _0402_5%
RC151100K_0402_5% RC151100K_0402_5%
RC153100K_0402_5% RC153100K_0402_5%
RC155100K_0402_5% RC155100K_0402_5%
EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
CPU_DPB_AUX#
CPU_DPC_AUX#
DPC_HPD
CPU_DPB_AUX
CPU_DPC_AUX
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
AD4
C54
C55
B58
C58
B55
A55
A57
B57
C51
C50
C53
B54
C49
B50
A53
B53
B8
A9
C6
U6
P4
N4
N2
U7
L1
L3
R5
L4
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
UC1I
UC1I
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDI EDP
DDI EDP
1 OF 19
1 OF 19
HASWELL_MCP_E
HASWELL_MCP_E
eDP SIDEBAND
eDP SIDEBAND
GPIO
GPIO
9 OF 19
9 OF 19
DISPLAY
DISPLAY
EDP_RCOMP
EDP_DISP_UTIL
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
EDP_BIA_PWM<22>
PANEL_BKLEN<22>
ENVDD_PCH<22,36>
T13@ PA D~DT13@ PAD~D
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
DDI2_LANE_N0
DDI2_LANE_P0
DDI2_LANE_N1
DDI2_LANE_P1
DDI2_LANE_N2
DDI2_LANE_P2
DDI2_LANE_N3
DDI2_LANE_P3
EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
DGPU_PWROK
PIRQC#
PIRQD#
TOUCHPAD_INTR#
CODEC_IRQ
DDI1_LANE_N0<23>
DDI1_LANE_P0<23>
DDI1_LANE_N1<23>
DDI1_LANE_P1<23>
DDI1_LANE_N2<23>
DDI1_LANE_P2<23>
DDI1_LANE_N3<23>
DDI1_LANE_P3<23>
DDI2_LANE_N0<27>
DDI2_LANE_P0<27>
DDI2_LANE_N1<27>
+3.3V_RUN
C C
HDD_FALL_INT<25>
B B
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R495@ 0_0402_5%R495@ 0_0402_5%
1 2
R494 0_0402_5%R494 0_0402_5%
CONTACTLESS_DET#
DGPU_PWROK
TOUCHPAD_INTR#
PIRQC#
PIRQD#
ENVDD_PCH
12
CODEC_IRQ
PIRQC#
PIRQD#
RC137 10K_0402_5%RC137 10K_0402_5%
RC138 10K_0402_5%RC138 10K_0402_5%
RC140 10K_0402_5%RC140 10K_0402_5%
RC146 10K_0402_5%RC146 10K_0402_5%
RC148 10K_0402_5%RC148 10K_0402_5%
RC152@ 100K_0402_5%RC152@ 100K_0402_5%
RC154@ 1K_0402_5%RC154@ 1K_0402_5%
DDI2_LANE_P1<27>
DDI2_LANE_N2<27>
DDI2_LANE_P2<27>
DDI2_LANE_N3<27>
DDI2_LANE_P3<27>
CONTACTLESS_DET#<29>
TOUCH_RST_N_GYRO_INT1<12>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/12)
CPU (5/12)
CPU (5/12)
LA-9591P
LA-9591P
LA-9591P
10 58Friday, May 17, 2013
10 58Friday, May 17, 2013
10 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
D D
PCIE_PRX_MMITX_N5<30>
MMI -->
C C
10/100/1G LAN --->
WLAN (Mini Card 2)--->
PCIE_PRX_MMITX_P5<30>
PCIE_PTX_MMIRX_N5<30>
PCIE_PTX_MMIRX_P5<30>
PCIE_PRX_GLANTX_N3<28>
PCIE_PRX_GLANTX_P3<28>
PCIE_PTX_GLANRX_N3<28>
PCIE_PTX_GLANRX_P3<28>
PCIE_PRX_WLANTX_N 4<31>
PCIE_PRX_WLANTX_P4<31>
PCIE_PTX_WLANRX_N 4<31>
PCIE_PTX_WLANRX_P4<31>
Ext USB Port 2 <----
B B
1 2
+PCH_AUSB3PLL
RC161 3.01K_0402_1%RC161 3.01K_0402_1%
1 2
RC163@ 0_0402_5%RC163@ 0_0402_5%
T16@ PAD~DT16@ PAD~D
T17@ PAD~DT17@ PAD~D
4
PCIE_PRX_MMITX_N5
PCIE_PRX_MMITX_P5
PCIE_PTX_MMIRX_N5
PCIE_PTX_MMIRX_P5
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
PCIE_PRX_WLANTX_N 4
PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N 4
PCIE_PTX_WLANRX_P4
USB3RN3<32 >
USB3RP3<32>
USB3TN3<32>
USB3TP3<32>
PCH_PCIE_RCOMP
PCH_PCIE_IREF
F10
E10
C23
C22
F8
E8
B23
A23
H10
G10
B21
C21
E6
F6
B22
A21
G11
F11
C29
B30
F13
G13
B29
A29
G17
F17
C30
C31
F15
G15
B31
A31
E15
E13
A27
B27
UC1K
UC1K
PERN5_L0
PERP5_L0
PETN5_L0
PETP5_L0
PERN5_L1
PERP5_L1
PETN5_L1
PETP5_L1
PERN5_L2
PERP5_L2
PETN5_L2
PETP5_L2
PERN5_L3
PERP5_L3
PETN5_L3
PETP5_L3
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
HASWELL_MCP_E
HASWELL_MCP_E
PCIe USB
PCIe USB
11 OF 19
11 OF 19
3
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USBRBIAS
RSVD
RSVD
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
Rev1p2
Rev1p2
AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USBP0ÂUSBP0+
USBP1ÂUSBP1+
USBP2ÂUSBP2+
USBP3ÂUSBP3+
USBP4ÂUSBP4+
USBP5ÂUSBP5+
USBP6ÂUSBP6+
USBP7ÂUSBP7+
USBRBIAS
USB_OC1#
USB_OC2#
USB_OC3#
USBP0- <33>
USBP0+ <33>
USBP1- <35>
USBP1+ <35>
USBP2- <31>
USBP2+ <31>
USBP3- <22>
USBP3+ <22>
USBP4- <29>
USBP4+ <29>
USBP5- <32>
USBP5+ <32>
USBP6- <31>
USBP6+ <31>
USBP7- <22>
USBP7+ <22>
USB3RN1 <35>
USB3RP1 <35>
USB3TN1 <35>
USB3TP1 <35>
USB3RN2 <33>
USB3RP2 <33>
USB3TN2 <33>
USB3TP2 <33>
T14@PAD~D T14@PAD~D
T15@PAD~D T15@PAD~D
USB_OC0# <33>
USB_OC1# <35>
USB_OC2# <12,33>
2
-----> Ext Port 1 and DOCK2 (USB SW)
----->Ext Port 2 IO/B
----->WLAN/BT
----->Camera
----->USH
----->Ext Port 3 and DOCK1(USB SW)
----->WWAN
----->Touch
----->Ext USB3 Port 3 IO/B
----->Ext USB3 Port 1
USBRBIASUSB_OC0#
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
mils.
USB_OC0#
USB_OC1#
USB_OC3#
1 2
1 2
1 2
22.6_0402_1%
22.6_0402_1%
12
RC159
RC159
RC16010K_0402_5% RC 16010K_0402_5%
RC16510K_0402_5% RC 16510K_0402_5%
RC16610K_0402_5% RC 16610K_0402_5%
1
+3.3V_ALW_PCH
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (6/12)
CPU (6/12)
CPU (6/12)
LA-9591P
LA-9591P
LA-9591P
11 58Friday, May 17, 2013
11 58Friday, May 17, 2013
11 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
+PCH_VCCDSW3_3
D D
RC206 10K_0402_5%RC 206 10K_0402_5%
+3.3V_RUN
RC170 100K_0402_5%RC170 100K_0402_5%
RC199 100K_0402_5%RC199 100K_0402_5%
+PCH_VCCDSW3_3
RC197 10K_0402_5%RC197 10K_0402_5%
+3.3V_ALW_PCH
C C
B B
RC175 10K_0402_5%RC175 10K_0402_5%
RC200 10K_0402_5%RC200 10K_0402_5%
RC171 10K_0402_5%RC171 10K_0402_5%
RC230 10K_0402_5%RC230 10K_0402_5%
RC211 100K_0402_5%RC211 100K_0402_5%
RC210 100K_0402_5%RC210 100K_0402_5%
@
@
RC169
1 2
RP13
RP13
4 5
3
2
1
10K_8P4R_5%
10K_8P4R_5%
RP14
RP14
4 5
3
2
1
10K_8P4R_5%
10K_8P4R_5%
12
EC_WAKE#
12
MPHYP_PWR_EN
12
SIO_EXT_SCI#
12
PM_LANPHY_ENABLE
12
MEDIACARD_PWR EN
12
PCH_GPIO44
12
MEDIACARD_RST#
PCH_GPIO46
SIO_EXT_SMI#
6
SLATE_MODE_R
7
MEDIACARD_IRQ#
8
PCH_GPIO9
6
SIO_EXT_WAKE#
7
KB_DET#
8
12
3.3V_CAM_EN#
12
NFC_IRQ
12
MPHYP_PWR_EN
10K_0402_5%RC169
10K_0402_5%
1 2
RC177 @0_0402_5% RC177 @0_0402_5%
USB_OC2# <11,33>
PCH_GPIO73 <7>
LAN_WAKE# <28,37>
PM_LANPHY_ENABLE<28>
PCH_NFC_RST<20>
NFC_IRQ<20>
MEDIACARD_RST#<30>
MEDIACARD_PWR EN<30>
MEDIACARD_IRQ#<30>
TOUCH_PANEL_INTR#<22>
KB_DET#<38>
+3.3V_RUN +3.3V_RUN
1K_0402_5%
1K_0402_5%
12
RC283@
RC283@
PCH_GPIO66
1K_0402_5%
1K_0402_5%
12
RC288@
RC288@
PCH_AUDIO_EN<9>
SIO_EXT_WAKE#<36>
LAN_RST#<28>
T139@ PAD~DT139@ PAD~D
EC_WAKE#<37>
NFC_DET#<20>
T140@ PAD~DT140@ PAD~D
T141@ PAD~DT141@ PAD~D
MPHYP_PWR_EN<39>
T138@ PAD~DT138@ PAD~D
3.3V_CAM_EN#<22>
SIO_EXT_SMI#<37>
T137@ PAD~DT137@ PAD~D
mSATA_DEVSLP<31>
HDD_DEVSLP<25>
SIO_EXT_SCI#<37>
SPKR<26>
4
PCH_AUDIO_EN
SIO_EXT_WAKE#
PCH_GPIO15
PCH_GPIO17
EC_WAKE#
NFC_IRQ
MEDIACARD_RST#
SLATE_MODE_R
PCH_GPIO44
PCH_GPIO48
PCH_GPIO49
MPHYP_PWR_EN
KB_DET#
PCH_GPIO14
3.3V_CAM_EN#
SIO_EXT_SMI#
PCH_GPIO46
PCH_GPIO9
PCH_GPIO10
SIO_EXT_SCI#
SPKR
10K_0402_5%
10K_0402_5%
12
1K_0402_5%
1K_0402_5%
12
@
@
RC218
RC218
RC287@
RC287@
BBS_BIT
AM7
AM4
AM3
AM2
AU2
AD6
AD5
AN5
AD7
AN3
AG6
AP1
AL4
AT5
AK4
AB6
AT3
AH4
AG5
AG3
P1
Y1
T3
U4
Y3
P3
Y2
P2
C4
L2
N5
V2
UC1J
UC1J
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
GPIO
GPIO
+3.3V_ALW_PCH
3
HASWELL_MCP_E
HASWELL_MCP_E
D60
THERMTRIP
RCIN/GPIO82
CPU/
CPU/
MISC
MISC
LPIO
LPIO
10 OF 19
10 OF 19
I2C1_SDA_TCH_PAD
I2C1_SCL_TCH_PAD I2C1_SCL_TCH_PAD
1K_0402_5%
1K_0402_5%
12
RC190
RC190
PCH_GPIO15
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
Rev1p2
Rev1p2
RC174@ 0_0402_5%RC174@ 0_0402_5%
RC176@ 0_0402_5%RC176@ 0_0402_5%
+3.3V_RUN
H_THERMTRIP#_R
V4
SIO_RCIN#
T4
IRQ_SERIRQ
AW15
PCH_OPI_COMP
AF20
AB21
R6
PCH_GPIO83
L6
PCH_GPIO84
N6
PCH_GPIO85
L8
BBS_BIT
R7
PCH_GPIO87
L5
3.3V_TP_EN
N7
K2
J1
CPPE#
K3
CPUSB#
J2
G1
K4
G2
FFS_INT2
J3
LCD_CBL_DET#
J4
F2
I2C0_SDA
F3
I2C0_SCL
G4
I2C1_SDA_TCH_PAD
F1
I2C1_SCL_TCH_PAD
E3
USH_DET#
F4
CAM_MIC_CBL_DET#
D3
PCH_GPIO66
E4
TPM_ID0
C3
TPM_ID1
E2
SLP_ME_CSW_DEV #
12
12
I2C1_SCL_TCH_PAD <38>
1K_0402_5%
1K_0402_5%
12
RC222@
RC222@
I2C1_SDA_VMM <21>
I2C1_SCL_VMM <21>
I2C1_SDA_TCH_PAD <38>
SPKR
2
SIO_RCIN# <37>
IRQ_SERIRQ <29,36,37>
T18@ PA D~DT18@ PAD~D
T19@ PA D~DT19@ PAD~D
3.3V_TS_EN <22>
3.3V_HDD_EN <28>
CPPE# <31>
CPUSB# <31>
FFS_INT2 <25>
LCD_CBL_DET# <22>
USH_DET# <29>
CAM_MIC_CBL_DET# <22>
SLP_ME_CSW_DEV # <36>
12
12
ESD request add
RC172@ 0_0402_5% RC172@ 0_0402_5%
H_THERMTRIP#_R
@
@
CC91
CC91
100P_0402_50V8J
100P_0402_50V8J
H_THERMTRIP# <37>
TOUCH_RST_N_GYRO_INT1<10>
LANCLK_REQ#<28,7>
MINI1CLK_REQ#<31,7>
MINI2CLK_REQ#<31,7>
MPCIE_RST#<31,6>
CLKRUN#<29,36,37,9>
PCH_GPIO36<6>
H_THERMTRIP#
CAM_MIC_CBL_DET#
SLP_ME_CSW_DEV #
PCH_GPIO85
3.3V_TP_EN
TOUCH_PANEL_INTR#
3.3V_HDD_EN
LCD_CBL_DET#
CPUSB#
SIO_RCIN#
I2C0_SDA
I2C0_SCL
I2C1_SDA_TCH_PAD
IRQ_SERIRQ
PCH_GPIO87
FFS_INT2
USH_DET#
CPPE#
TPM_ID0
TPM_ID1
PCH_GPIO83
PCH_GPIO84
3.3V_TS_EN
PCH_OPI_COMP
PCH_GPIO83
1
12
12
12
12
12
12
12
12
12
12
12
RP4
RP4
45
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
RP5
RP5
45
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
RP6
RP6
45
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
RP7
RP7
1
8
2
7
3
6
4 5
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
RP11
RP11
45
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
1 2
1 2
7@
7@
+1.05V_VCCST
R241K_0402_5% R241K_0402_5%
+3.3V_RUN
RC183100K_0402_5% RC183100K_0402_5%
RC28210K_0402 _5% RC28210K_ 0402_5%
RC185100K _0402_5% RC185100K_0402_5%
RC19310K_0402 _5% RC19310K_ 0402_5%
RC28410K_0402 _5% RC28410K_ 0402_5%
RC28520K_0402_5% RC28520K_0402_5%
RC28910K_0402 _5% RC28910K_ 0402_5%
RC29010K_0402 _5% RC29010K_ 0402_5%
RC29110K_0402 _5% RC29110K_ 0402_5%
RC29410K_0402 _5% RC29410K_ 0402_5%
RC16849.9_0402 _1% RC16849.9_0402_1%
RC292100_0402_5%
RC292100_0402_5%
HIGH depop RC288 HIGH
LOW pop RC288 (DEFAULT)
A A
LOW(DEFAULT)
LPC
SPI
BOOT BIOS STRAP BIT BBS
TLS CONFIDENTIALITYTOP-BLOCK SWAP OVERRIDE
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (7/12)
CPU (7/12)
CPU (7/12)
LA-9591P
LA-9591P
LA-9591P
12 58Friday, May 17, 2013
12 58Friday, May 17, 2013
12 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
D D
4
3
2
1
CFG STRAPS for CPU
CFG1
CFG0
1K_0402_1%
1K_0402_1%
12
RC232@
RC232@
1K_0402_1%
1K_0402_1%
12
RC233@
RC233@
UC1S
UC1S
AC60
12
CFG_RCOMP
TDI_IREF
CFG0
CFG1
CFG4
CFG8
CFG9
CFG10
CFG_RCOMP
TDI_IREF
AC62
AC63
AA63
AA60
AA62
AA61
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
U63
U62
V63
A5
E1
D1
J20
H18
B12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
CFG0<9>
CFG1<9>
CFG2<9>
CFG3<9>
CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>
CFG8<9>
CFG9<9>
CFG10<9>
CFG11<9>
CFG12<9>
CFG13<9>
C C
CFG14<9>
CFG15<9>
CFG16<9>
CFG18<9>
CFG17<9>
CFG19<9>
T33@ PAD~DT33@ PAD~D
T35@ PAD~DT35@ PAD~D
T37@ PAD~DT37@ PAD~D
T38@ PAD~DT38@ PAD~D
T39@ PAD~DT39@ PAD~D
RC235 49.9_0402_1%RC235 49.9_0402_1%
1 2
RC236 8.2K_0402_1%RC236 8.2K_0402_1%
HASWELL_MCP_E
HASWELL_MCP_E
RESERVED
RESERVED
19 OF 19
19 OF 19
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
RSVD
RSVD
VSS
VSS
RSVD
RSVD
Rev1p2
Rev1p2
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
PROC_OPI_RCOMP
AV62
D58
P22
N21
P20
R20
PROC_OPI_RCOMP
PAD~D T30
PAD~D
1 2
T20@PAD~D T20@PAD~D
T21@PAD~D T21@PAD~D
T22@PAD~D T22@PAD~D
T23@PAD~D T23@PAD~D
T24@PAD~D T24@PAD~D
T25@PAD~D T25@PAD~D
T26@PAD~D T26@PAD~D
T27@PAD~D T27@PAD~D
T28@PAD~D T28@PAD~D
T29@PAD~D T29@PAD~D
@
@
T30
T31 @PAD~D T31 @PAD~D
T32 @PAD~D T32 @PAD~D
T34 @PAD~D T34 @PAD~D
T36 @PAD~D T36 @PAD~D
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
CFG0
1:(Default) Normal Operation; No stall
0:Lane Reversed
PCH/PCH LESS MODE SELECTION
CFG1
RC23749.9_0402_1% RC23749.9_0402_1%
1:(Default) Normal Operation
0:Lane Reversed
B B
SAFE MODE BOOT
CFG10
A A
CFG10 CFG4
1K_0402_1%
1K_0402_1%
12
RC239@
RC239@
NO SVID PROTOCOL CAPABLE VR CONNECTED
1: POWER FEATURES ACTIVATED DURING
RESET
0: POWER FEATURES (ESPECIALLY CLOCK
CFG9
GATINE ARE NOT ACTIVATED
CFG9
12
1K_0402_1%
1K_0402_1%
RC240@
RC240@
1: VRS support SVID protocol are present
0:No VR support SVID is present
The chip will not generate(OR Respond to)
SVID activity
ALLOW THE USE OF NOA ON LOCKED UNITS
CFG8
CFG8
1K_0402_1%
1K_0402_1%
12
RC241@
RC241@
1: Enable(Default): Noa will be disable in
locked units and enable in un-locked
units
0: Enable Noa will be available pegardless of
the locking of the unit
CFG4
1K_0402_1%
1K_0402_1%
12
RC238
RC238
Display Port Presence Strap
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (8/12)
CPU (8/12)
CPU (8/12)
LA-9591P
LA-9591P
LA-9591P
13 58Friday, May 17, 2013
13 58Friday, May 17, 2013
13 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
D D
C C
4
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
UC1Q
UC1Q
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
1
HASWELL_MCP_E
HASWELL_MCP_E
17 OF 19
17 OF 19
3
3
12
RC254 @0_0402_5% RC254 @0_0402_5%
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
Rev1p2
Rev1p2
12
RC269 @0_0402_5% RC269 @0_0402_5%
A3
DC_TEST_A3_B3
A4
DC_TEST_A4
A60
DC_TEST_A60
A61
DC_TEST_A61_B61
A62
DC_TEST_A62
AV1
DC_TEST_AV1
AW1
DC_TEST_AW1
AW2
DC_TEST_AY2_AW2
AW3
DC_TEST_AY3_AW3
AW61
DC_TEST_AY61_AW61
AW62
DC_TEST_AY62_AW62
AW63
DC_TEST_AW63
2
2
12
RC266@0_0402_5% RC266@0_0402_5%
12
RC268@0_0402_5% RC268@0_0402_5%
4
1
Package Daisy Chain:
1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
HASWELL_MCP_E
UC1R
UC1R
T50@ PAD~DT50@ PAD~D
T52@ PAD~DT52@ PAD~D
B B
A A
T54@ PAD~DT54@ PAD~D
T55@ PAD~DT55@ PAD~D
T58@ PAD~DT58@ PAD~D
T60@ PAD~DT60@ PAD~D
T62@ PAD~DT62@ PAD~D
RSVD_AT2
RSVD_AU44
RSVD_AV44
RSVD_D15
RSVD_F22
RSVD_H22
RSVD_J21
AU44
AV44
AT2
RSVD
RSVD
RSVD
D15
RSVD
F22
RSVD
H22
RSVD
J21
RSVD
HASWELL_MCP_E
18 OF 19
18 OF 19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Rev1p2
Rev1p2
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
RSVD_N23
RSVD_R23
RSVD_T23
RSVD_U10
RSVD_AL1
RSVD_AM11
RSVD_AP7
RSVD_AU10
RSVD_AU15
RSVD_AW14
RSVD_AY14
PAD~D T48
PAD~D
PAD~D T49
PAD~D
PAD~D T51
PAD~D
PAD~D T53
PAD~D
PAD~D T56
PAD~D
PAD~D T57
PAD~D
PAD~D T59
PAD~D
PAD~D T61
PAD~D
PAD~D T63
PAD~D
PAD~D T64
PAD~D
PAD~D T65
PAD~D
@
@
T48
@
@
T49
@
@
T51
@
@
T53
@
@
T56
@
@
T57
@
@
T59
@
@
T61
@
@
T63
@
@
T64
@
@
T65
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (9/12)
CPU (9/12)
CPU (9/12)
LA-9591P
LA-9591P
LA-9591P
14 58Friday, May 17, 2013
14 58Friday, May 17, 2013
14 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
+VCC_CORE +1.35V_MEM
+1.05V_RUN
150_0402_1%
150_0402_1%
12
RC253
D D
C C
RESET_OUT#<37,9>
SVID ALERT
B B
SVID DATA
VIDSOUT<46>
VCC_SENSE
A A
CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU
RC253
CPU_PWR_DEBUG#
10K_0402_5%
10K_0402_5%
12
@
@
RC258
RC258
H_VR_EN H_VR_R EADY
RC263@ 0_0402_5%RC263@ 0_0402_5%
VIDALERT_N<46>
VCCSENSE<46>
12
12
+1.05V_VCCST
75_0402_1%
75_0402_1%
12
+1.05V_VCCST
110_0402_1%
110_0402_1%
12
+1.05V_VCCST +3.3V_RUN
RC25610K_0402_5% RC 25610K_0402_5%
UC4
UC4
1
NC
2
A
3
GND
74AUP1G07GW_TSSOP5
74AUP1G07GW_TSSOP5
RC244
RC244
RC249
RC249
VIDSOUT
+VCC_CORE
100_0402_1%
100_0402_1%
12
RC250
RC250
ESD test request
CC57
EMC@
CC57
EMC@
1 2
22U_0603_6.3V6M
22U_0603_6.3V6M
1 2
VCCST_PWRGD
CC22
@
CC22
@
100P_0402_50V8J
100P_0402_50V8J
10K_0402_5%
+3.3V_ALW
5
4
Y
H_CPU_SVIDALRT#
RC24843_0402_5% RC24843_0402_5%
10K_0402_5%
12
RC259@
RC259@
1 2
CC24@ 0.1U_0402_25V6CC24@ 0.1U_0402_25V6
H_VCCST_PWRGD
10K_0402_5%
10K_0402_5%
12
RC255@
RC255@
VCC
CAD Note: Place the PU resistors close to CPU
RC224 close to CPU 300 Â1500mils
12
CAD Note: Place the PU resistors close to CPU
RC249close to CPU 300 - 1500mils
VCCSENSE
+1.05V_RUN +VCCIO_OUT
RC242 0_0603_5%
@
RC242 0_0603_5%
@
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
+1.05V_VCCST
1K_0402_5%
1K_0402_5%
RC243
RC243
1 2
+1.05V_RUN +1.05V_VCCST
12
H_VCCST_PWRGD<9>
H_VR_EN<46 >
H_VR_READY<46>
PJP11
@PJP11
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
+1.35V_MEM
VIDSCLK<46>
1 2
RC245@ 0_0402_5%RC245@ 0_0402_5%
1 2
RC246@ 0_0402_5%RC246@ 0_0402_5%
1 2
RC247@ 0_0402_5%RC247@ 0_0402_5%
check
CPU_PWR_DEBUG#<9>
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
CC50
CC50
12
12
@
@
CC26
CC26
+1.35V_MEM
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
12
T66@ PA D~DT66@ PAD~D
T67@ PA D~DT67@ PAD~D
+VCC_CORE
T68@
T68@
PAD~D
PAD~D
T69@
T69@
PAD~D
PAD~D
T70@
T70@
PAD~D
PAD~D
+VCCIO_OUT
+VCCIOA_OUT
T71@
T71@
PAD~D
PAD~D
T72@
T72@
PAD~D
PAD~D
T73@
T73@
PAD~D
PAD~D
T74@
T74@
PAD~D
PAD~D
T75@
T75@
PAD~D
PAD~D
T76@
T76@
PAD~D
PAD~D
T77@
T77@
PAD~D
PAD~D
T78@
T78@
PAD~D
PAD~D
T79@
T79@
PAD~D
PAD~D
T80@
T80@
PAD~D
PAD~D
T81@
T81@
PAD~D
PAD~D
T82@
T82@
PAD~D
PAD~D
T83@
T83@
PAD~D
PAD~D
T84@
T84@
PAD~D
PAD~D
T85@
T85@
PAD~D
PAD~D
T86@
T86@
PAD~D
PAD~D
+1.05V_VCCST
+VCC_CORE
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
@
@
@
@
12
CC81
CC81
CC52
CC52
VCCSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
12
CC12
CC12
L59
J58
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
F59
N58
AC58
E63
AB23
A59
E20
AD23
AA23
AE59
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
AC22
AE22
AE23
AB57
AD57
AG57
C24
C28
C32
VDDQ DECOUPLING
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
12
12
UC1L
UC1L
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
CC16
CC16
CC13
CC13
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
12
CC17
CC17
HASWELL_MCP_E
HASWELL_MCP_E
HSW ULT POWER
HSW ULT POWER
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12 OF 19
12 OF 19
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
CC18
CC18
CC19
CC19
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
12
12
CC21
CC21
CC20
CC20
+VCC_CORE
C36
VCC
C40
VCC
C44
VCC
C48
VCC
C52
VCC
C56
VCC
E23
VCC
E25
VCC
E27
VCC
E29
VCC
E31
VCC
E33
VCC
E35
VCC
E37
VCC
E39
VCC
E41
VCC
E43
VCC
E45
VCC
E47
VCC
E49
VCC
E51
VCC
E53
VCC
E55
VCC
E57
VCC
F24
VCC
F28
VCC
F32
VCC
F36
VCC
F40
VCC
F44
VCC
F48
VCC
F52
VCC
F56
VCC
G23
VCC
G25
VCC
G27
VCC
G29
VCC
G31
VCC
G33
VCC
G35
VCC
G37
VCC
G39
VCC
G41
VCC
G43
VCC
G45
VCC
G47
VCC
G49
VCC
G51
VCC
G53
VCC
G55
VCC
G57
VCC
H23
VCC
J23
VCC
K23
VCC
K57
VCC
L22
VCC
M23
VCC
M57
VCC
P57
VCC
U57
VCC
W57
VCC
Rev1p2
Rev1p2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/12)
CPU (10/12)
CPU (10/12)
LA-9591P
LA-9591P
LA-9591P
15 58Friday, May 17, 2013
15 58Friday, May 17, 2013
15 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
+1.05V_MODPHY +1.05V_MODPHY_PCH
1 2
RC262@ 0_0805_5%RC262@ 0_0805_5%
CC29 place near K9;
CC27 place near L10
D D
CC74 place near M9
+1.05V_MODPHY
LC1
LC1
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
1U_0402_6.3V6K
1U_0402_6.3V6K
12
22U_0603_6.3V6M
22U_0603_6.3V6M
12
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
12
CC27
CC27
CC74
CC74
+PCH_AUSB3PLL
22U_0603_6.3V6M
22U_0603_6.3V6M
12
CC76
CC76
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC29
CC29
CC42
CC42
CC42 place near B18
LC2
LC2
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
CC49 place near B11
C C
LC5
LC5
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
+PCH_ASATA3PLL+1.05V_MODPHY
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
CC77
CC77
CC49
12
12
CC49
12
+V1.05S_APLLOPI+1.05V_RUN
100U_1206_6.3V6M
100U_1206_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC55
CC55
CC56
CC56
+3.3V_ALW_PCH
12
0.1U_0402_10V7K
0.1U_0402_10V7K
+3.3V_ALW_PCH
CC44
CC44
12
CC56 place near AA21
+1.05V_M
1 2
RC276@ 0_0603_5%RC276@ 0_0603_5%
CC66 place near AH13
CC61 CC62 place near J13
B B
1 2
RC265 0_0402_5%@ RC265 0_0402_5%@
+3.3V_ALW
1 2
RC267@ 0_0402_5%RC267@ 0_0402_5%
CC32 place near AH10
+PCH_DCPSUS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
@
12
12
CC66@
CC66@
@
12
CC61@
CC61@
CC62
CC62
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
CC51 place near J18
+PCH_VCCDSW3_3+3.3V_ALW_PCH
+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
12
CC32
CC32
4
+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
12
CC31
CC31
CC44 place near AH14
CC28 place near AC9
22U_0603_6.3V6M
22U_0603_6.3V6M
+3.3V_RUN
CC28
CC28
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
22U_0603_6.3V6M
22U_0603_6.3V6M
12
CC43
CC43
+1.05V_RUN
LC3
LC3
LC6
LC6
1 2
CC43 place near V8
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC58 place near A20
+1.05V_MODPHY_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC64
CC64
CC63
CC63
100U_1206_6.3V6M
100U_1206_6.3V6M
12
12
+PCH_AUSB3PLL
+PCH_ASATA3PLL
+V1.05S_APLLOPI
+PCH_DCPSUS
+PCH_VCCDSW3_3
+PCH_VCC1P05
+PCH_VCCACLKPLL
CC63 close to Pin J17
CC64 close to Pin R21
+3.3V_ALW_PCH
+PCH_VCC1P05+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC79
CC79
CC51
CC51
+PCH_VCCACLKPLL
1U_0402_6.3V6K
1U_0402_6.3V6K
100U_1206_6.3V6M
100U_1206_6.3V6M
CC58
CC58
CC78
CC78
12
AA21
W21
AH14
AH13
AH10
AE20
AE21
B18
B11
AC9
AA9
K19
A20
R21
T21
K18
M20
V21
K9
L10
M9
N8
P9
Y20
J13
V8
W9
J18
J17
UC1M
UC1M
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
@
@
12
CC73
CC73
+
+
HASWELL_MCP_E
HASWELL_MCP_E
mPHY
mPHY
OPI
OPI
USB3
USB3
AXALIA/HDA
AXALIA/HDA
VRM/USB2/AZALIA
VRM/USB2/AZALIA
GPIO/LCC
GPIO/LCC
LPT LP POWER
LPT LP POWER
3
1 2
CC83 22U_0603_6.3V6MEMC@CC83 22U_0603_6.3V6MEMC@
1 2
CC84 22U_0603_6.3V6MEMC@CC84 22U_0603_6.3V6MEMC@
1 2
CC85 22U_0603_6.3V6MEMC@CC85 22U_0603_6.3V6MEMC@
AH11
AG10
AE7
+DCPRRTC
CC36 0.1U_0402_10V7KCC36 0.1U_0402_10V7K
Y8
AG14
AG13
J11
H11
H15
AE8
AF22
AG19
+PCH_VCCDSW
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16
U8
T9
AB8
AC20
AG16
CC60 place near AG16
AG17
ESD test request
+PCH_RTC_VCCSUS3_3
1 2
+1.05V_M
CC34 and CC33 place near
J11; CC37 place near AE8
CC46 CC47 place near AE9
+PCH_DCPSUS1
+1.5V_THERMAL
CC45 place near U8
+PCH_DCPSUS4
+1.05V_RUN
+1.05V_RUN+1.05V_M
13 OF 19
13 OF 19
@
@
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
12
+
+
CC71
CC71
THERMAL SENSOR
THERMAL SENSOR
@
@
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
12
+
+
CC72
CC72
RTC
RTC
SPI
SPI
CORE
CORE
SDIO/PLSS
SDIO/PLSS
SUS OSCILLATOR
SUS OSCILLATOR
USB2
USB2
+1.05V_RUN +VCC_CORE
+1.05V_RUN +3.3V_RUN
VCCSUS3_3
VCCRTC
DCPRTC
VCCSPI
VCCASW
VCCASW
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
VCC1_05
VCC1_05
Rev1p2
Rev1p2
2
CC35,CC38, CC39 place near AG10
CC40 place near Y8
+1.05V_M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CC46
CC46
@
@
CC47
CC47
12
1U_0402_6.3V6K
1U_0402_6.3V6K
CC45
CC45
CC59 place near K14
+3.3V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
CC60
CC60
12
+RTC_CELL
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
@
@
CC39
CC39
CC35
+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
CC33
CC33
CC35
+3.3V_M
0.1U_0402_10V7K
0.1U_0402_10V7K
@
@
12
CC40
CC40
10U_0603_6.3V6M
10U_0603_6.3V6M
12
CC34
CC34
+PCH_VCCDSW
CC38
CC38
12
CC37
CC37
CC65 place near AG19
+3.3V_RUN
0.1U_0402_10V7K
0.1U_0402_10V7K
12
CC59
CC59
+PCH_RTC_VCCSUS3_3 +3.3V_ALW_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC30
CC30
12
+PCH_DCPSUS4 +1.05V_M
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC53@
CC53@
1
RC275 5.11_0402_1%RC275 5.11_0402_1%
12
12
RC261 @0_0402_5% RC261@0_0402_5%
12
RC264@0_0402_5% RC264 @0_0402_5%
CC30 place near AH11
1U_0402_6.3V6K
1U_0402_6.3V6K
CC54@
CC54@
CC54 place near AD10
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
100U_1206_6.3V6M
100U_1206_6.3V6M
12
12
LC4@
LC4@
CC75@
CC75@
+PCH_VCCDSW_R
12
+3.3V_ALW
RC272 @0_0402_5% RC272 @0_0402_5%
12
1U_0402_6.3V6K
1U_0402_6.3V6K
CC65
CC65
+1.05V_M+PCH_DCPSUS1
CC53 place near AB8
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (11/12)
CPU (11/12)
CPU (11/12)
LA-9591P
LA-9591P
LA-9591P
1
16 58Friday, May 17, 2013
16 58Friday, May 17, 2013
16 58Friday, May 17, 2013
0.4
0.4
0.4
5
D D
HASWELL_MCP_E
HASWELL_MCP_E
UC1N
UC1N
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
AB22
VSS
AB7
VSS
AC61
VSS
AD21
VSS
AD3
VSS
AD63
VSS
AE10
VSS
AE5
VSS
AE58
C C
B B
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14 OF 19
14 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Rev1p2
Rev1p2
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
4
HASWELL_MCP_E
HASWELL_MCP_E
UC1O
UC1O
AP22
VSS
AP23
VSS
AP26
VSS
AP29
VSS
AP3
VSS
AP31
VSS
AP38
VSS
AP39
VSS
AP48
VSS
AP52
VSS
AP54
VSS
AP57
VSS
AR11
VSS
AR15
VSS
AR17
VSS
AR23
VSS
AR31
VSS
AR33
VSS
AR39
VSS
AR43
VSS
AR49
VSS
AR5
VSS
AR52
VSS
AT13
VSS
AT35
VSS
AT37
VSS
AT40
VSS
AT42
VSS
AT43
VSS
AT46
VSS
AT49
VSS
AT61
VSS
AT62
VSS
AT63
VSS
AU1
VSS
AU16
VSS
AU18
VSS
AU20
VSS
AU22
VSS
AU24
VSS
AU26
VSS
AU28
VSS
AU30
VSS
AU33
VSS
AU51
VSS
AU53
VSS
AU55
VSS
AU57
VSS
AU59
VSS
AV14
VSS
AV16
VSS
AV20
VSS
AV24
VSS
AV28
VSS
AV33
VSS
AV34
VSS
AV36
VSS
AV39
VSS
AV41
VSS
AV43
VSS
AV46
VSS
AV49
VSS
AV51
VSS
AV55
VSS
15 OF 19
15 OF 19
Rev1p2
Rev1p2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
UC1P
UC1P
2
HASWELL_MCP_E
HASWELL_MCP_E
16 OF 19
16 OF 19
VSS_SENSE
Rev1p2
Rev1p2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
VSSSENSE
RC260 100_0402_1%R C260 100_0402_1%
1
VSSSENSE <46>
1 2
CAD Note: RC260 SHOULD BE PLACED CLOSE TO CPU
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (12/12)
CPU (12/12)
CPU (12/12)
LA-9591P
LA-9591P
LA-9591P
17 58Friday, May 17, 2013
17 58Friday, May 17, 2013
17 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
DDR_A_DQS#[0..7]<8>
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
D D
Layout Note:
Place near JDIMM1
+1.35V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CD4
CD4
CD5
CD5
10U_0603_6.3V6M
10U_0603_6.3V6M
CD14
CD14
CD15@
CD15@
12
Layout Note:
Place near
JDIMM1.203,204
0.1U_0402_25V6
0.1U_0402_25V6
12
12
CD26
CD26
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD6
CD6
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD16
CD16
12
12
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
CD27
CD27
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CD7
CD7
10U_0603_6.3V6M
10U_0603_6.3V6M
CD17
CD17
12
12
CD28
CD28
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD9
CD9
CD8
CD8
@
@
CD18
CD18
0.1U_0402_25V6
0.1U_0402_25V6
CD10
CD10
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD20
CD20
CD19
CD19
12
12
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
CD30
CD30
CD29
CD29
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C C
B B
A A
+1.35V_MEM
10U_0603_6.3V6M
10U_0603_6.3V6M
12
+0.675V_DDR_VTT
12
12
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
CD11
CD11
10U_0603_6.3V6M
10U_0603_6.3V6M
12
CD21
CD21
+
+
CD31
CD31
+SM_VREF_DQ0_DIMM1
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
CD22
CD22
1 2
RD5@ 0_0402_5%RD5@ 0_0402_5%
1 2
RD6@ 0_0402_5%RD6@ 0_0402_5%
1 2
RD1@ 0_0402_5%RD1@ 0_0402_5%
+DIMM1_VREF_DQ
+3.3V_RUN
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
12
CD1
CD1
DDR_CKE0_DIMMA<8>
DDR_A_BS2<8>
M_CLK_DDR0<8>
DDR_A_BS0<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
DDR_CS1_DIMMA#<8>
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
@
@
12
CD25
CD25
DDR_A_D8
12
CD2
CD2
DDR_A_D14 DDR_A_D15
DDR_A_D10 DDR_A_D11
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_D44 DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA9
DDR_A_MA8
M_CLK_DDR0 M_CLK_DDR1
M_CLK_DDR#0 M_CLK_DDR#1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
DDR_A_D36 DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
+0.675V_DDR_VTT
0.1U_0402_25V6
0.1U_0402_25V6
12
CD24
CD24
H=4mm
Reverse Type
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26
CKE073CKE1
VDD175VDD2
77
NC1
79
BA2
VDD381VDD4
A12/BC#83A11
85
A9
VDD587VDD6
89
A8
91
A5
VDD793VDD8
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A621-U4R6-7H
FOX_AS0A621-U4R6-7H
CONN@
CONN@
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQS3
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
+1.35V_MEM+1.35V_MEM
2
4
DQ4
DQ5
DQ6
DQ7
A15
A14
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
DDR_A_D9
6
DDR_A_D12DDR_A_D13
8
10
DDR_A_DQS#1
12
DDR_A_DQS1
14
16
18
20
22
DDR_A_D25
24
DDR_A_D24
26
28
30
DDR3_DRAMRST#
32
34
DDR_A_D27
36
DDR_A_D26
38
40
42
DDR_A_D40DDR_A_D41
44
46
48
50
DDR_A_D42
52
DDR_A_D46
54
56
DDR_A_D52
58
DDR_A_D53
60
62
DDR_A_DQS#6
64
DDR_A_DQS6
66
68
DDR_A_D54
70
DDR_A_D55
72
74
76
78
DDR_A_MA15
80
DDR_A_MA14
82
84
DDR_A_MA11DDR_A_MA12
86
DDR_A_MA7
88
90
DDR_A_MA6
92
DDR_A_MA4DDR_A_MA5
94
96
DDR_A_MA2DDR_A_MA3
98
DDR_A_MA0DDR_A_MA1
100
102
104
106
108
DDR_A_BS1
110
DDR_A_RAS#
112
114
DDR_CS0_DIMMA#
116
M_ODT0
118
120
M_ODT1
122
124
126
128
130
DDR_A_D5
132
DDR_A_D4
134
136
138
140
DDR_A_D3
142
DDR_A_D7
144
146
DDR_A_D18
148
DDR_A_D19
150
152
DDR_A_DQS#2
154
DDR_A_DQS2
156
158
DDR_A_D22
160
DDR_A_D23
162
164
166
DDR_A_D32DDR_A_D33
168
170
172
174
DDR_A_D35
176
DDR_A_D39
178
180
DDR_A_D63
182
DDR_A_D59
184
186
DDR_A_DQS#7
188
DDR_A_DQS7
190
192
DDR_A_D56
194
DDR_A_D57
196
198
200
202
204
+0.675V_DDR_VTT
206
0.1U_0402_25V6
0.1U_0402_25V6
CD3@
CD3@
12
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_CKE1_DIMMA <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <8>
+SM_VREF_CA_DIMM1
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
CD12
CD12
CD13
CD13
12
12
DDR_XDP_WAN_SMBDAT <19,25,31,7,9>
DDR_XDP_WAN_SMBCLK <19,25,31,7,9>
1 2
+SM_VREF_CA_DIMM
RD12@0_0402_5% RD12@0_0402_5%
+5V_ALW
DDR_PG_CTRL<9>
1 2
RC279@ 0_0402_5%RC279@ 0_0402_5%
+1.35V_MEM
1.8K_0402_1%
1.8K_0402_1%
12
+SM_VREF_DQ0_DIMM1
1.8K_0402_1%
1.8K_0402_1%
12
DDR3L SODIMM ODT GENERATION
+1.35V_MEM
220K_0402_5%
220K_0402_5%
12
R28
R28
0.675V_DDR_VTT_ON
2M_0402_5%
2M_0402_5%
R32@
R32@
1 2
QD1
QD1
BSS138-G_SOT23-3
BSS138-G_SOT23-3
123
D
S
D
S
G
G
1
NC
2
A
3
GND
74AUP1G07GW_TSSOP5
74AUP1G07GW_TSSOP5
+1.35V_MEM
RC217
RC217
1 2
RC173 2_0402_1%RC173 2_0402_1%
RC221
RC221
1 2
R29 66.5_0402_1%R29 66.5_0402_1%
1 2
R30 66.5_0402_1%R30 66.5_0402_1%
1 2
R31 66.5_0402_1%R31 66.5_0402_1%
1 2
R33 66.5_0402_1%R33 66.5_0402_1%
+1.35V_MEM
U5
U5
5
VCC
4
Y
470_0402_5%
470_0402_5%
12
RD3
RD3
DDR3_DRAMRST#_CPU <9>DDR3_DRAMRST#<19>
0.022U_0402_16V7K
0.022U_0402_16V7K
CC70
CC70
12
24.9_0402_1%
24.9_0402_1%
12
RC195
RC195
M_ODT0
M_ODT1
1 2
CD23@ 0.1U_0402_25V6CD23@ 0.1U_0402_25V6
0.675V_DDR_VTT_ON
+SM_VREF_DQ0
M_ODT2 <19>
M_ODT3 <19>
0.675V_DDR_VTT_ON <43>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDR3L
DDR3L
DDR3L
LA-9591P
LA-9591P
LA-9591P
1
18 58Friday, May 17, 2013
18 58Friday, May 17, 2013
18 58Friday, May 17, 2013
0.4
0.4
0.4
5
4
3
2
1
H=4mm
DDR_B_DQS#[0..7]<8>
DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>
D D
DDR_B_MA[0..15]<8>
+SM_VREF_DQ1_DIMM2
1 2
RD7@ 0_0402_5%RD7@ 0_0402_5%
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
Layout Note:
Place near JDIMM2
+1.35V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C C
+1.35V_MEM
10U_0603_6.3V6M
10U_0603_6.3V6M
12
1U_0402_6.3V6K
12
12
CD35
CD35
CD36
CD36
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD45
CD45
CD46@
CD46@
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD39
CD39
CD38
CD38
CD37
CD37
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD48
CD48
CD47@
CD47@
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
10U_0603_6.3V6M
10U_0603_6.3V6M
CD49
CD49
12
1U_0402_6.3V6K
12
12
CD41
CD41
CD42
CD40
CD40
CD50
CD50
CD42
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
CD53
CD53
CD52
CD52
CD51
CD51
12
12
+
+
Layout Note:
Place near
0.1U_0402_25V6
0.1U_0402_25V6
CD54
CD54
12
JDIMM2.203,204
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
CD55
CD55
12
12
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
CD56
CD56
12
10U_0603_6.3V6M
CD58
CD58
CD59
CD57
CD57
CD59
12
12
+3.3V_RUN
B B
+0.675V_DDR_VTT
A A
+DIMM2_VREF_DQ
+3.3V_RUN
RD10@ 0_0402_5%RD10@ 0_0402_5%
12
+1.35V_MEM +1.35V_MEM
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
12
CD32
CD32
DDR_CKE2_DIMMB<8>
DDR_B_BS2<8>
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_B_BS0<8>
DDR_B_WE#<8>
DDR_B_CAS#<8>
DDR_CS3_DIMMB#<8>
12
0_0402_5%
0_0402_5%
DDR_B_D8 DDR_B_D9
0.1U_0402_25V6
0.1U_0402_25V6
DDR_B_D14
12
CD33
CD33
DDR_B_D10
DDR_B_D11
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D42
DDR_B_D56
DDR_B_D57
DDR_B_D59
DDR_B_D58
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
DDR_B_BS2
DDR_B_MA9
DDR_B_MA8
M_CLK_DDR2 M_CLK_DDR3
M_CLK_DDR#2 M_CLK_DDR#3
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D4
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20
DDR_B_D22
DDR_B_D23
DDR_B_D36 DDR_B_D37
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49
DDR_B_D48
DDR_B_D53
+0.675V_DDR_VTT +0.675V_DDR_VTT
RD11@
RD11@
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
12
CD61
CD61
CD60
CD60
Reverse Type
JDIMM2 CONN@
JDIMM2 CONN@
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A621-U4R6-7H
FOX_AS0A621-U4R6-7H
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_B_D12
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D13
DDR_B_D15
DDR_B_D25
DDR_B_D24
DDR3_DRAMRST#
DDR_B_D30
DDR_B_D31
DDR_B_D45
DDR_B_D44
DDR_B_D47
DDR_B_D43
DDR_B_D61
DDR_B_D60
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D63
DDR_B_D62
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11DDR_B_MA12
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4DDR_B_MA5
DDR_B_MA2DDR_B_MA3
DDR_B_MA0DDR_B_MA1
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_D5
DDR_B_D0DDR_B_D1
DDR_B_D2
DDR_B_D6
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D32DDR_B_D33
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
DDR3_DRAMRST# <18>
0.1U_0402_25V6
0.1U_0402_25V6
12
CD34@
CD34@
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_CKE3_DIMMB <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <8>
M_ODT2 <18>
M_ODT3 <18>
+SM_VREF_CA_DIMM2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
CD43
CD43
CD44
CD44
12
12
DDR_XDP_WAN_SMBDAT <18,25,31,7,9>
DDR_XDP_WAN_SMBCLK <18,25,31,7,9>
1 2
+SM_VREF_DQ1_DIMM2
+SM_VREF_CA_DIMM
RD13@0_0402_5% RD13@0_0402_5%
+1.35V_MEM
1.8K_0402_1%
1.8K_0402_1%
12
RC67
RC67
RC68 2_0402_1%RC68 2_0402_1%
1.8K_0402_1%
1.8K_0402_1%
12
RC69
RC69
+1.35V_MEM
1.8K_0402_1%
1.8K_0402_1%
12
RC130
RC130
1 2
RC126 2_0402_1%RC126 2_0402_1%
1.8K_0402_1%
1.8K_0402_1%
12
RC132
RC132
1 2
+SM_VREF_CA+SM_VREF_CA_DIMM
0.022U_0402_16V7K
0.022U_0402_16V7K
CC67
CC67
12
24.9_0402_1%
24.9_0402_1%
12
RC83
RC83
+SM_VREF_DQ1
0.022U_0402_16V7K
0.022U_0402_16V7K
CC69
CC69
12
24.9_0402_1%
24.9_0402_1%
12
RC128
RC128
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A11
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDR3L
DDR3L
DDR3L
LA-9591P
LA-9591P
LA-9591P
1
19 58Friday, May 17, 2013
19 58Friday, May 17, 2013
19 58Friday, May 17, 2013
0.4
0.4
0.4
5
D D
4
3
2
1
+3.3V_ALW_PCH
U29
U29
1 2
1 2
1
B
2
A
NFC_DET#
TP_NFC_RSVD3
PLTRST_NFC#<9>
PCH_NFC_RST<12>
TC7SH08FU_SSOP5~D
C C
B B
TC7SH08FU_SSOP5~D
+3.3V_ALW_PCH
R38 100K _0402_5%R38 100K_0402_5%
R37@ 0_0402_5%R37@ 0_0402_5%
5
P
G
3
0.1U_0402_25V6
0.1U_0402_25V6
4
O
C388@
C388@
12
NFC_RST
T87@ PAD~DT87@ PAD~ D
T88@ PAD~DT88@ PAD~ D
NFC_SMBCLK<7>
NFC_SMBDATA<7>
T89@ PAD~DT89@ PAD~ D
NFC CONN
+3.3V_ALW_PCH
TP_NFC_SWP_PW R_RSVD
TP_NFC_RSVD4
NFC_RST
NFC_SMBCLK
NFC_SMBDATA
NFC_IRQ<12>
NFC_DET#<12>
TP_NFC_RSVD3
TP_NFC_RSVD1
NFC_DET#
JNFC1
JNFC1
GND
GND
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E-T_6705K-Y15N-00L
E-T_6705K-Y15N-00L
CONN@
CONN@
17
16
+3.3V_ALW_PCH
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
12
C1
C1
C1 close to JNFC1
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
NFC
NFC
NFC
LA-9591P
LA-9591P
LA-9591P
20 58Friday, May 17, 2013
20 58Friday, May 17, 2013
20 58Friday, May 17, 2013
1
0.4
0.4
0.4
2
1
+1.05V_RUN_VMM
L1
L1
1 2
BLM18AG102SN1D_2P
BLM18AG102SN1D_2P
+1.05V_RUN_VMM
BLM18AG102SN1D_2P
BLM18AG102SN1D_2P
B B
+3.3V_RUN_VMM
1 2
BLM18AG102SN1D_2P
BLM18AG102SN1D_2P
L4
L4
1 2
L5
L5
10U_0603_6.3V6M
10U_0603_6.3V6M
12
C132
C132
+1.05V_VMM_VDD
1U_0603_10V6KC81U_0603_10V6K
12
12
C8
12
+1.05V_VMM_VDDTX
1U_0603_10V6K
1U_0603_10V6K
12
12
C21
C21
+3.3V_RUN_VDDIO
1U_0603_10V6K
1U_0603_10V6K
12
12
C26
C26
DOCKED<27,28,32,36>
+5V_ALW
+3.3V_RUN +3.3V_RUN_VMM
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
12
C11
C11
0.1U_0402_25V6
0.1U_0402_25V6
12
C17
C17
0.01U_0402_16V7K
0.01U_0402_16V7K
12
C23
C23
0.01U_0402_16V7K
0.01U_0402_16V7K
12
C28
C28
0.01U_0402_16V7K
12
C10
C10
0.01U_0402_16V7K
0.01U_0402_16V7K
C18
C18
0.01U_0402_16V7K
0.01U_0402_16V7K
C24
C24
0.01U_0402_16V7K
0.01U_0402_16V7K
C29
C29
1
2
3
4
5
6
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
0.1U_0402_25V6C90.1U_0402_25V6
12
C9
1U_0603_10V6K
1U_0603_10V6K
12
C25
C25
0.1U_0402_25V6
0.1U_0402_25V6
12
C22
C22
0.1U_0402_25V6
0.1U_0402_25V6
12
C27
C27
+3.3V_RUN_VDDA
+1.05V_RUN +1.05V_RUN_VMM
DOCKED
DOCKED
C12
C12
U31
U31
VIN1
VOUT1
VIN1
VOUT1
ON1
VBIAS
ON2
VIN2
VOUT2
VIN27VOUT2
F12
G12
E10
H11
E12
D12
J10
K10
C11
C12
K11
K12
E6
E7
E8
E9
H6
H7
H8
H9
E3
G3
C8
C9
J3
E5
H3
F3
D3
C7
C6
K8
K9
J2
C3
C4
K3
K4
J4
GND
GPAD
CT1
CT2
U6B
U6B
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDRX
VDDRX
VDDTX0
VDDTX0
VDDTX1
VDDTX1
VDDXT1V
VDDLP
VDDRXA0
VDDRXA1
VDDRXA2
VDDTX0A0
VDDTX0A1
VDDTX0A2
VDDTX1A0
VDDTX1A1
VDDTX1A2
VGA_AVDD
VGA_AVDD
VGA_AVDD
VGA_AVDD
VDDSA
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDXT3V
14
13
12
11
10
9
8
15
3.3V Analog
3.3V Analog
1V Digital 1 V Analog 3.3V IO
1V Digital 1 V Analog 3.3V IO
IDTVMM2320BKG8_BGA168
IDTVMM2320BKG8_BGA168
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
VDDRX_33
VDDTX0_33
VDDTX1_33
VGA_AVDD33
VGA_AVDD33
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
1 2
C432 0.1U_0402_10V7KC432 0.1U_0402_10V7K
1 2
C433 470P_0402_50V7KC433 470P_0402_50V7K
1 2
C394 470P_0402_50V7KC394 470P_0402_50V7K
C392
C392
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
+3.3V_RUN_VDDA
H5
C10
H12
K6
K7
C5
D5
D6
D7
D8
D9
D10
D11
E4
E11
F4
F5
F6
F7
F8
F9
F10
F11
G4
G5
G6
G7
G8
G9
G10
G11
H4
D4
J5
J11
J12
K5
H10
J6
J7
J8
J9
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
12
12
12
12
C15
C15
C14
C14
C13
C13
L2
L2
1 2
BLM18AG102SN1D_2P
BLM18AG102SN1D_2P
1U_0603_10V6K
1U_0603_10V6K
C16
C16
CLK_27M_IN_R
22P_0402_50V8J
22P_0402_50V8J
12
+3.3V_RUN_VMM
DP12412_P0<27>
DP12412_N0<27>
DP12412_P1<27>
DP12412_N1<27>
DP12412_P2<27>
DP12412_N2<27>
DP12412_P3<27>
DP12412_N3<27>
DP12412_AUX<27>
DP12412_AUX#<27>
12
VMM_GPIO9
R631M_0402_5% R631M_0402_5%
12
SW_DPC_AUX
R921M_0402_5% R921M_0402_5%
12
SW_DPB_AUX
R471M_0402_5% R471M_0402_5%
12
RED_DOCK
R311150_0402_1% R311150_0402_1%
12
GREEN_DOCK
R312150_0402_1% R312150_0402_1%
12
BLUE_DOCK
R351150_0402_1% R351150_0402_1%
12
R207@100K_0402_5% R207 @100K_0402_5%
R107@ 0_0402_5%R107@ 0_0402_5%
27MHZ_12PF_X1E000021042600
27MHZ_12PF_X1E000021042600
1
2
C42
C42
LP_CTL
1 2
Y1
Y1
IN
GND
U6A
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
DP12412_HPD<27>
PLTRST_VMM2320#<9>
1M_0402_5%
1M_0402_5%
12
R66
R66
3
OUT
4
GND
22P_0402_50V8J
22P_0402_50V8J
12
C43
C43
DP12412_P0_C
C1550.1U_0402_10V7K C1550.1U_0402_10V7K
DP12412_N0_C
C1560.1U_0402_10V7K C1560.1U_0402_10V7K
DP12412_P1_C
C1570.1U_0402_10V7K C1570.1U_0402_10V7K
DP12412_N1_C
C1580.1U_0402_10V7K C1580.1U_0402_10V7K
DP12412_P2_C
C1590.1U_0402_10V7K C1590.1U_0402_10V7K
DP12412_N2_C
C1600.1U_0402_10V7K C1600.1U_0402_10V7K
DP12412_P3_C
C1610.1U_0402_10V7K C1610.1U_0402_10V7K
DP12412_N3_C
C1620.1U_0402_10V7K C1620.1U_0402_10V7K
DP12412_AUX_C
C190.1U_0402_10V7K C190.1U_0402_10V7K
DP12412_AUX#_C
C200.1U_0402_10V7K C200.1U_0402_10V7K
SRCDET
DP12412_HPD
VMM_MESCL
VMM_MESDA
VMM_SPI_WP#
VMM_SPI_CS#
VMM_SPI_CLK
VMM_SPI_DIN
VMM_SPI_DO
VMM_GPIO6
VMM_GPIO7
VMM_GPIO8
VMM_GPIO9
LP_CTL
CLK_27M_IN
CLK_27M_OUT
EEPROM
U7
U7
VMM_SPI_CS#
VMM_SPI_DIN
VMM_SPI_WP#
1
CS#
2
DO(IO1)
3
WP#(IO2)
GND4DI(IO0)
G1
G2
F1
F2
E1
E2
D1
D2
H1
H2
C2
J1
A13
B5
B6
B1
A4
B3
B4
A3
D14
D13
C14
C13
B14
B13
C1
M12
M13
L3
B2
A5
K2
L2
M1
M2
K1
L1
VCC
HOLD#(IO3)
CLK
W25X10CVSNIG_SO8
W25X10CVSNIG_SO8
U6A
RxP0
RxN0
RxP1
RxN1
RxP2
RxN2
RxP3
RxN3
RxAUXP
RXAUXN
RxSRCDET
RxHPD
RSTN_IN
MESCL
MESDA
ROMWP
SPICS
SPICLK
SPIDI
SPIDO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6/INT
GPIO7/MSCL
GPIO8/MSDA
GPIO9
LP_CTL
LP_EN
RX_STS
TX0_STS
TX1_STS
TX2_STS
XIN
XOUT
IDTVMM2320BKG8_BGA168
IDTVMM2320BKG8_BGA168
+3.3V_RUN_VMM
1 2
0.1U_0402_25V6
0.1U_0402_25V6
8
7
VMM_SPI_HOLD
6
VMM_SPI_CLK
5
VMM_SPI_DO
B7
Tx0P0
A7
Tx0N0
B8
Tx0P1
A8
Tx0N1
B9
Tx0P2
A9
Tx0N2
B10
Tx0P3
A10
Tx0N3
A14
CAD0
B11
Tx0HPD
Tx1P0
Tx1N0
Tx1P1
Tx1N1
Tx1P2
Tx1N2
Tx1P3
Tx1N3
CAD1
Tx1HPD
SSDA
SSCL
TRSTN
TMS2
TCK
TMS
TDI
TDO
SW_DPC_AUX
A11
SW_DPC_AUX#
B12
VMM_DPC_CTRLCLK
A12
VMM_DPC_CTRLDAT
A6
E13
E14
F13
F14
G13
G14
H13
H14
M14
J13
SW_DPB_AUX
J14
SW_DPB_AUX#
K13
VMM_DPB_CTRLCLK
L14
VMM_DPB_CTRLDAT
K14
L9
M9
M6
L6
M7
L7
M8
L8
L4
M4
M3
VMM2310_HDP
M5
VMM2310_AUXN
L5
VMM2310_AUXP
A1
A2
M11
M10
L12
L13
L11
L10
VMM2310_TX2P0
VMM2310_TX2N0
VMM2310_TX2N3
VMM2310_TX2N2
VMM2310_TX2N1
VMM2310_SCL
VMM2310_SDA
SW_DPB_AUX#
VMM_GPIO6
SRCDET
VMM_DPB_CTRLCLK
VMM_DPB_CTRLDAT
VMM_GPIO7
VMM_GPIO8
VMM_MESCL
VMM_MESDA
VMM_DPC_CTRLCLK
VMM_DPC_CTRLDAT
SW_DPC_AUX#
VMM_SPI_CS#
VMM_SPI_HOLD
Tx0AUXP
Tx0AUXN
Tx0DDCSCL
Tx0DDCSDA
Tx1AUXP
Tx1AUXN
Tx1DDCSCL
Tx1DDCSDA
VGA_VSYNC
VGA_HSYNC
VGA_RP
VGA_RN
VGA_GP
VGA_GN
VGA_BP
VGA_BN
VGA_SCL
VGA_SDA
VGA_DET
VGA_IREF
VGA_NC
C34
C34
DPC_LANE_P0 <34>
DPC_LANE_N0 <34>
DPC_LANE_P1 <34>
DPC_LANE_N1 <34>
DPC_LANE_P2 <34>
DPC_LANE_N2 <34>
DPC_LANE_P3 <34>
DPC_LANE_N3 <34>
DPC_CA_DET <24,34>
SW_DPC_AUX <24>
SW_DPC_AUX# <24>
VMM_DPC_CTRLCLK <24>
VMM_DPC_CTRLDAT <24>
DPC_DOCK_HPD <34>
DPB_LANE_P0 <34>
DPB_LANE_N0 <34>
DPB_LANE_P1 <34>
DPB_LANE_N1 <34>
DPB_LANE_P2 <34>
DPB_LANE_N2 <34>
DPB_LANE_P3 <34>
DPB_LANE_N3 <34>
DPB_CA_DET <24,34>
SW_DPB_AUX <24>
SW_DPB_AUX# < 24>
VMM_DPB_CTRLCLK <24>
VMM_DPB_CTRLDAT <24>
DPB_DOCK_HPD <34>
T40@ PAD~DT40@ PAD~D
I2C1_SDA_VMM < 12>
I2C1_SCL_VMM < 12>
+3.3V_RUN_VMM
1 2
R441M_0402_5% R 441M_0402_5%
1 2
R522.2K_0402_5% R522.2K_0402_5%
1 2
R691M_0402_5% R 691M_0402_5%
RP9
RP9
1
8
2
7
3
6
4 5
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
1 2
R402.2K_0402_5% R402.2K_0402_5%
1 2
R422.2K_0402_5% R422.2K_0402_5%
1 2
R492.2K_0402_5% R492.2K_0402_5%
1 2
R462.2K_0402_5% R462.2K_0402_5%
1 2
R911M_0402_5% R911M_0402_5%
12
R6410K_0402_5% R6410K_0402_5%
12
R652.2K_0402_5% R652.2K_0402_5%
1 2
+3.3V_RUN_VMM
12
R7410K_0402_5% 3@ R7410K_0402_5% 3@
R853.74K_0402_1% 3@ R853.74K_0402_1% 3@
VMM2310_TX2N3
VMM2310_TX2N2
A A
VMM2310_TX2N1
VMM2310_SCL
VMM2310_SDA
VMM2310_TX2N0
VMM2310_TX2P0
1 2
1 2
1 2
1 2
1 2
1 2
1 2
RED_DOCK
GREEN_DOCK
BLUE_DOCK
CLK_DDC2_DOCK
DAT_DDC2_DOCK
HSYNC_DOCK
VSYNC_DOCK
R73@ 0_0402_5%R73@ 0_0402_5%
R75@ 0_0402_5%R75@ 0_0402_5%
R76@ 0_0402_5%R76@ 0_0402_5%
R77@ 0_0402_5%R77@ 0_0402_5%
R81@ 0_0402_5%R81@ 0_0402_5%
R84@ 0_0402_5%R84@ 0_0402_5%
R88@ 0_0402_5%R88@ 0_0402_5%
RED_DOCK <34>
GREEN_DOCK <34>
BLUE_DOCK <34>
CLK_DDC2_DOCK <34>
DAT_DDC2_DOCK <34>
HSYNC_DOCK <34>
VSYNC_DOCK <34>
VMM2310_HDP
VMM2310_AUXN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DP 1.2 MST HUB
DP 1.2 MST HUB
DP 1.2 MST HUB
LA-9591P
LA-9591P
LA-9591P
21 58Friday, May 17, 2013
21 58Friday, May 17, 2013
21 58Friday, May 17, 2013
0.4
0.4
0.4
5
4
3
2
1
JEDP1
JEDP1
45
44
43
42
41
D D
ACES_50398-04071-001
ACES_50398-04071-001
CONN@
C C
B B
CONN@
+BL_PWR_SRC
Close to JEDP1.24~27
BIA_PWM
10K_0402_5%
10K_0402_5%
12
WebCAM
CCD_OFF<36>
3.3V_CAM_EN#<12>
change back to CCD_OFF at Goliad project
USBP3+<11>
A A
40
40
G5
39
39
G4
38
38
G3
37
37
G2
36
36
G1
35
35
34
34
33
33
32
32
31
31
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0.1U_0603_50V7K
0.1U_0603_50V7K
12
C52
C52
R95
R95
+3.3V_CAM
R102@ 0_0402_5%R102@ 0_0402_5%
R106@ 0_0402_5%R106@ 0_0402_5%
5
+5V_TSP
USBP3_DÂUSBP3_D+
LOOP_BACK
LE1
EMC@
LE1
EMC@
DISP_ON
EDP_CPU_AUX#_C
EDP_CPU_AUX_C
EDP_CPU_LANE_P0_C
EDP_CPU_LANE_N0_C
EDP_CPU_LANE_P1_C
EDP_CPU_LANE_N1_C
+LCDVDD
Close to JEDP1.11,12
D10
D10
3
1
2
BAT54CW_SOT323-3
BAT54CW_SOT323-3
PAD-OPEN1x1m
PAD-OPEN1x1m
12
@
@
PJP9
PJP9
+3.3V_CAM_Q
1 2
1 2
L8
EMC@
L8
EMC@
1
1
4
4
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
1 2
R100@ 0_0402_5%R100@ 0_0402_5%
1 2
R101@ 0_0402_5%R101@ 0_0402_5%
DMIC0 <26>
DMIC_CLK <26>
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
+3.3V_CAM
CAM_MIC_CBL_DET# <12>
+BL_PWR_SRC
1 2
EDP_CPU_HPD <10>
LCD_TST <36>
+LCDVDD
LCD_CBL_DET# <12>
+3.3V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
12
C63
C63
EDP_BIA_PWM
BIA_PWM_EC
BIA_PWM
BLM15BB221SN1D_2P~D
BLM15BB221SN1D_2P~D
12
C54 0.1U_0402_10V7KC54 0.1U_0402_10V7K
12
C55 0.1U_0402_10V7KC55 0.1U_0402_10V7K
12
C59 0.1U_0402_10V7KC59 0.1U_0402_10V7K
12
C56 0.1U_0402_10V7KC56 0.1U_0402_10V7K
12
C60 0.1U_0402_10V7KC60 0.1U_0402_10V7K
12
C57 0.1U_0402_10V7KC57 0.1U_0402_10V7K
+3.3V_CAM +5V_ALW
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
@
@
C68
C68
Close to JEDP1.33 Close to JLED1.1 Close to JLED1.40 Close to JLED1.2
EDP_BIA_PWM <10>
BIA_PWM_EC <37>
100P_0402_50V8J
12
12
CE1@
CE1@
CE2@
CE2@
EDP_CPU_AUX# <10 >
EDP_CPU_AUX <10>
EDP_CPU_LANE_P0 <10>
EDP_CPU_LANE_N0 <10>
EDP_CPU_LANE_P1 <10>
EDP_CPU_LANE_N1 <10>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
@
@
C3
C3
DISP_ON
100K_0402_5%
100K_0402_5%
12
R96
R96
Backlight POWER
+PWR_SRC
1000P_0402_50V7K
1000P_0402_50V7K
12
C66
C66
Q3
Q3
LP2301ALT1G_SOT23-3
LP2301ALT1G_SOT23-3
123
D
S
D
S
G
G
2
USBP3_D+
2
3
USBP3_D-
3
+3.3V_RUN
12
0.1U_0402_25V6
0.1U_0402_25V6
C67
C67
4
L30ESDL5V0C3-2_SOT23-3
L30ESDL5V0C3-2_SOT23-3
2
3
1
ESD depop location
LOOP_BACK
1K_0402_5%
1K_0402_5%
12
+5V_TSP
0.1U_0402_25V6
0.1U_0402_25V6
12
@
@
C62
C62
D21
D21
1
BAT54CW_SOT323-3
BAT54CW_SOT323-3
FDC654P-G_SSOT-6
FDC654P-G_SSOT-6
S
S
4 5
100K_0402_5%
100K_0402_5%
12
R97
R97
PWR_SRC_ON
1 2
R99 47K_0402_5%R99 47K_0402_5%
EN_INVPWR<37>USBP3-<11>
3
D8@
D8@
R108
R108
+3.3V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
12
@
@
C64
C64
3
2
Q2
Q2
D
D
6
2
1
G
G
Q4
Q4
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
123
D
S
D
S
G
G
USBP7- <11>
USBP7+ <11>
+5V_ALW
BATT_WHITE_LED#<40>
BATT_YELLOW_LED#<40>
PANEL_HDD_LED#<40>
BREATH_WHITE_LED#<40>
TOUCH_PANEL_INTR#<12>
For Touchscreen
3.3V_TS_EN<12>
LCDVDD POWER
PANEL_BKLEN <10>
PANEL_BKEN_EC <36>
LCD_VCC_TEST_EN<36>
ENVDD_PCH<10,36>
+BL_PWR_SRC
0.1U_0603_50V7K
0.1U_0603_50V7K
12
C65
C65
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
47K_0402_5%
47K_0402_5%
12
R94
R94
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
6
Q17A
Q17A
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
D2
D2
2
1
3
BAT54CW_SOT323-3
BAT54CW_SOT323-3
LED CONN
JLED1
JLED1
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
E-T_4260K-Q06N-23L
E-T_4260K-Q06N-23L
CONN@
CONN@
+5V_TSP
PAD-OPEN1x1m
PAD-OPEN1x1m
12
@
@
PJP10
PJP10
C431@
C431@
+5V_TSP_Q
+LCDVDD
12
EN_LCDPWR
100K_0402_5%
100K_0402_5%
1 2
LP2301ALT1G_SOT23-3
LP2301ALT1G_SOT23-3
123
34
Q17B
Q17B
5
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
VOUT
2
GND
3
EN
APL3512ABI-TRG_SOT23-5
APL3512ABI-TRG_SOT23-5
R104
R104
2nd source SA000028Y10
+5V_RUN+5V_RU N
Q1
Q1
D
S
D
S
0.1U_0402_25V6
0.1U_0402_25V6
G
G
C61
C61
12
+3.3V_ALW
U9
U9
5
VIN
4
SS
0.01U_0402_16V7K
0.01U_0402_16V7K
@
@
C430
C430
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
eDP CONN & Touch screen
eDP CONN & Touch screen
eDP CONN & Touch screen
LA-9591P
LA-9591P
LA-9591P
22 58Friday, May 17, 2013
22 58Friday, May 17, 2013
22 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
DDI1_LANE_P3<10>
DDI1_LANE_N3<10>
D D
DDI1_LANE_P2<10>
DDI1_LANE_N2<10>
DDI1_LANE_P1<10>
DDI1_LANE_N1<10>
C C
DDI1_LANE_P0<10>
DDI1_LANE_N0<10>
+3.3V_RUN
B B
CPU_DPB_CTRLCLK<10>
CPU_DPB_CTRLDAT<10>
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DPB_HPD<10>
1 2
A A
4
C103 0.1U_0402_10V7KC103 0.1U_0402_10V7K
C191 0.1U_0402_10V7KC191 0.1U_0402_10V7K
C199 0.1U_0402_10V7KC199 0.1U_0402_10V7K
C209 0.1U_0402_10V7KC209 0.1U_0402_10V7K
C269 0.1U_0402_10V7KC269 0.1U_0402_10V7K
C270 0.1U_0402_10V7KC270 0.1U_0402_10V7K
C271 0.1U_0402_10V7KC271 0.1U_0402_10V7K
C272 0.1U_0402_10V7KC272 0.1U_0402_10V7K
2
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
5
34
Q120B
Q120B
+3.3V_RUN
1M_0402_5%
1M_0402_5%
R475
R475
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
12
12
12
12
12
12
12
12
Q120A
Q120A
6
CPU_DPB_CTRLCLK_R
CPU_DPB_CTRLDAT_R
G
G
123
D
S
D
S
Q121
Q121
TMDS_CLK_C
TMDS_CLK#_C
TMDS_P0_C
TMDS_N0_C
TMDS_P1_C
TMDS_N1_C
TMDS_P2_C
TMDS_N2_C
HDMI_HPD_SINK
L9 @
L9 @
1 2
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L10EMC@
L10EMC@
4
4
1
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
L11 @
L11 @
1 2
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L12 @
L12 @
1 2
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L13 EMC@
L13 EMC@
4
4
1
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
L14 @
L14 @
1 2
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L15 @
L15 @
1 2
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L16 EMC@
L16 EMC@
4
4
1
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
L17 @
L17 @
1 2
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L18 @
L18 @
1 2
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L19 EMC@
L19 EMC@
4
4
1
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
L20 @
L20 @
1 2
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
1 2
R471 2.2K_0402_5%R471 2.2K_0402_5%
1 2
R470 2.2K_0402_5%R470 2.2K_0402_5%
1 2
R474 20K_0402_5%R474 20K_0402_5%
+5V_HDMI_DDC
3
3
3
2
2
3
3
2
2
3
3
2
2
3
3
2
2
12
12
12
1.8P_0402_50V8
1.8P_0402_50V8
12
+5V_RUN
1 2
@
@
C279
C279
RB751VM-40TE-17_SOD323-2
RB751VM-40TE-17_SOD323-2
TMDSB_CON_CLK
TMDSB_CON_CLK#
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
@
@
@
@
12
C274
C274
C273
C273
TMDSB_CON_P0
TMDSB_CON_N0
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
@
@
@
@
12
C275
C275
C276
C276
TMDSB_CON_P1
TMDSB_CON_N1
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
1.8P_0402_50V8
@
@
@
@
12
C278
C278
C277
C277
TMDSB_CON_P2
TMDSB_CON_N2
1.8P_0402_50V8
1.8P_0402_50V8
@
@
12
C382
C382
0_0402_5%
0_0402_5%
12
@
@
D65
D65
R472@
R472@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
C333
C333
HDMI_CEC
TMDS_P2_C
TMDS_N2_C
TMDS_P1_C
TMDS_N1_C
TMDS_P0_C
TMDS_N0_C
TMDS_CLK_C
TMDS_CLK#_C
+3.3V_RUN
12
2
+5V_RUN
1
AP2330W-7_SC59-3
AP2330W-7_SC59-3
IN
U48
U48
GND2OUT
3
+3.3V_RUN
12
R473@10K_0402_5% R473@10K_0402_5%
1 2
R465 470_0402_1%R465 470_0402_1%
R468 470_0402_1%R468 470_0402_1%
1 2
1 2
R467 470_0402_1%R467 470_0402_1%
R469 470_0402_1%R469 470_0402_1%
1 2
1 2
R462 470_0402_1%R462 470_0402_1%
1 2
R463 470_0402_1%R463 470_0402_1%
R464 470_0402_1%R464 470_0402_1%
1 2
1 2
R466 470_0402_1%R466 470_0402_1%
R460 10K_0402_5%R460 10K_0402_5%
1 2
+VHDMI_VCC
0.1U_0402_10V7K
0.1U_0402_10V7K
12
12
C87@
C87@
HDMI_HPD_SINK
CPU_DPB_CTRLDAT_R
CPU_DPB_CTRLCLK_R
HDMI_CEC
TMDSB_CON_CLK#
TMDSB_CON_CLK
TMDSB_CON_N0
TMDSB_CON_P0
TMDSB_CON_N1
TMDSB_CON_P1
TMDSB_CON_N2
TMDSB_CON_P2
HDMI_OB
2
G
G
10U_0603_6.3V6M
10U_0603_6.3V6M
C88
C88
19
18
17
16
15
14
13
12
11
10
LCN_AUF05-1922S10-0019
LCN_AUF05-1922S10-0019
1
D
D
Q29
Q29
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
S
S
3
JHDMI1 CONN@
JHDMI1 CONN@
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKÂCK_shield
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
GND
GND
GND
GND
1
20
21
22
23
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
HDMI CONN
HDMI CONN
HDMI CONN
LA-9591P
LA-9591P
LA-9591P
23 58Friday, May 17, 2013
23 58Friday, May 17, 2013
23 58Friday, May 17, 2013
0.4
0.4
0.4
5
4
3
2
1
14
13
12
11
10
9
8
+3.3V_RUN_VMM
+3.3V_RUN_VMM
AUX/DDC SW for DPB to E-DOCK
U11
U11
1
BE0
12
D D
C C
SW_DPB_AUX<21>
DPB_DOCK_AUX<34>
SW_DPB_AUX#<21>
DPB_DOCK_AUX#<34>
DPB_CA_DET<21,34>
SW_DPB_AUX_C
C94 0.1U_0402_10V7KC94 0.1U_040 2_10V7K
DPB_DOCK_AUX
12
SW_DPB_AUX#_C
C95 0.1U_0402_10V7KC95 0.1U_040 2_10V7K
DPB_DOCK_AUX#
DPB_CA_DET
2
3
4
5
6
7
+3.3V_RUN_VMM
2
G
G
VCC
A0
BE3
B0
BE1
A1
B1
GND
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
100K_0402_5%
100K_0402_5%
12
1
D
D
S
S
3
R60
R60
BSS138W-7-F_SOT323-3
BSS138W-7-F_SOT323-3
A3
B3
BE2
A2
B2
DPB_CA_DET#
Q10
Q10
AUX/DDC SW for DPC to E-DOCK
U13
U13
1
12
SW_DPC_AUX<21>
DPC_DOCK_AUX<34>
SW_DPC_AUX#<21>
DPC_DOCK_AUX#<34>
B B
SW_DPC_AUX_C
C98 0.1U_0402_10V7KC98 0.1U _0402_10V7K
DPC_DOCK_AUX
12
SW_DPC_AUX#_C
C99 0.1U_0402_10V7KC99 0.1U _0402_10V7K
DPC_DOCK_AUX#
BE0
2
A0
3
B0
4
BE1
5
A1
6
B1
7
GND
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
+3.3V_RUN_VMM
100K_0402_5%
100K_0402_5%
12
R56
R56
VCC
14
13
BE3
12
A3
11
B3
10
BE2
9
A2
8
B2
C93
C93
1 2
0.1U_0402_25V6
0.1U_0402_25V6
VMM_DPB_CTRLCLK <21>
VMM_DPB_CTRLDAT <21>
C97
C97
1 2
0.1U_0402_25V6
0.1U_0402_25V6
VMM_DPC_CTRLCLK <21>
VMM_DPC_CTRLDAT <21>
DPC_CA_DET#
BSS138W-7-F_SOT323-3
BSS138W-7-F_SOT323-3
1
D
D
2
G
G
S
S
Q6
Q6
3
1 2
1 2
DPC_CA_DET
DPB_CA_DET
DPC_CA_DET
DPC_CA_DET<21,34>
A A
R120 1M_0402_5%R120 1M_0402_5%
R121 1M_0402_5%R121 1M_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DP SW
DP SW
DP SW
LA-9591P
LA-9591P
LA-9591P
24 58Friday, May 17, 2013
24 58Friday, May 17, 2013
24 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
D D
+3.3V_RUN
1 2
1 2
DDR_XDP_WAN_S MBDAT
DDR_XDP_WAN_S MBCLK
R122 10K_0402_5%R122 10K_0402_5%
R123 10K_0402_5%R123 10K_0402_5%
C C
4
+3.3V_RUN
PAD-OPEN1x1m
PAD-OPEN1x1m
12
@PJP2
@
PJP2
+3.3V_RUN_FFS
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
12
12
C101
C101
HDD_FALL_INT<10>
DDR_XDP_WAN_S MBDAT<18,19,31,7,9>
DDR_XDP_WAN_S MBCLK<18,19,31,7,9>
+3.3V_HDD
FFS_INT2
1 2
R188@ 10K_0402_5%R188@ 10K_0402_5%
HDD_DEVSLP
Free Fall Sensor
C102
C102
1
11
9
7
6
4
8
U15
U15
LNG3DM
LNG3DM
VDD_IO
VDD14RES
INT 1
INT 2
SDO/SA0
SDA / SDI / SDO
SCL/SPC
CS
LNG3DMTR_LGA16_3X3~D
LNG3DMTR_LGA16_3X3~D
GND
GND
RES
RES
RES
3
+3.3V_RUN
100K_0402_5%
100K_0402_5%
R126
10
13
15
16
5
12
2
NC
3
NC
FFS_INT2<12 >
FFS_INT2
R126
2
2
+5V_HDD
100K_0402_5%
100K_0402_5%
12
R125@
R125@
12
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
6
Q19A
Q19A
1
FFS_INT2_Q
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
34
Q19B
Q19B
5
1
JSATA1
JSATA1
1
12
SATA_PTX_DRX_P1_C<6>
SATA_PTX_DRX_N1_C<6>
SATA_PRX_DTX_N1_C<6>
SATA_PRX_DTX_P1_C<6>
B B
+5V_HDD +3.3V_HDD
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
C111
C111
C112
12
C112
12
12
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
C114
C114
@
@
12
C113
C113
C105 0.01U_0402_16V7KC105 0.01U_0402_16V7K
12
C106 0.01U_0402_16V7KC106 0.01U_0402_16V7K
12
C109 0.01U_0402_16V7KC109 0.01U_0402_16V7K
12
C108 0.01U_0402_16V7KC108 0.01U_0402_16V7K
+3.3V_HDD
HDD_DEVSLP<12>
HDD_DET#<6>
PJP3@
PJP3@
+5V_RUN
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
HDD_DET#
+5V_HDD
FFS_INT2_Q
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
G1
22
G2
23
G3
24
G4
ACES_50406-02071-001
ACES_50406-02071-001
CONN@
CONN@
Place near HDD CONN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
HDD CONN
HDD CONN
HDD CONN
LA-9591P
LA-9591P
LA-9591P
25 58Friday, May 17, 2013
25 58Friday, May 17, 2013
25 58Friday, May 17, 2013
1
0.4
0.4
0.4
2
1
place close to pin27
+VDDA_AVDD1
0.1U_0402_25V6
0.1U_0402_25V6
12
C115
C115
+VDDA_PVDD
AUD_SENSE_A
AUD_SENSE_B
RING2
SLEEVE
1 2
C385 10U_0603_6.3V6MC385 10U_0603_6.3V6M
R162 18_0402_5%R162 18_0402_5%
R166 18_0402_5%R166 18_0402_5%
DMIC_CLK_L
R170EMC@ 33_0402_5%R170EMC@ 33_0402_5%
12
+ALC290_LDO_CAP
+ALC3226_CPVEE
+ALC3226_VREF
1 2
1 2
1 2
AUD_OUT_L
AUD_OUT_R
INT_SPK_L+
INT_SPK_L-
INT_SPK_R+
INT_SPK_R-
AUD_PC_BEEP
C134 2.2U_0603_6.3V6KC 134 2.2U_0603_6.3V6K
PCH_AZ_CODEC_BITCLK<6>
PCH_AZ_CODEC_SDOUT<6>
PCH_AZ_CODEC_SYNC<6>
PCH_AZ_CODEC_SDIN0<6>
PCH_AZ_CODEC_RST#<6>
DAI_12MHZ#<34>
DAI_DO#<34>
AUD_NB_MUTE#<36>
+3.3V_RUN_AUDIO
+3.3V_RUN_AUDIO
12
DAI_BCLK#<34>
DAI_LRCK#<34>
DAI_DI<34>
R150 10K_0402_5%R150 10K_0402_5%
Internal Speakers Header
CONN@
40 mils trace keep 10 mil spacing
INT_SPK_L+
INT_SPK_LÂINT_SPK_R+
INT_SPK_R-
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
12
12
C124@
C124@
B B
1 2
L22 BLM18PG330SN1_2P
EMC@
L22 BLM18PG330SN1_2P
EMC@
1 2
L23 BLM18PG330SN1_2P
EMC@
L23 BLM18PG330SN1_2P
EMC@
1 2
L24 BLM18PG330SN1_2P
EMC@
L24 BLM18PG330SN1_2P
EMC@
1 2
L25 BLM18PG330SN1_2P
EMC@
L25 BLM18PG330SN1_2P
EMC@
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
12
12
C125@
C125@
C127@
C127@
C126@
C126@
INT_SPKR_L+
INT_SPKR_LÂINT_SPKR_R+
INT_SPKR_R-
Close to U17
Close to U17 pin5 Close to U17 pin6
PCH_AZ_CODEC_SDOUT
47_0402_5%
47_0402_5%
12
R148@
R148@
0.1U_0402_10V7K
0.1U_0402_10V7K
C135@
C135@
12
PCH_AZ_CODEC_BITCLK
33_0402_5%
33_0402_5%
12
R149@
R149@
10P_0402_50V8J
10P_0402_50V8J
12
C136@
C136@
CONN@
JSPK1
JSPK1
1
1
2
2
3
3
4
4
5
GND1
6
GND2
E-T_4280K-F04N-05L
E-T_4280K-F04N-05L
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_25V6
0.1U_0402_25V6
C118
C118
C119
C119
12
Place R136 close to codec
R136 33_0402_5%R136 33_0402_5%
R137EMC_3@ 22_0402_5%R137EMC_3@ 22_0402_5%
R139EMC_3@ 22_0402_5%R139EMC_3@ 22_0402_5%
R142 33_0402_5%
3@
R142 33_0402_5%
3@
R143@ 0_0402_5%R143@ 0_0402_5%
R144@ 0_0402_5%R144@ 0_0402_5%
1 2
+3.3V_RUN_AUDIO
1U_0603_10V6K
1U_0603_10V6K
12
1 2
1 2
1 2
1 2
1 2
1 2
AUD_NB_MUTE#
@
@
C405
C405
12
I2S_MCLK
I2S_BCLK
I2S_DO
I2S_LRCLK
I2S_DI#
0.1U_0402_25V6
0.1U_0402_25V6
C120
C120
1U_0603_10V6K
1U_0603_10V6K
12
+DVDD_CORE
10U_0603_6.3V6M
10U_0603_6.3V6M
12
C121
C121
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_SDOUT
PCH_AZ_SDIN0_R
PCH_AZ_CODEC_RST#
Place R142 close to codec
C410
C410
U17
U17
1
DREG_OUT
3
DVDD-IO
9
DVDD
6
BIT-CLK
5
SDATA-OUT
10
SYNC
8
SDATA-IN
11
RESET#
15
I2S_MCLK
16
I2S_SCLK
17
I2S_DOUT
18
I2S_LRCK
24
I2S_DIN
19
MIC1-L
20
MIC1-R
47
EAPD/PD
7
DVSS
42
PVSS
49
GND
ALC3226-CG_QFN48_7X7
ALC3226-CG_QFN48_7X7
Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
AVDD2/HVDD(3.3)
LINE1-R/SLEEVE
HPOUT-L/MIC-CAP
AVSS2/HPOUT-L
GPIO0/DMIC-CLK
GPIO1/DMIC-DATA
MONO-OUT/CBP
AVDD1
PVDD2
PVDD1
Sense A
Sense B
LINE1-L/RING2
LINE1-VREFO
HP-OUT-R
SPK-L+
SPK-L-
SPK-R+
SPK-R-
PCBEEP
DMIC1/GPIO2
GPIO3
CBP/AVSS2
LDO-CAP
JDREF
CPVEE
VREF
MIC1-VREFO
AVSS1
27
38
45
39
13
14
28
29
23
31
33
32
40
41
44
43
12
2
4
46
48
37
35
CBN
36
21
22
34
25
30
26
1 2
10U_0603_6.3V6M
10U_0603_6.3V6M
PBY160808T-600Y-N_2P
PBY160808T-600Y-N_2P
place close to pin38
12
C117
C117
+VDDA_AVDD2
12
RING2 <35>
SLEEVE <35>
+VREFOUT
12
C145 0.1U_0402_25V6C 145 0.1U_0402_25V6
12
C146 0.1U_0402_25V6C 146 0.1U_0402_25V6
DMIC_CLK
1 2
R186@ 0_0402_5%R186@ 0_0402_5%
Place C134 close to Codec
Place close to Codec
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
12
C167
C167
1 2
+5V_RUN_AUDIO
L21
L21
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
12
C116
C116
C150
C150
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
AUD_HP_OUT_L
AUD_HP_OUT_R
EN_I2S_NB_CODEC# <36>
12
C169
C169
12
SLEEVE/RING2 please keep 40 mils trace width
1 2
R194@ 10K_0402_5%R194@ 10K_0402_5%
1 2
R153@ 10K_0402_5%R153@ 10K_0402_5%
1 2
R147 1K_0402_5%R147 1K_0402_5%
1 2
R151 1K_0402_5%R151 1K_0402_5%
DMIC_CLK <22>
DMIC0 <22>
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
20K_0402_1%
20K_0402_1%
12
C138
C138
R39
R39
+3.3V_RUN_AUDIO
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
12
C128
C128
C129
C129
AUD_HP_OUT_L <35>
AUD_HP_OUT_R <35>
10U_0603_6.3V6M
10U_0603_6.3V6M
12
C140
C140
12
place close to pin45place close to pin39
12
SPKR <12>
BEEP <37>
+5V_RUN_AUDIO
0_0603_5%
0_0603_5%
R140@
R140@
0.1U_0402_25V6
0.1U_0402_25V6
12
C123
C123
0_0805_5%
0_0805_5%
12
R130@
R130@
10U_0603_6.3V6M
10U_0603_6.3V6M
C122
C122
RING2
SLEEVE
+VREFOUT
DMIC_CLK
1 2
1 2
+VREFOUT
R1872.2K_0402_5% R 1872.2K_0402_5%
R1972.2K_0402_5% R 1972.2K_0402_5%
1U_0603_10V4Z
1U_0603_10V4Z
12
@
@
C131
C131
22P_0402_50V8J
22P_0402_50V8J
12
@
@
C130
C130
place close to pin2
Place closely to Pin 13.
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
A A
Place closely to Pin 14
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Q20A
Q20A
AUD_SENSE_A
2
39.2K_0402_1%
39.2K_0402_1%
12
R152
R152
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
34
Q20B
Q20B
6
1
5
0.1U_0402_25V6
0.1U_0402_25V6
12
C137
C137
Add for solve pop noise and de tect issue
AUD_SENSE_B
39.2K_0402_1%
39.2K_0402_1%
20K_0402_1%
20K_0402_1%
12
12
R156
R156
R157
6
1
R157
34
5
Q21B
Q21B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
100K_0402_5%
100K_0402_5%
12
R159
R159
+3.3V_RUN_AUDIO +3.3V_RUN_AUDIO
100K_0402_5%
100K_0402_5%
12
R158
R158
2
Q21A
Q21A
10U_0603_6.3V6M
10U_0603_6.3V6M
12
C408@
C408@
DOCK_MIC_DET <36>DOCK_HP_DET<36>
AUD_HP_NB_SENSE <35,36>
place at AGND and DGND plane
1 2
C141@ 0.1U_0402_25V6C 141@ 0. 1U_0402_25V6
1 2
C142@ 0.1U_0402_25V6C 142@ 0. 1U_0402_25V6
1 2
C144@ 0.1U_0402_25V6C 144@ 0. 1U_0402_25V6
SLEEVE
+RTC_CELL
100K_0402_5%
100K_0402_5%
12
R202
34
Q123B
Q123B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
R202
5
6
2
1
Q123A
Q123A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1 2
1 2
PCH_AZ_CODEC_RST#
AUD_NB_MUTE#
R213@ 0_0402_5%R213@ 0_0402_5%
R220@ 0_0402_5%R220@ 0_0402_5%
Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5
PJP4@
PJP4@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
VOUT1
VOUT1
VOUT2
GPAD
+5V_RUN_AUDIO
14
13
12
CT1
11
GND
10
CT2
9
8
15
1 2
C188 0.1U_0402_10V7K@C188 0.1U_0402_10V7K@
1 2
C147 470P_0402_50V7KC147 470P_0402_50V7K
1 2
C148 1000P_0402_50V7KC148 1000P_0402_50V7K
+3.3V_RUN_AUDIO
0.1U_0402_10V7K
0.1U_0402_10V7K
@ C139
@
12
C139
U18
U18
+5V_ALW
RUN_ON<36,37,39>
1 2
R154@ 0_0402_5%R154@ 0_0402_5%
+3.3V_ALW
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
VIN27VOUT2
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Codec _ALC3226
Codec _ALC3226
Codec _ALC3226
LA-9591P
LA-9591P
LA-9591P
26 58Friday, May 17, 2013
26 58Friday, May 17, 2013
26 58Friday, May 17, 2013
0.4
0.4
0.4
5
D D
+3.3V_RUN
1 2
R163 100K_0402_5%R163 100K_0402_5%
1 2
R164 100K_0402_5%R164 100K_0402_5%
1 2
R165 100K_0402_5%R165 100K_0402_5%
R167 1M_0402_5%R167 1M _0402_5%
1 2
R168 5.1M _0402_5%R168 5.1M_0402_5%
C C
B B
12
mDP_AUX#_C
mDP_HPD
mDP_AUX_C
mDP_CA_DET
DPB_MB_P14
4
+3.3V_RUN
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
12
12
C151
C151
C152
C152
DOCKED<21,28,32,36>
DDI2_LANE_N0<10>
DDI2_LANE_P0<10>
DDI2_LANE_N1<10>
DDI2_LANE_P1<10>
DDI2_LANE_N2<10>
DDI2_LANE_P2<10>
DDI2_LANE_N3<10>
DDI2_LANE_P3<10>
CPU_DPC_AUX#<10>
CPU_DPC_AUX<10>
DPC_HPD<10>
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
12
C154
C154
C153@
C153@
DOCKED
DOCKED
U19
U19
12
VDD
21
VDD
34
VDD
2
GPU_SEL
3
D0-
4
D0+
6
D1-
7
D1+
8
D2-
9
D2+
10
D3-
11
D3+
13
AUX-
14
AUX+
5
AUX_HPD_SEL
18
HPD
1
GND
17
GND
22
GND
43
HGND
PI3VDP12412ZHEX_TQFN42_9X3P5~D
PI3VDP12412ZHEX_TQFN42_9X3P5~D
DOCKED
function
1
Dock
0
mini DP
AUX/DDC SW for DPC to Mini DP
U49
U49
1
mDP_AUX
C174 0.1U_0402_10V7KC174 0.1U_0402_10V7K
mDP_AUX#
C175 0.1U_0402_10V7KC175 0.1U_0402_10V7K
12
SW_mDP_AUX_C
mDP_AUX_C
12
SW_mDP_AUX#_C
mDP_AUX#_C
BE0
2
A0
3
B0
4
BE1
5
A1
6
B1
7
GND
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
+3.3V_RUN
100K_0402_5%
100K_0402_5%
12
R67
R67
VCC
BE3
BE2
D0-A
D0+A
D1-A
D1+A
D2-A
D2+A
D3-A
D3+A
AUX-A
AUX+A
HPD_A
D0-B
D0+B
D1-B
D1+B
D2-B
D2+B
D3-B
D3+B
AUX-B
AUX+B
HPD_B
A3
B3
A2
B2
3
42
41
40
39
38
37
36
35
24
23
16
33
32
31
30
29
28
27
26
19
20
15
25
OE
R161 4.7K_0402_5%R161 4.7K_0402_5%
14
13
12
11
10
9
8
mDP_LANE_N0
mDP_LANE_P0
mDP_LANE_N1
mDP_LANE_P1
mDP_LANE_N2
mDP_LANE_P2
mDP_LANE_N3
mDP_LANE_P3
mDP_AUX#
mDP_AUX
mDP_HPD
+3.3V_RUN
C163 0.1U_0402_10V7KC163 0.1U_04 02_10V7K
C164 0.1U_0402_10V7KC164 0.1U_04 02_10V7K
C165 0.1U_0402_10V7KC165 0.1U_04 02_10V7K
C166 0.1U_0402_10V7KC166 0.1U_04 02_10V7K
C168 0.1U_0402_10V7KC168 0.1U_04 02_10V7K
C170 0.1U_0402_10V7KC170 0.1U_04 02_10V7K
C172 0.1U_0402_10V7KC172 0.1U_04 02_10V7K
C173 0.1U_0402_10V7KC173 0.1U_04 02_10V7K
DP12412_N0 <21>
DP12412_P0 <21>
DP12412_N1 <21>
DP12412_P1 <21>
DP12412_N2 <21>
DP12412_P2 <21>
DP12412_N3 <21>
DP12412_P3 <21>
DP12412_AUX# <21>
DP12412_AUX <21>
DP12412_HPD <21>
12
C411
C411
1 2
0.1U_0402_25V6
0.1U_0402_25V6
CPU_DPC_CTRLCLK <10>
CPU_DPC_CTRLDAT <10>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+3.3V_RUN
mDP_LANE_N0_C
mDP_LANE_P0_C
mDP_LANE_N1_C
mDP_LANE_P1_C
mDP_LANE_N2_C
mDP_LANE_P2_C
mDP_LANE_N3_C
mDP_LANE_P3_C
2
+3.3V_RUN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
@
@
C383
C383
mDP_AUX#_C
mDP_LANE_N2_C
mDP_AUX_C
mDP_LANE_P2_C
mDP_LANE_N3_C
mDP_LANE_N1_C
mDP_LANE_P3_C
mDP_LANE_P1_C
DPB_MB_P14
mDP_LANE_N0_C
mDP_CA_DET
mDP_LANE_P0_C
mDP_HPD
1
IN
GND2OUT
3
AP2337SA-7 SOT-23
AP2337SA-7 SOT-23
U50
U50
+VDISPLAY_VCC
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
0.01U_0402_16V7K
0.01U_0402_16V7K
C171
C171
12
JmDP1 CONN@
JmDP1 CONN@
DP_PWR
GND
AUX_CH_N
GND4
LANE2_N
GND3
AUX_CH_P
GND2
LANE2_P
GND1
GND
GND
LANE3_N
LANE1_N
LANE3_P
LANE1_P
GND
GND
CONFIG2
LANE0_N
CONFIG1
LANE0_P
HOT_PLUG
GND
ACON_MAR2F-20K1800
ACON_MAR2F-20K1800
24
23
22
21
mDP_CA_DET#
BSS138W-7-F_SOT323-3
BSS138W-7-F_SOT323-3
1
D
D
mDP_CA_DET
A A
2
Q31
Q31
G
G
S
S
3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Mini DP
Mini DP
Mini DP
LA-9591P
LA-9591P
LA-9591P
27 58Friday, May 17, 2013
27 58Friday, May 17, 2013
27 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
LANCLK_REQ#<12,7>
CLK_PCIE_LAN<7>
CLK_PCIE_LAN#<7>
PCIE_PRX_GLANTX_P3<11>
+3.3V_LAN
1 2
D D
C C
B B
Layout Notice : Place bead as
close PI3L500 as possible
A A
R171@ 10K_0402_5%R171@ 10K_0402_5%
R172@ 10K_0402_5%R172@ 10K_0402_5%
R176 4.7K_0402_5%@ R176 4.7K_0402_5%@
PM_LANPHY_ENABLE<12>
+3.3V_RUN
R331 10K_0402_5%R 331 10K_0402_5%
LAN_TX0+ LAN_TX0+R
LAN_TX0- LAN_TX0-R
LAN_TX1+ LAN_TX1+R
LAN_TX1- LAN_TX1-R
LAN_TX2+ LAN_TX2+R
LAN_TX2- LAN_TX2-R
LAN_TX3+ LAN_TX3+R
LAN_TX3- LAN_TX3-R
DOCKED
TP_LAN_JTAG_TMS
1 2
TP_LAN_JTAG_TCK
12
LAN_WAKE#_R
1 2
R180 0_0402_5%@ R180 0_0402_5%@
12
LAN_RST#
LAN_RST#<12>
PLTRST_LAN#<9>
1 2
L27EMC@ 12NH_0603CS-120EJTS_5%L27EMC@ 12NH_0603CS-120EJTS_5%
1 2
L28EMC@ 12NH_0603CS-120EJTS_5%L28EMC@ 12NH_0603CS-120EJTS_5%
1 2
L29EMC@ 12NH_0603CS-120EJTS_5%L29EMC@ 12NH_0603CS-120EJTS_5%
1 2
L30EMC@ 12NH_0603CS-120EJTS_5%L30EMC@ 12NH_0603CS-120EJTS_5%
1 2
L31EMC@ 12NH_0603CS-120EJTS_5%L31EMC@ 12NH_0603CS-120EJTS_5%
1 2
L32EMC@ 12NH_0603CS-120EJTS_5%L32EMC@ 12NH_0603CS-120EJTS_5%
1 2
L33EMC@ 12NH_0603CS-120EJTS_5%L33EMC@ 12NH_0603CS-120EJTS_5%
1 2
L34EMC@ 12NH_0603CS-120EJTS_5%L34EMC@ 12NH_0603CS-120EJTS_5%
DOCKED<21,27,32,36>
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
1: TO DOCK
0: TO RJ45
+3.3V_LAN
12
12
33P_0402_50V8J
33P_0402_50V8J
C189
C189
1 2
+3.3V_RUN
1
B
2
A
U20
@ U20
@
+3.3V_LAN
0.1U_0402_25V6
0.1U_0402_25V6
12
12
C192
C192
DOCKED
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
PCIE_PRX_GLANTX_N3<11>
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
5
3
PCIE_PTX_GLANRX_P3<11>
PCIE_PTX_GLANRX_N3<11>
R173@
R173@
R182@
R182@
25MHZ_18PF_7V25000034
25MHZ_18PF_7V25000034
0.1U_0402_10V7K
0.1U_0402_10V7K
P
G
LAN_SMBDATA<7>
LAN_WAKE#<12,37>
SMBus Device Address 0xC8
1 2
R183@ 0_0402_5%R183@ 0_0402_5%
Y3
Y3
3
IN
OUT
4
GND
GND
12
R145@ 0_0402_5% R145@ 0_0402_5%
C406@
C406@
12
4
PLT_LAN_RST#
O
LAN ANALOG SWITCH
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
C194
C194
C193
C193
U23
U23
2
A0+
3
A0-
6
A1+
7
A1-
9
A2+
10
A2-
11
A3+
12
A3-
13
SEL
15
LEDA0
16
LEDA1
42
LEDA2
5
PD
43
PAD_GND
PI3L720ZHEX_TQFN42_9X3P5~D
PI3L720ZHEX_TQFN42_9X3P5~D
4
U21
U21
RES_BIAS
R185
R185
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
2
LANWAKE_N
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTAL_OUT
10
XTAL_IN
30
TEST_EN
12
RBIAS
WGI218LM-SLK3A-B1_QFN48_6X6~D
WGI218LM-SLK3A-B1_QFN48_6X6~D
SW_LAN_TX0+ <35>
SW_LAN_TX0- <35>
SW_LAN_TX1+ <35>
SW_LAN_TX1- <35>
SW_LAN_TX2+ <35>
SW_LAN_TX2- <35>
SW_LAN_TX3+ <35>
SW_LAN_TX3- <35>
DOCK_LOM_TRD0+ <34>
DOCK_LOM_TRD0- <34>
DOCK_LOM_TRD1+ <34>
DOCK_LOM_TRD1- <34>
DOCK_LOM_TRD2+ <34>
DOCK_LOM_TRD2- <34>
DOCK_LOM_TRD3+ <34>
DOCK_LOM_TRD3- <34>
DOCK_LOM_ACTLED_YEL# <34>
DOCK_LOM_SPD100LED_ORG# <34>
DOCK_LOM_SPD10LED_GRN# <34>
1 2
R169 0_0402_5%@R 169 0_0402_5%@
C179 0.1U_0402_10V7KC179 0. 1U_0402_10V7K
C176 0.1U_0402_10V7KC176 0. 1U_0402_10V7K
1 2
C178 0.1U_0402_10V7KC178 0. 1U_0402_10V7K
1 2
C181 0.1U_0402_10V7KC181 0. 1U_0402_10V7K
4
VDD
LAN_DISABLE#_R<36>
T92@ PAD~DT92@ PAD~D
T93@ PAD~DT93@ PAD~D
12
1 2
1
VDD
VDD
R174 0_0402_5%@ R174 0_0402_5%@
R177 0_0402_5%@ R177 0_0402_5%@
R179 0_0402_5%@ R179 0_0402_5%@
R206
R206
1M_0402_5%
1M_0402_5%
33P_0402_50V8J
33P_0402_50V8J
C190
C190
B0+
B0-
B1+
B1-
B2+
B2-
B3+
B3-
LEDB0
LEDB1
LEDB2
C0+
C0-
C1+
C1-
C2+
C2-
C3+
C3-
LEDC0
LEDC1
LEDC2
1 2
1 2
1 2
38
37
34
33
29
28
25
24
17
18
41
36
35
32
31
27
26
23
22
19
20
40
LAN_SMBCLK<7>
1
2
100K_0402_5%
100K_0402_5%
12
R25@
R25@
8
14
21
30
39
VDD
VDD
VDD
VDD
LANCLK_REQ#_R
PLT_LAN_RST#
12
PCIE_PRX_GLANTX_P3_C
12
PCIE_PRX_GLANTX_N3_C
PCIE_PTX_GLANRX_P3_C
PCIE_PTX_GLANRX_N3_C
LAN_SMBCLK_R
LAN_SMBDATA_R
LAN_WAKE#_R
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
XTALOXTALO_R
XTALI
LAN_TEST_EN
3.01K_0402_1%
3.01K_0402_1%
1K_0402_5%
1K_0402_5%
12
12
R184
R184
SW_LAN_TX0+
SW_LAN_TX0-
SW_LAN_TX1+
SW_LAN_TX1-
SW_LAN_TX2+
SW_LAN_TX2-
SW_LAN_TX3+
SW_LAN_TX3-
SW_ACTLED_YEL#
SW_100_ORG#
SW_10_GRN#
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#
PCIE
PCIE
JTAG LED
JTAG LED
MDI_PLUS0
MDI_MINUS0
MDI_PLUS1
MDI_MINUS1
MDI_PLUS2
MDI
MDI
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
RSVD_VCC3P3_1
SMBUS
SMBUS
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD0P9_47
VDD0P9_46
VDD0P9_37
VDD0P9_43
VDD0P9_11
VDD0P9_40
VDD0P9_22
VDD0P9_16
3
SVR_EN_N
VDD3P3_IN
VDD3P3_4
VDD0P9_8
CTRL0P9
VSS_EPAD
13
14
17
18
20
21
23
24
6
VCT_LAN_R1
1
+RSVD_VCC3P3_1
5
4
15
19
29
47
46
37
43
11
40
22
16
8
7
REGCTL_PNP10
49
LAN_TX0+
LAN_TX0-
LAN_TX1+
LAN_TX1-
LAN_TX2+
LAN_TX2-
LAN_TX3+
LAN_TX3-
+3.3V_LAN_OUT
+0.9V_LAN
SIO_SLP_LAN#<36,9>
3.3V_HDD_EN<12>
1U_0603_10V6K
1U_0603_10V6K
12
SW_ACTLED_YEL#
SW_100_ORG#
12
12
R181@ 0_0603_5%R181@ 0_0603_5%
Pin 6 is SVR_EN in Clarkville
C182
C182
R196@ 0_0402_5%R196@ 0_0402_5%
1 2
R129@ 0_0402_5%R129@ 0_0402_5%
Q32A
Q32A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
2
Q32B
Q32B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
5
R175 0_0402_5%@R 175 0_0402_5%@
R178 4. 7K_0402_5%R 178 4.7K_0402_5%
+3.3V_LAN
12
12
+5V_ALW
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
6
MASK_BASE_LEDS#
34
MASK_BASE_LEDS#
2
+3.3V_LAN
+3.3V_ALW
REGCTL_PNP10
1
2
3
4
5
6
LAN_ACTLED_YEL# <35>
MASK_BASE_LEDS# <40>
LED_100_ORG# <35>
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
12
12
C183
C183
Note:
+1.0V_LAN will work at 0.95V to 1.15V
U22
U22
VIN1
VOUT1
VIN1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VOUT2
VIN27VOUT2
GPAD
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
+3.3V_LAN
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
5
1
P
B
4
O
2
A
G
U24
U24
NL17SZ08DFT2G_SSOP5~D
NL17SZ08DFT2G_SSOP5~D
3
L264.7UH_CBC2012T4R7M_20% L264.7UH_CBC2012T4R7M_20%
0.1U_0402_10V7K
0.1U_0402_10V7K
12
Place C177, C180 and L26 close to U21
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
C184
C184
14
13
12
11
10
9
8
15
C198@
C198@
0.1U_0402_10V7K
12
12
C185
C185
+3.3V_LAN
C426 0.1U_0402_10V7KC426 0.1U_0402_10V7K
C407 470P_0402_50V7KC407 470P_0402_50V7K
C429 470P_0402_50V7KC429 470P_0402_50V7K
WLAN_LAN_DISB# <36>
SW_10_GRN#
C186
C186
+0.9V_LAN
10U_0603_6.3V6M
10U_0603_6.3V6M
C180
C180
C177
C177
12
+0.9V_LAN
22U_0805_6.3V6M
22U_0805_6.3V6M
12
C187
C187
1 2
1 2
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
@C428
@
12
C428
Q33A
Q33A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
2
Q33B
Q33B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
5
+3.3V_HDD
6
MASK_BASE_LEDS#
34
1
LED_10_GRN# <35>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
LAN
LAN
LAN
LA-9591P
LA-9591P
LA-9591P
1
28 58Friday, May 17, 2013
28 58Friday, May 17, 2013
28 58Friday, May 17, 2013
0.4
0.4
0.4
5
D D
PJP5@
PJP5@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
PCH_TPM_LPC_EN<7>
SP_TPM_LPC_EN<36>
C C
4
+3.3V_RUN_TPM+3.3V_RUN
R198
R198
R193
@ 0_0402_5%
R193
@ 0_0402_5%
LPC_LAD0<36,37,7>
LPC_LAD1<36,37,7>
LPC_LAD2<36,37,7>
LPC_LAD3<36,37,7>
CLK_PCI_TPM_TCM<7>
LPC_LFRAME#<36,37,7>
PCH_PLTRST#_EC<31,36,37,9>
IRQ_SERIRQ<12,36,37>
CLKRUN#<12,36,37,9>
+3.3V_RUN_TPM
1 2
1 2
0.1U_0402_25V6
0.1U_0402_25V6
12
C200@
C200@
10_0402_5%@
10_0402_5%@
SP_TPM_LPC_EN_R
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
IRQ_SERIRQ
CLKRUN#
3
4700P_0402_25V7K
4700P_0402_25V7K
12
C201
C201
ATMEL TPM for E4
U25
U25
5
SB3V
28
LPCPD#
26
LAD0
23
LAD1
20
LAD2
17
LAD3
21
LCLK
22
LFRAME#
16
LRESET#
27
SERIRQ
15
CLKRUN#
1
ATEST_1
2
ATEST_2
3
ATEST_3
AT97SC320412-ABF _TSSOP28
AT97SC320412-ABF _TSSOP28
VCC_0
VCC_1
VCC_2
V_BAT
NBO_13
NBO_14
GPIO6
TESTBI
TESTI
NC_7
GND_4
GND_11
GND_18
GND_25
12
2200P_0402_50V7K
2200P_0402_50V7K
C202
C202
+3.3V_RUN_TPM
2200P_0402_50V7K
2200P_0402_50V7K
12
10
19
24
12
13
14
6
9
8
7
4
11
18
25
2200P_0402_50V7K
2200P_0402_50V7K
C203
C203
12
2
0.1U_0402_25V6
0.1U_0402_25V6
C384@
C384@
C204
C204
12
1
USH CONN
JUSH1
+3.3V_SUS
B B
1 2
R190 2.2K_0402_5%R190 2.2K_0402_5%
1 2
R191 2.2K_0402_5%R191 2.2K_0402_5%
1 2
R195 1M_0402_5%R195 1M_0402_5%
12
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C208
C208
USH_SMBCLK
USH_SMBDAT
USH_PWR_STATE#
0.1U_0402_25V6
0.1U_0402_25V6
12
USBP4-<11>
USBP4+<11>
USH_SMBCLK<37>
USH_SMBDAT<37>
BCM5882_ALERT#<36>
+3.3V_SUS
+3.3V_RUN
+5V_RUN
PLTRST_USH#<9>
USH_PWR_STATE#<36>
+3.3V_SUS+3.3V_RUN+5V _RUN
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C207
C207
12
@
@
C206
C206
CONTACTLESS_DET#<10>
USH_DET#<12>
JUSH1
22
GND2
21
GND1
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
CONN@
CONN@
ACES_50506-02041-P01
ACES_50506-02041-P01
Close to JUSH1
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USH & TPM
USH & TPM
USH & TPM
LA-9591P
LA-9591P
LA-9591P
29 58Friday, May 17, 2013
29 58Friday, May 17, 2013
29 58Friday, May 17, 2013
1
0.4
0.4
0.4
A
B
C
D
E
+3.3V_RUN
1 2
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
12
C211
C211
C210
C210
+1.2V_LDO
1 2
L36
L36
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
12
C223
C223
@U26
@
L35 BLM15AG601SN1D_2PL35 BLM15AG601SN1D_2P
0.1U_0402_25V6
0.1U_0402_25V6
C212
C212
0.1U_0402 _25V6
0.1U_0402 _25V6
0.1U_0402_25V6
0.1U_0402_25V6
C217
C217
C218
C218
1 2
1 2
+1.2V_LDO_AIN
0.1U_0402 _25V6
0.1U_0402 _25V6
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
C231
C231
C230
C230
1 2
1 2
1 2
PCIE_PTX_MMIRX_P5<11>
PCIE_PTX_MMIRX_N5<11>
PCIE_PRX_MMITX_P5<11>
PCIE_PRX_MMITX_N5<11>
+3.3V_RUN
100K_0402_5%
100K_0402_5%
12
R212
R212
IO_LDOSEL
100K_040 2_5%
100K_040 2_5%
12
R214@
R214@
1 2
R443 0_0402_5%@R443 0_0402_5%@
+3.3V_RUN
C341@
C341@
5
0.1U_0402_25V6
0.1U_0402_25V6
1
P
B
4
O
2
A
U26
G
3
+3.3V_RUN
0.1U_0402 _25V6
0.1U_0402 _25V6
1 1
C210 close to U27.42
C211 C212 close to
U27.23
2 2
3 3
MEDIACARD_RST#<12>
4 4
12
+1.2V_LDO
1 2
BLM15AG601SN1D_2P
BLM15AG601SN1D_2P
PLTRST_MMI#<9>
A
C215 close to U27.9
C213 C214 close to
U27.35
+3.3V_RUN_AIN
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
12
+3.3V_RUN
0.1U_0402 _25V6
0.1U_0402 _25V6
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
C224
C224
1 2
1 2
0.1U_0402 _25V6
0.1U_0402 _25V6
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C233
C233
C232
C232
1 2
1 2
C235 0.1U_0402_10V7KC235 0.1U_0402_10V7K
1 2
1 2
C236 0.1U_0402_10V7KC236 0.1U_0402_10V7K
1 2
C237 0.1U_0402_10V7KC237 0.1U_0402_10V7K
1 2
C238 0.1U_0402_10V7KC238 0.1U_0402_10V7K
12
100K_0402_5%
100K_0402_5%
R27@
R27@
0.1U_0402 _25V6
0.1U_0402 _25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
12
C214
C214
C215
1 2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C225
C225
CLK_PCIE_MMI#<7>
CLK_PCIE_MMI<7>
MEDIACARD_IRQ#<12>
MMICLK_REQ#<7>
PE_RST#
1 2
B
C215
0.1U_0402_25V6
0.1U_0402_25V6
C226
C226
1 2
R205 191_0402_1%R205 191_0402_1%
PCIE_PTX_MMIRX_P5_C
PCIE_PTX_MMIRX_N5_C
PCIE_PRX_MMITX_P5_C
PCIE_PRX_MMITX_N5_C
PE_RST#
IO_LDOSEL
SD/MMCDAT0 SD/MMCDAT0_D
SD/MMCDAT1 SD/MMCDAT1_D
SD_UHS2_D0P SD_UHS2_D0P_D
SD_UHS2_D0N SD_UHS2_D0N_D
SD_UHS2_D1P SD_UHS2_D1P_D
SD_UHS2_D1N SD_UHS2_D1N_D
U27
U27
9
PE_33VCCAIN
27
UHSII_33VCCAIN/NC
42
SD_33VCCD
23
SD_SKT_33VIN
13
AUX _33VIN
11
MAIN_LDO_VIN
10
MAIN_LDO_12VOUT
41
CORE_12VCCD
36
UHSII_12VCCAIN/NC
31
UHSII_12VCCAIN/NC
28
UHSII_12VCCAIN/NC
1
PE_12VCCAIN
4
PE_REXT
please routing daisy chain
1. from U27.38 (SD_D0) -> U27.32 (SD_RCLK_P) -> L46.4
2. From U27.37 (SD_D1) -> U27.33 (SD_RCLK_N) -> L46.1
PE_REXT
6
PE_RXP
5
PE_RXM
7
PE_TXP
8
PE_TXM
2
PE_REFCLKM
3
PE_REFCLKP
15
PE_RST#_GATE#
14
MAIN_LDO_EN
16
DEV_WAKE#
17
CLKREQ#
18
IO0_LDOSEL
OZ777FJ2LN_QFN48_6X6
OZ777FJ2LN_QFN48_6X6
R231,R297,R306,R315,R333,R337 for EMI solution
1 2
R231 0_0402_5%@R231 0_0402_5%@
L46
@L46
@
4
4
1
1
DLW21SN900SQ2L-0805_4P
DLW21SN900SQ2L-0805_4P
1 2
R297 0_0402_5%@R297 0_0402_5%@
1 2
R306 0_0402_5%@R306 0_0402_5%@
L47
@L47
@
4
4
1
1
DLW21SN900SQ2L-0805_4P
DLW21SN900SQ2L-0805_4P
1 2
R315 0_0402_5%@R315 0_0402_5%@
R333 0_0402_5%@R333 0_0402_5%@
1 2
L48
@L48
@
1
1
4
4
DLW21SN900SQ2L-0805_4P
DLW21SN900SQ2L-0805_4P
R337 0_0402_5%@R337 0_0402_5%@
1 2
OZ777FJ2LN
OZ777FJ2LN
3
3
2
2
3
3
2
2
2
2
3
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
AUX_LDO_CAP
SD_IO_LDO_CAP
SD_SKT_33VOUT
SD_SKT_18VOUT
SD_RCLK_M/NC
SD_RCLK_P/NC
SD_REXT/NC
+3.3V_RUN_CARD
Near to JSD1
SD_WPI
SD_CD#
SD_CLK
SD_CMD
MMC_D7
MMC_D6
MMC_D5
MMC_D4
SD_D3
SD_D2
SD_D1
SD_D0
SD_D1P/NC
SD_D1M/NC
SD_D0M/NC
SD_D0P/NC
LED#
GND
0.1U_0402_25V6
0.1U_0402_25V6
12
C239
C239
12
+AUX_LDO
25
+SD_IO_LDO
22
24
20
21
43
45
39
40
44
46
47
48
37
38
29
30
32
33
34
35
26
19
49
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
@
@
12
C240
C240
+3.3V_RUN_CARD
+1.8V_RUN_CARD
SDWP
SD/MMCCD#
SD/MMCCLK_R
SD/MMCCMD
SD/MMCDAT3 SD/MMCDAT3_R
SD/MMCDAT2 SD/MMCDAT2_R
SD/MMCDAT1
SD/MMCDAT0
SD_UHS2_D1P
SD_UHS2_D1N
SD_UHS2_D0N
SD_UHS2_D0P
R211 4.7K_0402_1%R211 4.7K_0402_1%
+1.8V_RUN_CARD
R230 EMC@ 10_0402_5%R230 EMC@ 10_0402_5%
R410@ 0_0402_5%R410@ 0_0402_5%
R341@ 0_0402_5%R341@ 0_0402_5%
1 2
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
12
12
C246
C246
1 2
1 2
1 2
EMI solution for SD card
C247
C247
D
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
C220
C220
1 2
+3.3V_RUN_CARD
+1.8V_RUN_CARD
1M_0402_5%
1M_0402_5%
12
R493
R493
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
1U_0402_6.3V6K
1 2
SD/MMCCLK
1U_0402_6.3V6K
2
C222
C222
C221@
C221@
1
5P_0402_ 50V8C
5P_0402_ 50V8C
@
@
12
C255
C255
0.1U_0402 _25V6
0.1U_0402 _25V6
C216
C216
1 2
EMI depop location
+3.3V_RUN_CARD +1.8V_RUN_CARD
0.1U_0402_25V6
0.1U_0402 _25V6
0.1U_0402 _25V6
12
C227@
C227@
0.1U_0402_25V6
12
12
C229@
C229@
C227 near U27.22 C228 C229 near U27.24
JSD1
CONN@JSD1
CONN@
4
VDD/VDD1
14
VDD2
SD/MMCCMD
SD/MMCCLK
SD/MMCCD#
0.1U_0402 _25V6
0.1U_0402 _25V6
C256
C256
SDWP
SD/MMCDAT0_D
SD/MMCDAT1_D
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P_D
SD_UHS2_D0N_D
SD_UHS2_D1P_D
SD_UHS2_D1N_D
12
2
CMD
5
CLK
18
CARD DETECT
19
WRITE PROTEC
7
DAT0/RCLK+
8
DAT1/RCLK-
9
DAT2
1
CD/DAT3
11
D0+
12
DO-
16
D1+
15
D1-
3
VSS1
6
VSS2
10
VSS3
13
VSS4
17
VSS5
ALPS_SCDADA0101_NR
ALPS_SCDADA0101_NR
GND1
GND2
GND3
GND4
GND5
GND6
GND7
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Card Reader
Card Reader
Card Reader
LA-9591P
LA-9591P
LA-9591P
E
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
C228@
C228@
20
21
22
23
24
25
26
0.4
0.4
30 58Friday, May 17, 2013
30 58Friday, May 17, 2013
30 58Friday, May 17, 2013
0.4
C213
C213
C219
C219
0.1U_0402_25V6
0.1U_0402_25V6
C234
C234
MEDIACARD_PWREN<12>
12
5
4
3
2
1
Mini WWAN/GPS/LTE/mSATA/PP H=4
+3.3V_mSATA_WW AN+3.3V_mSATA_WW AN
JMINI2
JMINI2
PCIE_WAKE#<37>
MINI1CLK_REQ#<12,7>
CLK_PCIE_MINI1#<7>
D D
SATA_PTX_MSATARX_N3<6>
SATA_PTX_MSATARX_P3<6>
+3.3V_mSATA_WW AN
DDR_XDP_WAN_SMBCLK<18,19,25,7,9>
C C
DDR_XDP_WAN_SMBDAT<18,19,25,7,9>
CLK_PCIE_MINI1<7>
SATA_PRX_MSATATX_P3<6>
SATA_PRX_MSATATX_N3<6>
1 2
C244 0.1U_ 0402_10V7KC24 4 0.1U_0402_10V7K
1 2
C245 0.1U_ 0402_10V7KC24 5 0.1U_0402_10V7K
1 2
mSATA_DEVSLP
R160@ 10K_0402_5%R160@ 10K_0402 _5%
PCIE_WAKE#
MINI1CLK_REQ#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
SATA_PRX_MSATATX_P3
SATA_PRX_MSATATX_N3
SATA_PTX_mSATARX_N3_C
SATA_PTX_mSATARX_P3_C
HW_GPS_DISABLE2#<36>
+3.3V_mSATA_WW AN
12
R218@ 0_0402_5%R218@ 0_0402_5%
12
R219@ 0_0402_5%R219@ 0_0402_5%
LCN_DAN08-52406-0500
LCN_DAN08-52406-0500
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
12
12
R217@
R217@
R216@
R216@
WWAN_SM BCLK
WWAN_SM BDAT
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
GND153GND2
CONN@
CONN@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
+3.3V_mSATA_WW AN
0.047U_0402_16V4Z
0.047U_0402_16V4Z
12
12
C248
C248
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
MINI_CARD_RST#
WWAN_SM BCLK
WWAN_SM BDAT
LED_WWAN_ OUT#
33P_0402_50V8J
33P_0402_50V8J
0.047U_0402_16V4Z
0.047U_0402_16V4Z
12
C250
C250
C249
C249
+SIM_PWR
WWAN_RADIO_DIS# <36>
USBP6- <11>
USBP6+ <11>
mSATA_DEVSLP <12>
22U_0805_6.3V6M
22U_0805_6.3V6M
33P_0402_50V8J
33P_0402_50V8J
12
12
C251
C251
C252
C252
MINI2CLK_REQ#<12,7>
CLK_PCIE_MINI2#<7>
CLK_PCIE_MINI2<7>
EC5048_TX<36,37>
MSCLK<37>
PCIE_PRX_WLANTX_N4<11>
PCIE_PRX_WLANTX_P4<11>
1 2
PCIE_PTX_WLANRX_N4<11>
PCIE_PTX_WLANRX_P4<11>
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
3@
3@
12
12
+
+
+
+
C254@
C254@
C253
C253
WLAN_RADIO_DIS#<36>
WIGIG60GHZ_DIS#<36>
BT_RADIO_DIS#< 36>
C242 0.1U_0402_10 V7KC24 2 0.1U_0402_10V7K
1 2
C243 0.1U_0402_10 V7KC24 3 0.1U_0402_10V7K
PCH_CL_CLK1<7>
PCH_CL_DATA1<7>
PCH_CL_RST1#<7 >
1 2
R215 0_0402_5%@ R215 0_0402_5%@
1 2
D12
D12
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
1 2
R224 0_0402_5%@ R224 0_0402_5%@
1 2
D13
D13
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
1 2
R225 0_0402_5%@ R225 0_0402_5%@
1 2
D14
D14
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
CPPE#<12>
1 2
R223@ 0_0402_5%R223@ 0_0402_5%
Mini WLAN/WIiGi/BT H=4
+3.3V_WLAN +3.3V_WLAN
JMINI1
PCIE_WAKE#
PCIE_PRX_WLANTX_N4
PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N4_C
PCIE_PTX_WLANRX_P4_C
BT_RADIO_DIS#_R
WLAN_RADIO_DIS#_R
WIGIG60GHZ_DIS#_R
BT_RADIO_DIS#_R
JMINI1
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
GND153GND2
LCN_DAN08-52406-0500
LCN_DAN08-52406-0500
CONN@
CONN@
PWR
Rail
+3.3V
+3.3Vaux
Voltage
Tolerance
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
+3.3V_WLAN
12
+-9%
+-9%
MSDATA
4700P_0402_25V7K
4700P_0402_25V7K
WLAN_RADIO_DIS#_R
MINI_CARD_RST#
WIGIG60GHZ_DIS#_R
WIMAX_LED#
WLAN_LED#
BT_LED#
1 2
R222@ 0_0402 _5%R222@ 0_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
12
12
C257@
C257@
C258
C258
C259
C259
1 2
Primary Power Aux Power
Peak Normal Normal
1000 750
330 250
C241
C241
1 2
HOST_DEBUG_TX <37>
USBP2- <11>
USBP2+ <11>
CPUSB# <12>
MSDATA <37>
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
C260
C260
C261
C261
1 2
250 (Wake enable)
5 (Not wake enable)
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C262
C262
SIM Card Push-Push
+SIM_PWR
UIM_RESET
1U_0402_6.3V6K
1U_0402_6.3V6K
UIM_CLK
3@
3@
12
C263
B B
A A
C263
UIM_RESET
UIM_VPP
12
33P_0402_50V8J
33P_0402_50V8J
UIM_VPP
UIM_DATA
C264@
C264@
5
33P_0402_50V8J
33P_0402_50V8J
12
C265@
C265@
JSIM1
CONN@
JSIM1
CONN@
1
VCC
2
RST
GND_2
3
CLK
GND_3
4
D+
GND_4
5
GND_1
GND_5
6
VPP
GND_6
7
I/O
GND_7
8
D-
GND_8
9
DET
GND_9
10
COM
T-SOL_159-1000302602
T-SOL_159-1000302602
U28@
U28@
1
2
3 4
SRV05-4.TCT_SOT23-6~D
SRV05-4.TCT_SOT23-6~D
11
12
13
14
15
16
17
18
6
UIM_CLK
5
+SIM_PWR
UIM_DATA
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
12
12
C267@
C267@
C266@
C266@
4
1 2
MCARD_WWAN_P WREN
R50 100K_0402_5%R50 100K_0402_5%
1 2
AUX_EN_WOWL
R51 100K_0402_5%R51 100K_0402_5%
MCARD_WWAN_P WREN<36>
AUX_EN_WOWL< 36>
LED control circuit
+3.3V_WLAN
WIMAX_LED#
WLAN_LED#
BT_LED#
LED_WWAN_ OUT#
2
100K_0402_5%
100K_0402_5%
R229
R229
1 2
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
R227
R227
1 2
1 2
126
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
R228
R228
5
34
Q22B
Q22B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
126
Q22A
Q22A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Q30A
Q30A
+3.3V_mSATA_WW AN
100K_0402_5%
100K_0402_5%
R226
R226
5
1 2
34
Q30B
Q30B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Mini Card
Mini Card
Mini Card
LA-9591P
LA-9591P
LA-9591P
WIRELESS_LED# <36,40>
31 58Friday, May 17, 2013
31 58Friday, May 17, 2013
31 58Friday, May 17, 2013
1
0.4
0.4
0.4
VOUT1
VOUT1
GND
VOUT2
GPAD
1 2
0.1U_0402_25V6
0.1U_0402_25V6
5
P
O
G
3
CT1
CT2
1 2
4
+3.3V_mSATA_WW AN+3.3V_ALW
14
13
12
11
10
9
8
15
C338@
C338@
MINI_CARD_RST#
1 2
C425 0.1U_0402_10V 7K@ C425 0.1U_0 402_10V7K@
1 2
C427
C427
1 2
C409 470P_04 02_50V7KC409 470P_0402_ 50V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
@C422
@
12
C422
100K_0402_5%
100K_0402_5%
12
R26@
R26@
470P_0402_50V7K
470P_0402_50V7K
+3.3V_WLAN
U3
U3
1
VIN1
2
VIN1
3
ON1
+5V_ALW
PCH_PLTRST#_EC<29,36,37,9>
MPCIE_RST#<12,6>
4
5
6
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
U30
@U30
@
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
VBIAS
ON2
VIN2
VIN27VOUT2
R232@ 0_0402_5%R232@ 0_0402_5%
+3.3V_RUN
1
B
2
A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
D D
C C
+3.3V_SUS
12
4
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
12
C419@
C419@
C420
C420
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
12
C415
C415
C418@
C418@
USB3TP3<11>
USB3TN3<11>
USB3RP3<11>
USB3RN3<11 >
USBP5+<11>
USBP5-<11>
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
C417@
C417@
DOCKED<21,27,28,36>
0.1U_0402_25V6
12
12
C414
C414
C416
C416
12
16
20
29
10
32
3
U33
U33
3
VDD
9
VDD
VDD
VDD
VDD
VDD
1
TX+
2
TX-
4
RX+
5
RX-
6
D+
7
D-
8
USB_ID
SS_SEL
HS_SEL
PI3USB3102ZLEX_TQFN32_6X3
PI3USB3102ZLEX_TQFN32_6X3
TX+A
TX-A
RX+A
RX-A
D+A
USB_IDA
TX+B
TX-B
RX+B
RX-B
D+B
USB_IDB
OE#
GND
GND
HGND
2
31
30
27
26
19
18
D-A
17
25
24
23
22
15
14
D-B
13
11
21
28
33
SW_USB3TP3 <33>
SW_USB3TN3 <33>
SW_USB3RP3 <33>
SW_USB3RN3 <33>
SW_USBP5+ <33>
SW_USBP5- <33>
DOCK_USB3TP3 <34>
DOCK_USB3TN3 <34>
DOCK_USB3RP3 <34>
DOCK_USB3RN3 <34>
DOCK_USBP5+ <34>
DOCK_USBP5- <34>
1
check port mapping
DOCKED
B B
function
Dock
1
M/B
0
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB SW
USB SW
USB SW
LA-9591P
LA-9591P
LA-9591P
32 58Friday, May 17, 2013
32 58Friday, May 17, 2013
32 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
+USB_PWR
L37 EMC@
L37 EMC@
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
1
1D+
2
1D-
3
2D+
4
2D-
5
GND
function
Dock
M/B
4
4
1
1
1 2
R235@ 0_0402_5%R235@ 0_0402_5%
1 2
R236@ 0_0402_5%R236@ 0_0402_5%
L38 EMC@
L38 EMC@
4
4
1
1
1 2
R237@ 0_0402_5%R237@ 0_0402_5%
1 2
R239@ 0_0402_5%R239@ 0_0402_5%
SW_USBP0+
SW_USBP0-
SW_USB3RN3<32>
SW_USB3RP3<32>
D D
12
SW_USB3TN3<32>
SW_USB3TP3<32>
C C
+3.3V_ALW
0.1U_0402_25V6
0.1U_0402_25V6
12
C322
C322
B B
DOCKED_LIO_EN<36>
USBP0+<11>
USBP0-<11>
C282 0.1U_0402_10V7KC282 0.1U_0402_10V7K
C283 0.1U_0402_10V7KC283 0.1U_0402_10V7K
SW_USB3TN3_C
12
SW_USB3TP3_C
support APR/SPR/LIO Dock
U36
U36
10
VCC
9
S
8
D+
7
D-
6
OE#
NX3DV221GM_XQFN10U10_2X1P55
NX3DV221GM_XQFN10U10_2X1P55
check port mapping
DOCKED_LIO_EN
1
0
3
3
2
2
3
3
2
2
USB_PWR_SHR_EN#<36>
USB3RN2<11>
USB3RP2<11>
USB3RP3_D+
USB3TN3_D-
USB3TP3_D+
DOCK_USBP0+ <34>
DOCK_USBP0- <34>
1 2
R242@ 0_0402_5%R242@ 0_0402_5%
L40 EMC@
L40 EMC@
4
4
1
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
1 2
R246@ 0_0402_5%R246@ 0_0402_5%
1 2
R247@ 0_0402_5%R247@ 0_0402_5%
SW_USBP5+<32>
SW_USBP5-<32>
SB#
SW_USBP0ÂSW_USBP0+
+5V_ALW
12
3
3
2
2
USB3RN3_D- USB3RN3_D-USB3RN3_D-
USB3RP3_D+ USB3RP3_D+
USB3TN3_D- USB3TN3_D-
USB3TP3_D+ USB3TP3_D+
USB_PWR_SHR_VBUS_EN<36>
8
CB
7
TDM
6
TDP
5
VDD
SLGC55594AVTR_TDFN8_2X2
C287
C287
SLGC55594AVTR_TDFN8_2X2
USB3RN2_D-
USB3RP2_D+
0.1U_0402_25V6
0.1U_0402_25V6
D15 EMC@
D15 EMC@
1
2
4
5 6
3
TVWDF1004AD0_DFN9
TVWDF1004AD0_DFN9
L39
EMC@
L39
EMC@
1
1
4
4
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
1 2
R238@ 0_0402_5%R238@ 0_0402_5%
1 2
R240@ 0_0402_5%R240@ 0_0402_5%
U39
U39
1
CEN
2
DM
3
DP
4
SELCDP
9
Thermal Pad
9
8
7
2
USBP5_D+
2
3
USBP5_D-
3
1 2
R241@ 0_0402_5%R241@ 0_0402_5%
PWRSHARE_EN
PS_USBP0_DÂPS_USBP0_D+
SEL
SEL
USB3RN2_D- USB3RN2_D-
USB3RP2_D+ USB3RP2_D+
USB3TN2_D- USB3TN2_D-
1 2
12
+5V_ALW
+5V_ALW
100K_0402_5%
100K_0402_5%
R243
R243
1 2
PWRSHARE_EN#
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
1
D
D
2
Q7
Q7
G
G
S
S
3
+5V_ALW
R24410K_0402_5% R24410K_0402_5%
D17
D17
EMC@
EMC@
1
2
4
5 6
3
TVWDF1004AD0_DFN9
TVWDF1004AD0_DFN9
150U_D2_6.3VY_R15M
150U_D2_6.3VY_R15M
0.1U_0402_25V6
100U_1206_6.3V6M
100U_1206_6.3V6M
C86
C86
12
9
8
7
0.1U_0402_25V6
12
12
+
+
C281
C281
C280@
C280@
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
12
C284
C284
USB3TP2_D+USB3TP2_D+
3
ESATA_USB_PWR_EN#<36>
C285
C285
L30ESDL5V0C3-2_SOT23-3
L30ESDL5V0C3-2_SOT23-3
2
D16 EMC@
D16 EMC@
1
+5V_USB_CHG_PWR
100U_1206_6.3V6M
100U_1206_6.3V6M
12
C89
C89
+5V_ALW
USBP5_DÂUSBP5_D+
USB3RN3_DÂUSB3RP3_D+
USB3TN3_DÂUSB3TP3_D+
150U_D2_6.3VY_R15M
150U_D2_6.3VY_R15M
12
+
+
C290@
C290@
10U_0603_6.3V6M
10U_0603_6.3V6M
C288
C288
12
12
U32
U32
1
GND
VOUT
2
VIN
VOUT
3
VIN
VOUT
EN4FLG
G547I2P81U_MSOP8
G547I2P81U_MSOP8
0.1U_0402_25V6
0.1U_0402_25V6
12
C291
C291
0.1U_0402_25V6
0.1U_0402_25V6
PWRSHARE_EN#
C289
C289
JUSB2 CONN@
JUSB2 CONN@
1
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
7
GND
8
SSTX-
9
SSTX+
SANTA_373070-1
SANTA_373070-1
+USB_PWR
8
7
6
5
L30ESDL5V0C3-2_SOT23-3
L30ESDL5V0C3-2_SOT23-3
2
3
1
D18 EMC@
D18 EMC@
GND
GND
GND
GND
USBP0_DÂUSBP0_D+
USB3RN2_DÂUSB3RP2_D+
USB3TN2_DÂUSB3TP2_D+
1
2
3
10
11
12
13
USB_OC2# <11,12>
+5V_USB_CHG_PWR
U35
U35
8
GND
VOUT
7
VIN
VOUT
6
VIN
VOUT
5
EN4FLG
G547I2P81U_MSOP8
G547I2P81U_MSOP8
JUSB1
JUSB1
CONN@
CONN@
1
VBUS
2
D-
3
D+
4
GND
5
StdA-SSRX-
6
StdA-SSRX+
7
8
9
TAITW_PUBAU4-09FLBS1NN4H0
TAITW_PUBAU4-09FLBS1NN4H0
GND
GND-DRAIN
GND
StdA-SSTX-
GND
StdA-SSTX+
GND
USB_OC0# <11>
10
11
12
13
L42
EMC@
L42
EMC@
L41 EMC@
12
USB3TN2<11>
USB3TP2<11>
A A
USB3TN2_C USB3TN2_D-
C292 0.1U_0402_10V7KC292 0.1U_0402_10V7K
12
USB3TP2_C USB3TP2_D+
C293 0.1U_0402_10V7KC293 0.1U_0402_10V7K
L41 EMC@
4
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
3
4
1
2
1 2
R248@ 0_0402_5%R248@ 0_0402_5%
1 2
R250@ 0_0402_5%R250@ 0_0402_5%
3
2
PS_USBP0_D+
PS_USBP0_D-
1 2
CMM0805-120Y-N_4P
CMM0805-120Y-N_4P
1 2
R249@ 0_0402_5%R249@ 0_0402_5%
1 2
R251@ 0_0402_5%R251@ 0_0402_5%
USBP0_D+
34
USBP0_D-
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB3.0
USB3.0
USB3.0
LA-9591P
LA-9591P
LA-9591P
1
33 58Friday, May 17, 2013
33 58Friday, May 17, 2013
33 58Friday, May 17, 2013
0.4
0.4
0.4
5
12
D D
C C
B B
A A
DPC_LANE_P0<21>
DPC_LANE_N0<21>
DPC_LANE_P1<21>
DPC_LANE_N1<21>
DPC_LANE_P2<21>
DPC_LANE_N2<21>
DPC_LANE_P3<21>
DPC_LANE_N3<21>
DPC_DOCK_HPD
C302 0.1U_0402_10V7KC302 0.1U_0402_10V7K
12
C295 0.1U_0402_10V7KC295 0.1U_0402_10V7K
12
C297 0.1U_0402_10V7KC297 0.1U_0402_10V7K
12
C299 0.1U_0402_10V7KC299 0.1U_0402_10V7K
12
C304 0.1U_0402_10V7KC304 0.1U_0402_10V7K
12
C306 0.1U_0402_10V7KC306 0.1U_0402_10V7K
12
C300 0.1U_0402_10V7KC300 0.1U_0402_10V7K
12
C301 0.1U_0402_10V7KC301 0.1U_0402_10V7K
DPC_DOCK_HPD<21> DPB_DOCK_HPD <21>
Close to DOCK
Its for Enhance ESD on
dock issue.
100K_0402_5%
100K_0402_5%
12
R268
R268
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
0.033U_0402_16V7K
0.033U_0402_16V7K
12
+DOCK_PWR_BAR +DOCK_PWR_BAR
4
JDOCK1 CONN@
JDOCK1 CONN@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
GND1
146
PWR1
147
PWR1
151
Shield_G
152
Shield_G
153
Shield_G
154
Shield_G
155
Shield_G
156
Shield_G
JAE_WD2F144W B7-DT
JAE_WD2F144W B7-DT
SLICE_BAT_PRES#
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0603_50V7K
0.1U_0603_50V7K
@
@
12
CE7
CE7
DOCK_DET_1
DPC_CA_DET
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2
DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3
DPC_DOCK_AUX
DPC_DOCK_AUX#
BLUE_DOCK
RED_DOCK
GREEN_DOCK
L30ESD24VC3-2_SOT23-3
L30ESD24VC3-2_SOT23-3
2
3
C317
C317
1
D20 @
D20 @
DOCK_LOM_SPD10LED_GRN#<28>
1 2
R259 33_0402_5%EM C@ R259 33_0402_5%EMC@
1 2
R252 33_0402_5%EM C@ R252 33_0402_5%EMC@
1 2
R253 33_0402_5%EM C@ R253 33_0402_5%EMC@
1 2
R255 33_0402_5%EM C@ R255 33_0402_5%EMC@
1 2
R257 33_0402_5%EM C@ R257 33_0402_5%EMC@
1 2
R263 33_0402_5%EM C@ R263 33_0402_5%EMC@
1 2
R265 33_0402_5%EM C@ R265 33_0402_5%EMC@
1 2
R266 33_0402_5%EM C@ R266 33_0402_5%EMC@
DPC_DOCK_AUX<24>
DPC_DOCK_AUX#<24>
DPC_DOCK_HPD
+NBDOCK_DC_IN_SS
C310@
C310@
BLUE_DOCK<21>
RED_DOCK<21>
GREEN_DOCK<21>
HSYNC_DOCK<21>
VSYNC_DOCK<21>
CLK_MSE<37>
DAT_MSE<37>
DAI_BCLK#<26>
DAI_LRCK#<26>
DAI_DI<26>
DAI_DO#<26>
DAI_12MHZ#<26>
D_LAD0<36>
D_LAD1<36>
D_LAD2<36>
D_LAD3<36>
D_LFRAME#<36>
D_CLKRUN#<36>
D_SERIRQ<36>
D_DLDRQ1#<36>
CLK_PCI_DOCK<7>
DOCK_SMB_CLK<37>
DOCK_SMB_DAT<37>
DOCK_SMB_ALERT#<36,41,48>
DOCK_PSID<41>
DOCK_PWR_BTN#<37>
SLICE_BAT_PRES#<36,41,48> DOCK_DET# <36,48>
12
3
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
GND2
PWR2
PWR2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
WD2F144WB7
WD2F144WB7
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
148
149
150
157
158
159
160
161
162
DOCK_AC_OFF
DPB_CA_DET
DPB_DOCK_LANE_P0
DPB_DOCK_LANE_N0
DPB_DOCK_LANE_P1
DPB_DOCK_LANE_N1
DPB_DOCK_LANE_P2
DPB_DOCK_LANE_N2
DPB_DOCK_LANE_P3
DPB_DOCK_LANE_N3
DPB_DOCK_AUX
DPB_DOCK_AUX#
DPB_DOCK_HPD
SATA_PRX_DKTX_P0
SATA_PRX_DKTX_N0
SATA_PTX_DKRX_P0
SATA_PTX_DKRX_N0
DOCK_USBP0_D+
DOCK_USBP0_D-
DOCK_DET_R#
0.1U_0603_50V7K
0.1U_0603_50V7K
12
C318
C318
2
4
6
8
DOCK_AC_OFF <48>
DOCK_LOM_SPD100LED_ORG# <28>
DPB_CA_DET <21,24>DPC_CA_DET<21,24>
ACAV_DOCK_SRC# <48>
DOCK_USBP5+ <32>
DOCK_USBP5- <32>
CLK_KBD <37>
DAT_KBD <37>
DOCK_USB3RN3 <32>
DOCK_USB3RP3 <32>
DOCK_USB3TN3 <32>
DOCK_USB3TP3 <32>
BREATH_LED# <36,40>
DOCK_LOM_ACTLED_YEL# <28>
DOCK_LOM_TRD0+ <28>
DOCK_LOM_TRD0- <28>
DOCK_LOM_TRD1+ <28>
DOCK_LOM_TRD1- <28>
+LOM_VCT
DOCK_LOM_TRD2+ <28>
DOCK_LOM_TRD2- <28>
DOCK_LOM_TRD3+ <28>
DOCK_LOM_TRD3- <28>
DOCK_POR_RST# <37>
R260 33_0402_5%EM C@ R260 33_0402_5%EMC@
R261 33_0402_5%EM C@ R261 33_0402_5%EMC@
R254 33_0402_5%EM C@ R254 33_0402_5%EMC@
R256 33_0402_5%EM C@ R256 33_0402_5%EMC@
R262 33_0402_5%EM C@ R262 33_0402_5%EMC@
R264 33_0402_5%EM C@ R264 33_0402_5%EMC@
R258 33_0402_5%EM C@ R258 33_0402_5%EMC@
R267 33_0402_5%EM C@ R267 33_0402_5%EMC@
DPB_DOCK_AUX <24>
DPB_DOCK_AUX# <24>
DAT_DDC2_DOCK <21>
CLK_DDC2_DOCK <21>
C312 0.01U_0402_16V7KC312 0.01U_0402_16V7K
C313 0.01U_0402_16V7KC313 0.01U_0402_16V7K
1 2
1 2
C314 0.01U_0402_16V7KC314 0.01U_0402_16V7K
C315 0.01U_0402_16V7KC315 0.01U_0402_16V7K
DOCK_DCIN_IS+ <4 7>
DOCK_DCIN_IS- <47>
10_0402_1%
10_0402_1%
12
RE4@
RE4@
4.7P_0402_50V8C
4.7P_0402_50V8C
12
CE8@
CE8@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
2
2
3
3
DLW21SN900SQ2L-0805_4P
DLW21SN900SQ2L-0805_4P
@
@
R269 0_0402_5%@R269 0_0402_5%@
R270 0_0402_5%@R270 0_0402_5%@
EMI solution for E-Docking USB
+LOM_VCT
D19
D19
1 2
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
10_0402_1%
10_0402_1%
12
RE5@
RE5@
4.7P_0402_50V8C
4.7P_0402_50V8C
12
DPB_LANE_P0_C
DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
SATA_PRX_DKTX_P0_C <6>
SATA_PRX_DKTX_N0_C <6>
SATA_PTX_DKRX_P0_C <6>
SATA_PTX_DKRX_N0_C <6>
1
1
4
4
L43
L43
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
12
C316
C316
CE9@
CE9@
C294 0.1U_0402_10V7KC294 0.1U_04 02_10V7K
C296 0.1U_0402_10V7KC296 0.1U_04 02_10V7K
C298 0.1U_0402_10V7KC298 0.1U_04 02_10V7K
C303 0.1U_0402_10V7KC303 0.1U_04 02_10V7K
C305 0.1U_0402_10V7KC305 0.1U_04 02_10V7K
C307 0.1U_0402_10V7KC307 0.1U_04 02_10V7K
C308 0.1U_0402_10V7KC308 0.1U_04 02_10V7K
C309 0.1U_0402_10V7KC309 0.1U_04 02_10V7K
DOCK_USBP0+ <33>
DOCK_USBP0- <33>
CLK_PCI_DOCKDAI_12MHZ# DAI_BCLK#
R273@
R273@
12P_0402_50V8J
12P_0402_50V8J
C319@
C319@
EMI depop location
1 2
DOCK_DET#
33_0402_5%
33_0402_5%
12
12
1
12
12
12
12
12
12
12
12
0.033U_0402_16V7K
0.033U_0402_16V7K
12
@
@
C311
C311
Close to DOCK
Its for Enhance ESD on dock
issue.
DPB_DOCK_HPD
+3.3V_ALW
R27210K_0402_5% R27210K_0402_5%
DPB_LANE_P0 <21>
DPB_LANE_N0 <21>
DPB_LANE_P1 <21>
DPB_LANE_N1 <21>
DPB_LANE_P2 <21>
DPB_LANE_N2 <21>
DPB_LANE_P3 <21>
DPB_LANE_N3 <21>
100K_0402_5%
100K_0402_5%
12
R271
R271
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
E-Dock
E-Dock
E-Dock
LA-9591P
LA-9591P
LA-9591P
34 58Friday, May 17, 2013
34 58Friday, May 17, 2013
34 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
T94
T94
1
SW_LAN_TX1-<28>
D D
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
12
12
C323
C323
C324
C324
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
C C
12
12
C326
C326
C325
C325
SW_LAN_TX1+<28>
SW_LAN_TX0-<28>
SW_LAN_TX0+<28>
SW_LAN_TX3-<28>
SW_LAN_TX3+<28>
SW_LAN_TX2-<28>
SW_LAN_TX2+<28>
SW_LAN_TX1-
SW_LAN_TX1+
SW_LAN_TX0-
SW_LAN_TX0+
SW_LAN_TX3-
SW_LAN_TX3+
SW_LAN_TX2-
SW_LAN_TX2+
TD1+
2
TD1-
3
TDCT1
4
TDCT2
5
TD2+
6
TD2-
7
TD3+
8
TD3-
9
TDCT3
10
TDCT4
11
TD4+
12
TD4-
GND
GND
CHASSIS
CHASSIS
350uH_IH-115-F
350uH_IH-115-F
4
1:1
1:1
1:1
1:1
TX1+
TX1-
TXCT1
TXCT2
TX2+
24
NB_LAN_TX1-
23
NB_LAN_TX1+
22
Z2805
21
Z2807
20
NB_LAN_TX0-
3
2
+3.3V_LAN
470P_0402_50V7K
470P_0402_50V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
C321
12
C321
12
C320
C320
1
RJ45 LOM circuit
C327
1 2
1:1
1:1
1:1
1:1
EMC@
EMC@
150P_1808_2.5KV8JC327
150P_1808_2.5KV8J
19
NB_LAN_TX0+
TX2-
18
NB_LAN_TX3-
TX3+
17
NB_LAN_TX3+
TX3-
16
Z2806
TXCT3
15
Z2808
TXCT4
14
NB_LAN_TX2-
TX4+
13
NB_LAN_TX2+
TX4-
+GND_CHASSIS
use 40mil trace if necessary
12
R278 75_0402_1%R278 75_0402_1%
R277 75_0402_1%R277 75_0402_1%12R279 75_0402_1%R279 75_0402_1%
LAN_ACTLED_YEL#<28>
12
12
R280 75_0402_1%R280 75_0402_1%
LED_10_GRN#<28>
LED_100_ORG#<28>
1 2
R274 150_0402_5%R274 15 0_0402_5%
NB_LAN_TX3-
NB_LAN_TX3+
NB_LAN_TX1-
NB_LAN_TX2-
NB_LAN_TX2+
NB_LAN_TX1+
NB_LAN_TX0-
NB_LAN_TX0+
1 2
R275 150_0402_5%R275 150_0402_5%
1 2
R276 150_0402_5%R276 150_0402_5%
LAN_ACTLED_YEL_R#
LED_10_GRN_R#
LED_100_ORG_R#
+3.3V_LAN:20mils
JLOM1
CONN@
JLOM1
10
9
8
7
6
5
4
3
2
1
11
13
12
CONN@
Yellow LED-
Yellow LED+
PR4-
PR4+
PR2-
PR3-
PR3+
PR2+
PR1-
PR1+
Green LED-
Orange LED-
Green-Orange LED+
SANTA_130456-341
SANTA_130456-341
GND
GND
rev1
rev1
15
14
USB3RP1_IO
USB3RN1_IO
+5V_ALW
JIO1
JIO1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
GND
28
GND
ACES_50506-02641-P01
ACES_50506-02641-P01
CONN@
CONN@
+5V_ALW +3.3V_ALW +3.3V_RUN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
@
12
@
12
12
C4
C4
C50
C50
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
C77
C77
USB3.0 repeater
B B
+3.3V_RUN
12
R478
R478
R479
R479
R480
@
R480
@
A A
EQ0
4.7K_0402_5%
4.7K_0402_5%
12
EQ1
4.7K_0402_5%
4.7K_0402_5%
12
DE
4.7K_0402_5%
4.7K_0402_5%
+3.3V_RUN +3.3V_RUN
12
C395
C395
U51
U51
R476
R476
0.01U_0402_16V7K
0.01U_0402_16V7K
USB3RN1_IO
USB3RP1_IO
12
3.01K_0402_1%
3.01K_0402_1%
6
VDD
1
INn
2
INp
4
NC
19
EQ0
18
DE
DE
10
REXT
3
GND
13
GND
21
GND
PS8711BTQFN20GTR-A0_TQFN20_3X3
PS8711BTQFN20GTR-A0_TQFN20_3X3
VDD
OUTn
OUTp
EQ1
EQ_INC#
PD#
I2C_EN
16
15
USB3RN1_RP
14
USB3RP1_RP
12
NC
17
EQ1EQ0
11
4.7K_0402_5%
4.7K_0402_5%
20
5
7
NC
8
NC
9
NC
12
C381
C381
0.1U_0402_10V7K
0.1U_0402_10V7K
12
C335 0.1U_0402_10V7KC335 0.1U_04 02_10V7K
12
C286 0.1U_0402_10V7KC286 0.1U_04 02_10V7K
1 2
R477
@
R477
@
USB3RN1 <11>
USB3RP1 <11>
I/O CONN
WIRELESS_ON#/OFF<36>
USB_OC1#<11>
USB_SIDE_EN#<36>
AUD_HP_NB_SENSE<26,36>
AUD_HP_OUT_R<26>
RING2<26>
SLEEVE<26>
AUD_HP_OUT_L<26>
USB3TP1<11>
USB3TN1<11>
USBP1+<11>
USBP1-<11>
LID_CL#<36,40>
+3.3V_ALW
+3.3V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
RJ45 & I/O
RJ45 & I/O
RJ45 & I/O
LA-9591P
LA-9591P
LA-9591P
35 58Friday, May 17, 2013
35 58Friday, May 17, 2013
35 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
+3.3V_ALW +3.3V_ALW_U37
12
+3.3V_ALW
D D
C C
B B
A A
1 2
R281 10K_0402_5%R281 10K_0402_5%
1 2
R282 100K_0402_5%R282 100K_0402_5%
1 2
R283 100K_0402_5%R283 100K_0402_5%
1 2
R284 100K_0402_5%R284 100K_0402_5%
1 2
R285 100K_0402_5%R285 100K_0402_5%
1 2
R286 100K_0402_5%R286 100K_0402_5%
1 2
R287 100K_0402_5%R287 100K_0402_5%
1 2
R288 10K_0402_5%R288 10K_0402_5%
1 2
R289 100K_0402_5%R289 100K_0402_5%
1 2
R291 100K_0402_5%R291 100K_0402_5%
1 2
R292 100K_0402_5%R292 100K_0402_5%
1 2
R293 100K_0402_5%R293 100K_0402_5%
1 2
R295 100K_0402_5%R295 100K_0402_5%
1 2
R298 100K_0402_5%R298 100K_0402_5%
1 2
R302 100K_0402_5%@ R302 100K_0402_5%@
+3.3V_RUN
1 2
R304@ 10K_0402_5%R304@ 10K_0402_5%
1 2
R309 100K_0402_5%R309 100K_0402_5%
1 2
R310 10K_0402_5%R310 10K_0402_5%
1 2
R313 100K_0402_5%R313 100K_0402_5%
ALS_INT#
HW_GPS_DISABLE2#
PROCHOT_GATE
CPU_DETECT#
SLICE_BAT_PRES#
WWAN_RADIO_DIS#
USB_PWR_SHR_EN#
WIGIG60GHZ_DIS#
USB_PWR_SHR_VBUS_EN
WIRELESS_ON#/OFF
ESATA_USB_PWR_EN#
BT_RADIO_DIS#
XFR_ID_BIT#
SP_TPM_LPC_EN
LCD_TST
SYS_LED_MASK#
CHARGE_EN
ME_FWP PCH has internal 20K PD.
(suspend power rail)
5
ME_FWP
DOCKED_LIO_EN<33>
T97@ PAD~DT97@ PAD~D
PROCHOT_GATE<47>
DOCK_SMB_ALERT#<34,41,48>
T98@ PAD~DT98@ PAD~D
USB_SIDE_EN#<35>
EN_I2S_NB_CODEC#<26>
USH_PWR_STATE#<29>
EN_DOCK_PWR_BAR<48>
PANEL_BKEN_EC<22>
ENVDD_PCH<10,22>
LCD_TST<22>
PSID_DISABLE#<41>
PBAT_PRES#<41,48>
DOCKED<21,27,28,32>
DOCK_DET#<34,48>
AUD_NB_MUTE#<26>
MCARD_WWAN_PWREN<31>
LCD_VCC_TEST_EN<22>
AUD_HP_NB_SENSE<26,35>
ESATA_USB_PWR_EN#<33>
T106@ PAD~DT106@ PAD~D
SLICE_BAT_ON<48>
SLICE_BAT_PRES#<34,41,48>
T107@ PAD~DT107@ PAD~D
T110@ PAD~DT110@ PAD~D
WIGIG60GHZ_DIS#<31>
EC5048_TX<31,37>
MCARD_PCIE_SATA#<6>
CPU_DETECT#<9>
T115@ PAD~DT115@ PAD~D
BCM5882_ALERT#<29>
SUSACK#<9>
T118@ PAD~DT118@ PAD~D
SLP_ME_CSW_DEV#<12>
LAN_DISABLE#_R<28>
SYS_LED_MASK#<40>
SIO_EXT_WAKE#<12>
WIRELESS_LED#<31,40>
USB_PWR_SHR_VBUS_EN<33>
WLAN_RADIO_DIS#<31>
WIRELESS_ON#/OFF<35> BC_CLK_ECE5048 <37>
BT_RADIO_DIS#<31>
WWAN_RADIO_DIS#<31>
SYS_PWROK<9>
T121@ PAD~DT121@ PAD~D
SIO_SLP_WLAN#<9>
PCH_DPWROK<9>
1K_0402_ 5%
1K_0402_ 5%
12
R326@
R326@
MCARD_MISC_PWREN
PROCHOT_GATE
LID_CL_SIO#
DOCK_SMB_ALERT#
TOUCH_SCREEN_PD#
USB_SIDE_EN#USB_SIDE_EN#
EN_I2S_NB_CODEC#
USH_PWR_STATE#
EN_DOCK_PWR_BAR
PANEL_BKEN_EC
ENVDD_PCH
LCD_TST
PSID_DISABLE#
PBAT_PRES#
DOCKED
DOCK_DET#
AUD_NB_MUTE#
MCARD_WWAN_PWREN
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR_EN#
MODULE_ON
SLICE_BAT_ON
SLICE_BAT_PRES#
MODULE_BATT_PRES#
CHARGE_PBATT
WIGIG60GHZ_DIS#
EC5048_TX
mCARD_PCIE_SATA#
CPU_DETECT#
XFR_ID_BIT#
DP_HDMI_HPD
BCM5882_ALERT#
EDID_SELECT#
VGA_ID
SLP_ME_CSW_DEV#
LAN_DISABLE#_R
CHARGE_EN
SYS_LED_MASK#
ALS_INT#
SIO_EXT_WAKE#
WIRELESS_LED#
WLAN_RADIO_DIS#
WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RADIO_DIS#
SYS_PWROK
DGPU_SELECT#
CPU_VTT_ON
1 2
R319@ 0_0402_5%R319@ 0_0402_5%
+3.3V_ALW
100K_040 2_5%
100K_040 2_5%
R317
R317
1 2
VGA_ID
100K_040 2_5%
100K_040 2_5%
R320@
R320@
Discrete
1 2
UMA 1
4
B52
A49
B53
A50
B54
A51
B55
A52
A33
B36
A34
B37
A35
B38
A36
A37
B40
A38
B41
A39
B42
A40
B43
A41
B44
B32
A31
B33
B15
A15
B16
A16
A1
B2
A2
B3
A3
B45
A42
B4
A59
B62
A58
B61
A56
B59
A55
B58
B47
A45
B48
A46
B49
A47
B50
A48
B13
A13
A53
B57
B14
A14
B17
B18
VGA_ID0
10U_0603 _6.3V6M
10U_0603 _6.3V6M
C328
C328
U37
U37
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
GPIOB0
GPIOB1
GPOC2
GPOC3
GPOC4
GPOC5
GPOC6/TACH4
GPIOC7
GPIOD0
GPIOC1
GPIOC0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#
GPIOF0
GPIOF1
GPIOF2
GPIOF3/TACH8
GPIOF4/TACH7
GPIOF5
GPIOF6
GPIOF7
GPIOG0/TACH5
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7/TACH6
GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7
0
PJP6
PJP6
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
12
B5
A17
B30
A43
A54
VCC1
VCC1
VCC1
VCC1
VCC1
14.318MHZ/GPIOM0
ECE5048-LZY_DQFN132_11X11~D
ECE5048-LZY_DQFN132_11X11~D
0.1U_0402 _25V6
0.1U_0402 _25V6
0.1U_0402 _25V6
0.1U_0402 _25V6
0.1U_0402 _25V6
0.1U_0402 _25V6
0.1U_0402 _25V6
12
C330
C330
C329
C329
A23
GPIOI0
B63
GPIOI1
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
GPIOJ0
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
GPIOK0
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
GPIOL6
GPIOM1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ1#
SER_IRQ
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
BC_INT#
BC_DAT
BC_CLK
PWRGD
OUT65
TEST_PIN
CAP_LDO
A60
A61
B65
A62
B66
A63
B67
A64
A5
B6
A6
B7
A7
B8
A8
B9
B10
A10
B11
A11
B12
A12
B60
A57
B64
B68
A9
B1
A18
A44
B34
B39
B51
A27
A26
B26
B25
A21
B22
A28
B20
A22
B21
A32
B35
B29
B28
A25
A24
B23
A19
B24
A20
A29
B31
A30
A4
B56
B19
B46
B27
VSS
C1
EP
GPIOI2/TACH0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOK1/TACH3
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL7/PWM5
GPIOM3/PWM4
GPIOM4/PWM6
CLK32/GPIOM2
DB Version 0.4
DB Version 0.4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
0.1U_0402 _25V6
0.1U_0402 _10V7K
0.1U_0402 _10V7K
12
12
C331
C331
C334
C334
SIO_SLP_A#
AUX_EN_WOWL
SIO_SLP_LAN#
SIO_SLP_SUS#
MODC_EN
DOCK_HP_DET
DOCK_MIC_DETDOCK_SMB_ALERT#
ME_FWP
MASK_SATA_LED#
USB_PWR_SHR_EN#
LED_SATA_DIAG_OUT#
RUN_ON
SUS_ON
BAT1_LED#
BAT2_LED#
FP_POA_EN
HW_GPS_DISABLE2#
BREATH_LED#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_PLTRST#_EC
CLK_PCI_5048
CLKRUN#
LPC_LDRQ1#
IRQ_SERIRQ
D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ
BC_INT#_ECE5048
BC_DAT_ECE5048
BC_CLK_ECE5048
RUNPWROK
SP_TPM_LPC_EN
1 2
R321 1K_0402_5%R321 1K_0402_5%
+CAP_LDO
12
C332
C332
SIO_SLP_A# <39,44,9>
SIO_SLP_S4# <39,43,9>
SIO_SLP_S3# <39,43,9>
IMVP_PWRGD <46>
IMVP_VR_ON <46>
DOCK_AC_OFF_EC <48>
AUX_EN_WOWL <31>
WLAN_LAN_DISB# <28>
SIO_SLP_LAN# <28,9>
SIO_SLP_SUS# <9>
GPIO_PSID_SELECT <41>
T101 @PAD~D T101 @PAD~D
DOCK_HP_DET <26>
DOCK_MIC_DET <26>
ME_FWP <6>
MASK_SATA_LED# <40>
USB_PWR_SHR_EN# <33>
LED_SATA_DIAG_OUT# <40>
RUN_ON <26,37,39>
AC_DIS <41,48>CCD_OFF<22>
SPI_WP#_SEL <7>
SUS_ON <39,43>
BAT1_LED# <40>
BAT2_LED# <40>
USH_PWR_ON <39>
T100 @PAD~D T100 @PAD~D
HW_GPS_DISABLE2# <31>
BREATH_LED# <34,40>
DIS_BAT_PROCHOT# <48>
LPC_LAD0 <29,37,7>
LPC_LAD1 <29,37,7>
LPC_LAD2 <29,37,7>
LPC_LAD3 <29,37,7>
LPC_LFRAME# <29,37,7>
PCH_PLTRST#_EC <29,31,37,9>
CLK_PCI_5048 <7>
CLKRUN# <12,29,37,9>
IRQ_SERIRQ <12,29,37>
EC_32KHZ_ECE5048 <37>
D_LAD0 <34>
D_LAD1 <34>
D_LAD2 <34>
D_LAD3 <34>
D_LFRAME# <34>
D_CLKRUN# <34>
D_DLDRQ1# <34>
D_SERIRQ <34>
BC_INT#_ECE5048 <37>
BC_DAT_ECE5048 <37>
RUNPWROK <37,9>
SP_TPM_LPC_EN <29>
4.7U_0603 _6.3V6K
4.7U_0603 _6.3V6K
12
C336
C336
+CAP_LDO trace width 20 mils
EMI depop location
EMI depop location
EMI depop locationEMI depop location
CLK_PCI_5048
trace width 20 mils
trace width 20 mils
33_0402_ 5%
33_0402_ 5%
12
R324@
R324@
33P_0402 _50V8J
33P_0402 _50V8J
C339@
C339@
12
2
+3.3V_RUN
RP8
RP8
1
8
2
7
3
6
4 5
100K_0804_8P4R_5%
100K_0804_8P4R_5%
12
12
12
12
12
LID_CL# <35,40>
LID_CL_SIO#
D_CLKRUN#
D_SERIRQ
D_DLDRQ1#
LPC_LDRQ1#
RUN_ON
R303 100K_0402_5%R303 100K_0402_5%
CPU_VTT_ON
R305 100K_0402_5%R305 100K_0402_5%
SLICE_BAT_ON
R307 100K_0402_5%R307 100K_0402_5%
SUS_ON
R308 100K_0402_5%R308 100K_0402_5%
+3.3V_ALW
100K_040 2_5%
100K_040 2_5%
12
R322
R322
0.047U_04 02_16V4Z
0.047U_04 02_16V4Z
12
C337
C337
R325 10_0402_1%R325 10_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
ECE5048
ECE5048
ECE5048
LA-9591P
LA-9591P
LA-9591P
1
0.4
0.4
36 58Friday, May 17, 2013
36 58Friday, May 17, 2013
36 58Friday, May 17, 2013
0.4
5
1
JTAG1 CONN@
@SHORT PADS~D
JTAG1 CONN@
@SHORT PADS~D
1
2
2
CONN@
CONN@
JDEG1
JDEG1
1
2
3
4
5
11
6
G1
12
7
G2
8
9
10
HB_A531015-SCHR21
HB_A531015-SCHR21
CONN@
CONN@
JLPDE1
JLPDE1
1
2
3
4
5
11
6
G1
12
7
G2
8
9
10
HB_A531015-SCHR21
HB_A531015-SCHR21
+3.3V_ALW
1 2
R340 10K_0 402_5%R3 40 10K_04 02_5%
1 2
R343 100K_ 0402_5%R 343 100K_ 0402_5%
1 2
R345 2.2K_0 402_5%R3 45 2.2K_04 02_5%
1 2
R339 2.2K_0 402_5%R3 39 2.2K_04 02_5%
+5V_RUN
1
2
3
4 5
4.7K_8P4R_ 5%
4.7K_8P4R_ 5%
+3.3V_RUN
1 2
R358@ 100K_0402_5%R358@ 100K _0402_5%
1 2
R360@ 100K_0402_5%R360@ 100K _0402_5%
1 2
R362@ 100K_0402_5%R362@ 100K _0402_5%
1 2
R408 10K_0402_ 5%R40 8 10K_0402_5%
1 2
R376 10K_0402_ 5%R37 6 10K_0402_5%
+3.3V_ALW
RP18
RP18
8
7
100K_0804 _8P4R_5%
100K_0804 _8P4R_5%
1 2
R366 10K_0402_ 5%R36 6 10K_0402_5%
1 2
R371 100K_0402 _5%R371 100K_04 02_5%
1 2
R373 8.2K_0402 _5%@R373 8.2K_ 0402_5%@
+3.3V_ALW
100K_0402_5%
100K_0402_5%
12
1U_0402_6.3V6K
1U_0402_6.3V6K
100_0402_1%
100_0402_1%
12
12
C362
C362
+3.3V_ALW
49.9_0402_1%
49.9_0402_1%
12
R388
R388
1
2
3
4
5
6
MSCLK
7
MSDATA
8
HOST_DEB_TX
9
10
+3.3V_RUN
1
2
3
LPC_LAD0
4
LPC_LAD1
5
LPC_LAD2
6
LPC_LAD3
7
LPC_LFRAME#
8
PCH_PLTRST#_EC
9
10
5
RP2
RP2
8
7
6
1
2
3456
R380
R380
JTAG_RST#
R384@
R384@
10K_8P4R_5%
10K_8P4R_5%
678
123
4 5
PCIE_WAKE#
BC_DAT_ECE5048
PBAT_SMBDAT
PBAT_SMBCLK
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
VOL_MUTE
VOL_DOWN
VOL_UP
FAN1_PWM
FAN1_TACH
BC_DAT_ECE1117
PCH_ALW_ON
DOCK_POR_RST#
MSDATA
EN_INVPWR
RESET_OUT#
+3.3V_ALW
RP1
RP1
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
1 2
R400@ 0_0402_5 %R400@ 0_ 0402_5%
CLK_PCI_LPDEBUG <7>
+3.3V_ALW +3.3V_ALW_U38
12
10_0402_1%
10_0402_1%
R382@
R382@
Place close pin A29
100K_0402_5%
100K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
12
12
12
R397
R397
R395
R395
R396
R396
Pin8 5075_TXD f or EC Debug
pin9 5048_TXD f or SBIOS
debug
PJP7
PJP7
1 2
10U_0603_6.3V6M
10U_0603_6.3V6M
PAD-OPEN1x1m
PAD-OPEN1x1m
C348
C348
32 KHz Clock
1 2
MEC_XTAL1
22P_0402_50V8J
22P_0402_50V8J
32.768KHZ_12 .5PF_Q13FC1 35000040
32.768KHZ_12 .5PF_Q13FC1 35000040
12
C364
C364
CLK_PCI_MEC
12
4.7P_0402_50V8C
4.7P_0402_50V8C
@
@
12
C363
C363
EMI depop locat ion
R398@
R398@
HOST_DEBUG_TX
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
C349
C349
MEC_XTAL2
Y4
Y4
EC5048_TX <31,36>
12
D D
C C
B B
A A
+RTC_CELL
+3.3V_ALW_U38
+3.3V_ALW_U38
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
C350
C350
C354
C354
22P_0402_50V8J
22P_0402_50V8J
12
C365
C365
12
Place close pin A21
4
R332@ 0_0402_5%R332@ 0_0402_5%
R336@ 0_0402_5%R336@ 0_0402_5%
1 2
R354@ 0_04 02_5%R354@ 0 _0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
12
C355
C355
C356
C356
EC_32KHZ_ECE5048<36>
DOCK_POR_RST#
0.1U_0402_25V6
0.1U_0402_25V6
C357
C357
1 2
1 2
0.1U_0402_25V6
0.1U_0402_25V6
12
0.1U_0402_25V6
0.1U_0402_25V6
12
C345
C345
0.1U_0402_25V6
0.1U_0402_25V6
12
C346
C346
0.1U_0402_25V6
0.1U_0402_25V6
12
C353
C353
C351
C351
SML1_SMBDATA<7>
SML1_SMBCLK<7>
CLK_TP_SIO<38>
DAT_TP_SIO<38>
CLK_KBD<34>
DAT_KBD<34>
CLK_MSE<34>
DAT_MSE<34>
PBAT_SMBDAT<41>
PBAT_SMBCLK<41>
DOCK_POR_RST#<34>
PCH_ALW_ON<39>
BIA_PWM_EC<22>
BC_CLK_ECE5048<36>
BC_DAT_ECE5048<36>
BC_INT#_ECE5048<36>
ACAV_IN_NB<47,4 8>
SIO_SLP_S5#<9>
BEEP<26>
BC_CLK_ECE1117<38>
BC_DAT_ECE1117<38>
BC_INT#_ECE1117<38>
SIO_EXT_SMI#<12>
IRQ_SERIRQ<12,29,36>
PCH_PLTRST#_EC<29,31,36,9>
CLK_PCI_MEC<7>
LPC_LFRAME#<29,36,7>
LPC_LAD0<29,36,7>
LPC_LAD1<29,36,7>
LPC_LAD2<29,36,7>
LPC_LAD3<29,36,7>
CLKRUN#<12,29,36,9>
SIO_EXT_SCI#<12>
MEC_XTAL2 MEC_XTAL2_R
R378@ 0_0402_5%R378@ 0_0402_5%
R379@ 0_0402_5%R379@ 0_0402_5%
R392 C368
240K 4700p
130K 4700p
4700p
62K
4700p
33K
4700p
8.2K
4700p
4.3K
4700p
2K
1K
4700p
*
BOARD_ID rise time is measured from 5%~68%.
4
12
12
EC_WAKE#<12>
SIO_RCIN#<12>
1 2
+RTC_CELL_VBAT
+3.3V_VTR
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C352
C352
+3.3V_VTR_ADC
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C347
C347
A_ON<39 ,44>
12
REV
X00
X01
***
X02
***
***
***
A00
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
FAN1_TACH
DOCK_POR_RST#
A_ONA_ON
PCH_ALW_ON
BIA_PWM_EC
FAN1_PWM
BC_CLK_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE5048
ACAV_IN_NB
SIO_SLP_S5#
BEEP
BC_CLK_ECE1117
BC_DAT_ECE1117
BC_INT#_ECE1117
SIO_EXT_SMI#
SIO_RCIN#
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
MEC_XTAL1
U38
U38
B64
VBAT
A22
H_VTR
A58
VTR_ADC
B3
VTR
A11
VTR
A26
VTR
B35
VTR
A41
VTR
A52
VTR
A5
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY
B6
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR
A37
GPIO110/PS2_CLK2/GPTP-IN6
B40
GPIO111/PS2_DAT2/GPTP-OUT6
A38
GPIO112/PS2_CLK1A
B41
GPIO113/PS2_DAT1A
A39
GPIO114/PS2_CLK0A
B42
GPIO115/PS2_DAT0A
B59
GPIO154/I2C1C_DATA/PS2_CLK1B
A56
GPIO155/I2C1C_CLK/PS2_DAT1B
A51
GPIO145/I2C1K_DATA/JTAG_TDI
B55
GPIO146/I2C1K_CLK/JTAG_TDO
B56
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
A53
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
A57
JTAG_RST#
B22
GPIO050/FAN_TACH1/GTACH
A21
GPIO051/FAN_TACH2
B23
GPIO052/FAN_TACH3
B24
GPIO053/PWM0
A23
GPIO054/PWM1
B25
GPIO055/PWM2
A24
GPIO056/PWM3/GPWM
A43
GPIO123/BCM_A_CLK
B45
GPIO122/BCM_A_DAT
A42
GPIO121/BCM_A_INT#
B20
GPIO032/BCM_E_CLK
A18
GPIO031/GPTP-OUT2/BCM_E_DAT
B19
GPIO030/GPTP-IN2/BCM_E_INT#
A20
GPIO047/LSBCM_D_CLK
B21
GPIO046/LSBCM_D_DAT
A19
GPIO045/LSBCM_D_INT#
A6
GPIO011/nSMI/GANG_DATA0
A27
GPIO061/LPCPD#
A28
SER_IRQ
B30
LRESET#
A29
PCI_CLK
B31
LFRAME#
A30
LAD0
B32
LAD1
A31
LAD2
B33
LAD3
A32
CLKRUN#
A33
GPIO100/NEC_SCI
A61
XTAL1
A62
XTAL2
B62
GPIO160/32KHZ_OUT
B66
15mil
RUN_ON<26,36,39>
+3.3V_ALW
1K_0402_5%
1K_0402_5%
12
R392
R392
BOARD_ID
4700P_0402_25V7K
4700P_0402_25V7K
12
C368
C368
AGND
VSS
VSS_ADC
B11
B60
SYSTEM_ID
CHIPSET_ID for BID function
3
+RTC_CELL
100K_0402_5%
100K_0402_5%
12
R327
R327
POWER_SW_IN#
VR_CAP
B12
+VR_CAP
12
1 2
R329 10 K_0402_5%R3 29 10K_ 0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C343
C343
GPIO101/ECGP_SCLK/GANG_DATA5
GPIO103/ECGP_MISO/GANG_DATA7
GPIO102/BCM_C_INT#/GANG_DATA6
GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP
GPIO015/GPTP-OUT7/GANG_DATA3
GPIO003/I2C1A_DATA/GANG_MODE
GPIO004/I2C1A_CLK/GANG_START
GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE
GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL
GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1
GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2
GPIO130/I2C2A_DATA/BCM_C_DAT
GPIO141/I2C1F_DATA/I2C2B_DATA
VSS_RO
H_VSS
EP
MEC5075-LZY_ DQFN132_11X1 1~D
MEC5075-LZY_ DQFN132_11X1 1~D
C1
B54
B18
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C366
C366
ESR <2ohms
+3.3V_ALW
100K_0402_5%
100K_0402_5%
12
RUNPWROK
R36
R36
RUN_ON#
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
6
Q5A
Q5A
2
1
+3.3V_ALW
1K_0402_5%
1K_0402_5%
12
R386
R386
4700P_0402_25V7K
4700P_0402_25V7K
12
C369
C369
3
1 2
1U_0402_6.3 V6K
1U_0402_6.3 V6K
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO014/GPTP-IN7/RC_ID3
GPIO025/UART_CLK
GPIO120/UART_TX
GPIO124/GPTP-OUT5/UART_RX
VCC_PWRGD
GPIO060/KBRST/BCM_B_INT#
GPIO105/ECGP_MOSI
GPIO104
GPIO106
GPIO117/MSCLK/V2P_COUT_HI
GPIO127/A20M
GPIO156/LED0
GPIO157/LED1
GPIO153/LED2
GPIO027/GPTP-OUT1
GPIO026/GPTP-IN1
GPIO001/ECSPI_CS1
GPIO016/GPTP-IN8/GANG_DATA4
GPIO017/GPTP-OUT8
GPIO107/NRESET_OUT
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
GPIO131/I2C2A_CLK/BCM_C_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK
SYSPWR_PRES
VCI_OVRD_IN
VCI_OUT
VCI_IN0#
VCI_IN1#
VCI_IN2#
VCI_IN3#
VREF_PECI
PECI_DAT
DN1-THERM
DP1-VREF_T
THERMTRIP2#
GPIO002/THERMTRIP3#
GPIO024/THSEL_STRAP
PROCHOT_IN#/PROCHOT_IO#
V_ISYS
+3.3V_RUN
10K_0402_5%
10K_0402_5%
12
R35
R35
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Q5B
Q5B
34
5
+3.3V_ALW
10K_0402_5%
10K_0402_5%
12
R393
R393
FWP#
10K_0402_5%
10K_0402_5%
R399@
R399@
1 2
2
+RTC_CELL
100K_0402_5%
100K_0402_5%
12
R328
DOCK_PWR_SW#
1 2
R367 1K _0402_5%R36 7 1K_0 402_5%
100K_0402_5%
100K_0402_5%
12
R370
R370
PECI_EC <9>
Location
CPU
DIMM
V.R
2
R328
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C344
C344
REM_DIODE1_P
REM_DIODE1_N
REM_DIODE2_P
REM_DIODE2_N
REM_DIODE4_P
REM_DIODE4_N
1 2
R330 10K_ 0402_5%R33 0 10K_040 2_5%
+3.3V_ALW2
R866 close to U38 at least 250mils
R374 0 _0402_5%@R374 0_0402_5%@
0.1U_0402_25V6
0.1U_0402_25V6
C360
C360
12
JFAN1
JFAN1
GND1
GND2
ACES_50271-00 40N-001
ACES_50271-00 40N-001
CONN@
CONN@
C342@
C342@
1 2
1U_0402_6.3 V6K
1U_0402_6.3 V6K
1 2
1
1
2
2
3
3
4
4
5
6
+1.05V_RUN
H_THERMTRIP#<12>
0.1U_0402_25V6
0.1U_0402_25V6
12
12
C367
C367
Rest=1.58K , Tp=96 degree
PROCHOT#_EC
+1.05V_RUN
FAN1_PWM
FAN1_TACH
22U_0805_6.3V6MC722U_0805_6.3V6M
12
C7
reserve for DC fan
1 2
R403 2.2K_0402_5%R403 2.2K_0402 _5%
VSET_5075
1.58K_0402_1%
1.58K_0402_1%
R394
R394
C340@
C340@
POWER_SW#_MB <40,9> DOCK_PWR_BTN# <34>
A10
SYSTEM_ID
B10
BOARD_ID
1 2
B8
R338 1K_040 2_5%R338 1 K_0402_5%
B27
LAN_WAKE#
B44
HOST_DEBUG_TX
B46
HOST_DEBUG_RX
B26
RUNPWROK
A25
EN_INVPWR
B36
PCH_SATA_MOD_EN#
B37
B38
PCIE_WAKE#
A34
DDR_HVREF_RST_GATE
A35
A36
A40
MSDATA
B43
MSCLK
A45
B65
FWP#
NFWP
DN2
DP2
DN3
DP3
DN4
DP4
VIN
VSET
VCP
1 2
B57
R349 1K_040 2_5%R349 1 K_0402_5%
B1
DEVICE_DET#
A55
PS_ID
A1
B28
1.05V_A_PWRGD
1 2
B2
A8
R352 1K_040 2_5%R352 1 K_0402_5%
B9
1.35V_SUS_PWRGD
A9
PM_APWROK
B39
RESET_OUT#
A44
PCH_PCIE_WAKE#
B47
PCH_RSMRST#
A54
AC_PRESENT
B58
SIO_PWRBTN#
A3
DOCK_SMB_DAT DOCK_SMB_DAT
B4
DOCK_SMB_CLK DOCK_SMB_CLK
A4
LCD_SMBDAT LCD_SMBDAT
B5
LCD_SMBCLK LCD_SMBCLK
B7
BAY_SMBDAT
A7
BAY_SMBCLK
B48
GPU_SMBDAT
B49
GPU_SMBCLK
A47
CHARGER_SMBDAT
B50
CHARGER_SMBCLK
B52
CARD_SMBDAT
A49
CARD_SMBCLK
B53
USH_SMBDAT
A50
USH_SMBCLK
A59
A64
ACAV_IN
A60
ALWON
B67
POWER_SW_IN#
A63
DOCK_PWR_SW#
B63
VCI_IN2#
B68
POA_WAKE#
B51
+PECI_VREF
A48
PECI_EC_RPECI_EC_R
B13
A13
B14
A14
A15
B16
A16
B17
B15
A17
A12
B34
A2
B29
A46
B61
R375 43_040 2_5%R375 43_0402_ 5%
REM_DIODE1_N
C358 2200P_0402_ 50V7KC358 2200P_0402_ 50V7K
REM_DIODE1_P
REM_DIODE2_N
C359 2200P_0402_ 50V7KC359 2200P_0402_ 50V7K
REM_DIODE2_P
REM_DIODE4_N
C361 2200P_0402_ 50V7KC361 2200P_0402_ 50V7K
REM_DIODE4_P
VSET_5075
THERMATRIP2#
THERMATRIP3#
THSEL_STRAP
PROCHOT#_EC
1 2
R381 4.7K_040 2_5%R3 81 4.7K_0402_ 5%
5075 Setting for Thermal Design
5075 Setting for Thermal Design
5075 Setting for Thermal Design5075 Setting for Thermal Design
VOL_UP <40 >
LAN_WAKE# <12,28>
HOST_DEBUG_TX <31>
RUNPWROK <36,9>
EN_INVPWR <22>
T123@PAD~D T123@PAD~D
SLICE_PERF_EN <48 >
PCIE_WAKE# <31>
DYN_TUR_CURRNT_SET# <47>
SIO_SLP_S0# <9>
MSDATA <31>
MSCLK <31>
VOL_DOWN <40>
PS_ID <41>
ALW_PWRGD_3V_5V <42>
1.05V_A_PWRGD <44>
VOL_MUTE <40>
ME_SUS_PWR_ACK <9>
1.35V_SUS_PWRGD <4 3>
PM_APWROK <9>
RESET_OUT# <15,9>
PCH_PCIE_WAKE# <9>
PCH_RSMRST# <38>
AC_PRESENT <9>
SIO_PWRBTN# <9>
DOCK_SMB_DAT <34>
DOCK_SMB_CLK <34>
CHARGER_SMBDAT <47>
CHARGER_SMBCLK <47>
USH_SMBDAT <29>
USH_SMBCLK <29>
ACAV_IN <47,48>
ALWON <42>
1 2
1 2
1 2
1 2
C283, C285, C286, C287 Place near U38
VCP <47>
V_SYS <47>
Thermal diode mapping
5075 Channel
DP1/DN1
DP2/DN2
DP4/DN4
Place under CPU
Place C266 close to the Q11 as possible
100P_0402_50V8J
100P_0402_50V8J
C
C
2
C370@
C370@
B
B
1 2
E
E
Q11
Q11
3 1
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
DP2/DN2 for SODIMM on Q13, place Q13 close
to SODIMM and C372 close to Q13
100P_0402_50V8J
100P_0402_50V8J
12
C
C
C372@
C372@
2
B
B
E
E
Q13
Q13
3 1
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
DP4/DN4 for Skin on Q14, place Q14 close to Vcore VR choke.
100P_0402_50V8J
100P_0402_50V8J
@
@
C
C
C373
C373
2
B
B
1 2
E
E
Q14
Q14
3 1
MMBT3904WT1G_SC70-3~D
MMBT3904WT1G_SC70-3~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
12
+1.05V_RUN
12
1 2
+5V_RUN
RB751V40_SC76-2
RB751V40_SC76-2
D1@
D1@
10K_0402_5%
10K_0402_5%
100K_0402_5%
100K_0402_5%
1 2
R334 0_0402_5 %@ R334 0_0 402_5%@
L2N7002WT1G_SC-70-3
R335@
R335@
R342@
R342@
L2N7002WT1G_SC-70-3
1
D
D
2
G
G
S
S
3
DYN_TUR_CURRNT_SET#
BAY_SMBDAT
BAY_SMBCLK
DDR_HVREF_RST_GATE
GPU_SMBDAT
GPU_SMBCLK
CARD_SMBCLK
CARD_SMBDAT
THERMATRIP3#
DEVICE_DET#
POA_WAKE#
VCI_IN2#
HOST_DEBUG_RX
CHARGER_SMBDAT
CHARGER_SMBCLK
PCH_RSMRST#
+3.3V_ALW
8.2K_0402_5%
8.2K_0402_5%
12
R402
R402
THERMATRIP2#
MMST3904-7-F_SOT323-3
MMST3904-7-F_SOT323-3
1
C
C
2
Q12
Q12
B
B
E
E
3
THSEL_STRAP
R383 1K_040 2_5%R383 1 K_0402_5%
1: Channel 1 will provide Thermistor Readings
0: Channel 1 will provide Diode Readings
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Doc ument Number Rev
Size Doc ument Number Rev
Size Doc ument Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Q9@
Q9@
2.2K_0804_ 8P4R_5%
2.2K_0804_ 8P4R_5%
2.2K_0804_ 8P4R_5%
2.2K_0804_ 8P4R_5%
100K_0804 _8P4R_5%
100K_0804 _8P4R_5%
0.1U_0402_25V6
0.1U_0402_25V6
C371
C371
12
1 2
1
RP15
RP15
1
2
3
4 5
RP16
RP16
1
2
3
4 5
RP17
RP17
1
2
3
4 5
RP19
RP19
1
2
3
4 5
10K_8P4R_5 %
10K_8P4R_5 %
1
H_PROCHOT# <46,47,48,9>
+3.3V_ALW
12
R363100K_040 2_5% R363100K_0 402_5%
12
R4532.2K_040 2_5% R4532.2K_0402_ 5%
12
R4522.2K_040 2_5% R4522.2K_0402_ 5%
12
R353100K_040 2_5% R353100K_0 402_5%
8
7
6
8
7
6
8
+RTC_CELL
7
6
+3.3V_ALW
8
7
6
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
MEC5075
MEC5075
MEC5075
LA-9591P
LA-9591P
LA-9591P
37 58Friday, May 17, 2013
37 58Friday, May 17, 2013
37 58Friday, May 17, 2013
0.4
0.4
0.4
5
D D
4
3
2
1
Touch Pad
+3.3V_RUN +3.3V_T P
PJP8
PJP8
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
1 2
DAT_TP_SIO<37>
I2C1_SDA_TCH_PAD<12>
CLK_TP_SIO<37>
I2C1_SCL_TCH_PAD<12>
C C
R444@ 0_0402_5%R444@ 0_0402_5%
1 2
R450@ 0_0402_5%R450@ 0_0402_5%
1 2
R441@ 0_0402_5%R441@ 0_0402_5%
1 2
R449@ 0_0402_5%R449@ 0_0402_5%
+3.3V_TP
4.7K_0402_5%
4.7K_0402_5%
12
12
4.7K_0402_5%
4.7K_0402_5%
12
R404
R404
R405
R405
TP_DATA
TP_CLK
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
12
C377@
C377@
C378@
C378@
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
12
12
C379@
C379@
C380@
C380@
Keyboard
JKBTP1
JKBTP1
18
GND2
17
GND1
16
KB_DET#<12>
+5V_RUN
+3.3V_ALW
BC_INT#_ECE1117<37>
BC_DAT_ECE1117<37>
BC_CLK_ECE1117<37>
+3.3V_TP
TP_DATA
TP_CLK
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
CONN@
CONN@
ACES_50506-01641-P01
ACES_50506-01641-P01
+5V_RUN+3.3V_ALW+3.3V_T P
0.1U_0402_25V6
0.1U_0402_25V6
12
C374@
C374@
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
12
C375@
C375@
Place close to JKBTP1
C376@
C376@
EMI depop location
RSMRST circuit
1 2
+5V_ALW
33_0402_5%
33_0402_5%
12
R411
R411
U41
U41
1
VCC
RESET#
2
GND
RT9818A-44GU3_SC70-3
RT9818A-44GU3_SC70-3
3
12
+5V_ALW_U41
0.01U_0402_16V7K
0.01U_0402_16V7K
C387
C387
B B
RSMRST#
+3.3V_ALW
10K_0402_5%
10K_0402_5%
12
R440
R440
PCH_RSMRST#<37>
R414@ 0_0402_5%R414@ 0_0402_5%
+3.3V_ALW
1 2
0.1U_0402_25V6
0.1U_0402_25V6
5
1
P
B
4
O
2
A
G
3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
C386@
C386@
1 2
R413@ 0_0402_5%R413@ 0_0402_5%
U42
U42
PCH_RSMRST#_Q <9>
@IO FFC
@IO FFC
Part Number
Part Number
DA30000GZ00 FPC 0VN LF-9591P REV0 M/B-IO/B
DA30000GZ00 FPC 0VN LF-9591P REV0 M/B-IO/B
@eDP TS Cable
@eDP TS Cable
Part Number
Part Number
DC02C004S00 H-CONN SET 0VN MB-LCD-LED-CAM-TS
DC02C004S00 H-CONN SET 0VN MB-LCD-LED-CAM-TS
@eDP Cable
@eDP Cable
Part Number
Part Number
DC02C004T00 H-CONN SET 0VN MB-LCD-LED-CAM
DC02C004T00 H-CONN SET 0VN MB-LCD-LED-CAM
@SATA Cable
@SATA Cable
Part Number
Part Number
DC02C004K00 H-CONN SET 0VN MB-HDD
DC02C004K00 H-CONN SET 0VN MB-HDD
@DC-IN Cable
@DC-IN Cable
Part Number
Part Number
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
@RTC BATT
@RTC BATT
Part Number
Part Number
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
@FAN
@FAN
Part Number Description
Part Number Description
DC28A000800
DC28A000800
Description
Description
Description
Description
Description
Description
Description
Description
Description
Description
Description
Description
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
@MEDIA Board FFC
@MEDIA Board FFC
Part Number
Part Number
NBX0001CW00 FFC 8P G P0.5 PAD0.3 50MM MB-MEDIA/B 0VN
NBX0001CW00 FFC 8P G P0.5 PAD0.3 50MM MB-MEDIA/B 0VN
@KBTP FFC
@KBTP FFC
Part Number
Part Number
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
@NFC Board FFC
@NFC Board FFC
Part Number
Part Number
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
@USH Board FFC
@USH Board FFC
Part Number
Part Number
NBX0001CY00 FFC 20P G P0.5 PAD=0.3 75MM MB-USH/B 0VN
NBX0001CY00 FFC 20P G P0.5 PAD=0.3 75MM MB-USH/B 0VN
@FP FFC
@FP FFC
Part Number
Part Number
NBX0001D100 FFC 6P G P0.5 PAD=0.3 75MM USH/B-FP 0VN
NBX0001D100 FFC 6P G P0.5 PAD=0.3 75MM USH/B-FP 0VN
@Speak
@Speak
Part Number Description
Part Number Description
PK230003Q0L
PK230003Q0L
Description
Description
Description
Description
Description
Description
Description
Description
Description
Description
SPK PACK ZJX 2.0W 4 OHM FG
SPK PACK ZJX 2.0W 4 OHM FG
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Keyboard
Keyboard
Keyboard
LA-9591P
LA-9591P
LA-9591P
38 58Friday, May 17, 2013
38 58Friday, May 17, 2013
38 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
+1.05V_MODPHY +3.3V_ALW_PCH/+1.05V_RUN source
+3.3V_ALW2
100K_0402_5%
100K_0402_5%
2
12
R442
R442
MPHYP_PWR_EN#
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
6
Q124A
Q124A
1
D D
MPHYP_PWR_EN<12>
1 2
R420@ 0_0 402_5%R42 0@ 0_0402_5%
+5V_ALW
5
+1.05V_M +1.05V_MODPHY
10K_0402_5%
10K_0402_5%
12
R445
R445
1.05V_MODPHY_EN
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
34
Q124B
Q124B
Q125
Q125
SI3456DDV-T1-GE3_TSOP6
SI3456DDV-T1-GE3_TSOP6
D
D
6
S
S
45
2
1
G
G
3
2200P_0402_50V7K
2200P_0402_50V7K
C412
C412
12
10U_0603_6.3V6M
10U_0603_6.3V6M
20K_0402_5%
20K_0402_5%
12
C413
C413
12
R447@
R447@
PCH_ALW_ON<37>
RUN_ON<26,36,37>
SIO_SLP_S3#<36,43,9>
1 2
R416@ 0_0402_5%R416@ 0_0402_5%
1 2
R418@ 0_0402_5%R418@ 0_0402_5%
1 2
R417@ 0_0402_5%R417@ 0_0402_5%
+3.3V_ALW
+5V_ALW
+1.05V_M
U43
U43
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
VBIAS
GND
ON2
VIN2
VOUT2
VIN27VOUT2
GPAD
CT1
CT2
4
5
6
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
+3.3V_ALW_PCH
14
13
12
11
10
9
8
15
1 2
C389 0.1U_0402_10 V7KC389 0.1U_0402_ 10V7K
1 2
C390 470P_0402_50 V7KC39 0 470P_0 402_50V7K
1 2
C391 470P_0402_50 V7KC39 1 470P_0 402_50V7K
+1.05V_RUN
0.1U_0402_10V7K
0.1U_0402_10V7K
C393
C393
1 2
+3.3V_SUS/+3.3V_M source
C C
USH_PWR_ON<36>
SIO_SLP_S4#<36,43,9>
SUS_ON<36,43>
SIO_SLP_A#<36,44, 9>
A_ON<37,44>
1 2
R439@ 0_0 402_5%R43 9@ 0_0402_5%
1 2
R421@ 0_0 402_5%R42 1@ 0_0402_5%
1 2
R422@ 0_0402_5%R422@ 0_0402_5%
1 2
R423@ 0_0 402_5%R42 3@ 0_0402_5%
1 2
R424@ 0_0402_5%R424@ 0_0402_5%
+5V_ALW
+3.3V_ALW
U45
U45
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
VBIAS
GND
ON2
VIN2
VOUT2
VIN27VOUT2
GPAD
CT1
CT2
4
5
6
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
+3.3V_SUS
14
13
12
11
10
9
8
15
1 2
C396 0.1U_0402_10V7KC396 0.1U_0402 _10V7K
1 2
C397 470P_0402_50 V7KC39 7 470P_0 402_50V7K
1 2
C398 470P_0402_50 V7KC39 8 470P_0 402_50V7K
+3.3V_M
0.1U_0402_10V7K
0.1U_0402_10V7K
12
C399
C399
B B
A A
+3.3V_RUN/+5V_RUN source
+5V_ALW
SIO_SLP_S3#
RUN_ON
1 2
R425@ 0_04 02_5%R425@ 0_0402_5%
1 2
R426@ 0_04 02_5%R426@ 0_0402_5%
+3.3V_ALW
U46
U46
1
VIN1
VOUT1
2
VIN1
VOUT1
3
ON1
VBIAS
GND
ON2
VIN2
VOUT2
VIN27VOUT2
GPAD
CT1
CT2
4
5
6
TPS22966DPUR_SON14_2X3
TPS22966DPUR_SON14_2X3
+5V_RUN
14
13
12
11
10
9
8
15
1 2
C400 0.1U_0402_10V7KC400 0.1U_0 402_10V7K
1 2
C401 470P_0402_50 V7KC40 1 470P_0 402_50V7K
1 2
C402 1000P_0402_5 0V7KC402 1000 P_0402_50V7K
+3.3V_RUN
0.1U_0402_10V7K
0.1U_0402_10V7K
12
C403
C403
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power control
Power control
Power control
LA-9591P
LA-9591P
LA-9591P
1
39 58Friday, May 17, 2013
39 58Friday, May 17, 2013
39 58Friday, May 17, 2013
0.4
0.4
0.4
5
4
3
2
1
HDD LED solution for White LED
+3.3V_ALW
10K_0402_5%
10K_0402_5%
12
R428
R428
Q24A
Q24B
Q24B
DMN66D0LDW-7_SOT363-6
D D
SATA_ACT#<6>
MASK_SATA_LED#<36>
LED_SATA_DIAG_OUT#<36>
DMN66D0LDW-7_SOT363-6
5
D23
D23
1 2
34
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
D24
D24
1 2
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
MASK_BASE_LEDS#
SYS_LED_MASK#
Q24A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
6
2
Q25B
Q25B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
5
34
+5V_ALW
3
2
1
3
2
1
Q15
Q15
PDTA114EU_SC70-3
PDTA114EU_SC70-3
1 2
SATA_LED
R430 330_0402_5%R430 330_0402_5%
R438 150_0402_5%R438 150_0402_5%
Q26
Q26
PDTA114EU_SC70-3
PDTA114EU_SC70-3
1 2
PANEL_HDD_LED# <22>
LED6
LED6
LTW-193ZDS5_WHITE
LTW-193ZDS5_WHITE
12
Battery LED
BAT2_LED#<36>
BAT1_LED#<36>
Q23B
Q23B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
5
MASK_BASE_LEDS#
Q23A
Q23A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
126
MASK_BASE_LEDS#
+5V_ALW
LED7
LED7
LTW-295DSKS-5A_YEL-WHITE
LTW-295DSKS-5A_YEL-WHITE
1 2
W
W
3 4
Y
Y
BATT_WHITE_LED# <22>
BATT_YELLOW_LED# < 22>
BAT1_LED#_Q
1 2
R427 390_0402_5%R427 390_0402_5%
1 2
R429 220_0402_5%R429 220_0402_5%
1 2
R431 330_0402_5%R431 330_0402_5%
1 2
R433 330_0402_5%R433 330_0402_5%
BATT_YELLOW#
34
BAT2_LED#_Q BATT_WHITE#
WLAN LED solution for White LED
+3.3V_ALW
100K_0402_5%
100K_0402_5%
SYS_LED_MASK#<36>
12
R432
R432
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
MASK_BASE_LEDS#
LID_CL#<35,36>
Q25A
Q25A
1
2
+3.3V_ALW
1
B
2
A
C C
WIRELESS_LED#<31,36>
2
6
C404@
C404@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
5
P
4
O
G
U47
U47
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
+5V_ALW
3
PDTA114EU_SC70-3
PDTA114EU_SC70-3
1
1 2
R435 390_0402_5%R435 390_0402_5%
Q16
Q16
WLAN_LED
LTW-193ZDS5_WHITE
LTW-193ZDS5_WHITE
MASK_BASE_LEDS# <28>
LED5
LED5
12
Breath LED
BREATH_LED#<34,36>
Q28A
Q28A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
126
MASK_BASE_LEDS#
Q28B
Q28B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
BREATH_LED#_Q BREATH_WHITE_LED_SNIFF
34
5
LED1
LED1
LTW-193ZDS5_WHITE
LTW-193ZDS5_WHITE
1 2
Place LED1 close to SW5
1 2
R436 220_0402_5%R436 220_0402_5%
1 2
R434 330_0402_5%R434 330_0402_5%
BREATH_WHITE_LED# <22>
+5V_ALW
B B
POWER & INSTANT ON SWITCH
H_2P8
H_2P8
H17@
H17@
1
H_2P8
H_2P8
X
H18@
H18@
H_2P8
H_2P8
1
EMI CLIP
CLIP1
CLIP1
EMI_CLIP
EMI_CLIP
H21@
H21@
H19@
H19@
H_1P0N
H_1P0N
H_1P0N
H_1P0N
1
1
1
GND
ST2@
ST2@
ST1@
ST1@
CLIP_C5P5
H22@
H22@
H24@
H24@
H23@
H23@
H_2P1X2P6
H_2P1X2P6
H_2P1
H_2P1
1
1
1
CLIP_C5P5
CLIP_C5P5
1
CLIP_C5P5
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
SW1
SW1
1
POWER_SW#_MB<37,9>
Fiducial Mark
FD1@
FD1@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FD2@
FD2@
A A
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FD3@
FD3@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FD4@
FD4@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
5
H_2P8
H_2P8
H1@
H1@
H_2P8
H_2P8
1
2
3
4
SKRBAAE010_4P
SKRBAAE010_4P
LED Circuit Control Table
SYS_LED_MASK# LID_CL#
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11
H2@
H2@
1
H_3P1
H_3P1
H5@
H5@
H6@
H6@
H4@
H4@
H3@
H3@
H_2P8
H_2P8
1
1
H_2P8
H_2P8
H8@
H8@
H_3P1
H_3P1
H_3P8
H_3P8
1
1
1
H_3P8
H_3P8
H11@
H11@
H10@
H10@
H9@
H9@
1
H_3P8
H_3P8
H12@
H12@
H_3P8
H_3P8
H_5P0
H_5P0
1
1
0
1 0
H14@
H14@
H15@
H15@
H13@
H13@
H_2P3
H_2P3
H_2P8
H_2P8
H_2P8
H_2P8
H_2P8
1
H_2P8
1
1
1
4
H16@
H16@
1
Media board CONN
VOL_MUTE<37>
VOL_DOWN<37>
VOL_UP<37>
ACES_50506-00641-P01
ACES_50506-00641-P01
2
1
2
3
4
5
6
JMEDIA
JMEDIA
1
2
3
4
5
6
CONN@
CONN@
7
GND
8
GND
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PAD, LED
PAD, LED
PAD, LED
LA-9591P
LA-9591P
LA-9591P
1
40 58Friday, May 17, 2013
40 58Friday, May 17, 2013
40 58Friday, May 17, 2013
0.4
0.4
0.4
5
4
3
2
1
+COINCELL
COIN RTC Battery
12
PR1
PR1
1K_0402_5%~D
+3.3V_RTC_LDO
D D
1
PD1
PD1
TVNST52302AB0_SOT523-3
TVNST52302AB0_SOT523-3
2
Primary Battery Connector
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
12
PC3
PC3
2200P_0402_50V7K~D
2200P_0402_50V7K~D
C C
@
@
PBATT1
PBATT1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
GND
11
GND
Z4304
Z4305
Z4306
GND
3
1
PD2
PD2
TVNST52302AB0_SOT523-3
TVNST52302AB0_SOT523-3
2
3
PRP2
PRP2
100_0804_8P4R_5%
100_0804_8P4R_5%
PL1
PL1
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
1 2
PL2
PL2
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
PBATT+_C
@
@
0.1U_0603_25V7K~D
18
27
36
45
0.1U_0603_25V7K~D
PBAT_SMBCLK <37>
PBAT_SMBDAT <37>
1 2
12
PC2
PC2
+PBATT
SLICE_BAT_PRES#<34,36,48>
+3.3V_ALW
12
PR2
PR2
100K_0402_5%~D
100K_0402_5%~D
PD4
PD4
1 2
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
BAS40CW SOT-323
BAS40CW SOT-323
@
@
PR6
PR6
1 2
0_0402_5%
0_0402_5%
+5V_ALW
+3.3V_ALW
2
3
PD5
@
PD5
@
DA204U_SOT323~D
PR7
@
PR7
@
change from 0603 to 0402 size PN: SM010028600
PL3
PL3
BLM15AG102SN1D_2P
BLM15AG102SN1D_2P
NB_PSID
B B
12
PR10
PR10
100K_0402_1%~D
100K_0402_1%~D
PR12
PR12
15K_0402_1%~D
15K_0402_1%~D
1 2
1 2
1 2
0_0402_5%~D
0_0402_5%~D
D
D
1 3
G
G
2
C
C
2
PQ3
PQ3
B
B
MMST3904-7-F_SOT323~D
MMST3904-7-F_SOT323~D
E
E
3 1
S
S
PQ2
PQ2
FDV301N_G_NL_SOT23-3~D
FDV301N_G_NL_SOT23-3~D
DA204U_SOT323~D
PR9
PR9
33_0402_5%~D
33_0402_5%~D
1 2
1
+5V_ALW
12
PR11
PR11
10K_0402_1%~D
10K_0402_1%~D
GND
PR13
@
PR13
@
1 2
10K_0402_5%~D
10K_0402_5%~D
PR8
PR8
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2
DOCK_PSID<34> GPIO_PSID_SELECT <36>
NB_PSID_TS5A63157
PSID_DISABLE# <36>
1K_0402_5%~D
Z4012
2
3
PD3
PD3
1
PBAT_PRES# <36,48>
PQ1
PQ1
ME2301D-G 1P SOT-23-3
ME2301D-G 1P SOT-23-3
1 3
1
3
1
3
2
2
2
12
PC4
PC4
1500P_0402_7K~D
1500P_0402_7K~D
PU111
PU111
1
NO
2
GND
NC3COM
TS5A63157DCKR_SC70-6~D
TS5A63157DCKR_SC70-6~D
+COINCELL
+RTC_CELL
1
PC1
PC1
1U_0603_10V4Z~D
1U_0603_10V4Z~D
2
DOCK_SMB_ALERT# <34,36,48>
6
IN
5
+5V_ALW
V+
4
PS_ID <37>
JRTC1
@
JRTC1
@
1
3
1
G
4
22G
TYCO_2-1775293-2~D
TYCO_2-1775293-2~D
DC_IN+ Source
+DC_IN
PL4
PL4
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
1 2
PQ6B
PQ6B
2
12
16
PR16
PR16
@
@
4.7K_0805_5%~D
4.7K_0805_5%~D
DCX124EK-7-F PNP/NPN_SC74-6~D
DCX124EK-7-F PNP/NPN_SC74-6~D
PC9
PC9
1000P_0603_50V7K~D
1000P_0603_50V7K~D
@
@
12
@
@
PJP1
PJP1
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
1
12
PD6
PD6
2
PC11
PC11
@
@
VZ0603M260APT_0603
VZ0603M260APT_0603
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
ACES_50299-00501-003
ACES_50299-00501-003
7
GND
6
GND
5
-DCIN_JACK
5
4
4
3
+DCIN_JACK
3
@
@
PJPDC1
PJPDC1
2
2
1
1
12
PC12
PC12
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
5
A A
PQ6A
PQ6A
5
+DC_IN
DCX124EK-7-F PNP/NPN_SC74-6~D
DCX124EK-7-F PNP/NPN_SC74-6~D
4 3
AC_DIS <36,48>
12
PC5
PC5
PR14
PR14
1 2
1M_0402_5%~D
1M_0402_5%~D
0.022U_0805_50V7K~D
0.022U_0805_50V7K~D
4
FDMC6679AZ_MLP8-5
FDMC6679AZ_MLP8-5
1
2
3 5
1 2
10K_0402_5%~D
10K_0402_5%~D
12
PR18
PR18
1M_0402_5%~D
1M_0402_5%~D
PR17
PR17
PQ4
PQ4
4
SOFT_START_GC <48>
12
12
PC7
PC7
PC6
PC6
@
@
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
+DC_IN_SS
12
12
PC8
PC8
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
12
PC10
PC10
PR15
PR15
10U_0805_25V6K
10U_0805_25V6K
100K_0402_5%~D
100K_0402_5%~D
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+DCIN
+DCIN
+DCIN
LA-9591P
LA-9591P
LA-9591P
1
41 57Friday, May 17, 2013
41 57Friday, May 17, 2013
41 57Friday, May 17, 2013
0.4
0.4
0.4
A
B
C
D
E
1 1
PJP100
@
PJP100
@
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PL100
PL100
1UH_PCMB053T-1R0MS_7A_20%
1UH_PCMB053T-1R0MS_7A_20%
2 2
+PWR_SRC
+3.3V_ALWP
12
PC113
PC112
PC112
@
@
3 3
PC113
0.1U_0603_25V7K
0.1U_0603_25V7K
@
@
20130510:
PC113_X76 to control
X7651731L21 for ECAP MAIN
X7651731L22 for ECAP 2ND
+DC1_PWR_SRC
12
12
PC108
PC108
PC105
PC105
@
@
@
@
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
PL101
PL101
2.2UH_ETQP3W2R2WF N_8.5A_20%
2.2UH_ETQP3W2R2WF N_8.5A_20%
1
+
+
2
220U_6.3V_R18M
220U_6.3V_R18M
680P_0603_50V7K
680P_0603_50V7K
12
PC107
PC107
@
@
10U_0805_25V6K
10U_0805_25V6K
12
@
@
PC111
PC111
PR111
@
PR111
@
4.7_1206_5%
4.7_1206_5%
12
PC104
PC104
10U_0805_25V6K
10U_0805_25V6K
12
12
12
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
PQ100
PQ100
ALW_PWRGD_3V_ 5V<37>
3 5
241
PQ102
PQ102
FDMC7692S_POWER33-8-5
FDMC7692S_POWER33-8-5
3 5
241
+3.3V_ALW
100K_0402_1%~D
100K_0402_1%~D
@
@
PR108
PR108
1 2
0_0402_5%
0_0402_5%
PC109
PC109
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
PR107
PR107
+3.3V_ALW2
PR100
PR100
6.49K_0402_1%~D
6.49K_0402_1%~D
1 2
PR102
PR102
10K_0402_5%~D
10K_0402_5%~D
1 2
PR105
PR105
20K_0402_1%~D
20K_0402_1%~D
1 2
1 2
PR110
PR110
2.2_0603_5%
2.2_0603_5%
1 2
EN
PGOOD_3V_5V
UG_3V
BST_3V
SW2
LG_3V
+DC1_PWR_SRC
@
@
0_0402_5%
0_0402_5%
PU100
PU100
6
7
10
9
8
PR103
PR103
EN2
PGOOD
DRVH2
VBST2
SW2
12
PC100
PC100
1 2
4.7U_0603_10V6K
4.7U_0603_10V6K
2
3
4
5
CS2
VFB2
VREG3
TPS51285BRUKR QFN 20P
TPS51285BRUKR QFN 20P
DRVL211VIN12VREG5
13
20
EN
12
PC117
PC117
PC118
PC118
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0603_10V6K
4.7U_0603_10V6K
PR101
PR101
15K_0402_1%
15K_0402_1%
PR104
PR104
10K_0402_5%~D
10K_0402_5%~D
1
CS1
VFB1
VCLK
DRVH1
VBST1
DRVL1
EN1
15
12
1 2
PAD
VO1
SW1
12
12
PR106
PR106
16.9K_0402_1%
16.9K_0402_1%
21
14
19
16
UG_5V
17
BST_5V
18
SW1
LG_5V
+5V_ALW2
PR114
PR114
200_0402_1%
200_0402_1%
12
PR109
PR109
2.2_0603_5%
2.2_0603_5%
1 2
PC110
PC110
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
FDMC7692S_POWER33-8-5
FDMC7692S_POWER33-8-5
PQ103
PQ103
PQ101
PQ101
3 5
241
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
3 5
241
+DC1_PWR_SRC
12
12
PC106
PC106
PC102
PC101
PC101
@
@
0.1U_0402_25V6
0.1U_0402_25V6
PC102
@
@
2200P_0402_50V7K
2200P_0402_50V7K
3.3UH_ETQP3W3R3W FN_7A_20%
3.3UH_ETQP3W3R3W FN_7A_20%
1 2
12
@
@
PC114
PC114
680P_0603_50V7K
680P_0603_50V7K
12
@
@
PR112
PR112
4.7_1206_5%
4.7_1206_5%
12
12
PC103
PC103
@
@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PL102
PL102
PC115
PC115
@
@
20130510:
PC115_X76 to control
X7651731L21 for ECAP MAIN
X7651731L22 for ECAP 2ND
220U_6.3V_R18M
220U_6.3V_R18M
1
+
+
2
+5V_ALWP
12
PC116
PC116
@
@
0.1U_0603_25V7K
0.1U_0603_25V7K
+3.3V_RTC_LDO
3VALWP
TDC 6.7 A
Peak Current 8.1 A
OCP Current 9.72 A
ALWON<37>
Rds(on): 13.6m ohm (max)
4 4
A
B
EN
PR113
@
PR113
@
0_0402_5%
0_0402_5%
12
+5V_ALWP
+3.3V_ALWP
12
PC119
PC119
@
@
1U_0603_10V6K
1U_0603_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
PJP101
PJP101
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PJP102
PJP102
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
+5V_ALW
+3.3V_ALW
5VALWP
TDC 4.88 A
Peak Current 6.89 A
OCP Current 8.268 A
Rds(on):13.6m ohm (max)
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
LA-9591P
LA-9591P
LA-9591P
42 57Friday, May 17, 2013
42 57Friday, May 17, 2013
42 57Friday, May 17, 2013
E
0.4
0.4
0.4
5
4
3
2
1
1.35Volt +/- 5%
TDC: 7.2 A
Peak Current: 10 A
OCP current: 12 A
Rds(on): 13.6m ohm(max)
PJP200
+PWR_SRC
D D
+1.35V_MEN_P
C C
20130510:
PC207_X76 to control
X7651731L21 for ECAP MAIN
X7651731L22 for ECAP 2ND
B B
Mode S3 S5 +1.5V_MEN +V_DDR_REF +0.75V_P
S5 L L off off off
S3 L H on on off(Hi-Z)
S0 H H on on on
PJP200
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
330U_2.5V_ESR16M
330U_2.5V_ESR16M
@
@
1
PC207
PC207
+
+
2
1.35V_B+
12
12
PC200
PC200
4.7U_0805_25V6K~ D
4.7U_0805_25V6K~ D
PL200
PL200
1UH_PCMB063T-1R0MS_ 12A_20%
1UH_PCMB063T-1R0MS_ 12A_20%
1 2
12
PC208
@
PC208
@
680P_0603_50V7 K
680P_0603_50V7 K
SNUB_1.35V
12
@
@
PR203
PR203
4.7_1206 _5%
4.7_1206 _5%
SIO_SLP_S4#<36,39,9>
SUS_ON<36,39 >
12
PC202
PC202
PC201
PC201
@
@
4.7U_0805_25V6K~ D
4.7U_0805_25V6K~ D
FDMC8884_POW ER33-8-5
FDMC8884_POW ER33-8-5
FDMC7692S_POW ER33-8-5
FDMC7692S_POW ER33-8-5
0.1U_0402_25V6
0.1U_0402_25V6
12
PC203
PC203
@
@
1.35V_SUS_PW RGD<37>
@
@
0_0402_5%~D
0_0402_5%~D
1 2
1 2
2200P_0402_50V 7K~D
2200P_0402_50V 7K~D
PQ200
PQ200
PQ201
PQ201
PR207
PR207
PR208
@
PR208
@
0_0402_5%
0_0402_5%
3 5
241
3 5
241
100K_0402_1%~D
100K_0402_1%~D
12
PC215
@
PC215
@
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
1 2
PC204
PC204
0.22U_0603_16V7K ~D
0.22U_0603_16V7K ~D
+5V_ALW
+3.3V_ALW
12
PR204
PR204
PR200
PR200
1 2
2.2_0603_5%~D
2.2_0603_5%~D
PR202
PR202
1 2
5.1_0603_5%~D
5.1_0603_5%~D
S5_1.35V
BOOT_1.35V
PR201
PR201
23.7K_0402_1%
23.7K_0402_1%
1 2
PC209
PC209
1U_0603_10V6K~D
1U_0603_10V6K~D
PC211
PC211
1U_0603_10V6K~D
1U_0603_10V6K~D
DH_1.35V
SW_ 1.35V
DL_1.35V
CS_1.35V
VDD_1.35 V
+5V_ALW
1.35V_SUS_PW RGD
1.35V_B+
0.675V_DDR_VTT_ON<18>
SIO_SLP_S3#<36,39,9>
16
15
LGATE
14
PGND
13
CS
RT8207MZQW _WQFN20_3X3
RT8207MZQW _WQFN20_3X3
12
VDDP
11
VDD
10
PR206
PR206
1 2
1M_0402_1%~D
1M_0402_1%~D
@
@
PR210
PR210
1 2
0_0402_5%
0_0402_5%
@
@
PR211
PR211
1 2
0_0402_5%~D
0_0402_5%~D
+1.35V_MEN_P
PJP201
PJP201
+VLDOIN_1.35V
18
17
PHASE
UGATE
PGOOD
TON
8
9
20
19
PU11
PU11
21
VTT
BOOT
S5
PAD
VTTGND
VTTSNS
GND
VTTREF
VDDQ
FB
6
1.35V_FB
1
2
3
4
5
VLDOIN
S3
7
12
+1.35V_MEN_P
PAD-OPEN1x1m
PAD-OPEN1x1m
+V_DDR_ REF
+1.35V_MEN_P
FB sense trace
when FB pull down to GND
PR205
PR205
8.06K_04 02_1%~D
8.06K_04 02_1%~D
12
PC213
PC213
100P_0402_50V8 J~D
100P_0402_50V8 J~D
12
PR209
PR209
10K_040 2_1%
10K_040 2_1%
1 2
12
@
@
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A
12
PC205
PC205
22U_0805_6.3V6M
22U_0805_6.3V6M
PC214
PC214
+0.675V_P
+V_DDR_REF
PC212
PC212
0.033U_0402_16V7 ~D
0.033U_0402_16V7 ~D
FB sense trace
PJP203
PJP203
2
112
JUMP_1x3m
JUMP_1x3m
PJP204
PJP204
+1.35V_MEN_P
A A
2
JUMP_1x3m
JUMP_1x3m
112
+1.35V_MEM
+0.675V_P
PJP202
PJP202
12
PAD-OPEN1x1m
PAD-OPEN1x1m
+0.675V_DDR_VTT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sh eet of
Date: Sh eet of
Date: Sh eet of
Compal Electronics, Inc.
+1.35V_MEN/+0.675V_DDR_VTT
+1.35V_MEN/+0.675V_DDR_VTT
+1.35V_MEN/+0.675V_DDR_VTT
LA-9591P
LA-9591P
LA-9591P
43 57Friday, May 17, 2013
43 57Friday, May 17, 2013
43 57Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
+V1.05SP_B+
PJP300
PJP300
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
1
+PWR_SRC
12
D D
1.05V_A_PWRGD<3 7>
PR302
PR302
1 2
95.3K_0402_1%
95.3K_0402_1%
@
@
PR303
PR303
SIO_SLP_A#<36,39,9>
S0 mode be high level
C C
A_ON<37,39>
1 2
0_0402_5%~D
0_0402_5%~D
PR304
@
PR304
@
1 2
0_0402_5%
0_0402_5%
0.1U_0402_16V7K
0.1U_0402_16V7K
@
@
PC308
PC308
12
+3.3V_ALW
TRIP_+V1.05SP
EN_+V1.05SP
FB_+V1.05SP
RF_+V1.05SP
12
PR305
PR305
470K_0402_1%
470K_0402_1%
12
PR300
PR300
100K_0402_1%~D
100K_0402_1%~D
4.99K_0402_1%
4.99K_0402_1%
PU300
PU300
1
2
3
4
5
VBST
PGOOD
TRIP
DRVH
EN
VFB
RF
TPS51212DSCR_SON10_3X3
TPS51212DSCR_SON10_3X3
PR307
PR307
SW
V5IN
DRVL
TP
12
10
9
8
7
6
11
BST_+V1.05SP
UG_+V1.05SP
SW_+V1.05SP
LG_+V1.05SP
+5V_ALW
12
PC305
PC305
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
PR301
PR301
2.2_0603_5%
2.2_0603_5%
1 2
PC304
PC304
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
PQ301
FDMC7692S_POWER33-8-5
FDMC7692S_POWER33-8-5
PQ301
PQ300
PQ300
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
3 5
241
3 5
241
12
@
@
680P_0603_50V7K
680P_0603_50V7K
12
@
@
4.7_1206_5%
4.7_1206_5%
12
PC300
PC300
PC301
PC301
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
@
@
@
@
2.2UH_ETQP3W2R2 WFN_8.5A_20%
2.2UH_ETQP3W2R2 WFN_8.5A_20%
1 2
PC306
PC306
PR306
PR306
PL300
PL300
@
@
12
12
10U_0805_25V
10U_0805_25V
PC303
PC303
PC302
PC302
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
+1.05V_MP
1
+
+
PC307
PC307
220U_B2_2.5VM_R15M
220U_B2_2.5VM_R15M
2
+1.05Volt +/- 5%
B B
PR308
PR308
10K_0402_1%
10K_0402_1%
1 2
+1.05V_MP
PJP301
PJP301
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
+1.05V_M
TDC 3.67 A
Peak Current 5.25 A
OCP current 6.3 A
Rds(on): 13.6m ohm (max)
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Doc ument Numb er Rev
Size Doc ument Numb er Rev
Size Doc ument Numb er Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.05V_M
+1.05V_M
+1.05V_M
LA-9591P
LA-9591P
LA-9591P
44 57Friday, May 17, 2013
44 57Friday, May 17, 2013
44 57Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
D D
+3.3V_RUN
PR400
PR400
1 2
100K_0402_5%~D
100K_0402_5%~D
@
@
PR401
PR401
47K_0402_5%
47K_0402_5%
C C
B B
12
12
@
@
0.1U_0402_16V7K
0.1U_0402_16V7K
PC402
PC402
7
POK
8
EN
+5V_ALW
6
VCNTL
GND
1
PAD-OPEN1x1m
PAD-OPEN1x1m
12
PC400
PC400
1U_0402_6.3V6K
1U_0402_6.3V6K
5
VIN
4
VOUT
3
VOUT
2
FB
9
VIN
PU400
PU400
APL5930KAI-TRG_SO8
APL5930KAI-TRG_SO8
PJP400
PJP400
+3.3V_RUN
12
12
PC401
PC401
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
PR402
PR402
1.54K_0402_1%
1.54K_0402_1%
+3.3V_ALW
12
@
@
PAD-OPEN1x1m
PAD-OPEN1x1m
12
12
PR403
PR403
1.74K_0402_1%
1.74K_0402_1%
PJP402
PJP402
1.5VSP
12
PC403
PC403
0.01U_0402_25V7K
0.01U_0402_25V7K
12
PC404
PC404
22U_0805_6.3V6M
22U_0805_6.3V6M
PJP401
PJP401
PAD-OPEN1x1m
PAD-OPEN1x1m
12
+1.5V_THERMAL
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
<Issued_Date> <Deciphered_Date>
<Issued_Date> <Deciphered_Date>
<Issued_Date> <Deciphered_Date>
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
+1.05VS_VTTP/+1.0VSP
+1.05VS_VTTP/+1.0VSP
+1.05VS_VTTP/+1.0VSP
Chief River VC
1
0.4
0.4
45 57Friday, May 17, 2013
45 57Friday, May 17, 2013
45 57Friday, May 17, 2013
0.4
5
4
20120911 TI-Alex Note: Although there is no pulse-overlap in 1-phase mode, during USR, the pulse comes in immediately.
So, the problem with PR504 = DNP is that if there is a high ripple, and USR is faultily detected, you will get a double-pulse.
So, we want to make sure USR is not active if it is not necessary. So, I moved it all the way to highest level so PR504 works to 8.87k.
3
2
1
VREF
100K_0402_1%_NCP15WF104F03RC
100K_0402_1%_NCP15WF104F03RC
12
PH500
PR505
PR505
PU500
PU500
17
CSP1
18
CSN1
19
CSN2
20
CSP2
21
PU3
22
N/C
23
GFB
24
VFB
PR521
PR521
1 2
2.32K_0402_1%
2.32K_0402_1%
10_0603_1%
10_0603_1%
H_PROCHOT#<37,47,48,9>
10K_0402_5%~D
10K_0402_5%~D
PR526
PR526
1 2
VREF
PC507
PC507
PH500
12
PC501
PC501
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
15
16
14
13
VBAT
SLEWA
THERM
COMP26VCLK31V5A28DROP
25
29
27
1 2
12
1 2
@
@
PR500
PR500
75_0402_1%
75_0402_1%
1 2
D D
+VCC_PWR_SRC
SLEWA
PR510
PR510
39K_0402_5%~D
39K_0402_5%~D
PR511
PR511
1 2
10K_0402_5%~D
10K_0402_5%~D
CSN1
1 2
CSP1
+3.3V_RUN
+3.3V_RUN
VFB
GFB
C C
PC506
@ PC506
@
1 2
100P_0402_50V8~D
100P_0402_50V8~D
PR523
PR523
1 2
10K_0402_5%~D
10K_0402_5%~D
1 2
1 2
0.33U_0603_10V7K~D
PR535
PR535
4.87K_0402_1%
4.87K_0402_1%
PC512
PC512
1500P_0402_50V7K
1500P_0402_50V7K
0.33U_0603_10V7K~D
+5V_ALW
+1.05V_VCCST
B B
12
12
PR528
PR528
PR527
PR527
@
@
75_0402_1%
75_0402_1%
54.9_0402_1%
VIDSCLK<15>
VIDALERT_N<15>
VIDSOUT<15>
54.9_0402_1%
12
12
PR529
PR529
110_0402_1%
110_0402_1%
1 2
PC500
PC500
4700P_0603_50V7K
4700P_0603_50V7K
12
11
10
9
IMON
OCP-I
F-IMAX
B-RAMP
ALERT#
GND33GND
VR_HOT#30VREF
32
VR_HOT#
12
PC510
PC510
1U_0603_10V7K~D
1U_0603_10V7K~D
PC511
PC511
0.1U_0402_25V6
0.1U_0402_25V6
IMON
OCP-I
O-USR
VR_ON
SKIP#
PWM1
PWM2
N/C
PGOOD
VDD
VDIO
TPS51622RSM
TPS51622RSM
PR534
PR534
@
@
0_0402_5%
0_0402_5%
1 2
PC514
PC514
47P_0402_50V8J~D
47P_0402_50V8J~D
8
7
6
5
4
3
2
1
VIDSCLK
PR501
PR501
1 2
365K_0402_1%
365K_0402_1%
PR506
PR506
1 2
75K_0402_1%
75K_0402_1%
@
@
PR537 0_0402_5%
PR537 0_0402_5%
VIDSOUT
VIDALERT_N
B-RAMP
@
@
PR536
PR536
0_0402_5%
0_0402_5%
SKIP#
PWM1
@
@
1 2
PR502
PR502
1 2
75_0402_1%
75_0402_1%
F-IMAX
PR507
PR507
1 2
150K_0402_1%
150K_0402_1%
12
12
@
@
PR513
PR513
1 2
75_0402_1%
75_0402_1%
@ PR516
@
1 2
1.91K_0402_1%~D
1.91K_0402_1%~D
PR519
PR519
12
1_0603_5%
1_0603_5%
PC505
PC505
1U_0603_10V6K
1U_0603_10V6K
VCCSENSE<15>
from processor
VSSSENSE<17>
PR503
PR503
1M_0402_1%
1M_0402_1%
1 2
O-USR
PR508
PR508
1 2
150K_0402_1%
150K_0402_1%
H_VR_EN <15>
IMVP_VR_ON <36>
PR516
+3.3V_RUN
PR504
PR504
1 2
8.87K_0402_1%
8.87K_0402_1%
PR509
PR509
1 2
150K_0402_1%
150K_0402_1%
@
@
PR539
PR539
0_0402_5%
0_0402_5%
@
@
PR540
PR540
0_0402_5%
0_0402_5%
+3.3V_RUN
+PWR_SRC
12
H_VR_READY <15>
12
IMVP_PWRGD <36>
PWM1
@
@
PR531
PR531
0_0402_5%
0_0402_5%
PR532
PR532
@
@
0_0402_5%
0_0402_5%
PJP500
@ PJP500
@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
1 2
FBMA-L11-453215-121LMA90T
FBMA-L11-453215-121LMA90T
+VCC_PWR_SRC
PL501
PL501
PC503
PC503
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1 2
TI recommend 1nF
12
VFB
12
GFB
12
12
PC731
PC731
PC736
PC736
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PC504
PC504
1 2
0.1U_0402_25V6
0.1U_0402_25V6
0_0603_5%~D
0_0603_5%~D
CPU
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DCR: 0.82m +-5% ohm
PH500 B value: 4250k 1%
PH501 B value: 3435k 1%
12
12
PC734
PC734
PC732
PC732
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
9
8
7
6
12
5
PR517
PR517
CSD97374CQ4M_SON8_3P5X4P5
CSD97374CQ4M_SON8_3P5X4P5
1
+
+
PC735
PC735
@
@
2
PU501
PU501
PGND2
PWM
VSW
BOOT
PGND1
BOOT_R
SKIP#
VIN
1U_0603_10V7K~D
1U_0603_10V7K~D
VDD
1
1
+
+
+
+
PC738
PC738
PC739
PC739
2
2
@
@
330U_2.5V_ESR17M
100U_D3L_20VM_R55M
100U_D3L_20VM_R55M
1 2
PR520
PR520
1 2
0_0402_5%@
0_0402_5%@
330U_2.5V_ESR17M
SKIP#SKIP#1
+5V_RUN
2.1K_0402_1%~D
2.1K_0402_1%~D
PL500
PL500
0.22UH_FDUE0640J-H-R22M=P3_25A_20%
0.22UH_FDUE0640J-H-R22M=P3_25A_20%
4
12
3
PR522
PR522
@
@
4.7_1206_5%~D
4.7_1206_5%~D
12
PC508
PC508
@
@
680P_0603_50V7K~D
680P_0603_50V7K~D
PR512
PR512
12
12
PR514
PR514
43.2K_0402_1%
43.2K_0402_1%
+VCC_CORE
1
2
CSP1
12
PH501
PH501
12
1 2
1 2
PC502
PC502
0.068U_0402_16V7K
0.068U_0402_16V7K
PC513
PC513
0.068U_0402_16V7K
PR515
PR515
3.01K_0402_1%
3.01K_0402_1%
10K_0402_1%_TSM0A103F34D1RZ
10K_0402_1%_TSM0A103F34D1RZ
0.068U_0402_16V7K
CSN1
33U_D_25VM_R60M
33U_D_25VM_R60M
4
3
2
1
PC509
PC509
A A
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+VCC_CORE
+VCC_CORE
+VCC_CORE
LA-9591P
LA-9591P
LA-9591P
46 57Friday, May 17, 2013
46 57Friday, May 17, 2013
46 57Friday, May 17, 2013
1
0.4
0.4
0.4
5
PQ700 V30415-T1-GE3 1P POWERPAK1212-8PQ700 V30415-T1-GE3 1P POWERPAK1212-8
+DC_IN_SS
D D
1
2
35
4
@
@
PR701
PR701
1 2
0_0402_5%
0_0402_5%
+DOCK_PWR_BAR
+CHGR_DC_IN<48>
+SDC_IN
PR713
PR713
261K_0402_1%
261K_0402_1%
PR714
PR714
49.9K_0402_1%~D
49.9K_0402_1%~D
C C
ACAV_IN<37,47,48>
12
PR747
PR747
100K_0402_1%~D
100K_0402_1%~D
12
PR746
PR746
121K_0402_1%~D
121K_0402_1%~D
GNDA_CHG
BQ24715_REGN
V_SYS<37>
GNDA_CHG
12
12
PC708 0.1U_0402_25V6PC708 0.1U_0402_25V6
CHARGER_SMBDAT<37>
CHARGER_SMBCLK<37>
@
@
PR717
PR717
1 2
0_0402_5%
0_0402_5%
1 2
GNDA_CHG
CHARGER_CELL_PIN<48>
+3.3V_ALW2
B B
DYN_TUR_CURRENT_SET#
PC724
45W
65W
DYN_TUR_CURRNT_SET#<37>
A A
High
Low
PQ712A
DMN66D0LDW-7 2N SOT363-6
DMN66D0LDW-7 2N SOT363-6
PQ712A
+3.3V_ALW2
12
PR730
PR730
150K_0402_1%
150K_0402_1%
12
12
PR734
PR734
210K_0402_1%
210K_0402_1%
61
2
12
PC726
PC726
PR735
PR735
69.8K_0402_1%
69.8K_0402_1%
100P_0402_50V8J~D
100P_0402_50V8J~D
VCP
PR732
PR732
20K_0402_1%~D
20K_0402_1%~D
1 2
+5V_ALW
PC724
@
@
12
Adapter Protection Circuit for Turbo Mode
5
DC_BLOCK_GC <48>
CSS_GC<48>
+DC_IN_SS
1 2
+3.3V_ALW
PC719
PC719
100P_0402_50V8J~D
100P_0402_50V8J~D
12
12
PC725
PC725
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
3
2
PC727
PC727
220P_0402_50V8J~D
220P_0402_50V8J~D
4
+SDC_IN
PD701
PD701
2
3
BAT54CW_SOT323~D
BAT54CW_SOT323~D
@
@
PR708
PR708
1 2
1_0805_1%~D
1_0805_1%~D
PC706
PC706
10U_0805_25V6K
10U_0805_25V6K
12
BQ24715_REGN
PR729
PR729
1.8M_0402_1%
1.8M_0402_1%
1 2
8
PU2A
PU2A
P
+
1
O
-
G
LM393DR_SO8~D
LM393DR_SO8~D
4
220P_0402_50V8J
220P_0402_50V8J
4
@
@
PR702
PR702
1 2
0_0402_5%
0_0402_5%
1
PR745
PR745
+SDC_IN
1 2
PR726
PR726
@
@
1 2
10K_0402_1%~D
10K_0402_1%~D
PR711
PR711
1 2
10K_0402_1%~D
10K_0402_1%~D
@
@
PR750
PR750
1 2
0_0402_5%
0_0402_5%
@
@
PR751
PR751
1 2
10K_0402_1%~D
10K_0402_1%~D
PR727
PR727
221K_0402_1%~D
221K_0402_1%~D
PC740
PC740
@
@
@
@
12
PC700
PC700
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PQ702
PQ702
NTR4502PT1G_SOT23-3~D
NTR4502PT1G_SOT23-3~D
PC703
PC703
1U_0603_25V6K
1U_0603_25V6K
1 2
12
GNDA_CHG
10_1206_5%~D
10_1206_5%~D
+DCIN
PR725
@
PR725
@
0_0402_5%
0_0402_5%
+5V_ALW
1 2
1 2
61
2
12
0.01_1206_1%~D
0.01_1206_1%~D
4
3
13
D
D
2
G
G
S
S
CSSP_1
10K_0402_5%~D
10K_0402_5%~D
12
PR704
PR704
10_0402_5%~D
10_0402_5%~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
2
PU700
PU700
20
ACP
VCC
3
CMSRC
4
ACDRV
6
ACDET
8
SDA
9
SCL
5
ACOK
7
IOUT
10
CELL
BQ24715RGRR_QFN
BQ24715RGRR_QFN
GNDA_CHG
GNDA_CHG
PR728
@
PR728
@
0_0402_5%
0_0402_5%
DMN66D0LDW-7 2N SOT363-6
DMN66D0LDW-7 2N SOT363-6
PQ710A
PQ710A
3
4
PR700
PR700
PR703
PR703
PC704
PC704
1 2
TP
21
1 2
PQ710B
PQ710B
5
+PWR_SRC_AC
1
2
13
D
D
2
PQ701
PQ701
G
NTR4502PT1G_SOT23-3~D
G
NTR4502PT1G_SOT23-3~D
S
S
CSSN_1
12
12
PR705
PR705
10_0402_5%~D
10_0402_5%~D
PC705
PC705
1 2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
16
ACN
REGN
17
BTST
1 2
18
HIDRV
19
PHASE
15
LODRV
14
GND
13
SRP
12
SRN
11
1 2
/BATDRV
PJP701
PJP701
PAD-OPEN1x1m
PAD-OPEN1x1m
H_PROCHOT# <37,46,48,9>
DMN66D0LDW-7 2N SOT363-6
DMN66D0LDW-7 2N SOT363-6
+3.3V_ALW
5
PU3
PU3
P
B
4
O
A
G
3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
PQ703A
PQ703A
SI3993CDV-T1-GE3_TSOP6~D
SI3993CDV-T1-GE3_TSOP6~D
S
S
G
G
1
12
PR706
PR706
100K_0402_1%~D
100K_0402_1%~D
GNDA_CHG
BQ24715_REGN
PR715
PR715
2.2_0603_5%
2.2_0603_5%
CHG_LGATE
PR722
PR722
4.02K_0402_1%
4.02K_0402_1%
1UH_PCMB042T-1R0MS_4.5A_20%
1UH_PCMB042T-1R0MS_4.5A_20%
@
@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
D
D
65
PQ703B
PQ703B
SI3993CDV-T1-GE3_TSOP6~D
SI3993CDV-T1-GE3_TSOP6~D
S
S
G
G
12
3
PR707
PR707
100K_0402_1%~D
100K_0402_1%~D
PC709
PC709
1 2
1U_0603_10V6K~D
1U_0603_10V6K~D
PD702
PD702
BAT54HT1G_SOD323-2~D
BAT54HT1G_SOD323-2~D
1 2
CHG_UGATE
12
PC713
PC713
0.047U_0603_25V7M
0.047U_0603_25V7M
PQ706
PQ706
SIRA06DP-T1-GE3_POWERPAKSO-8
SIRA06DP-T1-GE3_POWERPAKSO-8
PL700
PL700
PJP700
PJP700
D
D
42
PR709
@
PR709
@
1 2
0_0402_5%
0_0402_5%
4
12
12
PC701
PC701
PC702
PC702
@
@
@
@
47P_0402_50V8J~D
47P_0402_50V8J~D
DOCK_DCIN_IS+ <34>
DOCK_DCIN_IS- <34>
DK_CSS_GC <48>
5
4
123
PQ704
PQ704
SIRA14DP-T1GE3_POWERPAK-SO8-5
SIRA14DP-T1GE3_POWERPAK-SO8-5
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
5
123
12
1 2
PR724
PR724
@
@
BATDRV# <48>
12
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PC707
PC707
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PC714
PC714
@
@
4.7_1206_5%~D
4.7_1206_5%~D
CHAGER_SRC
12
PC710
PC710
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PL701
PL701
1000P_0603_50V7K~D
1000P_0603_50V7K~D
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
GNDA_CHG
12
PC720
PC720
1 2
2
12
PC737
PC737
12
PC711
PC711
22U_0805_25V6M
22U_0805_25V6M
12
10U_0805_25V6K
10U_0805_25V6K
+SDC_IN
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
PC712
PC712
22U_0805_25V6M
22U_0805_25V6M
+PWR_SRC
12
PC716
PC716
1 2
10U_0805_25V6K
10U_0805_25V6K
PC741
PC741
22U_0805_25V6M
22U_0805_25V6M
PR716
PR716
0.01_1206_1%~D
0.01_1206_1%~D
4
3
PR718
PR718
@
@
0_0402_5%
0_0402_5%
PC721
PC721
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1 2
+3.3V_ALW2
+3.3V_ALW
PC728
PC728
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
12
1
2
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
12
PR740
PR740
100K_0402_5%~D
100K_0402_5%~D
PROCHOT_GATE <36>
3
5
PQ712B
PQ712B
4
DMN66D0LDW-7 2N SOT363-6
DMN66D0LDW-7 2N SOT363-6
ACAV_IN <37,47,48>
+DC_IN
12
12
PR737
PR737
PR738
PR738
48.7K_0402_1%
48.7K_0402_1%
232K_0402_1%~D
232K_0402_1%~D
12
12
12
PC729
PC729
100P_0402_50V8J~D
100P_0402_50V8J~D
PR743
PR743
PR742
PR742
42.2K_0402_1%~D
42.2K_0402_1%~D
22.6K_0402_1%~D
22.6K_0402_1%~D
2
PR736
PR736
1M_0402_1%~D
1M_0402_1%~D
1 2
+5V_ALW
5
+
6
-
12
PC730
PC730
100P_0402_50V8J~D
100P_0402_50V8J~D
PC733
PC733
12
PC742
PC742
PR719
PR719
@
@
8
PU2B
PU2B
P
O
G
LM393DR_SO8~D
LM393DR_SO8~D
4
1
sense adapter
PR710
@
PR710
VCP<37>
12
@
1 2
0_0402_5%
0_0402_5%
PU703
PU703
1
Out
REF
2
IN-
GND
3
V+
IN+
INA199A1DCKR_SC70-6~D
INA199A1DCKR_SC70-6~D
6
PR748
PR748
44.2_0402_1%~D
44.2_0402_1%~D
5
4
12
Discrete current monitor circuit
12
@
@
22U_0805_25V6M
22U_0805_25V6M
12
12
PC744
PC744
PC743
PC743
@
@
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
+VCHGR
1
2
12
12
12
PC718
PC718
PC717
PC717
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
12
PC745
PC745
PC746
PC746
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@
@
@
@
PC715
PC715
0_0402_5%
0_0402_5%
1 2
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PC722
PC722
1 2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
GNDA_CHG
BQ24715_REGN
12
PR739
PR739
10K_0402_1%~D
10K_0402_1%~D
@
@
PR741
PR741
7
1 2
0_0402_5%
0_0402_5%
12
PR744
PR744
10K_0402_1%~D
10K_0402_1%~D
ACAV_IN_NB <37,48>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+GPU_CORE
+GPU_CORE
+GPU_CORE
LA-9591P
LA-9591P
LA-9591P
1
PR749
PR749
59_0402_1%
59_0402_1%
CSSN_1
12
CSSP_1
0.4
0.4
47 57Friday, May 17, 2013
47 57Friday, May 17, 2013
47 57Friday, May 17, 2013
0.4
5
+BATT_SUM
PR813
PD800
PD800
PDS5100H-13_POWERDI5-3~D
+VCHGR
PDS5100H-13_POWERDI5-3~D
BATDRV#<47>
D D
C C
B B
+DC_IN
+3.3V_ALW2
ACAV_DOCK_SRC#<34>
+SDC_IN
+3.3V_ALW2
A A
1
PQ800
PQ800
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
1
2
3 6
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
1 2
47_0805_5%~D
47_0805_5%~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
PR846
PR846
SOFT_START_GC<41>
1 2
100K_0402_5%~D
100K_0402_5%~D
PR854
@
PR854
@
1 2
0_0402_5%
0_0402_5%
DC_BLOCK_GC<47>
@
@
PR859
PR859
1 2
ACAV_IN<37,47,48>
0_0402_5%
0_0402_5%
@
@
PR862
PR862
1 2
0_0402_5%
0_0402_5%
3
2
PR835
PR835
PR813
100K_0402_5%~D
100K_0402_5%~D
8
7
5
PD811
PD811
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
PQ812A
PQ812A
PBAT_PRES#<36,41>
12
PC813
PC813
@
@
PR847
PR847
1 2
ACAVDK_SRCACAVDK_SRC
0_0402_5%
0_0402_5%
PC815
PC815
5
1
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
1
2
3 6
1 2
12
PR815
PR815
10K_0402_5%~D
10K_0402_5%~D
1 2
61
2
+DC_IN_SS
+CHGR_DC_IN<47>
CD3301_DCIN
ERC1
12
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PD806
PD806
PDS5100H-13_POWERDI5-3~D
PDS5100H-13_POWERDI5-3~D
3
2
PQ809
PQ809
8
7
5
4
+3.3V_ALW2
PR816
PR816
100K_0402_5%~D
100K_0402_5%~D
1 2
3
5
PQ812B
PQ812B
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PR831
PR831
@
@
0_0402_5%
0_0402_5%
1 2
1 2
PR833
PR833
@
@
0_0402_5%
0_0402_5%
PU800
PU800
1
DC_IN
2
SS_GC
3
ERC1
4
ACAVDK_SRC
5
GND
6
SDC_IN
7
DC_BLK_GC
8
ACAVIN
ACAV_IN
9
P33ALW2
P33ALW2
37
TP
CSS_GC<47>
DK_CSS_GC<47>
12
PC816
PC816
0.047U_0603_25V7M
0.047U_0603_25V7M
+PBATT
SLICE_BAT_ON <36,48>
+3.3V_ALW2
+3.3V_ALW
SLICE_BAT_PRES#<34,36,41,48>
@
@
CHGVR_DCIN
DK_PWRBAR
DC_IN_SS
DSCHRG_MOSFET_GC
28
29
30NC31
33
34
35
36
32
NC
GND
PBatt+
DC_IN_SS
DK_PWRBAR
BLK_MOSFET_GC
DK_AC_OFF_EN
CHARGERVR_DCIN
DSCHRG_MOSFET_GC
DK_AC_OFF_EN
SL_BAT_PRES#
BLKNG_MOSFET_GC
NBDK_DCINSS
SS_DCBLK_GC
CSS_GC10DK_CSS_GC11ERC312ERC213GND14PWR_SRC
EN_DK_PWRBAR17P33ALW
16
15
18
ERC2
ERC3
EN_DK_PWRBAR
12
STSTART_DCBLOCK_GC
PC817
PC817
@
@
3301_PWRSRC
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
1
2
3 6
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
AC_DIS<36,41>
PR832
@
PR832
@
0_0402_5%
0_0402_5%
12
PR841
PR841
12
3301_DSCHRG_FET_GC
0_0402_5%
0_0402_5%
@
@
PR838
PR838
0_0402_5%
0_0402_5%
P50ALW
PBATT_OFF
ACAV_IN_NB
GND
CD3301BRHHR_QFN36_6X6~D
CD3301BRHHR_QFN36_6X6~D
@
@
1 2
P33ALW
0_0402_5%
0_0402_5%
@
@
PR877
PR877
1 2
0_0402_5%
0_0402_5%
PQ811
PQ811
@
@
1 2
0_0402_5%~D
0_0402_5%~D
@
@
1 2
0_0402_5%
0_0402_5%
12
27
26
25
24
23
22
21
20
19
PR868
PR868
+PBATT_IN_SS
FDS6679AZ-G_SO8~D
FDS6679AZ-G_SO8~D
4
820_0603_5%~D
820_0603_5%~D
1 2
12
PC811
PC811
0.01U_0603_25V7K~D
0.01U_0603_25V7K~D
PR894
PR894
PR895
PR895
100K_0402_5%~D
100K_0402_5%~D
PD820
PD820
1 2
PR828
PR828
1 2
10K_0402_5%~D
10K_0402_5%~D
+DOCK_PWR_BAR
+PBATT
P50ALW
CD_PBATT_OFF
DK_AC_OFF
DK_AC_OFF_ENCD3301_SDC_IN
SL_BAT_PRES#
PR874
PR874
1 2
1M_0402_5%~D
1M_0402_5%~D
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
8
1 2
7
330K_0402_5%~D
330K_0402_5%~D
5
PR821
PR821
SI2301CDS-T1-GE3 1P_SOT23-3
SI2301CDS-T1-GE3 1P_SOT23-3
PR830
PR830
2
G
G
PR843
PR843
@
@
0_0402_5%
0_0402_5%
1 2
@
@
PR850
PR850
1 2
0_0402_5%
0_0402_5%
3301_ACAV_IN_NB
+3.3V_ALW
+PWR_SRC_AC
4
PD807
PD807
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
12
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
PR817
PR817
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
3301_DSCHRG_FET_GC
PQ829
PQ829
1
3
1
3
13
12
2
2
2
13
PQ832
PQ832
D
D
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
S
S
+5V_ALW
SLICE_BAT_ON <36,48>
PR855
@
PR855
@
0_0402_5%
0_0402_5%
1 2
1 2
@
@
PR857
PR857
0_0402_5%
0_0402_5%
PR860
PR860
@
@
0_0402_5%
0_0402_5%
1 2
@
@
PR863
PR863
1 2
0_0402_5%
0_0402_5%
13
D
D
S
S
NTR4502PT1G 1P SOT23-3
NTR4502PT1G 1P SOT23-3
PR802
PR802
1 2
12
+3.3V_ALW2
PR804
PR804
61
PQ807A
PQ807A
PQ807B
PQ807B
+DOCK_PWR_BAR
<37,48>
PD815
PD815
2
1
3
BAT54CW_SOT323~D
BAT54CW_SOT323~D
PR858
PR858
1 2
1M_0402_5%~D
1M_0402_5%~D
SLICE_BAT_PRES# <34,36,41,48>
PR866
PR866
0_0402_5%
0_0402_5%
@
@
12
PR856
@
PR856
@
0_0402_5%~D
0_0402_5%~D
2
G
G
PQ827
PQ827
@
@
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
PQ801
PQ801
1
3
1
3
13
2
2
2
12
PR808
PR808
100K_0402_5%~D
100K_0402_5%~D
2
3
5
SLICE_BAT_PRES# <34,36,41,48>
4
PDS5100H-13_POWERDI5-3~D
PDS5100H-13_POWERDI5-3~D
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PQ813B
PQ813B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
PR848
PR848
@
@
1 2
0_0402_5%~D
0_0402_5%~D
SLICE_PERF_EN
<34,36,48>
DOCK_AC_OFF <34>
12
PR844
@
PR844
@
10K_0402_5%~D
10K_0402_5%~D
ACAV_IN_NB <37,47>
DOCK_AC_OFF_EC <36>
EN_DOCK_PWR_BAR <36>
DOCK_DET# <34,36,48>
12
+NBDOCK_DC_IN_SS
PD808
PD808
2
FDS6679AZ-G_SO8~D
FDS6679AZ-G_SO8~D
PQ813A
PQ813A
61
100K_0402_5%~D
100K_0402_5%~D
2
3
PR829
PR829
100K_0402_5%~D
100K_0402_5%~D
5
PR853
PR853
SLICE_BAT_PRES# <34,36,41,48>
@
@
0_0402_5%
0_0402_5%
1 2
1 2
DOCK_DET#
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PQ821B
PQ821B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
5
1 2
SLICE_PERF_EN<37,48>
ME2301D-G 1P SOT-23-3
ME2301D-G 1P SOT-23-3
SLICE_PERF_EN<37,48>
3
+PWR_SRC_AC
PC803
PC803
1 2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PC806
PC806
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PC807
PC807
1 2
0.47U_0805_25V7K~D
0.47U_0805_25V7K~D
36
241
1
578
3
5
123
36
241
PQ815
PQ815
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
PR826
PR826
12
12
+3.3V_ALW2
1 2
100K_0402_5%~D
100K_0402_5%~D
G
G
2
@
@
PR861
PR861
0_0402_5%
0_0402_5%
PQ821A
PQ821A
2
3
PR849
PR849
100K_0402_5%~D
100K_0402_5%~D
@
@
PR851
PR851
0_0402_5%~D
0_0402_5%~D
1 2
<34,36,48>
DOCK_DET#
PQ823
@
PQ823
@
3
3
2
2
@
@
PR869
PR869
1 2
240K_0402_5%~D
240K_0402_5%~D
+3.3V_ALW2
3
@
@
PQ810
PQ810
FDS6679AZ-G_SO8~D
FDS6679AZ-G_SO8~D
PR814
PR814
330K_0402_5%~D
330K_0402_5%~D
PQ826
PQ826
FDMC6679AZ_MLP8-5
FDMC6679AZ_MLP8-5
4
1500P_0402_7K~D
1500P_0402_7K~D
578
12
PD813
PD813
13
2
2
2
PR827
PR827
S
S
PQ828
PQ828
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
D
D
1 3
PR839
PR839
61
100K_0402_5%~D
100K_0402_5%~D
12
+3.3V_ALW2
PR852
@
PR852
@
0_0402_5%
0_0402_5%
1
1
13
2
@
@
PR870
PR870
1 2
47K_0402_5%~D
47K_0402_5%~D
1 2
PR875
@
PR875
@
100K_0402_5%~D
100K_0402_5%~D
PR811
PR811
12
0_0402_5%
0_0402_5%
STSTART_DCBLOCK_GC
12
@
@
12
PC809
PC809
PR818
PR818
1 2
100K_0402_5%~D
100K_0402_5%~D
12
PR822
PR822
10K_0402_5%~D
10K_0402_5%~D
13
D
D
S
S
PQ816
PQ816
AO3418_SOT23-3
AO3418_SOT23-3
1
1
PQ814
PQ814
3
3
NTR4502PT1G 1P SOT23-3
NTR4502PT1G 1P SOT23-3
+NBDOCK_DC_IN_SS
12
12
13
1
1
2
2
2
3
3
PR840
PR840
1 2
100K_0402_5%~D
100K_0402_5%~D
+DC_IN_SS
+NBDOCK_DC_IN_SS
PQ824A
PQ824A
@
@
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
61
@
@
PQ824B
PQ824B
2
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
5
Purpose: Trigger PROCHOT# when
active battery is removed from
system.
Allows EC to re-establish
system performance for battery
next in line.
SLICE_BAT_ON
DIS_BAT_PROCHOT#<36>
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
1 2
PD810
PD810
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
2
G
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
PD814
PD814
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
1 2
PD819
PD819
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
1 2
PD816
PD816
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
PQ822
PQ822
NTR4502PT1G 1P SOT23-3
NTR4502PT1G 1P SOT23-3
12
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
13
1
1
PQ830
PQ830
3
3
NTR4502PT1G_SOT23-3~D
NTR4502PT1G_SOT23-3~D
2
2
2
PR836
PR836
100K_0402_5%~D
100K_0402_5%~D
+PBATT
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
SLICE_BAT_PRES#
SLICE_BAT_ON
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
+3.3V_ALW
12
PR810
PR810
100K_0402_5%~D
100K_0402_5%~D
3
PQ806B
PQ806B
5
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PR812
PR812
@
@
1 2
0_0402_5%
0_0402_5%
+3.3V_ALW2
PU806
PU806
4
PD821
PD821
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
PC810
PC810
12
0.1U_0402_10V7K
0.1U_0402_10V7K
5
1
P
B
@
@
PR820
A
G
3
2
+3.3V_ALW2
PU807
PU807
4
O
PR837
PR837
100K_0402_5%~D
100K_0402_5%~D
2
PR820
1 2
0_0402_5%
0_0402_5%
0.1U_0402_10V7K
0.1U_0402_10V7K
5
P
B
A
G
3
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
12
O
DOCK_SMB_ALERT# <34,36,41>
12
PC801
PC801
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
PC805
PC805
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
PBAT_PRES#
+3.3V_ALW2
PU805
PU805
4
O
ACAV_IN#
PC812
PC812
12
1
SLICE_BAT_ON <36,48>
PR825
@
PR825
@
1 2
2
0_0402_5%
0_0402_5%
PQ831
PQ831
1 3
D
S
D
S
G
G
2
+3.3V_ALW
5
1
P
B
2
A
G
3
PU801
PU801
+3.3V_ALW
1
B
2
A
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
PC808
PC808
0.1U_0402_10V7K
0.1U_0402_10V7K
5
1
P
B
2
A
G
3
+3.3V_ALW2
PQ818
PQ818
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
+3.3V_ALW2
0.1U_0402_10V7K
0.1U_0402_10V7K
5
P
B
4
O
A
G
3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
61
2
4
O
61
PQ806A
PQ806A
2
5
P
4
O
G
PU804
PU804
3
12
SLICE_BAT_PRES# <34,36,41,48>
PR819
PR819
1 2
100K_0402_5%~D
100K_0402_5%~D
13
D
D
2
DOCK_DET# <34,36,48>
G
G
PQ817
PQ817
S
S
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
PR823
PR823
100K_0402_5%~D
100K_0402_5%~D
1 2
13
D
D
2
G
G
S
S
@
@
PR834
PR834
1 2
0_0402_5%
0_0402_5%
PC814
PC814
12
1
SLICE_BAT_PRES# <34,36,41,48>
DOCK_DET# <34,36,48>
2
PU808
PU808
PR801
PR801
100K_0402_5%~D
100K_0402_5%~D
12
PQ802A
PQ802A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
+3.3V_ALW
+3.3V_ALW
12
PR807
PR807
5
61
PQ805A
PQ805A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
2
@
@
PD818
PD818
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
1 2
Purpose: Turn on the PQ817
for primary or module bay
battery to provide power to
dock side without AC exist.
+3.3V_ALW2
+3.3V_ALW2
Purpose: Turn on the PQ817
for Slice battery discharge
without AC exist
@
@
PR824
PR824
100K_0402_5%~D
100K_0402_5%~D
1 2
3
5
ACAV_IN#
PQ819B
PQ819B
@
@
4
61
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
2
SLICE_PERF_EN <37,48>
@
@
PQ819A
PQ819A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
SLICE_BAT_PRES# <34,36,41,48>
@
@
ACAV_IN<37,47,48>
1 2
0_0402_5%
0_0402_5%
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
DELL CONFIDENTI AL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
H_PROCHOT# <37,46,47,9>
3
PQ805B
PQ805B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
CHARGER_CELL_PIN <47>
+3.3V_ALW2
12
PR864
PR864
100K_0402_5%~D
100K_0402_5%~D
ACAV_IN#
13
D
PR872
PR872
D
2
G
G
S
S
PQ825
PQ825
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Selector
Selector
Selector
LA-9591P
LA-9591P
LA-9591P
1
0.4
0.4
48 57Friday, May 17, 2013
48 57Friday, May 17, 2013
48 57Friday, May 17, 2013
0.4
5
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE
4
3
2
1
D D
C C
B B
1
@
@
PC900
PC900
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC905
PC905
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC910
PC910
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC915
PC915
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC901
PC901
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC906
PC906
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC911
PC911
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC921
PC921
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC902
PC902
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC907
PC907
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC912
PC912
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC917
PC917
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC922
PC922
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC903
PC903
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC908
PC908
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC913
PC913
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC918
PC918
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC923
PC923
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC928
PC928
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC904
PC904
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC909
PC909
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC914
PC914
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC919
PC919
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
@
@
PC924
PC924
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
PC930
PC930
+
+
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sh eet of
Date: Sh eet of
Date: Sh eet of
Compal Electronics, Inc.
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
LA-9591P
LA-9591P
LA-9591P
49 57Friday, May 17, 2013
49 57Friday, May 17, 2013
49 57Friday, May 17, 2013
1
0.4
0.4
0.4
5
Request
Request
Item
Item Issue Description
ItemItem
Page# Title
Page#Page#
Title
TitleTitle
Date
DateDate
RequestRequest
Owner
Owner
OwnerOwner
4
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Issue DescriptionDate
Issue DescriptionIssue Description
3
Page 1
Page 1
Page 1Page 1
2
Solution Description
Solution Description Rev.
Solution DescriptionSolution Description
1
Rev.Page#
Rev.Rev.
P45 1.5VSP
1
D D
2
P42 +5V/+3.3V
3
P47 Charger
4
P46 Vcore
5
P48 Selector
P43
6
P42
7
C C
8
P44
1.35V/0.675V 8/17
+5V/+3.3V
+1.05V_MP
+5V/+3.3VP429
B B
10
P47
P48
Charger
Selector
ChargerP4711
12
A A
P46
Vcore
8/17 Compal
8/17 Compal
8/17 Compal
8/17 Compal
8/17 Compal
Compal
10/22
10/22
10/22
10/22
10/22
11/02
Compal
Compal
Compal
Compal
Compal
Compal
Base power budget request, add 1.5V powre rail Add PU400
reserver PR114 for TPS51282 application
schematic control error cause can't set OCP add Vref net for correct connect
in order to meet latest multi-battery request
chagne OCP setting
Reserve 0ohm for 3v5v enable debug
+1.05V_MP EA for ripple portion can't meet
spec. 31.5mv, after change from 1u to 2.2u test is pass
Original 3v5v IC -TPS51225 can't support 2cell battery
follow TI suggestion, When TPS51285A/B is used,
please update the below four components.
1)VREG5 cap to 4.7uF
2)VREG3 cap to 4.7uF
3)CS1 resistor to 1/5 of the Tps51275’s value
4)CS2 resistor to 1/5 of the Tps51275’s value
5)VCLK connection (when not be used): add 200-ohm to GND
To avoid HW and Power SMT materials can't entirely
replace
follow E5- Salado 14"15" schematic 1) @PQ819, @PQ824
follow TI suggestion modify setting value to meet Intel
VR12.6(ULV) validation EA
1) Imon
2) Loadline
3) transient
ADD @PR114
modify SMBus net for correct connectEC can't detect charger IC cause can't charger
change control signal for meet E5 request
change PR201 from 20k to 24.9k.
Change PR113
from SD03420018L (S RES 1/16W 2K +-1% 0402)
to SD028000080 (S RES 1/16W 0 +-5% 0402)
Change PL300
from SH00000PJ00 (S COIL 1UH +-20% PCMB063T-1R0MS 12A)
to SH00000MR00 (S COIL 2.2UH +-20% ETQP3W2R2WFN 8.5A)
Change PU100
from SA00005LS00 (S IC TPS51225CRUKR QFN 20P PWM)
to SA000064T00 (S IC TPS51285BRUKR QFN 20P PWM)
1)2)Change PC118(VREG5 Cap) and PC100(VREG3 Cap)
from SE080105K80(S CER CAP 1U 10V K X5R 0603)
to SE00000MA00(S CER CAP 4.7U 10V K X5R 0603)
3) Change PR106(for CS1)
from SD03484528L (S RES 1/16W 84.5K +-1% 0402)
to SD034169280 (S RES 1/16W 16.9K +-1% 0402)
4) Change PR105(for CS2)
from SD03410038L (S RES 1/16W 100K +-1% 0402)
to SD034200280 (S RES 1/16W 20K +-1% 0402)
5) Add PR114 SD034200080(S RES 1/16W 200 +-1% 0402)
Change PU3,PU801,PU804,PU805,PU806,PU807
from SA74108040L(S IC 74AHC1G08GW SOT353 AND)
to SA00708012L(S IC TC7SH08FU SSOP 5P AND)
2) EMI request for add PL700
SH00000IW00(S COIL 1UH +-20% PCMB042T-1R0MS 4.5A)
1) Change PR501
from SD034422380 (S RES 1/16W 422K +-1% 0402)
to SD034365380 (S RES 1/16W 365K +-1% 0402)
2) Change PR521
from SD000009M80 (S RES 1/16W 2.61K +-1% 0402)
to SD00000WS8L(S RES 1/16W 2.32K +-1% 0402)
3) @PC506 100p_0402 and change PR535
from SD02810028L(S RES 1/16W 10K +-5% 0402)
to SD034487100 (S RES 1/16W 4.87K +-1% 0402 (LF))
X01
X01
X01
X01
X01
X01
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 1
PWR_PIR 1
PWR_PIR 1
LA-9591P
LA-9591P
LA-9591P
50 57Friday, May 17, 2013
50 57Friday, May 17, 2013
50 57Friday, May 17, 2013
1
0.4
0.4
0.4
5
Request
Request
Item
Item Issue Description
ItemItem
D D
C C
Page# Title
Page#Page#
P47 Charger
13 Compal
14
P42
15
16
17
P47 Charger
P47 Charger 11/05
P44
Title
TitleTitle
+5V/+3.3V
+1.05VTTP
Date
DateDate
11/05
11/05
11/05 X01
11/05
RequestRequest
Owner
Owner
OwnerOwner
4
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Issue DescriptionDate
Issue DescriptionIssue Description
1) TI suggestion BQ24715 cell pin pull high 3.3V change
to V_regn(6v) for sequence issue
2) Reserve 0 ohm for debug
Compal
Compal
Compal
Compal
-QAD team
-Huang.Hanks
(PCP)
follow E5- Salado 14"15" schematic
Improve charger efficiency
follow E5- Salado 14"15" schematic
Support QAD WCEPTA analysis, to modify 1.05 OCP Rtrip
resistance to 95K, Cpk value will pass specification.
3
2
Page 1
Page 1
Page 1Page 1
Solution Description
Solution Description Rev.
Solution DescriptionSolution Description
1) Change PR711
from SD02800008L (S RES 1/16W 0 +-5% 0402)
to SD034100280 (S RES 1/16W 10K +-1% 0402)
,add PR750 SD028000080(S RES 1/16W 0 +-5% 0402)
2) Add @PR751
1) @PR863, @PR870, @PR869, @PR824, @PR875, @PQ823
2) Add @PR848, @PR851
and add PR834, PR852, PR853, all is
SD028000080(S RES 1/16W 0 +-5% 0402)
3) Add PR874 SD028100480(S RES 1/16W 1M +-5% 0402)
4) Add PD819 SCS0340L01L(S SCH DIO SDMK0340L-7-F SOD-323)
Change PR715
from SD028200A80 (S RES 1/16W 20 +-5% 0402)
to SD013220B80 (S RES 1/10W 2.2 +-5% 0603)
Delete @PR731, @PR733, @PU702
Change PR302
from SD00000H880 (S RES 1/16W 54.9K +-1% 0402)
to SD034953280 (S RES 1/16W 95.3K +-1% 0402 )
1
Rev.Page#
Rev.Rev.
X01
X01
X01
X01
18
P48
+5V/+3.3V
1.35V/0.675V
11/05
Compal
- EMC team
Wen. Andy
EMC team suggestion
@PC105, @PC203, @PC301
X01
+1.05V_MP
19
B B
20
P47 Charger
P48
A A
21
P41
SelectorP48
Selector
+DCIN
5
11/15
12/12
2013
/01/11
Compal
Compal
CompalÂESD team
follow E5- Salado 14"15" schematic
for undock shutdown issue
ESD team's PD1 vendor(NXP) proposal PD1 pin 5
connected to the VCC (5V or 3.3V).
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
Add
PQ827 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3),
@PR856 SD028000080 (S RES 1/16W 0 +-5% 0402),
PQ816 SB534020000 (S TR AO3402 1N SOT-23),
PQ828 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3),
PR861 SD028000080 (S RES 1/16W 0 +-5% 0402)
PR802, PR827, PR840 change
from SD028240380 (S RES 1/16W 240K +-5% 0402)
to SD028470280 (S RES 1/16W 47K +-5% 0402),
PR804, PR826, PR839 change
from SD028470280 (S RES 1/16W 47K +-5% 0402),
to SD028240380 (S RES 1/16W 240K +-5% 0402)
Change PR713
from SD034294380 (S RES 1/16W 294K +-1% 0402)
to SD034261380 (S RES 1/16W 261K +-1% 0402)
@PR844
PD1 pin5 connect to +3.3V_ALW
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 2
PWR_PIR 2
PWR_PIR 2
LA-9591P
LA-9591P
LA-9591P
1
X01
X01
X01_2
51 57Friday, May 17, 2013
51 57Friday, May 17, 2013
51 57Friday, May 17, 2013
0.4
0.4
0.4
5
Request
Request
Page#
Item
Item Issue Description
ItemItem
D D
Page# Title
Page#Page#
P48
22
Title
TitleTitle
Selector
Date
DateDate
2013/
01/23
RequestRequest
Owner
Owner
OwnerOwner
4
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Issue DescriptionDate
Issue DescriptionIssue Description
Compal
To avoid +DOCK_PWR_BAR leakage voltage when system
only with main battery
3
2
Page 1
Page 1
Page 1Page 1
Solution Description
Solution Description
Solution DescriptionSolution Description
1). Add PU808
P/N: SA007080120 (S IC TC7SH08FU SSOP 5P AND)
2). Add PQ830
P/N: SB000007900 (S TR NTR4502PT1G 1P SOT23-3)
3). Add PQ831
P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3)
4). Add PD821
P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323)
5). Add PR836, PR837
P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
6). Add PC814
P/N: SE102104K00 (S CER CAP 0.1U 10V +-10% X7R 0402)
1
Rev.
Rev.
Rev.Rev.
X01_2
23
24
25
P41
P48
P41
C C
B B
+DCIN
Selector
+DCIN
2013
/02/07
2013/
02/18
2013/
Compal
Compal
Compal-ME
02/18
26
Selector
2013/
CompalP48
PPM-Jovins_Chang and Sourcer-Willie_Zeng highlight
SB000009N8L will shortage after 2013/05
AC_DIS# should be change to AC_DIS because it’s
high active not low active for our application.
DFX highlight Battery connetor(locattion:PBATT1)
hard to insert.
layout spec limit
02/18
27
P41
+DCIN
2013
/02/21
CompalÂESD team
follow ESD team request
Anderson
A A
Change PQ6
From : SB000009N8L (S TR IMD2AT-108 PNP/NPN SC74-62)
To : SB000009P80 (TR DCX124EK-7-F PNP/NPN SC74R-6)
1). Change PQ6A.5 and PR828.1 net name from AC_DIS#
to AC_DIS
2). Add PQ829
P/N: SB00000H500 (S TR SI2301CDS-T1-GE3 1P SOT23-3)
, PQ832
P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3)
, PD820
P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323)
, @PR894
, PR895
P/N: SD028000080 (S RES 1/16W 0 +-5% 0402)
3). modify PR828,PR830
4). Delete PQ820
5). Delete PL5, add PJP1
Battery connetor(locattion:PBATT1) footprint follow
ME team Iris requesti to change
from SUYIN_200277GR009M262ZR_9P-T
to ALLTO_C144LS-109A9-L_9P-T
Delete PD817, modify PD815 footprint same as PD701,
from SDMK0340L-7-F_SOD323-2
to RB717F_SOT323-3
Goliad 14 need change PD1(6 pin*1) as Goliad 12
(3 pin*2), the main and 2nd source also,
these two ESD diode need to close battery connector
as possible.
Change PD1 and add PD2
From : SC300001100 (S DIO(BR) IP4223CZ6 SO-6 ESD)
To : SCA00001W00 (S ZEN ROW TVNST52302AB0 C/C SOT523
ESD after check 1.75X1.7xH=0.9mm <ME H=1.5mm)
X02
X02
X02
X02
X02
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 3
PWR_PIR 3
PWR_PIR 3
LA-9591P
LA-9591P
LA-9591P
52 57Friday, May 17, 2013
52 57Friday, May 17, 2013
52 57Friday, May 17, 2013
1
0.4
0.4
0.4
5
Request
Request
Page#
Item
Item Issue Description
ItemItem
D D
Page# Title
Page#Page#
P48
28
Title
TitleTitle
Selector
Date
DateDate
2013/
02/21
RequestRequest
Owner
Owner
OwnerOwner
4
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Issue DescriptionDate
Issue DescriptionIssue Description
Compal
follow E5- Salado 14"15" schematic
3
1) For Input current sense stablilze
2) To provent charger into sleep mode dual
AC transient.
3) Fine tune ACOK response time.
4) Adapter protect rating setting
Page 1
Page 1
Page 1Page 1
1). Change PC703 from 0.1U to 1U
P/N: SE000006900 (S CER CAP 1UF 25V K X5R 0603)
2). Change PC706 from 1U to 10U
P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25)
3). Change PC708 from 0.01U to 0.1U
P/N: SE00000G880 (S CER CAP 0.1U 25V K X5R 0402)
4). Change PR734 from 100K ohm to 210K ohm
P/N: SD034210380 (S RES 1/16W 210K +-1% 0402)
Change PR735 from 46.4K ohm to 69.8K ohm
P/N: SD034698280 (S RES 1/16W 69.8K +-1% 0402)
2
Solution Description
Solution Description
Solution DescriptionSolution Description
1
Rev.
Rev.
Rev.Rev.
X02
5) Fine tune H_PROCHOT# response time.
6) Improve ACAV_IN_NB ref voltage accuracy.
C C
29
P48
Selector
2013/
Compal
02/27
30
P47
Charger
2013/
Compal
03/18
B B
31
32
P42
P43
P44
P47
+5V/+3.3V
1.35V/0.675V
+1.05V_MP
Charger
2013/
03/20
2013/
Compal
Compal
7) Improve current sense accuracy.
Modify resistor value to meet voltage
tolerence
follow E5- Salado 14"15" schematic to
add charger input MLCC to 88u
support DFX team change choke layout pad
to avoid soldering issue
Support acoustic team to reduce noise
03/21
P49
PROCESSOR
DECOUPLING
P46
A A
Vcore
5). Add @PC740
6). Change PR738.pin1 from BQ24715_REGN connect to +3.3V_ALW2.
Change PR738 from 118K ohm to 48.7K ohm
P/N: SD034487280 (S RES 1/16W 48.7K +1% 0402)
Change PR744 from 12K ohm to 10K ohm
P/N: SD034100280 (S RES 1/16W 10K +-1%
7). Change PR748 from 6.8 ohm to 210K ohm
P/N: SD034442A80 (S RES 1/16W 44.2 +-1% 0402)
Change PR749 from 10 ohm to 69.8K ohm
P/N: SD00000W200 (S RES 1/16W 59 +-1% 0402)
1). Change PR802,PR827,PR840 from 47K ohm to 100K
P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
2). Change PR804,PR826,PR839 from 240K to 100K
P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
1). Add PC741, PC742
P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
1). Change PL101, PL102, PL200, PL300 PCB FootPrint
change
from CYNTE_PCMC063T-2R2MN_2P
to CYNTE_PCMB064T-3R3MS_2P
1). Add PC930
P/N: SGA00002680 (S POLY C 330U 2.5V Y D2 LESR9M
EEFS H1.9)
2). Del PC916, PC920, PC925, PC926, PC927, PC929
P/N: SE000001120 (S CER CAP 22U 6.3V M X5R 0805 H0.85)
3). Change PC738
from 33U(SGA00005M00) to 100U
P/N: SGA00008R00 (S POLY C 100U 20V M D ESR55M
(D3L_H=2.8mm)
4). Depop PC928, PC924, PC919, PC915, PC911
and Add PC901
P/N: SE000001120 (S CER CAP 22U 6.3V M X5R 0805 H0.85)
X02
X02_1
X02_1
X02_1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 4
PWR_PIR 4
PWR_PIR 4
LA-9591P
LA-9591P
LA-9591P
53 57Friday, May 17, 2013
53 57Friday, May 17, 2013
53 57Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
1 HW
2 X01
3 HW
10
22 DELL10/23/2012 DELL drop ALS function Remove ALS interface from EC and CPU side than move touch screen
HW
10/23/2012
10/23/2012
Owner
COMPAL
DELL drop Media LED function Remove backlight LED function and change connector to 6pin
Remove EMI solution at Speaker side Remove R132, R133, R134 and R135
signal to eDP side
4 HW X01COMPAL
6 HW
22 10/23/2012 change LCDVDD power control circuit change U9 from TPS22966 to APL3512 solution
22 10/23/2012 change Webcam power enable from PCH pop R106 and de-pop R102
10 10/23/2012 remove eDP backlight control pull up resistor Remove RC150
HW5 COMPAL X01
COMPAL X01
change +1.05V_RUN_VMM power enable signal from LP_EN to DOCKED and add
+3.3V_RUN_VMM for DP2320 series 3.3V power rail
remove L3 and move U6.E5 to +1.05V_VMM_VDD power rail
7 HW
C C
21
10/23/2012
COMPAL
Vendor update schematic for power saving
change U6.J4 to +3.3V_RUN_VDDA
R85 change to 3.74K_1%
remove LP_EN, R232 and U6A.A5 to NC
remove R55 and pop-option R207 when use VMM2310
8
9
21
18 19 10/23/2012 COMPAL Remove DIMM VERF power rail from power side Remove RD2, RD4, RD8 and RD9
26
26 10/23/2012 refer salado 14" to change PCBEEP circuit remove C132,C146,R146,R138,C133 and C143 than add C145,C146,R147,R151
HW 10/23/2012 change VMM2320 config remove DP to VGA PTN3392 circuit and add 0ohm pop option for 2320 config
HW
COMPAL10
change miniDP OCP solution remove D10 R160 F2 and add U50 de-pop C383
HW COMPAL11 X01
and de-pop R194 R153
26 10/23/2012 If doesn't has external power, Sleeve will
HW12 COMPAL
Add AUD_NB_MUTE# to control Sleeve pin.
be floating mode and no reference GND.
13
B B
37,36,12 20
14 HW COMPAL X01
37 Change board ID to X01 change R392 form 240K to 130Kohm
HW
10/23/2012
11/8/2012
COMPAL
GPIO map update to 2.7 version
Move EC_WAKE# from ECE5048[L]5 to MEC5075 GPIO52.
Change name: 1.5V_SUS_PWRGD to 1.35V_SUS_PWRGD for DDR3L.
Add NFC_DET# ECE5048 GPIOL[5] to NFC moudle and add pull
up 10K resistor
remove RC167,RC202,RC293 and RC290 then add RP4
remove RC295,RC189,RC191 and RC51 then add RP5
remove RC177,RC15,RC62 and RC43 then add RP6
remove RC201,RC203,RC204 and RC208 then add RP7
10
12
15 HW COMPAL X01
21
36
11/8/2012 change to network resistor
37
remove R299,RC300,R301 and R296 then add RP8
remove R53,R54,R70 and R72 then add RP9
remove RC216,RC178,RC80 and RC21 then add RP11
remove RC77,RC85,RC71 and RC215 then add RP12
remove RC207,RC214,RC205 and RC164 then add RP13
remove RC229,RC188,RC34 and RC196 then add RP14
remove R359,R361,R451 and R387 then add RP15
remove R445,R456,R457 and R454 then add RP16
remove R346,R347,R364 and R365 then add RP17
A A
remove R344,R368,R369 and R372 then add RP18
remove R401,R348,R350 and R377 then add RP19
Solution Description Rev.Page# Title
X01DELL40 36
X01
X01
X01COMPAL
X01
X01HW 10/23/2012
X01
X01
Request
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (1/5)
EE P.I.R (1/5)
EE P.I.R (1/5)
LA-9591P
LA-9591P
LA-9591P
54 58Friday, May 17, 2013
54 58Friday, May 17, 2013
54 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
16
17
39 +1.05V_MODPHY can't meet INTEL timing spec change +1.05V_MODPHY to MOS solution
18 19 11/8/2012
HW
HW
HW
11/8/201222
11/8/2012
Owner
COMPAL
COMPAL
COMPAL
Add Mic power and remove DBC function Add 3.3V_RUN for Mic power and remove DBC function at JeDP.2
refer PDG1.0 to change SODIMM control
circuit resistor
change RC68, RC126 and RC173 from 2.2 to 2ohm 1%
change RC67,RC69,RC130,RC132,RC217 and RC221
from 1.82K to 1.8Kohm 1%
19 27,32,26,20,40 11/8/2012 COMPAL ME change connector change JmDP1,JSIM1,JSPK1,JNFC1,JMEDIA,SW1,JSD1
20 2, 3, 6, 34 11/13/2012 update SATA topology fro Mainstream CPU exchange SATA1&SATA2 topology
12 11/13/2012 refer Goliad 12" add LAN_WAKE# T-topology add RC177 to link LAN_WAKE# and EC_WAKE#
22 15 11/13/2012 remove RC252 for cost saving change RC252 to PJP11(1mm jumper-short)
23
C C
34 11/14/2012 ME change Docking connector change JDOCK1
24 16 11/14/2012 INTEL
25 COMPALHW 11/14/2012 change AND gate to same source Change U20, U26, U29 and U30 from SA74108040L to SA00708012L 20,28,30,31
33 11/14/2012
24 change AUX/DDC power rail same as VMM2320 Change U11,U13 power rail from +3.3V_RUN to +3.3V_RUN_VMM
29 HW COMPAL X01
31 11/14/2012 remove TPS22965 solution remove U51(TPS22965) and U34(TPS22965) than add U3(TPS22966)
ME X01
HW COMPAL
HW
HW
COMPAL
COMPAL
ME COMPAL
HW
MOW_WW46 request change for VCCUSB3PLL and
VCCSATA3PLL
change CC42 and CC49 from 1u_0402 to 22u_0603
change CC76 and CC77 from 100u_1206 to
22u_0603
HW
HW COMPAL27 X01
HW28 COMPAL X01
11/14/2012
11/14/201238,12 remove +3.3V_TP power load switch solution remove U40, R458,C424 and C423
COMPAL26
add USB power cap 150u co-layout with 100u add C86,C89(1206) co-layout with C280,C290(B2) X01
Solution Description Rev.Page# Title
X01
X01
X01
X01
X0121
X01
X01
X01
X01
Request
30 HW COMPAL X01
31 HW COMPAL X01
B B
22 11/15/2012 change diode to daul-diode fro cost saving remove D4,D5,D6,D7 and add D10,D21
9 11/16/2012 change APS pin 11 net_name for DELL APS debug Change JAPS1.11 net name from SIO_PWRBTN# to POWER_SW#_MB
add mSATA_DEVSLP from UC1.P2(DEVSLP1/GPIO38) to mSATA_HDD(JMINI2.44)
32
33
34
31,12
37
12,28
HW COMPAL X01
HW COMPAL X01
HW COMPAL X01
11/16/2012 add mSATA_DSLP for mSATA HDD
11/16/2012
11/16/2012
change thermal diode for cost saving change D11,D13 and D14 form SB000008P0L to SB33904510L
support TLS confidentility
and pull up 10K(R160 depop) to +3.3V_mSATA_WWAN.
de pop HDD_DEVSLP pull up resistor R155
change net name from HOST_ALERT1_R_N to PCH_GPIO15, and pop RC190
remove R188
change L44 and L45 from SM01000558L to SM01000C500
35
38,26,30,22 change Bead for cost reduce
HW X01
11/16/2012
COMPAL
change L35 and L36 from SM01000AM0L to SM01000C500
change LE1 from SM01000DH0L to SM01000BV00
change L21 from SM01001788L to SM010005N00
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (2/5)
EE P.I.R (2/5)
EE P.I.R (2/5)
LA-9591P
LA-9591P
LA-9591P
55 58Friday, May 17, 2013
55 58Friday, May 17, 2013
55 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
36
37
38
39
40
29
25 remove HDD_DEVSLP resisrtor
37
28 11/20/2012 LOM LED issue reverse Q32,Q33 of C & D gate
22 40 38
26
HW
HW
HW
11/19/2012 exchange JUSH1,JMEDIA pin define for ME update exchange JUSH1 and JMEDIA pin define
11/19/2012
11/19/2012
HW X01
HW COMPAL X01
11/22/2012 Remove ESD reserve location Per ESD experiment, D3,D27,D22,DE1,DE2 can be remove
Owner
COMPAL
COMPAL
COMPAL
COMPAL
remove R189
change thermal OTP to 98 degree change R394 from 1.24K to 1.82K_1%
HW COMPAL41 15 11/23/2012 Per Intel CRB updated Change VCCST_PWRGD pull high value from 10K ohm to 1K ohm.
HW42 COMPAL26 11/23/2012 Universal Jack no longer supported on X5 Remove D9,D11,R209,R210,C195,C196,R198,R199
C C
43 HW12 11/27/2012 COMPAL Change GPIO connection change NFC_DET# connection from EC GPIOL[5]/PWM2 to LPT_LP GPIO59
44 6 HW 11/28/2012 COMPAL
45 12 HW 11/28/2012 COMPAL
To support mainstream and Premium CPU,
change to SATA port assignment.
To support the SATA DevSLP
function for new SATA port assignment.
Change docking SATA port form SATA port 1 to SATA port 0 and spindle HDD
from port 0 to port 1
Change DEVSLP0/GPIO33 to mSATA_DEVSLP
and DEVSLP1 to HDD_DEVSLP
46 12 HW 11/28/2012 COMPAL USB port 0 EA result Change L42 from DLW21SN900SQ2L to OCE2012120YZF
47 31 HW 11/28/2012 COMPAL Change WWAN power control.
Change power control signal from 3.3V_WWAN_EN
& 3.3V_mSATA_EN to MCARD_WWAN_PWREN
Solution Description Rev.Page# Title
X01
X01
X01
X01
X01
X01
X01
X01
X01
X01
Request
3148 HW 11/28/2012 COMPAL Change WLAN power control.
B B
Change power control signal from 3.3_1.5V_WLAN_EN
to AUX_EN_WOWL
3849 HW 11/28/2012 COMPAL Per EMI test result Remove L44,L45
50 34
HW 11/28/2012 COMPAL Per EMI test result Change R259,R252,R253,R255,R257,R263,R265,R266
R260,R261,R254,R256,R262,R264,R258,R267 from 0 ohm to 33 ohm.
51 9 HW 1/9/2013 COMPAL add RSMRST pull down resistor add RC136
52 38 HW 1/9/2013 COMPAL add repeater at USB3 RX IO connector side add U51 circuit
53 22 HW 1/9/2013 COMPAL change LCDVDD power chip soft start cap change C430 from 0.1u to 0.01u
54 36 1/9/2013 COMPAL change dock SMbus alert pull up resistor change R292 from 10K to 100Kohm
55 40
A A
HW
HW 1/17/2013 COMPAL change LED series resistor form LED measure change R435 from 1.8K to 390ohm, change R430 from 2.2K to 220ohm,
change R434 from 220 to 150ohm, change R427 from 1K to 390ohm.
X01
X01
X01
X01
X01
X01
X01
X01
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (3/5)
EE P.I.R (3/5)
EE P.I.R (3/5)
LA-9591P
LA-9591P
LA-9591P
56 58Friday, May 17, 2013
56 58Friday, May 17, 2013
56 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
56
57
1 9 1/23/2013 add XDP@ for XDP component change XDP circuit to XDP@
37 change board ID to ST config change R392 from 130K to 33Kohm
58 37 1/30/2013 change HW thermal shortdwon temperature change R394 from 1.82K to 1.58Kohm
60 26 2/1/2013 COMPAL
61 26 2/1/2013 remove RC121 and pop RC102
HW
HW
1/23/2013
HW
HW
2/1/2013
HW
HW COMPAL update XDP circuit for INTEL ITE can't boot
Owner
COMPAL
COMPAL
COMPAL
COMPAL
change eDP connector pin define for factory
burn out issue
update speaker EMI bead for audio precsison
fail issue
1.add pull down 1Kohm at JEDP1.29
2.Swap JEDP1.1 and JEDP1.2
change L22~L25 from SM01000L300 to SM010019400
62 36 HW 2/18/2013 COMPAL power update AC_DIS# circuit to high active change AC_DIS# net name to AC_DIS
63 11 35 HW 2/21/2013 COMPAL
C C
Fixed 2 USB IO Port use the same OC# signal
issue
1.change IO/B USB OC# from USB_OC0# to USB_OC1#
2.change USB_OC1#/3# to USB_OC1#, USB_OC3# and add RC166 for OC3# pull
up resistor
64 7 HW 2/21/2013 COMPAL add jumper for clock buffer co-layout add PJP12, PJP13 and PJP14 beween UC5
65 7 HW 2/21/2013 COMPAL change TAA connector from ME request change JTAA1 from ACES_50185-02041-001 to PANAS_AXK820145WG
1.Pop CC71 and CC72
66 16 HW 2/22/2013 add ESD solution
67 33 HW 2/22/2013
COMPAL
COMPAL change USB charge solution for SAMSUNG phone change U39 from SA00004VH00 to SA00006L600
68 7 HW 2/25/2013 COMPAL add RF noise solution at clock buffer
2.Add two 22u 0603 between +VCC_CORE and +1.05V_RUN power plan
3.Add 22u 0603 between +1.05V_RUN and +3.3V_RUN power plan
1. add CC86~CC89 between clock signal
2. add RC62 for UC5 power rail
3. change RC100 from 0ohm short to 10ohm
B B
69 23 HW 2/25/2013 COMPAL refer INTEL MOW to update HDMI cost reduce
4. change UC5 from IDT_5V60034DCG8 to CYPRESS_CY2304SXI-1T
cahnge R462~R469 resistor from 680(SD034680080) to 470ohm(SD034470080)
level shifter main link
70
11 12
HW 2/25/2013 COMPAL
For AOAC function, can’t wake up from S3
through SIO_EXT_SMI#
change net name from USB_OC3# to SIO_EXT_SMI#, and change SIO_EXT_SMI#
to PCH_GPIO45
Solution Description Rev.Page# Title
X02
X02
X02
X0259 22
X02
X02
X02
X02
X02
X02
X02
X02
X02
X02
X02
Request
9
add EMI solution at H_PROCHOT#
add CC149_22P_0402(SE071220J80) depop for EMI requestCOMPAL71 HW 2/26/2013
72 26 HW 2/26/2013 COMPAL for Fixed BIOS flash HOTSOS issue change R154 from PCH_AUDIO_EN to RUN_ON
73 7 HW 2/28/2013 COMPAL remove clock Buffer solution
1.remove item 68 location and CC25 CC57 CC80 CC22 UC5 RC100 and CC23
2.change RC65 to 0ohm_short
74 7 29 HW 2/28/2013 COMPAL refer GPIO3.0 to add PCH_TPM_LPC_EN add RC56 for pull up enable signal and add R198 for pop option
A A
with SD card inserted incompletely issue.
1. SD/MMCCD# add C256(0.1uF) & R493(1M) pull-down to GND
2. C222 change to 1uF(SE000000K80) from 0.1u(SE00000G880)
X02
X02
X02
X02
X0275 30 HW 3/12/2013 COMPAL For O2 enters into test mode unexpectedly
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (4/5)
EE P.I.R (4/5)
EE P.I.R (4/5)
LA-9591P
LA-9591P
LA-9591P
57 58Friday, May 17, 2013
57 58Friday, May 17, 2013
57 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
Version Change List ( P. I. R. List )
3
2
1
Item Issue DescriptionDate
D D
Owner
1. LANCLK_REQ# change to UC1.AD1 from UC1.Y5
2. MINI1CLK_REQ# change to UC1.T2 from UC1.U2
76
7 3/13/2013 Base on INTEL EDS SPEC Update Rev 1.5.1
HW X02COMPAL
3. MINI2CLK_REQ# change to UC1.N1 from UC1.T2
4. MMICLK_REQ# change to UC1.U5 from UC1.AD1
5. PCH_TPM_LPC_EN change to UC1.Y5 from UC1.U5
1. CLK_PCIE_LAN change CLKOUT_PCIE port2
77 HW7 3/14/2013 COMPAL For PCIE CLK & PCIE CLK REQ signal mapping
2. CLK_PCIE_MINI2 change CLKOUT_PCIE port3
3. CLK_PCIE_MMI change CLKOUT_PCIE port4
4. CLK_PCIE_MINI1 change CLKOUT_PCIE port5
78 21 HW 3/15/2013 COMPAL remove VMM2310 co-layout schematic remove U8, R93, R98, R105 circuit
79 15 HW 3/15/2013 COMPAL add ESD solution add CC22 and CC57
80 7 HW 3/18/2013 COMPAL For INTEL request PCIECLK_REQ0# add RC57(10k) pull-high to+3.3V_RUN
C C
21 HW 3/20/2013 COMPAL For Synaptics vender request 1. Delete R78/R80/R82
81
2. add C132
82 9 12 HW 3/21/2013 COMPAL add ESD solution add CC90 and CC91
83 HW COMPAL
84
85 33 HW
35
HW
4/02/2013
4/25/2013
4/25/2013 for JUSB2 can't wake from S3 issue change U33 power rail from +3.3V_RUN to +3.3V_SUS
COMPAL
COMPAL
For USB3.0 1M cable Pop R478, R479 and change R476 to 3.01K ohm
change board ID to A00 version change R392 from 33K to 1K ohm A0037
Solution Description Rev.Page# Title
X02
X02
X02
X02
X02
X02
X02
A00
A0086 9 HW 4/25/2013 COMPAL for XDP signal should be contact to PCH change RC97 and RC135 to 0ohm short
Request
87 28 HW 4/25/2013 COMPAL for support Vpro reset pin depop U20 and add R145
88 12 HW 4/25/2013 COMPAL reserve for support non vpro pop option pin reserve RC292 pull down
B B
A00
A00
R434 change from 150 to 330ohm, R430 change from 220 to 330ohm, R438
89 40 HW 4/25/2013 COMPAL current LED resistor for LED EA measure
change to 2.2K to 150ohm, R436 change from 2.2K to 220ohm and R429
change from 620 to 220ohm
A00
90 10 HW 5/14/2013 COMPAL HDD Free Fall Sensor A00add R494 & R495
91 15 16 HW 5/16/2013 COMPAL add ESD solution Pop CC57, depop CC71 , CC72
Follow Goliad12, Pop RC290 & change RC292 from 10K to 100ohm.91 12 HW 5/16/2013 COMPAL reserve for support non vpro pop option pin
A A
A00
A00
X02
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (5/5)
EE P.I.R (5/5)
EE P.I.R (5/5)
LA-9591P
LA-9591P
LA-9591P
58 58Friday, May 17, 2013
58 58Friday, May 17, 2013
58 58Friday, May 17, 2013
1
0.4
0.4
0.4
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