Compal LA-9591P VAUA0 Goliad 14, Latitude E7440 Schematic
A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
PCB NO :
BOM P/N :
LA-9591P (DAA00005W10)
4319LK31L01
MODEL NAME :
VAUA0
GPIO MAP: 3.0
2 2
Goliad 14"
Haswell ULT
2013-05-17
REV : 1.0 (A00)
@ : Nopop Component
1@ : M/B SPI ROM
3 3
EMC@ : EMI, ESD and RF Component
SPI on M/B TAA
XDP@ : XDP Component
2@ : TAA/B SPI ROM
Vpro
1@/3@/4@/EMC@ 2@/3@/5@/EMC@
CONN@ : Connector Component
3@ : M/B for non support WWAN
non-Vpro
1@/EMC@ 2@/EMC@
4@ : M/B SPI 4M ROM Component
5@ : TAA/B SPI 4M ROM Component
7@ : M/B for Non-Vpro
4 4
MB PCB
MB PCB
Part Number
Part Number
DAA00005W10
DAA00005W10
Description
Description
PCB 0VN LA-9591P REV1 M/B
PCB 0VN LA-9591P REV1 M/B
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-9591P
LA-9591P
LA-9591P
1 58Friday, May 17, 2013
1 58Friday, May 17, 2013
1 58Friday, May 17, 2013
E
0.4
0.4
0.4
A
Goliad 14 Block Diagram
B
C
D
E
Memory BUS (DDR3L)
1 1
Mini-DP
eDP CONN
PAGE 22
DP
PAGE 27
eDP
1333/1600MHz
INTEL
DP
For MB/Dock
Video Switch
DP
IDT VMM2320
VGA
DOCKING
PORT
2 2
PAGE 34
DAI
DOCK_USB3.0[3]
SATA0
DOCK_USB2.0[0]
DOCK_USB2.0[5]
PCIE3 PCIE4
PAGE 21
HDMI CONN
PAGE 23
SD4.0
PAGE 30 PAGE 30
DP
HDMI
Intel Clarkville
I218LM
PAGE 28
3 3
LAN SWITCH
PI3L720
PAGE 28
Transformer
PAGE 35
Smart Card
RFID
RJ45
PAGE 35
4 4
A
PAGE 31 PAGE 31
TDA8034HN
Fingerprint
CONN
Pericom
PI3VDP12412
PAGE 27
Reduce Level
Shifter
PAGE 23
Card reader
O2 Micro OZ777FJ2LN
PCI Express BUS
PCIE6_L0
Full Mini CardWLAN+BT/
WWAN+mSATA
SATA3
USB2.0[6]USB2.0[2]
FP_USB
USH
BCM5882
USB2.0[4]
USH board
PAGE 29
FAN CONN
KB and TP CONN
B
DDI2
HASWELL ULT
DDI1
PCIE5_L0
SPI
Discrete TPM
AT97SC3204
PAGE 37 PAGE 37
PAGE 29
LPC
SMSC KBC
MEC5075
PAGE 38
DOCKED_LIO_EN
NX3DV221
USB20 Switch
PI3USB3102
USB3&2 Switch
SATA Conn60GHz
PAGE 6~17
W25Q64CVSSIQ
64M 4K sector
USB
USB2.0[7]
USB2.0[0]
DOCKED
USB2.0[5]
USB3.0[3]
HD Audio I/F
SATA1
W25Q32BVSSIQ
32M 4K sector
SMSC SIO
PAGE 7
Touch Screen
Conn
Trough eDP Cable
ECE5048
PAGE 36
BC BUS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
DDR3L-DIMM X2
BANK 0, 1, 2, 3
PAGE 33
PAGE 32
PAGE 25
PAGE 22
D
PAGE 18 19
USB2.0[3]
SW_USB2.0[0]
DOCK _USB2.0[0]
SW_USB2.0[5]
SW_USB3.0[3]
USB2.0[1]
USB3.0[1]
HDA Codec
ALC3226
PAGE 26
Trough eDP Cable
Camera
PAGE 22
Trough eDP Cable
SLGC55584A
USB POWER SHARE
USB3.0/2.0
DOCK _USB2.0[5]
DOCK_USB3.0[3]
USB3.0/2.0
PAGE 33
PAGE 33
PAGE 35
USB3.0[2]
IO/B
USB3.0/2.0+PS
PAGE 33
Free Fall sensor
PAGE 25
INT.Speaker
PAGE 26
Near Field
Communications con
Vol bottom SW
Combo Jack
DAI
To Docking side
IO/B
CPU XDP Port
PAGE 40
PAGE 9
Automatic Power
Dig. MIC
PAGE 22
Switch (APS)
WiFi ON/OFF
PAGE 9
PAGE 35
DC/DC Interface
PAGE 39
Power On/Off
SW & LED
PAGE 40
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block diagram
Block diagram
Block diagram
LA-9591P
LA-9591P
LA-9591P
2 58Friday, May 17, 2013
2 58Friday, May 17, 2013
2 58Friday, May 17, 2013
E
PAGE 20
IO/B
0.4
0.4
0.4
5
4
3
2
1
POWER STATES
State
D D
S0 (Full ON) / M0
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCIE
PCIE 1
PCIE 2
PCIE 3
PCIE 4
PCIE 5
PCIE 6 WWAN(PP/mSATA)
USB3.0
USB3.0 1
USB3.0 2
USB3.0 3
SATA
SATA 3
DESTINATION
JUSB3-->IO-->Right
JUSB1-->Rear left
JUSB2-->Rear Right//DOCK
LOM
WLAN (WiGi)
MMI (CARD READER)
C C
PM TABLE
power
plane
+3.3V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
+3.3V_SUS+5V_ALW +5V_RUN
+1.35V_MEM
+0.675V_DDR_VTT
+1.05V_RUN
+VCC_CORE
+3.3V_M +3.3V_M
+1.05V_M+3.3V_RUN
+1.05V_M
(M-OFF)
SATA 2
SATA 0
USB PORT#
State
0
1
S0
B B
S3
S5 S4/AC
S5 S4/AC don't exist
ON
ON
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
ON
ON
ON
ON
OFF
OFF
OFFOFF
HSW
ULT
2
3
4
5
JUSB1 // E-Dock 1
IO/ JUSB3
WLAN + BT
CAMERA
USH->SMART CARD
JUSB2 // E-Dock 2
NA
HDDSATA 1
DOCK
DESTINATION
need to update Power Status and
PM Table
6
7
0
WWAN
TOUCH
BIO
USH
A A
1
NA
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Port assignment
Port assignment
Port assignment
LA-9591P
LA-9591P
LA-9591P
3 58Friday, May 17, 2013
3 58Friday, May 17, 2013
3 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
+1.05V_RUN
+3.3V_RUN
A_ON
PWRSHARE_EN#
ESATA_USB_PWR_EN#
TPS51212
(PU300)
G471
(U35)
D D
ADAPTER
EN_INVPWR
FDC654P
(Q2)
DOCKED
TPS22966
+1.05V_M
+5V_USB_
CHG_PWR
G471
(U35)
+USB_PWR
(U31)
+BL_PWR_SRC
MPHYP_PWR_EN
BATTERY +PWR_SRC
C C
+1.05V_RUN_VMM
CHARGER
+3.3V_RUN_VMM
ALWON
TPS51225
(PU100)
SI3456
(Q125) +1.05V_MOD_PHY
+5V_ALW
USB_SIDE_EN#
G471
+3.3V_ALW
RUN_ON
PCH_ALW_ON
AUX_EN_WOWL
MCARD_WWAN_PWREN
TPS22966
(U3)
TPS51622
(PU500)
B B
RT8207
(PU11)
A_ON
TPS22966
(U45)
SUS_ON
SIO_SLP_LAN#
3.3V_HDD_EN
TPS22966
(U22)
EN_LCDPWR
APL3512
(U9)
RUN_ON
RUN_ON
TPS22966
(U46)
RUN_ON
RUN_ON
TPS22966
(U18)
TPS22966
(U43)
(IO/B)
+USB_IO_PWR
+3.3V_ALW_PCH
H_VR_EN
SUS_ON
+VCC_CORE
A A
+1.35V_MEM
+0.675V_DDR_VTT
+5V_RUN
_AUDIO
0.675V_DDR_VTT_ON
+3.3V_M
+3.3V_WLAN
+3.3V_SUS
+3.3V_LAN
+3.3V_mSATA
_WWAN
+LCDVDD
+3.3V_HDD
+3.3V_CAM
+3.3V_RUN
3.3V_CAM_EN#
LP2301ALT1G
(Q3)
+5V_RUN
3.3V_TS_EN
LP2301ALT1G
(Q1)
+5V_TSP
+3.3V_RUN
_AUDIO
+1.05V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power rails
Power rails
Power rails
LA-9591P
LA-9591P
LA-9591P
4 58Friday, May 17, 2013
4 58Friday, May 17, 2013
4 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
SMBUS Address [0x9a]
B4
A3
B5
A4
MEM_SMBCLK
MEM_SMBDATA
SML0CLK
SML0DATA
2.2K
2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMDATA
+3.3V_ALW_PCH
AP2
AH1
D D
PCH
AN1
AK1
AU3AH3
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
1K
1K
2.2K
2.2K
4
+3.3V_ALW_PCH
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW
2N7002
2N7002
0ohm
0ohm
0ohm
0ohm
127
129
NFC_SMBCLK
NFC_SMBDATA
DOCKING
LAN_SMBCLK
LAN_SMBDATA
3
28
31
LOM
2
202
200
202
200
53
51
DIMMA
DIMMB
XDP
1
10K
NFC
10K
4
6
30
32
+3.3V_RUN
G Sensor
WWAN
2.2K
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
A50
B53
A49
B52
USH_SMBCLK
USH_SMBDAT
2.2K
2.2K
CARD_SMBCLK
CARD_SMBDAT
1E
B B
1E
MEC 5075
2B
2B
10K
B50
A47
CHARGER_SMBCLK
CHARGER_SMBDAT
1G
1G
10K
2.2K
2.2K
B7
A7
BAY_SMBDAT
BAY_SMBCLK
A A
2D
2D
2.2K
2.2K
B48
B49
GPU_SMBDAT
GPU_SMBCLK
4
2A
2A
5
+3.3V_ALW
100 ohm
100 ohm
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
7
BATTERY
6
CONN
M9
L9
USH
9
8
Charger
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SMbus Block diagram
SMbus Block diagram
SMbus Block diagram
LA-9591P
LA-9591P
LA-9591P
5 58Friday, May 17, 2013
5 58Friday, May 17, 2013
5 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
+RTC_CELL
330K_0402_1%
330K_0402_1%
12
RC1
RC1
D D
PCH_INTVRMEN
330K_0402_1%
330K_0402_1%
12
RC2@
RC2@
+3.3V_ALW_PCH
RC3@ 1K_0402_5%RC3@ 1K_0402_5%
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT)
HIGH = DISABLE
1 2
4
PCH_AZ_SDOUT
3
2
1
CC1
CC1
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
1 2
RC7 1M_0402_5%RC 7 1M_0402_5%
+RTC_CELL
C C
1
1
ME1@SHORT PADS~DME1@SHORT PADS~D
1 2
CC3 1U_0402_6.3V6KCC3 1U_0402_6.3V6K
2
2
CMOS_CLR1
1 2
1 2
RC8 20K_0402_5%RC8 20K_0402_5%
RC6 20K_0402_5%RC6 20K_0402_5%
1
CC4
CC4
CMOS place near DIMM
CMOS setting
1 2
18P_0402_50V8J
18P_0402_50V8J
CC2
CC2
1 2
18P_0402_50V8J
18P_0402_50V8J
1
CMOS1@SHORT PADS~DCM OS1@SHORT PADS~D
1 2
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
12
Shunt Clear CMOS
Open
ME_CLR1
Keep CMOS
TPM setting
Shunt Clear ME RTC Registers
Open
B B
+1.05V_M
12
0_0603_5%
@
0_0603_5%
@
RC16
RC16
+1.05V_M_JTAG
RC17 51_0402_1%RC17 51_0402_1%
RC18 51_0402_1%RC18 51_0402_1%
RC20 51_0402_1%RC20 51_0402_1%
RC10@ 1K_0402_1%RC10@ 1K_0402_1%
RC22@ 51_0402_1%RC22@ 51_0402_1%
Keep ME RTC Registers
12
PCH_JTAG_TDI
12
PCH_JTAG_TDO
12
PCH_JTAG_TMS
12
PCH_JTAG_JTAGX
12
PCH_JTAG_TCK
HDA for Codec
1 2
RC4@ 0_0402_5 %RC4@ 0_0402_5%
YC1
YC1
32.768KHZ_12.5PF_Q13FC135000040
32.768KHZ_12.5PF_Q13FC135000040
PCH_RTCRST#<9>
PCH_AZ_CODEC_SDIN0<26>
ME_FWP<36>
RC9 1 K_0402_5%RC9 1 K_0402_5%
PCH_JTAG_TRST#<9>
PCH_JTAG_TCK<9>
PCH_JTAG_TDI<9>
PCH_JTAG_TDO<9>
PCH_JTAG_TMS<9>
PCH_JTAG_JTAGX<9>
PCH_AZ_CODEC_SDOUT<26>
PCH_AZ_CODEC_SYNC<26>
PCH_AZ_CODEC_RST#<26>
PCH_AZ_CODEC_BITCLK<26>
PCH_RTCX1PCH_RTCX1_R
10M_0402_5%
10M_0402_5%
12
RC5
RC5
PCH_RTCX2
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
1 2
PCH_AZ_SDOUT
PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
T3@ PAD~ DT3@ PAD~ D
T4@ PAD~ DT4@ PAD~ D
T5@ PAD~ DT5@ PAD~ D
1 2
RC23 33_0402_5%RC23 33_0402_5%
1 2
RC24 33_0402_5%RC24 33_0402_5%
1 2
RC25 33_0402_5%RC25 33_0402_5%
1 2
EMC@
EMC@
RC26 33_0402_5%
RC26 33_0402_5%
27P_0402_50V8J
27P_0402_50V8J
12
CC5@
CC5@
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER
AV7
INTVRMEN
AV6
SRTCRST
AU7
RTCRST
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN/I2S1_TXD
AV10
HDA_DOCK_RST/I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
PCH_AZ_SDOUT
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_BITCLK
UC1E
UC1E
HASWELL_MCP_E
HASWELL_MCP_E
RTC
RTC
JTAG
JTAG
5 OF 19
5 OF 19
HDD_DET#
mCARD_PCIE_SATA#
SATA_IREF
RSVD
RSVD
SATALED
Rev1p2
Rev1p2
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
A12
L11
K10
C12
U3
MPCIE_RST#
HDD_DET#
SATA_IREF
SATA_COMP
SATA_ACT#
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATAAUDIO
SATAAUDIO
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_RCOMP
SATA_PRX_DKTX_N0_C <34>
SATA_PRX_DKTX_P0_C <34>
SATA_PTX_DKRX_N0_C <34>
SATA_PTX_DKRX_P0_C <34>
SATA_PRX_DTX_N1_C <25>
SATA_PRX_DTX_P1_C <25>
SATA_PTX_DRX_N1_C <25>
SATA_PTX_DRX_P1_C <25>
SATA_PRX_MSATATX_N3 <31>
SATA_PRX_MSATATX_P3 <31>
SATA_PTX_MSATARX_N3 <31>
SATA_PTX_MSATARX_P3 <31>
MPCIE_RST# <12,31>
HDD_DET# <25>
PCH_GPIO36 <12>
MCARD_PCIE_SATA# <36>
RC14@ 0_0402_5%RC14@ 0_0402_5%
12
T1 @PAD~D T1 @PAD~D
T2 @PAD~D T2 @PAD~D
SATA_ACT# <40>
+PCH_ASATA3PLL
SATA Impedance Compensation
SATA_COMP
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
1 2
1 2
1 2
DOCK
SATA HDD
WWAN mSATA
+PCH_ASATA3PLL
RC193.01K_0402_1% RC193.01K_0402_1%
+3.3V_RUN
RC11100K _0402_5% RC11100K _0402_5%
RC1210K_0402_5% RC1210K_0402_5%
A A
Reserve for EMI
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (1/12)
CPU (1/12)
CPU (1/12)
LA-9591P
LA-9591P
LA-9591P
6 58Friday, May 17, 2013
6 58Friday, May 17, 2013
6 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
HASWELL_MCP_E
UC1G
UC1G
LPC_LAD0<29,36,37>
LPC_LAD1<29,36,37>
LPC_LAD2<29,36,37>
LPC_LAD3<29,36,37>
LPC_LFRAME#<29,36,37>
D D
+3.3V_M
1 2
R1 1K_0402_5%R1 1K_0402_5%
R2 1K_0402_5%R2 1K_0402_5%
SPI_WP#_SEL<36>
C C
SPI_CLK32
33_0402_5%
33_0402_5%
R45@
R45@
1 2
33P_0402_50V8J
33P_0402_50V8J
C85@
C85@
1 2
B B
PCI_CLK_LPC_0
PCI_CLK_LPC_1
PCH_SPI_DO2
1 2
PCH_SPI_DO3
PCH_SPI_CS0#
PCH_SPI_DIN
PCH_SPI_DO2
SPI_WP#_SEL
PCH_SPI_CS1# PCH_SPI_CS1#
PCH_SPI_DIN
PCH_SPI_DO2
SPI_WP#_SEL
1 2
1 2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3
R31@ 0_0402_5%R31@ 0_0402_5%
1 2
1 2
R41@ 33_0402_5%R41@ 33_0402_5%
R61@ 33_0402_5%R61@ 33_0402_5%
1 2
R8@ 0_0402_5%R8@ 0_0402_5%
1 2
R144@ 0_0402_5%R144@ 0_0402_5%
R154@ 33_0402_5%R154@ 33_0402_5%
1 2
1 2
R194@ 33_0402_5%R194@ 33_0402_5%
R23@ 0_0402_5%R23@ 0_0402_5%
SPI_CLK64
33_0402_5%
33_0402_5%
R57@
R57@
33P_0402_50V8J
33P_0402_50V8J
@
@
C76
C76
12
CC15@12P_0402_50V8J CC15@12P_0402_50V8J
12
CC14@12P_0402_50V8J CC14@12P_0402_50V8J
Reserve for EMI
A A
AU14
LAD0
AW12
LAD1
AY12
LAD2
AW11
LAD3
AV12
LFRAME
AA3
SPI_CLK
Y7
SPI_CS0
Y4
SPI_CS1
AC2
SPI_CS2
AA2
SPI_MOSI
AA4
SPI_MISO
Y6
SPI_IO2
AF1
SPI_IO3
SPI_PCH_CS0#_R
SPI_DIN64
12
12
SPI_PCH_DO2_64
SPI_PCH_CS1#_R
SPI_DIN32
SPI_PCH_DO2_32
WWAN (Mini Card 1)--->
HASWELL_MCP_E
LPC
LPC
SPI C-LINK
SPI C-LINK
10/100/1G LAN --->
WLAN (Mini Card 2)--->
MMI --->
4
SMBUS
SMBUS
SML1ALERT/PCHHOT/GPIO73
7 OF 19
7 OF 19
64Mb Flash ROM
U1 1@
U1 1@
1
/CS
2
DO(IO1)
/HOLD(IO3)
3
/WP(IO2)
4
GND
W25Q64FVSSIQ_SO8
W25Q64FVSSIQ_SO8
32Mb Flash ROM
U2 4@
U2 4@
1
/CS
2
DO/IO1
3
4
/HOLD/IO3
/WP/IO2
GND
W25Q32FVSSIQ_SO8
W25Q32FVSSIQ_SO8
SMBALERT/GPIO11
SML0ALERT/GPIO60
SML1DATA/GPIO74
VCC
CLK
DI(IO0)
VCC
CLK
DI/IO0
PCH_TPM_LPC_EN<29>
CLK_PCIE_LAN#<28>
CLK_PCIE_LAN<28>
LANCLK_REQ#<12,28>
CLK_PCIE_MINI2#<31>
CLK_PCIE_MINI2<31>
MINI2CLK_REQ#<12,31>
CLK_PCIE_MMI#<30>
CLK_PCIE_MMI<30>
MMICLK_REQ#<30>
CLK_PCIE_MINI1#<31>
CLK_PCIE_MINI1<31>
MINI1CLK_REQ#<12,31>
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK/GPIO75
CL_CLK
CL_DATA
CL_RST
Rev1p2
Rev1p2
+3.3V_M
8
7
SPI_PCH_DO3_64
6
SPI_CLK64
5
SPI_DO64
+3.3V_M
8
7
SPI_PCH_DO3_32
6
SPI_CLK32
5
SPI_DO32
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
AN2
PCH_SMB_ALERT#
AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
AL2
AN1
SML0CLK
AK1
SML0DATA
AU4
AU3
SML1_SMBCLK
AH3
SML1_SMBDATA
AF2
PCH_CL_CLK1
AD2
PCH_CL_DATA1
AF4
PCH_CL_RST1#
C51@
C51@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
1 2
R51@ 33_0402_5%R51@ 33_0402_5%
R71@ 33_0402_5%R71@ 33_0402_5%
1 2
1 2
R91@ 33_0402_5%R91@ 33_0402_5%
C64@
C64@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
R164@ 33_0402_5%R164@ 33_0402_5%
1 2
1 2
R204@ 33_0402_5%R204@ 33_0402_5%
R214@ 33_0402_5%R214@ 33_0402_5%
1 2
1 2
RC57 10K_0402_5%RC57 10K_0402_5%
1 2
RC56 10K_0402_5%RC56 10K_0402_5%
1 2
RC55 10K_0402_5%RC55 10K_0402_5%
3
PCH_GPIO73 <12>
SML1_SMBCLK <37>
SML1_SMBDATA <37>
PCH_CL_CLK1 <31>
PCH_CL_DATA1 <31>
PCH_CL_RST1# <31>
PCH_SPI_DO3
PCH_SPI_CLK
PCH_SPI_DO
PCH_SPI_DO3
PCH_SPI_CLK
PCH_SPI_DO
C43
C42
PCIECLK_REQ0#
U2
B41
A41
Y5
C41
B42
AD1
B38
C37
N1
A39
B39
U5
B37
A37
T2
PCI_CLK_LPC
SML0CLK
SML0DATA
UC1F
UC1F
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23
1 2
RC58 EMC@ 22_0402_5%RC58 EMC@ 22_0402_5%
RC61 EMC@ 22_0402_5%RC61 EMC@ 22_0402_5%
1 2
RC63 EMC@ 22_0402_5%RC63 EMC@ 22_0402_5%
1 2
MEM_SMBCLK
MEM_SMBDATA
RC35@ 0_0402_5%RC35@ 0_0402_5%
RC33@ 0_0402_5%RC33@ 0_0402_5%
RC31@ 0_0402_5%RC31@ 0_0402_5%
RC29@ 0_0402_5%RC29@ 0_0402_5%
12
12
12
12
TAA Config
PCH_SPI_DO
PCH_SPI_DO
PCH_SPI_CLK
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_DIN
PCH_SPI_DIN
HASWELL_MCP_E
HASWELL_MCP_E
CLOCK
CLOCK
SIGNALS
SIGNALS
6 OF 19
6 OF 19
R112@ 33_0402_5%R112@ 33_0402_5%
R125@ 33_0402_5%R125@ 33_0402_5%
R132@ 33_0402_5%R132@ 33_0402_5%
R185@ 33_0402_5%R185@ 33_0402_5%
R102@ 0_0402_5%R102@ 0_0402_5%
R175@ 0_0402_5%R175@ 0_0402_5%
R222@ 33_0402_5%R222@ 33_0402_5%
R415@ 33_0402_5%R415@ 33_0402_5%
CLK_PCI_TPM_TCM <29>
CLK_PCI_5048 <36>
CLK_PCI_MEC <37>
+3.3V_RUN
6
5
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
3 4
QC1B
QC1B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
LAN_SMBCLK <28>
NFC_SMBCLK <20>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
DIFFCLK_BIASREF
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
Rev1p2
Rev1p2
2
2
1
QC1A
QC1A
LAN_SMBDATA <28>
NFC_SMBDATA <20>
TAA_DO64
TAA_DO32
TAA_CLK64
TAA_CLK32
TAA_CS0#_R
TAA_CS1#_R
TAA_DIN64
TAA_DIN32
A25
XTAL24_IN
B25
XTAL24_OUT
K21
M21
C26
CLK_BIASREF
C35
MCP_TESTLOW1
C34
MCP_TESTLOW2
AK8
MCP_TESTLOW3
AL8
MCP_TESTLOW4
AN15
AP15
PCI_CLK_LPC_1
B35
A35
DDR_XDP_WAN_SMBCLK <18,19,25,31,9>
DDR_XDP_WAN_SMBDAT <18,19,25,31,9>
PCH_SMB_ALERT#
MEM_SMBCLK
MEM_SMBDATA
SML1_SMBCLK
SML1_SMBDATA
SML0CLK
SML0DATA
+3.3V_M
JTAA1
JTAA1
2
112
4
334
6
556
8
TAA_DO3_64
778
10
TAA_DO3_32
9910
12
TAA_DO2_64
111112
14
TAA_DO2_32
131314
16
151516
18
171718
20
191920
22
G21G
24
G23G
ACES_50185-02041-001
ACES_50185-02041-001
CONN@
CONN@
1 2
RC40@ 0_0402_5%RC40@ 0_0402_5%
1M_0402_5%
1M_0402_5%
RC44
RC44
1 2
T6 @
T6 @
PAD~D
PAD~D
T7 @
T7 @
PAD~D
PAD~D
1 2
1 2
1 2
+3.3V_ALW_PCH
12
RC2710K_0402_5% RC2710K_0402_5%
12
RC282.2K_0402_5% RC282.2K_0402_5%
12
1 2
1 2
XTAL24_IN_R
RC65 @0_0402_5% RC65 @0_0402_5%
RC64 EMC_3@22_0402_5% RC64 EMC_3@22_0402_5%
RC66 EMC@22_0402_5% RC66 EMC@22_0402_5%
CLK_BIASREF
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
RC302.2K_0402_5% RC302.2K_0402_5%
RC362.2K_0402_5% RC362.2K_0402_5%
RC372.2K_0402_5% RC372.2K_0402_5%
12
RC381K_0402_5% RC381K_0402_5%
12
RC391K_0402_5% RC391K_0402_5%
1 2
R432@ 33_0402_5%R432@ 33_0402_5%
R485@ 33_0402_5%R485@ 33_0402_5%
1 2
1 2
R582@ 33_0402_5%R582@ 33_0402_5%
1 2
R595@ 33_0402_5%R595@ 33_0402_5%
18P_0402_50V8J
3
1
18P_0402_50V8J
4
YC2
YC2
24MHZ_12PF_X3G024000DC1H
24MHZ_12PF_X3G024000DC1H
2
18P_0402_50V8J
18P_0402_50V8J
PCI_CLK_LPCPCI_CLK_LPC_0
CLK_PCI_DOCK <34>
CLK_PCI_LPDEBUG <37>
1 2
1 2
1 2
1 2
1 2
1
CC7
CC7
12
CC6
CC6
12
+PCH_VCCACLKPLL
RC453.01K_0402_1% RC453.01K_0402_1%
RC4610K_0402_5% RC4610K_0402_5%
RC4710K_0402_5% RC4710K_0402_5%
RC5010K_0402_5% RC5010K_0402_5%
RC5210K_0402_5% RC5210K_0402_5%
PCH_SPI_DO3
PCH_SPI_DO3
PCH_SPI_DO2
PCH_SPI_DO2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (2/12)
CPU (2/12)
CPU (2/12)
LA-9591P
LA-9591P
LA-9591P
1
7 58Friday, May 17, 2013
7 58Friday, May 17, 2013
7 58Friday, May 17, 2013
0.4
0.4
0.4
5
HASWELL_MCP_E
D D
DDR_A_D[0..63]<18>
C C
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
UC1C
UC1C
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
HASWELL_MCP_E
DDR CHANNEL A
DDR CHANNEL A
4
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
3
UC1D
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
UC1D
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
DDR_B_D[0..63]<19>
AU37
M_CLK_DDR#0
AV37
M_CLK_DDR0
AW36
M_CLK_DDR#1
AY36
M_CLK_DDR1
AU43
DDR_CKE0_DIMMA
AW43
DDR_CKE1_DIMMA DDR_CKE2_DIMMB
AY42
AY43
AP33
DDR_CS0_DIMMA#
AR32
DDR_CS1_DIMMA# DDR_CS2_DIMMB#
AP32
AY34
DDR_A_RAS#
AW34
DDR_A_WE#
AU34
DDR_A_CAS#
AU35
DDR_A_BS0
AV35
DDR_A_BS1
AY41
DDR_A_BS2
AU36
DDR_A_MA0
AY37
DDR_A_MA1
AR38
DDR_A_MA2
AP36
DDR_A_MA3
AU39
DDR_A_MA4
AR36
DDR_A_MA5
AV40
DDR_A_MA6
AW39
DDR_A_MA7
AY39
DDR_A_MA8
AU40
DDR_A_MA9
AP35
DDR_A_MA10
AW41
DDR_A_MA11
AU41
DDR_A_MA12
AR35
DDR_A_MA13
AV42
DDR_A_MA14
AU42
DDR_A_MA15
AJ61
DDR_A_DQS#0
AN62
DDR_A_DQS#1
AM58
DDR_A_DQS#2
AM55
DDR_A_DQS#3
AV57
DDR_A_DQS#4
AV53
DDR_A_DQS#5
AL43
DDR_A_DQS#6
AL48
DDR_A_DQS#7
AJ62
DDR_A_DQS0
AN61
DDR_A_DQS1
AN58
DDR_A_DQS2
AN55
DDR_A_DQS3
AW57
DDR_A_DQS4
AW53
DDR_A_DQS5
AL42
DDR_A_DQS6
AL49
DDR_A_DQS7
AP49
AR51
AP51
M_CLK_DDR#0 <18>
M_CLK_DDR0 <18>
M_CLK_DDR#1 <18>
M_CLK_DDR1 <18>
DDR_CKE0_DIMMA < 18>
DDR_CKE1_DIMMA < 18>
DDR_CS0_DIMMA# <18>
DDR_CS1_DIMMA# <18>
DDR_A_RAS# <18>
DDR_A_WE# <18>
DDR_A_CAS# <18>
DDR_A_BS0 <18>
DDR_A_BS1 <18>
DDR_A_BS2 <18>
DDR_A_MA[0..15] <18>
DDR_A_DQS#[0..7] <18>
DDR_A_DQS[0..7] <18>
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
2
HASWELL_MCP_E
HASWELL_MCP_E
DDR CHANNEL B
DDR CHANNEL B
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
DDR_CKE3_DIMMB
DDR_CS3_DIMMB#
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
1
M_CLK_DDR#2 <19>
M_CLK_DDR2 <19>
M_CLK_DDR#3 <19>
M_CLK_DDR3 <19>
DDR_CKE2_DIMMB < 19>
DDR_CKE3_DIMMB < 19>
DDR_CS2_DIMMB# <19 >
DDR_CS3_DIMMB# <19 >
DDR_B_RAS# <19>
DDR_B_WE# <19>
DDR_B_CAS# <19>
DDR_B_BS0 <19>
DDR_B_BS1 <19>
DDR_B_BS2 <19>
DDR_B_MA[0..15] <19>
DDR_B_DQS#[0..7] <19>
DDR_B_DQS[0..7] <19>
Rev1p2
Rev1p2
3 OF 19
3 OF 19
A A
Rev1p2
4 OF 19
4 OF 19
Rev1p2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (3/12)
CPU (3/12)
CPU (3/12)
LA-9591P
LA-9591P
LA-9591P
1
8 58Friday, May 17, 2013
8 58Friday, May 17, 2013
8 58Friday, May 17, 2013
0.4
0.4
0.4
5
+3.3V_ALW_PCH
D D
C C
B B
A A
+PCH_VCCDSW3_3
+3.3V_RUN
PCH_JTAG_TDI<6>
+1.05V_VCCST
1 2
RC70 10K_0402_5%RC70 10K_040 2_5%
1 2
RC98 10K_0402_5%RC98 10K_040 2_5%
1 2
RC74@ 10K_0402_5%RC74@ 10K_0402_5%
RP12
RP12
4 5
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
1 2
RC136 10K_ 0402_5%RC136 10K_0402 _5%
1 2
RC81@ 8.2K_0402_5%RC81@ 8.2K_0402_5%
PCH_JTAG_TDO<6>
1 2
RC96 0_0402_5%
RC96 0_0402_5%
XDP@
XDP@
PCH_JTAG_TMS<6>
1 2
RC113@ 49.9_0402_1%RC113@ 49.9_0402_1%
1 2
RC114 62_0402_5%RC1 14 62_0402_5%
H_PROCHOT#
1
@
@
CC149
CC149
22P_0402_50V8J
22P_0402_50V8J
2
EMI request add
H_CPUPWRGD
10K_0402_5%
10K_0402_5%
12
RC115
RC115
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC115
ME_SUS_PWR_ACK
SUSACK#
SUS_STAT#/LPCPD#
PCH_BATLOW#
AC_PRESENT
PCH_PCIE_WAKE#
PCH_RSMRST#_R
ME_RESET#
TDI_XDP TDI_XDP_R
RUNPWROK<36,37>
H_CATERR#
H_PROCHOT#
PCH_AUDIO_EN <12>
ME_SUS_PWR_ACK<37>
CC41
XDP@CC41
XDP@
12
0.1U_0402_25V6
0.1U_0402_25V6
1 2
TDO_XDP
RC95 0_0402_5%
RC95 0_0402_5%
XDP@
XDP@
RUNPWROK
1 2
RC103 0_0402_5%
RC103 0_0402_5%
XDP@
XDP@
RUNPWROK
1 2
TMS_XDP
RC101 0_0402_5%
RC101 0_0402_5%
XDP@
XDP@
RUNPWROK
TRST#_XDP
RUNPWROK
PCH_JTAG_TRST#<6>
PCH_JTAG_JTAGX<6>
PLTRST_NFC#< 20>
PLTRST_USH#<29>
PLTRST_MMI#<30>
PLTRST_LAN#<28>
PLTRST_VMM2320#<21>
PCH_RSMRST#_Q<38>
+3.3V_RUN
SYS_PWROK<36>
RESET_OUT#< 15,37>
DDR3 COMPENSATION SIGNALS
12
SM_RCOMP0
RC125200_0402_1% RC125200_0402_1%
12
SM_RCOMP1
RC129121_0402_1% RC129121_0402_1%
12
SM_RCOMP2
RC133100_0402_1% RC133100_0402_1%
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
5
XDP_DBRESET#
RC76@ 8.2K_0402_5 %RC76@ 8.2K_0402_5 %
SUSACK#<36>
UC6
UC6
XDP@
XDP@
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
74CBTLV3126BQ_DHVQFN14_2P5X3
reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0
PCH_JTAG_TDO
PCH_JTAG_TCK
H_PROCHOT#<37,46,47,48>
DDR3_DRAMRST#_CPU<18>
H_CPUPWRGD
12
@
@
CC90
CC90
100P_0402_50V8J
100P_0402_50V8J
ESD request add
4
RC72@ 0_0402_5%RC72@ 0_0402_5%
12
ME_RESET#
1 2
RC86@ 0_0402_5%RC86@ 0_0402_5%
1 2
RC87@ 0_0402_5%RC87@ 0_0402_5%
1 2
RC88@ 0_0402_5%RC88@ 0_0402_5%
1 2
RC139@ 0_0402_5%RC139@ 0_0402_5%
1 2
RC89@ 0_0402_5%RC89@ 0_0402_5%
1 2
RC90@ 0_0402_5%RC90@ 0_0402_5%
1 2
RC91@ 0_0402_5%RC91@ 0_0402_5%
1 2
RC92@ 0_0402_5%RC92@ 0_0402_5%
1 2
RC93@ 0_0402_5%RC93@ 0_0402_5%
1 2
RC94@ 0_0402_5%RC94@ 0_0402_5%
SIO_PWRBTN#<37, 9>
AC_PRESENT<37>
SIO_SLP_S0#<37>
SIO_SLP_WLAN#<36>
1B
2B
3B
4B
GND
GND PAD
12
CPU_XDP_TRST#
RC135@ 0_0402_5% RC135@ 0_0402_5%
12
CPU_XDP_TCLK
RC97@ 0_0402_5% RC97@0_0402_ 5%
12
TDO_XDP
RC123 @0_0402_5% RC123 @0_0402_5%
12
TDI_XDP_R
RC104 @0_0402_5% RC104 @0_0402_5%
12
CPU_XDP_TCLK
RC124 @0_0402_5% RC124 @0_0402_5%
CPU_DETECT#<36>
PECI_EC<37>
1 2
RC117 56_0402_5%RC1 17 56_0402_5%
DDR_PG_CTRL<18>
H_PROCHOT#_R
4
1 2
+3.3V_RUN
1
B
2
A
3
CPU_XDP_TDO
6
CPU_XDP_TDI
8
CPU_XDP_TMS
11
CPU_XDP_TRST#
7
15
CPU_DETECT#
H_CATERR#
PECI_EC
H_CPUPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CC8@
CC8@
1 2
5
0.1U_0402_25V6
0.1U_0402_25V6
P
4
O
G
UC2@
UC2@
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
3
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK
PM_APWROK_R
PCH_PLTRST#
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
SIO_PWRBTN#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#
SIO_SLP_WLAN#
D61
PROC_DETECT
K61
CATERR
N62
PECI
K63
PROCHOT
C61
PROCPWRGD
AU60
SM_RCOMP0
AV60
SM_RCOMP1
AU61
SM_RCOMP2
AV15
SM_DRAMRST
AV61
SM_PG_CNTL1
SYS_RESET#
AK2
SUSACK
AC3
SYS_RESET
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST
AW6
RSMRST
AV4
SUSWARN/SUSPWRDNACK/GPIO30
AL7
PWRBTN
AJ8
ACPRESENT/GPIO31
AN4
BATLOW/GPIO72
AF3
SLP_S0
AM5
SLP_WLAN/GPIO29
UC1B
UC1B
PCH_DPWROK
ME_SUS_PWR_ACK_R
RESET_OUT#
UC1H
UC1H
HASWELL_MCP_E
HASWELL_MCP_E
MISC
MISC
THERMAL
THERMAL
PWR
PWR
DDR3
DDR3
3
1
PCH_PLTRST#
2
1 2
RC79 0_0402_5%@ RC79 0_0402_5%@
RC82 0_0402_5%@ RC82 0_0402_5%@
RC84@ 0_0402_5%RC84@ 0_0402_5%
H_VCCST_PWRGD<15>
DDR_XDP_WAN_SMBDAT<18,19,25,31,7>
DDR_XDP_WAN_SMBCLK<18,19,25,31,7>
2 OF 19
2 OF 19
PCH_RSMRST#_R
1 2
SUSACK#_R
1 2
SYS_PWROK_R
HASWELL_MCP_E
HASWELL_MCP_E
SYSTEM POWER MANAGEMENT
SYSTEM POWER MANAGEMENT
8 OF 19
8 OF 19
RC105 1K_0 402_5%
RC105 1K_0 402_5%
XDP@
XDP@
H_CPUPWRGD
SIO_PWRBTN#<37, 9>
CPU_PWR_DEBUG#<15>
SYS_PWROK
PCH_JTAG_TCK<6>
JTAG
JTAG
3
2
+3.3V_RUN
CC9@
CC9@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
5
P
B
4
O
A
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
+1.05V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
CC10
CC10
Place near JXDP1
RC5 need to close to JCPU1
1 2
RC106@ 1K_0 402_5%RC106@ 1K_0402_5%
RC107@ 0_0402 _5%RC107@ 0_0402_5%
RC108@ 0_0402 _5%RC108@ 0_0402_5%
RC110@ 0_0402 _5%RC110@ 0_0402_5%
RC111@ 0_0402 _5%RC111@ 0_0402_5%
RC112@ 0_0402 _5%RC112@ 0_0402_5%
RC142@ 0_0402 _5%RC142@ 0_0402_5%
PCH_PLTRST#_EC
UC3
UC3
DSWVRMEN
DPWROK
SLP_S4
SLP_S3
SLP_SUS
SLP_LAN
0.1U_0402_25V6
0.1U_0402_25V6
@
@
12
CC11
CC11
1 2
1 2
1 2
1 2
1 2
1 2
1 2
WAKE
SLP_A
Rev1p2
Rev1p2
AW7
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7
PCH_PLTRST#_EC <29,3 1,36,37>
SIO_SLP_A#
PM_APWROK
PM_APWROK<37>
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
SIO_SLP_LAN#
CPU_XDP_PREQ#
CPU_XDP_PRDY#
CFG0
CFG0<13>
CFG1
CFG1<13>
CFG2
CFG2<13>
CFG3
CFG3<13>
XDP_OBS0_R
XDP_OBS1_R
CFG4
CFG4<13>
CFG5
CFG5<13>
CFG6
CFG6<13>
CFG7
CFG7<13>
H_VCCST_PWRGD_XDP
CFD_PWRBTN#_XDP
CPU_PWR_DEBUG#_R
SYS_PWROK_XDP
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
PCH_JTAG_TCK_R
CPU_XDP_TCLK
PCH_DPWROK <36>
PCH_PCIE_WAKE# <37>
CLKRUN# < 12,29,36,37>
T10 @P AD~DT10 @PAD~D
SIO_SLP_S5# <37>
T11 @PAD~DT11 @PAD~D
T12@PAD~DT12@PAD~D
SIO_SLP_S4# <36,39,43>
SIO_SLP_S3# <36,39,43>
SIO_SLP_A# <36,39,44>
SIO_SLP_SUS# <36>
SIO_SLP_LAN# <28,36>
+1.05V_RUN
+3.3V_ALW_PCH
1K_0402_5%
1K_0402_5%
1
2
RC144@ 0_0402 _5%RC144@ 0_0402_5%
JXDP1
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
OBSDATA_A09OBSDATA_C0
OBSDATA_A111OBSDATA_C1
13
GND4
OBSDATA_A215OBSDATA_C2
OBSDATA_A317OBSDATA_C3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
OBSDATA_B027OBSDATA_D0
OBSDATA_B129OBSDATA_D1
31
GND10
OBSDATA_B233OBSDATA_D2
OBSDATA_B335OBSDATA_D3
37
GND12
PWRGOOD/HOOK039ITPCLK/HOOK4
41
HOOK1
VCC_OBS_AB43VCC_OBS_CD
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
RC102
XDP@
RC102
XDP@
1 2
SYS_PWROK_XDP
0.1U_0402_25V6
0.1U_0402_25V6
12
CC48@
CC48@
J62
CPU_XDP_PRDY#
PRDY
K62
CPU_XDP_PREQ#
PREQ
E60
CPU_XDP_TCLK
PROC_TCK
E61
PROC_TMS
PROC_TRST
PROC_TDO
CPU_XDP_TMS
E59
CPU_XDP_TRST#
F63
CPU_XDP_TDI
PROC_TDI
F62
CPU_XDP_TDO
J60
XDP_OBS0_R
BPM#0
H60
XDP_OBS1_R
BPM#1
H61
XDP_OBS2_R
BPM#2
H62
XDP_OBS3_R
BPM#3
K59
XDP_OBS4_R
BPM#4
H63
XDP_OBS5_R
BPM#5
K60
XDP_OBS6_R
BPM#6
J61
XDP_OBS7_R
BPM#7
Rev1p2
Rev1p2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Place near JXDP1.47
T122 @PAD~D T122 @PAD~D
T126 @PAD~D T126 @PAD~D
T129 @PAD~D T129 @PAD~D
T130 @PAD~D T130 @PAD~D
T131 @PAD~D T131 @PAD~D
T132 @PAD~D T132 @PAD~D
2
+3.3V_ALW2
0.1U_0402_25V6
0.1U_0402_25V6
5
P
B
O
A
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
1 2
CC82@
CC82@
1 2
4
PM_APWROK_R
UC7
UC7
OBSFN_C0
OBSFN_C1
OBSFN_D0
OBSFN_D1
ITPCLK#/HOOK5
RESET#/HOOK6
DBR#/HOOK7
Place near JXDP1.48
XDP_DBRESET#
1
+RTC_CELL
330K_0402_1%
330K_0402_1%
RC73
RC73
1 2
DSWODVREN
330K_0402_1%
330K_0402_1%
RC78@
RC78@
1 2
DSWODVREN - ON DIE DSW VR ENABLE
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
JAPS1
JAPS1
PCH_PLTRST#_EC
+1.05V_RUN
12
RC280@51_0402_1% RC280@51_0402_1%
12
RC116
RC116
12
RC118@
RC118@
12
RC119@
RC119@
12
RC120@
RC120@
12
RC122
RC122
12
RC127
RC127
12
RC131
@
RC131
@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
CONN@
CONN@
ACES_50506-01841-P01
ACES_50506-01841-P01
+3.3V_RUN
+1.05V_RUN
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
+PCH_VCCDSW3_3
PCH_RTCRST#< 6>
POWER_SW#_M B<37,40>
+1.05V_RUN
2
GND1
4
CFG17
6
CFG16
8
GND3
10
CFG8
12
CFG9
14
GND5
16
CFG10
18
CFG11
20
GND7
22
CFG19
24
CFG18
26
GND9
28
CFG12
30
CFG13
32
GND11
34
CFG14
36
CFG15
38
GND13
40
42
44
46
XDP_RST#_R
48
XDP_DBRESET#
50
GND15
52
TDO_XDP
TD0
54
TRST#
TMS
GND17
CONN@SAMTE_BSH-030-01-L-D-A
CONN@SAMTE_BSH-030-01-L-D-A
TRST#_XDP
56
TDI_XDP
TDI
58
TMS_XDP
60
0.1U_0402_25V6
0.1U_0402_25V6
12
CC68
XDP@CC68
XDP@
RC99 1K_0402_5%
RC99 1K_0402_5%
XDP@
XDP@
CFG17 <13>
CFG16 <13>
CFG8 < 13>
CFG9 < 13>
CFG10 <13>
CFG11 <13>
CFG19 <13>
CFG18 <13>
CFG12 <13>
CFG13 <13>
CFG14 <13>
CFG15 <13>
RC109 1K_0402_5%
RC109 1K_0402_5%
XDP@
XDP@
1 2
TDO_XDP
XDP_DBRESET#
1K_0402_5%
1K_0402_5%
CPU_XDP_TMS
51_0402_1%
51_0402_1%
CPU_XDP_TDI
51_0402_1%
51_0402_1%
CPU_XDP_PREQ#
51_0402_1%
51_0402_1%
CPU_XDP_TDO
51_0402_1%
51_0402_1%
CPU_XDP_TCLK
51_0402_1%
51_0402_1%
CPU_XDP_TRST#
51_0402_1%
51_0402_1%
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
12
CFG3CFG3_R
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (4/12)
CPU (4/12)
CPU (4/12)
LA-9591P
LA-9591P
LA-9591P
1
9 58Friday, May 17, 2013
9 58Friday, May 17, 2013
9 58Friday, May 17, 2013
0.4
0.4
0.4
5
D D
4
HASWELL_MCP_E
UC1A
UC1A
HASWELL_MCP_E
3
2
1
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
Rev1p2
Rev1p2
DDPB_HPD
DDPC_HPD
EDP_HPD
Rev1p2
Rev1p2
C45
EDP_CPU_LANE_N0
B46
EDP_CPU_LANE_P0
A47
EDP_CPU_LANE_N1
B47
EDP_CPU_LANE_P1
C47
C46
A49
B49
A45
EDP_CPU_AUX#
B45
EDP_CPU_AUX
D20
EDP_COMP
A43
B9
CPU_DPB_CTRLCLK
C9
CPU_DPB_CTRLDAT
D9
CPU_DPC_CTRLCLK
D11
CPU_DPC_CTRLDAT
C5
CPU_DPB_AUX#
B6
CPU_DPC_AUX#
B5
CPU_DPB_AUX
A6
CPU_DPC_AUX
C8
DPB_HPD
A8
DPC_HPD
D6
EDP_CPU_LANE_N0 <22>
EDP_CPU_LANE_P0 <22>
EDP_CPU_LANE_N1 <22>
EDP_CPU_LANE_P1 <22>
EDP_CPU_AUX# <22>
EDP_CPU_AUX <22>
CPU_DPB_CTRLCLK <23>
CPU_DPB_CTRLDAT <23>
CPU_DPC_CTRLCLK <27>
CPU_DPC_CTRLDAT <27>
CPU_DPC_AUX# <27>
CPU_DPC_AUX <27>
DPB_HPD <23>
DPC_HPD <27>
RC158
RC158
EDP_CPU_HPD <22>
100K_0402_5%
100K_0402_5%
12
COMPENSATION PU FOR eDP
+VCCIOA_OUT
RP3
RP3
1
2
3
4 5
8
7
6
12
12
12
12
12
12
RC13424.9_0402_1% RC 13424.9_0402_1%
+3.3V_RUN
RC147100K_040 2_5% RC147100K _0402_5%
RC149100K_040 2_5% RC149100K _0402_5%
RC151100K_0402_5% RC151100K_0402_5%
RC153100K_0402_5% RC153100K_0402_5%
RC155100K_0402_5% RC155100K_0402_5%
EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
CPU_DPB_AUX#
CPU_DPC_AUX#
DPC_HPD
CPU_DPB_AUX
CPU_DPC_AUX
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
AD4
C54
C55
B58
C58
B55
A55
A57
B57
C51
C50
C53
B54
C49
B50
A53
B53
B8
A9
C6
U6
P4
N4
N2
U7
L1
L3
R5
L4
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
UC1I
UC1I
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDI EDP
DDI EDP
1 OF 19
1 OF 19
HASWELL_MCP_E
HASWELL_MCP_E
eDP SIDEBAND
eDP SIDEBAND
GPIO
GPIO
9 OF 19
9 OF 19
DISPLAY
DISPLAY
EDP_RCOMP
EDP_DISP_UTIL
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
EDP_BIA_PWM<22>
PANEL_BKLEN<22>
ENVDD_PCH<22,36>
T13@ PA D~DT13@ PAD~D
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
DDI2_LANE_N0
DDI2_LANE_P0
DDI2_LANE_N1
DDI2_LANE_P1
DDI2_LANE_N2
DDI2_LANE_P2
DDI2_LANE_N3
DDI2_LANE_P3
EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
DGPU_PWROK
PIRQC#
PIRQD#
TOUCHPAD_INTR#
CODEC_IRQ
DDI1_LANE_N0<23>
DDI1_LANE_P0<23>
DDI1_LANE_N1<23>
DDI1_LANE_P1<23>
DDI1_LANE_N2<23>
DDI1_LANE_P2<23>
DDI1_LANE_N3<23>
DDI1_LANE_P3<23>
DDI2_LANE_N0<27>
DDI2_LANE_P0<27>
DDI2_LANE_N1<27>
+3.3V_RUN
C C
HDD_FALL_INT<25>
B B
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R495@ 0_0402_5%R495@ 0_0402_5%
1 2
R494 0_0402_5%R494 0_0402_5%
CONTACTLESS_DET#
DGPU_PWROK
TOUCHPAD_INTR#
PIRQC#
PIRQD#
ENVDD_PCH
12
CODEC_IRQ
PIRQC#
PIRQD#
RC137 10K_0402_5%RC137 10K_0402_5%
RC138 10K_0402_5%RC138 10K_0402_5%
RC140 10K_0402_5%RC140 10K_0402_5%
RC146 10K_0402_5%RC146 10K_0402_5%
RC148 10K_0402_5%RC148 10K_0402_5%
RC152@ 100K_0402_5%RC152@ 100K_0402_5%
RC154@ 1K_0402_5%RC154@ 1K_0402_5%
DDI2_LANE_P1<27>
DDI2_LANE_N2<27>
DDI2_LANE_P2<27>
DDI2_LANE_N3<27>
DDI2_LANE_P3<27>
CONTACTLESS_DET#<29>
TOUCH_RST_N_GYRO_INT1<12>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (5/12)
CPU (5/12)
CPU (5/12)
LA-9591P
LA-9591P
LA-9591P
10 58Friday, May 17, 2013
10 58Friday, May 17, 2013
10 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
D D
PCIE_PRX_MMITX_N5<30>
MMI -->
C C
10/100/1G LAN --->
WLAN (Mini Card 2)--->
PCIE_PRX_MMITX_P5<30>
PCIE_PTX_MMIRX_N5<30>
PCIE_PTX_MMIRX_P5<30>
PCIE_PRX_GLANTX_N3<28>
PCIE_PRX_GLANTX_P3<28>
PCIE_PTX_GLANRX_N3<28>
PCIE_PTX_GLANRX_P3<28>
PCIE_PRX_WLANTX_N 4<31>
PCIE_PRX_WLANTX_P4<31>
PCIE_PTX_WLANRX_N 4<31>
PCIE_PTX_WLANRX_P4<31>
Ext USB Port 2 <----
B B
1 2
+PCH_AUSB3PLL
RC161 3.01K_0402_1%RC161 3.01K_0402_1%
1 2
RC163@ 0_0402_5%RC163@ 0_0402_5%
T16@ PAD~DT16@ PAD~D
T17@ PAD~DT17@ PAD~D
4
PCIE_PRX_MMITX_N5
PCIE_PRX_MMITX_P5
PCIE_PTX_MMIRX_N5
PCIE_PTX_MMIRX_P5
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
PCIE_PRX_WLANTX_N 4
PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N 4
PCIE_PTX_WLANRX_P4
USB3RN3<32 >
USB3RP3<32>
USB3TN3<32>
USB3TP3<32>
PCH_PCIE_RCOMP
PCH_PCIE_IREF
F10
E10
C23
C22
F8
E8
B23
A23
H10
G10
B21
C21
E6
F6
B22
A21
G11
F11
C29
B30
F13
G13
B29
A29
G17
F17
C30
C31
F15
G15
B31
A31
E15
E13
A27
B27
UC1K
UC1K
PERN5_L0
PERP5_L0
PETN5_L0
PETP5_L0
PERN5_L1
PERP5_L1
PETN5_L1
PETP5_L1
PERN5_L2
PERP5_L2
PETN5_L2
PETP5_L2
PERN5_L3
PERP5_L3
PETN5_L3
PETP5_L3
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
HASWELL_MCP_E
HASWELL_MCP_E
PCIe USB
PCIe USB
11 OF 19
11 OF 19
3
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USBRBIAS
RSVD
RSVD
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
Rev1p2
Rev1p2
AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USBP0ÂUSBP0+
USBP1ÂUSBP1+
USBP2ÂUSBP2+
USBP3ÂUSBP3+
USBP4ÂUSBP4+
USBP5ÂUSBP5+
USBP6ÂUSBP6+
USBP7ÂUSBP7+
USBRBIAS
USB_OC1#
USB_OC2#
USB_OC3#
USBP0- <33>
USBP0+ <33>
USBP1- <35>
USBP1+ <35>
USBP2- <31>
USBP2+ <31>
USBP3- <22>
USBP3+ <22>
USBP4- <29>
USBP4+ <29>
USBP5- <32>
USBP5+ <32>
USBP6- <31>
USBP6+ <31>
USBP7- <22>
USBP7+ <22>
USB3RN1 <35>
USB3RP1 <35>
USB3TN1 <35>
USB3TP1 <35>
USB3RN2 <33>
USB3RP2 <33>
USB3TN2 <33>
USB3TP2 <33>
T14@PAD~D T14@PAD~D
T15@PAD~D T15@PAD~D
USB_OC0# <33>
USB_OC1# <35>
USB_OC2# <12,33>
2
-----> Ext Port 1 and DOCK2 (USB SW)
----->Ext Port 2 IO/B
----->WLAN/BT
----->Camera
----->USH
----->Ext Port 3 and DOCK1(USB SW)
----->WWAN
----->Touch
----->Ext USB3 Port 3 IO/B
----->Ext USB3 Port 1
USBRBIASUSB_OC0#
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
mils.
USB_OC0#
USB_OC1#
USB_OC3#
1 2
1 2
1 2
22.6_0402_1%
22.6_0402_1%
12
RC159
RC159
RC16010K_0402_5% RC 16010K_0402_5%
RC16510K_0402_5% RC 16510K_0402_5%
RC16610K_0402_5% RC 16610K_0402_5%
1
+3.3V_ALW_PCH
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (6/12)
CPU (6/12)
CPU (6/12)
LA-9591P
LA-9591P
LA-9591P
11 58Friday, May 17, 2013
11 58Friday, May 17, 2013
11 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
+PCH_VCCDSW3_3
D D
RC206 10K_0402_5%RC 206 10K_0402_5%
+3.3V_RUN
RC170 100K_0402_5%RC170 100K_0402_5%
RC199 100K_0402_5%RC199 100K_0402_5%
+PCH_VCCDSW3_3
RC197 10K_0402_5%RC197 10K_0402_5%
+3.3V_ALW_PCH
C C
B B
RC175 10K_0402_5%RC175 10K_0402_5%
RC200 10K_0402_5%RC200 10K_0402_5%
RC171 10K_0402_5%RC171 10K_0402_5%
RC230 10K_0402_5%RC230 10K_0402_5%
RC211 100K_0402_5%RC211 100K_0402_5%
RC210 100K_0402_5%RC210 100K_0402_5%
@
@
RC169
1 2
RP13
RP13
4 5
3
2
1
10K_8P4R_5%
10K_8P4R_5%
RP14
RP14
4 5
3
2
1
10K_8P4R_5%
10K_8P4R_5%
12
EC_WAKE#
12
MPHYP_PWR_EN
12
SIO_EXT_SCI#
12
PM_LANPHY_ENABLE
12
MEDIACARD_PWR EN
12
PCH_GPIO44
12
MEDIACARD_RST#
PCH_GPIO46
SIO_EXT_SMI#
6
SLATE_MODE_R
7
MEDIACARD_IRQ#
8
PCH_GPIO9
6
SIO_EXT_WAKE#
7
KB_DET#
8
12
3.3V_CAM_EN#
12
NFC_IRQ
12
MPHYP_PWR_EN
10K_0402_5%RC169
10K_0402_5%
1 2
RC177 @0_0402_5% RC177 @0_0402_5%
USB_OC2# <11,33>
PCH_GPIO73 <7>
LAN_WAKE# <28,37>
PM_LANPHY_ENABLE<28>
PCH_NFC_RST<20>
NFC_IRQ<20>
MEDIACARD_RST#<30>
MEDIACARD_PWR EN<30>
MEDIACARD_IRQ#<30>
TOUCH_PANEL_INTR#<22>
KB_DET#<38>
+3.3V_RUN +3.3V_RUN
1K_0402_5%
1K_0402_5%
12
RC283@
RC283@
PCH_GPIO66
1K_0402_5%
1K_0402_5%
12
RC288@
RC288@
PCH_AUDIO_EN<9>
SIO_EXT_WAKE#<36>
LAN_RST#<28>
T139@ PAD~DT139@ PAD~D
EC_WAKE#<37>
NFC_DET#<20>
T140@ PAD~DT140@ PAD~D
T141@ PAD~DT141@ PAD~D
MPHYP_PWR_EN<39>
T138@ PAD~DT138@ PAD~D
3.3V_CAM_EN#<22>
SIO_EXT_SMI#<37>
T137@ PAD~DT137@ PAD~D
mSATA_DEVSLP<31>
HDD_DEVSLP<25>
SIO_EXT_SCI#<37>
SPKR<26>
4
PCH_AUDIO_EN
SIO_EXT_WAKE#
PCH_GPIO15
PCH_GPIO17
EC_WAKE#
NFC_IRQ
MEDIACARD_RST#
SLATE_MODE_R
PCH_GPIO44
PCH_GPIO48
PCH_GPIO49
MPHYP_PWR_EN
KB_DET#
PCH_GPIO14
3.3V_CAM_EN#
SIO_EXT_SMI#
PCH_GPIO46
PCH_GPIO9
PCH_GPIO10
SIO_EXT_SCI#
SPKR
10K_0402_5%
10K_0402_5%
12
1K_0402_5%
1K_0402_5%
12
@
@
RC218
RC218
RC287@
RC287@
BBS_BIT
AM7
AM4
AM3
AM2
AU2
AD6
AD5
AN5
AD7
AN3
AG6
AP1
AL4
AT5
AK4
AB6
AT3
AH4
AG5
AG3
P1
Y1
T3
U4
Y3
P3
Y2
P2
C4
L2
N5
V2
UC1J
UC1J
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
GPIO
GPIO
+3.3V_ALW_PCH
3
HASWELL_MCP_E
HASWELL_MCP_E
D60
THERMTRIP
RCIN/GPIO82
CPU/
CPU/
MISC
MISC
LPIO
LPIO
10 OF 19
10 OF 19
I2C1_SDA_TCH_PAD
I2C1_SCL_TCH_PAD I2C1_SCL_TCH_PAD
1K_0402_5%
1K_0402_5%
12
RC190
RC190
PCH_GPIO15
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
Rev1p2
Rev1p2
RC174@ 0_0402_5%RC174@ 0_0402_5%
RC176@ 0_0402_5%RC176@ 0_0402_5%
+3.3V_RUN
H_THERMTRIP#_R
V4
SIO_RCIN#
T4
IRQ_SERIRQ
AW15
PCH_OPI_COMP
AF20
AB21
R6
PCH_GPIO83
L6
PCH_GPIO84
N6
PCH_GPIO85
L8
BBS_BIT
R7
PCH_GPIO87
L5
3.3V_TP_EN
N7
K2
J1
CPPE#
K3
CPUSB#
J2
G1
K4
G2
FFS_INT2
J3
LCD_CBL_DET#
J4
F2
I2C0_SDA
F3
I2C0_SCL
G4
I2C1_SDA_TCH_PAD
F1
I2C1_SCL_TCH_PAD
E3
USH_DET#
F4
CAM_MIC_CBL_DET#
D3
PCH_GPIO66
E4
TPM_ID0
C3
TPM_ID1
E2
SLP_ME_CSW_DEV #
12
12
I2C1_SCL_TCH_PAD <38>
1K_0402_5%
1K_0402_5%
12
RC222@
RC222@
I2C1_SDA_VMM <21>
I2C1_SCL_VMM <21>
I2C1_SDA_TCH_PAD <38>
SPKR
2
SIO_RCIN# <37>
IRQ_SERIRQ <29,36,37>
T18@ PA D~DT18@ PAD~D
T19@ PA D~DT19@ PAD~D
3.3V_TS_EN <22>
3.3V_HDD_EN <28>
CPPE# <31>
CPUSB# <31>
FFS_INT2 <25>
LCD_CBL_DET# <22>
USH_DET# <29>
CAM_MIC_CBL_DET# <22>
SLP_ME_CSW_DEV # <36>
12
12
ESD request add
RC172@ 0_0402_5% RC172@ 0_0402_5%
H_THERMTRIP#_R
@
@
CC91
CC91
100P_0402_50V8J
100P_0402_50V8J
H_THERMTRIP# <37>
TOUCH_RST_N_GYRO_INT1<10>
LANCLK_REQ#<28,7>
MINI1CLK_REQ#<31,7>
MINI2CLK_REQ#<31,7>
MPCIE_RST#<31,6>
CLKRUN#<29,36,37,9>
PCH_GPIO36<6>
H_THERMTRIP#
CAM_MIC_CBL_DET#
SLP_ME_CSW_DEV #
PCH_GPIO85
3.3V_TP_EN
TOUCH_PANEL_INTR#
3.3V_HDD_EN
LCD_CBL_DET#
CPUSB#
SIO_RCIN#
I2C0_SDA
I2C0_SCL
I2C1_SDA_TCH_PAD
IRQ_SERIRQ
PCH_GPIO87
FFS_INT2
USH_DET#
CPPE#
TPM_ID0
TPM_ID1
PCH_GPIO83
PCH_GPIO84
3.3V_TS_EN
PCH_OPI_COMP
PCH_GPIO83
1
12
12
12
12
12
12
12
12
12
12
12
RP4
RP4
45
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
RP5
RP5
45
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
RP6
RP6
45
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
RP7
RP7
1
8
2
7
3
6
4 5
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
RP11
RP11
45
3
6
2
7
1
8
10K_8P4R_5%
10K_8P4R_5%
1 2
1 2
7@
7@
+1.05V_VCCST
R241K_0402_5% R241K_0402_5%
+3.3V_RUN
RC183100K_0402_5% RC183100K_0402_5%
RC28210K_0402 _5% RC28210K_ 0402_5%
RC185100K _0402_5% RC185100K_0402_5%
RC19310K_0402 _5% RC19310K_ 0402_5%
RC28410K_0402 _5% RC28410K_ 0402_5%
RC28520K_0402_5% RC28520K_0402_5%
RC28910K_0402 _5% RC28910K_ 0402_5%
RC29010K_0402 _5% RC29010K_ 0402_5%
RC29110K_0402 _5% RC29110K_ 0402_5%
RC29410K_0402 _5% RC29410K_ 0402_5%
RC16849.9_0402 _1% RC16849.9_0402_1%
RC292100_0402_5%
RC292100_0402_5%
HIGH depop RC288 HIGH
LOW pop RC288 (DEFAULT)
A A
LOW(DEFAULT)
LPC
SPI
BOOT BIOS STRAP BIT BBS
TLS CONFIDENTIALITYTOP-BLOCK SWAP OVERRIDE
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (7/12)
CPU (7/12)
CPU (7/12)
LA-9591P
LA-9591P
LA-9591P
12 58Friday, May 17, 2013
12 58Friday, May 17, 2013
12 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
D D
4
3
2
1
CFG STRAPS for CPU
CFG1
CFG0
1K_0402_1%
1K_0402_1%
12
RC232@
RC232@
1K_0402_1%
1K_0402_1%
12
RC233@
RC233@
UC1S
UC1S
AC60
12
CFG_RCOMP
TDI_IREF
CFG0
CFG1
CFG4
CFG8
CFG9
CFG10
CFG_RCOMP
TDI_IREF
AC62
AC63
AA63
AA60
AA62
AA61
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
U63
U62
V63
A5
E1
D1
J20
H18
B12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
CFG0<9>
CFG1<9>
CFG2<9>
CFG3<9>
CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>
CFG8<9>
CFG9<9>
CFG10<9>
CFG11<9>
CFG12<9>
CFG13<9>
C C
CFG14<9>
CFG15<9>
CFG16<9>
CFG18<9>
CFG17<9>
CFG19<9>
T33@ PAD~DT33@ PAD~D
T35@ PAD~DT35@ PAD~D
T37@ PAD~DT37@ PAD~D
T38@ PAD~DT38@ PAD~D
T39@ PAD~DT39@ PAD~D
RC235 49.9_0402_1%RC235 49.9_0402_1%
1 2
RC236 8.2K_0402_1%RC236 8.2K_0402_1%
HASWELL_MCP_E
HASWELL_MCP_E
RESERVED
RESERVED
19 OF 19
19 OF 19
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
RSVD
RSVD
VSS
VSS
RSVD
RSVD
Rev1p2
Rev1p2
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
PROC_OPI_RCOMP
AV62
D58
P22
N21
P20
R20
PROC_OPI_RCOMP
PAD~D T30
PAD~D
1 2
T20@PAD~D T20@PAD~D
T21@PAD~D T21@PAD~D
T22@PAD~D T22@PAD~D
T23@PAD~D T23@PAD~D
T24@PAD~D T24@PAD~D
T25@PAD~D T25@PAD~D
T26@PAD~D T26@PAD~D
T27@PAD~D T27@PAD~D
T28@PAD~D T28@PAD~D
T29@PAD~D T29@PAD~D
@
@
T30
T31 @PAD~D T31 @PAD~D
T32 @PAD~D T32 @PAD~D
T34 @PAD~D T34 @PAD~D
T36 @PAD~D T36 @PAD~D
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
CFG0
1:(Default) Normal Operation; No stall
0:Lane Reversed
PCH/PCH LESS MODE SELECTION
CFG1
RC23749.9_0402_1% RC23749.9_0402_1%
1:(Default) Normal Operation
0:Lane Reversed
B B
SAFE MODE BOOT
CFG10
A A
CFG10 CFG4
1K_0402_1%
1K_0402_1%
12
RC239@
RC239@
NO SVID PROTOCOL CAPABLE VR CONNECTED
1: POWER FEATURES ACTIVATED DURING
RESET
0: POWER FEATURES (ESPECIALLY CLOCK
CFG9
GATINE ARE NOT ACTIVATED
CFG9
12
1K_0402_1%
1K_0402_1%
RC240@
RC240@
1: VRS support SVID protocol are present
0:No VR support SVID is present
The chip will not generate(OR Respond to)
SVID activity
ALLOW THE USE OF NOA ON LOCKED UNITS
CFG8
CFG8
1K_0402_1%
1K_0402_1%
12
RC241@
RC241@
1: Enable(Default): Noa will be disable in
locked units and enable in un-locked
units
0: Enable Noa will be available pegardless of
the locking of the unit
CFG4
1K_0402_1%
1K_0402_1%
12
RC238
RC238
Display Port Presence Strap
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (8/12)
CPU (8/12)
CPU (8/12)
LA-9591P
LA-9591P
LA-9591P
13 58Friday, May 17, 2013
13 58Friday, May 17, 2013
13 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
D D
C C
4
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
UC1Q
UC1Q
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
1
HASWELL_MCP_E
HASWELL_MCP_E
17 OF 19
17 OF 19
3
3
12
RC254 @0_0402_5% RC254 @0_0402_5%
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
Rev1p2
Rev1p2
12
RC269 @0_0402_5% RC269 @0_0402_5%
A3
DC_TEST_A3_B3
A4
DC_TEST_A4
A60
DC_TEST_A60
A61
DC_TEST_A61_B61
A62
DC_TEST_A62
AV1
DC_TEST_AV1
AW1
DC_TEST_AW1
AW2
DC_TEST_AY2_AW2
AW3
DC_TEST_AY3_AW3
AW61
DC_TEST_AY61_AW61
AW62
DC_TEST_AY62_AW62
AW63
DC_TEST_AW63
2
2
12
RC266@0_0402_5% RC266@0_0402_5%
12
RC268@0_0402_5% RC268@0_0402_5%
4
1
Package Daisy Chain:
1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
HASWELL_MCP_E
UC1R
UC1R
T50@ PAD~DT50@ PAD~D
T52@ PAD~DT52@ PAD~D
B B
A A
T54@ PAD~DT54@ PAD~D
T55@ PAD~DT55@ PAD~D
T58@ PAD~DT58@ PAD~D
T60@ PAD~DT60@ PAD~D
T62@ PAD~DT62@ PAD~D
RSVD_AT2
RSVD_AU44
RSVD_AV44
RSVD_D15
RSVD_F22
RSVD_H22
RSVD_J21
AU44
AV44
AT2
RSVD
RSVD
RSVD
D15
RSVD
F22
RSVD
H22
RSVD
J21
RSVD
HASWELL_MCP_E
18 OF 19
18 OF 19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Rev1p2
Rev1p2
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
RSVD_N23
RSVD_R23
RSVD_T23
RSVD_U10
RSVD_AL1
RSVD_AM11
RSVD_AP7
RSVD_AU10
RSVD_AU15
RSVD_AW14
RSVD_AY14
PAD~D T48
PAD~D
PAD~D T49
PAD~D
PAD~D T51
PAD~D
PAD~D T53
PAD~D
PAD~D T56
PAD~D
PAD~D T57
PAD~D
PAD~D T59
PAD~D
PAD~D T61
PAD~D
PAD~D T63
PAD~D
PAD~D T64
PAD~D
PAD~D T65
PAD~D
@
@
T48
@
@
T49
@
@
T51
@
@
T53
@
@
T56
@
@
T57
@
@
T59
@
@
T61
@
@
T63
@
@
T64
@
@
T65
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (9/12)
CPU (9/12)
CPU (9/12)
LA-9591P
LA-9591P
LA-9591P
14 58Friday, May 17, 2013
14 58Friday, May 17, 2013
14 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
+VCC_CORE +1.35V_MEM
+1.05V_RUN
150_0402_1%
150_0402_1%
12
RC253
D D
C C
RESET_OUT#<37,9>
SVID ALERT
B B
SVID DATA
VIDSOUT<46>
VCC_SENSE
A A
CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU
RC253
CPU_PWR_DEBUG#
10K_0402_5%
10K_0402_5%
12
@
@
RC258
RC258
H_VR_EN H_VR_R EADY
RC263@ 0_0402_5%RC263@ 0_0402_5%
VIDALERT_N<46>
VCCSENSE<46>
12
12
+1.05V_VCCST
75_0402_1%
75_0402_1%
12
+1.05V_VCCST
110_0402_1%
110_0402_1%
12
+1.05V_VCCST +3.3V_RUN
RC25610K_0402_5% RC 25610K_0402_5%
UC4
UC4
1
NC
2
A
3
GND
74AUP1G07GW_TSSOP5
74AUP1G07GW_TSSOP5
RC244
RC244
RC249
RC249
VIDSOUT
+VCC_CORE
100_0402_1%
100_0402_1%
12
RC250
RC250
ESD test request
CC57
EMC@
CC57
EMC@
1 2
22U_0603_6.3V6M
22U_0603_6.3V6M
1 2
VCCST_PWRGD
CC22
@
CC22
@
100P_0402_50V8J
100P_0402_50V8J
10K_0402_5%
+3.3V_ALW
5
4
Y
H_CPU_SVIDALRT#
RC24843_0402_5% RC24843_0402_5%
10K_0402_5%
12
RC259@
RC259@
1 2
CC24@ 0.1U_0402_25V6CC24@ 0.1U_0402_25V6
H_VCCST_PWRGD
10K_0402_5%
10K_0402_5%
12
RC255@
RC255@
VCC
CAD Note: Place the PU resistors close to CPU
RC224 close to CPU 300 Â1500mils
12
CAD Note: Place the PU resistors close to CPU
RC249close to CPU 300 - 1500mils
VCCSENSE
+1.05V_RUN +VCCIO_OUT
RC242 0_0603_5%
@
RC242 0_0603_5%
@
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
+1.05V_VCCST
1K_0402_5%
1K_0402_5%
RC243
RC243
1 2
+1.05V_RUN +1.05V_VCCST
12
H_VCCST_PWRGD<9>
H_VR_EN<46 >
H_VR_READY<46>
PJP11
@PJP11
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
+1.35V_MEM
VIDSCLK<46>
1 2
RC245@ 0_0402_5%RC245@ 0_0402_5%
1 2
RC246@ 0_0402_5%RC246@ 0_0402_5%
1 2
RC247@ 0_0402_5%RC247@ 0_0402_5%
check
CPU_PWR_DEBUG#<9>
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
CC50
CC50
12
12
@
@
CC26
CC26
+1.35V_MEM
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
12
T66@ PA D~DT66@ PAD~D
T67@ PA D~DT67@ PAD~D
+VCC_CORE
T68@
T68@
PAD~D
PAD~D
T69@
T69@
PAD~D
PAD~D
T70@
T70@
PAD~D
PAD~D
+VCCIO_OUT
+VCCIOA_OUT
T71@
T71@
PAD~D
PAD~D
T72@
T72@
PAD~D
PAD~D
T73@
T73@
PAD~D
PAD~D
T74@
T74@
PAD~D
PAD~D
T75@
T75@
PAD~D
PAD~D
T76@
T76@
PAD~D
PAD~D
T77@
T77@
PAD~D
PAD~D
T78@
T78@
PAD~D
PAD~D
T79@
T79@
PAD~D
PAD~D
T80@
T80@
PAD~D
PAD~D
T81@
T81@
PAD~D
PAD~D
T82@
T82@
PAD~D
PAD~D
T83@
T83@
PAD~D
PAD~D
T84@
T84@
PAD~D
PAD~D
T85@
T85@
PAD~D
PAD~D
T86@
T86@
PAD~D
PAD~D
+1.05V_VCCST
+VCC_CORE
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
@
@
@
@
12
CC81
CC81
CC52
CC52
VCCSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
12
CC12
CC12
L59
J58
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
F59
N58
AC58
E63
AB23
A59
E20
AD23
AA23
AE59
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
AC22
AE22
AE23
AB57
AD57
AG57
C24
C28
C32
VDDQ DECOUPLING
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
12
12
UC1L
UC1L
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
CC16
CC16
CC13
CC13
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
12
CC17
CC17
HASWELL_MCP_E
HASWELL_MCP_E
HSW ULT POWER
HSW ULT POWER
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12 OF 19
12 OF 19
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12
CC18
CC18
CC19
CC19
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
12
12
CC21
CC21
CC20
CC20
+VCC_CORE
C36
VCC
C40
VCC
C44
VCC
C48
VCC
C52
VCC
C56
VCC
E23
VCC
E25
VCC
E27
VCC
E29
VCC
E31
VCC
E33
VCC
E35
VCC
E37
VCC
E39
VCC
E41
VCC
E43
VCC
E45
VCC
E47
VCC
E49
VCC
E51
VCC
E53
VCC
E55
VCC
E57
VCC
F24
VCC
F28
VCC
F32
VCC
F36
VCC
F40
VCC
F44
VCC
F48
VCC
F52
VCC
F56
VCC
G23
VCC
G25
VCC
G27
VCC
G29
VCC
G31
VCC
G33
VCC
G35
VCC
G37
VCC
G39
VCC
G41
VCC
G43
VCC
G45
VCC
G47
VCC
G49
VCC
G51
VCC
G53
VCC
G55
VCC
G57
VCC
H23
VCC
J23
VCC
K23
VCC
K57
VCC
L22
VCC
M23
VCC
M57
VCC
P57
VCC
U57
VCC
W57
VCC
Rev1p2
Rev1p2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (10/12)
CPU (10/12)
CPU (10/12)
LA-9591P
LA-9591P
LA-9591P
15 58Friday, May 17, 2013
15 58Friday, May 17, 2013
15 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
+1.05V_MODPHY +1.05V_MODPHY_PCH
1 2
RC262@ 0_0805_5%RC262@ 0_0805_5%
CC29 place near K9;
CC27 place near L10
D D
CC74 place near M9
+1.05V_MODPHY
LC1
LC1
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
1U_0402_6.3V6K
1U_0402_6.3V6K
12
22U_0603_6.3V6M
22U_0603_6.3V6M
12
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
12
CC27
CC27
CC74
CC74
+PCH_AUSB3PLL
22U_0603_6.3V6M
22U_0603_6.3V6M
12
CC76
CC76
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC29
CC29
CC42
CC42
CC42 place near B18
LC2
LC2
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
CC49 place near B11
C C
LC5
LC5
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
+PCH_ASATA3PLL+1.05V_MODPHY
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
CC77
CC77
CC49
12
12
CC49
12
+V1.05S_APLLOPI+1.05V_RUN
100U_1206_6.3V6M
100U_1206_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC55
CC55
CC56
CC56
+3.3V_ALW_PCH
12
0.1U_0402_10V7K
0.1U_0402_10V7K
+3.3V_ALW_PCH
CC44
CC44
12
CC56 place near AA21
+1.05V_M
1 2
RC276@ 0_0603_5%RC276@ 0_0603_5%
CC66 place near AH13
CC61 CC62 place near J13
B B
1 2
RC265 0_0402_5%@ RC265 0_0402_5%@
+3.3V_ALW
1 2
RC267@ 0_0402_5%RC267@ 0_0402_5%
CC32 place near AH10
+PCH_DCPSUS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
@
12
12
CC66@
CC66@
@
12
CC61@
CC61@
CC62
CC62
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
CC51 place near J18
+PCH_VCCDSW3_3+3.3V_ALW_PCH
+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
12
CC32
CC32
4
+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
12
CC31
CC31
CC44 place near AH14
CC28 place near AC9
22U_0603_6.3V6M
22U_0603_6.3V6M
+3.3V_RUN
CC28
CC28
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
22U_0603_6.3V6M
22U_0603_6.3V6M
12
CC43
CC43
+1.05V_RUN
LC3
LC3
LC6
LC6
1 2
CC43 place near V8
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC58 place near A20
+1.05V_MODPHY_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC64
CC64
CC63
CC63
100U_1206_6.3V6M
100U_1206_6.3V6M
12
12
+PCH_AUSB3PLL
+PCH_ASATA3PLL
+V1.05S_APLLOPI
+PCH_DCPSUS
+PCH_VCCDSW3_3
+PCH_VCC1P05
+PCH_VCCACLKPLL
CC63 close to Pin J17
CC64 close to Pin R21
+3.3V_ALW_PCH
+PCH_VCC1P05+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC79
CC79
CC51
CC51
+PCH_VCCACLKPLL
1U_0402_6.3V6K
1U_0402_6.3V6K
100U_1206_6.3V6M
100U_1206_6.3V6M
CC58
CC58
CC78
CC78
12
AA21
W21
AH14
AH13
AH10
AE20
AE21
B18
B11
AC9
AA9
K19
A20
R21
T21
K18
M20
V21
K9
L10
M9
N8
P9
Y20
J13
V8
W9
J18
J17
UC1M
UC1M
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
@
@
12
CC73
CC73
+
+
HASWELL_MCP_E
HASWELL_MCP_E
mPHY
mPHY
OPI
OPI
USB3
USB3
AXALIA/HDA
AXALIA/HDA
VRM/USB2/AZALIA
VRM/USB2/AZALIA
GPIO/LCC
GPIO/LCC
LPT LP POWER
LPT LP POWER
3
1 2
CC83 22U_0603_6.3V6MEMC@CC83 22U_0603_6.3V6MEMC@
1 2
CC84 22U_0603_6.3V6MEMC@CC84 22U_0603_6.3V6MEMC@
1 2
CC85 22U_0603_6.3V6MEMC@CC85 22U_0603_6.3V6MEMC@
AH11
AG10
AE7
+DCPRRTC
CC36 0.1U_0402_10V7KCC36 0.1U_0402_10V7K
Y8
AG14
AG13
J11
H11
H15
AE8
AF22
AG19
+PCH_VCCDSW
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16
U8
T9
AB8
AC20
AG16
CC60 place near AG16
AG17
ESD test request
+PCH_RTC_VCCSUS3_3
1 2
+1.05V_M
CC34 and CC33 place near
J11; CC37 place near AE8
CC46 CC47 place near AE9
+PCH_DCPSUS1
+1.5V_THERMAL
CC45 place near U8
+PCH_DCPSUS4
+1.05V_RUN
+1.05V_RUN+1.05V_M
13 OF 19
13 OF 19
@
@
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
12
+
+
CC71
CC71
THERMAL SENSOR
THERMAL SENSOR
@
@
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
12
+
+
CC72
CC72
RTC
RTC
SPI
SPI
CORE
CORE
SDIO/PLSS
SDIO/PLSS
SUS OSCILLATOR
SUS OSCILLATOR
USB2
USB2
+1.05V_RUN +VCC_CORE
+1.05V_RUN +3.3V_RUN
VCCSUS3_3
VCCRTC
DCPRTC
VCCSPI
VCCASW
VCCASW
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
VCC1_05
VCC1_05
Rev1p2
Rev1p2
2
CC35,CC38, CC39 place near AG10
CC40 place near Y8
+1.05V_M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CC46
CC46
@
@
CC47
CC47
12
1U_0402_6.3V6K
1U_0402_6.3V6K
CC45
CC45
CC59 place near K14
+3.3V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
CC60
CC60
12
+RTC_CELL
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
@
@
CC39
CC39
CC35
+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
CC33
CC33
CC35
+3.3V_M
0.1U_0402_10V7K
0.1U_0402_10V7K
@
@
12
CC40
CC40
10U_0603_6.3V6M
10U_0603_6.3V6M
12
CC34
CC34
+PCH_VCCDSW
CC38
CC38
12
CC37
CC37
CC65 place near AG19
+3.3V_RUN
0.1U_0402_10V7K
0.1U_0402_10V7K
12
CC59
CC59
+PCH_RTC_VCCSUS3_3 +3.3V_ALW_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC30
CC30
12
+PCH_DCPSUS4 +1.05V_M
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CC53@
CC53@
1
RC275 5.11_0402_1%RC275 5.11_0402_1%
12
12
RC261 @0_0402_5% RC261@0_0402_5%
12
RC264@0_0402_5% RC264 @0_0402_5%
CC30 place near AH11
1U_0402_6.3V6K
1U_0402_6.3V6K
CC54@
CC54@
CC54 place near AD10
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
100U_1206_6.3V6M
100U_1206_6.3V6M
12
12
LC4@
LC4@
CC75@
CC75@
+PCH_VCCDSW_R
12
+3.3V_ALW
RC272 @0_0402_5% RC272 @0_0402_5%
12
1U_0402_6.3V6K
1U_0402_6.3V6K
CC65
CC65
+1.05V_M+PCH_DCPSUS1
CC53 place near AB8
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (11/12)
CPU (11/12)
CPU (11/12)
LA-9591P
LA-9591P
LA-9591P
1
16 58Friday, May 17, 2013
16 58Friday, May 17, 2013
16 58Friday, May 17, 2013
0.4
0.4
0.4
5
D D
HASWELL_MCP_E
HASWELL_MCP_E
UC1N
UC1N
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
AB22
VSS
AB7
VSS
AC61
VSS
AD21
VSS
AD3
VSS
AD63
VSS
AE10
VSS
AE5
VSS
AE58
C C
B B
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14 OF 19
14 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Rev1p2
Rev1p2
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
4
HASWELL_MCP_E
HASWELL_MCP_E
UC1O
UC1O
AP22
VSS
AP23
VSS
AP26
VSS
AP29
VSS
AP3
VSS
AP31
VSS
AP38
VSS
AP39
VSS
AP48
VSS
AP52
VSS
AP54
VSS
AP57
VSS
AR11
VSS
AR15
VSS
AR17
VSS
AR23
VSS
AR31
VSS
AR33
VSS
AR39
VSS
AR43
VSS
AR49
VSS
AR5
VSS
AR52
VSS
AT13
VSS
AT35
VSS
AT37
VSS
AT40
VSS
AT42
VSS
AT43
VSS
AT46
VSS
AT49
VSS
AT61
VSS
AT62
VSS
AT63
VSS
AU1
VSS
AU16
VSS
AU18
VSS
AU20
VSS
AU22
VSS
AU24
VSS
AU26
VSS
AU28
VSS
AU30
VSS
AU33
VSS
AU51
VSS
AU53
VSS
AU55
VSS
AU57
VSS
AU59
VSS
AV14
VSS
AV16
VSS
AV20
VSS
AV24
VSS
AV28
VSS
AV33
VSS
AV34
VSS
AV36
VSS
AV39
VSS
AV41
VSS
AV43
VSS
AV46
VSS
AV49
VSS
AV51
VSS
AV55
VSS
15 OF 19
15 OF 19
Rev1p2
Rev1p2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
UC1P
UC1P
2
HASWELL_MCP_E
HASWELL_MCP_E
16 OF 19
16 OF 19
VSS_SENSE
Rev1p2
Rev1p2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
VSSSENSE
RC260 100_0402_1%R C260 100_0402_1%
1
VSSSENSE <46>
1 2
CAD Note: RC260 SHOULD BE PLACED CLOSE TO CPU
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CPU (12/12)
CPU (12/12)
CPU (12/12)
LA-9591P
LA-9591P
LA-9591P
17 58Friday, May 17, 2013
17 58Friday, May 17, 2013
17 58Friday, May 17, 2013
1
0.4
0.4
0.4
5
4
3
2
1
DDR_A_DQS#[0..7]<8>
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
D D
Layout Note:
Place near JDIMM1
+1.35V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CD4
CD4
CD5
CD5
10U_0603_6.3V6M
10U_0603_6.3V6M
CD14
CD14
CD15@
CD15@
12
Layout Note:
Place near
JDIMM1.203,204
0.1U_0402_25V6
0.1U_0402_25V6
12
12
CD26
CD26
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD6
CD6
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD16
CD16
12
12
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
CD27
CD27
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
12
CD7
CD7
10U_0603_6.3V6M
10U_0603_6.3V6M
CD17
CD17
12
12
CD28
CD28
1U_0402_6.3V6K
1U_0402_6.3V6K
12
12
CD9
CD9
CD8
CD8
@
@
CD18
CD18
0.1U_0402_25V6
0.1U_0402_25V6
CD10
CD10
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD20
CD20
CD19
CD19
12
12
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
CD30
CD30
CD29
CD29
1U_0402_6.3V6K
1U_0402_6.3V6K
12
C C
B B
A A
+1.35V_MEM
10U_0603_6.3V6M
10U_0603_6.3V6M
12
+0.675V_DDR_VTT
12
12
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
CD11
CD11
10U_0603_6.3V6M
10U_0603_6.3V6M
12
CD21
CD21
+
+
CD31
CD31
+SM_VREF_DQ0_DIMM1
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
CD22
CD22
1 2
RD5@ 0_0402_5%RD5@ 0_0402_5%
1 2
RD6@ 0_0402_5%RD6@ 0_0402_5%
1 2
RD1@ 0_0402_5%RD1@ 0_0402_5%
+DIMM1_VREF_DQ
+3.3V_RUN
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
12
CD1
CD1
DDR_CKE0_DIMMA<8>
DDR_A_BS2<8>
M_CLK_DDR0<8>
DDR_A_BS0<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
DDR_CS1_DIMMA#<8>
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
@
@
12
CD25
CD25
DDR_A_D8
12
CD2
CD2
DDR_A_D14 DDR_A_D15
DDR_A_D10 DDR_A_D11
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_D44 DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA9
DDR_A_MA8
M_CLK_DDR0 M_CLK_DDR1
M_CLK_DDR#0 M_CLK_DDR#1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
DDR_A_D36 DDR_A_D37
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
+0.675V_DDR_VTT
0.1U_0402_25V6
0.1U_0402_25V6
12
CD24
CD24
H=4mm
Reverse Type
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
VSS925VSS10
DQS#127DM1
DQS129RESET#
VSS1131VSS12
DQ1033DQ14
DQ1135DQ15
VSS1337VSS14
DQ1639DQ20
DQ1741DQ21
VSS1543VSS16
DQS#245DM2
DQS247VSS17
VSS1849DQ22
DQ1851DQ23
DQ1953VSS19
VSS2055DQ28
DQ2457DQ29
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
DQ2667DQ30
DQ2769DQ31
VSS2571VSS26
CKE073CKE1
VDD175VDD2
77
NC1
79
BA2
VDD381VDD4
A12/BC#83A11
85
A9
VDD587VDD6
89
A8
91
A5
VDD793VDD8
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A621-U4R6-7H
FOX_AS0A621-U4R6-7H
CONN@
CONN@
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQS3
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
+1.35V_MEM+1.35V_MEM
2
4
DQ4
DQ5
DQ6
DQ7
A15
A14
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
DDR_A_D9
6
DDR_A_D12DDR_A_D13
8
10
DDR_A_DQS#1
12
DDR_A_DQS1
14
16
18
20
22
DDR_A_D25
24
DDR_A_D24
26
28
30
DDR3_DRAMRST#
32
34
DDR_A_D27
36
DDR_A_D26
38
40
42
DDR_A_D40DDR_A_D41
44
46
48
50
DDR_A_D42
52
DDR_A_D46
54
56
DDR_A_D52
58
DDR_A_D53
60
62
DDR_A_DQS#6
64
DDR_A_DQS6
66
68
DDR_A_D54
70
DDR_A_D55
72
74
76
78
DDR_A_MA15
80
DDR_A_MA14
82
84
DDR_A_MA11DDR_A_MA12
86
DDR_A_MA7
88
90
DDR_A_MA6
92
DDR_A_MA4DDR_A_MA5
94
96
DDR_A_MA2DDR_A_MA3
98
DDR_A_MA0DDR_A_MA1
100
102
104
106
108
DDR_A_BS1
110
DDR_A_RAS#
112
114
DDR_CS0_DIMMA#
116
M_ODT0
118
120
M_ODT1
122
124
126
128
130
DDR_A_D5
132
DDR_A_D4
134
136
138
140
DDR_A_D3
142
DDR_A_D7
144
146
DDR_A_D18
148
DDR_A_D19
150
152
DDR_A_DQS#2
154
DDR_A_DQS2
156
158
DDR_A_D22
160
DDR_A_D23
162
164
166
DDR_A_D32DDR_A_D33
168
170
172
174
DDR_A_D35
176
DDR_A_D39
178
180
DDR_A_D63
182
DDR_A_D59
184
186
DDR_A_DQS#7
188
DDR_A_DQS7
190
192
DDR_A_D56
194
DDR_A_D57
196
198
200
202
204
+0.675V_DDR_VTT
206
0.1U_0402_25V6
0.1U_0402_25V6
CD3@
CD3@
12
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_CKE1_DIMMA <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <8>
+SM_VREF_CA_DIMM1
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
CD12
CD12
CD13
CD13
12
12
DDR_XDP_WAN_SMBDAT <19,25,31,7,9>
DDR_XDP_WAN_SMBCLK <19,25,31,7,9>
1 2
+SM_VREF_CA_DIMM
RD12@0_0402_5% RD12@0_0402_5%
+5V_ALW
DDR_PG_CTRL<9>
1 2
RC279@ 0_0402_5%RC279@ 0_0402_5%
+1.35V_MEM
1.8K_0402_1%
1.8K_0402_1%
12
+SM_VREF_DQ0_DIMM1
1.8K_0402_1%
1.8K_0402_1%
12
DDR3L SODIMM ODT GENERATION
+1.35V_MEM
220K_0402_5%
220K_0402_5%
12
R28
R28
0.675V_DDR_VTT_ON
2M_0402_5%
2M_0402_5%
R32@
R32@
1 2
QD1
QD1
BSS138-G_SOT23-3
BSS138-G_SOT23-3
123
D
S
D
S
G
G
1
NC
2
A
3
GND
74AUP1G07GW_TSSOP5
74AUP1G07GW_TSSOP5
+1.35V_MEM
RC217
RC217
1 2
RC173 2_0402_1%RC173 2_0402_1%
RC221
RC221
1 2
R29 66.5_0402_1%R29 66.5_0402_1%
1 2
R30 66.5_0402_1%R30 66.5_0402_1%
1 2
R31 66.5_0402_1%R31 66.5_0402_1%
1 2
R33 66.5_0402_1%R33 66.5_0402_1%
+1.35V_MEM
U5
U5
5
VCC
4
Y
470_0402_5%
470_0402_5%
12
RD3
RD3
DDR3_DRAMRST#_CPU <9>DDR3_DRAMRST#<19>
0.022U_0402_16V7K
0.022U_0402_16V7K
CC70
CC70
12
24.9_0402_1%
24.9_0402_1%
12
RC195
RC195
M_ODT0
M_ODT1
1 2
CD23@ 0.1U_0402_25V6CD23@ 0.1U_0402_25V6
0.675V_DDR_VTT_ON
+SM_VREF_DQ0
M_ODT2 <19>
M_ODT3 <19>
0.675V_DDR_VTT_ON <43>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDR3L
DDR3L
DDR3L
LA-9591P
LA-9591P
LA-9591P
1
18 58Friday, May 17, 2013
18 58Friday, May 17, 2013
18 58Friday, May 17, 2013
0.4
0.4
0.4
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