Compal LA-9531P V5WE2, Aspire E1-532G, Aspire E1-572G, LA-9531P V5WC2, LA-9531P V5WT2 Schematic

A

B

C

D

E

Compal Confidential

Model Name : V5WE2/T2/C2 (EA/EG/BA50_HW)

1 1

File Name : LA-9531P

Compal Confidential

2 2

EA50_HW M/B Schematics Document

Intel Shark Bay ULT (Hasswell + Lynx Point-LP)

AMD MARS / SUN

3 3

2013-04-11

REV:1.0

4 4

ZZZ

Part Number

DAZ0VR00100 PCB V5WE2 LA-9531P LS-9531P/9532P

V5WE2_PCB

Description

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/07/10 2013/07/10

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

152Thursday, April 11, 2013

152Thursday, April 11, 2013

152Thursday, April 11, 2013

E

1.0

1.0

1.0

A

B

C

D

E

CRT Conn.

page 28

DP to VGA

1 1

ITE IT6511FN

page 27

DP x 2 lanes HDMI x 4 lanes

2.7GT/s

MINI Card

WLAN

USB port 4

2 2

page 31

PCIe 2.0
5GT/s

port 4

PCIe 2.0
5GT/s

port 3

LAN(GbE)

Boardcom
57786X

page 29

HDMI Conn. eDP Conn.

page 26

2.97GT/s

AMD SUN/MARS
with DDR3 x4 or 8

page 17~23

PCIe 2.0 x4
5GT/s

port 5

SATA3.0 SATA3.0

port 0

SATA HDD
Conn.

page 32

SATA CDROM
Conn.

page 25

Flexible IO

6.0 Gb/s6.0 Gb/s

port 2

page 32

eDP

DDI

Intel Haswell ULT

Haswell ULT

Processor

OPI

Lynx Point - LP

PCH

1168pin BGA

page 04~14

Memory BUS

Dual Channel

1.35V DDR3L 1333/1600

USBx8

HD Audio

SPI

48MHz

204pin DDR3L-SO-DIMM X1

BANK 0, 1, 2, 3

204pin DDR3L-SO-DIMM X1

BANK 4, 5, 6, 7

USB 3.0
conn x1

USB port 0

page 33 page 25

3.3V 24MHz

USB 2.0
conn x2

page 33

HDA Codec

ALC3225

(port 1,2)USB/B

Fan Control

page 15

CMOS
Camera

USB port 7

page 36

page 36

page 16

Finger
Print

USB

Touch
Screen

USB

(port 5)

page 26

(port 6)

page 25

3 3

4 4

Card Reader

2 in 1
(SD)

page 30

RTC CKT.

page 6

Power On/Off CKT.

page 35

DC/DC Interface CKT.

page 38

Power Circuit DC/DC

page 39~49

A

Sub Board

LS-9531P

PWR/B

page 33

LS-9532P

USB/B

page 33

(port 1,2)

LPC BUS

CLK=24MHz

ENE
KB9012

page 34

SPI ROM x2

page 7

Int. Speaker Combo JackInt. MIC

page 36

page 36 page 36

Touch Pad Int.KBD

page 35

page 35

EC ROM x1
(reserved)

page 34

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

2012/07/10 2013/07/10

2012/07/10 2013/07/10

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

252Tuesday, March 26, 2013

252Tuesday, March 26, 2013

252Tuesday, March 26, 2013

E

1.0

1.0

1.0

A

Voltage Rails

Power Plane Description
VIN
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+

1 1

+CPU_CORE
+VGA_CORE Core voltage for GPU
+0.675VS +0.675VS power rail for DDR3L terminator
+1.05VS_VTT +1.05V power rail for CPU
+0.95VSDGPU +0.95VSDGPU switched power rail for GPU

+1.5VS
+1.5VSDGPU +1.5VSDGPU power rail for GPU ON OFF OFF
+1.8VSDGPU +1.8VSDGPU power rail for GPU ON OFF OFF
+3VALW +3VALW always on power rail
+3VLP B+ to +3VLP power rail for suspend power ON ON
+3VS

+5VALW
+5VS +3VALW to +5VS power rail OFFON OFF
+RTCVCC RTC power

2 2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Adapter power supply (19V)

AC or battery power rail for power circuit.
Core voltage for CPU

+1.35V power rail for DDR3L ON ON OFF+1.35V
+1.5V power rail for CPU

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

EC SM Bus2 address

Address Address

0001 011X

Device

On Board Thermal Senser
VGA Internal Thermal Senser
G Senser

PCH SM Bus address

Device Address

ChannelA DIMM0

3 3

DIMM1ChannelB JDIMM2

1001 000x
1001 010x

JDIMM1

B

S1 S3 S5
N/A N/A N/A

ON
ON OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF

ON OFF OFF

ON

ON ON*

OFF

ON

ON

ON ON*

0100 110x
0100 000x
0011 000x

N/AN/AN/A
OFFOFF
OFF

ON
OFF
OFFOFFON+3VS to +3VSDGPU power rail for GPU+3VSDGPU

ONONON

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

LOW

LOW

LOW LOW LOW LOW

D

HIGH

LOWLOWLOW

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7NC

100K +/- 5%Ra/Rc/Re

Rb / Rd / Rf V min

0

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0 V

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

0.4

0.5

1.0

USB Port Table

USB 2.0 Port

0
1
2

EHCI1

3
4
5
6
7

3 External
USB Port

USB Port(Left 3.0)
USB Port(Right 2.0)
USB Port(Right 2.0)

Mini Card (WLAN+BT)

Camera

ON

ON

HIGHHIGHHIGH

HIGH

HIGH

V typ

AD_BID

ON

ON

ON

ON

OFF

ON

ON

OFF

V

0 V 0 V

0.503 V

0.819 V

1.185 V 1.264 V

2.200 V

3.300 V

BTO Item BOM Structure

Unpop @

EC 9012 9012@
UMA Component
AMD GPU
1 SPI ROM 1ROM@

Assembly Level 45@
Cable for Power 45PWR@

Debug Only DEG@

Reservec for EMC XEMC@
eDP to LVDS TL@
TPM Module TPM@
G-Sensor GSEN@
V5WE2/T2/C2 EA50@
Reserved BA51@
Touch Screen TS@
For IOAC

E

ON ON

LOW

ON

OFF

OFF

OFF

OFF

OFF

OFF

max

AD_BID

0.538 V

0.875 V

2.341 V

3.300 V

BTO Option Table

CONN@Connector
940@EC 932

UMA@
VGA@

2ROM@2 SPI ROM

BL@KB Backlight

EMC@EMC Component

IOAC@

For EDP panel EDP@

Mars component
SUN component

MARS@
SUN@

128@VRAM x 8pcs

PortUSB 3.0

0

USB Port(Left 3.0)

4 4

XHCI

1
2

Micron 4G x 8
Hynix 2G x 4
Hynix 2G x 8

X76@VRAM Selection
X7601@
X7603@
X7604@

3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/07/10 2013/07/10

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

352Thursday, April 11, 2013

352Thursday, April 11, 2013

352Thursday, April 11, 2013

E

1.0

1.0

1.0

5

4

3

U1A

HASWELL_MCP_E

2

1

CPU_DP1_N027
CPU_DP1_P027
CPU_DP1_N127

DP to CRT

D D

HDMI

CPU_DP1_P127

CPU_DP2_N026
CPU_DP2_P026
CPU_DP2_N126
CPU_DP2_P126
CPU_DP2_N226
CPU_DP2_P226
CPU_DP2_N326
CPU_DP2_P326

Reserved for ESD

1 2

C94 6.8P_0402_50V8C
XEMC@

+1.35V

C C

12

R184
470_0603_5%

2

C96

6.8P_0402_50V8C

1

XEMC@

Reserved for ESD

DIMM_DRAMRST# 15,16

Close to AV15

Reserved for ESD 1120

+1.05VS_VTT

H_PROCHOT#34,39,40

H_PECI34

Reserved for ESD

12

R68

62_0402_5%

1 2

C95 6.8P_0402_50V8C
XEMC@

1 2

R6 10K_0402_5%

1 2

C60 6.8P_0402_50V8C
XEMC@

1 2

R11 200_0402_1%

1 2

R13 120_0402_1%

1 2

R41 100_0402_1%

DDR_PG_CTRL15

DDR3 Compensation Signals

R8
56_0402_5%

1 2

T20 @
T2 @

H_PROCHOT#_R

H_CPUPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DIMM_DRAMRST#
DDR_PG_CTRL

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

HASWELL-MCP-E-ULT_BGA1168
@

U1B

D61

PROC_DETECT

K61

CATERR

N62

PECI

K63

PROCHOT

C61

PROCPWRGD

AU60

SM_RCOMP0

AV60

SM_RCOMP1

AU61

SM_RCOMP2

AV15

SM_DRAMRST

AV61

SM_PG_CNTL1

HASWELL-MCP-E-ULT_BGA1168
@

DDI EDP

1 OF 19

HASWELL_MCP_E

MISC

JTAG

THERMAL

PWR

DDR3

2 OF 19

EDP_AUXN

EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

Rev1p2

PRDY

PREQ
PROC_TCK
PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

Rev1p2

C45
B46
A47
B47

C47
C46
A49
B49

A45
B45

D20
A43

EDP_TXN0 25
EDP_TXP0 25
EDP_TXN1 25
EDP_TXP1 25

EDP_AUXN 25
EDP_AUXP 25

1 2

R1 24.9_0402_1%

Tracewidth=20mils,Spacing=25mil,Maxlength=100mils

EDP_DISP_UTIL 25

XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI_R
XDP_TDO_R

XDP_BPM#0_R
XDP_BPM#1_R

T148@
T149@
T150@
T151@
T152@
T153@

T157@
T158@
T159@
T160@
T161@
T162@
T163@

T164@
T165@

J62
K62
E60
E61
E59
F63
F62

J60
H60
H61
H62
K59
H63
K60
J61

EDP_COMP

+VCCIOA_OUT

B B

5

U1

CPU_SR170_C1
SR170@

SA00006SMB0

U1

CPU_QEK4_C0
QEK4@

SA00006NM50

U1

CPU_QEVG_C0
QEVG@

SA00006SX30

U1

CPU_QEVE_C0
QEVE@

SA00006SM30

Security Classification

Security Classification

Security Classification

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(1/11) DDI,MSIC,XDP

HSW MCP(1/11) DDI,MSIC,XDP

HSW MCP(1/11) DDI,MSIC,XDP

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

452Monday, April 08, 2013

452Monday, April 08, 2013

452Monday, April 08, 2013

1

1.0

1.0

1.0

U1

CPU_SR16Q_C1
SR16Q@

A A

SA00006SX70

U1

CPU_QEK2_C0
QEK2@

SA00006SJ40

5

U1C

AH63

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

D D

C C

B B

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57

AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54

AL55
AK55
AR54
AN54
AY58

AW58

AY56

AW56

AV58
AU58
AV56
AU56
AY54

AW54

AY52

AW52

AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

HASWELL_MCP_E

DDR CHANNEL A

4

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1
SA_CKE0

SA_CKE1
SA_CKE2
SA_CKE3

SA_CS#0
SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS
SA_BA0

SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

AU43
AW43
AY42
AY43

AP33
AR32

AP32
AY34

AW34
AU34

AU35
AV35
AY41

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

AP49
AR51
AP51

DDRA_ODT0

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_CLK_DDR#0 15
SA_CLK_DDR0 15
SA_CLK_DDR#1 15
SA_CLK_DDR1 15

DDRA_CKE0_DIMMA 15
DDRA_CKE1_DIMMA 15

DDRA_CS0_DIMMA# 15
DDRA_CS1_DIMMA# 15

T4@

DDR_A_RAS# 15

DDR_A_WE# 15

DDR_A_CAS# 15

DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15

DDR_A_D[0..63]15

DDR_A_MA[0..15]15

DDR_A_DQS#[0..7]15

DDR_A_DQS[0..7]15

SM_DIMM_VREFCA 15
SA_DIMM_VREFDQ 15
SB_DIMM_VREFDQ 16

3

U1D

AY31

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AW31

AY29

AW29

AV31
AU31
AV29
AU29
AY27

AW27

AY25

AW25

AV27
AU27
AV25
AU25
AM29
AK29

AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25

AL25
AY23

AW23

AY21

AW21

AV23
AU23
AV21
AU21
AY19

AW19

AY17

AW17

AV19
AU19
AV17
AU17
AR21
AR22

AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18

AL18
AK20
AM20
AR18
AP18

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

2

HASWELL_MCP_E

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_CS#0
SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0
SB_BA1
SB_BA2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

AY49
AU50
AW49
AV50

AM32
AK32

AL32

DDRB_ODT0

AM35
AK35
AM33

AL35
AM36
AU49

AP40

DDR_B_MA0

AR40

DDR_B_MA1

AP42

DDR_B_MA2

AR42

DDR_B_MA3

AR45

DDR_B_MA4

AP45

DDR_B_MA5

AW46

DDR_B_MA6

AY46

DDR_B_MA7

AY47

DDR_B_MA8

AU46

DDR_B_MA9

AK36

DDR_B_MA10

AV47

DDR_B_MA11

AU47

DDR_B_MA12

AK33

DDR_B_MA13

AR46

DDR_B_MA14

AP46

DDR_B_MA15

AW30

DDR_B_DQS#0

AV26

DDR_B_DQS#1

AN28

DDR_B_DQS#2

AN25

DDR_B_DQS#3

AW22

DDR_B_DQS#4

AV18

DDR_B_DQS#5

AN21

DDR_B_DQS#6

AN18

DDR_B_DQS#7

AV30

DDR_B_DQS0

AW26

DDR_B_DQS1

AM28

DDR_B_DQS2

AM25

DDR_B_DQS3

AV22

DDR_B_DQS4

AW18

DDR_B_DQS5

AM21

DDR_B_DQS6

AM18

DDR_B_DQS7

1

SB_CLK_DDR#0 16
SB_CLK_DDR0 16
SB_CLK_DDR#1 16
SB_CLK_DDR1 16

DDRB_CKE0_DIMMB 16
DDRB_CKE1_DIMMB 16

DDRB_CS0_DIMMB# 16
DDRB_CS1_DIMMB# 16

T5@

DDR_B_RAS# 16
DDR_B_WE# 16
DDR_B_CAS# 16

DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16

DDR_B_D[0..63]16

DDR_B_MA[0..15]16

DDR_B_DQS#[0..7]16

DDR_B_DQS[0..7]16

HASWELL-MCP-E-ULT_BGA1168
@

A A

5

3 OF 19

Rev1p2

HASWELL-MCP-E-ULT_BGA1168
@

Security Classification

Security Classification

Security Classification

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4 OF 19

2

Rev1p2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

HSW MCP(2/11) DDRIII

HSW MCP(2/11) DDRIII

HSW MCP(2/11) DDRIII

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

1

of

552Tuesday, March 26, 2013

552Tuesday, March 26, 2013

552Tuesday, March 26, 2013

1.0

1.0

1.0

5

PCH_RTCX1

1 2

R101 10M_0402_5%

Y1

32.768KHZ_12.5PF_Q13FC135000040

1

D D

2

PCH_INTVRMEN

C C

12

C153
15P_0402_50V8J

R73 330K_0402_5%
R74 330K_0402_5%@

INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

HDA for AUDIO

HDA_BITCLK_AUDIO36

HDA_SYNC_AUDIO36
HDA_RST_AUDIO#36

HDA_SDOUT_AUDIO36

HDA_SDO34

SPI_WP1#_R32,34,7

PCH_RTCX2

1

C154

15P_0402_50V8J

2

1 2
1 2

RP14

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

1 2

R163 0_0402_5%9012@

1 2

R161

940@

+RTCVCC

+RTCVCC

EMC@

1U_0402_10V6K

R69
20K_0402_1%

1 2
1 2

R70
20K_0402_1%

1U_0402_10V6K

4.7K_0402_5%

1

C149

ME CMOS

2

12

1

C150

R71
0_0603_5%@

2

RTCRST close RAM door

HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDOUT

CMOS

4

+RTCVCC

1 2

R72 1M_0402_5%

HDA_SDIN036

1 2

R9751_0402_5% @

T6 @
T7 @

T8 @
T9 @

T95 @
T21 @

T19 @
T15 @
T10 @
T11 @
T22 @
T12 @

PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#

HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDIN0

HDA_SDOUT

PCH_JTAG_RST#

PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TCK_JTAGX

3

U1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

HASWELL-MCP-E-ULT_BGA1168
@

HASWELL_MCP_E

RTC

JTAG

5 OF 19

2

RSVD
RSVD

SATALED

Rev1p2

J5
H5
B15
A15

J8
H8
A17
B17

J6
H6
B14
C15

F5
E5
C17
D17

V1
U1
V6
AC1

A12
L11
K10
C12
U3

PCH_GPIO34
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37

SATA_IREF

T13@
T14@

SATA_RCOMP

PCH_SATALED#

1 2

R10
10K_0402_5%

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATAAUDIO

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

SATA_IREF

SATA_RCOMP

SATA_PRX_DTX_N0 32
SATA_PRX_DTX_P0 32
SATA_PTX_DRX_N0 32
SATA_PTX_DRX_P0 32

SATA_PRX_DTX_N1 32
SATA_PRX_DTX_P1 32
SATA_PTX_DRX_N1 32
SATA_PTX_DRX_P1 32

R937
0_0402_5%

1 2

@

PCH_GPIO35 9
PCH_GPIO36 9
PCH_GPIO37 9

1 2

R75 0_0603_5%@

within500mils

1 2

R2 3.01K_0402_1%

+3VS

1

EC_SCI# 34,9
PCH_GPIO34 9

PCH_SATALED# 35

HDD

ODD

+1.05VS_ASATA3PLL

ME Debug

W=20mils W=20milstrace width 10mil

B B

A A

20mil

+RTCVCC

1

2

D23

1

BAS40-04_SOT23-3

+RTCBATT

+CHGRTC

2

1

C168

0.1U_0402_16V4Z
@

5

2

3

R446
1K_0402_5%
@

1 2

+RTCBATT_R

3

20mil

D32
CHN202UPT_SC70-3
@

+RTCVCC+RTCBATT +CHGRTC

1

2

C151

0.1U_0402_16V4Z

+RTCBATT

1

+

-

JBATT1
LOTES_AAA-BAT-054-K01

2

CONN@

SP07000H700

Security Classification

Security Classification

Security Classification

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(3/11) RTC,SATA,XDP

HSW MCP(3/11) RTC,SATA,XDP

HSW MCP(3/11) RTC,SATA,XDP

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

652Thursday, April 18, 2013

652Thursday, April 18, 2013

652Thursday, April 18, 2013

1

1.0

1.0

1.0

5

4

3

2

1

U1F

XTAL24_IN XTAL24_IN

12

R481M_0402_5%

D D

C C

PCH_SPI_CLK_1_R32
PCH_SPI_CS0#_1_R32
PCH_SPI_MOSI_1_R32
PCH_SPI_MISO_1_R32

B B

A A

Y2

24MHZ_12PF_X3G024000DC1H

123

12

C2
10P_0402_50V8J

SPI_HOLD1#_R32

4

SPI_WP1#_R32,34,6

SPI ROM ( 8MByte for Chrome)

U6

MX25L6406EM2I-12G_SO8
940@

SA00004G600

12

C3
10P_0402_50V8J

+3VS

12

R216
10K_0402_5%
@

VGA_CLKREQ#

12

R221
10K_0402_5%

1 2

R572 0_0402_5%DEG@

1 2

R599 0_0402_5%DEG@

1 2

R603 0_0402_5%DEG@

1 2

R602 0_0402_5%DEG@

1 2

R604 0_0402_5%DEG@

PCH_SPI_WP1#

+BIOS_SPI

R105 1K_0402_5%1ROM@
R106 1K_0402_5%1ROM@

R103 1K_0402_5%2ROM@
R102 1K_0402_5%2ROM@
R564 1K_0402_5%940@

PCH_SPI_WP1#

5

XTAL24_OUT

1 2
1 2

1 2
1 2
1 2

PCH_SPI_CLK_1
PCH_SPI_CS0#
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_SPI_HOLD1#

R108
15_0402_5%

12

1ROM@

PCIE LAN

WLAN

PCH_SPI_CS0#
PCH_SPI_MISO_1
PCH_SPI_IO2_1

PCH_SPI_IO2_1
PCH_SPI_IO3_1

PCH_SPI_HOLD1#

PCH_SPI_WP1#

PCH_SPI_CS1#
PCH_SPI_MISO_2

12

PCH_SPI_IO2_2

R10933_0402_5% 2ROM@

R108
33_0402_5%
2ROM@

21

CLK_PCIE_LAN#29
CLK_PCIE_LAN29

+3VS
LAN_CLKREQ#29
CLK_PCIE_MINI1#31
CLK_PCIE_MINI131
MINI1_CLKREQ#31,8

CLK_PEG_VGA#17
CLK_PEG_VGA17

SPI ROM ( 8MByte )

U6

1

CS#

2

DO(IO1)

HOLD#(IO3)

3

WP#(IO2)

4

GND

EN25QH64-104HIP_SO8
1ROM@

SPI ROM ( 4MByte )

U7

1

CS#

2

DO

3

WP#

4

GND

EN25QH32-104HIP_SO8
2ROM@

2ROM is SPI ROM 2M + 4M Byte

RP19

33_0804_8P4R_5%
2ROM@

SD309330A80

4

U6

EN25QH16-104HIP_SO8
2ROM@

SA00004UG00

PCH_GPIO189

PCH_GPIO199

CLK_PCIE_LAN#
CLK_PCIE_LAN

1 2

R52 10K_0402_5%

CLK_PCIE_MINI1#
CLK_PCIE_MINI1
MINI1_CLKREQ#

CLK_PEG_VGA#
CLK_PEG_VGA

PCH_GPIO239

LPC_FRAME#34,35

8

VCC

7

PCH_SPI_IO3_1

6

VCC

CLK

5

DI

PCH_SPI_CLK_1
PCH_SPI_MOSI_1

8
7
6
5

PCH_SPI_IO3_2
PCH_SPI_CLK_2
PCH_SPI_MOSI_2

CLK

DI(IO0)

HOLD#

PCH_GPIO18

PCH_GPIO19

VGA_CLKREQ#

PCH_GPIO23

LPC_AD034,35
LPC_AD134,35
LPC_AD234,35
LPC_AD334,35

+BIOS_SPI

C152
10P_0402_50V8J

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1# SML0CLK

PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_WP1#

PCH_SPI_HOLD1#

D29 design for Debug
board flash SPI ROM
(can be short after MP)

1 2

R305 0_0402_5%

1 2

D29 RB751V40_SC76-2940@

1 2

C66 0.1U_0402_16V7K

PCH_SPI_MOSI_1
PCH_SPI_CLK_1
PCH_SPI_IO3_1

Reserve for EMI(Near SPI ROM)

1 2

R104 33_0402_5%XEMC@

XEMC@

+3VS

C67 0.1U_0402_16V7K

Reserve for EMI(Near SPI ROM)

C453
10P_0402_50V8J

1 2

XEMC@

Issued Date

Issued Date

Issued Date

C43
C42

B41
A41

C41
B42
AD1

B38
C37

A39
B39

B37
A37

AW12
AW11

9012@

12

1 2

PCH_SPI_MOSI_2
PCH_SPI_CLK_2
PCH_SPI_IO3_2

R402 33_0402_5%XEMC@

3

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18
CLKOUT_PCIE_N1

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19
CLKOUT_PCIE_N2

CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21
CLKOUT_PCIE_N4

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22
CLKOUT_PCIE_N5

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

HASWELL-MCP-E-ULT_BGA1168
@

U1G

AU14

LAD0
LAD1

AY12

LAD2
LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

HASWELL-MCP-E-ULT_BGA1168
@

RP19

1 8
2 7
3 6
4 5

PCH_SPI_CLK_1

2ROM@

12

2012/07/10 2013/07/10

2012/07/10 2013/07/10

2012/07/10 2013/07/10

PCH_SPI_MOSI
PCH_SPI_CLK
PCH_SPI_HOLD1#
PCH_SPI_MISOPCH_SPI_MISO_1

1ROM@

15_0804_8P4R_5%

RP20

1 8
2 7
3 6
4 5

33_0804_8P4R_5%
2ROM@

PCH_SPI_CLK_2

HASWELL_MCP_E

CLOCK

SIGNALS

6 OF 19

HASWELL_MCP_E

LPC

SPI C-LINK

7 OF 19

+3VS

PCH_SPI_MOSI
PCH_SPI_CLK
PCH_SPI_HOLD1#
PCH_SPI_MISOPCH_SPI_MISO_2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DIFFCLK_BIASREF

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

SMBALERT/GPIO11

SMBUS

SML0ALERT/GPIO60

SML1ALERT/PCHHOT/GPIO73

SML1CLK/GPIO75

SML1DATA/GPIO74

A25

XTAL24_IN

XTAL24_OUT

TESTLOW_C35

TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

B25
K21

RSVD

M21

RSVD

C26
C35

C34
AK8
AL8

AN15
AP15

B35
A35

Rev1p2

AN2
AP2

SMBCLK

AH1

SMBDATA

AL2
AN1

SML0CLK

AK1

SML0DATA

AU4
AU3
AH3

AF2

CL_CLK

AD2

CL_DATA

AF4

CL_RST

Rev1p2

DMN66D0LDW-7_SOT363-6

PCH_SMBDATA D_CK_SDATA

PCH_SMBCLK D_CK_SCLK

DMN66D0LDW-7_SOT363-6

SML1CLK

SML1DATA

2

XTAL24_OUT

T16@
T17@

XCLK_BIASREF

1 2

R140 10K_0402_5%

1 2

R141 10K_0402_5%

1 2

R142 10K_0402_5%

1 2

R148 10K_0402_5%

CLKOUT_LPC0
CLKOUT_LPC1

CLK_BCLK_ITP#
CLK_BCLK_ITP

PCH_GPIO11
PCH_SMBCLK
PCH_SMBDATA
PCH_GPIO60
SML0CLK
SML0DATA
PCH_GPIO73
SML1CLK
SML1DATA

+3VS

Q7A

2

6 1

6 1

5

3 4

Q7B

+3VS

Q8A

2

DMN66D0LDW-7_SOT363-6

3 4

DMN66D0LDW-7_SOT363-6

Q8B

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

R78 3.01K_0402_1%

R390 22_0402_5%
R395 22_0402_5%

T23@
T24@
T25@

4.7K_0402_5%

5

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

12

EMC@

12

TPM@

T184@
T183@

PCH_GPIO11 9

PCH_SMBCLK 31

PCH_SMBDATA 31

PCH_GPIO60 9

PCH_GPIO73 9

1 8

RP8 2.2K_0804_8P4R_5%
SML0DATA
PCH_SMBDATA
PCH_SMBCLK

SML1CLK
SML1DATA

+3VS

R116

1 2

PU 2.2K at EC side (+3VS)

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

HSW MCP(4/11) CLK,SPI,SMBUS

HSW MCP(4/11) CLK,SPI,SMBUS

HSW MCP(4/11) CLK,SPI,SMBUS

2 7
3 6
4 5

1 2

R114 2.2K_0402_5%

1 2

R113 2.2K_0402_5%

R119

4.7K_0402_5%

1 2

D_CK_SDATA 15,16,37

EC_SMB_CK2 18,24,34

EC_SMB_DA2 18,24,34

D_CK_SCLK 15,16,37

1

+1.05VS_AXCK_LCPLL

CLK_PCI_LPC 34
CLK_PCI_TPM 35

752Tuesday, March 26, 2013

752Tuesday, March 26, 2013

752Tuesday, March 26, 2013

+3VALW_PCH

1.0

1.0

1.0

5

+3VS

12

R227
10K_0402_5%

1 2

XDP_DBRESET#32

D D

PCH_RSMRST#

R59 0_0402_5%DEG@

1 2

R117 10K_0402_5%

SYS_RESET#

Note: EC is +3VL change to @

+3VALW_PCH

12

R245

100K_0402_5%

@

D21

@

RB751V40_SC76-2

PCH_PWROK
VGATE_3V

10K_0402_5%

2
3

10K_0804_8P4R_5%

12

@

Project_ID0Project_ID1

1 2

1 2

2
1

12

U43

R208

10K_0402_5%

MC74VHC1G08DFT2G_SC70-5
@

U17

NC1VCC
A
GND

74AUP1G07GW_TSSOP5
@

G_SEN_INT
PCH_GPIO80
MINI1_CLKREQ#
DEVSLP0

+3VS+3VS

12

R204

@

R215

10K_0402_5%

1 2

5

VGATE11,46

1 8

RP27

2 7
3 6
4 5

10K_0402_5%

10K_0402_5%

ACIN34,39,41

R205

R214

C C

B B

+3VS

A A

+3VS

5

P

B
A

G

3

+1.05VS_VTT

Y

5

4

PCH_ACIN

4

SYS_PWROK

Y

VGATE_3V

MINI1_CLKREQ# 31,7
DEVSLP0 32,9

Note: Deep Sx need use EC GPIO for
ACPRESENT function

R65
0_0402_5%

1 2

12

R207
10K_0402_5%

@

+3VS

12

R310

10K_0402_5%

@

Project ID

*

V5WE2/T2
Reserved
Reserved
Reserved

PCH_PWROK34
VCCST_PG_EC11,34

PLT_RST#34,35

PCH_RSMRST#34

SUSWARN#9

PBTN_OUT#34

+3VALW_PCH

PCH_PWROK

VGATE_3V 34

4

1 2

SYS_PWROK

PCH_PWROK_R

1 2

R61 0_0402_5%@

1 2

R62 0_0402_5%

1 2

R63 0_0402_5%@

1 2

R79 0_0402_5%@

1 2

R110 0_0402_5%@

1 2

R156 8.2K_0402_5%

PCH_INV_PWM24,25
ENBKL34
PCH_ENVDD25

EC_SMI#34

VGA_ON38,9 DDI1_AUX_DN 27

DGPU_HOLD_RST#9

PCH_GPIO559

G_SEN_INT37

PCH_GPIO519

PLT_RST#
DGPU_HOLD_RST#

Project_ID0Project_ID1

GPIO53GPIO54
00
0
1

1
0

11

4

3

U1H

R206
0_0402_5%@

12

R64 0_0402_5%

SUSACK#SUSWARN#
SYS_RESET#

SYS_PWROK_R

PCH_PWROK_R
PM_APWROK

PLT_RST#

PCH_RSMRST#_R

SUSWARN#
PBTN_OUT#_R
PCH_ACIN
PCH_BATLOW#

T31 @

EC_SMI#
VGA_ON
DGPU_HOLD_RST#
PCH_GPIO80

T26 @

PCH_GPIO55
G_SEN_INT
Project_ID1
PCH_GPIO51
Project_ID0

R405

0_0402_5%

+3VS

1

IN1

2

IN2

U37
MC74VHC1G08DFT2G_SC70-5
VGA@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

HASWELL-MCP-E-ULT_BGA1168
@

U1I

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

HASWELL-MCP-E-ULT_BGA1168
@

12

@

5

VCC

4

OUT

GND

3

12

R391
100K_0402_5%
VGA@

2012/07/10 2013/07/10

2012/07/10 2013/07/10

2012/07/10 2013/07/10

3

HASWELL_MCP_E

SYSTEM POWER MANAGEMENT

HASWELL_MCP_E

eDP SIDEBAND

GPIO

PLTRST_VGA# 17

Compal Secret Data

Compal Secret Data

Compal Secret Data

8 OF 19

DISPLAY

9 OF 19

Deciphered Date

Deciphered Date

Deciphered Date

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DDPB_HPD
DDPC_HPD

DSWVRMEN

DPWROK

WAKE

SLP_S4
SLP_S3

SLP_A
SLP_SUS
SLP_LAN

Rev1p2

EDP_HPD

Rev1p2

PLT_RST#

2

AW7

DSWODVREN

AV5

PCH_RSMRST#_R

AJ5

PCH_PCIE_WAKE#

V5

CLKRUN#

AG4

LPCPD#

AE6

SUSCLK

AP5

PM_SLP_S5#

AJ6

PM_SLP_S4#

AT4

PM_SLP_S3#

AL5
AP4
AJ7

PM_SLP_LAN#

B9
C9
D9
D11

C5
B6
B5
A6

C8
A8
D6

2

1 2

R271 2.2K_0402_5%
DDI2_CTRL_CK
DDI2_CTRL_DATA

DDI1_AUX_DN
DDI1_AUX_DP

R403

0_0402_5%

+3VS

5

1

IN1

2

IN2

U30
MC74VHC1G08DFT2G_SC70-5

3

1

DSWODVREN - On Die DSW VR Enable

H：Enable(DEFAULT)

*

L

：

Disable

1 2

R124 330K_0402_5%

1 2

R125 330K_0402_5%@

1 2
1 2

T30@
T96@

R118
10K_0402_5%

R1201K_0402_5%
R1578.2K_0402_5%

T27@
T28@

1 2

@

+RTCVCC

+3VALW_PCH
+3VS

CLKRUN# 35

T29@

+3VALW_PCH

LPCPD# 35
SUSCLK 34
PM_SLP_S5# 34

PM_SLP_S4# 34
PM_SLP_S3# 34

PCH_PCIE_WAKE# 29

not support Deep S4,S5 can NC

DDPB_CTRLDATA: Port B Detected

DDPC_CTRLDATA: Port C Detected

1: Port B or C is detected

*

0: Port B or C is not detected

(Have internal PD)

+3VS

DDI2_CTRL_CK 26

DDI2_CTRL_DATA 26

DDI1_AUX_DP 27

CPU_DP_HPD 27
CPU_HDMI_HPD 26
CPU_EDP_HPD 25

12

@

VCC

4

OUT

GND

12

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

Date: Sheet of

Date: Sheet of

Date: Sheet of

PLT_RST_BUF# 29,31

R416
100K_0402_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

HSW MCP(5/11) PM,GPIO,DDI

HSW MCP(5/11) PM,GPIO,DDI

HSW MCP(5/11) PM,GPIO,DDI

852Tuesday, March 26, 2013

852Tuesday, March 26, 2013

852Tuesday, March 26, 2013

1

1.0

1.0

1.0

5

+3VS

1 8

RP23

2 7
3 6
4 5

1 8

RP24

2 7
3 6

D D

C C

+3VALW_PCH

B B

+3VS

A A

10K_0402_5%

DGPU_PRSNT#

10K_0402_5%

RP25

RP16

RP28

RP29

RP30

RP31

RP32

R311
10K_0402_5%

RP34

RP35

RP37

RP38

RP39

RP40

R248
10K_0402_5%

+3VS

R306
UMA@

R219
VGA@

4 5
1 8

2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 2

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 2

12

1 2

10K_0804_8P4R_5%

10K_0804_8P4R_5%

10K_0804_8P4R_5%

10K_0804_8P4R_5%

10K_0804_8P4R_5%

10K_0804_8P4R_5%

10K_0804_8P4R_5%

18
27
36
45

10K_0804_8P4R_5%

18
27
36
45

10K_0804_8P4R_5%

18
27
36
45

10K_0804_8P4R_5%

10K_0804_8P4R_5%

18
27
36
45

10K_0804_8P4R_5%

10K_0804_8P4R_5%

10K_0804_8P4R_5%

10K_0804_8P4R_5%

10K_0804_8P4R_5%

5

PCH_GPIO51
PCH_GPIO83
PCH_GPIO55
SERIRQ

EC_IN_RW
PCH_GPIO69
PCH_GPIO4
PCH_GPIO7

PCH_GPIO5
PCH_GPIO1
PCH_GPIO94
PCH_GPIO93

PCH_GPIO2
PCH_GPIO91
PCH_GPIO90
PCH_GPIO38

PCH_GPIO19
PCH_GPIO36
VGA_ON
EC_KBRST#

PCH_GPIO18
PCH_GPIO35
PCH_GPIO48
PCH_GPIO34

PCH_GPIO71
PCH_GPIO49
PCH_GPIO16
PCH_GPIO37

PCH_GPIO67
PCH_GPIO65
PCH_GPIO6
PCH_GPIO64

PCH_GPIO84
PCH_GPIO0
PCH_GPIO3
PCH_GPIO89

PCH_GPIO17
PCH_GPIO23
PCH_GPIO76
PCH_GPIO50

PCH_GPIO70

PCH_GPIO10
PCH_GPIO11
SUSWARN#
USB_OC3#

PCH_GPIO8
USB_OC1#
PCH_GPIO13
PCH_GPIO26

PCH_GPIO45
PCH_GPIO14
PCH_GPIO44
PCH_GPIO46

DGPU_HOLD_RST#
PCH_GPIO47
PCH_GPIO24
PCH_GPIO28

PCH_GPIO58
PCH_GPIO59
PCH_GPIO27
PCH_GPIO25

USB_OC2#
PCH_GPIO60
USB_OC0#
PCH_GPIO9

PCH_GPIO73

DIS,Optimus

UMA

PCH_GPIO51 8

PCH_GPIO55 8

PCH_GPIO19 7
PCH_GPIO36 6
VGA_ON 38,8

PCH_GPIO18 7
PCH_GPIO35 6

PCH_GPIO34 6

PCH_GPIO37 6

PCH_GPIO23 7

PCH_GPIO11 7
SUSWARN# 8
USB_OC3# 10

USB_OC1# 10

DGPU_HOLD_RST# 8

USB_OC2# 10
PCH_GPIO60 7

USB_OC0# 10,33

PCH_GPIO73 7

GPIO87

DGPU_PRSNT#

0
1

+3VS

RP36

4

1 8
2 7
3 6
4 5

4

PCH_GPIO88
PCH_GPIO92
PCH_GPIO85
PCH_GPIO39

10K_0804_8P4R_5%

EC_SCI#34,6

GPIO15 : TLS Confidentiality

*

3

U1J

PCH_GPIO76
PCH_GPIO8

1 2

EC_LID_OUT#
PCH_GPIO16
PCH_GPIO17
PCH_GPIO24
PCH_GPIO27
PCH_GPIO28
PCH_GPIO26

PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
PCH_GPIO59
PCH_GPIO44
PCH_GPIO47
PCH_GPIO48
PCH_GPIO49
PCH_GPIO50
PCH_GPIO71
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46

PCH_GPIO9
DEVSLP0

PCH_GPIO70
PCH_GPIO38
PCH_GPIO39
PCH_SPKR

EC_LID_OUT#34

R66
0_0402_5%

1 2

EC_SCI# PCH_GPIO10

DEVSLP032,8

PCH_SPKR36

+3VALW_PCH

@

R247 10K_0402_5%@

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASWELL-MCP-E-ULT_BGA1168
@

+3VALW_PCH

12

R301

10K_0402_5%

EC_LID_OUT#

+3VALW_PCH

12

1: Intel ME TLS with confidentiality

0: Intel ME TLS with no confidentiality

(Have internal PD)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

2012/07/10 2013/07/10

2012/07/10 2013/07/10

3

HASWELL_MCP_E

CPU/
MISC

GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86

GPIO

R303
10K_0402_5%

PCH_GPIO57PCH_GPIO56

10 OF 19

PCH_GPIO86

GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93

LPIO

UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

1 2

R272 1K_0402_1%@

1 2

R273 1K_0402_5%

GSPI0_MOSI / GPIO86 : Boot BIOS Strap

1: ENABLED

0: SPI ROM

*

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

(Have internal PD)

2

THERMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD
RSVD

GSPI0_CS/GPIO83

GSPI1_CS/GPIO87

I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7

SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

Rev1p2

2

D60
V4
T4
AW15
AF20
AB21

R6

PCH_GPIO83

L6

PCH_GPIO84

N6

PCH_GPIO85

L8

PCH_GPIO86

R7

DGPU_PRSNT#

L5

PCH_GPIO88

N7

PCH_GPIO89

K2

PCH_GPIO90

J1

PCH_GPIO91

K3

PCH_GPIO92

J2

PCH_GPIO93

G1

PCH_GPIO94

K4

PCH_GPIO0

G2

PCH_GPIO1

J3

PCH_GPIO2

J4

PCH_GPIO3

F2

PCH_GPIO4

F3

PCH_GPIO5

G4

PCH_GPIO6

F1

PCH_GPIO7

E3

PCH_GPIO64

F4

PCH_GPIO65

D3

PCH_GPIO66

E4

PCH_GPIO67

C3

EC_IN_RW

E2

PCH_GPIO69

+3VS

1

+1.05VS_VTT

12

R144
1K_0402_5%

H_THERMTRIP#
SERIRQ

PCH_OPIRCOMP

T106@RP26
T32@

+3VS

1 2

EC_IN_RW 35

1 2

R269 1K_0402_1%@

R145

49.9_0402_1%

EC_KBRST# 34

SERIRQ 34,35

PCH_SPKR

SPKR / GPIO81 : NO REBOOT

1: ENABLED

0: DISABLED

*

(Have internal PD)

PCH_GPIO66

R270 1K_0402_1%@

1 2

SDIO_D0 / GPIO66 : Top-Block Swap Override

1: ENABLED

0: DISABLED

*

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

HSW MCP(6/11) GPIO,LPIO

HSW MCP(6/11) GPIO,LPIO

HSW MCP(6/11) GPIO,LPIO

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

(Have internal PD)

952Tuesday, March 26, 2013

952Tuesday, March 26, 2013

952Tuesday, March 26, 2013

1

1.0

1.0

1.0

of

5

PEG_GTX_HRX_N0 PEG_GTX_C_HRX_N0
PEG_GTX_HRX_P0 PEG_GTX_C_HRX_P0

PEG_HTX_C_GRX_N0 PEG_HTX_GRX_N0

PEG_GTX_HRX_N[0..3] 17
PEG_GTX_HRX_P[0..3] 17

D D

PEG_HTX_C_GRX_N[0..3] 17
PEG_HTX_C_GRX_P[0..3] 17

PCIE LAN

WLAN

C C

PEG_GTX_HRX_N1 PEG_GTX_C_HRX_N1
PEG_GTX_HRX_P1 PEG_GTX_C_HRX_P1

PEG_HTX_C_GRX_N1 PEG_HTX_GRX_N1

PEG_GTX_HRX_N2 PEG_GTX_C_HRX_N2
PEG_GTX_HRX_P2

PEG_HTX_C_GRX_P2 PEG_HTX_GRX_P2
PEG_GTX_HRX_N3 PEG_GTX_C_HRX_N3

PEG_GTX_HRX_P3 PEG_GTX_C_HRX_P3
PEG_HTX_C_GRX_N3 PEG_HTX_GRX_N3

PCIE_PRX_DTX_N329
PCIE_PRX_DTX_P329

PCIE_PTX_C_DRX_N329
PCIE_PTX_C_DRX_P329

PCIE_PRX_DTX_N431
PCIE_PRX_DTX_P431

PCIE_PTX_C_DRX_N431
PCIE_PTX_C_DRX_P431

+1.05VS_AUSB3PLL

C76 0.1U_0402_16V7KVGA@
C77 0.1U_0402_16V7KVGA@

C78 0.1U_0402_16V7KVGA@
C79 0.1U_0402_16V7KVGA@

C80 0.1U_0402_16V7KVGA@
C81 0.1U_0402_16V7KVGA@

C82 0.1U_0402_16V7KVGA@
C83 0.1U_0402_16V7KVGA@

C84 0.1U_0402_16V7KVGA@
C85 0.1U_0402_16V7KVGA@

C86 0.1U_0402_16V7KVGA@
C87 0.1U_0402_16V7KVGA@

C88 0.1U_0402_16V7KVGA@
C89 0.1U_0402_16V7KVGA@

C90 0.1U_0402_16V7KVGA@
C91 0.1U_0402_16V7KVGA@

R232 3.01K_0402_1%
R155 0_0603_5%@

4

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

C155 0.1U_0402_16V7K

1 2

C160 0.1U_0402_16V7K

1 2

C156 0.1U_0402_16V7K

1 2

C157 0.1U_0402_16V7K

1 2
1 2

PEG_HTX_GRX_P0PEG_HTX_C_GRX_P0

PEG_HTX_GRX_P1PEG_HTX_C_GRX_P1

PEG_GTX_C_HRX_P2
PEG_HTX_GRX_N2PEG_HTX_C_GRX_N2

PEG_HTX_GRX_P3PEG_HTX_C_GRX_P3
PCIE_PRX_DTX_N3

PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3

PCIE_PTX_DRX_P3
PCIE_PRX_DTX_N4

PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4

PCIE_PTX_DRX_P4

T33 @

T34 @
PCIE_RCOMP
PCIE_IREF

U1K

F10

PERN5_L0

E10

PERP5_L0

C23

PETN5_L0

C22

PETP5_L0

F8

PERN5_L1

E8

PERP5_L1

B23

PETN5_L1

A23

PETP5_L1

H10

PERN5_L2

G10

PERP5_L2

B21

PETN5_L2

C21

PETP5_L2

E6

PERN5_L3

F6

PERP5_L3

B22

PETN5_L3

A21

PETP5_L3

G11

PERN3

F11

PERP3

C29

PETN3

B30

PETP3

F13

PERN4

G13

PERP4

B29

PETN4

A29

PETP4

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27

PCIE_IREF

HASWELL-MCP-E-ULT_BGA1168
@

3

HASWELL_MCP_E

PCIe

USB3.0 P3 / PCIE P1

USB3.0 P4 / PCIE P2

11 OF 19

USB

USB3.0 P1

USB3.0 P2

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

USB3RN1
USB3RP1

USB3TN1
USB3TP1

USB3RN2
USB3RP2

USB3TN2
USB3TP2

USBRBIAS
USBRBIAS

RSVD
RSVD

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

Rev1p2

AN8
AM8

AR7
AT7

AR8
AP8

AR10
AT10

AM15
AL15

AM13
AN13

AP11
AN11

AR13
AP13

G20
H20

C33
B34

E18
F18

B33
A33

AJ10
AJ11
AN10
AM10

AL3
AT1
AH2
AV3

USBRBIAS

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

2

USB20_N0
USB20_P0

USB20_N1
USB20_P1

USB20_N2
USB20_P2

USB20_N4
USB20_P4

USB20_N5
USB20_P5

USB20_N6
USB20_P6

USB20_N7
USB20_P7

1 2

R154 22.6_0402_1%

T35@
T36@

1

C612

0.1U_0402_16V4Z
@

2

1

USB20_N0 33
USB20_P0 33

USB20_N1 33
USB20_P1 33

USB20_N2 33
USB20_P2 33

USB20_N4 31
USB20_P4 31

USB20_N5 33
USB20_P5 33

USB20_N6 25
USB20_P6 25

USB20_N7 25
USB20_P7 25

PCH_USB3_RX0_N 33

PCH_USB3_RX0_P 33

PCH_USB3_TX0_N 33
PCH_USB3_TX0_P 33

CADnote:
Routesingle‐end50‐ohmsandmax450‐milslength.
Avoidroutingnexttoclockpinsorunderstitchingcapacitors.
Recommendedminimumspacingtoothersignaltracesis15mils

USB_OC0# 33,9
USB_OC1# 9
USB_OC2# 9
USB_OC3# 9

USB2 Port 0 (USB3.0 P0)
USB2 Port 1
USB2 Port 2

Mini Card(WLAN+BT)
Finger Print
Touch Screen
Camera

USB3 Port 0

B B

A A

Security Classification

Security Classification

Security Classification

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(7/11) PCIE,USB

HSW MCP(7/11) PCIE,USB

HSW MCP(7/11) PCIE,USB

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

10 52Tuesday, March 26, 2013

10 52Tuesday, March 26, 2013

10 52Tuesday, March 26, 2013

1

1.0

1.0

1.0

5

Shark Bay ULT have internal gate for VDDQ

+1.35V +1.35V_CPU

J2

@

1 2

JUMP_43X118

Q5

@

AO4304L_SO8

8

D D

3VS_GATE38

+3VS

12

R422

100K_0402_5%

C C

VCCST_PG_EC34,8

@

7
6
5

1 2

@

R182
0_0402_5%

U16

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

Y

4

1

C5

0.1U_0603_25V7K
@

2

+3VALW_PCH

5

4

VCCST_PG_EC_R

1
2
3

R309

10K_0402_5%

SVID ALERT

+1.05VS_VTT

Place the PU

12

resistors close to CPU

R171
75_0402_1%

R172
43_0402_1%

12

VR_ALERT#46

B B

SVID DATA

R174
0_0402_5%

VR_SVID_DATA46

+CPU_CORE

R177

100_0402_1%

VCC_SENSE_R

A A

VSS_SENSE_R13

R233

100_0402_1%

@

12

Note:0ohmPLACEDCLOSETOCPU

@

@

12

5

H_CPU_SVIDALRT#

+1.05VS_VTT

Place the PU
resistors close to CPU

12

R173
130_0402_1%

12

12

12

R178
0_0402_5%

R235
0_0402_5%

VIDSOUT

VCC_SENSE 46

VSS_SENSE 46

+1.05VS_VTT

12

R166
0_0402_5%

1 2

4

@

VCCST_PWRGD 34,45

+1.05VS_VTT

R169
150_0402_1%
@

1 2

R170
10K_0402_5%
@

1 2

CPU_PWR_DEBUG

VR_SVID_CLK46

3

+1.05VS_VTT

+VCCIOA_OUT

VR_ON46

VGATE46,8

CPU_PWR_DEBUG

+CPU_CORE

R164

12

0_1206_5%@

1 2

1 2
1 2

1 2

Reserved Only

+1.05VS_VTT

+CPU_CORE

+1.35V_CPU

+1.35V_CPU

+VCCIO_OUT

R1650_0402_5% @

R1670_0402_5%
R1680_0402_5%
C167

@

0.1U_0402_16V7K

T37 @
T38 @

T39 @
T40 @

VCC_SENSE_R

T41 @

T42 @
T43 @
T44 @

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
VIDSOUT
VCCST_PG_EC_R
PCH_VR_EN
VR_READY

T45 @
T46 @
T47 @
T48 @
T98 @
T142 @
T143 @
T144 @
T141 @
T140 @
T147 @
T145 @
T146 @

2

U1L

L59

RSVD

J58

RSVD

AH26

VDDQ

AJ31

VDDQ

AJ33

VDDQ

AJ37

VDDQ

AN33

VDDQ

AP43

VDDQ

AR48

VDDQ

AY35

VDDQ

AY40

VDDQ

AY44

VDDQ

AY50

VDDQ

F59

VCC

N58

RSVD

AC58

RSVD

E63

VCC_SENSE

AB23

RSVD

A59

VCCIO_OUT

E20

VCCIOA_OUT

AD23

RSVD

AA23

RSVD

AE59

RSVD

L62

VIDALERT

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWRGD

F60

VR_EN

C59

VR_READY

D63

VSS

H59

PWR_DEBUG

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

RSVD

AD60

RSVD

AD59

RSVD

AA59

RSVD

AE60

RSVD

AC59

RSVD

AG58

RSVD

U59

RSVD

V59

RSVD

AC22

VCCST

AE22

VCCST

AE23

VCCST

AB57

VCC

AD57

VCC

AG57

VCC

C24

VCC

C28

VCC

C32

VCC

HASWELL-MCP-E-ULT_BGA1168
@

HASWELL_MCP_E

HSW ULT POWER

12 OF 19

1

+CPU_CORE

C36

VCC

C40

VCC

C44

VCC

C48

VCC

C52

VCC

C56

VCC

E23

VCC

E25

VCC

E27

VCC

E29

VCC

E31

VCC

E33

VCC

E35

VCC

E37

VCC

E39

VCC

E41

VCC

E43

VCC

E45

VCC

E47

VCC

E49

VCC

E51

VCC

E53

VCC

E55

VCC

E57

VCC

F24

VCC

F28

VCC

F32

VCC

F36

VCC

F40

VCC

F44

VCC

F48

VCC

F52

VCC

F56

VCC

G23

VCC

G25

VCC

G27

VCC

G29

VCC

G31

VCC

G33

VCC

G35

VCC

G37

VCC

G39

VCC

G41

VCC

G43

VCC

G45

VCC

G47

VCC

G49

VCC

G51

VCC

G53

VCC

G55

VCC

G57

VCC

H23

VCC

J23

VCC

K23

VCC

K57

VCC

L22

VCC

M23

VCC

M57

VCC

P57

VCC

U57

VCC

W57

VCC

Rev1p2

VDDQDECOUPLING

2.2U_0402_6.3V6M
C8

1

@

2

+1.05VS_VTT

1

C6

2

22U_0805_6.3V6M

1U_0402_6.3V6K

C7

1

@

2

Security Classification

Security Classification

Security Classification

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

@

4

2.2U_0402_6.3V6M
C9

1

2

2.2U_0402_6.3V6M
C10

1

2

2.2U_0402_6.3V6M
C11

1

2

10U_0603_6.3V6M

1

C12

2

2

EMC@

10U_0603_6.3V6M

1

2

For ESD

C13

EMC@

10U_0603_6.3V6M

1

1

C14

2

2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C15

2

+1.35V : 470UF/2V/7343 *2

Title

Title

Title

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

10U_0603_6.3V6M

1

1

+

C16

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

HSW MCP(8/11) Power

HSW MCP(8/11) Power

HSW MCP(8/11) Power

C18

C17

330U_2.5V_M

2

10UF/6.3V/0603 * 6

2.2UF/6.3V/0402 * 4

1

1.0

1.0

1.0

11 52Tuesday, March 26, 2013

11 52Tuesday, March 26, 2013

11 52Tuesday, March 26, 2013

5

+1.05VS_VTT

1

+

C408

220U_6.3V_M

D D

C C

Near PJ602

+1.05VS_VTT +1.05VS_AUSB3PLL

1 2

L1

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

1 2

L2

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

R210
0_0805_5%

1 2

@

1 2

L3

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

+1.05VS_VTT +1.05VS_AXCK_DCB

1 2

L4

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

1 2

L5

2.2UH_LQM2MPN2R2NG0L_30%

Idc 1.2A Rdc 0.11ohm +/-30%

2

C42 1U_0402_6.3V6K
C32 100U_1206_6.3V6M

+1.05VS_ASATA3PLL

C46 1U_0402_6.3V6K
C61 100U_1206_6.3V6M

+1.05VS_APLLOPI

C47 1U_0402_6.3V6K
C22 100U_1206_6.3V6M

C48 1U_0402_6.3V6K
C23 100U_1206_6.3V6M

+1.05VS_AXCK_LCPLL

C49 1U_0402_6.3V6K
C24 100U_1206_6.3V6M

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

Near B18

Near B11

Near AA21

Near J18

Near A20

+1.05VS_VTT

1

C21

1U_0402_6.3V6K

2

1

2

C20

1U_0402_6.3V6K

1

2

Near K9 Near L10 Near M9

Near J17

Near R21

4

C31
1U_0402_6.3V6K
EMC@

HDA --> 3.3V or 1.5V
I2C --> 1.8V

Near AC9

Near AH10

Near V8

+1.05VS_VTT

+1.05VS_AUSB3PLL

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

+3VALW_PCH

12

C38
1U_0402_6.3V6K

C28

12

22U_0805_6.3V6M
C59

@

12

0.1U_0402_16V7K
C29

12

22U_0805_6.3V6M

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL
C57

12

1U_0402_6.3V6K
C56

12

1U_0402_6.3V6K

+3VALW_PCH

+3VS

T105 @

T116 @

+3VALW_PCH

T100 @
T101 @
T102 @

U1M

K9

VCCHSIO

L10

VCCHSIO

M9

VCCHSIO

N8

VCC1_05

P9

VCC1_05

B18

VCCUSB3PLL

B11

VCCSATA3PLL

Y20

RSVD

AA21

VCCAPLL

W21

VCCAPLL

J13

DCPSUS3

AH14

VCCHDA

AH13

DCPSUS2

AC9

VCCSUS3_3

AA9

VCCSUS3_3

AH10

VCCDSW3_3

V8

VCC3_3

W9

VCC3_3

J18

VCCCLK

K19

VCCCLK

A20

VCCACLKPLL

J17

VCCCLK

R21

VCCCLK

T21

VCCCLK

K18

RSVD

M20

RSVD

V21

RSVD

AE20

VCCSUS3_3

AE21

VCCSUS3_3

HASWELL-MCP-E-ULT_BGA1168
@

3

HASWELL_MCP_E

mPHY

OPI

USB3

AXALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

LPT LP POWER

13 OF 19

RTC

SPI

CORE

THERMAL SENSOR

SDIO/PLSS

SUS OSCILLATOR

USB2

VCCSUS3_3

VCCRTC
DCPRTC

VCCSPI

VCCASW
VCCASW

VCC1_05
VCC1_05
VCC1_05
VCC1_05

VCC1_05
DCPSUSBYP
DCPSUSBYP

VCCASW
VCCASW

VCCASW
DCPSUS1
DCPSUS1

VCCTS1_5

VCC3_3
VCC3_3

VCCSDIO

VCCSDIO

DCPSUS4

RSVD
VCC1_05
VCC1_05

Rev1p2

+3VALW_PCH

AH11
AG10
AE7

Y8

AG14
AG13

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8

J15
K14
K16

U8
T9

AB8

AC20
AG16
AG17

C30 1U_0402_6.3V6K

+VCCRTCEXT

C54 0.1U_0402_16V7K

+3VS

C58 0.1U_0402_16V7K

C27 10U_0603_6.3V6M
C33 1U_0402_6.3V6K
C40 10U_0603_6.3V6M
EMC@

+PCH_VCCDSW

R209 0_0402_5%

C36 22U_0805_6.3V6M
C37 1U_0402_6.3V6K
C43 1U_0402_6.3V6K@

1 2

C55 0.1U_0402_16V7K

1 2

C44 1U_0402_6.3V6K

1 2

C53 1U_0402_6.3V6K@

1 2

C25 100U_1206_6.3V6M@

T103@

+1.05VS_VTT

1 2

C45 1U_0402_6.3V6K

2

1 2

1 2

@

1 2
1 2
1 2

1 2
1 2
1 2

+RTCVCC

12

+1.05VS_VTT
+1.05VS_VTT

1 2

@

+PCH_VCCDSW_R

+1.05VS_VTT

+1.5VS
+3VS

+3VS

C41
1U_0402_6.3V6K

1 2

+RTCVCC

1

C52

2

1U_0402_6.3V6K

1

1

@

C51

2

0.1U_0402_16V7K

1

@

C50

2

0.1U_0402_16V7K

+3VALW TO +3VALW(PCH AUX Power)

Short J5 for PCH VCCSUS3.3

B B

A A

+3VALW +3VALW_PCH

5

J5

@

JUMP_43X39

112

2

Security Classification

Security Classification

Security Classification

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(9/11) Power

HSW MCP(9/11) Power

HSW MCP(9/11) Power

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

12 52Tuesday, March 26, 2013

12 52Tuesday, March 26, 2013

12 52Tuesday, March 26, 2013

1

1.0

1.0

1.0

5

4

3

2

1

HASWELL_MCP_E

D D

C C

B B

U1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

AB22

VSS

AB7

VSS

AC61

VSS

AD21

VSS

AD3

VSS

AD63

VSS

AE10

VSS

AE5

VSS

AE58

VSS

AF11

VSS

AF12

VSS

AF14

VSS

AF15

VSS

AF17

VSS

AF18

VSS

AG1

VSS

AG11

VSS

AG21

VSS

AG23

VSS

AG60

VSS

AG61

VSS

AG62

VSS

AG63

VSS

AH17

VSS

AH19

VSS

AH20

VSS

AH22

VSS

AH24

VSS

AH28

VSS

AH30

VSS

AH32

VSS

AH34

VSS

AH36

VSS

AH38

VSS

AH40

VSS

AH42

VSS

AH44

VSS

AH49

VSS

AH51

VSS

AH53

VSS

AH55

VSS

AH57

VSS

AJ13

VSS

AJ14

VSS

AJ23

VSS

AJ25

VSS

AJ27

VSS

AJ29

VSS

HASWELL-MCP-E-ULT_BGA1168
@

14 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1p2

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29

AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49

AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63

AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

HASWELL_MCP_E

U1O

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

HASWELL-MCP-E-ULT_BGA1168
@

15 OF 19

Rev1p2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

U1P

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

HASWELL-MCP-E-ULT_BGA1168
@

G18
G22

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49

D50
D51
D53
D54
D55
D57
D59
D62

E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61

H13

D5

D8

G3
G5
G6
G8

16 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS_SENSE

VSS

Rev1p2

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

V58
AH46
V23
E62
AH16

VSS_SENSE_R 11

A A

Security Classification

Security Classification

Security Classification

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(10/11) GND

HSW MCP(10/11) GND

HSW MCP(10/11) GND

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

13 52Tuesday, March 26, 2013

13 52Tuesday, March 26, 2013

13 52Tuesday, March 26, 2013

1

1.0

1.0

1.0

5

4

3

2

1

U1Q

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3

T49 @

DC_TEST_AY61_AW61
DC_TEST_AY62_AW62

D D

C C

B B

T50 @

T104 @
T107 @
T108 @
T166 @
T167 @

T169 @
T170 @
T171 @
T172 @
T182 @
T181 @
T180 @
T179 @
T178 @
T177 @

T176 @
T175 @
T174 @
T173 @

DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63

DC_TEST_C1_C2

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG18
CFG17
CFG19

CFG_RCOMP

T90 @
T91 @

T92 @
T93 @
T94 @

TD_IREF

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

HASWELL-MCP-E-ULT_BGA1168
@

U1S

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD

E1

RSVD

D1

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

HASWELL-MCP-E-ULT_BGA1168
@

HASWELL_MCP_E

17 OF 19

HASWELL_MCP_E

RESERVED

19 OF 19

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

Rev1p2

PROC_OPI_RCOMP

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD

RSVD_TP
RSVD_TP

RSVD_TP

RSVD
RSVD

RSVD

RSVD
RSVD

VSS
VSS

RSVD
RSVD

Rev1p2

A3
A4

A60
A61
A62
AV1
AW1
AW2
AW3
AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

AV63
AU63

C63
C62
B43

A51
B51

L60
N60
W23

Y22
AY15

AV62
D58

P22
N21

P20
R20

DC_TEST_A3_B3

DC_TEST_A61_B61

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3

T75@
T76@

T77@
T78@T168 @
T79@

T80@
T81@

T82@
T83@
T84@

T85@

OPI_COMP

T86@
T87@

T88@
T89@

U1R

T51 @

T58@
T59@
T60@

T61@
T62@

T63@

T52 @
T53 @
T54 @

T55 @
T56 @
T57 @

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

HASWELL-MCP-E-ULT_BGA1168
@

CFG Straps for Processor

Physical Debug Enable (DFX Privacy)

CFG3

HASWELL_MCP_E

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

Rev1p2

CFG3

18 OF 19

12

R224
1K_0402_1%
@

1: DISABLED

0: ENABLED; SET DFX ENABLED BIT
IN DEBUG INTERFACE MSR

CFG4

12

R225
1K_0402_5%

N23
R23
T23
U10

AL1
AM11
AP7
AU10
AU15
AW14
AY14

T64@
T65@
T66@
T67@

T68@
T69@
T70@
T71@
T72@
T73@
T74@

12

R222 49.9_0402_1%
R223 49.9_0402_1%
R226 8.2K_0402_5%

A A

5

CFG_RCOMP

12
12

OPI_COMP

TD_IREF

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

Security Classification

Security Classification

Security Classification

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/07/10 2013/07/10

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(11/11) RSVD

HSW MCP(11/11) RSVD

HSW MCP(11/11) RSVD

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

14 52Tuesday, March 26, 2013

14 52Tuesday, March 26, 2013

14 52Tuesday, March 26, 2013

1

1.0

1.0

1.0

A

SA_DIMM_VREFDQ5

C158

0.022U_0402_25V7K

1 1

Layout Note:
Place near JDIMM1

+1.35V

C107

1U_0402_6.3V6K

1

1

@

2

2

2 2

+1.35V

C111

10U_0603_6.3V6M

1

1

2

2

+1.35V

C115

10U_0603_6.3V6M

1

1

2

2

3 3

+0.675VS

C121

1U_0402_6.3V6K

1

1

@

@

2

2

Layout Note:
Place near JDIMM1.203,204

4 4

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

C112

C116

1U_0402_6.3V6K

24.9_0402_1%

C108

1

@

2

C113

10U_0603_6.3V6M

1

2

EMC@

C117

10U_0603_6.3V6M

1

2

C122

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

R176

@

C109

1

2

C123

1 2

1

@

2

12

C110

1U_0402_6.3V6K

1

2

C114

10U_0603_6.3V6M

1

@

+

C118

330U_2.5V_M

2

SF000002Z00
330U 2.5V H4.2
17mohm OSCON

C124

1U_0402_6.3V6K

1

2

+1.35V

R293
2_0402_1%

All VREF traces should
have 10 mil trace width

1

2

+0.675VS

12

R54

1.8K_0402_1%

12

R185

1.8K_0402_1%

DDRA_CKE0_DIMMA5

DDRA_CS1_DIMMA#5

EMC@

C161

10U_0603_6.3V6M

+3VS

+V_DDR_REFA

2.2U_0402_6.3V6M
C106

0.1U_0402_16V7K

C105

1

1

@

2

2

DDRA_CKE0_DIMMA

C125

1

@

2

DDR_A_BS2

DDRA_CS1_DIMMA#

2.2U_0402_6.3V6M

C126

@

1 2

DDR_A_BS25

SA_CLK_DDR05
SA_CLK_DDR#05

DDR_A_BS05
DDR_A_WE#5

DDR_A_CAS#5

0.1U_0402_16V7K

1

2

B

+1.35V +1.35V

JDIMM1

VREF_DQ1VSS1

3

VSS2

R212

0_0402_5%

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013022-1
CONN@

SP07000JN10

DDR_A_D13
DDR_A_D8

DDR_A_D14
DDR_A_D10

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_D44
DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D43
DDR_A_D47

DDR_A_D51
DDR_A_D50

DDR_A_D49
DDR_A_D48

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

SA_CLK_DDR0
SA_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D6

DDR_A_D21
DDR_A_D20

DDR_A_D17
DDR_A_D16

DDR_A_D36
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D38

DDR_A_D62
DDR_A_D58

DDR_A_D60
DDR_A_D61

R211

0_0402_5%

@

1 2

DQ4
DQ5

VSS3

DQS#0

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3
DQ30

DQ31

CKE1
VDD2

A15
A14

VDD4

A11

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1
RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

C

2
4

DDR_A_D9

6

DDR_A_D12

8
10

DDR_A_DQS#1

12

DDR_A_DQS1

14
16

DDR_A_D15

18

DDR_A_D11

20
22

DDR_A_D25

24

DDR_A_D24

26
28
30

DIMM_DRAMRST#

32
34

DDR_A_D27

36

DDR_A_D26

38
40

DDR_A_D45

42

DDR_A_D40

44
46
48
50

DDR_A_D42

52

DDR_A_D46

54
56

DDR_A_D52

58

DDR_A_D53

60
62

DDR_A_DQS#6

64

DDR_A_DQS6

66
68

DDR_A_D54

70

DDR_A_D55

72

74

DDRA_CKE1_DIMMA

76
78

DDR_A_MA15

80

DDR_A_MA14

82
84

DDR_A_MA11

86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
SA_CLK_DDR1

SA_CLK_DDR#1
DDR_A_BS1

DDR_A_RAS#
DDRA_CS0_DIMMA#

SA_ODT0
SA_ODT1

+VREF_CA
DDR_A_D5

DDR_A_D4

DDR_A_D3
DDR_A_D7

DDR_A_D18
DDR_A_D19

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D23

DDR_A_D37
DDR_A_D32

DDR_A_D35
DDR_A_D39

DDR_A_D63
DDR_A_D59

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D56
DDR_A_D57

D_CK_SDATA
D_CK_SCLK

+0.675VS

A7
A6

A4
A2

A0

G2

DIMM_DRAMRST# 16,4

DDRA_CKE1_DIMMA 5

SA_CLK_DDR1 5
SA_CLK_DDR#1 5

DDR_A_BS1 5
DDR_A_RAS# 5

DDRA_CS0_DIMMA# 5

@

D_CK_SDATA 16,37,7
D_CK_SCLK 16,37,7

DDR_PG_CTRL4

DDR_A_DQS#[0..7] 5

DDR_A_DQS[0..7] 5

DDR_A_D[0..63] 5

DDR_A_MA[0..15] 5

+1.35V

12

R56

1.8K_0402_1%
R296

1 2

0.1U_0402_16V7K
C120

12

2.2U_0402_6.3V6M
C119

1

1

2

2

R295

1.8K_0402_1%

2_0402_1%

+VREF_CA 16

0.1U_0402_16V7K

U45

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

1

@

2

12

@

C34

1

@

2

5

4

Y

C162

0.022U_0402_25V7K

R294

24.9_0402_1%

+1.35V

+5VALW

SM_DIMM_VREFCA 5

D

R186
100K_0402_5%
@

1 2

+5VS

R191
100K_0402_5%

1 2

2

G

DDR_VTT_PG_CTRL 43

+1.35V

Q18
LBSS138LT1G_SOT-23-3

13

D

S

M_A_B_DIMM_ODT

1 2

R187

66.5_0402_1%

1 2

R188

66.5_0402_1%

1 2

R189

66.5_0402_1%

1 2

R190

66.5_0402_1%

E

SA_ODT0

SA_ODT1

SB_ODT0

SB_ODT1

SB_ODT0 16

SB_ODT1 16

Channel A

<Address: SA1:SA0=00>

DIMM_1 STD H:4mm

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/07/10 2013/07/10

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom
Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMA

DDRIII DIMMA

DDRIII DIMMA

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

E

of

15 52Tuesday, March 26, 2013

of

15 52Tuesday, March 26, 2013

of

15 52Tuesday, March 26, 2013

1.0

1.0

1.0

A

10U_0603_6.3V6M

1 2

1

@

2

12

C132

1U_0402_6.3V6K

1

2

C136

C146

1U_0402_6.3V6K

1

@

2

SB_DIMM_VREFDQ5

C159

0.022U_0402_25V7K

1 1

Layout Note:
Place near JDIMM1

+1.35V

C129

1U_0402_6.3V6K

1

1

@

2

2

2 2

+1.35V

C133

10U_0603_6.3V6M

1

1

2

2

+1.35V

C137

10U_0603_6.3V6M

1

1

2

2

3 3

+0.675VS

C143

1U_0402_6.3V6K

1

1

@

2

2

Layout Note:
Place near JDIMM1.203,204

4 4

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

C134

C138

1U_0402_6.3V6K

24.9_0402_1%

C130

1

@

2

C135

10U_0603_6.3V6M

1

2

C139

10U_0603_6.3V6M

1

@

2

C144

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

R179

@

C131

1

2

C145

+1.35V

R297
2_0402_1%

All VREF traces should
have 10 mil trace width

+0.675VS

12

R57

1.8K_0402_1%

12

R213

1.8K_0402_1%

DDRB_CKE0_DIMMB5

DDRB_CS1_DIMMB#5

+3VS

@

DDR_B_BS25

SB_CLK_DDR05
SB_CLK_DDR#05

DDR_B_BS05
DDR_B_WE#5

DDR_B_CAS#5

R229

10K_0402_5%

2.2U_0402_6.3V6M
C127

1

2

+3VS

1 2

C147

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

1

2

1

@

2

+V_DDR_REFB

C128

DDRB_CKE0_DIMMB

DDR_B_BS2

DDRB_CS1_DIMMB#

2.2U_0402_6.3V6M
C148

@

1 2

B

+1.35V +1.35V

JDIMM2

VREF_DQ1VSS1

3

VSS2

DDR_B_D8
DDR_B_D14

DDR_B_D10
DDR_B_D11

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D26
DDR_B_D27

DDR_B_D40
DDR_B_D41

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D42

DDR_B_D56
DDR_B_D57

DDR_B_D59
DDR_B_D58

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

SB_CLK_DDR0
SB_CLK_DDR#0

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13

DDR_B_D4
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D3
DDR_B_D7

DDR_B_D21
DDR_B_D20

DDR_B_D22
DDR_B_D23

DDR_B_D36
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D35
DDR_B_D39

DDR_B_D52
DDR_B_D49

DDR_B_D48
DDR_B_D53

R231

0_0402_5%

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013022-1
CONN@

SP07000JN10

DQ4
DQ5

VSS3

DQS#0

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3
DQ30

DQ31

CKE1
VDD2

A15
A14

VDD4

A11

VDD6

VDD8

VDD10

CK1

CK1#

VDD12

BA1
RAS#

VDD14

S0#

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

C

2
4

DDR_B_D12

6

DDR_B_D9

8
10

DDR_B_DQS#1

12

DDR_B_DQS1

14
16

DDR_B_D13

18

DDR_B_D15

20
22

DDR_B_D25

24

DDR_B_D24

26
28
30

DIMM_DRAMRST#

32
34

DDR_B_D30

36

DDR_B_D31

38
40

DDR_B_D45

42

DDR_B_D44

44
46
48
50

DDR_B_D47

52

DDR_B_D43

54
56

DDR_B_D61

58

DDR_B_D60

60
62

DDR_B_DQS#7

64

DDR_B_DQS7

66
68

DDR_B_D63

70

DDR_B_D62

72

74

DDRB_CKE1_DIMMB

76
78

DDR_B_MA15

80

DDR_B_MA14

82
84

DDR_B_MA11

86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
SB_CLK_DDR1

SB_CLK_DDR#1
DDR_B_BS1

DDR_B_RAS#
DDRB_CS0_DIMMB#

SB_ODT0
SB_ODT1

+VREF_CA
DDR_B_D5

DDR_B_D0

DDR_B_D2
DDR_B_D6

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19
DDR_B_D18

DDR_B_D37
DDR_B_D32

DDR_B_D34
DDR_B_D38

DDR_B_D51
DDR_B_D55

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54
DDR_B_D50

D_CK_SDATA
D_CK_SCLK

+0.675VS

A7
A6

A4
A2

A0

G2

DIMM_DRAMRST# 15,4

DDRB_CKE1_DIMMB 5

SB_CLK_DDR1 5
SB_CLK_DDR#1 5

DDR_B_BS1 5
DDR_B_RAS# 5

DDRB_CS0_DIMMB# 5
SB_ODT0 15

SB_ODT1 15

2.2U_0402_6.3V6M
C141

1

@

2

D_CK_SDATA 15,37,7
D_CK_SCLK 15,37,7

0.1U_0402_16V7K

1

2

DDR_B_DQS#[0..7] 5

DDR_B_DQS[0..7] 5

DDR_B_D[0..63] 5

DDR_B_MA[0..15] 5

+VREF_CA 15

C142

D

E

Channel B

<Address: SA1:SA0=10>

DIMM_2 STD H:4mm

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/07/10 2013/07/10

2012/07/10 2013/07/10

2012/07/10 2013/07/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom
Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMB

DDRIII DIMMB

DDRIII DIMMB

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

V5WE2 M/B LA-9531P Schematic

E

of

16 52Tuesday, March 26, 2013

of

16 52Tuesday, March 26, 2013

of

16 52Tuesday, March 26, 2013

1.0

1.0

1.0