Compal LA-9431P VAZ50 Goliad 12, Latitude E7240 Schematic

A

COMPAL CONFIDENTIAL

B

C

D

E

1 1

PCB NO :
BOM P/N :

LA-9431P (DAA00005Z10)
4319LL31LXX

MODEL NAME :

VAZ50

GPIO MAP: 3.0C

2 2

Goliad 12"

Haswell ULT

2013-05-17

@ : Nopop Component

1@ : M/B 8M SPI ROM Component

3 3

2@ : TAA/B 8M SPI ROM

REV : 1.0 (A00)

SPI on MB TAA

EMC@ : EMI & ESD & RF Component

XDP@ : XDP Component

CONN@ : Connector Component

3@ : Delete componet for cost down BOM

Vpro

non-Vpro

1@/4@/EMC@/
3@/EMC_3@

1@/EMC@/
3@/EMC_3@

2@/5@/EMC@
3@/EMC_3@

2@/5@/EMC@
3@/EMC_3@

EMC_3@ : Delete EMC component for cost down BOM

4@ : M/B 4M SPI ROM Component
5@ : TAA/B 4M SPI ROM

4 4

MB PCB

MB PCB

Part Number

Part Number

DAA00005Z10

DAA00005Z10

7@ : M/B for 8M SPI(Reverse)

Description

Description

PCB 0VM LA-9431P REV1 M/B 4

PCB 0VM LA-9431P REV1 M/B 4

A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

B

C

non-Vpro
(cost down)

1@/EMC@

D

2@/5@/EMC@/

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-9431P

LA-9431P

LA-9431P

1 59Friday, May 17, 2013

1 59Friday, May 17, 2013

1 59Friday, May 17, 2013

E

0.3

0.3

0.3

A

Goliad12 Block Diagram

B

C

D

E

Memory BUS (DDR3L)

USB

USB2.0[7]

PAGE 7

PAGE 36

1333/1600MHz

DOCKED_LIO_EN

USB2.0[0]

DOCKED

USB2.0[5]
USB3.0[3]

HD Audio I/F

SATA0

Full Mini Card
mSATA

Trough eDP Cable

NX3DV221

USB20 Switch

PI3USB3102

USB3&2 Switch

Touch Screen
Conn

PAGE 27

eDP

DDI2

INTEL

HASWELL
ULT

1 1

Mini-DP

DP

For MB/Dock

DP

Video Switch

IDT VMM2320

VGA

eDP CONN

PAGE 27

PAGE 21

PAGE 22

DP

DP

Pericom
PI3VDP12412

BGA CPU

DOCKING
PORT

2 2

PAGE 34

DAI

DOCK_USB3.0[3]

SATA1
DOCK_USB2.0[0]
DOCK_USB2.0[5]

PCIE3 PCIE4

HDMI CONN

PAGE 23

SD4.0

HDMI

PAGE 30 PAGE 30

Intel Clarkville

RFID

60GHz

PAGE 31 PAGE 31

TDA8034HN

Fingerprint
CONN

I218LM

PAGE 28

3 3

LAN SWITCH
PI3L720

PAGE 28

Transformer

PAGE 35

RJ45

PAGE 35

Smart Card

Reduce Level
Shifter

PAGE 23

Card reader

O2 Micro OZ777FJ2LN

PCI Express BUS

PCIE6_L0

Full Mini CardWLAN+BT/
WWAN+mSATA

SATA2

USB2.0[6]USB2.0[2]

BCM5882

FP_USB

PAGE 29

FAN CONN

4 4

A

B

DDI1

PCIE5_L0

Discrete TPM

AT97SC3204

PAGE 29

USH

USB2.0[4]

USH board

SMSC KBC

MEC5075

PAGE 37 PAGE 37

KB and TP CONN

PAGE 38

PAGE 6~17

SPI

W25Q64FVSSIQ

64M 4K sector

W25Q32FVSSIQ

LPC

32M 4K sector

SMSC SIO

ECE5048

BC BUS

C

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

REV. type

SW_USB2.0[0]

PAGE 33

PAGE 32

PAGE 25

PAGE 22

HDA Codec
ALC3226

D

PAGE 18 19

USB2.0[3]

USB POWER SHARE

DOCK _USB2.0[0]

SW_USB2.0[5]
SW_USB3.0[3]

USB2.0[1]

USB3.0[1]

PAGE 26

Trough eDP Cable

Camera

PAGE 22

Trough eDP Cable

SLGC55594A

PAGE 33

USB3.0/2.0+PS

IO/B

Near Field

PAGE 33

PAGE 20

USB3.0/2.0

DOCK _USB2.0[5]
DOCK_USB3.0[3]

USB3.0/2.0

PAGE 35

USB3.0[2]

PAGE 33

Communications con

INT.Speaker

PAGE 26

Vol bottom SW

Combo Jack

DAI

To Docking side

CPU XDP Port

PAGE 40

PAGE 9

Automatic Power

Dig.
MIC

PAGE 22

Switch (APS)

WiFi ON/OFF

PAGE 9

PAGE 35

DC/DC Interface

PAGE 39

Power On/Off
SW & LED

PAGE 40

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

LA-9431P

LA-9431P

LA-9431P

2 59Friday, May 17, 2013

2 59Friday, May 17, 2013

2 59Friday, May 17, 2013

E

IO/B

0.3

0.3

0.3

5

4

3

2

1

POWER STATES

State

S0 (Full ON) / M0

D D

S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF

S4 (Suspend to DISK) / M3 ON ON OFF

S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF HIGH

S5 (SOFT OFF) / M-OFF

Signal

SLP
S3#

HIGH

LOW HIGH HIGH

LOW HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP

SLP

S5#

S4#

HIGH HIGH

LOW

LOW

SLP
A#

HIGH

HIGH

ALWAYS
PLANE

ON

M
PLANE

ON

SUS

RUN

PLANE

PLANE

ON ON ON

OFF

OFF

CLOCKS

OFF

OFF

OFF

PCIE

PCIE 1

PCIE 2

PCIE 3

PCIE 4

PCIE 5

PCIE 6 WWAN(PP/mSATA)

USB3.0

USB3.0 1

USB3.0 2

USB3.0 3

SATA

SATA 3

DESTINATION

JUSB3-->Right

JUSB1-->Rear left

JUSB2-->Rear Right//DOCK

LOM

WLAN (WiGi)

MMI (CARD READER)

PM TABLE

C C

power
plane

+3.3V_ALW

+3.3V_ALW_PCH

+3.3V_RTC_LDO

+3.3V_SUS+5V_ALW +5V_RUN

+1.35V_MEM

+0.675V_DDR_VTT

+1.05V_RUN

+VCC_CORE

+3.3V_M +3.3V_M

+1.05V_M+3.3V_RUN

+1.05V_M

(M-OFF)

SATA 2

SATA 0

USB PORT#

State

0

1

S0

S3

S5 S4/AC

S5 S4/AC don't exist

B B

ON

ON

ON ON

ON

OFF

OFFOFF

OFFON

OFF

OFF

ON

ON

ON

need to update Power Status and
PM Table

ON

OFF

OFF

OFFOFF

HSW
ULT

2

3

4

5

6

7

JUSB1 // E-Dock 1

JUSB3

WLAN + BT

CAMERA

USH->SMART CARD

JUSB2 // E-Dock 2

WWAN

TOUCH

NA

mSATASATA 1

DOCK

DESTINATION

USH

0

1

BIO

NA

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Index and Config.

Index and Config.

Index and Config.

LA-9431P

LA-9431P

LA-9431P

3 59Friday, May 17, 2013

3 59Friday, May 17, 2013

3 59Friday, May 17, 2013

1

0.3

0.3

0.3

5

4

3

2

1

+1.05V_RUN

+3.3V_RUN

A_ON

PWRSHARE_EN#

ESATA_USB_PWR_EN#

USB_SIDE_EN#

TPS51212

(PU300)

D D

ADAPTER

DOCKED

TPS22966

+1.05V_M

(U31)

MPHYP_PWR_EN

G547I2P81U

(U35)

+5V_USB_
CHG_PWR

G547I2P81U

(U32)

+USB_PWR

G547I2P81U

(U52)

+USB_SIDE_PWR

SI3456DDV

BATTERY +PWR_SRC

EN_INVPWR

+1.05V_RUN_VMM

FDC654P

(Q2)

C C

+3.3V_RUN_VMM

+BL_PWR_SRC

CHARGER

(Q125)

+1.05V_MODPHY

ALWON

TPS51285BRUKR

(PU100)

+5V_ALW

+3.3V_ALW

RUN_ON

PCH_ALW_ON

TPS22966

3.3V_HDD_EN

TPS22966

(U3)

AUX_EN_WOWL

ENVDD_PCH

APL3512A

(U9)

RUN_ON

TPS22966

(U46)

RUN_ON

RUN_ON

RUN_ON

TPS22966

(U18)

SIO_SLP_LAN#

SUS_ON

TPS51622

(PU500)

B B

RT8207
(PU11)

A_ON

TPS22966

(U45)

MCARD_WWAN_PWREN

TPS22966

(U22)

TPS22966

(U22)

(U43)

+3.3V_ALW_PCH

H_VR_EN

SUS_ON

+VCC_CORE

A A

+1.35V_MEM

+0.675V_DDR_VTT

5

+5V_RUN
_AUDIO

0.675V_DDR_VTT_ON

+3.3V_M

+3.3V_SUS

4

+3.3V_LAN

+3.3V_mSATA_WWAN

+3.3V_WLAN

+3.3V_RUN

+3.3V_HDD

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

+LCDVDD

+3.3V_CAM

3.3V_TS_EN

3.3V_CAM_EN

LP2301ALT1G

(Q3)

2

+5V_RUN

LP2301ALT1G

(Q1)

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3.3V_RUN
_AUDIO

+1.05V_RUN

+3.3V_TSP

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Power Rail

Power Rail

Power Rail

LA-9431P

LA-9431P

LA-9431P

4 59Friday, May 17, 2013

4 59Friday, May 17, 2013

4 59Friday, May 17, 2013

1

0.3

0.3

0.3

5

SMBUS Address [0x9a]

AP2

AH1

MEM_SMBCLK

MEM_SMBDATA

PCH

D D

B4

A3

B5

A4

SML0CLK

SML0DATA

2.2K

2.2K

DOCK_SMB_CLK

DOCK_SMB_DAT

LCD_SMBCLK

LCD_SMBDAT

+3.3V_ALW_PCH

AN1

AK1

AU3AH3

SML1_SMBDATA

SML1_SMBCLK

B6A5

3A

3A

1A

1A

C C

1B

1B

1K

1K

2.2K

2.2K

4

+3.3V_ALW_PCH

2.2K

2.2K

2.2K

2.2K

+3.3V_ALW_PCH

+3.3V_ALW

+3.3V_ALW

2N7002

2N7002

0ohm

0ohm

0ohm depop

0ohm depop

127

129

NFC_SMBCLK

NFC_SMBDATA

DOCKING

LAN_SMBCLK

LAN_SMBDATA

3

28

31

LOM

2

202

200

202

200

53

51

DIMMA

DIMMB

XDP

1

NFC

30

32

WWAN

2.2K

4

+3.3V_ALW

100 ohm

100 ohm

+3.3V_SUS

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

7

BATTERY

6

CONN

M9

L9

USH

9

8

Charger

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

Compal Electronics, Inc.

SMBUS TOPOLOGY

SMBUS TOPOLOGY

SMBUS TOPOLOGY

LA-9431P

LA-9431P

LA-9431P

5 59Friday, May 17, 2013

5 59Friday, May 17, 2013

5 59Friday, May 17, 2013

1

0.3

0.3

0.3

KBC

A56

1C1CB59

PBAT_SMBCLK

PBAT_SMBDAT

2.2K

2.2K

2.2K

A50

B53

A49

B52

USH_SMBCLK

USH_SMBDAT

2.2K

2.2K

CARD_SMBCLK

CARD_SMBDAT

1E

B B

1E

MEC 5075

2B

2B

10K

B50

A47

CHARGER_SMBCLK

CHARGER_SMBDAT

1G

1G

10K

2.2K

2.2K

B7

A7

BAY_SMBDAT

BAY_SMBCLK

2D

A A

2D

2.2K

2.2K

B7

A7

GPU_SMBDAT

GPU_SMBCLK

2A

2A

5

5

+RTC_CELL

330K_0402_1%

330K_0402_1%

12

RC1

RC1

PCH_INTVRMEN

330K_0402_1%

330K_0402_1%

12

@RC2

@

D D

INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs

RC2

+3.3V_AL W_PCH

1 2

RC3 1K_0 402_5%@RC3 1K_0402 _5%@

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = ENABLE (DEFAULT)
HIGH = DISABLE

PCH_AZ_S DOUT

4

3

2

1

1 2

CC1

CC1

15P_040 2_50V8J

15P_040 2_50V8J

C C

1 2

RC7 1M_0402 _5%RC7 1M_0402_5 %

CMOS_CLR1

Shunt Clear CMOS

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

0_0603_5%

0_0603_5%

12

@

@

B B

+1.05V_M_ JTAG PCH_JTAG_TDI

CMOS setting

TPM setting

Keep ME RTC Registers

RC16

RC16

RC17 51_ 0402_1%RC17 51_0402 _1%

RC18 51_ 0402_1%RC18 51_0402 _1%

RC20 51_ 0402_1%RC20 51_0402 _1%

RC10 1K_ 0402_1%@RC1 0 1K_040 2_1%@

RC22 51_ 0402_1%@ RC22 51_ 0402_1%@

reference 479493 figure 7-1

Keep CMOS

12

12

PCH_JTAG_TDO

12

PCH_JTAG_TMS

12

PCH_JTAG_JTA GX

12

PCH_JTAG_TCK

+RTC_CELL

1

1

2

@

@

ME1 SHORT PA DS~D

ME1 SHORT PA DS~D

1 2

CC3 1U_ 0402_6.3V 6KCC3 1U_0402_ 6.3V6K

1 2
1 2

RC8 20K_040 2_5%RC8 20K_040 2_5%
RC6 20K_040 2_5%RC6 20K_040 2_5%

2

CC2 15P _0402_50 V8JCC2 15P_0402_ 50V8J

1

1

@

@

CMOS1 SHORT PADS~ D

CMOS1 SHORT PADS~ D

1 2

CC4

CC4

CMOS place near DIMM

1 2

2

2

1U_0402 _6.3V6K

1U_0402 _6.3V6K

YC1

YC1

32.768K HZ_12.5PF_Q 13FC135000 040

32.768K HZ_12.5PF_Q 13FC135000 040

1 2

RC4 0_0402_ 5%@RC4 0_0402_ 5%@

12

PCH_RTCRST#<9>

PCH_AZ_CO DEC_SDIN0<26>

ME_FWP<36>

PCH_JTAG_TRS T#<9>
PCH_JTAG_TCK<9>
PCH_JTAG_TDI<9>
PCH_JTAG_TDO<9>
PCH_JTAG_TMS<9>

PCH_JTAG_JTA GX<9>

PCH_RTCX1PCH_RTCX1_R

10M_0402_5%

10M_0402_5%

12

RC5

RC5

PCH_RTCX2

INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#

PCH_AZ_B ITCLK
PCH_AZ_S YNC
PCH_AZ_RS T#
PCH_AZ_CO DEC_SDIN0

1 2

RC9 1K_04 02_5%RC9 1K_ 0402_5%

PCH_AZ_S DOUT

T3 PAD~D@T3 PAD~ D@
T4 PAD~D@T4 PAD~ D@

T5 PAD~D@T5 PAD~ D@

PCH_JTAG_TRS T#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_JTAG_JTA GX

UC1E

UC1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

HASWELL_MCP_E

HASWELL_MCP_E

RTC

RTC

JTAG

JTAG

5 OF 19

5 OF 19

SATAAUDIO

SATAAUDIO

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

SATA_IREF

RSVD
RSVD

SATA_RCOMP

SATALED

Rev1p2

Rev1p2

J5
H5
B15
A15

J8
H8
A17
B17

J6
H6
B14
C15

F5
E5
C17
D17

V1

MPCIE_RST#

U1

HDD_DET#

V6

PCH_GPIO 36

AC1

mCARD_PC IE_SATA#

A12

SATA_IREF

L11
K10
C12

SATA_COMP

U3

SATA_ACT#

SATA_PRX_ DKTX_N0_C <3 4>
SATA_PRX_ DKTX_P0_C <34>
SATA_PTX_DK RX_N0_C <34>
SATA_PTX_DK RX_P0_C <34>

SATA_PRX_ DTX_N1_C <25 >
SATA_PRX_ DTX_P1_C <25>
SATA_PTX_DR X_N1_C <2 5>
SATA_PTX_DR X_P1_C <25>

SATA_PRX_ mSATATX_N3 <31>

SATA_PRX_ mSATATX_P3 <31>
SATA_PTX_m SATARX_N3 <31>
SATA_PTX_m SATARX_P3 <31>

MPCIE_RST# <31,7>

HDD_DET# <25 >

PCH_GPIO 36 <1 0>

mCARD_PC IE_SATA# <36>

12

RC14 0_0 402_5%@RC1 4 0_0402 _5%@

SATA_ACT# <40>

T1PAD~D @T1PAD~D @
T2PAD~D @T2PAD~D @

DOCK

SATA HDD (for G oliad 12 to MSA TA)

mSATA HDD(for W WAN card)

PCH Rx side need use strap pin to update PCIE +/-

+PCH_ASATA 3PLL

mCARD_PC IE_SATA#

SATA Impedance Compensation

SATA_COMP

CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.

1 2

HDD_DET#

1 2

+PCH_ASATA 3PLL

1 2

RC19 3.0 1K_0402_1 %R C19 3.01K_ 0402_1%

reference FFRD sch 0.5

+3.3V_RUN+1.05V_M

RC11100K_04 02_5% RC11100K_04 02_5%

RC1210K_040 2_5% RC1210K_040 2_5%

HDA for Codec

1 2

PCH_AZ_CO DEC_SDOUT<26>

PCH_AZ_CO DEC_SYNC<26>

PCH_AZ_CO DEC_RST#<26>

PCH_AZ_CO DEC_BITCLK<26>

A A

RC23 33_0402 _5%RC23 33_0402_5 %

RC24 33_0402 _5%RC24 33_0402_5 %

RC25 33_0402 _5%RC25 33_0402_5 %

RC26 33_0402 _5%

RC26 33_0402 _5%
27P_0402_50V8J

27P_0402_50V8J

@CC5

@

CC5

1

2

EMI depop location

5

1 2

1 2

1 2

EMC@

EMC@

PCH_AZ_S DOUT

PCH_AZ_S YNC

PCH_AZ_RS T#

PCH_AZ_B ITCLK

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Title

Title

Size Documen t Number Rev

Size Documen t Number Rev

Size Documen t Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(1/12)

MCP(1/12)

MCP(1/12)

LA-9431P

LA-9431P

LA-9431P

1

6 59Friday, May 17, 20 13

6 59Friday, May 17, 20 13

6 59Friday, May 17, 20 13

0.3

0.3

0.3

5

HASWELL_MCP_E

SPI_PCH_DO2_64PCH_SPI_DO2

HASWELL_MCP_E

LPC

LPC

SPI C-LINK

SPI C-LINK

UC1G

UC1G

LPC_LAD0<25,29,36,37>
LPC_LAD1<25,29,36,37>
LPC_LAD2<25,29,36,37>
LPC_LAD3<25,29,36,37>

LPC_LFRAME#<25,29,36,37>

D D

+3.3V_M

1 2

1 2

reference PDG0.7

SPI_WP#_SEL<36>

PCH_SPI_DO2

PCH_SPI_DO3

PCH_SPI_CS0# SPI_PCH_CS0#_R
PCH_SPI_DIN SPI_DIN64

SPI_WP#_SEL

R1 1K_0402_5%R1 1K_0402_5%

R2 1K_0402_5%R2 1K_0402_5%

C C

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#

PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3

reference PDG0.7

R3 0_0402_5%1@ R3 0_0402_5%1@

R4 33_0402_5%1@ R4 33_0402_5%1@

R6 33_0402_5%1@ R6 33_0402_5%1@

R8 0_0402_5%@R8 0_0402_5%@

1 2
1 2
1 2

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

12

200 MIL SO8

reference PDG0.7

R23 0_0402_5%@R23 0_0402_5%@

1 2

R14 0_0402_5%4@ R14 0_0402_5%4@

1 2

R15 33_0402_5%4@ R15 33_0402_5%4@
R19 33_0402_5%4@ R19 33_0402_5%4@

1 2

SPI_DIN32PCH_SPI_DIN
SPI_PCH_DO2_32

12

10/100/1G LAN - -->

PCH_SPI_CS1# SPI_PCH_CS1#_R

PCH_SPI_DO2

SPI_WP#_SEL

SPI_CLK64SPI_CLK32

33_0402_5%

33_0402_5%

33_0402_5%

@

@

R45

R45

1 2

0.1U_0402_25V6

0.1U_0402_25V6

@

@

2

C85

C85

1

B B

33_0402_5%

@

@

R57

R57

1 2

0.1U_0402_25V6

0.1U_0402_25V6

@

@

2

C76

C76

1

WLAN (Mini Card 2)--->

ADD EMI solution(EMC)

+3.3V_RUN

PCI_CLK_LPC_0

PCI_CLK_LPC_1

A A

RP4

RP4

1 8
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

12

CC1512P_0402_50V8J @ CC1512P_0402_50V8J @

12

CC1412P_0402_50V8J @CC1412P_0402_50V8J @

DGPU_PWROK
MINI2CLK_REQ#
MINI1CLK_REQ#
MPCIE_RST#

WWAN (Mini Card 1)--->

DGPU_PWROK <10>

MPCIE_RST# <31,6>

32Mb Flash ROM

MMI--->

1
2
3
4

4

SMBUS

SMBUS

SML1ALERT/PCHHOT/GPIO73

7 OF 19

7 OF 19

64Mb Flash ROM

200 MIL SO8

U1

1@U1

1@

1

/CS

2

DO(IO1)

/HOLD(IO3)

3

/WP(IO2)

4

GND

W25Q64FVSSIQ_SO8

W25Q64FVSSIQ_SO8

U2

4@U2

4@

/CS
DO/IO1
/WP/IO2
GND

W25Q32FVSSIQ_SO8

W25Q32FVSSIQ_SO8

/HOLD/IO3

DI/IO0

DI(IO0)

VCC

CLK

AN2

SMBALERT/GPIO11

SMBCLK

SMBDATA

SML0ALERT/GPIO60

SML0CLK

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

Rev1p2

Rev1p2

+3.3V_M

8

VCC

7
6

SPI_CLK64

CLK

5

SPI_DO64 PCH_SPI_DO

+3.3V_M

0.1U_0402_25V6

0.1U_0402_25V6

8
7

SPI_PCH_DO3_32

6
5

SPI_DO32

+3.3V_RUN

PCH_TPM_LPC_EN<29>

+3.3V_RUN

CLK_PCIE_LAN#<28>
CLK_PCIE_LAN<28>

LANCLK_REQ#<10,28>

CLK_PCIE_MINI2#<31>

CLK_PCIE_MINI2<31>
MINI2CLK_REQ#<31>

CLK_PCIE_MMI#<30>
CLK_PCIE_MMI<30>

MMICLK_REQ#<30>

+3.3V_RUN

CLK_PCIE_MINI1#<31>
CLK_PCIE_MINI1<31>
MINI1CLK_REQ#<31>

PCI_CLK_LPC

PCH_SMB_ALERT#

AP2

MEM_SMBCLK

AH1

MEM_SMBDATA

AL2
AN1
AK1

SML0DATA

AU4

PCH_GPIO73

AU3

SML1_SMBCLK

AH3

SML1_SMBDATA

AF2

PCH_CL_CLK1

AD2

PCH_CL_DATA1

AF4

PCH_CL_RST1#

C5

1@ C5

1@

1 2

0.1U_0402_25V6

0.1U_0402_25V6

R5 33_0402_5%1@ R5 33_0402_5%1@

1 2
1 2

R7 33_0402_5%1@ R7 33_0402_5%1@
R9 33_0402_5%1@ R9 33_0402_5%1@

1 2

C6

4@ C6

4@

1 2

1 2

R16 33_0402_5%4@ R16 33_0402_5%4@
R20 33_0402_5%4@ R20 33_0402_5%4@

1 2
1 2

R21 33_0402_5%4@ R21 33_0402_5%4@

1 2

RC57 10K_0402_5%RC57 10K_0402_5%

1 2

RC56 10K_0402_5%RC56 10K_0402_5%

1 2

RC55 10K_0402_5%RC55 10K_0402_5%

SML1_SMBCLK <37>

PCIECLK_REQ0#

CLK_PCIE_LAN#
CLK_PCIE_LAN
LANCLK_REQ#

CLK_PCIE_MINI2#
CLK_PCIE_MINI2
MINI2CLK_REQ#

CLK_PCIE_MMI#
CLK_PCIE_MMI
MMICLK_REQ#

CLK_PCIE_MINI1#
CLK_PCIE_MINI1
MINI1CLK_REQ#

1 2

RC58 22_0402_5%EMC@RC58 22_0402_5%EMC@

1 2

RC61 22_0402_5%EMC@RC61 22_0402_5%EMC@

1 2

RC63 22_0402_5%EMC@RC63 22_0402_5%EMC@

3

PCH_SMB_ALERT# <11>

SML1_SMBDATA <37>

PCH_CL_CLK1 <31>
PCH_CL_DATA1 <31>
PCH_CL_RST1# <31>

PCH_SPI_DO3SPI_PCH_DO3_64
PCH_SPI_CLK

PCH_SPI_DO3
PCH_SPI_CLKSPI_CLK32
PCH_SPI_DO

UC1F

UC1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

PCH_SPI_DO
PCH_SPI_DO

PCH_SPI_CLK
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#

PCH_SPI_DIN
PCH_SPI_DIN

HASWELL_MCP_E

HASWELL_MCP_E

CLK_PCI_TPM_TCM <29>

CLK_PCI_5048 <36>

CLK_PCI_MEC <37>

SML0CLK

SML0DATA

CLOCK

CLOCK

SIGNALS

SIGNALS

6 OF 19

6 OF 19

R11 33_0402_5%2@ R11 33_0402_5%2@
R12 33_0402_5%5@ R12 33_0402_5%5@

R13 33_0402_5%2@ R13 33_0402_5%2@
R18 33_0402_5%5@ R18 33_0402_5%5@
R10 0_0402_5%2@ R10 0_0402_5%2@
R17 0_0402_5%5@ R17 0_0402_5%5@

R22 33_0402_5%2@ R22 33_0402_5%2@
R41 33_0402_5%5@ R41 33_0402_5%5@

RC29 0_0402_5%@ RC29 0_0402_5%@

RC31 0_0402_5%@ RC31 0_0402_5%@

RC33 0_0402_5%@ RC33 0_0402_5%@

RC35 0_0402_5%@ RC35 0_0402_5%@

1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2

DIFFCLK_BIASREF

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

MEM_SMBCLKSML0CLK

MEM_SMBDATA

+3.3V_RUN

XTAL24_IN

XTAL24_OUT

RSVD
RSVD

Rev1p2

Rev1p2

2

12

12

12

12

1 2

1 2

TAA_DO64
TAA_DO32

TAA_CLK64
TAA_CLK32
TAA_CS0#_R
TAA_CS1#_R

TAA_DIN64
TAA_DIN32

DDR_XDP_WAN_SMBDAT

DDR_XDP_WAN_SMBCLK

15
17
19

R122 10K_0402_5%R122 10K_0402_5%

R123 10K_0402_5%R123 10K_0402_5%

21

ACES_50185-02041-001

ACES_50185-02041-001

A25

XTAL24_IN

B25

XTAL24_OUT

K21
M21
C26

CLK_BIASREF

C35

MCP_TESTLOW1

C34

MCP_TESTLOW2

AK8

MCP_TESTLOW3

AL8

MCP_TESTLOW4

AN15

PCI_CLK_LPC_0

AP15

PCI_CLK_LPC_1

B35
A35

+3.3V_RUN

5

3 4

QC1A

QC1A

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

LAN_SMBCLK <28>

LAN_SMBDATA <28>

NFC_SMBCLK <20>

NFC_SMBDATA <20>

+3.3V_M

CONN@

CONN@

JTAA1

JTAA1

2

112

4

334

6

556

8

TAA_DO3_64

778

10

TAA_DO3_32

9910

12

TAA_DO2_64

111112

14

TAA_DO2_32

131314

16

16

15

18

18

17

20

20

19

G22G

24

G23G

RC40 0_0402_5%@RC40 0_0402_5%@

1M_0402_5%

1M_0402_5%

RC44

RC44

1 2

T6

PAD~D

PAD~D

T7

PAD~D

PAD~D

2

G

G

6 1

S

D

S

D

QC1B

QC1B

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

SGD

SGD

MEM_SMBCLK

MEM_SMBDATA

PCH_GPIO73

SML1_SMBCLK

SML1_SMBDATA

SML0CLK

SML0DATA

TAA Config

R43 33_0402_5%2@ R43 33_0402_5%2@

1 2
1 2

R48 33_0402_5%5@ R48 33_0402_5%5@
R58 33_0402_5%2@ R58 33_0402_5%2@

1 2
1 2

R59 33_0402_5%5@ R59 33_0402_5%5@

XB use 50185-02041-001

1 2

@T6

@
@T7

@

1 2
1 2
1 2

XTAL24_IN_R

RC650_0402_5% @RC650_0402_5% @
RC6422_0402_5% EMC_3@RC6422_0402_5% EMC_3@
RC6622_0402_5% EMC@RC6622_0402_5% EMC@

CLK_BIASREF

MCP_TESTLOW1

MCP_TESTLOW2

MCP_TESTLOW3

MCP_TESTLOW4

3

1

4

24MHZ_12PF_X3G024000DC1H

24MHZ_12PF_X3G024000DC1H

2

PCI_CLK_LPC

1

DDR_XDP_WAN_SMBCLK <18,19,31,9>

DDR_XDP_WAN_SMBDAT <18,19,31,9>

1 2

1 2

Intel PDG 0.9

CC7

CC7

18P_0402_50V8J

18P_0402_50V8J

YC2

YC2

CC6

CC6

18P_0402_50V8J

18P_0402_50V8J

CLK_PCI_DOCK <34>
CLK_PCI_LPDEBUG <25>

+PCH_VCCACLKPLL

1 2

1 2

1 2

1 2

1 2

PCH_SPI_DO3
PCH_SPI_DO3
PCH_SPI_DO2
PCH_SPI_DO2

12

12

RC453.01K_0402_1% RC453.01K_0402_1%

RC4610K_0402_5% RC4610K_0402_5%

RC4710K_0402_5% RC4710K_0402_5%

RC5010K_0402_5% RC5010K_0402_5%

RC5210K_0402_5% RC5210K_0402_5%

12

RC282.2K_0402_5% RC282.2K_0402_5%

12

RC302.2K_0402_5% RC302.2K_0402_5%

12

RC3410K_0402_5% RC3410K_0402_5%

RC362.2K_0402_5% RC362.2K_0402_5%

RC372.2K_0402_5% RC372.2K_0402_5%

12

RC381K_0402_5% RC381K_0402_5%

12

RC391K_0402_5% RC391K_0402_5%

+3.3V_ALW_PCH

For RF request(EMC)

Every pin need one gnd by itself

5

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(2/12)

MCP(2/12)

MCP(2/12)

LA-9431P

LA-9431P

LA-9431P

1

7 59Friday, May 17, 2013

7 59Friday, May 17, 2013

7 59Friday, May 17, 2013

0.3

0.3

0.3

5

HASWELL_MCP_E

D D

DDR_A_D[0..63]<18>

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AH63
AH62
AK63
AK62
AH61
AH60
AK61

AK60
AM63
AM62

AP63

AP62
AM61
AM60

AP61

AP60

AP58

AR58
AM57

AK57

AL58
AK58
AR57
AN57
AP55
AR55

AM54

AK54

AL55
AK55
AR54
AN54
AY58

AW58

AY56

AW56

AV58
AU58
AV56
AU56
AY54

AW54

AY52

AW52

AV54
AU54
AV52
AU52
AK40
AK42

AM43
AM45

AK45
AK43

AM40
AM42
AM46

AK46

AM49

AK49

AM48

AK48

AM51

AK51

UC1C

UC1C

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

HASWELL_MCP_E

DDR CHANNEL A

DDR CHANNEL A

4

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1

SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3

SA_CS#0
SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0
SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36

AU43
AW43
AY42
AY43

AP33
AR32

AP32

AY34
AW34
AU34

AU35
AV35
AY41

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

AP49
AR51
AP51

M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

M_CLK_DDR#0 <18>
M_CLK_DDR0 <18>
M_CLK_DDR#1 <18>
M_CLK_DDR1 <18>

DDR_CKE0_DIMMA <18>
DDR_CKE1_DIMMA <18>

DDR_CS0_DIMMA# <18>
DDR_CS1_DIMMA# <18>

DDR_A_RAS# <18>

DDR_A_WE# <18>

DDR_A_CAS# <18>

DDR_A_BS0 <18>
DDR_A_BS1 <18>
DDR_A_BS2 <18>

DDR_A_MA[0..15] <18>

DDR_A_DQS#[0..7] <18>

DDR_A_DQS[0..7] <18>

+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1

3

UC1D

AY31

AW31

AY29

AW29

AV31
AU31
AV29
AU29

AY27

AW27

AY25

AW25

AV27
AU27
AV25
AU25
AM29
AK29

AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25

AL25

AY23

AW23

AY21

AW21

AV23
AU23
AV21
AU21

AY19

AW19

AY17

AW17

AV19
AU19
AV17
AU17
AR21
AR22

AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18

AL18
AK20
AM20
AR18
AP18

UC1D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

DDR_B_D[0..63]<19>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

2

HASWELL_MCP_E

HASWELL_MCP_E

DDR CHANNEL B

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_CS#0
SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0
SB_BA1
SB_BA2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

AY49
AU50
AW49
AV50

AM32
AK32

AL32

AM35
AK35
AM33

AL35
AM36
AU49

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3

DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

1

M_CLK_DDR#2 <19>
M_CLK_DDR2 <19>
M_CLK_DDR#3 <19>
M_CLK_DDR3 <19>

DDR_CKE2_DIMMB <19>
DDR_CKE3_DIMMB <19>

DDR_CS2_DIMMB# <19>
DDR_CS3_DIMMB# <19>

DDR_B_RAS# <19>

DDR_B_WE# <19>

DDR_B_CAS# <19>

DDR_B_BS0 <19>
DDR_B_BS1 <19>
DDR_B_BS2 <19>

DDR_B_MA[0..15] <19>

DDR_B_DQS#[0..7] <19>

DDR_B_DQS[0..7] <19>

Rev1p2

3 OF 19

3 OF 19

A A

Rev1p2

4 OF 19

4 OF 19

Rev1p2

Rev1p2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(3/12)

MCP(3/12)

MCP(3/12)

LA-9431P

LA-9431P

LA-9431P

1

8 59Friday, May 17, 2013

8 59Friday, May 17, 2013

8 59Friday, May 17, 2013

0.3

0.3

0.3

+3.3V_ALW_PCH +RTC_CELL

+PCH_VCCDSW3_3

D D

+3.3V_RUN

+3.3V_ALW_PCH

RC136 1 0K_0402_5%RC136 10K_0402_5%

C C

PCH_JTAG_TDI<6>

H_PROCHOT#

1

@

@

CC149

CC149
22P_0402_50V8J

22P_0402_50V8J

2

ESD request, place near CPU side

B B

+1.05V_VCCST

1 2

RC113 49.9_0402_1%@ RC113 49.9_0402_1%@

1 2

RC114 62_0402_5%RC114 62_0402_5%

reference CRB

CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC115

5

1 2

1 2

1 2

ME_SUS_PWR_ACK
USB_OC3#
SIO_EXT_WAKE#

KB_DET#

PCH_RSMRST#_R

1 2

RC96 0_ 0402_5%

RC96 0_ 0402_5%

XDP@

XDP@

PCH_JTAG_TMS<6>

H_CATERR#

H_PROCHOT#

H_CPUPWRGD

10K_0402_5%

10K_0402_5%

100P_0402_50V8J

100P_0402_50V8J

12

RC115

RC115

SUS_STAT#/LPCPD#

PCH_PCIE_WAKE#

1

@

@

CC90

CC90

RC74 10K_0402_5%@RC74 10K _0402_5%@

RC71 10K_0402_5%RC71 10K_0402_5 %

RC81 8.2K_0402_5%@RC81 8.2K_0402_5%@

RP10

RP10

1 8
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

1 2

PCH_JTAG_TDO<6>

2

ME_RESET#

USB_OC3# <11>
SIO_EXT_WAKE# <12,36>
KB_DET# <12,38>

RC95 0_0402_5%XDP@ RC95 0_0402_5%XDP@

RC103 0_0402_5%

RC103 0_0402_5%

XDP@

XDP@

RC101 0_0402_5%

RC101 0_0402_5%

XDP@

XDP@

RUNPWROK<36,37>

ESD request

XDP_DBRESET#

RC76 8.2K_0402_5%@ RC76 8.2K_0402_5%@

PCH_DPWROK PCH_RSMRST#_R

ME_SUS_PWR_ACK_ R SUSA CK#_R

RESET_OUT# SYS_PWROK_R

SUSACK#<12,36>

SYS_PWROK<36,9>
RESET_OUT#<15,37>

1 2

PLTRST_NFC#<20>
PLTRST_USH#<29>
PLTRST_MMI#<30>
PLTRST_LAN#<28>

PLTRST_VMM2320#< 21>

XDP@ CC41

XDP@

0.1U_0402_25V6

0.1U_0402_25V6

1 2

1 2

1 2

RC300 0 _0402_5%@RC300 0_0402_5%@

1 2

RC89 0_0402_5%@ RC89 0_0402_5%@

1 2

RC90 0_0402_5%@ RC90 0_0402_5%@

1 2

RC91 0_0402_5%@ RC91 0_0402_5%@

1 2

RC92 0_0402_5%@ RC92 0_0402_5%@

PCH_RSMRST#_Q<38>

ME_SUS_PWR_ACK<37>

+3.3V_RUN

CC41

12

RUNPWROK

RUNPWROK

RUNPWROK

TRST#_XDP CPU_X DP_TRST#

RUNPWROK

PCH_JTAG_TRST#<6>

PCH_JTAG_JTAGX<6>

UC6

UC6

XDP@

XDP@

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126BQ_DHVQFN14_2P5X3

74CBTLV3126BQ_DHVQFN14_2P5X3

reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0

PCH_JTAG_TDO TDI_XDP_R

PCH_JTAG_TCK

H_PROCHOT#<37,46,47,48>

DDR3 COMPENSATION SIGNALS

A A

CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil

12

SM_RCOMP0

RC125200_0402_1% RC125200_0402_1%

12

SM_RCOMP1

RC129121_ 0402_1% RC129121_0402_1%

12

SM_RCOMP2

RC133100_0402_1% RC133100_0402_1%

5

4

RC72 0_0402_5%@RC72 0_0402_5%@

1

2

12

ME_RESET#

1 2

RC79 0_0402_5%@ RC79 0_0402_5%@

1 2

RC82 0_0402_5%@ RC82 0_0402_5%@

1 2

RC84 0_0402_5%@ RC84 0_0402_5%@

1 2

RC86 0_0402_5%@ RC86 0_0402_5%@

1 2

RC87 0_0402_5%@ RC87 0_0402_5%@

1 2

RC88 0_0402_5%@ RC88 0_0402_5%@

1 2

RC93 0_0402_5%@ RC93 0_0402_5%@

1 2

RC94 0_0402_5%@ RC94 0_0402_5%@

SIO_PWRBTN#<37,9>

AC_PRESENT<12,37>
PCH_BATLOW#<12>
SIO_SLP_S0#<37>
SIO_SLP_WLAN#<36>

GND PAD

12

CPU_XDP_TRST#

RC1350_0402_5% @RC1350_0 402_5% @

12

CPU_XDP_TCLK

RC970_0402_5% @RC970_0402_5% @

12

TDO_XDP

RC1230_0402_5% @RC1230_0402_5% @

12

RC1040_0402_5% @RC1040_0402_5% @

12

CPU_XDP_TCLK

RC1240_0402_5% @RC1240_0402_5% @

CPU_DETECT#<36>

PECI_EC<37>

1 2

RC117 5 6_0402_5%RC117 56_0402_5%

DDR3_DRAMRST#_CPU<18>

DDR_PG_CTRL<18>

4

1 2

+3.3V_RUN

5

0.1U_0402_25V6

0.1U_0402_25V6

P

B

O

A

G

74AHC1G09GW_TSSOP5~D

74AHC1G09GW_TSSOP5~D

3

3

1B

6

2B

8

3B

11

4B

7

GND

15

CPU_DETECT#
H_CATERR#
PECI_EC

H_PROCHOT#_R

H_CPUPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

CC8

@CC8

@

1 2

4

UC2

@UC2

@

SYS_RESET#
SYS_PWROK_R
PCH_PWROK
PM_APWROK_R
PCH_PLTRST#

PCH_RSMRST#_R

ME_SUS_PWR_ACK_ R

SIO_PWRBTN#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#

CPU_XDP_TDOTDO_XDPPCH_JTAG_TDO

CPU_XDP_TDITDI_XDP TDI_XDP_R

CPU_XDP_TMSTMS_XDP

SUSACK#_R

D61

K61

N62

K63

C61

AU60
AV60
AU61
AV15
AV61

SYS_RESET#

UC1H

UC1H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

UC1B

UC1B

PROC_DETECT
CATERR
PECI

PROCHOT

PROCPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

THERMAL

THERMAL

MISC

MISC

PWR

PWR

DDR3

DDR3

PCH_PLTRST#

SYSTEM POWER MANAGEMENT

SYSTEM POWER MANAGEMENT

H_VCCST_PWRGD<15>

DDR_XDP_WAN_SMBDAT<18,19,31,7>

DDR_XDP_WAN_SMBCLK<18,19,31,7>

HASWELL_MCP_E

HASWELL_MCP_E

2 OF 19

2 OF 19

1

2

HASWELL_MCP_E

HASWELL_MCP_E

8 OF 19

8 OF 19

SIO_PWRBTN#<37,9>

CPU_PWR_DEBUG#<15>

JTAG

JTAG

PCH_JTAG_TCK<6>

3

+3.3V_RUN

CC9

@CC9

@

1 2

0.1U_0402_25V6

0.1U_0402_25V6

5

P

B

4

PCH_PLTRST#_EC

O

A

G

UC3

UC3

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

3

SUS_STAT/GPIO61

+1.05V_RUN

Place near JXDP1

RC5 need to close to JCPU1

1 2

RC105 1 K_0402_5%

RC105 1 K_0402_5%

XDP@

XDP@

H_CPUPWRGD

SYS_PWROK<36,9>

PROC_TCK
PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

3

2

+3.3V_ALW2

CC82

@CC82

@

PCH_PLTRST#_EC <25,29,31,36,3 7>

SIO_SLP_A#

PM_APWROK

PM_APWROK<37>

RC144 0 _0402_5%@RC144 0_0402_5%@

AW7

WAKE

SLP_A

Rev1p2

Rev1p2

0.1U_0402_25V6

0.1U_0402_25V6

1

@

@

2

1 2
1 2

1 2
1 2

1 2
1 2
1 2

CPU_XDP_PRDY#
CPU_XDP_PREQ#
CPU_XDP_TCLK
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TDO

XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R

AV5
AJ5

V5
AG4
AE6
AP5

AJ6
AT4
AL5
AP4
AJ7

CC11

CC11

DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#

CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#

SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
SIO_SLP_LAN#

PCH_DPWROK < 36>
PCH_PCIE_WAKE# <37>

CLKRUN# <10,29,36,37>

T10 PAD~D@T10 PAD~D@

SIO_SLP_S5# <37>

T11 PAD~D@T11 PAD~D@

T12 PAD~D

T12 PAD~D

SIO_SLP_S4# <36,39,43>
SIO_SLP_S3# <36,39,43>
SIO_SLP_A# <36,39,44>
SIO_SLP_SUS# <36>
SIO_SLP_LAN# <28,36>

+1.05V_RUN

CPU_XDP_PREQ#
CPU_XDP_PRDY#

CFG0

CFG0<13>

CFG1

CFG1<13>

CFG2 CFG10

CFG2<13>
CFG3<13>

XDP_OBS0_R
XDP_OBS1_R

CFG4

CFG4<13>

CFG5

CFG5<13>

CFG6

CFG6<13>

CFG7

CFG7<13>

H_VCCST_PWRGD_XDP
CFD_PWRBTN#_XDP

CPU_PWR_DEBUG#_R PCH_PLTRST#_ECPCH_PLTRST#_EC
SYS_PWROK_XDP

DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
PCH_JTAG_TCK_R

CPU_XDP_TCLK

+3.3V_ALW_PCH

T122PAD~D @T122PAD~D @
T126PAD~D @T126PAD~D @
T129PAD~D @T129PAD~D @
T130PAD~D @T130PAD~D @
T131PAD~D @T131PAD~D @
T132PAD~D @T132PAD~D @

DSWVRMEN

DPWROK

CLKRUN/GPIO32

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4
SLP_S3

SLP_SUS
SLP_LAN

0.1U_0402_25V6

0.1U_0402_25V6

1

@

@

CC10

CC10

2

RC106 1 K_0402_5%@RC106 1K_040 2_5%@
RC107 0 _0402_5%@RC107 0_0402_5%@

RC108 0 _0402_5%@RC108 0_0402_5%@
RC110 0 _0402_5%@RC110 0_0402_5%@

RC111 0 _0402_5%@RC111 0_0402_5%@
RC112 0 _0402_5%@RC112 0_0402_5%@
RC142 0 _0402_5%@RC142 0_0402_5%@

J62

PRDY

K62

PREQ

E60
E61
E59
F63
F62

J60
H60
H61
H62
K59
H63
K60
J61

Rev1p2

Rev1p2

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

0.1U_0402_25V6

0.1U_0402_25V6

5

1

P

B

O

2

A

G

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

3

1 2

@

@

JXDP1

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

XDP@

XDP@

RC102

RC102
1K_0402_5%

1K_0402_5%

1 2

SYS_PWROK_XDP

1

CC48

@CC48

@

0.1U_0402_25V6

0.1U_0402_25V6

2

Place near JXDP1.47

2

1 2

4

PM_APWROK_R

UC7

UC7

SAMTE_BSH-030-01-L-D-A CONN@

SAMTE_BSH-030-01-L-D-A CONN@

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TD0

TRST#

TDI

TMS

GND17

Place near JXDP1.48

XDP_DBRESET#

1

330K_0402_1%

330K_0402_1%

RC73

RC73

1 2

DSWODVREN

330K_0402_1%

330K_0402_1%

@RC78

@

RC78

1 2

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT)

LOW = DISABLED

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

+1.05V_RUN

1

2

+3.3V_ALW_PCH

+PCH_VCCDSW3_3

+PCH_VCCDSW3_3

CFG17
CFG16

CFG8
CFG9

CFG11CFG3

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

XDP_RST#_R
XDP_DBRESET#

TDO_XDP
TRST#_XDP
TDI_XDP
TMS_XDP

CFG3_R

CC68

XDP@ CC68

XDP@

0.1U_0402_25V6

0.1U_0402_25V6

PCH_RTCRST#< 6>

POWER_SW #_MB<37,40>

SIO_SLP_S3#

SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#

PCH_RTCRST#

POWER_SW #_MB

SYS_RESET#

SIO_SLP_S0#

CFG17 <13>
CFG16 <13>

CFG8 <13>
CFG9 <13>

CFG10 <13>
CFG11 <13>

CFG19 <13>
CFG18 <13>

CFG12 <13>
CFG13 <13>

CFG14 <13>
CFG15 <13>

RC109 1K_0402_5%

RC109 1K_0402_5%

XDP@

XDP@

1 2

RC99 1K_0402_5%

RC99 1K_0402_5%

XDP@

XDP@

TDO_XDP

CFG3

RC280 51_0402_1%@ RC280 51_0402_1%@

PU/PD for JTAG signals

XDP_DBRESET#

CPU_XDP_TMS

CPU_XDP_TDI

CPU_XDP_PREQ#

CPU_XDP_TDO

CPU_XDP_TCLK

CPU_XDP_TRST#

RC116 1K_0402_5%RC116 1K _0402_5%

RC118 51_0402_1%@ RC118 51_0402_1%@

RC119 51_0402_1%@ RC119 51_0402_1%@

RC120 51_0402_1%@ RC120 51_0402_1%@

RC122 51_0402_1%RC122 51_0402_1%

RC127 51_0402_1%RC127 51_0402_1%

RC131 51_0402_1%@ RC131 51_0402_1%@

12

12

12

12

12

12

12

12

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(4/12)

MCP(4/12)

MCP(4/12)

LA-9431P

LA-9431P

LA-9431P

1

JAPS1

CONN@JAPS1

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

GND

20

GND

ACES_50506-01841-P01

ACES_50506-01841-P01

+1.05V_RUN

+3.3V_RUN

+1.05V_RUN

9 59Friday, May 17, 2013

9 59Friday, May 17, 2013

9 59Friday, May 17, 2013

0.3

0.3

0.3

5

4

HASWELL_MCP_E

UC1A

UC1A

HASWELL_MCP_E

3

2

1

DDI1_LANE_N0<23>
DDI1_LANE_P0<23>
DDI1_LANE_N1<23>
DDI1_LANE_P1<23>
DDI1_LANE_N2<23>
DDI1_LANE_P2<23>
DDI1_LANE_N3<23>

D D

+3.3V_RUN

C C

1 2

RC137 10K_0402_5%RC137 10K_0402_5%

1 2

RC140 10K_0402_5%RC140 10K_0402_5%

1 2

RC202 10K_0402_5%RC202 10K_0402_5%

1 2

RC152 100K_0402_5%@RC152 100K_0402_5%@

RC154 1K_0402_5%@RC154 1K_0402_5%@

+3.3V_RUN

RP6

RP6

1 8
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

12

CONTACTLESS_DET#

TOUCHPAD_INTR#

TOUCH_RST_N_GYRO_INT1

ENVDD_PCH

CODEC_IRQ

CLKRUN#
LANCLK_REQ#
HDD_FALL_INT
PCH_GPIO36

CLKRUN# <29,36,37,9>
LANCLK_REQ# <28,7>

PCH_GPIO36 <6>

DDI1_LANE_P3<23>

DDI2_LANE_N0<27>
DDI2_LANE_P0<27>

DDI2_LANE_N1<27>

DDI2_LANE_P1<27>

DDI2_LANE_N2<27>

DDI2_LANE_P2<27>

DDI2_LANE_N3<27>

DDI2_LANE_P3<27>

CONTACTLESS_DET#<29>

DGPU_PWROK<7>

PIRQ#_TPM<12>

DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3

DDI2_LANE_N0
DDI2_LANE_P0
DDI2_LANE_N1
DDI2_LANE_P1
DDI2_LANE_N2
DDI2_LANE_P2
DDI2_LANE_N3
DDI2_LANE_P3

EDP_BIA_PWM<22>
PANEL_BKLEN<22>
ENVDD_PCH<22,36>

T13 PAD~D@ T13 PAD~D@

TOUCHPAD_INTR#
TOUCH_RST_N_GYRO_INT1

CODEC_IRQ

EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH

DGPU_PWROK

PIRQ#_TPM

HDD_FALL_INT

C54
C55
B58
C58
B55
A55
A57
B57

C51
C50
C53
B54
C49
B50
A53
B53

AD4

B8
A9
C6

U6
P4
N4
N2

U7
L1
L3
R5
L4

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

UC1I

UC1I

EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN

PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME

GPIO55
GPIO52
GPIO54
GPIO51
GPIO53

DDI EDP

DDI EDP

1 OF 19

1 OF 19

HASWELL_MCP_E

HASWELL_MCP_E

eDP SIDEBAND

eDP SIDEBAND

GPIO

GPIO

9 OF 19

9 OF 19

DISPLAY

DISPLAY

EDP_RCOMP

EDP_DISP_UTIL

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

reference PDG 0.9

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP_AUXN
EDP_AUXP

Rev1p2

Rev1p2

DDPB_HPD
DDPC_HPD

EDP_HPD

Rev1p2

Rev1p2

C45

EDP_CPU_LANE_N0

B46

EDP_CPU_LANE_P0

A47

EDP_CPU_LANE_N1

B47

EDP_CPU_LANE_P1

C47
C46
A49
B49

A45

EDP_CPU_AUX#

B45

EDP_CPU_AUX

D20

EDP_COMP

A43

B9

CPU_DPB_CTRLCLK

C9

CPU_DPB_CTRLDAT

D9

CPU_DPC_CTRLCLK

D11

CPU_DPC_CTRLDAT

C5

CPU_DPB_AUX#

B6

CPU_DPC_AUX#

B5

CPU_DPB_AUX

A6

CPU_DPC_AUX

C8

DPB_HPD

A8

DPC_HPD

D6

100K_0402_5%

100K_0402_5%

12

EDP_CPU_LANE_N0 <22>
EDP_CPU_LANE_P0 <22>
EDP_CPU_LANE_N1 <22>
EDP_CPU_LANE_P1 <22>

EDP_CPU_AUX# <2 2>
EDP_CPU_AUX <22 >

CPU_DPB_CTRLCLK <23>

CPU_DPB_CTRLDAT <23>

CPU_DPC_CTRLCLK <27>

CPU_DPC_CTRLDAT <27>

CPU_DPC_AUX# <27>

CPU_DPC_AUX <27>

DPB_HPD <23>
DPC_HPD <27>
EDP_CPU_HPD <22>

0.1U_0402_25V6

0.1U_0402_25V6

@

@

CC450

CC450

RC158

RC158

1

2

ESD solution for black screen issue

Intel WW18 Strapping option

Intel WW18 Strapping option

COMPENSATION PU FOR eDP

EDP_COMP

CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.

follow intel feedback

+VCCIOA_OUT

12

CPU_DPB_CTRLCLK

CPU_DPB_CTRLDAT

CPU_DPC_CTRLCLK

CPU_DPC_CTRLDAT

CPU_DPB_AUX#

CPU_DPC_AUX#

DPC_HPD

CPU_DPB_AUX

CPU_DPC_AUX

RC13424.9_0402_1% RC13424.9_0402_1%

+3.3V_RUN

12

RC1392.2K_0402_5% RC1392.2K_0402_5%

12

RC1412.2K_0402_5% RC1412.2K_0402_5%

12

RC1432.2K_0402_5% RC1432.2K_0402_5%

12

RC1452.2K_0402_5% RC1452.2K_0402_5%

12

RC147100K_0402_5% RC147100K_0402_5%

12

RC149100K_0402_5% RC149100K_0402_5%

12

RC151100K_0402_5% RC151100K_0402_5%

12

RC153100K_0402_5% RC153100K_0402_5%

12

RC155100K_0402_5% RC155100K_0402_5%

B B

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(5/12)

MCP(5/12)

MCP(5/12)

LA-9431P

LA-9431P

LA-9431P

10 59Friday, May 17, 2013

10 59Friday, May 17, 2013

10 59Friday, May 17, 2013

1

0.3

0.3

0.3

5

D D

PCIE_PRX_MMITX_N5<30>

MMI -->

C C

10/100/1G LAN --->

WLAN (Mini Card 2)--->

PCIE_PRX_MMITX_P5<30>

PCIE_PTX_MMIRX_N5<30>
PCIE_PTX_MMIRX_P5<30>

PCIE_PRX_GLANTX_N3<28>
PCIE_PRX_GLANTX_P3<28>

PCIE_PTX_GLANRX_N3<28>
PCIE_PTX_GLANRX_P3<28>

PCIE_PRX_WLANTX_ N4<31>
PCIE_PRX_WLANTX_ P4<31>

PCIE_PTX_WLANRX_ N4<31>
PCIE_PTX_WLANRX_ P4<31>

PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3

PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3

PCIE_PRX_WLANTX_ N4
PCIE_PRX_WLANTX_ P4

PCIE_PTX_WLANRX_ N4
PCIE_PTX_WLANRX_ P4

Ext USB Port 2 <----

B B

+PCH_AUSB3PLL

reference CRB 3.01K 1%

RC161 3.01K_0402_1%RC 161 3.01K_0402_1%
RC163 0_0402_5%@ RC163 0_0402_5%@

1 2
1 2

T16 PAD~D@T16 PAD~D@
T17 PAD~D@T17 PAD~D@

4

PCIE_PRX_MMITX_N5
PCIE_PRX_MMITX_P5

PCIE_PTX_MMIRX_N5
PCIE_PTX_MMIRX_P5

USB3RN3<32>
USB3RP3<3 2>

USB3TN3<32>
USB3TP3<32>

PCH_PCIE_RCOMP
PCH_PCIE_IREF

F10

E10

C23
C22

F8

E8

B23
A23

H10
G10

B21
C21

E6

F6

B22
A21

G11

F11

C29
B30

F13

G13

B29
A29

G17

F17

C30
C31

F15

G15

B31
A31

E15
E13
A27
B27

UC1K

UC1K

PERN5_L0
PERP5_L0

PETN5_L0
PETP5_L0

PERN5_L1
PERP5_L1

PETN5_L1
PETP5_L1

PERN5_L2
PERP5_L2

PETN5_L2
PETP5_L2

PERN5_L3
PERP5_L3

PETN5_L3
PETP5_L3

PERN3
PERP3

PETN3
PETP3

PERN4
PERP4

PETN4
PETP4

PERN1/USB3RN3
PERP1/USB3RP3

PETN1/USB3TN3
PETP1/USB3TP3

PERN2/USB3RN4
PERP2/USB3RP4

PETN2/USB3TN4
PETP2/USB3TP4

RSVD
RSVD
PCIE_RCOMP
PCIE_IREF

PCIe

PCIe

HASWELL_MCP_E

HASWELL_MCP_E

11 OF 19

11 OF 19

3

AN8
AM8

AR7
AT7

AR8
AP8

AR10
AT10

AM15
AL15

AM13
AN13

AP11
AN11

AR13
AP13

G20
H20

C33
B34

E18
F18

B33
A33

AJ10
AJ11
AN10
AM10

AL3
AT1
AH2
AV3

USBP0­USBP0+

USBP1­USBP1+

USBP2­USBP2+

USBP3­USBP3+

USBP4­USBP4+

USBP5­USBP5+

USBP6­USBP6+

USBP7­USBP7+

USBRBIAS

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

USB3RN1

USB

USB

USB3RP1

USB3TN1
USB3TP1

USB3RN2
USB3RP2

USB3TN2
USB3TP2

USBRBIAS
USBRBIAS

RSVD
RSVD

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

Rev1p2

Rev1p2

USBP0- <33>
USBP0+ <33>

USBP1- <35>
USBP1+ <35>

USBP2- <31>
USBP2+ <31>

USBP3- <22>
USBP3+ <22>

USBP4- <29>
USBP4+ <29>

USBP5- <32>
USBP5+ <32>

USBP6- <31>
USBP6+ <31>

USBP7- <22>
USBP7+ <22>

USB3RN1 <35>

USB3RP1 <35>

USB3TN1 <35>

USB3TP1 <35>

USB3RN2 <33>

USB3RP2 <33>

USB3TN2 <33>

USB3TP2 <33>

T14PAD~D @T14PAD~D @
T15PAD~D @T15PAD~D @

USB_OC0# <33>
USB_OC1# <35>
USB_OC2# <33>

USB_OC3# <9>

2

----->Ext Port 1 and DOCK2 (USB SW)

----->Ext Port 2 IO/B

----->WLAN/BT

----->Camera

----->USH

----->Ext Port 3 and DOCK1(USB SW)

----->WWAN

----->Touch

----->Ext USB3 Port 1

USBRBIAS

----->Ext USB3 Port 3 IO/B

CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.

USB_OC1#

22.6_0402_1%

22.6_0402_1%

12

RC159

RC159

1 2

1

+3.3V_ALW_PCH

RC16610K_0402_5% RC16610K_0402_5%

+3.3V_ALW_PCH

RP5

RP5

USB_OC2#
USB_OC0#

PCH_SMB_ALERT#<7>

MEDIACARD_PWR EN<12,30>

A A

PCH_SMB_ALERT#
MEDIACARD_PWR EN

18
27
36
45

10K_8P4R_5%

10K_8P4R_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(6/12)

MCP(6/12)

MCP(6/12)

LA-9431P

LA-9431P

LA-9431P

11 59Friday, May 17, 2013

11 59Friday, May 17, 2013

11 59Friday, May 17, 2013

1

0.3

0.3

0.3

5

LAN_WAKE#<28,37>

+3.3V_RUN

D D

C C

B B

RC170 100K_0402_5%RC170 100K_0402_5 %

RC199 100K_0402_5%RC199 100K_0402_5 %

+PCH_VCCDSW3 _3

RC197 10K_0402_5%RC197 10K_0402_5%

RC206 10K_0402_5%RC206 10K_0402_5%

+3.3V_ALW_PCH

RC200 10K_0402_5%RC200 10K_0402_5%

RC205 10K_0402_5%RC205 10K_0402_5%

RC211 100K_0402_5%RC211 100K_0402_5 %

RC210 100K_0402_5%RC210 100K_0402_5 %

RC169 10K_0402_5%

RC169 10K_0402_5%

@

@

RC215 10K_0402_5%RC215 10K_0402_5%

+3.3V_RUN +3.3V_RUN

1K_0402_5%

1K_0402_5%

12

@RC283

@

RC283

PCH_GPIO66

1K_0402_5%

1K_0402_5%

12

@RC288

@

RC288

1 2

RC301 0_0402_5%@RC301 0_0402_5%@

12

12

SIO_EXT_SCI#

12

PM_LANPHY_ENABLE

12

EC_WAKE#

suppoer DSW mode

12

PCH_GPIO44

12

MEDIACARD_IRQ#

12

12

12

12

GPIO66 GPIO86

TOP-BLOCK SWAP OVERRIDE

Low depop RC288 (DEFAULT) :Enable
High pop RC288:Diable

503118_503118_LPT_LP_PCH_EDS_Rev1_0

MPHYP_PWR_EN

3.3V_CAM_EN#

NFC_IRQ

MPHYP_PWR_EN

PCH_AUDIO_EN

EC_WAKE#

+3.3V_ALW_PCH

10K_0402_5%

10K_0402_5%

12

RC218

RC218

1K_0402_5%

1K_0402_5%

12

@RC287

@

RC287

@

@

BBS_BIT

RP7

RP7

1 8
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

BOOT BIOS STRAP BIT BBS

HIGH
LOW(DEFAULT)

LPC
SPI

PM_LANPHY_ENABLE<28>

MEDIACARD_RST#<30>
MEDIACARD_PWR EN<11,30>

TOUCH_PANEL_INTR#<22>

SIO_EXT_WAKE#<36,9>

LAN_RST#<28>

T139 PAD~D@ T139 PAD~D@

EC_WAKE#<37>
PCH_NFC_RST<20>
NFC_IRQ<20>

NFC_DET#<20>

MEDIACARD_IRQ#<30>

T140 PAD~D@ T140 PAD~D@
T141 PAD~D@ T141 PAD~D@

MPHYP_PWR_EN<39>

KB_DET#<38,9>

T138 PAD~D@ T138 PAD~D@

3.3V_CAM_EN#<22>
SIO_EXT_SMI#<37>

T137 PAD~D@ T137 PAD~D@

mSATA_DEVSLP<31>

HDD_DEVSLP<25>

SIO_EXT_SCI#<37>

MEDIACARD_RST#
PCH_GPIO46
SUSACK#
SIO_EXT_SMI#

4

PCH_AUDIO_EN
SIO_EXT_WAKE#
PM_LANPHY_ENABLE
PCH_GPIO15

PCH_GPIO17

EC_WAKE#

NFC_IRQ

MEDIACARD_RST#
MEDIACARD_PWR EN
SLATE_MODE_R
NFC_DET#
PCH_GPIO44

PCH_GPIO48
PCH_GPIO49
TOUCH_PANEL_INTR#
MPHYP_PWR_EN
KB_DET#
PCH_GPIO14

3.3V_CAM_EN#
SIO_EXT_SMI#

PCH_GPIO46

PCH_GPIO9
PCH_GPIO10 I2C1_SDA_TCH_PAD

SIO_EXT_SCI#
SPKR

SPKR<26>

+3.3V_ALW_PCH

1K_0402_5%

1K_0402_5%

12

RC190

RC190

PCH_GPIO15

GPIO15 GPIO81

TLS CONFIDENTIALITY

HIGH
LOW(DEFAULT)

P1
AU2
AM7
AD6

Y1

T3
AD5

AN5
AD7
AN3

AG6
AP1
AL4
AT5
AK4
AB6

U4

Y3

P3

Y2

AT3
AH4
AM4
AG5
AG3

AM3
AM2

P2
C4
L2
N5
V2

SUSACK# <36,9>

UC1J

UC1J

BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26

GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46

GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81

+3.3V_RUN

1K_0402_5%

1K_0402_5%

12

GPIO

GPIO

@RC222

@

RC222

SPKR

NO REBOOT STRAP

HIGH
LOW(DEFAULT)

HASWELL_MCP_E

HASWELL_MCP_E

10 OF 19

10 OF 19

3

CPU/

CPU/
MISC

MISC

GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86

GSPI1_MISO/GPIO89

UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93

LPIO

LPIO

UART0_CTS/GPIO94

TOUCH_PANEL_INTR#

THERMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD
RSVD

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88

GSPI_MOSI/GPIO90

UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

Rev1p2

Rev1p2

I2C1_SDA_TCH_PAD

I2C1_SCL_TCH_PAD

D60
V4
T4
AW15
AF20
AB21

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

+3.3V_RUN

12

12

H_THERMTRIP#

H_THERMTRIP#_R
SIO_RCIN#
IRQ_SERIRQ
PCH_OPI_COMP

PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
BBS_BIT
PCH_GPIO87

3.3V_TP_EN

CPPE#
CPUSB#

LCD_CBL_DET#

I2C0_SDA
I2C0_SCL

I2C1_SCL_TCH_PAD
USH_DET#
CAM_MIC_CBL_DET#
PCH_GPIO66
TPM_ID0
TPM_ID1
SLP_ME_CSW_DE V#

RC174 0_0402_5%@ RC174 0_0402_5%@

RC176 0_0402_5%@ RC176 0_0402_5%@

RC181

RC181
10K_0402_5%

10K_0402_5%

RC180

@R C180

@

10K_0402_5%

10K_0402_5%

non use GPIO:

2

100P_0402_50V8J

100P_0402_50V8J

1

@

@

CC91

CC91

2

ESD request

RC172 0_0402_5%@ RC172 0_0402_5%@

SIO_RCIN# <37>

IRQ_SERIRQ <29,36,37>

T18 PAD~D@T18 PAD~D@
T19 PAD~D@T19 PAD~D@

3.3V_TS_EN <22>

3.3V_HDD_EN <31>
CPPE# <31>
CPUSB# <31>

LCD_CBL_DET# <22>

USH_DET# <29>
CAM_MIC_CBL_DET# <22>

SLP_ME_CSW_DE V# <36>

12

PCH_GPIO83

12

12

I2C1_SDA_TCH_PAD <38>

I2C1_SCL_TCH_PAD <38>

H_THERMTRIP# <37>

PCH_BATLOW#<9>
AC_PRESENT<37,9>

1 2

I2C1_SDA_VMM <21>

I2C1_SCL_VMM <21>

PIRQ#_TPM<10>

RC292100_0402_5% 7@RC292100_0402_5% 7@

PIRQ#_TPM
PCH_GPIO83
SIO_RCIN#

3.3V_TS_EN
PCH_GPIO84
PCH_GPIO85

3.3V_TP_EN

PCH_GPIO9
SLATE_MODE_R
PCH_BATLOW#
AC_PRESENT

IRQ_SERIRQ

USH_DET#

LCD_CBL_DET#

CPPE#

CAM_MIC_CBL_DET#

CPUSB#

I2C1_SDA_TCH_PAD

I2C1_SCL_TCH_PAD

TPM_ID0

TPM_ID1

SLP_ME_CSW_DE V#

3.3V_HDD_EN

I2C0_SDA

I2C0_SCL

PCH_GPIO87

RP9

RP9

10K_8P4R_5%

10K_8P4R_5%

reference PDG0.9

H_THERMTRIP#

PCH_OPI_COMP

1

10K_8P4R_5%

10K_8P4R_5%

10K_8P4R_5%

10K_8P4R_5%

+3.3V_ALW_PCH

18
27
36
45

1 2

1 2

RP2

RP2

RP8

RP8

12

R241K_0402_5% R241K_0402_5%

12

12

12

12

12

12

12

12

12

12

12

12

12

12

+3.3V_RUN

18
27
36
45

18
27
36
45

+PCH_VCCDSW3 _3

+1.05V_VCCST

RC16849.9_0402_1% RC16849.9_0402_1%

+3.3V_RUN

RC17810K_ 0402_5% RC17810K_0402 _5%

RC28210K_ 0402_5% RC28210K_0402 _5%

RC18910K_ 0402_5% RC18910K_0402 _5%

RC185100K_0402_5% RC185100K_0402_5%

RC19310K_ 0402_5% RC19310K_0402 _5%

RC191100K_0402_5% RC191100K_0402_5%

RC2012.2K_0402 _5% RC2012.2K_0402_5%

RC2032.2K_0402 _5% RC2032.2K_0402_5%

RC28410K_ 0402_5% RC28410K_0402 _5%

RC28520K_0402_5% RC28520K_0402_5%

RC28910K_ 0402_5% RC28910K_0402 _5%

RC29510K_ 0402_5% RC29510K_0402 _5%

RC2042.2K_0402 _5% RC2042.2K_0402_5%

RC2082.2K_0402 _5% RC2082.2K_0402_5%

RC21610K_0402_5% RC21610K_0402_5%

GPIO0 GPIO3 GPIO10 GPIO14
GPIO17 GPIO21 GPIO22 GPIO24
GPIO36 GPIO38 GPIO48 GPIO49
GPIO51 GPIO54 GPIO59 GPIO60

A A

GPIO66 GPIO70 GPIO73 GPIO79
GPIO87 GPIO93 GPIO94

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(7/12)

MCP(7/12)

MCP(7/12)

LA-9431P

LA-9431P

LA-9431P

12 59Friday, May 17, 2013

12 59Friday, May 17, 2013

12 59Friday, May 17, 2013

1

0.3

0.3

0.3

5

4

3

2

1

CFG STRAPS for CPU

D D

UC1S

UC1S

AC60

12

CFG_RCOMP

TDI_IREF

CFG0
CFG1

CFG3
CFG4

CFG8
CFG9
CFG10

CFG_RCOMP

TDI_IREF

AC62
AC63
AA63
AA60

AA62

AA61

Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60

U63

U62

V63

A5

E1
D1

J20
H18
B12

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG18
CFG17
CFG19

CFG_RCOMP

RSVD

RSVD
RSVD
RSVD
RSVD
TD_IREF

CFG0<9>
CFG1<9>
CFG2<9>
CFG3<9>
CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>
CFG8<9>
CFG9<9>

C C

B B

CFG10<9>
CFG11<9>
CFG12<9>
CFG13<9>
CFG14<9>
CFG15<9>

CFG16<9>
CFG18<9>
CFG17<9>
CFG19<9>

T33 PAD~D@T33 PAD ~D@

T35 PAD~D@T35 PAD ~D@
T37 PAD~D@T37 PAD ~D@
T38 PAD~D@T38 PAD ~D@
T39 PAD~D@T39 PAD ~D@

RC235 49.9_0402_1%RC235 49.9_0402_1%

1 2

RC236 8.2K_0402_ 1%RC236 8.2K_0402_1 %

HASWELL_MCP_E

HASWELL_MCP_E

RESERVED

RESERVED

19 OF 19

19 OF 19

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD

RSVD_TP
RSVD_TP

RSVD_TP

RSVD

RSVD
RSVD

PROC_OPI_RCOMP

RSVD
RSVD

VSS
VSS

RSVD
RSVD

Rev1p2

Rev1p2

AV63
AU63

C63
C62
B43

A51
B51

L60

N60

W23
Y22
AY15

PROC_OPI_RCOMP

AV62
D58

P22
N21

P20
R20

PROC_OPI_RCOMP

1 2

RC23749.9_0402_1% RC23749.9_0402_1%

T20PAD~D @T20PAD~D @
T21PAD~D @T21PAD~D @

T22PAD~D @T22PAD~D @
T23PAD~D @T23PAD~D @
T24PAD~D @T24PAD~D @

T25PAD~D @T25PAD~D @
T26PAD~D @T26PAD~D @

T27PAD~D @T27PAD~D @

T28PAD~D @T28PAD~D @

T29PAD~D @T29PAD~D @
T30PAD~D @T30PAD~ D @

T31PAD~D @T31PAD~ D @
T32PAD~D @T32PAD~ D @

T34PAD~D @T34PAD~ D @
T36PAD~D @T36PAD~ D @

EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE

CFG0

1:(Default) Normal Operation; No stall
0:Lane Reversed

PCH/PCH LESS MODE SELECTION

CFG1

1:(Default) Normal Operation
0:Lane Reversed

CFG0

CFG1

1K_0402_1%

1K_0402_1%

12

@RC232

@

RC232

1K_0402_1%

1K_0402_1%

12

@RC233

@

RC233

CFG10

CFG9

1K_0402_1%

1K_0402_1%

12

@RC239

@

RC239

1K_0402_1%

1K_0402_1%

12

@RC240

@

RC240

CFG8

1K_0402_1%

1K_0402_1%

12

@RC241

@

RC241

CFG4

1K_0402_1%

1K_0402_1%

12

RC238

RC238

Display Port Presence Strap

SAFE MODE BOOT

1: POWER FEATURES ACTIVATED DURING
RESET

A A

CFG10

0: POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED

NO SVID PROTOCOL CAPABLE VR CONNECTED

1: VRS support SVID protocol are present
0:No VR support SVID is present

CFG9

The chip will not generate(OR Respond to)
SVID activity

ALLOW THE USE OF NOA ON LOCKED UNITS

1: Enable(Default): Noa will be disable in
locked units and enable in un-locked units

CFG8

0: Enable Noa will be available pegardless of
the locking of the unit

CFG4

1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(8/12)

MCP(8/12)

MCP(8/12)

LA-9431P

LA-9431P

LA-9431P

13 59Friday, May 17, 2013

13 59Friday, May 17, 2013

13 59Friday, May 17, 2013

1

0.3

0.3

0.3

5

4

3

2

1

D D

UC1Q

UC1Q

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61

DC_TEST_B62_B63

DC_TEST_C1_C2

C C

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

Package Daisy Chain:

HASWELL_MCP_E

HASWELL_MCP_E

17 OF 19

17 OF 19

3

1

12

RC2540_0402_5% @RC2540_ 0402_5% @

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

Rev1p2

Rev1p2

12

RC2690_0402_5% @RC2690_ 0402_5% @

A3

DC_TEST_A3_B3

A4

DC_TEST_A4

A60

DC_TEST_A60

A61

DC_TEST_A61_B61

A62

DC_TEST_A62

AV1

DC_TEST_AV1

AW1

DC_TEST_AW1

AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

DC_TEST_AW63

2

12

RC2660_0402_5% @RC2660_ 0402_5% @

12

RC2680_0402_5% @RC2680_ 0402_5% @

4

1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4

2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60

3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63

4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1

HASWELL_MCP_E

UC1R

UC1R

AT2

T50 P AD~D@T50 PAD~D@
T52 P AD~D@T52 PAD~D@
T54 P AD~D@T54 PAD~D@

T58 P AD~D@T58 PAD~D@
T60 P AD~D@T60 PAD~D@
T62 P AD~D@T62 PAD~D@

B B

RSVD_AT2
RSVD_AU44
RSVD_AV44
RSVD_D15

RSVD_F22
RSVD_H22
RSVD_J21

AU44
AV44

RSVD
RSVD
RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

HASWELL_MCP_E

18 OF 19

18 OF 19

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

Rev1p2

Rev1p2

N23
R23
T23
U10

AL1
AM11
AP7
AU10
AU15
AW14
AY14

RSVD_N23
RSVD_R23
RSVD_T23
RSVD_U10

RSVD_AL1
RSVD_AM11
RSVD_AP7
RSVD_AU10
RSVD_AU15
RSVD_AW14
RSVD_AY14

@

T48PAD~D@T48PAD~D

@

T49PAD~D@T49PAD~D

@

T51PAD~D@T51PAD~D

@

T53PAD~D@T53PAD~D

@T55 P AD~D@T55 PAD~D@

T56PAD~D@T56PAD~D

@

T57PAD~D@T57PAD~D

@

T59PAD~D@T59PAD~D

@

T61PAD~D@T61PAD~D

@

T63PAD~D@T63PAD~D

@

T64PAD~D@T64PAD~D

@

T65PAD~D@T65PAD~D

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(9/12)

MCP(9/12)

MCP(9/12)

LA-9431P

LA-9431P

LA-9431P

14 59Friday, May 17, 2013

14 59Friday, May 17, 2013

14 59Friday, May 17, 2013

1

0.3

0.3

0.3

5

+1.05V_RUN

150_0402_1%

150_0402_1%

12

RC253

RC253

CPU_PWR_DEBU G#

10K_0402_5%

10K_0402_5%

D D

C C

RESET_OUT#<37,9>

SVID ALERT

VIDALERT_N<46>

SVID DATA

B B

VIDSOUT<46>

12

@

@

RC258

RC258

H_VR_EN H_VR_READY

RC263 0_0402_5%@ RC263 0_0402_5%@

+1.05V_VCCST

+1.05V_VCCST

12

RC25610K_ 0402_5% RC25610K_0402 _5%

12

75_0402_1%

75_0402_1%

12

RC244

RC244

110_0402_1%

110_0402_1%

12

RC249

RC249

VIDSOUT

VCC_SENSE

VCCSENSE<46>

+1.05V_RUN +VCCIO_OUT

RC242 0_0603_ 5%@RC242 0_0603_5%@

RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES

+1.05V_VCCST +3.3V_RUN

12

@

@

RC255

RC255
10K_0402_5%

10K_0402_5%

UC4

UC4

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

74AUP1G07GW_TSSOP5

CAD Note: Place the PU resistors close to CPU
RC224 close to CPU 300 - 1500mils

12

CAD Note: Place the PU resistors close to CPU
RC249close to CPU 300 - 1500mils

5

4

Y

H_CPU_SVIDALRT#

RC24843_0402_5% RC24843_0402_5%

+VCC_CORE

100_0402_1%

100_0402_1%

12

RC250

RC250

CC24 0.1U_0402_25V6@ CC24 0.1U_0402_25V6@

VCCSENSE

CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU

4

12

@

@

12

RC259

RC259
10K_0402_5%

10K_0402_5%

1 2

H_VCCST_PWRGD

reference ULT CRB

3

+1.35V_MEM +3.3V_ALW

+3.3V_RUN +5V_ALW

+VCC_CORE +1.35V_MEM

+VCC_CORE

+VCC_CORE

+VCC_CORE +1.35V_MEM

+1.05V_VCCST+3.3V_ALW

1K_0402_5%

1K_0402_5%
RC243

RC243

1 2

1 2

C452 22U_0603_6.3V6MEMC@ C452 22U_060 3_6.3V6MEMC@

1 2

C453 22U_0603_6.3V6MEMC@ C453 22U_060 3_6.3V6MEMC@

1 2

100P_0402_50V8J

100P_0402_50V8J

C454 22U_0603_6.3V6M@ C454 22U_0603_6.3V6M@

1 2

C458 22U_0603_6.3V6M@ C458 22U_0603_6.3V6M@

1 2

C459 22U_0603_6.3V6M@ C459 22U_0603_6.3V6M@

1 2

C460 22U_0603_6.3V6M@ C460 22U_0603_6.3V6M@

1 2

C461 22U_0603_6.3V6M@ C461 22U_0603_6.3V6M@

1

@

@

CC22

CC22

2

H_VCCST_PWRGD

+1.05V_RUN

+3.3V_RUN

+1.05V_RUN+1.35V_MEM

ESD Request

H_VCCST_PWRGD<9>

H_VR_EN<46>

H_VR_READY<46>

+1.05V_RUN +1.05V_VCCST

H_VCCST_PWRGD VCCST_PWRGD
H_VR_EN VR_EN
H_VR_READY VR_READY

CPU_PWR_DEBU G#<9>

PJP11

PJP11

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

+1.35V_MEM

RC245 0_0402_5%@ RC245 0_0402_5%@
RC246 0_0402_5%@ RC246 0_0402_5%@
RC247 0_0402_5%@ RC247 0_0402_5%@

CC50

CC50

VIDSCLK<46>

1 2
1 2
1 2

CPU_PWR_DEBU G#

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

CC26

CC26

1

2

1

2

T66 PAD~D@ T66 PAD~D@
T67 PAD~D@ T67 PAD~D@

+VCC_CORE

T68

@T68

@

PAD~D

PAD~D

T69

@T69

@

PAD~D

PAD~D

T70

@T70

@

PAD~D

PAD~D

+VCCIO_OUT
+VCCIOA_OUT

T71

@T71

@

PAD~D

PAD~D

T72

@T72

@

PAD~D

PAD~D

T73

@T73

@

PAD~D

PAD~D

T74

@T74

@

PAD~D

PAD~D

T75

@T75

@

PAD~D

PAD~D

T76

@T76

@

PAD~D

PAD~D

T77

@T77

@

PAD~D

PAD~D

T78

@T78

@

PAD~D

PAD~D

T79

@T79

@

PAD~D

PAD~D

T80

@T80

@

PAD~D

PAD~D

T81

@T81

@

PAD~D

PAD~D

T82

@T82

@

PAD~D

PAD~D

T83

@T83

@

PAD~D

PAD~D

T84

@T84

@

PAD~D

PAD~D

T85

@T85

@

PAD~D

PAD~D

T86

@T86

@

PAD~D

PAD~D

+1.05V_VCCST

+VCC_CORE

+1.35V_MEM

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

@

@

@

@

CC52

CC52

CC81

CC81

2

VCCSENSE

H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

1

CC12

CC12

2

2

L59
J58

AH26

AJ31
AJ33

AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

F59
N58

AC58

E63

AB23

A59

E20
AD23
AA23
AE59

L62

N63

L63
B59
F60
C59

D63
H59
P62
P60
P61
N59
N61
T59

AD60
AD59
AA59
AE60
AC59
AG58

U59
V59

AC22
AE22
AE23

AB57
AD57
AG57

C24
C28
C32

2

VDDQ DECOUPLING

Reference ULT DDRDG_080912 change to10uX6 2.2uX4

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

CC13

CC13

2

UC1L

UC1L

RSVD
RSVD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VCC
RSVD
RSVD

VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD

VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCST
VCCST
VCCST

VCC
VCC
VCC
VCC
VCC
VCC

1

@

@

CC17

CC17

CC16

CC16

2

1

CC18

CC18

2

HASWELL_MCP_E

HASWELL_MCP_E

10U_0603_6.3V6M

1

CC19

CC19

2

HSW ULT POWER

HSW ULT POWER

12 OF 19

12 OF 19

1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

@

@

CC21

CC21

CC20

CC20

2

2

+VCC_CORE

C36

VCC

C40

VCC

C44

VCC

C48

VCC

C52

VCC

C56

VCC

E23

VCC

E25

VCC

E27

VCC

E29

VCC

E31

VCC

E33

VCC

E35

VCC

E37

VCC

E39

VCC

E41

VCC

E43

VCC

E45

VCC

E47

VCC

E49

VCC

E51

VCC

E53

VCC

E55

VCC

E57

VCC

F24

VCC

F28

VCC

F32

VCC

F36

VCC

F40

VCC

F44

VCC

F48

VCC

F52

VCC

F56

VCC

G23

VCC

G25

VCC

G27

VCC

G29

VCC

G31

VCC

G33

VCC

G35

VCC

G37

VCC

G39

VCC

G41

VCC

G43

VCC

G45

VCC

G47

VCC

G49

VCC

G51

VCC

G53

VCC

G55

VCC

G57

VCC

H23

VCC

J23

VCC

K23

VCC

K57

VCC

L22

VCC

M23

VCC

M57

VCC

P57

VCC

U57

VCC

W57

VCC

Rev1p2

Rev1p2

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(10/12)

MCP(10/12)

MCP(10/12)

LA-9431P

LA-9431P

LA-9431P

15 59Friday, May 17, 2013

15 59Friday, May 17, 2013

15 59Friday, May 17, 2013

1

0.3

0.3

0.3

5

+1.05V_MODPHY +1.05V_MODPHY_PCH

1 2

RC262 0_0805_5%@ RC262 0_0805_5%@

CC29 place near K9;
CC27 place near L10
CC74 place near M9

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CC74

CC74

2

1U_0402_6.3V6K

1

1

@

@

CC27

CC27

CC29

CC29

2

2

VCCHSIO
S0 Iccmax = 1.838A

D D

+1.05V_MODPHY

1 2

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

CC42 place near B18

VCCUSB3PLL

LC1

LC1

+PCH_AUSB3PLL

22U_0603_6.3V6M

22U_0603_6.3V6M

1

CC76

CC76

2

22U_0603_6.3V6M

22U_0603_6.3V6M

1

CC42

CC42

2

S0 Iccmax = 41mA

LC2

LC2

1 2

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

CC49 place near B11

VCCSATA3PLL
S0 Iccmax = 42mA

C C

LC5

LC5

1 2

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

CC56 place near AA21

VCCAPLL
S0 Iccmax = 57mA

+1.05V_M

@

@

RC276

RC276

1 2

0_0603_5%

0_0603_5%

CC66 place near AH13
CC61 CC62 place near J13

DcpSus2

+PCH_ASATA3PLL+1.05V_MODPHY

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

CC77

CC77

2

2

+V1.05S_APLLOPI+1.05V_RUN

100U_1206_6.3V6M

100U_1206_6.3V6M

1

1

CC55

CC55

2

2

+PCH_DCPSUS

1U_0402_6.3V6K

1U_0402_6.3V6K

@CC66

@

1

1

CC66

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CC49

CC49

+3.3V_ALW_PCH

0.1U_0402_10V7K

0.1U_0402_10V7K

CC44

CC44

1

1U_0402_6.3V6K

1U_0402_6.3V6K

CC56

CC56

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

@

@

@CC61

@

1

CC62

CC62

CC61

2

CC44 place near AH14

+3.3V_ALW_PCH

2

CC28 place near AC9

22U_0603_6.3V6M

22U_0603_6.3V6M

+3.3V_RUN

CC28

CC28

1

CC43 place near V8

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

2

CC43

CC43

+1.05V_RUN

S0 Iccmax = 25mA
DcpSus3
S0 Iccmax = 10mA

B B

1 2

RC265 0_0402_5%@ RC265 0_0402_5%@

+3.3V_ALW

1 2

RC267 0_0402_5%@ RC267 0_0402_5%@

CC32 place near AH10

VCCDSW3_3

+PCH_VCCDSW3_3+3.3V_ALW_PCH

1U_0402_6.3V6K

1U_0402_6.3V6K

1

@

@

CC32

CC32

2

S0 Iccmax = 114mA

+PCH_VCC1P05+1.05V_RUN

1U_0402_6.3V6K

LC3

LC3

1 2

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

CC51 place near J18

VCCCLK
S0 Iccmax = 200mA

A A

+1.05V_RUN

LC6

LC6

1 2

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

CC58 place near A20

VCCACLKPLL

1U_0402_6.3V6K

100U_1206_6.3V6M

100U_1206_6.3V6M

1

1

CC79

CC79

CC51

CC51

2

2

+PCH_VCCACLKPLL

1U_0402_6.3V6K

1U_0402_6.3V6K

100U_1206_6.3V6M

100U_1206_6.3V6M

1

1

CC58

CC58

CC78

CC78

2

2

S0 Iccmax = 31mA

5

4

+1.05V_RUN

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CC63

CC63

2

2

4

+1.05V_MODPHY_PCH

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

CC63 close to Pin J17

CC64

CC64

CC64 close to Pin R21

@

@

CC31

CC31

+PCH_AUSB3PLL

+PCH_ASATA3PLL

+V1.05S_APLLOPI

+PCH_DCPSUS

+PCH_VCCDSW3_3

+PCH_VCC1P05

+PCH_VCCACLKPLL

+3.3V_ALW_PCH

AA21

AH14

AH13

AH10

AE20
AE21

L10

B18
B11

Y20

W21

J13

AC9
AA9

W9

J18
K19
A20

J17
R21
T21
K18
M20
V21

K9

M9
N8
P9

V8

UC1M

UC1M

VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL

RSVD
VCCAPLL
VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3

VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

@

@

1

CC73

CC73

+

+

2

mPHY

mPHY

OPI

OPI

USB3

USB3

AXALIA/HDA

AXALIA/HDA

VRM/USB2/AZALIA

VRM/USB2/AZALIA

GPIO/LCC

GPIO/LCC

LPT LP POWER

LPT LP POWER

3

+1.05V_RUN+1.05V_M

HASWELL_MCP_E

HASWELL_MCP_E

13 OF 19

13 OF 19

3

2

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

@

@

@

@

1

1

2

CC72

CC72

CC71

CC71

+

+

+

+

2

RTC

SPI

SPI

CORE

CORE

THERMAL SENSOR

THERMAL SENSOR

SDIO/PLSS

SDIO/PLSS

SUS OSCILLATOR

SUS OSCILLATOR

USB2

USB2

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

VCCRTC
DCPRTC

VCCSPI

VCCASW
VCCASW

VCC1_05
VCC1_05
VCC1_05
VCC1_05

VCC1_05
DCPSUSBYP
DCPSUSBYP

VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1

VCCTS1_5

VCC3_3
VCC3_3

VCCSDIO
VCCSDIO

DCPSUS4

RSVD
VCC1_05
VCC1_05

Rev1p2

Rev1p2

AG10
AE7

Y8

AG14
AG13

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8

J15
K14
K16

U8
T9

AB8

AC20
AG16
AG17

AH11

VCCSUS3_3

RTC

+PCH_RTC_VCCSUS3_3

1 2

+DCPRRTC

CC36

CC36

0.1U_0402_10V7K

0.1U_0402_10V7K

+1.05V_M

+PCH_VCCDSW

CC46 CC47 place near AE9

+PCH_DCPSUS1

+1.5V_THERMAL

+PCH_DCPSUS4

CC60 place near AG16

CC34 and CC33 place near
J11; CC37 place near AE8

1

2

CC45 place near U8

2

+1.05V_M

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.05V_RUN

CC40 place near Y8

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

22U_0805_6.3V6M

22U_0805_6.3V6M

CC37

CC37

2

2

1

@

@

CC46

CC46

CC47

CC47

2

CC59 place near K14

+3.3V_RUN

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CC45

CC45

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CC60

CC60

1

2

DELL CONFIDENTIAL/PROPRIETARY

1

CC35,CC38, CC39 place near AG10

+3.3V_M

0.1U_0402_10V7K

0.1U_0402_10V7K

1

@

@

CC40

+1.05V_RUN

1U_0402_6.3V6K

1U_0402_6.3V6K

CC33

CC33

+3.3V_RUN

CC40

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC34

CC34

2

0.1U_0402_10V7K

0.1U_0402_10V7K

1

2

+PCH_VCCDSW

CC59

CC59

CC65 place near AG19

+PCH_RTC_VCCSUS3_3 +3.3V_ALW_PCH

1

2

+RTC_CELL

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CC30 place near AH11

CC30

CC30

VCCSUS3_3

1

@

@

CC39

CC39

CC38

CC38

2

2

12

1U_0402_6.3V6K

1U_0402_6.3V6K

CC35

CC35

RC2755.11_0402_1% RC2755.11_0402_1%

12

RC2610_0402_5% @ RC2610_0402_5% @

+3.3V_ALW

12

RC2640_0402_5% @ RC2640_0402_5% @

S0 Iccmax = 63mA

1U_0402_6.3V6K

1U_0402_6.3V6K

@CC54

@

1

CC54

CC54 place near AD10

DCPSUS1

2

12

RC2720_0402_5% @ RC2720_0402_5% @

S0 Iccmax = 109mA

+PCH_DCPSUS4 +1.05V_M

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

@

@

CC53

CC53

2

2

@

@

LC4

LC4

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

100U_1206_6.3V6M

100U_1206_6.3V6M

@

@

CC75

CC75

CC53 place near AB8

DCPSUS4

12

S0 Iccmax = 1mA

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: S heet of

Date: S heet of

Date: S heet of

Compal Electronics, Inc.

MCP(11/12)

MCP(11/12)

MCP(11/12)

LA-9431P

LA-9431P

LA-9431P

1

16 59Friday, May 17, 2013

16 59Friday, May 17, 2013

16 59Friday, May 17, 2013

+PCH_VCCDSW_R

1U_0402_6.3V6K

1U_0402_6.3V6K

CC65

CC65

1

2

+1.05V_M+PCH_DCPSUS1

0.3

0.3

0.3

5

D D

HASWELL_MCP_E

HASWELL_MCP_E

UC1N

UC1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

AB22

VSS

AB7

VSS

AC61

VSS

AD21

VSS

AD3

VSS

AD63

VSS

AE10

VSS

AE5

C C

B B

AE58
AF11
AF12
AF14
AF15
AF17
AF18

AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57

AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

14 OF 19

14 OF 19

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1p2

Rev1p2

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

4

HASWELL_MCP_E

HASWELL_MCP_E

UC1O

UC1O

AP22

VSS

AP23

VSS

AP26

VSS

AP29

VSS

AP3

VSS

AP31

VSS

AP38

VSS

AP39

VSS

AP48

VSS

AP52

VSS

AP54

VSS

AP57

VSS

AR11

VSS

AR15

VSS

AR17

VSS

AR23

VSS

AR31

VSS

AR33

VSS

AR39

VSS

AR43

VSS

AR49

VSS

AR5

VSS

AR52

VSS

AT13

VSS

AT35

VSS

AT37

VSS

AT40

VSS

AT42

VSS

AT43

VSS

AT46

VSS

AT49

VSS

AT61

VSS

AT62

VSS

AT63

VSS

AU1

VSS

AU16

VSS

AU18

VSS

AU20

VSS

AU22

VSS

AU24

VSS

AU26

VSS

AU28

VSS

AU30

VSS

AU33

VSS

AU51

VSS

AU53

VSS

AU55

VSS

AU57

VSS

AU59

VSS

AV14

VSS

AV16

VSS

AV20

VSS

AV24

VSS

AV28

VSS

AV33

VSS

AV34

VSS

AV36

VSS

AV39

VSS

AV41

VSS

AV43

VSS

AV46

VSS

AV49

VSS

AV51

VSS

AV55

VSS

15 OF 19

15 OF 19

Rev1p2

Rev1p2

3

AV59

VSS

AV8

VSS

AW16

VSS

AW24

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B4

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D2

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

2

UC1P

UC1P

HASWELL_MCP_E

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49

D50
D51
D53
D54
D55
D57
D59
D62

E11
E17

F20
F26
F30
F34
F38
F42
F46
F50
F54
F58

F61
G18
G22

H13

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS
VSS

16 OF 19

16 OF 19

VSS_SENSE

Rev1p2

Rev1p2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

V58
AH46
V23
E62
AH16

100_0402_1%

100_0402_1%

12

RC260

RC260

1

VSSSENSE <46>

CAD Note: RC260 SHOULD BE PLACED CLOSE TO CPU

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MCP(12/12)

MCP(12/12)

MCP(12/12)

LA-9431P

LA-9431P

LA-9431P

17 59Friday, May 17, 2013

17 59Friday, May 17, 2013

17 59Friday, May 17, 2013

1

0.3

0.3

0.3

5

+SM_VREF_DQ0_DIMM1

Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3

D D

C C

B B

A A

VREFDQ multiple methods M3

All VREF traces should
have 10 mil trace width

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..15]<8>

Layout Note:
Place near JDIMM1

+1.35V_MEM

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD4

CD4

2

+1.35V_MEM

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD14

CD14

1

1

2

2

Layout Note:
Place near JDIMM1.203,204

+0.675V_DDR_VTT

0.1U_0402_25V6

0.1U_0402_25V6

CD26

CD26

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

2

@

@

CD15

CD15

CD6

CD6

CD5

CD5

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD16

CD16

1

1

2

2

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

CD27

CD27

1

1

2

2

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CD7

CD7

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

@

@

CD17

CD17

CD18

CD18

1

2

0.1U_0402_25V6

0.1U_0402_25V6

CD28

CD28

CD29

CD29

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

2

1

2

CD9

CD9

CD8

CD8

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD21

CD21

CD20

CD20

CD19

CD19

1

2

1

1

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD30

CD30

CD31

CD31

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

2

CD11

CD11

CD10

CD10

2

330U_D3_2.5VY_R6M

330U_D3_2.5VY_R6M

1

CD22

CD22

+

+

2

1 2

RD5 0_0402_5%@RD5 0_0402_5%@

1 2

RD6 0_0402_5%@RD6 0_0402_5%@

1 2

RD1 0_0402_5%@ RD1 0_0402_5%@

4

+3.3V_RUN

3

+DIMM1_VREF_DQ

0.1U_0402_25V6

0.1U_0402_25V6

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

CD1

CD1

2

DDR_CKE0_DIMMA<8>

DDR_A_BS2<8>

M_CLK_DDR0<8>

DDR_A_BS0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<8>

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

@

@

CD25

CD25

2

DDR_A_D13
DDR_A_D8

CD2

CD2

1

DDR_A_D14

2

DDR_A_D10

DDR_A_D29
DDR_A_D28 DDR_A_D24

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D43
DDR_A_D47

DDR_A_D51
DDR_A_D50

DDR_A_D49
DDR_A_D48

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_BS2

DDR_A_MA3

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10

DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D6

DDR_A_D21
DDR_A_D20

DDR_A_D17
DDR_A_D16

DDR_A_D36
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D38

DDR_A_D62
DDR_A_D58

DDR_A_D60
DDR_A_D61

0.1U_0402_25V6

0.1U_0402_25V6

1

CD24

CD24

+0.675V_DDR_VTT

2

H=4mm

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A621-U4R6-7H

FOX_AS0A621-U4R6-7H

CONN@JDIMM1

CONN@

VREF_CA

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

VDD10

CK1
CK1#

VDD12

BA1
RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

2-3A to 1 DIMMs/channel

+1.35V_MEM+1.35V_ME M

2
4

DDR_A_D9

6

DDR_A_D12

8
10

DDR_A_DQS#1

12

DDR_A_DQS1

14
16

DDR_A_D15

18

DDR_A_D11

20
22

DDR_A_D25

24
26
28
30

DDR3_DRAMRST#

32
34

DDR_A_D27

36

DDR_A_D26

38
40

DDR_A_D45DDR_A_D44

42

DDR_A_D40

44
46
48
50

DDR_A_D42

52

DDR_A_D46

54
56

DDR_A_D52

58

DDR_A_D53

60
62

DDR_A_DQS#6

64

DDR_A_DQS6

66
68

DDR_A_D54

70

DDR_A_D55

72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_A_MA15

DDR_A_MA14

DDR_A_MA11DDR_A_MA12

DDR_A_MA7DDR_A_MA9

DDR_A_MA6DDR_A_MA8

DDR_A_MA4DDR_A_MA5

DDR_A_MA2

DDR_A_MA0DDR_A_MA1

M_CLK_DDR1

M_CLK_DDR#1

DDR_A_BS1

DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT0

M_ODT1

+SM_VREF_CA_DIMM1

DDR_A_D5

DDR_A_D4

DDR_A_D3

DDR_A_D7

DDR_A_D18

DDR_A_D19

DDR_A_DQS#2

DDR_A_DQS2

DDR_A_D22

DDR_A_D23

DDR_A_D37

DDR_A_D32

DDR_A_D35

DDR_A_D39

DDR_A_D63

DDR_A_D59

DDR_A_DQS#7

DDR_A_DQS7

DDR_A_D56

DDR_A_D57

+0.675V_DDR_VTT

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

0.1U_0402_25V6

0.1U_0402_25V6

@

@

CD3

CD3

1

2

CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN

DDR_CKE1_DIMMA <8>

M_CLK_DDR1 <8>

M_CLK_DDR#1 <8>M_CLK_DDR#0<8>

DDR_A_BS1 <8>

DDR_A_RAS# <8>

DDR_CS0_DIMMA# <8>

0.1U_0402_25V6

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6

CD13

CD13

CD12

CD12

1

1

2

2

2

Reverse Type

+SM_VREF_DQ0_DIMM1

+5V_ALW +1.35V_MEM

220K_0402_5%~D

+SM_VREF_CA_DIMM

1 2

RD12 0_0402_5%@ RD12 0_0402_5%@

DDR_PG_CTRL<9>

DDR_XDP_WAN_ SMBDAT <19,31,7,9>

DDR_XDP_WAN_ SMBCLK <19,31,7,9>

220K_0402_5%~D

1

+1.35V_MEM

12

RD3

RD3
470_0402_5%

470_0402_5%

1 2

RC279 0_0402_5%@RC279 0_0402_5%@

+1.35V_MEM

1.8K_0402_1%

1.8K_0402_1%

12

RC217

RC217

RC173

RC173

1.8K_0402_1%

1.8K_0402_1%

12

RC221

RC221

1 2

2_0402_1%

2_0402_1%

DDR3_DRAMRST#_CP U <9>DDR3_DRAMRST#<19>

+SM_VREF_DQ0

1

CC70

CC70

0.022U_0402_16V7K

0.022U_0402_16V7K

2

12

RC195

RC195

24.9_0402_1%

24.9_0402_1%

DDR3L SODIMM ODT GENERATION

QD1

QD1
BSS138-G_SOT23-3

NC1VCC

A

GND

BSS138-G_SOT23-3

1 3

D

S

D

S

R29 66.5_0402_1%R29 66.5_0402_1%

G

G

2

R30 66.5_0402_1%R30 66.5_0402_1%

R31 66.5_0402_1%R31 66.5_0402_1%

R33 66.5_0402_1%R33 66.5_0402_1%

+1.35V_MEM

5

4

Y

1 2

1 2

1 2

1 2

CD23

@CD23

@

0.1U_0402_25V6

0.1U_0402_25V6

1 2

0.675V_DDR_VTT_ON

12

R28

R28

0.675V_DDR_VTT_ON

R32

@R32

@

2M_0402_5%

2M_0402_5%

1 2

U5

U5

2

3

74AUP1G07GW_TSSOP5

74AUP1G07GW_TSSOP5

M_ODT0

M_ODT1

M_ODT2 <19>

M_ODT3 <19>

0.675V_DDR_VTT_ON <43>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

LA-9431P

LA-9431P

LA-9431P

18 59Friday, May 17, 2013

18 59Friday, May 17, 2013

18 59Friday, May 17, 2013

1

0.3

0.3

0.3