Page 1
A
COMPAL CONFIDENTIAL
B
C
D
E
1 1
PCB NO :
BOM P/N :
LA-9431P (DAA00005Z10)
4319LL31LXX
MODEL NAME :
VAZ50
GPIO MAP: 3.0C
2 2
Goliad 12"
Haswell ULT
2013-05-17
@ : Nopop Component
1@ : M/B 8M SPI ROM Component
3 3
2@ : TAA/B 8M SPI ROM
REV : 1.0 (A00)
SPI on MB TAA
EMC@ : EMI & ESD & RF Component
XDP@ : XDP Component
CONN@ : Connector Component
3@ : Delete componet for cost down BOM
Vpro
non-Vpro
1@/4@/EMC@/
3@/EMC_3@
1@/EMC@/
3@/EMC_3@
2@/5@/EMC@
3@/EMC_3@
2@/5@/EMC@
3@/EMC_3@
EMC_3@ : Delete EMC component for cost down BOM
4@ : M/B 4M SPI ROM Component
5@ : TAA/B 4M SPI ROM
4 4
MB PCB
MB PCB
Part Number
Part Number
DAA00005Z10
DAA00005Z10
7@ : M/B for 8M SPI(Reverse)
Description
Description
PCB 0VM LA-9431P REV1 M/B 4
PCB 0VM LA-9431P REV1 M/B 4
A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
non-Vpro
(cost down)
1@/EMC@
D
2@/5@/EMC@/
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
LA-9431P
LA-9431P
LA-9431P
1 59Friday, May 17, 2013
1 59Friday, May 17, 2013
1 59Friday, May 17, 2013
E
0.3
0.3
0.3
Page 2
A
Goliad12 Block Diagram
B
C
D
E
Memory BUS (DDR3L)
USB
USB2.0[7]
PAGE 7
PAGE 36
1333/1600MHz
DOCKED_LIO_EN
USB2.0[0]
DOCKED
USB2.0[5]
USB3.0[3]
HD Audio I/F
SATA0
Full Mini Card
mSATA
Trough eDP Cable
NX3DV221
USB20 Switch
PI3USB3102
USB3&2 Switch
Touch Screen
Conn
PAGE 27
eDP
DDI2
INTEL
HASWELL
ULT
1 1
Mini-DP
DP
For MB/Dock
DP
Video Switch
IDT VMM2320
VGA
eDP CONN
PAGE 27
PAGE 21
PAGE 22
DP
DP
Pericom
PI3VDP12412
BGA CPU
DOCKING
PORT
2 2
PAGE 34
DAI
DOCK_USB3.0[3]
SATA1
DOCK_USB2.0[0]
DOCK_USB2.0[5]
PCIE3 PCIE4
HDMI CONN
PAGE 23
SD4.0
HDMI
PAGE 30 PAGE 30
Intel Clarkville
RFID
60GHz
PAGE 31 PAGE 31
TDA8034HN
Fingerprint
CONN
I218LM
PAGE 28
3 3
LAN SWITCH
PI3L720
PAGE 28
Transformer
PAGE 35
RJ45
PAGE 35
Smart Card
Reduce Level
Shifter
PAGE 23
Card reader
O2 Micro OZ777FJ2LN
PCI Express BUS
PCIE6_L0
Full Mini CardWLAN+BT/
WWAN+mSATA
SATA2
USB2.0[6]USB2.0[2]
BCM5882
FP_USB
PAGE 29
FAN CONN
4 4
A
B
DDI1
PCIE5_L0
Discrete TPM
AT97SC3204
PAGE 29
USH
USB2.0[4]
USH board
SMSC KBC
MEC5075
PAGE 37 PAGE 37
KB and TP CONN
PAGE 38
PAGE 6~17
SPI
W25Q64FVSSIQ
64M 4K sector
W25Q32FVSSIQ
LPC
32M 4K sector
SMSC SIO
ECE5048
BC BUS
C
DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
REV. type
SW_USB2.0[0]
PAGE 33
PAGE 32
PAGE 25
PAGE 22
HDA Codec
ALC3226
D
PAGE 18 19
USB2.0[3]
USB POWER SHARE
DOCK _USB2.0[0]
SW_USB2.0[5]
SW_USB3.0[3]
USB2.0[1]
USB3.0[1]
PAGE 26
Trough eDP Cable
Camera
PAGE 22
Trough eDP Cable
SLGC55594A
PAGE 33
USB3.0/2.0+PS
IO/B
Near Field
PAGE 33
PAGE 20
USB3.0/2.0
DOCK _USB2.0[5]
DOCK_USB3.0[3]
USB3.0/2.0
PAGE 35
USB3.0[2]
PAGE 33
Communications con
INT.Speaker
PAGE 26
Vol bottom SW
Combo Jack
DAI
To Docking side
CPU XDP Port
PAGE 40
PAGE 9
Automatic Power
Dig.
MIC
PAGE 22
Switch (APS)
WiFi ON/OFF
PAGE 9
PAGE 35
DC/DC Interface
PAGE 39
Power On/Off
SW & LED
PAGE 40
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
LA-9431P
LA-9431P
LA-9431P
2 59Friday, May 17, 2013
2 59Friday, May 17, 2013
2 59Friday, May 17, 2013
E
IO/B
0.3
0.3
0.3
Page 3
5
4
3
2
1
POWER STATES
State
S0 (Full ON) / M0
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
PCIE
PCIE 1
PCIE 2
PCIE 3
PCIE 4
PCIE 5
PCIE 6 WWAN(PP/mSATA)
USB3.0
USB3.0 1
USB3.0 2
USB3.0 3
SATA
SATA 3
DESTINATION
JUSB3-->Right
JUSB1-->Rear left
JUSB2-->Rear Right//DOCK
LOM
WLAN (WiGi)
MMI (CARD READER)
PM TABLE
C C
power
plane
+3.3V_ALW
+3.3V_ALW_PCH
+3.3V_RTC_LDO
+3.3V_SUS+5V_ALW +5V_RUN
+1.35V_MEM
+0.675V_DDR_VTT
+1.05V_RUN
+VCC_CORE
+3.3V_M +3.3V_M
+1.05V_M+3.3V_RUN
+1.05V_M
(M-OFF)
SATA 2
SATA 0
USB PORT#
State
0
1
S0
S3
S5 S4/AC
S5 S4/AC don't exist
B B
ON
ON
ON ON
ON
OFF
OFFOFF
OFFON
OFF
OFF
ON
ON
ON
need to update Power Status and
PM Table
ON
OFF
OFF
OFFOFF
HSW
ULT
2
3
4
5
6
7
JUSB1 // E-Dock 1
JUSB3
WLAN + BT
CAMERA
USH->SMART CARD
JUSB2 // E-Dock 2
WWAN
TOUCH
NA
mSATASATA 1
DOCK
DESTINATION
USH
0
1
BIO
NA
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Index and Config.
Index and Config.
Index and Config.
LA-9431P
LA-9431P
LA-9431P
3 59Friday, May 17, 2013
3 59Friday, May 17, 2013
3 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 4
5
4
3
2
1
+1.05V_RUN
+3.3V_RUN
A_ON
PWRSHARE_EN#
ESATA_USB_PWR_EN#
USB_SIDE_EN#
TPS51212
(PU300)
D D
ADAPTER
DOCKED
TPS22966
+1.05V_M
(U31)
MPHYP_PWR_EN
G547I2P81U
(U35)
+5V_USB_
CHG_PWR
G547I2P81U
(U32)
+USB_PWR
G547I2P81U
(U52)
+USB_SIDE_PWR
SI3456DDV
BATTERY +PWR_SRC
EN_INVPWR
+1.05V_RUN_VMM
FDC654P
(Q2)
C C
+3.3V_RUN_VMM
+BL_PWR_SRC
CHARGER
(Q125)
+1.05V_MODPHY
ALWON
TPS51285BRUKR
(PU100)
+5V_ALW
+3.3V_ALW
RUN_ON
PCH_ALW_ON
TPS22966
3.3V_HDD_EN
TPS22966
(U3)
AUX_EN_WOWL
ENVDD_PCH
APL3512A
(U9)
RUN_ON
TPS22966
(U46)
RUN_ON
RUN_ON
RUN_ON
TPS22966
(U18)
SIO_SLP_LAN#
SUS_ON
TPS51622
(PU500)
B B
RT8207
(PU11)
A_ON
TPS22966
(U45)
MCARD_WWAN_PWREN
TPS22966
(U22)
TPS22966
(U22)
(U43)
+3.3V_ALW_PCH
H_VR_EN
SUS_ON
+VCC_CORE
A A
+1.35V_MEM
+0.675V_DDR_VTT
5
+5V_RUN
_AUDIO
0.675V_DDR_VTT_ON
+3.3V_M
+3.3V_SUS
4
+3.3V_LAN
+3.3V_mSATA_WWAN
+3.3V_WLAN
+3.3V_RUN
+3.3V_HDD
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
+LCDVDD
+3.3V_CAM
3.3V_TS_EN
3.3V_CAM_EN
LP2301ALT1G
(Q3)
2
+5V_RUN
LP2301ALT1G
(Q1)
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3.3V_RUN
_AUDIO
+1.05V_RUN
+3.3V_TSP
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Power Rail
Power Rail
Power Rail
LA-9431P
LA-9431P
LA-9431P
4 59Friday, May 17, 2013
4 59Friday, May 17, 2013
4 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 5
5
SMBUS Address [0x9a]
AP2
AH1
MEM_SMBCLK
MEM_SMBDATA
PCH
D D
B4
A3
B5
A4
SML0CLK
SML0DATA
2.2K
2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
LCD_SMBCLK
LCD_SMBDAT
+3.3V_ALW_PCH
AN1
AK1
AU3AH3
SML1_SMBDATA
SML1_SMBCLK
B6A5
3A
3A
1A
1A
C C
1B
1B
1K
1K
2.2K
2.2K
4
+3.3V_ALW_PCH
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW
2N7002
2N7002
0ohm
0ohm
0ohm depop
0ohm depop
127
129
NFC_SMBCLK
NFC_SMBDATA
DOCKING
LAN_SMBCLK
LAN_SMBDATA
3
28
31
LOM
2
202
200
202
200
53
51
DIMMA
DIMMB
XDP
1
NFC
30
32
WWAN
2.2K
4
+3.3V_ALW
100 ohm
100 ohm
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
7
BATTERY
6
CONN
M9
L9
USH
9
8
Charger
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Compal Electronics, Inc.
SMBUS TOPOLOGY
SMBUS TOPOLOGY
SMBUS TOPOLOGY
LA-9431P
LA-9431P
LA-9431P
5 59Friday, May 17, 2013
5 59Friday, May 17, 2013
5 59Friday, May 17, 2013
1
0.3
0.3
0.3
KBC
A56
1C1CB59
PBAT_SMBCLK
PBAT_SMBDAT
2.2K
2.2K
2.2K
A50
B53
A49
B52
USH_SMBCLK
USH_SMBDAT
2.2K
2.2K
CARD_SMBCLK
CARD_SMBDAT
1E
B B
1E
MEC 5075
2B
2B
10K
B50
A47
CHARGER_SMBCLK
CHARGER_SMBDAT
1G
1G
10K
2.2K
2.2K
B7
A7
BAY_SMBDAT
BAY_SMBCLK
2D
A A
2D
2.2K
2.2K
B7
A7
GPU_SMBDAT
GPU_SMBCLK
2A
2A
5
Page 6
5
+RTC_CELL
330K_0402_1%
330K_0402_1%
12
RC1
RC1
PCH_INTVRMEN
330K_0402_1%
330K_0402_1%
12
@RC2
@
D D
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
High - Enable Internal VRs
Low - Enable External VRs
RC2
+3.3V_AL W_PCH
1 2
RC3 1K_0 402_5%@RC3 1K_0402 _5%@
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT)
HIGH = DISABLE
PCH_AZ_S DOUT
4
3
2
1
1 2
CC1
CC1
15P_040 2_50V8J
15P_040 2_50V8J
C C
1 2
RC7 1M_0402 _5%RC7 1M_0402_5 %
CMOS_CLR1
Shunt Clear CMOS
Open
ME_CLR1
Shunt Clear ME RTC Registers
Open
0_0603_5%
0_0603_5%
12
@
@
B B
+1.05V_M_ JTAG PCH_JTAG_TDI
CMOS setting
TPM setting
Keep ME RTC Registers
RC16
RC16
RC17 51_ 0402_1%RC17 51_0402 _1%
RC18 51_ 0402_1%RC18 51_0402 _1%
RC20 51_ 0402_1%RC20 51_0402 _1%
RC10 1K_ 0402_1%@RC1 0 1K_040 2_1%@
RC22 51_ 0402_1%@ RC22 51_ 0402_1%@
reference 479493 figure 7-1
Keep CMOS
12
12
PCH_JTAG_TDO
12
PCH_JTAG_TMS
12
PCH_JTAG_JTA GX
12
PCH_JTAG_TCK
+RTC_CELL
1
1
2
@
@
ME1 SHORT PA DS~D
ME1 SHORT PA DS~D
1 2
CC3 1U_ 0402_6.3V 6KCC3 1U_0402_ 6.3V6K
1 2
1 2
RC8 20K_040 2_5%RC8 20K_040 2_5%
RC6 20K_040 2_5%RC6 20K_040 2_5%
2
CC2 15P _0402_50 V8JCC2 15P_0402_ 50V8J
1
1
@
@
CMOS1 SHORT PADS~ D
CMOS1 SHORT PADS~ D
1 2
CC4
CC4
CMOS place near DIMM
1 2
2
2
1U_0402 _6.3V6K
1U_0402 _6.3V6K
YC1
YC1
32.768K HZ_12.5PF_Q 13FC135000 040
32.768K HZ_12.5PF_Q 13FC135000 040
1 2
RC4 0_0402_ 5%@RC4 0_0402_ 5%@
12
PCH_RTCRST#<9>
PCH_AZ_CO DEC_SDIN0<26>
ME_FWP<36>
PCH_JTAG_TRS T#<9>
PCH_JTAG_TCK<9>
PCH_JTAG_TDI<9>
PCH_JTAG_TDO<9>
PCH_JTAG_TMS<9>
PCH_JTAG_JTA GX<9>
PCH_RTCX1PCH_RTCX1_R
10M_0402_5%
10M_0402_5%
12
RC5
RC5
PCH_RTCX2
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
PCH_AZ_B ITCLK
PCH_AZ_S YNC
PCH_AZ_RS T#
PCH_AZ_CO DEC_SDIN0
1 2
RC9 1K_04 02_5%RC9 1K_ 0402_5%
PCH_AZ_S DOUT
T3 PAD~D@T3 PAD~ D@
T4 PAD~D@T4 PAD~ D@
T5 PAD~D@T5 PAD~ D@
PCH_JTAG_TRS T#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_JTA GX
UC1E
UC1E
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER
AV7
INTVRMEN
AV6
SRTCRST
AU7
RTCRST
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN/I2S1_TXD
AV10
HDA_DOCK_RST/I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
HASWELL_MCP_E
HASWELL_MCP_E
RTC
RTC
JTAG
JTAG
5 OF 19
5 OF 19
SATAAUDIO
SATAAUDIO
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
Rev1p2
Rev1p2
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
MPCIE_RST#
U1
HDD_DET#
V6
PCH_GPIO 36
AC1
mCARD_PC IE_SATA#
A12
SATA_IREF
L11
K10
C12
SATA_COMP
U3
SATA_ACT#
SATA_PRX_ DKTX_N0_C <3 4>
SATA_PRX_ DKTX_P0_C <34>
SATA_PTX_DK RX_N0_C <34>
SATA_PTX_DK RX_P0_C <34>
SATA_PRX_ DTX_N1_C <25 >
SATA_PRX_ DTX_P1_C <25>
SATA_PTX_DR X_N1_C <2 5>
SATA_PTX_DR X_P1_C <25>
SATA_PRX_ mSATATX_N3 <31>
SATA_PRX_ mSATATX_P3 <31>
SATA_PTX_m SATARX_N3 <31>
SATA_PTX_m SATARX_P3 <31>
MPCIE_RST# <31,7>
HDD_DET# <25 >
PCH_GPIO 36 <1 0>
mCARD_PC IE_SATA# <36>
12
RC14 0_0 402_5%@RC1 4 0_0402 _5%@
SATA_ACT# <40>
T1PAD~D @T1PAD~D @
T2PAD~D @T2PAD~D @
DOCK
SATA HDD (for G oliad 12 to MSA TA)
mSATA HDD(for W WAN card)
PCH Rx side need use strap pin to update PCIE +/-
+PCH_ASATA 3PLL
mCARD_PC IE_SATA#
SATA Impedance Compensation
SATA_COMP
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
1 2
HDD_DET#
1 2
+PCH_ASATA 3PLL
1 2
RC19 3.0 1K_0402_1 %R C19 3.01K_ 0402_1%
reference FFRD sch 0.5
+3.3V_RUN+1.05V_M
RC11100K_04 02_5% RC11100K_04 02_5%
RC1210K_040 2_5% RC1210K_040 2_5%
HDA for Codec
1 2
PCH_AZ_CO DEC_SDOUT<26>
PCH_AZ_CO DEC_SYNC<26>
PCH_AZ_CO DEC_RST#<26>
PCH_AZ_CO DEC_BITCLK<26>
A A
RC23 33_0402 _5%RC23 33_0402_5 %
RC24 33_0402 _5%RC24 33_0402_5 %
RC25 33_0402 _5%RC25 33_0402_5 %
RC26 33_0402 _5%
RC26 33_0402 _5%
27P_0402_50V8J
27P_0402_50V8J
@CC5
@
CC5
1
2
EMI depop location
5
1 2
1 2
1 2
EMC@
EMC@
PCH_AZ_S DOUT
PCH_AZ_S YNC
PCH_AZ_RS T#
PCH_AZ_B ITCLK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Title
Title
Title
Size Documen t Number Rev
Size Documen t Number Rev
Size Documen t Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(1/12)
MCP(1/12)
MCP(1/12)
LA-9431P
LA-9431P
LA-9431P
1
6 59Friday, May 17, 20 13
6 59Friday, May 17, 20 13
6 59Friday, May 17, 20 13
0.3
0.3
0.3
Page 7
5
HASWELL_MCP_E
SPI_PCH_DO2_64PCH_SPI_DO2
HASWELL_MCP_E
LPC
LPC
SPI C-LINK
SPI C-LINK
UC1G
UC1G
LPC_LAD0<25,29,36,37>
LPC_LAD1<25,29,36,37>
LPC_LAD2<25,29,36,37>
LPC_LAD3<25,29,36,37>
LPC_LFRAME#<25,29,36,37>
D D
+3.3V_M
1 2
1 2
reference PDG0.7
SPI_WP#_SEL<36>
PCH_SPI_DO2
PCH_SPI_DO3
PCH_SPI_CS0# SPI_PCH_CS0#_R
PCH_SPI_DIN SPI_DIN64
SPI_WP#_SEL
R1 1K_0402_5%R1 1K_0402_5%
R2 1K_0402_5%R2 1K_0402_5%
C C
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DO
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_DO3
reference PDG0.7
R3 0_0402_5%1@ R3 0_0402_5%1@
R4 33_0402_5%1@ R4 33_0402_5%1@
R6 33_0402_5%1@ R6 33_0402_5%1@
R8 0_0402_5%@R8 0_0402_5%@
1 2
1 2
1 2
AU14
LAD0
AW12
LAD1
AY12
LAD2
AW11
LAD3
AV12
LFRAME
AA3
SPI_CLK
Y7
SPI_CS0
Y4
SPI_CS1
AC2
SPI_CS2
AA2
SPI_MOSI
AA4
SPI_MISO
Y6
SPI_IO2
AF1
SPI_IO3
12
200 MIL SO8
reference PDG0.7
R23 0_0402_5%@R23 0_0402_5%@
1 2
R14 0_0402_5%4@ R14 0_0402_5%4@
1 2
R15 33_0402_5%4@ R15 33_0402_5%4@
R19 33_0402_5%4@ R19 33_0402_5%4@
1 2
SPI_DIN32PCH_SPI_DIN
SPI_PCH_DO2_32
12
10/100/1G LAN - -->
PCH_SPI_CS1# SPI_PCH_CS1#_R
PCH_SPI_DO2
SPI_WP#_SEL
SPI_CLK64SPI_CLK32
33_0402_5%
33_0402_5%
33_0402_5%
@
@
R45
R45
1 2
0.1U_0402_25V6
0.1U_0402_25V6
@
@
2
C85
C85
1
B B
33_0402_5%
@
@
R57
R57
1 2
0.1U_0402_25V6
0.1U_0402_25V6
@
@
2
C76
C76
1
WLAN (Mini Card 2)--->
ADD EMI solution(EMC)
+3.3V_RUN
PCI_CLK_LPC_0
PCI_CLK_LPC_1
A A
RP4
RP4
1 8
2 7
3 6
4 5
10K_8P4R_5%
10K_8P4R_5%
12
CC1512P_0402_50V8J @ CC1512P_0402_50V8J @
12
CC1412P_0402_50V8J @CC1412P_0402_50V8J @
DGPU_PWROK
MINI2CLK_REQ#
MINI1CLK_REQ#
MPCIE_RST#
WWAN (Mini Card 1)--->
DGPU_PWROK <10>
MPCIE_RST# <31,6>
32Mb Flash ROM
MMI--->
1
2
3
4
4
SMBUS
SMBUS
SML1ALERT/PCHHOT/GPIO73
7 OF 19
7 OF 19
64Mb Flash ROM
200 MIL SO8
U1
1@U1
1@
1
/CS
2
DO(IO1)
/HOLD(IO3)
3
/WP(IO2)
4
GND
W25Q64FVSSIQ_SO8
W25Q64FVSSIQ_SO8
U2
4@U2
4@
/CS
DO/IO1
/WP/IO2
GND
W25Q32FVSSIQ_SO8
W25Q32FVSSIQ_SO8
/HOLD/IO3
DI/IO0
DI(IO0)
VCC
CLK
AN2
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML0DATA
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST
Rev1p2
Rev1p2
+3.3V_M
8
VCC
7
6
SPI_CLK64
CLK
5
SPI_DO64 PCH_SPI_DO
+3.3V_M
0.1U_0402_25V6
0.1U_0402_25V6
8
7
SPI_PCH_DO3_32
6
5
SPI_DO32
+3.3V_RUN
PCH_TPM_LPC_EN<29>
+3.3V_RUN
CLK_PCIE_LAN#<28>
CLK_PCIE_LAN<28>
LANCLK_REQ#<10,28>
CLK_PCIE_MINI2#<31>
CLK_PCIE_MINI2<31>
MINI2CLK_REQ#<31>
CLK_PCIE_MMI#<30>
CLK_PCIE_MMI<30>
MMICLK_REQ#<30>
+3.3V_RUN
CLK_PCIE_MINI1#<31>
CLK_PCIE_MINI1<31>
MINI1CLK_REQ#<31>
PCI_CLK_LPC
PCH_SMB_ALERT#
AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
AL2
AN1
AK1
SML0DATA
AU4
PCH_GPIO73
AU3
SML1_SMBCLK
AH3
SML1_SMBDATA
AF2
PCH_CL_CLK1
AD2
PCH_CL_DATA1
AF4
PCH_CL_RST1#
C5
1@ C5
1@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
R5 33_0402_5%1@ R5 33_0402_5%1@
1 2
1 2
R7 33_0402_5%1@ R7 33_0402_5%1@
R9 33_0402_5%1@ R9 33_0402_5%1@
1 2
C6
4@ C6
4@
1 2
1 2
R16 33_0402_5%4@ R16 33_0402_5%4@
R20 33_0402_5%4@ R20 33_0402_5%4@
1 2
1 2
R21 33_0402_5%4@ R21 33_0402_5%4@
1 2
RC57 10K_0402_5%RC57 10K_0402_5%
1 2
RC56 10K_0402_5%RC56 10K_0402_5%
1 2
RC55 10K_0402_5%RC55 10K_0402_5%
SML1_SMBCLK <37>
PCIECLK_REQ0#
CLK_PCIE_LAN#
CLK_PCIE_LAN
LANCLK_REQ#
CLK_PCIE_MINI2#
CLK_PCIE_MINI2
MINI2CLK_REQ#
CLK_PCIE_MMI#
CLK_PCIE_MMI
MMICLK_REQ#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
MINI1CLK_REQ#
1 2
RC58 22_0402_5%EMC@RC58 22_0402_5%EMC@
1 2
RC61 22_0402_5%EMC@RC61 22_0402_5%EMC@
1 2
RC63 22_0402_5%EMC@RC63 22_0402_5%EMC@
3
PCH_SMB_ALERT# <11>
SML1_SMBDATA <37>
PCH_CL_CLK1 <31>
PCH_CL_DATA1 <31>
PCH_CL_RST1# <31>
PCH_SPI_DO3SPI_PCH_DO3_64
PCH_SPI_CLK
PCH_SPI_DO3
PCH_SPI_CLKSPI_CLK32
PCH_SPI_DO
UC1F
UC1F
C43
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
U2
PCIECLKRQ0/GPIO18
B41
CLKOUT_PCIE_N1
A41
CLKOUT_PCIE_P1
Y5
PCIECLKRQ1/GPIO19
C41
CLKOUT_PCIE_N2
B42
CLKOUT_PCIE_P2
AD1
PCIECLKRQ2/GPIO20
B38
CLKOUT_PCIE_N3
C37
CLKOUT_PCIE_P3
N1
PCIECLKRQ3/GPIO21
A39
CLKOUT_PCIE_N4
B39
CLKOUT_PCIE_P4
U5
PCIECLKRQ4/GPIO22
B37
CLKOUT_PCIE_N5
A37
CLKOUT_PCIE_P5
T2
PCIECLKRQ5/GPIO23
PCH_SPI_DO
PCH_SPI_DO
PCH_SPI_CLK
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_DIN
PCH_SPI_DIN
HASWELL_MCP_E
HASWELL_MCP_E
CLK_PCI_TPM_TCM <29>
CLK_PCI_5048 <36>
CLK_PCI_MEC <37>
SML0CLK
SML0DATA
CLOCK
CLOCK
SIGNALS
SIGNALS
6 OF 19
6 OF 19
R11 33_0402_5%2@ R11 33_0402_5%2@
R12 33_0402_5%5@ R12 33_0402_5%5@
R13 33_0402_5%2@ R13 33_0402_5%2@
R18 33_0402_5%5@ R18 33_0402_5%5@
R10 0_0402_5%2@ R10 0_0402_5%2@
R17 0_0402_5%5@ R17 0_0402_5%5@
R22 33_0402_5%2@ R22 33_0402_5%2@
R41 33_0402_5%5@ R41 33_0402_5%5@
RC29 0_0402_5%@ RC29 0_0402_5%@
RC31 0_0402_5%@ RC31 0_0402_5%@
RC33 0_0402_5%@ RC33 0_0402_5%@
RC35 0_0402_5%@ RC35 0_0402_5%@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
DIFFCLK_BIASREF
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
MEM_SMBCLKSML0CLK
MEM_SMBDATA
+3.3V_RUN
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
Rev1p2
Rev1p2
2
12
12
12
12
1 2
1 2
TAA_DO64
TAA_DO32
TAA_CLK64
TAA_CLK32
TAA_CS0#_R
TAA_CS1#_R
TAA_DIN64
TAA_DIN32
DDR_XDP_WAN_SMBDAT
DDR_XDP_WAN_SMBCLK
15
17
19
R122 10K_0402_5%R122 10K_0402_5%
R123 10K_0402_5%R123 10K_0402_5%
21
ACES_50185-02041-001
ACES_50185-02041-001
A25
XTAL24_IN
B25
XTAL24_OUT
K21
M21
C26
CLK_BIASREF
C35
MCP_TESTLOW1
C34
MCP_TESTLOW2
AK8
MCP_TESTLOW3
AL8
MCP_TESTLOW4
AN15
PCI_CLK_LPC_0
AP15
PCI_CLK_LPC_1
B35
A35
+3.3V_RUN
5
3 4
QC1A
QC1A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
LAN_SMBCLK <28>
LAN_SMBDATA <28>
NFC_SMBCLK <20>
NFC_SMBDATA <20>
+3.3V_M
CONN@
CONN@
JTAA1
JTAA1
2
112
4
334
6
556
8
TAA_DO3_64
778
10
TAA_DO3_32
9910
12
TAA_DO2_64
111112
14
TAA_DO2_32
131314
16
16
15
18
18
17
20
20
19
G22G
24
G23G
RC40 0_0402_5%@RC40 0_0402_5%@
1M_0402_5%
1M_0402_5%
RC44
RC44
1 2
T6
PAD~D
PAD~D
T7
PAD~D
PAD~D
2
G
G
6 1
S
D
S
D
QC1B
QC1B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
SGD
SGD
MEM_SMBCLK
MEM_SMBDATA
PCH_GPIO73
SML1_SMBCLK
SML1_SMBDATA
SML0CLK
SML0DATA
TAA Config
R43 33_0402_5%2@ R43 33_0402_5%2@
1 2
1 2
R48 33_0402_5%5@ R48 33_0402_5%5@
R58 33_0402_5%2@ R58 33_0402_5%2@
1 2
1 2
R59 33_0402_5%5@ R59 33_0402_5%5@
XB use 50185-02041-001
1 2
@T6
@
@T7
@
1 2
1 2
1 2
XTAL24_IN_R
RC650_0402_5% @RC650_0402_5% @
RC6422_0402_5% EMC_3@RC6422_0402_5% EMC_3@
RC6622_0402_5% EMC@RC6622_0402_5% EMC@
CLK_BIASREF
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4
3
1
4
24MHZ_12PF_X3G024000DC1H
24MHZ_12PF_X3G024000DC1H
2
PCI_CLK_LPC
1
DDR_XDP_WAN_SMBCLK <18,19,31,9>
DDR_XDP_WAN_SMBDAT <18,19,31,9>
1 2
1 2
Intel PDG 0.9
CC7
CC7
18P_0402_50V8J
18P_0402_50V8J
YC2
YC2
CC6
CC6
18P_0402_50V8J
18P_0402_50V8J
CLK_PCI_DOCK <34>
CLK_PCI_LPDEBUG <25>
+PCH_VCCACLKPLL
1 2
1 2
1 2
1 2
1 2
PCH_SPI_DO3
PCH_SPI_DO3
PCH_SPI_DO2
PCH_SPI_DO2
12
12
RC453.01K_0402_1% RC453.01K_0402_1%
RC4610K_0402_5% RC4610K_0402_5%
RC4710K_0402_5% RC4710K_0402_5%
RC5010K_0402_5% RC5010K_0402_5%
RC5210K_0402_5% RC5210K_0402_5%
12
RC282.2K_0402_5% RC282.2K_0402_5%
12
RC302.2K_0402_5% RC302.2K_0402_5%
12
RC3410K_0402_5% RC3410K_0402_5%
RC362.2K_0402_5% RC362.2K_0402_5%
RC372.2K_0402_5% RC372.2K_0402_5%
12
RC381K_0402_5% RC381K_0402_5%
12
RC391K_0402_5% RC391K_0402_5%
+3.3V_ALW_PCH
For RF request(EMC)
Every pin need one gnd by itself
5
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(2/12)
MCP(2/12)
MCP(2/12)
LA-9431P
LA-9431P
LA-9431P
1
7 59Friday, May 17, 2013
7 59Friday, May 17, 2013
7 59Friday, May 17, 2013
0.3
0.3
0.3
Page 8
5
HASWELL_MCP_E
D D
DDR_A_D[0..63]<18>
C C
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
UC1C
UC1C
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
HASWELL_MCP_E
DDR CHANNEL A
DDR CHANNEL A
4
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
AP33
AR32
AP32
AY34
AW34
AU34
AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
AP49
AR51
AP51
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
M_CLK_DDR#0 <18>
M_CLK_DDR0 <18>
M_CLK_DDR#1 <18>
M_CLK_DDR1 <18>
DDR_CKE0_DIMMA <18>
DDR_CKE1_DIMMA <18>
DDR_CS0_DIMMA# <18>
DDR_CS1_DIMMA# <18>
DDR_A_RAS# <18>
DDR_A_WE# <18>
DDR_A_CAS# <18>
DDR_A_BS0 <18>
DDR_A_BS1 <18>
DDR_A_BS2 <18>
DDR_A_MA[0..15] <18>
DDR_A_DQS#[0..7] <18>
DDR_A_DQS[0..7] <18>
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
3
UC1D
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
UC1D
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
DDR_B_D[0..63]<19>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
2
HASWELL_MCP_E
HASWELL_MCP_E
DDR CHANNEL B
DDR CHANNEL B
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
1
M_CLK_DDR#2 <19>
M_CLK_DDR2 <19>
M_CLK_DDR#3 <19>
M_CLK_DDR3 <19>
DDR_CKE2_DIMMB <19>
DDR_CKE3_DIMMB <19>
DDR_CS2_DIMMB# <19>
DDR_CS3_DIMMB# <19>
DDR_B_RAS# <19>
DDR_B_WE# <19>
DDR_B_CAS# <19>
DDR_B_BS0 <19>
DDR_B_BS1 <19>
DDR_B_BS2 <19>
DDR_B_MA[0..15] <19>
DDR_B_DQS#[0..7] <19>
DDR_B_DQS[0..7] <19>
Rev1p2
3 OF 19
3 OF 19
A A
Rev1p2
4 OF 19
4 OF 19
Rev1p2
Rev1p2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(3/12)
MCP(3/12)
MCP(3/12)
LA-9431P
LA-9431P
LA-9431P
1
8 59Friday, May 17, 2013
8 59Friday, May 17, 2013
8 59Friday, May 17, 2013
0.3
0.3
0.3
Page 9
+3.3V_ALW_PCH +RTC_CELL
+PCH_VCCDSW3_3
D D
+3.3V_RUN
+3.3V_ALW_PCH
RC136 1 0K_0402_5%RC136 10K_0402_5%
C C
PCH_JTAG_TDI<6>
H_PROCHOT#
1
@
@
CC149
CC149
22P_0402_50V8J
22P_0402_50V8J
2
ESD request, place near CPU side
B B
+1.05V_VCCST
1 2
RC113 49.9_0402_1%@ RC113 49.9_0402_1%@
1 2
RC114 62_0402_5%RC114 62_0402_5%
reference CRB
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC115
5
1 2
1 2
1 2
ME_SUS_PWR_ACK
USB_OC3#
SIO_EXT_WAKE#
KB_DET#
PCH_RSMRST#_R
1 2
RC96 0_ 0402_5%
RC96 0_ 0402_5%
XDP@
XDP@
PCH_JTAG_TMS<6>
H_CATERR#
H_PROCHOT#
H_CPUPWRGD
10K_0402_5%
10K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
12
RC115
RC115
SUS_STAT#/LPCPD#
PCH_PCIE_WAKE#
1
@
@
CC90
CC90
RC74 10K_0402_5%@RC74 10K _0402_5%@
RC71 10K_0402_5%RC71 10K_0402_5 %
RC81 8.2K_0402_5%@RC81 8.2K_0402_5%@
RP10
RP10
1 8
2 7
3 6
4 5
10K_8P4R_5%
10K_8P4R_5%
1 2
PCH_JTAG_TDO<6>
2
ME_RESET#
USB_OC3# <11>
SIO_EXT_WAKE# <12,36>
KB_DET# <12,38>
RC95 0_0402_5%XDP@ RC95 0_0402_5%XDP@
RC103 0_0402_5%
RC103 0_0402_5%
XDP@
XDP@
RC101 0_0402_5%
RC101 0_0402_5%
XDP@
XDP@
RUNPWROK<36,37>
ESD request
XDP_DBRESET#
RC76 8.2K_0402_5%@ RC76 8.2K_0402_5%@
PCH_DPWROK PCH_RSMRST#_R
ME_SUS_PWR_ACK_ R SUSA CK#_R
RESET_OUT# SYS_PWROK_R
SUSACK#<12,36>
SYS_PWROK<36,9>
RESET_OUT#<15,37>
1 2
PLTRST_NFC#<20>
PLTRST_USH#<29>
PLTRST_MMI#<30>
PLTRST_LAN#<28>
PLTRST_VMM2320#< 21>
XDP@ CC41
XDP@
0.1U_0402_25V6
0.1U_0402_25V6
1 2
1 2
1 2
RC300 0 _0402_5%@RC300 0_0402_5%@
1 2
RC89 0_0402_5%@ RC89 0_0402_5%@
1 2
RC90 0_0402_5%@ RC90 0_0402_5%@
1 2
RC91 0_0402_5%@ RC91 0_0402_5%@
1 2
RC92 0_0402_5%@ RC92 0_0402_5%@
PCH_RSMRST#_Q<38>
ME_SUS_PWR_ACK<37>
+3.3V_RUN
CC41
12
RUNPWROK
RUNPWROK
RUNPWROK
TRST#_XDP CPU_X DP_TRST#
RUNPWROK
PCH_JTAG_TRST#<6>
PCH_JTAG_JTAGX<6>
UC6
UC6
XDP@
XDP@
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
74CBTLV3126BQ_DHVQFN14_2P5X3
reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0
PCH_JTAG_TDO TDI_XDP_R
PCH_JTAG_TCK
H_PROCHOT#<37,46,47,48>
DDR3 COMPENSATION SIGNALS
A A
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
12
SM_RCOMP0
RC125200_0402_1% RC125200_0402_1%
12
SM_RCOMP1
RC129121_ 0402_1% RC129121_0402_1%
12
SM_RCOMP2
RC133100_0402_1% RC133100_0402_1%
5
4
RC72 0_0402_5%@RC72 0_0402_5%@
1
2
12
ME_RESET#
1 2
RC79 0_0402_5%@ RC79 0_0402_5%@
1 2
RC82 0_0402_5%@ RC82 0_0402_5%@
1 2
RC84 0_0402_5%@ RC84 0_0402_5%@
1 2
RC86 0_0402_5%@ RC86 0_0402_5%@
1 2
RC87 0_0402_5%@ RC87 0_0402_5%@
1 2
RC88 0_0402_5%@ RC88 0_0402_5%@
1 2
RC93 0_0402_5%@ RC93 0_0402_5%@
1 2
RC94 0_0402_5%@ RC94 0_0402_5%@
SIO_PWRBTN#<37,9>
AC_PRESENT<12,37>
PCH_BATLOW#<12>
SIO_SLP_S0#<37>
SIO_SLP_WLAN#<36>
GND PAD
12
CPU_XDP_TRST#
RC1350_0402_5% @RC1350_0 402_5% @
12
CPU_XDP_TCLK
RC970_0402_5% @RC970_0402_5% @
12
TDO_XDP
RC1230_0402_5% @RC1230_0402_5% @
12
RC1040_0402_5% @RC1040_0402_5% @
12
CPU_XDP_TCLK
RC1240_0402_5% @RC1240_0402_5% @
CPU_DETECT#<36>
PECI_EC<37>
1 2
RC117 5 6_0402_5%RC117 56_0402_5%
DDR3_DRAMRST#_CPU<18>
DDR_PG_CTRL<18>
4
1 2
+3.3V_RUN
5
0.1U_0402_25V6
0.1U_0402_25V6
P
B
O
A
G
74AHC1G09GW_TSSOP5~D
74AHC1G09GW_TSSOP5~D
3
3
1B
6
2B
8
3B
11
4B
7
GND
15
CPU_DETECT#
H_CATERR#
PECI_EC
H_PROCHOT#_R
H_CPUPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
CC8
@CC8
@
1 2
4
UC2
@UC2
@
SYS_RESET#
SYS_PWROK_R
PCH_PWROK
PM_APWROK_R
PCH_PLTRST#
PCH_RSMRST#_R
ME_SUS_PWR_ACK_ R
SIO_PWRBTN#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#
CPU_XDP_TDOTDO_XDPPCH_JTAG_TDO
CPU_XDP_TDITDI_XDP TDI_XDP_R
CPU_XDP_TMSTMS_XDP
SUSACK#_R
D61
K61
N62
K63
C61
AU60
AV60
AU61
AV15
AV61
SYS_RESET#
UC1H
UC1H
AK2
SUSACK
AC3
SYS_RESET
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST
AW6
RSMRST
AV4
SUSWARN/SUSPWRDNACK/GPIO30
AL7
PWRBTN
AJ8
ACPRESENT/GPIO31
AN4
BATLOW/GPIO72
AF3
SLP_S0
AM5
SLP_WLAN/GPIO29
UC1B
UC1B
PROC_DETECT
CATERR
PECI
PROCHOT
PROCPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1
THERMAL
THERMAL
MISC
MISC
PWR
PWR
DDR3
DDR3
PCH_PLTRST#
SYSTEM POWER MANAGEMENT
SYSTEM POWER MANAGEMENT
H_VCCST_PWRGD<15>
DDR_XDP_WAN_SMBDAT<18,19,31,7>
DDR_XDP_WAN_SMBCLK<18,19,31,7>
HASWELL_MCP_E
HASWELL_MCP_E
2 OF 19
2 OF 19
1
2
HASWELL_MCP_E
HASWELL_MCP_E
8 OF 19
8 OF 19
SIO_PWRBTN#<37,9>
CPU_PWR_DEBUG#<15>
JTAG
JTAG
PCH_JTAG_TCK<6>
3
+3.3V_RUN
CC9
@CC9
@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
5
P
B
4
PCH_PLTRST#_EC
O
A
G
UC3
UC3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
SUS_STAT/GPIO61
+1.05V_RUN
Place near JXDP1
RC5 need to close to JCPU1
1 2
RC105 1 K_0402_5%
RC105 1 K_0402_5%
XDP@
XDP@
H_CPUPWRGD
SYS_PWROK<36,9>
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
3
2
+3.3V_ALW2
CC82
@CC82
@
PCH_PLTRST#_EC <25,29,31,36,3 7>
SIO_SLP_A#
PM_APWROK
PM_APWROK<37>
RC144 0 _0402_5%@RC144 0_0402_5%@
AW7
WAKE
SLP_A
Rev1p2
Rev1p2
0.1U_0402_25V6
0.1U_0402_25V6
1
@
@
2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CPU_XDP_PRDY#
CPU_XDP_PREQ#
CPU_XDP_TCLK
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TDI
CPU_XDP_TDO
XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7
CC11
CC11
DSWODVREN
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SUS_STAT#/LPCPD#
SUSCLK
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_SUS#
SIO_SLP_LAN#
PCH_DPWROK < 36>
PCH_PCIE_WAKE# <37>
CLKRUN# <10,29,36,37>
T10 PAD~D@T10 PAD~D@
SIO_SLP_S5# <37>
T11 PAD~D@T11 PAD~D@
T12 PAD~D
T12 PAD~D
SIO_SLP_S4# <36,39,43>
SIO_SLP_S3# <36,39,43>
SIO_SLP_A# <36,39,44>
SIO_SLP_SUS# <36>
SIO_SLP_LAN# <28,36>
+1.05V_RUN
CPU_XDP_PREQ#
CPU_XDP_PRDY#
CFG0
CFG0<13>
CFG1
CFG1<13>
CFG2 CFG10
CFG2<13>
CFG3<13>
XDP_OBS0_R
XDP_OBS1_R
CFG4
CFG4<13>
CFG5
CFG5<13>
CFG6
CFG6<13>
CFG7
CFG7<13>
H_VCCST_PWRGD_XDP
CFD_PWRBTN#_XDP
CPU_PWR_DEBUG#_R PCH_PLTRST#_ECPCH_PLTRST#_EC
SYS_PWROK_XDP
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
PCH_JTAG_TCK_R
CPU_XDP_TCLK
+3.3V_ALW_PCH
T122PAD~D @T122PAD~D @
T126PAD~D @T126PAD~D @
T129PAD~D @T129PAD~D @
T130PAD~D @T130PAD~D @
T131PAD~D @T131PAD~D @
T132PAD~D @T132PAD~D @
DSWVRMEN
DPWROK
CLKRUN/GPIO32
SUSCLK/GPIO62
SLP_S5/GPIO63
SLP_S4
SLP_S3
SLP_SUS
SLP_LAN
0.1U_0402_25V6
0.1U_0402_25V6
1
@
@
CC10
CC10
2
RC106 1 K_0402_5%@RC106 1K_040 2_5%@
RC107 0 _0402_5%@RC107 0_0402_5%@
RC108 0 _0402_5%@RC108 0_0402_5%@
RC110 0 _0402_5%@RC110 0_0402_5%@
RC111 0 _0402_5%@RC111 0_0402_5%@
RC112 0 _0402_5%@RC112 0_0402_5%@
RC142 0 _0402_5%@RC142 0_0402_5%@
J62
PRDY
K62
PREQ
E60
E61
E59
F63
F62
J60
H60
H61
H62
K59
H63
K60
J61
Rev1p2
Rev1p2
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
0.1U_0402_25V6
0.1U_0402_25V6
5
1
P
B
O
2
A
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
1 2
@
@
JXDP1
JXDP1
1
GND0
3
OBSFN_A0
5
OBSFN_A1
7
GND2
9
OBSDATA_A0
11
OBSDATA_A1
13
GND4
15
OBSDATA_A2
17
OBSDATA_A3
19
GND6
21
OBSFN_B0
23
OBSFN_B1
25
GND8
27
OBSDATA_B0
29
OBSDATA_B1
31
GND10
33
OBSDATA_B2
35
OBSDATA_B3
37
GND12
39
PWRGOOD/HOOK0
41
HOOK1
43
VCC_OBS_AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
XDP@
XDP@
RC102
RC102
1K_0402_5%
1K_0402_5%
1 2
SYS_PWROK_XDP
1
CC48
@CC48
@
0.1U_0402_25V6
0.1U_0402_25V6
2
Place near JXDP1.47
2
1 2
4
PM_APWROK_R
UC7
UC7
SAMTE_BSH-030-01-L-D-A CONN@
SAMTE_BSH-030-01-L-D-A CONN@
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
Place near JXDP1.48
XDP_DBRESET#
1
330K_0402_1%
330K_0402_1%
RC73
RC73
1 2
DSWODVREN
330K_0402_1%
330K_0402_1%
@RC78
@
RC78
1 2
DSWODVREN - ON DIE DSW VR ENABLE
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
+1.05V_RUN
1
2
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
+PCH_VCCDSW3_3
CFG17
CFG16
CFG8
CFG9
CFG11CFG3
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
XDP_RST#_R
XDP_DBRESET#
TDO_XDP
TRST#_XDP
TDI_XDP
TMS_XDP
CFG3_R
CC68
XDP@ CC68
XDP@
0.1U_0402_25V6
0.1U_0402_25V6
PCH_RTCRST#< 6>
POWER_SW #_MB<37,40>
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
POWER_SW #_MB
SYS_RESET#
SIO_SLP_S0#
CFG17 <13>
CFG16 <13>
CFG8 <13>
CFG9 <13>
CFG10 <13>
CFG11 <13>
CFG19 <13>
CFG18 <13>
CFG12 <13>
CFG13 <13>
CFG14 <13>
CFG15 <13>
RC109 1K_0402_5%
RC109 1K_0402_5%
XDP@
XDP@
1 2
RC99 1K_0402_5%
RC99 1K_0402_5%
XDP@
XDP@
TDO_XDP
CFG3
RC280 51_0402_1%@ RC280 51_0402_1%@
PU/PD for JTAG signals
XDP_DBRESET#
CPU_XDP_TMS
CPU_XDP_TDI
CPU_XDP_PREQ#
CPU_XDP_TDO
CPU_XDP_TCLK
CPU_XDP_TRST#
RC116 1K_0402_5%RC116 1K _0402_5%
RC118 51_0402_1%@ RC118 51_0402_1%@
RC119 51_0402_1%@ RC119 51_0402_1%@
RC120 51_0402_1%@ RC120 51_0402_1%@
RC122 51_0402_1%RC122 51_0402_1%
RC127 51_0402_1%RC127 51_0402_1%
RC131 51_0402_1%@ RC131 51_0402_1%@
12
12
12
12
12
12
12
12
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(4/12)
MCP(4/12)
MCP(4/12)
LA-9431P
LA-9431P
LA-9431P
1
JAPS1
CONN@JAPS1
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND
20
GND
ACES_50506-01841-P01
ACES_50506-01841-P01
+1.05V_RUN
+3.3V_RUN
+1.05V_RUN
9 59Friday, May 17, 2013
9 59Friday, May 17, 2013
9 59Friday, May 17, 2013
0.3
0.3
0.3
Page 10
5
4
HASWELL_MCP_E
UC1A
UC1A
HASWELL_MCP_E
3
2
1
DDI1_LANE_N0<23>
DDI1_LANE_P0<23>
DDI1_LANE_N1<23>
DDI1_LANE_P1<23>
DDI1_LANE_N2<23>
DDI1_LANE_P2<23>
DDI1_LANE_N3<23>
D D
+3.3V_RUN
C C
1 2
RC137 10K_0402_5%RC137 10K_0402_5%
1 2
RC140 10K_0402_5%RC140 10K_0402_5%
1 2
RC202 10K_0402_5%RC202 10K_0402_5%
1 2
RC152 100K_0402_5%@RC152 100K_0402_5%@
RC154 1K_0402_5%@RC154 1K_0402_5%@
+3.3V_RUN
RP6
RP6
1 8
2 7
3 6
4 5
10K_8P4R_5%
10K_8P4R_5%
12
CONTACTLESS_DET#
TOUCHPAD_INTR#
TOUCH_RST_N_GYRO_INT1
ENVDD_PCH
CODEC_IRQ
CLKRUN#
LANCLK_REQ#
HDD_FALL_INT
PCH_GPIO36
CLKRUN# <29,36,37,9>
LANCLK_REQ# <28,7>
PCH_GPIO36 <6>
DDI1_LANE_P3<23>
DDI2_LANE_N0<27>
DDI2_LANE_P0<27>
DDI2_LANE_N1<27>
DDI2_LANE_P1<27>
DDI2_LANE_N2<27>
DDI2_LANE_P2<27>
DDI2_LANE_N3<27>
DDI2_LANE_P3<27>
CONTACTLESS_DET#<29>
DGPU_PWROK<7>
PIRQ#_TPM<12>
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
DDI2_LANE_N0
DDI2_LANE_P0
DDI2_LANE_N1
DDI2_LANE_P1
DDI2_LANE_N2
DDI2_LANE_P2
DDI2_LANE_N3
DDI2_LANE_P3
EDP_BIA_PWM<22>
PANEL_BKLEN<22>
ENVDD_PCH<22,36>
T13 PAD~D@ T13 PAD~D@
TOUCHPAD_INTR#
TOUCH_RST_N_GYRO_INT1
CODEC_IRQ
EDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
DGPU_PWROK
PIRQ#_TPM
HDD_FALL_INT
C54
C55
B58
C58
B55
A55
A57
B57
C51
C50
C53
B54
C49
B50
A53
B53
AD4
B8
A9
C6
U6
P4
N4
N2
U7
L1
L3
R5
L4
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
UC1I
UC1I
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDI EDP
DDI EDP
1 OF 19
1 OF 19
HASWELL_MCP_E
HASWELL_MCP_E
eDP SIDEBAND
eDP SIDEBAND
GPIO
GPIO
9 OF 19
9 OF 19
DISPLAY
DISPLAY
EDP_RCOMP
EDP_DISP_UTIL
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
reference PDG 0.9
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
Rev1p2
Rev1p2
DDPB_HPD
DDPC_HPD
EDP_HPD
Rev1p2
Rev1p2
C45
EDP_CPU_LANE_N0
B46
EDP_CPU_LANE_P0
A47
EDP_CPU_LANE_N1
B47
EDP_CPU_LANE_P1
C47
C46
A49
B49
A45
EDP_CPU_AUX#
B45
EDP_CPU_AUX
D20
EDP_COMP
A43
B9
CPU_DPB_CTRLCLK
C9
CPU_DPB_CTRLDAT
D9
CPU_DPC_CTRLCLK
D11
CPU_DPC_CTRLDAT
C5
CPU_DPB_AUX#
B6
CPU_DPC_AUX#
B5
CPU_DPB_AUX
A6
CPU_DPC_AUX
C8
DPB_HPD
A8
DPC_HPD
D6
100K_0402_5%
100K_0402_5%
12
EDP_CPU_LANE_N0 <22>
EDP_CPU_LANE_P0 <22>
EDP_CPU_LANE_N1 <22>
EDP_CPU_LANE_P1 <22>
EDP_CPU_AUX# <2 2>
EDP_CPU_AUX <22 >
CPU_DPB_CTRLCLK <23>
CPU_DPB_CTRLDAT <23>
CPU_DPC_CTRLCLK <27>
CPU_DPC_CTRLDAT <27>
CPU_DPC_AUX# <27>
CPU_DPC_AUX <27>
DPB_HPD <23>
DPC_HPD <27>
EDP_CPU_HPD <22>
0.1U_0402_25V6
0.1U_0402_25V6
@
@
CC450
CC450
RC158
RC158
1
2
ESD solution for black screen issue
Intel WW18 Strapping option
Intel WW18 Strapping option
COMPENSATION PU FOR eDP
EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
follow intel feedback
+VCCIOA_OUT
12
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
CPU_DPB_AUX#
CPU_DPC_AUX#
DPC_HPD
CPU_DPB_AUX
CPU_DPC_AUX
RC13424.9_0402_1% RC13424.9_0402_1%
+3.3V_RUN
12
RC1392.2K_0402_5% RC1392.2K_0402_5%
12
RC1412.2K_0402_5% RC1412.2K_0402_5%
12
RC1432.2K_0402_5% RC1432.2K_0402_5%
12
RC1452.2K_0402_5% RC1452.2K_0402_5%
12
RC147100K_0402_5% RC147100K_0402_5%
12
RC149100K_0402_5% RC149100K_0402_5%
12
RC151100K_0402_5% RC151100K_0402_5%
12
RC153100K_0402_5% RC153100K_0402_5%
12
RC155100K_0402_5% RC155100K_0402_5%
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(5/12)
MCP(5/12)
MCP(5/12)
LA-9431P
LA-9431P
LA-9431P
10 59Friday, May 17, 2013
10 59Friday, May 17, 2013
10 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 11
5
D D
PCIE_PRX_MMITX_N5<30>
MMI -->
C C
10/100/1G LAN --->
WLAN (Mini Card 2)--->
PCIE_PRX_MMITX_P5<30>
PCIE_PTX_MMIRX_N5<30>
PCIE_PTX_MMIRX_P5<30>
PCIE_PRX_GLANTX_N3<28>
PCIE_PRX_GLANTX_P3<28>
PCIE_PTX_GLANRX_N3<28>
PCIE_PTX_GLANRX_P3<28>
PCIE_PRX_WLANTX_ N4<31>
PCIE_PRX_WLANTX_ P4<31>
PCIE_PTX_WLANRX_ N4<31>
PCIE_PTX_WLANRX_ P4<31>
PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
PCIE_PTX_GLANRX_N3
PCIE_PTX_GLANRX_P3
PCIE_PRX_WLANTX_ N4
PCIE_PRX_WLANTX_ P4
PCIE_PTX_WLANRX_ N4
PCIE_PTX_WLANRX_ P4
Ext USB Port 2 <----
B B
+PCH_AUSB3PLL
reference CRB 3.01K 1%
RC161 3.01K_0402_1%RC 161 3.01K_0402_1%
RC163 0_0402_5%@ RC163 0_0402_5%@
1 2
1 2
T16 PAD~D@T16 PAD~D@
T17 PAD~D@T17 PAD~D@
4
PCIE_PRX_MMITX_N5
PCIE_PRX_MMITX_P5
PCIE_PTX_MMIRX_N5
PCIE_PTX_MMIRX_P5
USB3RN3<32>
USB3RP3<3 2>
USB3TN3<32>
USB3TP3<32>
PCH_PCIE_RCOMP
PCH_PCIE_IREF
F10
E10
C23
C22
F8
E8
B23
A23
H10
G10
B21
C21
E6
F6
B22
A21
G11
F11
C29
B30
F13
G13
B29
A29
G17
F17
C30
C31
F15
G15
B31
A31
E15
E13
A27
B27
UC1K
UC1K
PERN5_L0
PERP5_L0
PETN5_L0
PETP5_L0
PERN5_L1
PERP5_L1
PETN5_L1
PETP5_L1
PERN5_L2
PERP5_L2
PETN5_L2
PETP5_L2
PERN5_L3
PERP5_L3
PETN5_L3
PETP5_L3
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
PCIe
PCIe
HASWELL_MCP_E
HASWELL_MCP_E
11 OF 19
11 OF 19
3
AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USBP0ÂUSBP0+
USBP1ÂUSBP1+
USBP2ÂUSBP2+
USBP3ÂUSBP3+
USBP4ÂUSBP4+
USBP5ÂUSBP5+
USBP6ÂUSBP6+
USBP7ÂUSBP7+
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB3RN1
USB
USB
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USBRBIAS
RSVD
RSVD
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
Rev1p2
Rev1p2
USBP0- <33>
USBP0+ <33>
USBP1- <35>
USBP1+ <35>
USBP2- <31>
USBP2+ <31>
USBP3- <22>
USBP3+ <22>
USBP4- <29>
USBP4+ <29>
USBP5- <32>
USBP5+ <32>
USBP6- <31>
USBP6+ <31>
USBP7- <22>
USBP7+ <22>
USB3RN1 <35>
USB3RP1 <35>
USB3TN1 <35>
USB3TP1 <35>
USB3RN2 <33>
USB3RP2 <33>
USB3TN2 <33>
USB3TP2 <33>
T14PAD~D @T14PAD~D @
T15PAD~D @T15PAD~D @
USB_OC0# <33>
USB_OC1# <35>
USB_OC2# <33>
USB_OC3# <9>
2
----->Ext Port 1 and DOCK2 (USB SW)
----->Ext Port 2 IO/B
----->WLAN/BT
----->Camera
----->USH
----->Ext Port 3 and DOCK1(USB SW)
----->WWAN
----->Touch
----->Ext USB3 Port 1
USBRBIAS
----->Ext USB3 Port 3 IO/B
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
USB_OC1#
22.6_0402_1%
22.6_0402_1%
12
RC159
RC159
1 2
1
+3.3V_ALW_PCH
RC16610K_0402_5% RC16610K_0402_5%
+3.3V_ALW_PCH
RP5
RP5
USB_OC2#
USB_OC0#
PCH_SMB_ALERT#<7>
MEDIACARD_PWR EN<12,30>
A A
PCH_SMB_ALERT#
MEDIACARD_PWR EN
18
27
36
45
10K_8P4R_5%
10K_8P4R_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(6/12)
MCP(6/12)
MCP(6/12)
LA-9431P
LA-9431P
LA-9431P
11 59Friday, May 17, 2013
11 59Friday, May 17, 2013
11 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 12
5
LAN_WAKE#<28,37>
+3.3V_RUN
D D
C C
B B
RC170 100K_0402_5%RC170 100K_0402_5 %
RC199 100K_0402_5%RC199 100K_0402_5 %
+PCH_VCCDSW3 _3
RC197 10K_0402_5%RC197 10K_0402_5%
RC206 10K_0402_5%RC206 10K_0402_5%
+3.3V_ALW_PCH
RC200 10K_0402_5%RC200 10K_0402_5%
RC205 10K_0402_5%RC205 10K_0402_5%
RC211 100K_0402_5%RC211 100K_0402_5 %
RC210 100K_0402_5%RC210 100K_0402_5 %
RC169 10K_0402_5%
RC169 10K_0402_5%
@
@
RC215 10K_0402_5%RC215 10K_0402_5%
+3.3V_RUN +3.3V_RUN
1K_0402_5%
1K_0402_5%
12
@RC283
@
RC283
PCH_GPIO66
1K_0402_5%
1K_0402_5%
12
@RC288
@
RC288
1 2
RC301 0_0402_5%@RC301 0_0402_5%@
12
12
SIO_EXT_SCI#
12
PM_LANPHY_ENABLE
12
EC_WAKE#
suppoer DSW mode
12
PCH_GPIO44
12
MEDIACARD_IRQ#
12
12
12
12
GPIO66 GPIO86
TOP-BLOCK SWAP OVERRIDE
Low depop RC288 (DEFAULT) :Enable
High pop RC288:Diable
503118_503118_LPT_LP_PCH_EDS_Rev1_0
MPHYP_PWR_EN
3.3V_CAM_EN#
NFC_IRQ
MPHYP_PWR_EN
PCH_AUDIO_EN
EC_WAKE#
+3.3V_ALW_PCH
10K_0402_5%
10K_0402_5%
12
RC218
RC218
1K_0402_5%
1K_0402_5%
12
@RC287
@
RC287
@
@
BBS_BIT
RP7
RP7
1 8
2 7
3 6
4 5
10K_8P4R_5%
10K_8P4R_5%
BOOT BIOS STRAP BIT BBS
HIGH
LOW(DEFAULT)
LPC
SPI
PM_LANPHY_ENABLE<28>
MEDIACARD_RST#<30>
MEDIACARD_PWR EN<11,30>
TOUCH_PANEL_INTR#<22>
SIO_EXT_WAKE#<36,9>
LAN_RST#<28>
T139 PAD~D@ T139 PAD~D@
EC_WAKE#<37>
PCH_NFC_RST<20>
NFC_IRQ<20>
NFC_DET#<20>
MEDIACARD_IRQ#<30>
T140 PAD~D@ T140 PAD~D@
T141 PAD~D@ T141 PAD~D@
MPHYP_PWR_EN<39>
KB_DET#<38,9>
T138 PAD~D@ T138 PAD~D@
3.3V_CAM_EN#<22>
SIO_EXT_SMI#<37>
T137 PAD~D@ T137 PAD~D@
mSATA_DEVSLP<31>
HDD_DEVSLP<25>
SIO_EXT_SCI#<37>
MEDIACARD_RST#
PCH_GPIO46
SUSACK#
SIO_EXT_SMI#
4
PCH_AUDIO_EN
SIO_EXT_WAKE#
PM_LANPHY_ENABLE
PCH_GPIO15
PCH_GPIO17
EC_WAKE#
NFC_IRQ
MEDIACARD_RST#
MEDIACARD_PWR EN
SLATE_MODE_R
NFC_DET#
PCH_GPIO44
PCH_GPIO48
PCH_GPIO49
TOUCH_PANEL_INTR#
MPHYP_PWR_EN
KB_DET#
PCH_GPIO14
3.3V_CAM_EN#
SIO_EXT_SMI#
PCH_GPIO46
PCH_GPIO9
PCH_GPIO10 I2C1_SDA_TCH_PAD
SIO_EXT_SCI#
SPKR
SPKR<26>
+3.3V_ALW_PCH
1K_0402_5%
1K_0402_5%
12
RC190
RC190
PCH_GPIO15
GPIO15 GPIO81
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3
AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3
AM3
AM2
P2
C4
L2
N5
V2
SUSACK# <36,9>
UC1J
UC1J
BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46
GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
+3.3V_RUN
1K_0402_5%
1K_0402_5%
12
GPIO
GPIO
@RC222
@
RC222
SPKR
NO REBOOT STRAP
HIGH
LOW(DEFAULT)
HASWELL_MCP_E
HASWELL_MCP_E
10 OF 19
10 OF 19
3
CPU/
CPU/
MISC
MISC
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_MISO/GPIO89
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
LPIO
LPIO
UART0_CTS/GPIO94
TOUCH_PANEL_INTR#
THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI_MOSI/GPIO90
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
Rev1p2
Rev1p2
I2C1_SDA_TCH_PAD
I2C1_SCL_TCH_PAD
D60
V4
T4
AW15
AF20
AB21
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
+3.3V_RUN
12
12
H_THERMTRIP#
H_THERMTRIP#_R
SIO_RCIN#
IRQ_SERIRQ
PCH_OPI_COMP
PCH_GPIO83
PCH_GPIO84
PCH_GPIO85
BBS_BIT
PCH_GPIO87
3.3V_TP_EN
CPPE#
CPUSB#
LCD_CBL_DET#
I2C0_SDA
I2C0_SCL
I2C1_SCL_TCH_PAD
USH_DET#
CAM_MIC_CBL_DET#
PCH_GPIO66
TPM_ID0
TPM_ID1
SLP_ME_CSW_DE V#
RC174 0_0402_5%@ RC174 0_0402_5%@
RC176 0_0402_5%@ RC176 0_0402_5%@
RC181
RC181
10K_0402_5%
10K_0402_5%
RC180
@R C180
@
10K_0402_5%
10K_0402_5%
non use GPIO:
2
100P_0402_50V8J
100P_0402_50V8J
1
@
@
CC91
CC91
2
ESD request
RC172 0_0402_5%@ RC172 0_0402_5%@
SIO_RCIN# <37>
IRQ_SERIRQ <29,36,37>
T18 PAD~D@T18 PAD~D@
T19 PAD~D@T19 PAD~D@
3.3V_TS_EN <22>
3.3V_HDD_EN <31>
CPPE# <31>
CPUSB# <31>
LCD_CBL_DET# <22>
USH_DET# <29>
CAM_MIC_CBL_DET# <22>
SLP_ME_CSW_DE V# <36>
12
PCH_GPIO83
12
12
I2C1_SDA_TCH_PAD <38>
I2C1_SCL_TCH_PAD <38>
H_THERMTRIP# <37>
PCH_BATLOW#<9>
AC_PRESENT<37,9>
1 2
I2C1_SDA_VMM <21>
I2C1_SCL_VMM <21>
PIRQ#_TPM<10>
RC292100_0402_5% 7@RC292100_0402_5% 7@
PIRQ#_TPM
PCH_GPIO83
SIO_RCIN#
3.3V_TS_EN
PCH_GPIO84
PCH_GPIO85
3.3V_TP_EN
PCH_GPIO9
SLATE_MODE_R
PCH_BATLOW#
AC_PRESENT
IRQ_SERIRQ
USH_DET#
LCD_CBL_DET#
CPPE#
CAM_MIC_CBL_DET#
CPUSB#
I2C1_SDA_TCH_PAD
I2C1_SCL_TCH_PAD
TPM_ID0
TPM_ID1
SLP_ME_CSW_DE V#
3.3V_HDD_EN
I2C0_SDA
I2C0_SCL
PCH_GPIO87
RP9
RP9
10K_8P4R_5%
10K_8P4R_5%
reference PDG0.9
H_THERMTRIP#
PCH_OPI_COMP
1
10K_8P4R_5%
10K_8P4R_5%
10K_8P4R_5%
10K_8P4R_5%
+3.3V_ALW_PCH
18
27
36
45
1 2
1 2
RP2
RP2
RP8
RP8
12
R241K_0402_5% R241K_0402_5%
12
12
12
12
12
12
12
12
12
12
12
12
12
12
+3.3V_RUN
18
27
36
45
18
27
36
45
+PCH_VCCDSW3 _3
+1.05V_VCCST
RC16849.9_0402_1% RC16849.9_0402_1%
+3.3V_RUN
RC17810K_ 0402_5% RC17810K_0402 _5%
RC28210K_ 0402_5% RC28210K_0402 _5%
RC18910K_ 0402_5% RC18910K_0402 _5%
RC185100K_0402_5% RC185100K_0402_5%
RC19310K_ 0402_5% RC19310K_0402 _5%
RC191100K_0402_5% RC191100K_0402_5%
RC2012.2K_0402 _5% RC2012.2K_0402_5%
RC2032.2K_0402 _5% RC2032.2K_0402_5%
RC28410K_ 0402_5% RC28410K_0402 _5%
RC28520K_0402_5% RC28520K_0402_5%
RC28910K_ 0402_5% RC28910K_0402 _5%
RC29510K_ 0402_5% RC29510K_0402 _5%
RC2042.2K_0402 _5% RC2042.2K_0402_5%
RC2082.2K_0402 _5% RC2082.2K_0402_5%
RC21610K_0402_5% RC21610K_0402_5%
GPIO0 GPIO3 GPIO10 GPIO14
GPIO17 GPIO21 GPIO22 GPIO24
GPIO36 GPIO38 GPIO48 GPIO49
GPIO51 GPIO54 GPIO59 GPIO60
A A
GPIO66 GPIO70 GPIO73 GPIO79
GPIO87 GPIO93 GPIO94
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(7/12)
MCP(7/12)
MCP(7/12)
LA-9431P
LA-9431P
LA-9431P
12 59Friday, May 17, 2013
12 59Friday, May 17, 2013
12 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 13
5
4
3
2
1
CFG STRAPS for CPU
D D
UC1S
UC1S
AC60
12
CFG_RCOMP
TDI_IREF
CFG0
CFG1
CFG3
CFG4
CFG8
CFG9
CFG10
CFG_RCOMP
TDI_IREF
AC62
AC63
AA63
AA60
AA62
AA61
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
U63
U62
V63
A5
E1
D1
J20
H18
B12
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
CFG0<9>
CFG1<9>
CFG2<9>
CFG3<9>
CFG4<9>
CFG5<9>
CFG6<9>
CFG7<9>
CFG8<9>
CFG9<9>
C C
B B
CFG10<9>
CFG11<9>
CFG12<9>
CFG13<9>
CFG14<9>
CFG15<9>
CFG16<9>
CFG18<9>
CFG17<9>
CFG19<9>
T33 PAD~D@T33 PAD ~D@
T35 PAD~D@T35 PAD ~D@
T37 PAD~D@T37 PAD ~D@
T38 PAD~D@T38 PAD ~D@
T39 PAD~D@T39 PAD ~D@
RC235 49.9_0402_1%RC235 49.9_0402_1%
1 2
RC236 8.2K_0402_ 1%RC236 8.2K_0402_1 %
HASWELL_MCP_E
HASWELL_MCP_E
RESERVED
RESERVED
19 OF 19
19 OF 19
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
RSVD
RSVD
VSS
VSS
RSVD
RSVD
Rev1p2
Rev1p2
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
PROC_OPI_RCOMP
AV62
D58
P22
N21
P20
R20
PROC_OPI_RCOMP
1 2
RC23749.9_0402_1% RC23749.9_0402_1%
T20PAD~D @T20PAD~D @
T21PAD~D @T21PAD~D @
T22PAD~D @T22PAD~D @
T23PAD~D @T23PAD~D @
T24PAD~D @T24PAD~D @
T25PAD~D @T25PAD~D @
T26PAD~D @T26PAD~D @
T27PAD~D @T27PAD~D @
T28PAD~D @T28PAD~D @
T29PAD~D @T29PAD~D @
T30PAD~D @T30PAD~ D @
T31PAD~D @T31PAD~ D @
T32PAD~D @T32PAD~ D @
T34PAD~D @T34PAD~ D @
T36PAD~D @T36PAD~ D @
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
CFG0
1:(Default) Normal Operation; No stall
0:Lane Reversed
PCH/PCH LESS MODE SELECTION
CFG1
1:(Default) Normal Operation
0:Lane Reversed
CFG0
CFG1
1K_0402_1%
1K_0402_1%
12
@RC232
@
RC232
1K_0402_1%
1K_0402_1%
12
@RC233
@
RC233
CFG10
CFG9
1K_0402_1%
1K_0402_1%
12
@RC239
@
RC239
1K_0402_1%
1K_0402_1%
12
@RC240
@
RC240
CFG8
1K_0402_1%
1K_0402_1%
12
@RC241
@
RC241
CFG4
1K_0402_1%
1K_0402_1%
12
RC238
RC238
Display Port Presence Strap
SAFE MODE BOOT
1: POWER FEATURES ACTIVATED DURING
RESET
A A
CFG10
0: POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED
NO SVID PROTOCOL CAPABLE VR CONNECTED
1: VRS support SVID protocol are present
0:No VR support SVID is present
CFG9
The chip will not generate(OR Respond to)
SVID activity
ALLOW THE USE OF NOA ON LOCKED UNITS
1: Enable(Default): Noa will be disable in
locked units and enable in un-locked units
CFG8
0: Enable Noa will be available pegardless of
the locking of the unit
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(8/12)
MCP(8/12)
MCP(8/12)
LA-9431P
LA-9431P
LA-9431P
13 59Friday, May 17, 2013
13 59Friday, May 17, 2013
13 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 14
5
4
3
2
1
D D
UC1Q
UC1Q
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
C C
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
Package Daisy Chain:
HASWELL_MCP_E
HASWELL_MCP_E
17 OF 19
17 OF 19
3
1
12
RC2540_0402_5% @RC2540_ 0402_5% @
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
Rev1p2
Rev1p2
12
RC2690_0402_5% @RC2690_ 0402_5% @
A3
DC_TEST_A3_B3
A4
DC_TEST_A4
A60
DC_TEST_A60
A61
DC_TEST_A61_B61
A62
DC_TEST_A62
AV1
DC_TEST_AV1
AW1
DC_TEST_AW1
AW2
DC_TEST_AY2_AW2
AW3
DC_TEST_AY3_AW3
AW61
DC_TEST_AY61_AW61
AW62
DC_TEST_AY62_AW62
AW63
DC_TEST_AW63
2
12
RC2660_0402_5% @RC2660_ 0402_5% @
12
RC2680_0402_5% @RC2680_ 0402_5% @
4
1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
HASWELL_MCP_E
UC1R
UC1R
AT2
T50 P AD~D@T50 PAD~D@
T52 P AD~D@T52 PAD~D@
T54 P AD~D@T54 PAD~D@
T58 P AD~D@T58 PAD~D@
T60 P AD~D@T60 PAD~D@
T62 P AD~D@T62 PAD~D@
B B
RSVD_AT2
RSVD_AU44
RSVD_AV44
RSVD_D15
RSVD_F22
RSVD_H22
RSVD_J21
AU44
AV44
RSVD
RSVD
RSVD
D15
RSVD
F22
RSVD
H22
RSVD
J21
RSVD
HASWELL_MCP_E
18 OF 19
18 OF 19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Rev1p2
Rev1p2
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
RSVD_N23
RSVD_R23
RSVD_T23
RSVD_U10
RSVD_AL1
RSVD_AM11
RSVD_AP7
RSVD_AU10
RSVD_AU15
RSVD_AW14
RSVD_AY14
@
T48PAD~D@T48PAD~D
@
T49PAD~D@T49PAD~D
@
T51PAD~D@T51PAD~D
@
T53PAD~D@T53PAD~D
@T55 P AD~D@T55 PAD~D@
T56PAD~D@T56PAD~D
@
T57PAD~D@T57PAD~D
@
T59PAD~D@T59PAD~D
@
T61PAD~D@T61PAD~D
@
T63PAD~D@T63PAD~D
@
T64PAD~D@T64PAD~D
@
T65PAD~D@T65PAD~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(9/12)
MCP(9/12)
MCP(9/12)
LA-9431P
LA-9431P
LA-9431P
14 59Friday, May 17, 2013
14 59Friday, May 17, 2013
14 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 15
5
+1.05V_RUN
150_0402_1%
150_0402_1%
12
RC253
RC253
CPU_PWR_DEBU G#
10K_0402_5%
10K_0402_5%
D D
C C
RESET_OUT#<37,9>
SVID ALERT
VIDALERT_N<46>
SVID DATA
B B
VIDSOUT<46>
12
@
@
RC258
RC258
H_VR_EN H_VR_READY
RC263 0_0402_5%@ RC263 0_0402_5%@
+1.05V_VCCST
+1.05V_VCCST
12
RC25610K_ 0402_5% RC25610K_0402 _5%
12
75_0402_1%
75_0402_1%
12
RC244
RC244
110_0402_1%
110_0402_1%
12
RC249
RC249
VIDSOUT
VCC_SENSE
VCCSENSE<46>
+1.05V_RUN +VCCIO_OUT
RC242 0_0603_ 5%@RC242 0_0603_5%@
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
+1.05V_VCCST +3.3V_RUN
12
@
@
RC255
RC255
10K_0402_5%
10K_0402_5%
UC4
UC4
NC1VCC
2
A
3
GND
74AUP1G07GW_TSSOP5
74AUP1G07GW_TSSOP5
CAD Note: Place the PU resistors close to CPU
RC224 close to CPU 300 - 1500mils
12
CAD Note: Place the PU resistors close to CPU
RC249close to CPU 300 - 1500mils
5
4
Y
H_CPU_SVIDALRT#
RC24843_0402_5% RC24843_0402_5%
+VCC_CORE
100_0402_1%
100_0402_1%
12
RC250
RC250
CC24 0.1U_0402_25V6@ CC24 0.1U_0402_25V6@
VCCSENSE
CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU
4
12
@
@
12
RC259
RC259
10K_0402_5%
10K_0402_5%
1 2
H_VCCST_PWRGD
reference ULT CRB
3
+1.35V_MEM +3.3V_ALW
+3.3V_RUN +5V_ALW
+VCC_CORE +1.35V_MEM
+VCC_CORE
+VCC_CORE
+VCC_CORE +1.35V_MEM
+1.05V_VCCST+3.3V_ALW
1K_0402_5%
1K_0402_5%
RC243
RC243
1 2
1 2
C452 22U_0603_6.3V6MEMC@ C452 22U_060 3_6.3V6MEMC@
1 2
C453 22U_0603_6.3V6MEMC@ C453 22U_060 3_6.3V6MEMC@
1 2
100P_0402_50V8J
100P_0402_50V8J
C454 22U_0603_6.3V6M@ C454 22U_0603_6.3V6M@
1 2
C458 22U_0603_6.3V6M@ C458 22U_0603_6.3V6M@
1 2
C459 22U_0603_6.3V6M@ C459 22U_0603_6.3V6M@
1 2
C460 22U_0603_6.3V6M@ C460 22U_0603_6.3V6M@
1 2
C461 22U_0603_6.3V6M@ C461 22U_0603_6.3V6M@
1
@
@
CC22
CC22
2
H_VCCST_PWRGD
+1.05V_RUN
+3.3V_RUN
+1.05V_RUN+1.35V_MEM
ESD Request
H_VCCST_PWRGD<9>
H_VR_EN<46>
H_VR_READY<46>
+1.05V_RUN +1.05V_VCCST
H_VCCST_PWRGD VCCST_PWRGD
H_VR_EN VR_EN
H_VR_READY VR_READY
CPU_PWR_DEBU G#<9>
PJP11
PJP11
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
+1.35V_MEM
RC245 0_0402_5%@ RC245 0_0402_5%@
RC246 0_0402_5%@ RC246 0_0402_5%@
RC247 0_0402_5%@ RC247 0_0402_5%@
CC50
CC50
VIDSCLK<46>
1 2
1 2
1 2
CPU_PWR_DEBU G#
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
CC26
CC26
1
2
1
2
T66 PAD~D@ T66 PAD~D@
T67 PAD~D@ T67 PAD~D@
+VCC_CORE
T68
@T68
@
PAD~D
PAD~D
T69
@T69
@
PAD~D
PAD~D
T70
@T70
@
PAD~D
PAD~D
+VCCIO_OUT
+VCCIOA_OUT
T71
@T71
@
PAD~D
PAD~D
T72
@T72
@
PAD~D
PAD~D
T73
@T73
@
PAD~D
PAD~D
T74
@T74
@
PAD~D
PAD~D
T75
@T75
@
PAD~D
PAD~D
T76
@T76
@
PAD~D
PAD~D
T77
@T77
@
PAD~D
PAD~D
T78
@T78
@
PAD~D
PAD~D
T79
@T79
@
PAD~D
PAD~D
T80
@T80
@
PAD~D
PAD~D
T81
@T81
@
PAD~D
PAD~D
T82
@T82
@
PAD~D
PAD~D
T83
@T83
@
PAD~D
PAD~D
T84
@T84
@
PAD~D
PAD~D
T85
@T85
@
PAD~D
PAD~D
T86
@T86
@
PAD~D
PAD~D
+1.05V_VCCST
+VCC_CORE
+1.35V_MEM
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
@
@
@
@
CC52
CC52
CC81
CC81
2
VCCSENSE
H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
1
CC12
CC12
2
2
L59
J58
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
F59
N58
AC58
E63
AB23
A59
E20
AD23
AA23
AE59
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
AC22
AE22
AE23
AB57
AD57
AG57
C24
C28
C32
2
VDDQ DECOUPLING
Reference ULT DDRDG_080912 change to10uX6 2.2uX4
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
CC13
CC13
2
UC1L
UC1L
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
1
@
@
CC17
CC17
CC16
CC16
2
1
CC18
CC18
2
HASWELL_MCP_E
HASWELL_MCP_E
10U_0603_6.3V6M
1
CC19
CC19
2
HSW ULT POWER
HSW ULT POWER
12 OF 19
12 OF 19
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
@
@
CC21
CC21
CC20
CC20
2
2
+VCC_CORE
C36
VCC
C40
VCC
C44
VCC
C48
VCC
C52
VCC
C56
VCC
E23
VCC
E25
VCC
E27
VCC
E29
VCC
E31
VCC
E33
VCC
E35
VCC
E37
VCC
E39
VCC
E41
VCC
E43
VCC
E45
VCC
E47
VCC
E49
VCC
E51
VCC
E53
VCC
E55
VCC
E57
VCC
F24
VCC
F28
VCC
F32
VCC
F36
VCC
F40
VCC
F44
VCC
F48
VCC
F52
VCC
F56
VCC
G23
VCC
G25
VCC
G27
VCC
G29
VCC
G31
VCC
G33
VCC
G35
VCC
G37
VCC
G39
VCC
G41
VCC
G43
VCC
G45
VCC
G47
VCC
G49
VCC
G51
VCC
G53
VCC
G55
VCC
G57
VCC
H23
VCC
J23
VCC
K23
VCC
K57
VCC
L22
VCC
M23
VCC
M57
VCC
P57
VCC
U57
VCC
W57
VCC
Rev1p2
Rev1p2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(10/12)
MCP(10/12)
MCP(10/12)
LA-9431P
LA-9431P
LA-9431P
15 59Friday, May 17, 2013
15 59Friday, May 17, 2013
15 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 16
5
+1.05V_MODPHY +1.05V_MODPHY_PCH
1 2
RC262 0_0805_5%@ RC262 0_0805_5%@
CC29 place near K9;
CC27 place near L10
CC74 place near M9
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC74
CC74
2
1U_0402_6.3V6K
1
1
@
@
CC27
CC27
CC29
CC29
2
2
VCCHSIO
S0 Iccmax = 1.838A
D D
+1.05V_MODPHY
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
CC42 place near B18
VCCUSB3PLL
LC1
LC1
+PCH_AUSB3PLL
22U_0603_6.3V6M
22U_0603_6.3V6M
1
CC76
CC76
2
22U_0603_6.3V6M
22U_0603_6.3V6M
1
CC42
CC42
2
S0 Iccmax = 41mA
LC2
LC2
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
CC49 place near B11
VCCSATA3PLL
S0 Iccmax = 42mA
C C
LC5
LC5
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
CC56 place near AA21
VCCAPLL
S0 Iccmax = 57mA
+1.05V_M
@
@
RC276
RC276
1 2
0_0603_5%
0_0603_5%
CC66 place near AH13
CC61 CC62 place near J13
DcpSus2
+PCH_ASATA3PLL+1.05V_MODPHY
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
CC77
CC77
2
2
+V1.05S_APLLOPI+1.05V_RUN
100U_1206_6.3V6M
100U_1206_6.3V6M
1
1
CC55
CC55
2
2
+PCH_DCPSUS
1U_0402_6.3V6K
1U_0402_6.3V6K
@CC66
@
1
1
CC66
2
2
22U_0603_6.3V6M
22U_0603_6.3V6M
CC49
CC49
+3.3V_ALW_PCH
0.1U_0402_10V7K
0.1U_0402_10V7K
CC44
CC44
1
1U_0402_6.3V6K
1U_0402_6.3V6K
CC56
CC56
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
@
@
@CC61
@
1
CC62
CC62
CC61
2
CC44 place near AH14
+3.3V_ALW_PCH
2
CC28 place near AC9
22U_0603_6.3V6M
22U_0603_6.3V6M
+3.3V_RUN
CC28
CC28
1
CC43 place near V8
22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
2
CC43
CC43
+1.05V_RUN
S0 Iccmax = 25mA
DcpSus3
S0 Iccmax = 10mA
B B
1 2
RC265 0_0402_5%@ RC265 0_0402_5%@
+3.3V_ALW
1 2
RC267 0_0402_5%@ RC267 0_0402_5%@
CC32 place near AH10
VCCDSW3_3
+PCH_VCCDSW3_3+3.3V_ALW_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
1
@
@
CC32
CC32
2
S0 Iccmax = 114mA
+PCH_VCC1P05+1.05V_RUN
1U_0402_6.3V6K
LC3
LC3
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
CC51 place near J18
VCCCLK
S0 Iccmax = 200mA
A A
+1.05V_RUN
LC6
LC6
1 2
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
CC58 place near A20
VCCACLKPLL
1U_0402_6.3V6K
100U_1206_6.3V6M
100U_1206_6.3V6M
1
1
CC79
CC79
CC51
CC51
2
2
+PCH_VCCACLKPLL
1U_0402_6.3V6K
1U_0402_6.3V6K
100U_1206_6.3V6M
100U_1206_6.3V6M
1
1
CC58
CC58
CC78
CC78
2
2
S0 Iccmax = 31mA
5
4
+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CC63
CC63
2
2
4
+1.05V_MODPHY_PCH
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
CC63 close to Pin J17
CC64
CC64
CC64 close to Pin R21
@
@
CC31
CC31
+PCH_AUSB3PLL
+PCH_ASATA3PLL
+V1.05S_APLLOPI
+PCH_DCPSUS
+PCH_VCCDSW3_3
+PCH_VCC1P05
+PCH_VCCACLKPLL
+3.3V_ALW_PCH
AA21
AH14
AH13
AH10
AE20
AE21
L10
B18
B11
Y20
W21
J13
AC9
AA9
W9
J18
K19
A20
J17
R21
T21
K18
M20
V21
K9
M9
N8
P9
V8
UC1M
UC1M
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
@
@
1
CC73
CC73
+
+
2
mPHY
mPHY
OPI
OPI
USB3
USB3
AXALIA/HDA
AXALIA/HDA
VRM/USB2/AZALIA
VRM/USB2/AZALIA
GPIO/LCC
GPIO/LCC
LPT LP POWER
LPT LP POWER
3
+1.05V_RUN+1.05V_M
HASWELL_MCP_E
HASWELL_MCP_E
13 OF 19
13 OF 19
3
2
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
@
@
@
@
1
1
2
CC72
CC72
CC71
CC71
+
+
+
+
2
RTC
SPI
SPI
CORE
CORE
THERMAL SENSOR
THERMAL SENSOR
SDIO/PLSS
SDIO/PLSS
SUS OSCILLATOR
SUS OSCILLATOR
USB2
USB2
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VCCRTC
DCPRTC
VCCSPI
VCCASW
VCCASW
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
VCC1_05
VCC1_05
Rev1p2
Rev1p2
AG10
AE7
Y8
AG14
AG13
J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8
J15
K14
K16
U8
T9
AB8
AC20
AG16
AG17
AH11
VCCSUS3_3
RTC
+PCH_RTC_VCCSUS3_3
1 2
+DCPRRTC
CC36
CC36
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.05V_M
+PCH_VCCDSW
CC46 CC47 place near AE9
+PCH_DCPSUS1
+1.5V_THERMAL
+PCH_DCPSUS4
CC60 place near AG16
CC34 and CC33 place near
J11; CC37 place near AE8
1
2
CC45 place near U8
2
+1.05V_M
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.05V_RUN
CC40 place near Y8
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
22U_0805_6.3V6M
22U_0805_6.3V6M
CC37
CC37
2
2
1
@
@
CC46
CC46
CC47
CC47
2
CC59 place near K14
+3.3V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC45
CC45
2
1U_0402_6.3V6K
1U_0402_6.3V6K
CC60
CC60
1
2
DELL CONFIDENTIAL/PROPRIETARY
1
CC35,CC38, CC39 place near AG10
+3.3V_M
0.1U_0402_10V7K
0.1U_0402_10V7K
1
@
@
CC40
+1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
CC33
CC33
+3.3V_RUN
CC40
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC34
CC34
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
+PCH_VCCDSW
CC59
CC59
CC65 place near AG19
+PCH_RTC_VCCSUS3_3 +3.3V_ALW_PCH
1
2
+RTC_CELL
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
CC30 place near AH11
CC30
CC30
VCCSUS3_3
1
@
@
CC39
CC39
CC38
CC38
2
2
12
1U_0402_6.3V6K
1U_0402_6.3V6K
CC35
CC35
RC2755.11_0402_1% RC2755.11_0402_1%
12
RC2610_0402_5% @ RC2610_0402_5% @
+3.3V_ALW
12
RC2640_0402_5% @ RC2640_0402_5% @
S0 Iccmax = 63mA
1U_0402_6.3V6K
1U_0402_6.3V6K
@CC54
@
1
CC54
CC54 place near AD10
DCPSUS1
2
12
RC2720_0402_5% @ RC2720_0402_5% @
S0 Iccmax = 109mA
+PCH_DCPSUS4 +1.05V_M
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
@
@
CC53
CC53
2
2
@
@
LC4
LC4
2.2UH_LQM2MPN2R2NG0L_30%
2.2UH_LQM2MPN2R2NG0L_30%
100U_1206_6.3V6M
100U_1206_6.3V6M
@
@
CC75
CC75
CC53 place near AB8
DCPSUS4
12
S0 Iccmax = 1mA
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: S heet of
Date: S heet of
Date: S heet of
Compal Electronics, Inc.
MCP(11/12)
MCP(11/12)
MCP(11/12)
LA-9431P
LA-9431P
LA-9431P
1
16 59Friday, May 17, 2013
16 59Friday, May 17, 2013
16 59Friday, May 17, 2013
+PCH_VCCDSW_R
1U_0402_6.3V6K
1U_0402_6.3V6K
CC65
CC65
1
2
+1.05V_M+PCH_DCPSUS1
0.3
0.3
0.3
Page 17
5
D D
HASWELL_MCP_E
HASWELL_MCP_E
UC1N
UC1N
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
AB22
VSS
AB7
VSS
AC61
VSS
AD21
VSS
AD3
VSS
AD63
VSS
AE10
VSS
AE5
C C
B B
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14 OF 19
14 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Rev1p2
Rev1p2
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
4
HASWELL_MCP_E
HASWELL_MCP_E
UC1O
UC1O
AP22
VSS
AP23
VSS
AP26
VSS
AP29
VSS
AP3
VSS
AP31
VSS
AP38
VSS
AP39
VSS
AP48
VSS
AP52
VSS
AP54
VSS
AP57
VSS
AR11
VSS
AR15
VSS
AR17
VSS
AR23
VSS
AR31
VSS
AR33
VSS
AR39
VSS
AR43
VSS
AR49
VSS
AR5
VSS
AR52
VSS
AT13
VSS
AT35
VSS
AT37
VSS
AT40
VSS
AT42
VSS
AT43
VSS
AT46
VSS
AT49
VSS
AT61
VSS
AT62
VSS
AT63
VSS
AU1
VSS
AU16
VSS
AU18
VSS
AU20
VSS
AU22
VSS
AU24
VSS
AU26
VSS
AU28
VSS
AU30
VSS
AU33
VSS
AU51
VSS
AU53
VSS
AU55
VSS
AU57
VSS
AU59
VSS
AV14
VSS
AV16
VSS
AV20
VSS
AV24
VSS
AV28
VSS
AV33
VSS
AV34
VSS
AV36
VSS
AV39
VSS
AV41
VSS
AV43
VSS
AV46
VSS
AV49
VSS
AV51
VSS
AV55
VSS
15 OF 19
15 OF 19
Rev1p2
Rev1p2
3
AV59
VSS
AV8
VSS
AW16
VSS
AW24
VSS
AW33
VSS
AW35
VSS
AW37
VSS
AW4
VSS
AW40
VSS
AW42
VSS
AW44
VSS
AW47
VSS
AW50
VSS
AW51
VSS
AW59
VSS
AW60
VSS
AY11
VSS
AY16
VSS
AY18
VSS
AY22
VSS
AY24
VSS
AY26
VSS
AY30
VSS
AY33
VSS
AY4
VSS
AY51
VSS
AY53
VSS
AY57
VSS
AY59
VSS
AY6
VSS
B20
VSS
B24
VSS
B26
VSS
B28
VSS
B32
VSS
B36
VSS
B4
VSS
B40
VSS
B44
VSS
B48
VSS
B52
VSS
B56
VSS
B60
VSS
C11
VSS
C14
VSS
C18
VSS
C20
VSS
C25
VSS
C27
VSS
C38
VSS
C39
VSS
C57
VSS
D12
VSS
D14
VSS
D18
VSS
D2
VSS
D21
VSS
D23
VSS
D25
VSS
D26
VSS
D27
VSS
D29
VSS
D30
VSS
D31
VSS
2
UC1P
UC1P
HASWELL_MCP_E
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D50
D51
D53
D54
D55
D57
D59
D62
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
H13
HASWELL_MCP_E
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
VSS
16 OF 19
16 OF 19
VSS_SENSE
Rev1p2
Rev1p2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
100_0402_1%
100_0402_1%
12
RC260
RC260
1
VSSSENSE <46>
CAD Note: RC260 SHOULD BE PLACED CLOSE TO CPU
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(12/12)
MCP(12/12)
MCP(12/12)
LA-9431P
LA-9431P
LA-9431P
17 59Friday, May 17, 2013
17 59Friday, May 17, 2013
17 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 18
5
+SM_VREF_DQ0_DIMM1
Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
D D
C C
B B
A A
VREFDQ multiple methods M3
All VREF traces should
have 10 mil trace width
DDR_A_DQS#[0..7]<8>
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
Layout Note:
Place near JDIMM1
+1.35V_MEM
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD4
CD4
2
+1.35V_MEM
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD14
CD14
1
1
2
2
Layout Note:
Place near JDIMM1.203,204
+0.675V_DDR_VTT
0.1U_0402_25V6
0.1U_0402_25V6
CD26
CD26
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
@
@
CD15
CD15
CD6
CD6
CD5
CD5
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD16
CD16
1
1
2
2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
CD27
CD27
1
1
2
2
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD7
CD7
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
CD17
CD17
CD18
CD18
1
2
0.1U_0402_25V6
0.1U_0402_25V6
CD28
CD28
CD29
CD29
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
1
2
CD9
CD9
CD8
CD8
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD21
CD21
CD20
CD20
CD19
CD19
1
2
1
1
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD30
CD30
CD31
CD31
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
CD11
CD11
CD10
CD10
2
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
1
CD22
CD22
+
+
2
1 2
RD5 0_0402_5%@RD5 0_0402_5%@
1 2
RD6 0_0402_5%@RD6 0_0402_5%@
1 2
RD1 0_0402_5%@ RD1 0_0402_5%@
4
+3.3V_RUN
3
+DIMM1_VREF_DQ
0.1U_0402_25V6
0.1U_0402_25V6
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
CD1
CD1
2
DDR_CKE0_DIMMA<8>
DDR_A_BS2<8>
M_CLK_DDR0<8>
DDR_A_BS0<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
DDR_CS1_DIMMA#<8>
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
@
@
CD25
CD25
2
DDR_A_D13
DDR_A_D8
CD2
CD2
1
DDR_A_D14
2
DDR_A_D10
DDR_A_D29
DDR_A_D28 DDR_A_D24
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_BS2
DDR_A_MA3
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
DDR_A_D36
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
0.1U_0402_25V6
0.1U_0402_25V6
1
CD24
CD24
+0.675V_DDR_VTT
2
H=4mm
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A621-U4R6-7H
FOX_AS0A621-U4R6-7H
CONN@JDIMM1
CONN@
VREF_CA
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
2-3A to 1 DIMMs/channel
+1.35V_MEM+1.35V_ME M
2
4
DDR_A_D9
6
DDR_A_D12
8
10
DDR_A_DQS#1
12
DDR_A_DQS1
14
16
DDR_A_D15
18
DDR_A_D11
20
22
DDR_A_D25
24
26
28
30
DDR3_DRAMRST#
32
34
DDR_A_D27
36
DDR_A_D26
38
40
DDR_A_D45DDR_A_D44
42
DDR_A_D40
44
46
48
50
DDR_A_D42
52
DDR_A_D46
54
56
DDR_A_D52
58
DDR_A_D53
60
62
DDR_A_DQS#6
64
DDR_A_DQS6
66
68
DDR_A_D54
70
DDR_A_D55
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9
DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
+SM_VREF_CA_DIMM1
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D7
DDR_A_D18
DDR_A_D19
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D23
DDR_A_D37
DDR_A_D32
DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D56
DDR_A_D57
+0.675V_DDR_VTT
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
0.1U_0402_25V6
0.1U_0402_25V6
@
@
CD3
CD3
1
2
CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN
DDR_CKE1_DIMMA <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <8>
0.1U_0402_25V6
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
CD13
CD13
CD12
CD12
1
1
2
2
2
Reverse Type
+SM_VREF_DQ0_DIMM1
+5V_ALW +1.35V_MEM
220K_0402_5%~D
+SM_VREF_CA_DIMM
1 2
RD12 0_0402_5%@ RD12 0_0402_5%@
DDR_PG_CTRL<9>
DDR_XDP_WAN_ SMBDAT <19,31,7,9>
DDR_XDP_WAN_ SMBCLK <19,31,7,9>
220K_0402_5%~D
1
+1.35V_MEM
12
RD3
RD3
470_0402_5%
470_0402_5%
1 2
RC279 0_0402_5%@RC279 0_0402_5%@
+1.35V_MEM
1.8K_0402_1%
1.8K_0402_1%
12
RC217
RC217
RC173
RC173
1.8K_0402_1%
1.8K_0402_1%
12
RC221
RC221
1 2
2_0402_1%
2_0402_1%
DDR3_DRAMRST#_CP U <9>DDR3_DRAMRST#<19>
+SM_VREF_DQ0
1
CC70
CC70
0.022U_0402_16V7K
0.022U_0402_16V7K
2
12
RC195
RC195
24.9_0402_1%
24.9_0402_1%
DDR3L SODIMM ODT GENERATION
QD1
QD1
BSS138-G_SOT23-3
NC1VCC
A
GND
BSS138-G_SOT23-3
1 3
D
S
D
S
R29 66.5_0402_1%R29 66.5_0402_1%
G
G
2
R30 66.5_0402_1%R30 66.5_0402_1%
R31 66.5_0402_1%R31 66.5_0402_1%
R33 66.5_0402_1%R33 66.5_0402_1%
+1.35V_MEM
5
4
Y
1 2
1 2
1 2
1 2
CD23
@CD23
@
0.1U_0402_25V6
0.1U_0402_25V6
1 2
0.675V_DDR_VTT_ON
12
R28
R28
0.675V_DDR_VTT_ON
R32
@R32
@
2M_0402_5%
2M_0402_5%
1 2
U5
U5
2
3
74AUP1G07GW_TSSOP5
74AUP1G07GW_TSSOP5
M_ODT0
M_ODT1
M_ODT2 <19>
M_ODT3 <19>
0.675V_DDR_VTT_ON <43>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
LA-9431P
LA-9431P
LA-9431P
18 59Friday, May 17, 2013
18 59Friday, May 17, 2013
18 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 19
5
+SM_VREF_DQ1_DIMM2
Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
D D
DDR_B_DQS#[0..7]<8>
DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..15]<8>
+1.35V_MEM
C C
+1.35V_MEM
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
B B
+0.675V_DDR_VTT
A A
VREFDQ multiple methods M3
Layout Note:
Place near JDIMM2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD35
CD35
2
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
CD46
CD46
CD45
CD45
1
2
Layout Note:
Place near JDIMM2.203,204
0.1U_0402_25V6
0.1U_0402_25V6
CD54
CD54
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD36
CD36
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD47
CD47
1
1
2
2
0.1U_0402_25V6
0.1U_0402_25V6
CD55
CD55
1
2
5
1U_0402_6.3V6K
1
1
CD37
CD37
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
CD48
CD48
CD49
CD49
1
2
0.1U_0402_25V6
0.1U_0402_25V6
CD56
CD56
1
1
2
2
All VREF traces should
have 10 mil trace width
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CD39
CD39
CD40
CD38
CD38
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD50
CD50
1
2
0.1U_0402_25V6
0.1U_0402_25V6
CD57
CD57
CD40
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CD52
CD52
CD51
CD51
1
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
+
+
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD59
CD59
CD58
CD58
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
CD42
CD42
CD41
CD41
2
CD53
CD53
4
+DIMM2_VREF_DQ
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
RD11 0_0402_5%@ RD11 0_0402_5%@
+3.3V_RUN
4
RD10 0_0402_5%@ RD10 0_0402_5%@
RD7 0_0402_5%@ RD7 0_0402_5%@
1 2
3
2-3A to 1 DIMMs/channel
2
4
DDR_B_D12
6
DDR_B_D9
8
10
DDR_B_DQS#1
12
DDR_B_DQS1
14
16
DDR_B_D13
18
DDR_B_D15
20
22
DDR_B_D25
24
DDR_B_D24
26
28
30
DDR3_DRAMRST#
32
34
DDR_B_D30
36
DDR_B_D31
38
40
DDR_B_D45
42
DDR_B_D44
44
46
48
50
DDR_B_D47
52
DDR_B_D43
54
56
DDR_B_D61
58
DDR_B_D60
60
62
DDR_B_DQS#7
64
DDR_B_DQS7
66
68
DDR_B_D63
70
DDR_B_D62
72
74
DDR_CKE3_DIMMB
76
78
DDR_B_MA15
80
DDR_B_MA14
82
84
DDR_B_MA11
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3
+SM_VREF_CA_DIMM2
DDR_B_D5
DDR_B_D0
DDR_B_D2
DDR_B_D6
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D37
DDR_B_D32
DDR_B_D34
DDR_B_D38
DDR_B_D51
DDR_B_D55
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D50
A7
A6
A4
A2
A0
+1.35V_MEM +1.35V_MEM
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
2
0.1U_0402_25V6
0.1U_0402_25V6
CD33
CD33
1
CD32
CD32
2
DDR_CKE2_DIMMB<8>
DDR_B_BS2<8>
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_B_BS0<8>
DDR_B_WE#<8>
DDR_B_CAS#<8>
DDR_CS3_DIMMB#<8>
12
+3.3V_RUN
12
DDR_B_D8
DDR_B_D14
DDR_B_D10
DDR_B_D11
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_B_D40
DDR_B_D41
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D42
DDR_B_D56
DDR_B_D57
DDR_B_D59
DDR_B_D58
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D4
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D3
DDR_B_D7
DDR_B_D21
DDR_B_D20
DDR_B_D22
DDR_B_D23
DDR_B_D36
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D39
DDR_B_D52
DDR_B_D49
DDR_B_D48
DDR_B_D53
+0.675V_DDR_VTT +0.675V_DDR_VTT
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
CD60
1
2
CD60
1
@
@
CD61
CD61
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
JDIMM2
3
5
7
9
11
13
15
17
19
21
23
25
27
33
35
39
41
45
47
49
51
53
55
57
59
63
67
69
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
FOX_AS0A621-U4R6-7H
FOX_AS0A621-U4R6-7H
3
H=4mm
CONN@JDIMM2
CONN@
VREF_DQ1VSS1
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS129RESET#
VSS1131VSS12
DQ10
DQ11
VSS1337VSS14
DQ16
DQ17
VSS1543VSS16
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS2261DQS#3
DM3
VSS2365VSS24
DQ26
DQ27
VSS2571VSS26
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
A15
A14
A11
S0#
G2
2
0.1U_0402_25V6
0.1U_0402_25V6
DDR3_DRAMRST# <18>
@
@
CD34
CD34
1
2
CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN
DDR_CKE3_DIMMB <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <8>
M_ODT2 <18>
M_ODT3 <18>
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
1
1
CD43
CD43
2
2
DDR_XDP_WAN_ SMBDAT <18,31,7,9>
DDR_XDP_WAN_ SMBCLK <18,31,7,9>
2
Reverse Type
+SM_VREF_DQ1_DIMM2
+SM_VREF_CA_DIMM
1 2
RD13 0_0402_5%@ RD13 0_0402_5%@
CD44
CD44
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
+1.35V_MEM
1.8K_0402_1%
1.8K_0402_1%
12
RC67
RC67
1 2
RC68
RC68
2_0402_1%
2_0402_1%
1.8K_0402_1%
1.8K_0402_1%
12
RC69
RC69
+1.35V_MEM
1.8K_0402_1%
1.8K_0402_1%
12
RC130
RC130
1 2
RC126
RC126
2_0402_1%
2_0402_1%
1.8K_0402_1%
1.8K_0402_1%
12
RC132
RC132
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
LA-9431P
LA-9431P
LA-9431P
1
+SM_VREF_CA+SM _VREF_CA_DIMM
1
CC67
CC67
0.022U_0402_16V7K
0.022U_0402_16V7K
2
12
RC83
RC83
24.9_0402_1%
24.9_0402_1%
+SM_VREF_DQ1
1
CC69
CC69
0.022U_0402_16V7K
0.022U_0402_16V7K
2
12
RC128
RC128
24.9_0402_1%
24.9_0402_1%
19 59Friday, May 17, 2013
19 59Friday, May 17, 2013
19 59Friday, May 17, 2013
0.3
0.3
0.3
Page 20
5
D D
+3.3V_ALW_PCH
C3880.1U_0402_25V6 @C3880.1U_0402_25V6 @
1 2
5
U29
C C
+3.3V_ALW_PCH
PLTRST_NFC#<9>
PCH_NFC_RST<12>
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
1 2
R38 100K_0402_5%R38 100K_0402_5%
1 2
R37 0_0402_5%@R37 0_0402_5%@
TP_NFC_RSVD3
NFC_DET#
U29
1
P
B
4
NFC_RST
O
2
A
G
3
4
+3.3V_ALW_PCH
CONN@
CONN@
JNFC1
JNFC1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
GND
17
GND
E-T_6718K-Y15N-01L
E-T_6718K-Y15N-01L
NFC_IRQ<12>
NFC_DET#<12>
TP_NFC_SWP_PWR_RSVD
TP_NFC_RSVD4
NFC_RST
NFC_SMBCLK
NFC_SMBDATA
TP_NFC_RSVD3
TP_NFC_RSVD1
NFC_DET#
T87 PAD~D@T87 PAD~D@
T88 PAD~D@T88 PAD~D@
NFC_SMBCLK<7>
NFC_SMBDATA<7>
T89 PAD~D@T89 PAD~D@
3
+3.3V_ALW_PCH
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
C1
C1
1
2
C1 close to JNFC1
2
1
ST change to 6718K-Y15N-01L
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
NFC/Sensor Hub Conn
NFC/Sensor Hub Conn
NFC/Sensor Hub Conn
LA-9431P
LA-9431P
LA-9431P
1
20 59Friday, May 17, 2013
20 59Friday, May 17, 2013
20 59Friday, May 17, 2013
0.3
0.3
0.3
Page 21
E6
E7
E8
E9
H6
H7
H8
H9
E3
G3
C8
C9
F12
G12
J3
E5
H3
F3
D3
E10
C7
C6
H11
E12
D12
J10
K8
K9
K10
J2
C3
C4
C11
C12
K3
K4
K11
K12
J4
VOUT1
VOUT1
VOUT2
VOUT2
GPAD
CT1
GND
CT2
U6B
U6B
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDRX
VDDRX
VDDTX0
VDDTX0
VDDTX1
VDDTX1
VDDXT1V
VDDLP
VDDRXA0
VDDRXA1
VDDRXA2
VDDTX0A0
VDDTX0A1
VDDTX0A2
VDDTX1A0
VDDTX1A1
VDDTX1A2
VGA_AVDD
VGA_AVDD
VGA_AVDD
VGA_AVDD
VDDSA
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDXT3V
2
IDTVMM2320BKG8_BGA168
IDTVMM2320BKG8_BGA168
14
13
+1.05V_RUN_VMM_U31
12
1 2
C433
C433
11
1 2
10
C394
C394
9
8
+3.3V_RUN_VMM_U31
15
3.3V Analog
3.3V Analog
1V Digital 1 V Analog 3.3V IO
1V Digital 1 V Analog 3.3V IO
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
VDDRX_33
VDDTX0_33
VDDTX1_33
VGA_AVDD33
VGA_AVDD33
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
VGA_AVSS
+1.05V_RUN_VMM
12
PAD-OPEN1x1m
PAD-OPEN1x1m
2
1
LP_CTL
H5
C10
1
H12
K6
K7
2
C5
VSS
D5
VSS
D6
VSS
D7
VSS
D8
VSS
D9
VSS
D10
VSS
D11
VSS
E4
VSS
E11
VSS
F4
VSS
F5
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
F10
VSS
F11
VSS
G4
VSS
G5
VSS
G6
VSS
G7
VSS
G8
VSS
G9
VSS
G10
VSS
G11
VSS
H4
VSS
D4
VSS
J5
VSS
J11
VSS
J12
VSS
K5
VSS
H10
J6
J7
J8
J9
PJP12
PJP12
1 2
C432 0.1U _0402_10V7KC432 0. 1U_0402_10V7K
12
PJP13 PAD-OPEN1x1mPJP13 PAD-OPEN1x1m
C392
C392
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
R207 100K_0402_5%@R207 100K_0402_5%@
+3.3V_RUN_VDDA
.01U_0402_16V7K
.01U_0402_16V7K
.01U_0402_16V7K
.01U_0402_16V7K
C13
C13
1
2
+3.3V_RUN_VMM
+3.3V_RUN_VMM
VMM_SPI_CS#
VMM_SPI_CLK
VMM_SPI_DIN
LP_CTL
CLK_27M_IN
12
R64
R64
10K_0402_5%
10K_0402_5%
U7
U7
1
CS#
2
DO(IO1)
3
WP#(IO2)
4
GND
W25X10CLSNIG _SO8
W25X10CLSNIG _SO8
U6A
U6A
G1
RxP0
G2
RxN0
F1
RxP1
F2
RxN1
E1
RxP2
E2
RxN2
D1
RxP3
D2
RxN3
H1
RxAUXP
H2
RXAUXN
C2
RxSRCDET
J1
RxHPD
A13
RSTN_IN
B5
MESCL
B6
MESDA
B1
ROMWP
A4
SPICS
B3
SPICLK
B4
SPIDI
A3
SPIDO
D14
GPIO0
D13
GPIO1
C14
GPIO2
C13
GPIO3
B14
GPIO4
B13
GPIO5
C1
GPIO6/INT
M12
GPIO7/MSCL
M13
GPIO8/MSDA
L3
GPIO9
B2
LP_CTL
A5
LP_EN
K2
RX_STS
L2
TX0_STS
M1
TX1_STS
M2
TX2_STS
K1
XIN
L1
XOUT
IDTVMM2320BKG8_BGA168
IDTVMM2320BKG8_BGA168
+3.3V_RUN_VMM
L2
L2
1 2
0.1U_0402_25V6
0.1U_0402_25V6
1U_0603_10V6K
1U_0603_10V6K
C14
C14
C15
C15
C16
C16
1
1
BLM18AG102SN1D_2P
BLM18AG102SN1D_2P
2
2
1 2
DP12412_P0<27>
DP12412_N0<27>
DP12412_P1<27>
DP12412_N1<27>
DP12412_P2<27>
DP12412_N2<27>
DP12412_P3<27>
DP12412_N3<27>
DP12412_AUX<27>
DP12412_AUX#<27>
CLK_27M_IN_R
22P_0402_50V8J
22P_0402_50V8J
1
C42
C42
27MHZ_12PF_X1E000021042600
27MHZ_12PF_X1E000021042600
2
R107 0_0402_5%@ R107 0_0402_5%@
Y1
Y1
1
2
1 2
IN
OUT
GND
GND
DP12412_HPD<27>
PLTRST_VMM2320#<9>
C1550.1U_0402_10V7K C1550.1U_0402_10V7K
1 2
C1560.1U_0402_10V7K C1560.1U_0402_10V7K
1 2
C1570.1U_0402_10V7K C1570.1U_0402_10V7K
1 2
C1580.1U_0402_10V7K C1580.1U_0402_10V7K
1 2
C1590.1U_0402_10V7K C1590.1U_0402_10V7K
1 2
C1600.1U_0402_10V7K C1600.1U_0402_10V7K
1 2
C1610.1U_0402_10V7K C1610.1U_0402_10V7K
1 2
C1620.1U_0402_10V7K C1620.1U_0402_10V7K
1 2
C190. 1U_0402_10V7K C190.1U_0402_10V7K
1 2
C200. 1U_0402_10V7K C200.1U_0402_10V7K
R63 1M_0402_5%R63 1M_0402_5%
12
R66
R66
1M_0402_5%
3
4
1M_0402_5%
22P_0402_50V8J
22P_0402_50V8J
1
C43
C43
2
XB: non Vpro us e A2 part
Vpro use A3 part
SRCDET
12
VMM_SPI_CS#
VMM_SPI_DIN
VMM_SPI_WP#
DP12412_P0_C
DP12412_N0_C
DP12412_P1_C
DP12412_N1_C
DP12412_P2_C
DP12412_N2_C
DP12412_P3_C
DP12412_N3_C
DP12412_AUX_C
DP12412_AUX#_C
DP12412_HPD
VMM_MESCL
VMM_MESDA
VMM_SPI_WP#
VMM_SPI_DO
VMM_GPIO6
VMM_GPIO7
VMM_GPIO8
VMM_GPIO9
CLK_27M_OUT
+1.05V_RUN_VMM
L1
L1
1 2
BLM18AG102SN1D_2P
BLM18AG102SN1D_2P
+1.05V_RUN_VMM
L4
L4
1 2
BLM18AG102SN1D_2P
BLM18AG102SN1D_2P
B B
+3.3V_RUN_VMM
L5
L5
1 2
BLM18AG102SN1D_2P
BLM18AG102SN1D_2P
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
C132
C132
+1.05V_VMM_VDD
1U_0603_10V6KC81U_0603_10V6K
C8
1
1
2
2
1U_0603_10V6K
1U_0603_10V6K
1
C25
C25
2
+1.05V_VMM_VDDTX
1U_0603_10V6K
1U_0603_10V6K
C21
C21
1
1
2
2
+3.3V_RUN_VDDIO
1U_0603_10V6K
1U_0603_10V6K
C26
C26
1
1
2
2
+3.3V_RUN_VDDA
DOCKED<27,28,32,36>
+3.3V_RUN
0.1U_0402_25V6C90.1U_0402_25V6
C9
1
2
0.1U_0402_25V6
0.1U_0402_25V6
1
C17
C17
2
0.1U_0402_25V6
0.1U_0402_25V6
.01U_0402_16V7K
.01U_0402_16V7K
C22
C22
1
2
0.1U_0402_25V6
0.1U_0402_25V6
.01U_0402_16V7K
.01U_0402_16V7K
C27
C27
1
2
+1.05V_RUN
DOCKED
+5V_ALW
DOCKED
.01U_0402_16V7K
.01U_0402_16V7K
C10
C10
C11
C11
1
2
C23
C23
C28
C28
1
2
.01U_0402_16V7K
.01U_0402_16V7K
C18
C18
.01U_0402_16V7K
.01U_0402_16V7K
C24
C24
1
2
.01U_0402_16V7K
.01U_0402_16V7K
C29
C29
1
2
C12
C12
1
2
U31
U31
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
TPS22966DPUR_SON14_2X3~D
TPS22966DPUR_SON14_2X3~D
.01U_0402_16V7K
.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
HOLD#(IO3)
DI(IO0)
1
+3.3V_RUN_VMM
8
VCC
7
VMM_SPI_HOLD
6
VMM_SPI_CLK
CLK
5
VMM_SPI_DO
VMM_DPC_CTRLCLK
VMM_DPC_CTRLDAT
SW_DPC_AUX#
SW_DPC_AUX
SW_DPB_AUX
RED_DOCK
GREEN_DOCK
BLUE_DOCK
C34
C34
1 2
0.1U_0402_25V6
0.1U_0402_25V6
R65
R65
B7
Tx0P0
A7
Tx0N0
B8
Tx0P1
A8
Tx0N1
B9
Tx0P2
A9
Tx0N2
B10
Tx0P3
A10
Tx0N3
A14
CAD0
B11
Tx0AUXP
A11
Tx0AUXN
B12
Tx0DDCSCL
A12
Tx0DDCSDA
A6
Tx0HPD
E13
Tx1P0
E14
Tx1N0
F13
Tx1P1
F14
Tx1N1
G13
Tx1P2
G14
Tx1N2
H13
Tx1P3
H14
Tx1N3
M14
CAD1
J13
Tx1AUXP
J14
Tx1AUXN
K13
Tx1DDCSCL
L14
Tx1DDCSDA
K14
Tx1HPD
L9
VGA_VSYNC
M9
VGA_HSYNC
M6
VGA_RP
L6
VGA_RN
M7
VGA_GP
L7
VGA_GN
M8
VGA_BP
L8
VGA_BN
L4
VGA_SCL
M4
VGA_SDA
M3
VGA_DET
M5
VGA_IREF
L5
VGA_NC
A1
SSDA
A2
SSCL
M11
TRSTN
M10
TCK
L12
TMS
L13
TMS2
L11
TDI
L10
TDO
1 2
R49 2.2K_0402_5%R49 2.2K_0402_5%
1 2
R46 2.2K_0402_5%R46 2.2K_0402_5%
1 2
R91 1M_0402_5%R91 1M_0402_5%
1 2
R92 1M_0402_5%R92 1M_0402_5%
1 2
R47 1M_0402_5%R47 1M_0402_5%
1 2
R311 150_0402_1%R311 150_0402_1%
1 2
R312 150_0402_1%R312 150_0402_1%
1 2
R351 150_0402_1%R351 150_0402_1%
12
2.2K_0402_5%
2.2K_0402_5%
VMM_DPC_CTRLCLK
VMM_DPC_CTRLDAT
VMM_DPB_CTRLCLK
VMM_DPB_CTRLDAT
VMM2310_TX2P0
VMM2310_TX2N0
VMM2310_TX2N3
VMM2310_TX2N2
VMM2310_TX2N1
VMM2310_SCL
VMM2310_SDA
VMM2310_HDP
VMM2310_AUXN
VMM2310_AUXP
+3.3V_RUN_VMM
EEPROM
DPC_LANE_P0 <34>
DPC_LANE_N0 <34>
DPC_LANE_P1 <34>
DPC_LANE_N1 <34>
DPC_LANE_P2 <34>
DPC_LANE_N2 <34>
DPC_LANE_P3 <34>
DPC_LANE_N3 <34>
DPC_CA_DET <24,34>
SW_DPC_AUX <24>
SW_DPC_AUX# <24>
VMM_DPC_CTRLCLK <24>
VMM_DPC_CTRLDAT <24>
DPC_DOCK_HPD <34>
DPB_LANE_P0 <34>
DPB_LANE_N0 <34>
DPB_LANE_P1 <34>
DPB_LANE_N1 <34>
DPB_LANE_P2 <34>
DPB_LANE_N2 <34>
DPB_LANE_P3 <34>
DPB_LANE_N3 <34>
DPB_CA_DET <24,34>
SW_DPB_AUX <24>
SW_DPB_AUX# <24>
VMM_DPB_CTRLCLK <24>
VMM_DPB_CTRLDAT <24>
DPB_DOCK_HPD <34>
T40PAD~D @T40PAD~D @
I2C1_SDA_VMM <12>
I2C1_SCL_VMM <12>
I2C debug port to VMM2320
VMM_MESCL
VMM_MESDA
SW_DPB_AUX#
VMM_GPIO6
VMM_GPIO7
VMM_GPIO8
SRCDET
VMM_DPB_CTRLCLK
VMM_DPB_CTRLDAT
1 2
R40 2.2K_0402_5%R40 2.2K_0402_5%
1 2
R42 2.2K_0402_5%R42 2.2K_0402_5%
1 2
R44 1M_0402_5%R44 1M_0402_5%
1 2
R52 2.2K_0402_5%R52 2.2K_0402_5%
1 2
R53 2.2K_0402_5%R53 2.2K_0402_5%
1 2
R54 2.2K_0402_5%R54 2.2K_0402_5%
1 2
R69 1M_0402_5%R69 1M_0402_5%
1 2
R70 2.2K_0402_5%R70 2.2K_0402_5%
1 2
R72 2.2K_0402_5%R72 2.2K_0402_5%
+3.3V_RUN_VMM
VMM2310_SCL
VMM2310_SDA
VMM2310_TX2N0
VMM2310_TX2P0
R73 0_0402_5%@ R73 0_0402_5%@
R75 0_0402_5%@ R75 0_0402_5%@
R76 0_0402_5%@ R76 0_0402_5%@
R77 0_0402_5%@ R77 0_0402_5%@
R81 0_0402_5%@ R81 0_0402_5%@
R84 0_0402_5%@ R84 0_0402_5%@
R88 0_0402_5%@ R88 0_0402_5%@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
RED_DOCK
GREEN_DOCK
BLUE_DOCK
CLK_DDC2_DOCK
DAT_DDC2_DOCK
HSYNC_DOCK
VSYNC_DOCK
RED_DOCK <34>
GREEN_DOCK < 34>
BLUE_DOCK <34>
CLK_DDC2_DOCK <34>
DAT_DDC2_DOCK <34>
HSYNC_DOCK <34>
VSYNC_DOCK <34>
VMM2310_HDP
R74 10K_0402_5%R74 10K_0402_5%
VMM2310_AUXN
+3.3V_RUN_VMM
12
1 2
R85 3.74K_0402_1%R85 3.74K_0402_1%
VMM2310_TX2N3
A A
VMM2310_TX2N2
VMM2310_TX2N1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
IDT VMM2320 DP and VGA SW
IDT VMM2320 DP and VGA SW
IDT VMM2320 DP and VGA SW
LA-9431P
LA-9431P
LA-9431P
21 59Friday, May 17, 2013
21 59Friday, May 17, 2013
21 59Friday, May 17, 2013
0.3
0.3
0.3
Page 22
5
4
3
2
1
ACES_50398-04071-001
ACES_50398-04071-001
45
44
43
42
41
D D
C C
B B
JEDP1
+LCDVDD
Close to
JEDP1.11,12
BIA_PWM
12
10K_0402_5%
10K_0402_5%
40
40
G5
39
39
G4
38
38
G3
37
37
G2
36
36
G1
35
35
34
34
33
33
32
32
31
31
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
CONN@JEDP1
CONN@
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C63
C63
1
Close to
2
JEDP1.33
D10
D10
1
R95
R95
BAT54CW_SOT323-3
BAT54CW_SOT323-3
For Webcam
change back to CCD_OFF at Goliad project
A A
USBP3+<11 >
USBP3-<11>
+3.3V_TSP
+3.3V_CAM
USBP3_DÂUSBP3_D+
1 2
IO_LOOP
R108 1K_0402_5%R108 1K_0402_5%
+BL_PWR_SRC
1 2
C52 0.1U_0603_50V7KC52 0.1U_0603_50V7K
1 2
LE1
EMC@LE1
EMC@
DISP_ON
EDP_CPU_HPD <10>
LCD_TST <36>
+LCDVDD
EDP_CPU_AUX#_C
EDP_CPU_AUX_C
EDP_CPU_LANE_P0_C
EDP_CPU_LANE_N0_C
EDP_CPU_LANE_P1_C
EDP_CPU_LANE_N1_C
LCD_CBL_DET# <12>
+3.3V_RUN
+3.3V_CAM +5V_ALW
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C68
C68
1
Close to
2
JLED1.1
3
EDP_BIA_PWM
2
BIA_PWM_EC
+3.3V_CAM
12
CCD_OFF<36>
3.3V_CAM_EN#<12>
5
1 2
R102 0_0402_5%@ R102 0_04 02_5%@
R106 0_0402_5%@R106 0_0402_5%@
1
1
4
4
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
1 2
R100 0_0402_5%@ R100 0_04 02_5%@
1 2
R101 0_0402_5%@ R101 0_04 02_5%@
USBP7- <11>
USBP7+ <11>
For LCDVDD
LCD_VCC_TEST_EN<36>
ENVDD_PCH<10,36>
10U_0603_6.3V6M
10U_0603_6.3V6M
D2
D2
2
1
3
BAT54CW_SOT323-3
BAT54CW_SOT323-3
@
@
C431
C431
EN_LCDPWR
CAM_MIC_CBL_DET# <12>
BIA_PWM
BLM15BB221SN1D_2P~D
BLM15BB221SN1D_2P~D
12
C54 0.1U_0402_1 0V7KC54 0.1U_0402_10V7K
12
C55 0.1U_0402_1 0V7KC55 0.1U_0402_10V7K
12
C59 0.1U_0402_1 0V7KC59 0.1U_0402_10V7K
12
C56 0.1U_0402_1 0V7KC56 0.1U_0402_10V7K
12
C60 0.1U_0402_1 0V7KC60 0.1U_0402_10V7K
12
C57 0.1U_0402_1 0V7KC57 0.1U_0402_10V7K
Pin 29 for cable detact GND
Pin 17 ~20 for BL_GND
Pin 3, 10 for eDP High speed GND
Pin 14,15 for LCD_GND
Close to
JEDP1.40
+3.3V_TSP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
@
@
C3
C3
2
EDP_BIA_PWM <10>
BIA_PWM_EC <37>
0.1U_0402_25V6
0.1U_0402_25V6
1
@
@
C62
C62
2
Close to
JEDP1.2
100P_0402_50V8J
100P_0402_50V8J
1
CE1
CE1
2
EDP_CPU_AUX# <10>
EDP_CPU_AUX <10>
EDP_CPU_LANE_P0 <10>
EDP_CPU_LANE_N0 <10 >
EDP_CPU_LANE_P1 <10>
EDP_CPU_LANE_N1 <10 >
+3.3V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
@
@
1
C64
C64
2
check
DISP_ON
12
R96
R96
100K_0402_5%
100K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
@
@
DMIC0 <26>
DMIC_CLK <26>
1
@
@
CE2
CE2
2
ESD depop location(EMC)
BATT_WHITE_LED#<40>
BATT_YELLOW_LED#<4 0>
PANEL_HDD_LED#<40>
BREATH_WHITE_LED #<40>
TOUCH_PANEL_INTR#<12>
D21
D21
3
1
2
BAT54CW_SOT323-3
BAT54CW_SOT323-3
+5V_ALW
2
3
L30ESDL5V0C3-2_SOT23-3
L30ESDL5V0C3-2_SOT23-3
@
@
D8
D8
1
CONN@
CONN@
JLED1
JLED1
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_50450-0067N-P01
ACES_50450-0067N-P01
PANEL_BKLEN <10>
PANEL_BKEN_EC <36>
Touch Screen Connector
+3.3V_TSP
Q2
PJP9
PJP9
PAD-OPEN1x1m
PAD-OPEN1x1m
LP2301ALT1G_SOT23-3
LP2301ALT1G_SOT23-3
+3.3V_CAM_Q +3.3V_TSP_Q
1 2
L8EMC @
L8EMC @
2
2
3
3
Q3
Q3
1 3
D
D
2
+3.3V_RUN
S
S
G
G
USBP3_D+
USBP3_D-
0.1U_0402_25V6
0.1U_0402_25V6
C67
C67
1
2
4
+PWR_SRC
40mil
1000P_0402_50V7K
1000P_0402_50V7K
1
C66
C66
2
EN_INVPWR<37>
12
R97
R97
100K_0402_5%
100K_0402_5%
1 2
R99 47K_040 2_5%R99 47K_0402_5%
check Resistor
4 5
PWR_SRC_ON
EN_INVPWR
Panel backlight power control by EC
D
D
6
S
S
2
1
G
G
3
Q4
Q4
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
1 3
D
D
2
Q2
40mil
FDC654P-G_SSOT-6
FDC654P-G_SSOT-6
1
2
S
S
G
G
+BL_PWR_SRC
C65
C65
0.1U_0603_50V7K
0.1U_0603_50V7K
FDC654P: P CHANNAL
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
3.3V_TS_EN<12>
+3.3V_RUN
G
G
2
12
10K_0402_5%
10K_0402_5%
PJP10
12
61
D
D
S
S
PJP10
PAD-OPEN1x1m
PAD-OPEN1x1m
R94
R94
Q17B
Q17B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
LP2301ALT1G_SOT23-3
LP2301ALT1G_SOT23-3
DELL CONFIDENTIAL/PROPRIETARY
2
+3.3V_ALW+LCD VDD
U9
12
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
2
3
APL3512ABI-TRG_SOT23-5
APL3512ABI-TRG_SOT23-5
R104
R104
100K_0402_5%
100K_0402_5%
1 2
+3.3V_RUN
Q1
Q1
1 3
D
S
D
S
G
G
2
G
G
5
34
VOUT
GND
EN
D
D
S
S
U9
5
VIN
4
SS
0.1U_0402_25V6
0.1U_0402_25V6
C61
C61
1
2
Q17A
Q17A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
eDP & CAM &TS Conn
eDP & CAM &TS Conn
eDP & CAM &TS Conn
LA-9431P
LA-9431P
LA-9431P
1
0.01U_0402_16V7K
0.01U_0402_16V7K
@C430
@
C430
1
2
22 59Friday, May 17, 2013
22 59Friday, May 17, 2013
22 59Friday, May 17, 2013
0.3
0.3
0.3
Page 23
5
D D
C C
4
DDI1_LANE_P3<10>
DDI1_LANE_N3<10>
DDI1_LANE_P2<10>
DDI1_LANE_N2<10>
DDI1_LANE_P1<10>
DDI1_LANE_N1<10>
DDI1_LANE_P0<10>
DDI1_LANE_N0<10>
12
C103 0.1U_0402_10V7KC103 0.1U_0402_10V7K
12
C191 0.1U_0402_10V7KC191 0.1U_0402_10V7K
12
C199 0.1U_0402_10V7KC199 0.1U_0402_10V7K
12
C209 0.1U_0402_10V7KC209 0.1U_0402_10V7K
12
C269 0.1U_0402_10V7KC269 0.1U_0402_10V7K
12
C270 0.1U_0402_10V7KC270 0.1U_0402_10V7K
12
C271 0.1U_0402_10V7KC271 0.1U_0402_10V7K
12
C272 0.1U_0402_10V7KC272 0.1U_0402_10V7K
TMDS_CLK_C
TMDS_P0_C
TMDS_N0_C
TMDS_P1_C
TMDS_N1_C
TMDS_P2_C
TMDS_N2_C
3
L9
EMC@L9
EMC@
1 2
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L10
@L10
@
1
1
4
4
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
EMC@L11
EMC@
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
EMC@L12
EMC@
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L13
1
1
4
4
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
EMC@L14
EMC@
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
EMC@L15
EMC@
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L16
1
1
4
4
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
EMC@L17
EMC@
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
EMC@L18
EMC@
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L19
1
1
4
4
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
EMC@L20
EMC@
9NH_0402HS-9N0EJTS_5%
9NH_0402HS-9N0EJTS_5%
L11
1 2
L12
1 2
@L13
@
L14
1 2
L15
1 2
@L16
@
L17
1 2
L18
1 2
@L19
@
L20
1 2
2
3
2
3
2
3
2
3
2
TMDSB_CON_CLK
3
TMDSB_CON_CLK#TMDS_CLK#_C
1.8P_0402_50V8
1.8P_0402_50V8
1
2
EMI depop location(EMC)
2
TMDSB_CON_P0
3
TMDSB_CON_N0
1.8P_0402_50V8
1.8P_0402_50V8
1
2
EMI depop location(EMC)
2
TMDSB_CON_P1
3
TMDSB_CON_N1
1.8P_0402_50V8
1.8P_0402_50V8
1
2
EMI depop location(EMC)
2
TMDSB_CON_P2
3
TMDSB_CON_N2
1.8P_0402_50V8
1.8P_0402_50V8
@
@
1
C279
C279
2
2
1.8P_0402_50V8
1.8P_0402_50V8
@
@
@
@
1
C273
C273
C274
C274
2
1.8P_0402_50V8
1.8P_0402_50V8
@
@
@
@
1
C275
C275
C276
C276
2
1.8P_0402_50V8
1.8P_0402_50V8
@
@
@
@
1
C277
C277
C278
C278
2
1.8P_0402_50V8
1.8P_0402_50V8
@
@
1
C382
C382
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AP2330W-7_SC59-3
AP2330W-7_SC59-3
+5V_RUN
@
@
C333
C333
1
1
U48
U48
2
IN
GND2OUT
3
+VHDMI_VCC
0.1U_0402_10V7K
0.1U_0402_10V7K
1
@
@
C87
C87
2
HDMI_HPD_SINK
CPU_DPB_CTRLDAT_R
CPU_DPB_CTRLCLK_R
HDMI_CEC
TMDSB_CON_CLK#
TMDSB_CON_CLK
TMDSB_CON_N0
TMDSB_CON_P0
TMDSB_CON_N1
TMDSB_CON_P1
TMDSB_CON_N2
TMDSB_CON_P2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C88
C88
2
JHDMI1
CONN@JHDMI1
CONN@
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CK-
11
CK_shield
10
CK+
9
D0-
8
D0_shield
7
D0+
6
D1-
5
D1_shield
4
D1+
3
D2-
2
D2_shield
1
D2+
LCN_AUF05-1922S10-0019
LCN_AUF05-1922S10-0019
GND
GND
GND
GND
20
21
22
23
EMI depop location(EMC)
+3.3V_RUN
B B
+3.3V_RUN
Q120B
Q120B
2
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
G
G
61
CPU_DPB_CTRLCLK<10>
CPU_DPB_CTRLDAT<10>
A A
DPB_HPD<10>
5
34
SGD
SGD
Q120A
Q120A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1M_0402_5%
1M_0402_5%
R475
R475
1 2
CPU_DPB_CTRLCLK_R +5V_HDMI_DDC
S
D
S
D
CPU_DPB_CTRLDAT_R
+3.3V_RUN
G
G
2
13
HDMI_HPD_SINK
D
S
D
S
Q121
Q121
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
1 2
R471 2.2K_0402_5%R 471 2.2K_0402_5%
1 2
R470 2.2K_0402_5%R 470 2.2K_0402_5%
1 2
R474 20K_0402_5%R474 20K_0402_5%
+5V_RUN
21
HDMI_CEC
RB751VM-40TE-17_SOD323-2
RB751VM-40TE-17_SOD323-2
0_0402_5%
0_0402_5%
12
@
@
R472
R472
@
@
D65
D65
TMDS_P2_C HDMI_OB
TMDS_N2_C
TMDS_P1_C
TMDS_N1_C
TMDS_P0_C
TMDS_N0_C
TMDS_CLK_C
TMDS_CLK#_C
R473 10K_0402_5%@ R473 10 K_0402_5%@
R465 470_0402_1%R465 470_0402_1%
R468 470_0402_1%R468 470_0402_1%
R467 470_0402_1%R467 470_0402_1%
R469 470_0402_1%R469 470_0402_1%
R462 470_0402_1%R462 470_0402_1%
R463 470_0402_1%R463 470_0402_1%
R464 470_0402_1%R464 470_0402_1%
R466 470_0402_1%R466 470_0402_1%
+3.3V_RUN
12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R460 10K_0402_5%R460 10K_0402_5%
13
2
G
G
D
D
Q29
Q29
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
S
S
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
HDMI Conn
HDMI Conn
HDMI Conn
LA-9431P
LA-9431P
LA-9431P
23 59Friday, May 17, 2013
23 59Friday, May 17, 2013
23 59Friday, May 17, 2013
0.3
0.3
0.3
Page 24
5
4
3
2
1
AUX/DDC SW for DPB to E-DOCK
U11
U11
1
D D
C C
SW_DPB_AUX< 21>
DPB_DOCK_AUX<34>
SW_DPB_AUX#<21>
DPB_DOCK_AUX#<34>
DPB_CA_DET<21,34>
12
SW_DPB_AUX_C
C94 0.1U_0402_10V7KC94 0.1U_0402_10V7K
DPB_DOCK_AUX
12
C95 0.1U_0402_10V 7KC95 0.1U_0402_10V7K
SW_DPB_AUX#_C
DPB_DOCK_AUX#
DPB_CA_DET
BE0
2
A0
3
B0
4
BE1
5
A1
6
B1
7
GND
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
+3.3V_RUN_VMM
12
13
2
G
G
14
VCC
13
BE3
12
A3
11
B3
10
BE2
9
A2
8
B2
100K_0402_5%
100K_0402_5%
R60
R60
D
D
Q10
Q10
BSS138W-7-F_SOT323-3
BSS138W-7-F_SOT323-3
S
S
DPB_CA_DET#
AUX/DDC SW for DPC to E-DOCK
U13
U13
1
12
SW_DPC_AUX<21>
SW_DPC_AUX#<21>
B B
C98 0.1U_0402_10V 7KC98 0.1U_0402_10V7K
DPC_DOCK_AUX<34>
C99 0.1U_0402_10V 7KC99 0.1U_0402_10V7K
DPC_DOCK_AUX#<34>
SW_DPC_AUX_C
DPC_DOCK_AUX
12
SW_DPC_AUX#_C
DPC_DOCK_AUX#
BE0
2
A0
3
B0
4
BE1
5
A1
6
B1
7
GND
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
VCC
BE3
BE2
14
13
12
A3
11
B3
10
9
A2
8
B2
+3.3V_RUN_VMM
1 2
C93
C93
0.1U_0402_25V6
0.1U_0402_25V6
VMM_DPB_CTRLCLK <21>
VMM_DPB_CTRLDAT <21>
+3.3V_RUN_VMM
1 2
C97
C97
0.1U_0402_25V6
0.1U_0402_25V6
VMM_DPC_CTRLCLK <21>
VMM_DPC_CTRLDAT <21>
+3.3V_RUN_VMM
100K_0402_5%
100K_0402_5%
R56
R56
12
DPC_CA_DET#
13
D
D
DPC_CA_DET<21,34>
A A
DPC_CA_DET
2
G
G
Q6
Q6
BSS138W-7-F_SOT323-3
BSS138W-7-F_SOT323-3
S
S
DELL CONFIDENTIAL/PROPRIETARY
1 2
R120 1M_0402_5%R 120 1M_0402 _5%
1 2
R121 1M_0402_5%R 121 1M_0402 _5%
5
DPB_CA_DET
DPC_CA_DET
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DP SW_DP125
DP SW_DP125
DP SW_DP125
LA-9431P
LA-9431P
LA-9431P
24 59Friday, May 17, 2013
24 59Friday, May 17, 2013
24 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 25
5
4
3
2
1
+3.3V_HDD
1 2
R155 10K_0402_5%@ R155 10K_0402_5%@
D D
PCH_PLTRST#_EC<29,31,36,37,9>
CLK_PCI_LPDEBUG<7>
SATA_PRX_DTX_P1_C<6>
SATA_PRX_DTX_N1_C< 6>
SATA_PTX_DRX_N1_C< 6>
SATA_PTX_DRX_P1_C<6>
+3.3V_HDD
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C113
C113
C114
1
2
C C
Place near JMINI3
C114
1
2
HDD_DEVSLP
PCH_PLTRST#_EC
12
12
C108 .01U_0402_16V7KC108 .01U_0402_16V7K
C109 .01U_0402_16V7KC109 .01U_0402_16V7K
12
C106 .01U_0402_16V7KC106 .01U_0402_16V7K
12
C105 .01U_0402_16V7KC105 .01U_0402_16V7K
HDD_DET#<6>
Mini mSATA H=4
JMINI3
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
HDD_DET#
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
LCN_DAN08-52406-0500
LCN_DAN08-52406-0500
CONN@JMINI3
CONN@
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
+3.3V_HDD+3.3V_H DD
2
2
4
4
6
6
8
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
HDD_DEVSLP
LPC_LFRAME# <29,36,37,7>
LPC_LAD3 < 29,36,37,7>
LPC_LAD2 < 29,36,37,7>
LPC_LAD1 < 29,36,37,7>
LPC_LAD0 < 29,36,37,7>
HDD_DEVSLP <12>
RING2 ,RING2_L
AUD_HP_OUT_L ,AUD_HP_OUT_L1
AUD_HP_OUT_R ,AUD_HP_OUT_R1
SLEEVE ,EXT_MIC
Trace width to 15mils.
B B
RING2<26>
AUD_HP_OUT_L<26>
AUD_HP_OUT_R<26>
SLEEVE<26>
RING2
AUD_HP_OUT_L
AUD_HP_OUT_R
SLEEVE
R491 0_0402_5%@R 491 0_0402_5%@
R492 0_0402_5%@R492 0_0402_5%@
12
12
BLM18AG221SN1D_2PEMC@L51 BLM18AG221SN1D_2PEMC@L51
12
BLM18AG221SN1D_2PEMC@L52 BLM18AG221SN1D_2PEMC@L52
12
+3.3V_RUN
12
R480
R480
10K_0402_5%
10K_0402_5%
RING2_L
AUD_HP_OUT_L1
AUD_HP_NB_SENSE
AUD_HP_OUT_R1
SLEEVE_L
Combo Jack
JHP1
CONN@JHP1
CONN@
7
3
1
5
6
2
4
SINGA_2SJ3080-003111F
SINGA_2SJ3080-003111F
Normal
Open
EMC@
EMC@
EMC@
2
3
D30
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
1
1
@
@
@
@
C441
C441
C440
C440
2
2
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
1
1
@
@
@
@
C443
C443
C442
C442
2
2
D30
L03ESDL5V0CC3-2_SOT23-3
L03ESDL5V0CC3-2_SOT23-3
1
EMC@
EMC@
2
3
D31
D31
L03ESDL5V0CC3-2_SOT23-3
L03ESDL5V0CC3-2_SOT23-3
1
EMC@
2
3
D32
D32
L03ESDL5V0CC3-2_SOT23-3
L03ESDL5V0CC3-2_SOT23-3
1
AUD_HP_NB_SENSE
12
R481
R481
100K_0402_5%
100K_0402_5%
AUD_HP_NB_SENSE <26,36>
EMI depop location(EMC)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Min Card/mSATA/Combo Jack
Min Card/mSATA/Combo Jack
Min Card/mSATA/Combo Jack
LA-9431P
LA-9431P
LA-9431P
25 59Friday, May 17, 2013
25 59Friday, May 17, 2013
25 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 26
2
Internal Speakers Header
L22 BL M18PG330SN1_2PEMC@ L22 BLM18PG 330SN1_2PEMC@
L23 BL M18PG330SN1_2PEMC@ L23 BLM18PG 330SN1_2PEMC@
L24 BL M18PG330SN1_2PEMC@ L24 BLM18PG 330SN1_2PEMC@
L25 BL M18PG330SN1_2PEMC@ L25 BLM18PG 330SN1_2PEMC@
C127 1000P_04 02_50V7K@C127 1000P_04 02_50V7K
61
D
D
G
G
S
S
1 2
1 2
1 2
1 2
AUD_SENSE_A
Q20B
Q20B
AUD_SENSE_B
Q21B
Q21B
DVDD_IO should match
with HDA Bus level
12
R149
@R149
@
33_0402_5%
33_0402_5%
1
C136
@C136
@
10P_0402_50V8J
10P_0402_50V8J
2
EMI depop location(EMC)
12
R152
R152
39.2K_0402_1%
39.2K_0402_1%
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
34
Q20A
Q20A
D
D
G
G
S
S
12
12
R157
61
D
D
S
S
R157
20K_0402_1%
20K_0402_1%
34
D
D
G
G
S
S
DMN66D0LDW-7_ SOT363-6
DMN66D0LDW-7_ SOT363-6
R156
R156
G
G
2
Q21A
Q21A
INT_SPKR_L+
INT_SPKR_LÂINT_SPKR_R+
INT_SPKR_R-
BCLK: Audio serial data bus bi t clock input/output
LRCK: Audio serial data bus w ord clock input/output
+3.3V_RUN_AUDIO
5
1
2
0.1U_0402_25V6
0.1U_0402_25V6
C137
C137
10U_0603_6.3V6M
10U_0603_6.3V6M
1
@
@
2
+3.3V_RUN_AUDIO
5
1
2
3
4
5
6
ACES_50209-0040N-001
ACES_50209-0040N-001
PCH_AZ_CODEC_BITCLK<6 >
PCH_AZ_CODEC_SDOUT<6 >
PCH_AZ_CODEC_SDIN0<6>
DAI_12MHZ#<34>
DAI_BCLK#<34>
DAI_DO#<34>
DAI_LRCK#<34>
DAI_DI<34>
AUD_NB_MUTE#<36>
1 2
R150 10K_0402_5%R150 10K_0402_5 %
AUD_HP_NB_SENSE <25,36>
C408
C408
12
R159
R159
100K_0402_5%
100K_0402_5%
DOCK_MIC_DET <36>DOCK_HP_DET<36>
2
40 mils trace keep 10 mil spacing
INT_SPK_L+
INT_SPK_LÂINT_SPK_R+
INT_SPK_R-
@
@
C124 1000P_04 02_50V7K@C124 1000P_04 02_50V7K
1
2
B B
@
@
C126 1000P_04 02_50V7K@C126 1000P_04 02_50V7K
C125 1000P_04 02_50V7K@C125 1000P_04 02_50V7K
1
1
1
2
2
2
Close to U17
EMI depop location(EMC)
Close to U17 pin5 Close to U17 pin6
PCH_AZ_CODEC_SDOUT PCH_ AZ_CODEC_BITCLK
12
R148
@R14 8
@
47_0402_5%
47_0402_5%
1
C135
@C135
@
0.1U_0402_10V7K
0.1U_0402_10V7K
2
Place closely to Pin 13.
2
Add for solve pop noise and de tect issue
A A
Place closely to Pin 14
+3.3V_RUN_AUDIO
39.2K_0402_1%
39.2K_0402_1%
12
R158
R158
100K_0402_5%
100K_0402_5%
DMN66D0LDW-7_ SOT363-6
DMN66D0LDW-7_ SOT363-6
CONN@
CONN@
JSPK1
JSPK1
PCH_AZ_CODEC_SYNC< 6>
PCH_AZ_CODEC_RST#<6>
1
2
3
4
GND
GND
+3.3V_RUN_AUDIO
1U_0603_10V6K
1U_0603_10V6K
1
1
C118
C118
2
2
Place R136 close to codec
R136 33_0402_5%R136 3 3_0402_5%
1 2
1 2
1 2
1 2
1 2
1
I2S_MCLK
I2S_BCLK
I2S_DO
I2S_LRCLK
I2S_DI#
1U_0603_10V6K
1U_0603_10V6K
C410
C410
R137 22_0402_5%R137 22_0402_5%
R139 22_0402_5%R139 22_0402_5%
R142 33_0402_5%R142 33_0402_5%
R143 0_0402_5%@R143 0_040 2_5%@
R144 0_0402_5%@R144 0_040 2_5%@
2
+3.3V_RUN_AUDIO
0.1U_0402_25V6
0.1U_0402_25V6
C119
C119
1U_0603_10V6K
1U_0603_10V6K
1
@
@
C405
C405
2
1 2
Place R142 close to codec
place at AGND and DGND plane
1 2
C141
C141
0.1U_0402_25V6
0.1U_0402_25V6
1 2
C142
C142
0.1U_0402_25V6
0.1U_0402_25V6
1 2
C144
C144
0.1U_0402_25V6
0.1U_0402_25V6
EMI Request(EMC)
SLEEVE
34
D
D
S
S
Q123A
Q123A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
+DVDD_CORE
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
1
1
C120
C120
2
2
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_SDOUT
PCH_AZ_SDIN0_R
PCH_AZ_CODEC_RST#
AUD_NB_MUTE#
+RTC_CELL
100K_0402_5%
100K_0402_5%
12
G
G
5
61
D
D
S
S
Q123B
Q123B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
C121
C121
U17
U17
1
DREG_OUT
3
DVDD-IO
9
DVDD
6
BIT-CLK
5
SDATA-OUT
10
SYNC
8
SDATA-IN
11
RESET#
15
I2S_MCLK
16
I2S_SCLK
17
I2S_DOUT
18
I2S_LRCK
24
I2S_DIN
19
MIC1-L
20
MIC1-R
47
EAPD/PD
7
DVSS
42
PVSS
49
GND
ALC3226-CG_QFN48_7 X7
ALC3226-CG_QFN48_7 X7
Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
place at Codec bottom side
PJP4
@PJP4
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
R202
R202
G
G
1 2
2
R213 0_0402_5%@ R213 0_0402_5%@
R220@ 0 _0402_5%R220@ 0_0402_5%
Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S
PCH_AZ_CODEC_RST#
1 2
AUD_NB_MUTE#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
AVDD2/HVDD(3.3)
LINE1-L/RING2
LINE1-R/SLEEVE
LINE1-VREFO
HPOUT-L/MIC-CAP
AVSS2/HPOUT-L
GPIO0/DMIC-CLK
GPIO1/DMIC-DATA
DMIC1/GPIO2
MONO-OUT/CBP
MIC1-VREFO
RUN_ON<36,37 ,39>
AVDD1
PVDD2
PVDD1
Sense A
Sense B
HP-OUT-R
SPK-L+
SPK-L-
SPK-R+
SPK-R-
PCBEEP
GPIO3
CBN
CBP/AVSS2
LDO-CAP
JDREF
CPVEE
VREF
AVSS1
27
38
45
39
13
14
28
29
23
31
33
32
40
41
44
43
12
2
4
46
48
37
35
36
21
22
34
25
30
26
R154 0_0402_5%@ R154 0_0402_5%@
place close to pin27
+VDDA_AVDD1
0.1U_0402_25V6
0.1U_0402_25V6
1
C115
C115
2
+VDDA_PVDD
AUD_SENSE_A
AUD_SENSE_B
RING2
SLEEVE
1 2
C385 1 0U_0603_6.3V6MC385 10U_0603_6.3V6M
AUD_OUT_L
AUD_OUT_R
INT_SPK_L+
INT_SPK_L-
INT_SPK_R+
INT_SPK_R-
AUD_PC_BEEP
DMIC_CLK_L DMIC_CLK
1 2
1 2
R162 18 _0402_5%R162 18_040 2_5%
R166 18 _0402_5%R166 18_040 2_5%
C145 0.1U_0402_25V6C14 5 0.1U_0402 _25V6
C146 0.1U_0402_25V6C14 6 0.1U_0402 _25V6
1 2
R170 33_0402_5%EMC@ R170 33_0402_5%EMC@
1 2
1
C134
C134
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2
Place C134 close to Codec
R186 0_040 2_5%@ R186 0_0402_5 %@
+ALC290_LDO_CAP
+ALC3226_CPVEE
+ALC3226_VREF
+5V_ALW
1 2
+3.3V_ALW
1 2
10U_0603_6.3V6M
10U_0603_6.3V6M
PBY160808T-600Y-N_2P
PBY160808T-600Y-N_2P
place close to pin38
1
C117
C117
2
+VREFOUT
12
12
Place close to Codec
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
1
2
C167
C167
2
1
1
L21
L21
+VDDA_AVDD2
0.1U_0402_25V6
0.1U_0402_25V6
1
2
C169
C169
1
2
3
4
5
6
7
+5V_RUN_AUDIO + 3.3V_RUN_AUDIO
10U_0603_6.3V6M
10U_0603_6.3V6M
place close to pin39 place close to pin45
1
C150
C150
C116
C116
2
RING2 <25>
SLEEVE <25>
SLEEVE/RING2/AUD_HP_OUT_R/AUD_HP_OUT_L
please keep 15mils trace
AUD_HP_OUT_L
AUD_HP_OUT_R
1 2
R194 10K_0402_5%@ R194 10K_0402_5%@
1 2
R153 10K_0402_5%@ R153 10K_0402_5%@
1 2
R147 1K_0402_5%R147 1K_0402_5 %
1 2
R151 1K_0402_5%R151 1K_0402_5 %
DMIC_CLK < 22>
DMIC0 <22>
EN_I2S_NB_CODEC# < 36>
10U_0603_6.3V6M
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
C138
C138
2
U18
U18
VIN1
VIN1
ON1
VBIAS
ON2
VIN2
VIN2
TPS22966DPUR_SON14_2X3~D
TPS22966DPUR_SON14_2X3~D
10U_0603_6.3V6M
20K_0402_1%
20K_0402_1%
12
1
R39
R39
2
VOUT1
VOUT1
CT1
GND
CT2
VOUT2
VOUT2
GPAD
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet of
Date: Sheet of
1
Date: Sheet of
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
1
1
C128
C128
C129
C129
2
2
AUD_HP_OUT_L <25>
AUD_HP_OUT_R < 25>
C140
C140
14
13
+5V_RUN_AUDIO_U18
C147
C147
12
11
10
C148
C148
9
8
+3.3V_RUN_AUDIO_U18
15
R140
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C122
C122
C123
C123
2
RING2
R187 2.2K_0402_5%R187 2.2K_0402_5%
SLEEVE
R197 2.2K_0402_5%R197 2.2K_0402_5%
+5V_RUN_AUDIO
12
R130
@R130
@
0_0805_5%
0_0805_5%
1 2
1 2
+VREFOUT
DMIC_CLK
place close to pin2
+VREFOUT
12
@R140
@
0_0603_5%
0_0603_5%
0.1U_0402_25V6
0.1U_0402_25V6
1
2
SPKR <1 2>
BEEP <37>
EMI depop location(EMC)
+5V_RUN_AUDIO
12
PJP24
PJP24
PAD-OPEN1x1m
PAD-OPEN1x1m
1 2
1 2
470P_0402_50V7K
470P_0402_50V7K
1 2
1000P_0402_50V7K
1000P_0402_50V7K
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Azalia (HD) Codec-ALC3226
Azalia (HD) Codec-ALC3226
Azalia (HD) Codec-ALC3226
LA-9431P
LA-9431P
LA-9431P
C188 0.1U_0 402_10V7K@ C188 0.1U_040 2_10V7K@
1
PJP25 PAD-OPEN1x1mPJP25 PAD-OPEN1x1m
C139
@C139
@
0.1U_0402_10V7K
0.1U_0402_10V7K
2
26 59Friday, May 17, 2013
26 59Friday, May 17, 2013
26 59Friday, May 17, 2013
12
+3.3V_RUN_AUDIO
1U_0603_10V4Z
1U_0603_10V4Z
1
@
@
C131
C131
2
22P_0402_50V8J
22P_0402_50V8J
1
@
@
C130
C130
2
0.3
0.3
0.3
Page 27
5
D D
4
3
2
1
XB use SA00006ZP00 (S IC AP2337SA-7 SOT-23 3P LOAD SWITCH)
0.1U_0402_16V4Z
+3.3V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
C152
C152
2
DOCKED<21,28,32,36>
DDI2_LANE_N0<10>
DDI2_LANE_P0<10>
DDI2_LANE_N1<10>
DDI2_LANE_P1<10>
DDI2_LANE_N2<10>
DDI2_LANE_P2<10>
DDI2_LANE_N3<10>
DDI2_LANE_P3<10>
CPU_DPC_AUX#<10>
CPU_DPC_AUX<10>
C411
C411
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
1
@
@
C153
C153
C154
C154
2
2
DOCKED
DOCKED
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C451
C451
1
2
U19
U19
12
VDD
21
VDD
34
VDD
2
GPU_SEL
3
D0-
4
D0+
6
D1-
7
D1+
8
D2-
9
D2+
10
D3-
11
D3+
13
AUX-
14
AUX+
5
AUX_HPD_SEL
18
HPD
1
GND
17
GND
22
GND
43
HGND
PI3VDP12412ZHEX_TQFN42_9X3P5~D
PI3VDP12412ZHEX_TQFN42_9X3P5~D
DOCKED
function
1
Dock
0
mini DP
42
D0-A
41
D0+A
40
D1-A
39
D1+A
38
D2-A
37
D2+A
36
D3-A
35
D3+A
24
AUX-A
23
AUX+A
16
HPD_A
33
D0-B
32
D0+B
31
D1-B
30
D1+B
29
D2-B
28
D2+B
27
D3-B
26
D3+B
19
AUX-B
20
AUX+B
15
HPD_B
25
OE
R161 4.7K_0402_5%R161 4.7K_0402_5%
mDP_LANE_N0
mDP_LANE_P0
mDP_LANE_N1
mDP_LANE_P1
mDP_LANE_N2
mDP_LANE_P2
mDP_LANE_N3
mDP_LANE_P3
mDP_AUX#
mDP_AUX
mDP_HPD
12
1 2
C163 0.1U_0402_10V7KC163 0.1U _0402_10V7K
1 2
C164 0.1U_0402_10V7KC164 0.1U _0402_10V7K
1 2
C165 0.1U_0402_10V7KC165 0.1U _0402_10V7K
1 2
C166 0.1U_0402_10V7KC166 0.1U _0402_10V7K
1 2
C168 0.1U_0402_10V7KC168 0.1U _0402_10V7K
1 2
C170 0.1U_0402_10V7KC170 0.1U _0402_10V7K
1 2
C172 0.1U_0402_10V7KC172 0.1U _0402_10V7K
1 2
C173 0.1U_0402_10V7KC173 0.1U _0402_10V7K
DP12412_N0 <21>
DP12412_P0 <21>
DP12412_N1 <21>
DP12412_P1 <21>
DP12412_N2 <21>
DP12412_P2 <21>
DP12412_N3 <21>
DP12412_P3 <21>
DP12412_AUX# <21>
DP12412_AUX <21>
DP12412_HPD <21>
+3.3V_RUN
mDP_LANE_N0_C
mDP_LANE_P0_C
mDP_LANE_N1_C
mDP_LANE_P1_C
mDP_LANE_N2_C
mDP_LANE_P2_C
mDP_LANE_N3_C
mDP_LANE_P3_C
4.7U_0603_6.3V6K
+3.3V_RUN
1 2
C C
R163 100K_0402_5%R163 100K_0402_5%
1 2
R164 100K_0402_5%R164 100K_0402_5%
1 2
R165 100K_0402_5%R165 100K_0402_5%
R167 1M_0402_5%R167 1M_0402_5%
1 2
R168 5.1M_0402_5%R168 5.1M_0402_5%
mDP_AUX#_C
mDP_HPD
12
mDP_AUX_C
mDP_CA_DET
DPB_MB_P14
4.7U_0603_6.3V6K
1
C151
C151
2
DPC_HPD<10>
ESD solution for black screen issue
B B
AUX/DDC SW for DPC to Mini DP
C174
C174
0.1U_0402_10V7K
0.1U_0402_10V7K
12
SW_mDP_AUX_CmDP_AUX
mDP_AUX_C
12
C175 0.1U_0402_10V7KC175 0.1U_0402_10V7K
SW_mDP_AUX#_CmDP_AUX#
mDP_AUX#_C
U49
U49
1
2
3
4
5
6
7
VCC
BE0
BE3
A0
B0
BE1
A1
BE2
B1
GND
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
14
13
12
A3
11
B3
10
9
A2
8
B2
+3.3V_RUN
1 2
CPU_DPC_CTRLCLK <10>
CPU_DPC_CTRLDAT <10>
0.1U_0402_16V4Z
AP2337SA-7 SOT-23
AP2337SA-7 SOT-23
+3.3V_RUN
@
@
C383
C383
1
U50
U50
2
mDP_AUX#_C
mDP_LANE_N2_C
mDP_AUX_C
mDP_LANE_P2_C
mDP_LANE_N3_C
mDP_LANE_N1_C
mDP_LANE_P3_C
mDP_LANE_P1_C
DPB_MB_P14
mDP_LANE_N0_C
mDP_CA_DET
mDP_LANE_P0_C
mDP_HPD
1
IN
GND2OUT
3
+VDISPLAY_VCC
.01U_0402_16V7K
.01U_0402_16V7K
1
C171
C171
2
JmDP1
CONN@JmDP1
CONN@
20
DP_PWR
19
GND
18
AUX_CH_N
17
LANE2_N
16
AUX_CH_P
15
LANE2_P
14
GND
13
GND
12
LANE3_N
11
LANE1_N
10
LANE3_P
9
LANE1_P
8
GND
7
GND
6
CONFIG2
5
LANE0_N
4
CONFIG1
3
LANE0_P
2
HOT-PLUG
1
GND
ACON_MAR2C-20K1800
ACON_MAR2C-20K1800
GND4
GND3
GND2
GND1
24
23
22
21
+3.3V_RUN
100K_0402_5%
100K_0402_5%
12
R67
R67
A A
mDP_CA_DET#
13
D
D
mDP_CA_DET
5
2
G
G
Q31
Q31
BSS138W-7-F_SOT323-3
BSS138W-7-F_SOT323-3
S
S
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
mDP/DP12412
mDP/DP12412
mDP/DP12412
LA-9431P
LA-9431P
LA-9431P
27 59Friday, May 17, 2013
27 59Friday, May 17, 2013
27 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 28
5
+3.3V_RUN
10K_0402_5%
10K_0402_5%
R331
R331
1 2
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
12
LAN_WAKE#_R
1 2
R145 0_0402_5%@ R145 0_0402_5%@
R180 0_0402_5%@ R180 0_0402_5%@
1
B
2
A
1 2
LAN_RST#<12>
PLTRST_LAN#<9>
TC7SH08FU_SSOP5~D
PM_LANPHY_ENABLE<12>
R171 10K_0402_5%@ R171 10K_0402_5%@
R172 10K_0402_5%@ R172 10K_0402_5%@
R176 4.7K_0402_5%@ R176 4.7K_0402_5%@
TC7SH08FU_SSOP5~D
1 2
1 2
D D
+3.3V_LAN
C C
C406
@C406
@
0.1U_0402_10V7K
0.1U_0402_10V7K
5
U20
P
4
O
G
3
33P_0402_50V8J
33P_0402_50V8J
12
@U20
@
PLT_LAN_RST#
C189
C189
2
1
100K_0402_5%
100K_0402_5%
12
+3.3V_LAN
10K_0402_5%
10K_0402_5%
12
10K_0402_5%
10K_0402_5%
12
@
@
R25
R25
@R173
@
R173
@R182
@
R182
R183 0_0402_5%@ R183 0_0402_5%@
3
4
LANCLK_REQ#<10,7>
CLK_PCIE_LAN<7>
CLK_PCIE_LAN#<7>
PCIE_PRX_GLANTX_P3<11>
PCIE_PRX_GLANTX_N3<11>
PCIE_PTX_GLANRX_P3<11>
PCIE_PTX_GLANRX_N3<11>
LAN_SMBCLK<7>
LAN_SMBDATA<7>
LAN_WAKE#<12,37>
SMBus Device Ad dress 0xC8
Pin 2 is WAKE_EN in Clarkville
1 2
Y3
Y3
1
IN
OUT
2
GND
GND
25MHZ_18PF_7V25000034
25MHZ_18PF_7V25000034
2
1
LAN_DISABLE#_R<36>
T92 PAD~D@ T92 PAD~D@
T93 PAD~D@ T93 PAD~D@
12
33P_0402_50V8J
33P_0402_50V8J
C190
C190
R169 0_0402_5%@ R169 0_0402_5%@
R206
R206
1M_0402_5%
1M_0402_5%
C179 0.1U_0402_10V7KC179 0.1U_0402_10V7K
C176 0.1U_0402_10V7KC176 0.1U_0402_10V7K
C178 0.1U_0402_10V7KC178 0.1U_0402_10V7K
C181 0.1U_0402_10V7KC181 0.1U_0402_10V7K
R174 0_0402_5%@ R174 0_0402_5%@
R177 0_0402_5%@ R177 0_0402_5%@
R179 0_0402_5%@ R179 0_0402_5%@
LAN ANALOG SWITCH
+3.3V_LAN
Layout Notice : Place bead as
close PI3L500 as possible
B B
DOCKED
A A
LAN_TX1+
LAN_TX1-
LAN_TX2-
LAN_TX3-
1 2
L27 12NH_0603CS-120EJTS_5%EMC@ L27 12NH_0603CS-120EJTS_5%EMC@
1 2
L28 12NH_0603CS-120EJTS_5%EMC@ L28 12NH_0603CS-120EJTS_5%EMC@
1 2
L29 12NH_0603CS-120EJTS_5%EMC@ L29 12NH_0603CS-120EJTS_5%EMC@
1 2
L30 12NH_0603CS-120EJTS_5%EMC@ L30 12NH_0603CS-120EJTS_5%EMC@
1 2
L31 12NH_0603CS-120EJTS_5%EMC@ L31 12NH_0603CS-120EJTS_5%EMC@
1 2
L32 12NH_0603CS-120EJTS_5%EMC@ L32 12NH_0603CS-120EJTS_5%EMC@
1 2
L33 12NH_0603CS-120EJTS_5%EMC@ L33 12NH_0603CS-120EJTS_5%EMC@
1 2
L34 12NH_0603CS-120EJTS_5%EMC@ L34 12NH_0603CS-120EJTS_5%EMC@
DOCKED<21,27,32,36>
1: TO DOCK
0: TO RJ45
LAN_TX0+RLAN_TX0+
LAN_TX0-RLAN_TX0-
LAN_TX1+R
LAN_TX1-R
LAN_TX2+RLAN_TX2+
LAN_TX2-R
LAN_TX3+RLAN_TX3+
LAN_TX3-R
DOCKED
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
2
0.1U_0402_25V6
0.1U_0402_25V6
1
1
C193
C193
C192
C192
2
2
C194
C194
U23
U23
2
A0+
3
A0-
6
A1+
7
A1-
9
A2+
10
A2-
11
A3+
12
A3-
13
SEL
15
LEDA0
16
LEDA1
42
LEDA2
5
PD
43
PAD_GND
PI3L720ZHEX_TQFN42_9X3P5~D
PI3L720ZHEX_TQFN42_9X3P5~D
1 2
CLK_PCIE_LAN
CLK_PCIE_LAN#
1 2
1 2
1 2
1 2
1 2
39
4
LANCLK_REQ#_R
PLT_LAN_RST#
12
PCIE_PRX_GLANTX_P3_C
12
PCIE_PRX_GLANTX_N3_C
PCIE_PTX_GLANRX_P3_C
PCIE_PTX_GLANRX_N3_C
LAN_SMBCLK_R
LAN_SMBDATA_R
LAN_WAKE#_R
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
TP_LAN_JTAG_TDI
TP_LAN_JTAG_TDO
TP_LAN_JTAG_TMS
TP_LAN_JTAG_TCK
XTALOXTALO_R
XTALI
LAN_TEST_EN
1K_0402_5%
1K_0402_5%
12
12
R184
R184
VDD1VDD4VDD8VDD14VDD21VDD30VDD
3.01K_0402_1%
3.01K_0402_1%
LEDB0
LEDB1
LEDB2
LEDC0
LEDC1
LEDC2
RES_BIAS
R185
R185
B0+
B0-
B1+
B1-
B2+
B2-
B3+
B3-
C0+
C0-
C1+
C1-
C2+
C2-
C3+
C3-
38
37
34
33
29
28
25
24
17
18
41
36
35
32
31
27
26
23
22
19
20
40
3
XB use SA000066 W3L(S IC WGI218 LM SLK3A B1 QFN 48P PHY )
U21
U21
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
2
LANWAKE_N
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTAG_TDI
34
JTAG_TDO
33
JTAG_TMS
35
JTAG_TCK
9
XTAL_OUT
10
XTAL_IN
30
TEST_EN
12
RBIAS
SW_ACTLED_YEL#
SW_100_ORG#
SW_10_GRN#
DOCK_LOM_ACTLED_YEL#
DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD10LED_GRN#
JTAG LED
JTAG LED
WGI218LM-SLK3A-B1_QFN48_6X6~D
WGI218LM-SLK3A-B1_QFN48_6X6~D
SW_LAN_TX0+
SW_LAN_TX0-
SW_LAN_TX1+
SW_LAN_TX1-
SW_LAN_TX2+
SW_LAN_TX2-
SW_LAN_TX3+
SW_LAN_TX3-
DOCK_LOM_TRD0+
DOCK_LOM_TRD0-
DOCK_LOM_TRD1+
DOCK_LOM_TRD1-
DOCK_LOM_TRD2+
DOCK_LOM_TRD2-
DOCK_LOM_TRD3+
DOCK_LOM_TRD3-
MDI
MDI
PCIE
PCIE
RSVD_VCC3P3_1
SMBUS
SMBUS
13
14
17
18
20
21
23
24
6
VCT_LAN_R1
1
+RSVD_VCC3P3_1
5
4
15
19
29
47
46
37
43
11
40
22
16
8
7
REGCTL_PNP10
49
LAN_TX0+
LAN_TX0-
LAN_TX1+
LAN_TX1-
LAN_TX2+
LAN_TX2-
LAN_TX3+
LAN_TX3-
reference INTEL r217 circuit version1.7
+3.3V_LAN_OUT
+0.9V_LAN
MDI_PLUS0
MDI_MINUS0
MDI_PLUS1
MDI_MINUS1
MDI_PLUS2
MDI_MINUS2
MDI_PLUS3
MDI_MINUS3
SVR_EN_N
VDD3P3_IN
VDD3P3_4
VDD3P3_15
VDD3P3_19
VDD3P3_29
VDD0P9_47
VDD0P9_46
VDD0P9_37
VDD0P9_43
VDD0P9_11
VDD0P9_40
VDD0P9_22
VDD0P9_16
VDD0P9_8
CTRL0P9
VSS_EPAD
SW_LAN_TX0+ <35>
SW_LAN_TX0- <35>
SW_LAN_TX1+ <35>
SW_LAN_TX1- <35>
SW_LAN_TX2+ <35>
SW_LAN_TX2- <35>
SW_LAN_TX3+ <35>
SW_LAN_TX3- <35>
DOCK_LOM_TRD0+ <34>
DOCK_LOM_TRD0- <34>
DOCK_LOM_TRD1+ <34>
DOCK_LOM_TRD1- <34>
DOCK_LOM_TRD2+ <34>
DOCK_LOM_TRD2- <34>
DOCK_LOM_TRD3+ <34>
DOCK_LOM_TRD3- <34>
DOCK_LOM_ACTLED_YEL# <34>
DOCK_LOM_SPD100LED_ORG# <34>
DOCK_LOM_SPD10LED_GRN# <34>
R175 0_0402_5%@ R175 0_0402_5%@
R178 4.7K_0402_5%R178 4.7K_0402_5%
1
2
1U_0603_10V6K
1U_0603_10V6K
C182
C182
12
12
R181 0_0603_5%@ R181 0_0603_5%@
SW_ACTLED_YEL#
SW_100_ORG#
Pin 6 is SVR_EN in Clarkville
+3.3V_LAN
12
SIO_SLP_LAN#<36,9>
MCARD_WWAN_PWREN<36>
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
+3.3V_LAN
R196 0_0402_5%@ R196 0_0402_5%@
MCARD_WWAN_PWREN
1 2
LOM_SPD100LED_ORG#
LOM_SPD10LED_GRN#
61
LAN_ACTLED_YEL#
MASK_BASE_LEDS#
34
LED_100_ORG#
MASK_BASE_LEDS#
MCARD_WWAN_PWREN
R50 100K_0402_5%R50 100K_0402_5%
Q32B
Q32B
S
D
S
D
G
G
2
Q32A
Q32A
SGD
SGD
5
2
+3.3V_ALW
12
+5V_ALW
+3.3V_LAN
1
B
2
A
LAN_ACTLED_YEL# <35>
MASK_BASE_LEDS# <40>
LED_100_ORG# <35>
REGCTL_PNP10
+0.9V_LAN
1
2
3
4
5
6
7
C198
@C198
@
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
5
P
4
O
G
U24
U24
NL17SZ08DFT2G_SSOP5~D
NL17SZ08DFT2G_SSOP5~D
3
1 2
L264.7UH_CBC2012T4R7M_20% L264.7UH_CBC2012T4R7M_20%
Place C117, C180 and L26 close to U21
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
C183
C183
2
Note:
+1.0V_LAN will work at 0.95V to 1.15V
U22
U22
VIN1
VIN1
ON1
VBIAS
ON2
VIN2
VIN2
TPS22966DPUR_SON14_2X3~D
TPS22966DPUR_SON14_2X3~D
1
1
C184
C184
2
2
14
VOUT1
13
VOUT1
12
CT1
11
GND
10
CT2
9
VOUT2
8
VOUT2
15
GPAD
WLAN_LAN_DISB# <36>
SW_10_GRN#
+0.9V_LAN
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
C177
C177
1
1
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
C186
C186
C185
C185
2
+3.3V_LAN_U22
1 2
C407 470P_0402_50V7KC407 470P_0402_50V7K
1 2
C427 470P_0402_50V7KC427 470P_0402_50V7K
+3.3V_mSATA_WWAN_U22
Q33B
Q33B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Q33A
Q33A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
SGD
SGD
5
C180
C180
22U_0805_6.3V6M
22U_0805_6.3V6M
C187
C187
1
2
61
S
D
S
D
G
G
2
34
1
+3.3V_LAN
12
PJP20
PJP20
PAD-OPEN1x1m
PAD-OPEN1x1m
1 2
C426 0.1U_0402_10V7KC426 0.1U_0402_10V7K
PJP21 PAD-OPEN1x1mPJ P21 PAD-OPEN1x1m
1
C425
@C425
@
0.1U_0402_10V7K
0.1U_0402_10V7K
2
LED_10_GRN#
MASK_BASE_LEDS#
12
+3.3V_mSATA_WWAN
LED_10_GRN# <35>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: S heet of
Date: S heet of
Date: S heet of
Compal Electronics, Inc.
LAN Lewisville / LAN SW
LAN Lewisville / LAN SW
LAN Lewisville / LAN SW
LA-9431P
LA-9431P
LA-9431P
1
28 59Friday, May 17, 2013
28 59Friday, May 17, 2013
28 59Friday, May 17, 2013
0.3
0.3
0.3
Page 29
5
D D
+3.3V_RUN_TPM+3.3V_RUN
PJP5
@PJP5
@
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
PCH_TPM_LPC_EN<7>
SP_TPM_LPC_EN<36>
C C
PCH_TPM_LPC_EN
LPC_LAD0<25,36,37,7>
LPC_LAD1<25,36,37,7>
LPC_LAD2<25,36,37,7>
LPC_LAD3<25,36,37,7>
CLK_PCI_TPM_TCM<7>
LPC_LFRAME#<25,36,37,7>
PCH_PLTRST#_EC<25,31,36,37,9>
IRQ_SERIRQ<12,36,37>
CLKRUN#<10,36,37,9>
R198 10_0402_5%@R198 10_0402_5%@
R193 0_0402_5%@ R193 0_04 02_5%@
+3.3V_RUN_TPM
1 2
1 2
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
IRQ_SERIRQ
CLKRUN#
0.1U_0402_25V6
0.1U_0402_25V6
4700P_0402_25V7K
4700P_0402_25V7K
1
1
@
@
C200
C200
C201
C201
2
2
SP_TPM_LPC_EN_R
ATMEL TPM for E4
5
28
26
23
20
17
21
22
16
27
15
1
2
3
XB use SA00004WQ50(S IC AT97SC3204-X4A12-ABF TSSOP 28P TPM)
4
U25
U25
VCC_0
SB3V
LPCPD#
LAD0
LAD1
LAD2
LAD3
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
ATEST_1
ATEST_2
ATEST_3
AT97SC3204-X4A12-ABF _TSSOP28
AT97SC3204-X4A12-ABF _TSSOP28
VCC_1
VCC_2
V_BAT
NBO_13
NBO_14
GPIO6
TESTBI
TESTI
NC_7
GND_4
GND_11
GND_18
GND_25
3
+3.3V_RUN_TPM
2200P_0402_50V7K
2200P_0402_50V7K
1
@
@
C203
10
19
24
12
13
14
6
9
8
7
4
11
18
25
C203
2
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
1
C202
C202
2
0.1U_0402_25V6
0.1U_0402_25V6
1
1
C384
C384
C204
C204
2
2
+3.3V_SUS
1 2
R190 2.2K_0402_5%R190 2.2K_0402_5%
1 2
R191 2.2K_0402_5%R191 2.2K_0402_5%
1 2
R195 1M_0402_5%R 195 1M_0402 _5%
USH_PWR_STATE #
+3.3V_SUS
+3.3V_RUN
+5V_RUN
USH_SMBCLK
USH_SMBDAT
2
1
USH board conn
CONN@
CONN@
JUSH1
JUSH1
1
1
USBP4-<11>
USBP4+<11 >
USH_SMBCLK<37>
USH_SMBDAT< 37>
BCM5882_ALERT#<36>
PLTRST_USH#<9>
USH_PWR_STATE #<36>
CONTACTLESS_DET#<10>
USH_DET#<12>
USH_SMBCLK
USH_SMBDAT
USH_PWR_STATE #
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
E-T_6718K-Y20N-00L
E-T_6718K-Y20N-00L
GND
GND
21
22
+5V_RUN
1
2
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C208
C208
+3.3V_RUN
1
2
0.1U_0402_25V6
0.1U_0402_25V6
@
@
+3.3V_SUS
C207
C207
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C206
C206
1
2
ST change to 6718K-Y20N-00L
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USH board conn / TPM
USH board conn / TPM
USH board conn / TPM
LA-9431P
LA-9431P
LA-9431P
29 59Friday, May 17, 2013
29 59Friday, May 17, 2013
29 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 30
A
+3.3V_RUN +3.3V_RUN
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
C210
C210
0.1U_0402_25V6
12
12
C211
C211
C212
C212
L35
L35
1 2
BLM15AG601SN1D_2P
BLM15AG601SN1D_2P
B
C215 close to U27.9
C213 C214 close to U27.35
+3.3V_RUN_AIN
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
12
12
12
C214
C214
C213
C213
C
0.1U_0402_25V6
0.1U_0402_25V6
C215
C215
D
+3.3V_RUN_CARD +1.8V_R UN_CARD
E
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
12
@
@
C227
C227
0.1U_0402_25V6
@
@
@
@
C228
C228
C229
C229
12
12
1 1
C210 close to U27.42
C211 C212 close to U27.23
C227 near U27.22 C228 C229 near U27.24
homestay ES1(no SD4.0)
+1.2V_LDO
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
C223
C223
C217
C217
1 2
+1.2V_LDO
2 2
3 3
+3.3V_RUN
IO_LDOSEL
1 2
1 2
L36
L36
1 2
BLM15AG601SN1D_2P
BLM15AG601SN1D_2P
PCIE_PTX_MMIRX_P5<11>
PCIE_PTX_MMIRX_N5<11>
PCIE_PRX_MMITX_P5<11>
PCIE_PRX_MMITX_N5<11>
MEDIACARD_PWR EN<11,12>
MEDIACARD_IRQ#<12>
12
R212
R212
100K_0402_5%
100K_0402_5%
12
R214@
R214@
100K_0402_5%
100K_0402_5%
+3.3V_RUN
use 3.3V
0.1U_0402_25V6
0.1U_0402_25V6
C218
C218
+1.2V_LDO_AIN
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C230
C230
1 2
CLK_PCIE_MMI#<7>
CLK_PCIE_MMI<7>
MMICLK_REQ#<7>
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C219
C219
C224
C224
1 2
1 2
0.1U_0402_25V6
0.1U_0402_25V6
1 2
C235 0.1U_0402_10V7KC235 0.1U _0402_10V7K
C236 0.1U_0402_10V7KC236 0.1U _0402_10V7K
C237 0.1U_0402_10V7KC237 0.1U _0402_10V7K
C238 0.1U_0402_10V7KC238 0.1U _0402_10V7K
1 2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
@
@
C232
C232
C231
C231
1 2
1 2
1 2
1 2
1 2
1 2
PE_RST#
IO_LDOSEL
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C226
C226
C225
C225
1 2
0.1U_0402_25V6
0.1U_0402_25V6
C233
C233
C234
C234
1 2
1 2
R205 191_0402_1%R205 191_0402_1%
PCIE_PTX_MMIRX_P5_C
PCIE_PTX_MMIRX_N5_C
PCIE_PRX_MMITX_P5_C
PCIE_PRX_MMITX_N5_C
PE_REXT
PLTRST_MMI#<9>
U27
U27
9
27
42
23
13
11
10
41
36
31
28
1
4
6
5
7
8
2
3
15
14
16
17
18
OZ777FJ2LN_QFN48_6X6
OZ777FJ2LN_QFN48_6X6
MEDIACARD_RST#<12>
SSI ES2(symbol should be update 26~36 pin swap)
12
PE_33VCCAIN
UHSII_33VCCAIN/NC
SD_33VCCD
SD_SKT_33VIN
AUX _33VIN
MAIN_LDO_VIN
MAIN_LDO_12VOUT
CORE_12VCCD
UHSII_12VCCAIN/NC
UHSII_12VCCAIN/NC
UHSII_12VCCAIN/NC
PE_12VCCAIN
PE_REXT
PE_RXP
PE_RXM
PE_TXP
PE_TXM
PE_REFCLKM
PE_REFCLKP
PE_RST#_GATE#
MAIN_LDO_EN
DEV_WAKE#
CLKREQ#
IO0_LDOSEL
R443 0_0402_5%@R 443 0_0402_5%@
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
OZ777FJ2LN
OZ777FJ2LN
1 2
+3.3V_RUN
C3410.1U_0402_25V 6 @ C3410.1U_0402_25V6 @
1 2
5
U26
@U26
@
1
P
B
4
O
2
A
G
3
100K_0402_5%
100K_0402_5%
12
PE_RST#
@
@
R27
R27
AUX_LDO_CAP
SD_IO_LDO_CAP
SD_SKT_33VOUT
SD_SKT_18VOUT
SD_WPI
SD_CD#
SD_CLK
SD_CMD
MMC_D7
MMC_D6
MMC_D5
MMC_D4
SD_D3
SD_D2
SD_D1
SD_D0
SD_RCLK_M/NC
SD_RCLK_P/NC
SD_D1P/NC
SD_D1M/NC
SD_D0M/NC
SD_D0P/NC
SD_REXT/NC
LED#
GND
Near to JSD1
+3.3V_RUN_CARD
+1.8V_RUN_CARD
+AUX_LDO
25
+SD_IO_LDO
22
24
20
SDWP
21
SD/MMCCD#
43
SD/MMCCLK_R
45
SD/MMCCMD
39
40
44
46
47
SD/MMCDAT3
48
SD/MMCDAT2
37
SD/MMCDAT1
38
SD/MMCDAT0
29
30
32
33
34
35
26
1 2
R211 4.7K_0402_1%R211 4.7K_0402_1%
19
49
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
1
1
@
@
C240
C240
C239
C239
2
2
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
C246
C246
C247
C247
2
2
+3.3V_RUN_CARD
+1.8V_RUN_CARD
EMC@
EMC@
1 2
R230 10_0402_5%
R230 10_0402_5%
1 2
R410 0_0402_5%@R 410 0_0402_5%@
1 2
R341 0_0402_5%@R 341 0_0402_5%@
SD_UHS2_D1P
SD_UHS2_D1N
SD_UHS2_D0N
SD_UHS2_D0P
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
@
@
C221
C221
C216
C216
C220
C220
1 2
1 2
1 2
SD/MMCDAT3_R
SD/MMCDAT2_R
EMI depop location(EMC)
+3.3V_RUN_CARD
+1.8V_RUN_CARD
SD/MMCCD#
0.1U_0402_25V6
0.1U_0402_25V6
1M_0402_5%
1M_0402_5%
12
R493
1
2
R493
C256
C256
O2 request
1U_0402_6.3V6K
1U_0402_6.3V6K
C222
C222
2
1
SD/MMCCLK
1
2
please routing daisy chain
1. from U27.38 (SD_D0) -> U27.32 (SD_RCLK_P) -> L46.4
2. From U27.37 (SD_D1) -> U27.33 (SD_RCLK_N) -> L46.1
SD/MMCDAT0
SD/MMCDAT1
SD_UHS2_D0P
5P_0402_50V8C
5P_0402_50V8C
@
@
C255
C255
SD_UHS2_D1P
SD/MMCCMD
SD/MMCCLK
SD/MMCCD#
SDWP
SD/MMCDAT0_D
SD/MMCDAT1_D
SD/MMCDAT2_R
SD/MMCDAT3_R
SD_UHS2_D0P_D
SD_UHS2_D0N_D
SD_UHS2_D1P_D
SD_UHS2_D1N_D
1 2
R231 0_0402_5%@R 231 0_0402_5%@
L46
@L46
@
4
4
1
1
DLW21SN900SQ2L-0805_4P
DLW21SN900SQ2L-0805_4P
1 2
R297 0_0402_5%@R 297 0_0402_5%@
1 2
R306 0_0402_5%@R 306 0_0402_5%@
L47
@L47
@
4
4
1
1
DLW21SN900SQ2L-0805_4P
DLW21SN900SQ2L-0805_4P
1 2
R315 0_0402_5%@R 315 0_0402_5%@
1 2
R333 0_0402_5%@R 333 0_0402_5%@
L48
@L48
@
1
1
4
4
DLW21SN900SQ2L-0805_4P
DLW21SN900SQ2L-0805_4P
1 2
R337 0_0402_5%@R 337 0_0402_5%@
MMC+ need confirm
JSD1
4
VDD/VDD1
14
VDD2
2
CMD
5
CLK
18
CARD DETECT
19
WRITE PROTEC
7
DAT0/RCLK+
8
DAT1/RCLK-
9
DAT2
1
CD/DAT3
11
D0+
12
DO-
16
D1+
15
D1-
3
VSS1
6
VSS2
10
VSS3
13
VSS4
VSS517GND7
ALPS_SCDADA0101_NR
ALPS_SCDADA0101_NR
CONN@JSD1
CONN@
3
3
2
2
3
3
2
2
2
2
3
3
SD/MMCDAT0_D
SD/MMCDAT1_D
SD_UHS2_D0P_D
SD_UHS2_D0N_DSD_UHS2_D0N
SD_UHS2_D1P_D
SD_UHS2_D1N_DSD_UHS2_D1N
20
GND1
21
GND2
22
GND3
23
GND4
24
GND5
25
GND6
26
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A
B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C
D
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Card Reader OZ777FJ2
Card Reader OZ777FJ2
Card Reader OZ777FJ2
LA-9431P
LA-9431P
LA-9431P
30 59Friday, May 17, 2013
30 59Friday, May 17, 2013
30 59Friday, May 17, 2013
E
0.3
0.3
0.3
Page 31
5
JMINI2
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
@R216
@
12
R216
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
LCN_DAN08-52216-0100
LCN_DAN08-52216-0100
@R217
@
R217
WWAN_SM BCLK
WWAN_SM BDAT
PCIE_WAKE#<37>
MINI1CLK_REQ#<7>
R160 10K_0402_5%@ R160 10K_04 02_5%@
DDR_XDP_WAN_ SMBCLK<18,19,7,9>
DDR_XDP_WAN_ SMBDAT<18,19,7,9>
CLK_PCIE_MINI1#<7>
CLK_PCIE_MINI1<7>
1 2
C244 0.1U_0402_10V7K3@ C244 0.1U_0402_10V7K3@
C245 0.1U_0402_10V7K
C245 0.1U_0402_10V7K
3@
3@
mSATA_DEVSLP
D D
SATA_PRX_mSATATX_P3<6>
SATA_PRX_mSATATX_N3<6>
SATA_PTX_mSATARX_N3<6>
SATA_PTX_mSATARX_P3<6>
+3.3V_mSATA_WWAN
C C
PCIE_WAKE#
MINI1CLK_REQ#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
1 2
SATA_PTX_mSATARX_N3_C
1 2
SATA_PTX_mSATARX_P3_C
HW_GPS_DISABLE2#<36>
R218 0_0402_5%@R218 0_0402_5%@
R219 0_0402_5%@R219 0_0402_5%@
+3.3V_mSATA_WWAN
12
12
12
4
3
2
Mini WLAN/WIiGi/BT H=3.6Mini WWAN/GPS/LTE/mSATA H=3.6
+3.3V_mSATA_WWAN+3.3V_mSATA_WWAN +3.3V_WLAN +3.3V_WLAN
CONN@JMINI2
CONN@
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
GND2
+3.3V_mSATA_WWAN
0.047U_0402_16V4Z
0.047U_0402_16V4Z
3@ C248
3@
1
C248
2
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
MINI_CARD_RST#
WWAN_SM BCLK
WWAN_SM BDAT
LED_WWAN _OUT#
mSATA_DEVSLP
0.047U_0402_16V4Z
0.047U_0402_16V4Z
33P_0402_50V8J
33P_0402_50V8J
3@ C249
3@
3@ C250
3@
1
1
C249
C250
2
2
+SIM_PWR
WWAN_RA DIO_DIS# <36>
USBP6- <11>
USBP6+ <11>
mSATA_DEVSLP <12>
33P_0402_50V8J
33P_0402_50V8J
22U_0805_6.3V6M
22U_0805_6.3V6M
3@ C252
3@
3@ C251
3@
1
1
1
2
+
+
C252
C251
2
2
PCIE_WAKE#
MINI2CLK_REQ#<7>
CLK_PCIE_MINI2#<7>
CLK_PCIE_MINI2<7>
EC5048_TX<36,37>
MSCLK<37>
PCIE_PRX_WLANTX_ N4<11>
PCIE_PRX_WLANTX_ P4<11>
PCIE_PTX_WLANRX_ N4<11>
PCIE_PTX_WLANRX_ P4<11>
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
3@
3@
1
+
+
@
@
C254
C254
C253
C253
2
WLAN_RADIO_DIS#<36>
WIGIG60GHZ_DIS#<36>
BT_RADIO_DIS#<36>
CPPE#<12>
PCH_CL_CLK1<7>
PCH_CL_DATA1<7>
PCH_CL_RST1#<7>
C242 0.1U_0402_10V7KC 242 0.1U_0402_10V7K
1 2
PCIE_PTX_WLANRX_ N4_C
1 2
PCIE_PTX_WLANRX_ P4_C
C243 0.1U_0402_10V7KC 243 0.1U_0402_10V7K
1 2
R223 0_0402_5%@R 223 0_0402_5%@
BT_RADIO_DIS#_R
1 2
R215 0_0402_5%@ R215 0 _0402_5%@
D12
D12
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
1 2
R224 0_0402_5%@ R224 0 _0402_5%@
D13
D13
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
1 2
R225 0_0402_5%@ R225 0 _0402_5%@
D14
D14
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
21
21
21
JMINI1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
LCN_DAN08-52216-0100
LCN_DAN08-52216-0100
WLAN_RADIO_DIS#_R
WIGIG60GHZ_DIS#_R
BT_RADIO_DIS#_R
CONN@JMINI1
CONN@
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
2
4
6
8
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
PWR
Rail
+3.3V
+3.3Vaux
MSDATA
WLAN_RADIO_DIS#_R
MINI_CARD_RST#
WIGIG60GHZ_DIS#_R
WIMAX_LED#
WLAN_LED#
BT_LED#
1 2
R222 0_0402_5%@ R222 0_0402_5%@
WIMAX_LED# STUDY FOR DEBUG
Voltage
Tolerance
+-9%
+-9%
+3.3V_WLAN
1 2
C241 4700P_0402_25V7KC241 4700P_0402_25V7K
HOST_DEBUG_TX <37>
USBP2- <11>
USBP2+ <11>
CPUSB# < 12>
MSDATA <37>
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
@ C257
@
1
1
C257
2
2
Primary Power Aux Power
Peak Normal Normal
1000 750
330 250
5 (Not wake enable)
1
0.1U_0402_25V6
0.1U_0402_25V6
0.047U_0402_16V4Z
0.047U_0402_16V4Z
2
2
1
C260
C260
C259
C259
C258
C258
1
1
2
250 (Wake enable)
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
C261
C261
C262
C262
2
+3.3V_HDD
12
PJP22
3.3V_ALW for LID power
B B
+3.3V_ALW
LID_CL#<36,40>
+SIM_PWR
UIM_DATA
UIM_VPP
UIM_RESET
UIM_CLK
+COINCELL<40,41>
+3.3V_ALW
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
@
@
C50
A A
C50
2
ST change to 6718K-Y12N-01L & swap pin
5
CONN@
CONN@
14
GND2
13
GND1
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JSH1
JSH1
E-T_6718K-Y12N-01L
E-T_6718K-Y12N-01L
3.3V_HDD_EN<12>
AUX_EN_WOW L<36>
1 2
R51 100K_0402_5%R51 100K_0402_5%
PCH_PLTRST#_EC<25,29,36,37,9>
MPCIE_RST#<6,7>
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
4
1 2
R129 0_0402_5%@R129 0_0402_5%@
AUX_EN_WOW L
AUX_EN_WOW L
1 2
R131 0_0402_5%@R131 0_0402_5%@
+3.3V_RUN
C3380.1U_ 0402_25V6 @ C3380.1U_0402_25V 6 @
12
1
B
2
A
+5V_ALW
5
P
G
3
@
@
U30
U30
O
+3.3V_ALW
4
MINI_CARD_RST#
MINI_CARD_RST#
U3
U3
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
TPS22966DPUR_SON14_2X3~D
TPS22966DPUR_SON14_2X3~D
100K_0402_5%
100K_0402_5%
12
@
@
R26
R26
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VOUT1
VOUT1
GND
VOUT2
VOUT2
GPAD
3
14
13
+3.3V_HDD_U3
12
CT1
11
10
CT2
9
8
+3.3V_WLAN_U3
15
PJP22
PAD-OPEN1x1m
PAD-OPEN1x1m
1 2
C428 0.1U_0402_10V7K@C428 0.1U_0402_10V7K@
1 2
C429 470P_0402_50V7KC429 470P_0402_50V7K
1 2
C409 470P_0402_50V7KC409 470P_0402_50V7K
PJP23 PAD-OPEN1x1mP JP23 PAD-OPEN1x1m
1
@
@
C422
C422
0.1U_0402_10V7K
0.1U_0402_10V7K
2
12
+3.3V_WLAN
2
LED control circuit
+3.3V_WLAN
R227
R227
R229
R229
WIMAX_LED#
WLAN_LED#
BT_LED#
LED_WWAN _OUT#
1 2
R228
1 2
100K_0402_5%
100K_0402_5%
R228
1 2
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
R226
R226
1 2
100K_0402_5%
100K_0402_5%
5
Q22A
Q22A
SGD
SGD
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
2
G
G
Q22B
Q22B
61
S
D
S
D
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
2
Q30B
Q30B
G
G
61
S
D
S
D
+3.3V_mSATA_WWAN
5
Q30A
Q30A
34
SGD
SGD
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Mini Card/SIM Card
Mini Card/SIM Card
Mini Card/SIM Card
LA-9431P
LA-9431P
LA-9431P
34
WIRELESS_LED# <36,40>
31 59Friday, May 17, 2013
31 59Friday, May 17, 2013
31 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 32
5
D D
C C
4
3
2
1
+3.3V_SUS
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
B B
check port mapping
DOCKED
A A
function
Dock
1
M/B
0
4.7U_0603_6.3V6K
1
C420
C420
2
USB3TP3<11>
USB3TN3<11>
USB3RP3<11>
USB3RN3<11>
USBP5+<11 >
USBP5-<11>
DOCKED<21,27,28,36>
0.1U_0402_25V6
1
1
@
@
C419
C419
C418
C418
2
2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
@
@
C415
C415
2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
1
1
@
@
C417
C417
C414
C414
C416
C416
2
2
2
SA000064200
U33
U33
3
VDD
9
VDD
12
VDD
16
VDD
20
VDD
29
VDD
1
TX+
2
TX-
4
RX+
5
RX-
6
D+
7
D-
8
USB_ID
10
SS_SEL
32
HS_SEL
PI3USB3102ZLEX_TQFN32_6X3
PI3USB3102ZLEX_TQFN32_6X3
TX+A
TX-A
RX+A
RX-A
D+A
USB_IDA
TX+B
TX-B
RX+B
RX-B
D+B
USB_IDB
OE#
GND
GND
HGND
31
30
27
26
19
18
D-A
17
25
24
23
22
15
14
D-B
13
11
21
28
33
SW_USB3TP3 <33>
SW_USB3TN3 <33>
SW_USB3RP3 <33>
SW_USB3RN3 <33>
SW_USBP5+ <33>
SW_USBP5- <33>
DOCK_USB3TP3 <3 4>
DOCK_USB3TN3 <34>
DOCK_USB3RP3 <34>
DOCK_USB3RN3 <34>
DOCK_USBP5+ <34>
DOCK_USBP5- <34>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Mini Card PWR
Mini Card PWR
Mini Card PWR
LA-9431P
LA-9431P
LA-9431P
32 59Friday, May 17, 2013
32 59Friday, May 17, 2013
32 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 33
5
L37
EMC@L37
EMC@
EMC@L38
EMC@
34
34
SW_USB3RN3<32>
SW_USB3RP3<32>
D D
SW_USB3TN3<32>
SW_USB3TP3<32>
12
C282 0.1U_0402_10V7KC282 0.1U_0402_10V7K
C283 0.1U_0402_10V7KC283 0.1U_0402_10V7K
SW_USB3TN3_C
12
1 2
DLW21SN670HQ2L_4P
DLW21SN670HQ2L_4P
1 2
R235 0_0402_5%@ R235 0_04 02_5%@
1 2
R236 0_0402_5%@ R236 0_04 02_5%@
L38
1 2
DLW21SN670HQ2L_4P
DLW21SN670HQ2L_4P
1 2
R237 0_0402_5%@ R237 0_04 02_5%@
1 2
R239 0_0402_5%@ R239 0_04 02_5%@
4
USB3RN3_D-
USB3RP3_D+
USB3TN3_D-
USB3TP3_D+SW_USB3TP3_C
SW_USBP5+<32>
SW_USBP5-<32>
USB3RN3_D-
USB3RP3_D+
USB3TN3_D-
USB3TP3_D+
D15
D15
EMC@
EMC@
1
2
4
5
3
TVWDF1004AD0_DFN 9
TVWDF1004AD0_DFN 9
SW_USBP5+
SW_USBP5-
3
9
USB3RN3_D-
8
USB3RP3_D+
7
USB3TN3_D-
6
USB3TP3_D+
L39 EMC@
L39 EMC@
1
1
4
4
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
1 2
R238 0_0402_5%@R238 0_0402_5%@
1 2
R240 0_0402_5%@R240 0_0402_5%@
2
+USB_PWR
USBP5_D-
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
0.1U_0402_25V6
0.1U_0402_25V6
1
1
+
+
C280
C280
C281
C281
2
2
2
2
USBP5_D+
2
3
USBP5_D-
3
+5V_ALW
1
2
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C284
C284
2
USBP5_D+
USB3RN3_DÂUSB3RP3_D+
USB3TN3_D-
3
USB3TP3_D+
L30ESDL5V0C3-2_SOT23-3
L30ESDL5V0C3-2_SOT23-3
EMC@D16
EMC@
D16
1
ESATA_USB_PWR _EN#<36>
C285
C285
JUSB2
1
VBUS
2
D-
3
D+
4
GND
5
SSRX-
6
SSRX+
7
GND
8
SSTX-
9
SSTX+
SANTA_373070-1
SANTA_373070-1
U32
U32
1
GND
2
VIN
VIN3VOUT
4
EN
G547I2P81U_MSOP8
G547I2P81U_MSOP8
CONN@JUSB2
CONN@
GND
GND
GND
GND
VOUT
VOUT
10
11
12
13
+USB_PWR
8
7
6
5
FLG
1
USB_OC2# <11>
C C
1 2
R241 0_0402_5%@R241 0_0402_5%@
1
PWRSHARE_EN
2
PS_USBP0_D-SW_USBP0-
3
DP
4
9
1 2
SEL
R244 10K_0402_5%R244 10K_0402_5%
+3.3V_ALW
1
2
USB_PWR_SHR_V BUS_EN<36>
U39
USB_PWR_SHR_E N#<36>
U36
U36
VCC
S
D+
DÂOE#
GND
1
SW_USBP0+
1D+
2
SW_USBP0-
1D-
3
2D+
4
2D-
5
0.1U_0402_25V6
0.1U_0402_25V6
C322
C322
DOCKED_LIO_EN<36>
USBP0+<11 >
USBP0-<11>
10
9
8
7
6
NX3DV221GM_XQFN10U10_2X1P55
NX3DV221GM_XQFN10U10_2X1P55
1 2
R242 0_0402_5%@R242 0_0402_5%@
DOCK_USBP0+ <34>
DOCK_USBP0- <34>
SB#
SW_USBP0+ PS_USBP0_D+
+5V_ALW
0.1U_0402_25V6
0.1U_0402_25V6
1
2
8
7
6
5
C287
C287
U39
CEN
CB
DM
TDM
TDP
SMART-CDP
Vdd
Thermal-Pad
SLG55594AVTR_TDFN8_2X2
SLG55594AVTR_TDFN8_2X2
check port mapping
B B
A A
DOCKED_LIO_EN
1
0
function
Dock
M/B
USB3RN2_D-
L40
EMC@L40
EMC@
USB3RN2<11>
USB3RP2<1 1>
USB3TN2<11>
USB3TP2<11>
12
C292 0.1U_0402_10V7KC292 0.1U_0402_10V7K
12
C293 0.1U_0402_10V7KC293 0.1U_0402_10V7K
USB3TP2_C USB3TP2_D+
4
4
1
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
1 2
R246 0_0402_5%@ R246 0_04 02_5%@
1 2
R247 0_0402_5%@ R247 0_04 02_5%@
L41
EMC@L41
EMC@
4
4
1
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
1 2
R248 0_0402_5%@ R248 0_0402_5%@
1 2
R250 0_0402_5%@ R250 0_0402_5%@
3
3
2
2
3
3
2
2
USB3RN2_D-
USB3RP2_D+
USB3TN2_D-USB3TN2_C
USB3RP2_D+
USB3TN2_D-
USB3TP2_D+
PS_USBP0_D+ U SBP0_D+
PS_USBP0_D-
+5V_ALW
1 2
13
2
G
G
+5V_ALW
D17
D17
EMC@
EMC@
1
2
4
5
3
TVWDF1004AD0_DFN 9
TVWDF1004AD0_DFN 9
L42
EMC@ L42
EMC@
1 2
CMM0805-120Y-N_4P
CMM0805-120Y-N_4P
1 2
R249 0_0402_5%@R249 0_0402_5%@
1 2
R251 0_0402_5%@R251 0_0402_5%@
R243
R243
100K_0402_5%
100K_0402_5%
PWRSHARE_EN #
D
D
Q7
Q7
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
S
S
9
8
7
6
34
USB3RN2_D-
USB3RP2_D+
USB3TN2_D-
USB3TP2_D+
USBP0_D-
+5V_USB_CHG_PWR
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
1
+
+
C290
C290
2
+5V_ALW
JUSB1
CONN@JUSB1
CONN@
1
VBUS
USBP0_D-
2
L30ESDL5V0C3-2_SOT23-3
L30ESDL5V0C3-2_SOT23-3
EMC@D18
EMC@
D18
1
PWRSHARE_EN #
USBP0_D+
USB3RN2_DÂUSB3RP2_D+
USB3TN2_DÂUSB3TP2_D+
1
2
4
0.1U_0402_25V6
0.1U_0402_25V6
1
C291
C291
3
2
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C289
C289
1
C288
C288
2
2
2
3
4
5
6
7
8
9
SANTA_373070-1
SANTA_373070-1
U35
U35
G547I2P81U_MSOP8
G547I2P81U_MSOP8
GND
VOUT
VOUT
VIN
VIN3VOUT
EN
8
7
6
5
FLG
DÂD+
GND
SSRXÂSSRX+
GND
GND
GND
SSTX-
GND
SSTX+
GND
+5V_USB_CHG_PWR
USB_OC0# <11>
10
11
12
13
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB x2
USB x2
USB x2
LA-9431P
LA-9431P
LA-9431P
33 59Friday, May 17, 2013
33 59Friday, May 17, 2013
33 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 34
5
D D
C C
B B
DPC_LANE_P0<21>
DPC_LANE_N0<21>
DPC_LANE_P1<21>
DPC_LANE_N1<21>
DPC_LANE_P2<21>
DPC_LANE_N2<21>
DPC_LANE_P3<21>
DPC_LANE_N3<21>
DPC_DOCK_HPD
12
C302 0.1U_0402_10V7KC302 0.1U_0402_10V7K
12
C295 0.1U_0402_10V7KC295 0.1U_0402_10V7K
12
C297 0.1U_0402_10V7KC297 0.1U_0402_10V7K
12
C299 0.1U_0402_10V7KC299 0.1U_0402_10V7K
12
C304 0.1U_0402_10V7KC304 0.1U_0402_10V7K
12
C306 0.1U_0402_10V7KC306 0.1U_0402_10V7K
12
C300 0.1U_0402_10V7KC300 0.1U_0402_10V7K
12
C301 0.1U_0402_10V7KC301 0.1U_0402_10V7K
DPC_DOCK_HPD<21> DPB_DOCK_HPD <21>
Close to DOCK
Its for Enhance ESD on dock issue.
12
R268
R268
100K_0402_5%
100K_0402_5%
DPC_LANE_P0_C
DPC_LANE_N0_C
DPC_LANE_P1_C
DPC_LANE_N1_C
DPC_LANE_P2_C
DPC_LANE_N2_C
DPC_LANE_P3_C
DPC_LANE_N3_C
4
SLICE_BAT_PRES#
0.1U_0603_50V7K
0.1U_0603_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@
@
1
CE7
CE7
2
DOCK_DET_1
DPC_CA_DET
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_N0
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_N1
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_N2
DPC_DOCK_LANE_P3
DPC_DOCK_LANE_N3
DPC_DOCK_AUX
DPC_DOCK_AUX#
BLUE_DOCK
RED_DOCK
GREEN_DOCK
PESD24VS2UT_SOT23-3
PESD24VS2UT_SOT23-3
2
3
@
C317
C317
@
1
D20
D20
DOCK_LOM_SPD10LED_GRN#<2 8>
1 2
R259 33_0402_5%R259 33_0402_5%
1 2
R252 33_0402_5%R252 33_0402_5%
1 2
R253 33_0402_5%R253 33_0402_5%
1 2
R255 33_0402_5%R255 33_0402_5%
1 2
R257 33_0402_5%R257 33_0402_5%
1 2
R263 33_0402_5%R263 33_0402_5%
1 2
R265 33_0402_5%R265 33_0402_5%
1 2
R266 33_0402_5%R266 33_0402_5%
DPC_DOCK_AUX<24>
DPC_DOCK_AUX#<24>
0.033U_0402_16V7K
0.033U_0402_16V7K
1
@
@
C310
C310
2
+DOCK_PWR_BAR +DOCK_PWR_BAR
DPC_DOCK_HPD
+NBDOCK_DC_IN_SS
BLUE_DOCK<21>
RED_DOCK<21>
GREEN_DOCK< 21>
HSYNC_DOCK<21>
VSYNC_DOCK<21>
CLK_MSE<37>
DAT_MSE<37>
DAI_BCLK#<26>
DAI_LRCK#< 26>
DAI_DI<26>
DAI_DO#<26>
DAI_12MHZ#<26>
D_LAD0<36>
D_LAD1<36>
D_LAD2<36>
D_LAD3<36>
D_LFRAME#<36>
D_CLKRUN#<36>
D_SERIRQ<36>
D_DLDRQ1#<36>
CLK_PCI_DOCK<7>
DOCK_SMB_CLK<37>
DOCK_SMB_DAT<37>
DOCK_SMB_ALERT#<36,41,48>
DOCK_PSID<41>
DOCK_PWR_BTN#<37>
SLICE_BAT_PRES#<36,41,48> DOCK_DET# <36,48>
1
2
ESD depop location(EMC)
JDOCK1
JDOCK1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
71
71
73
73
75
75
77
77
79
79
81
81
83
83
85
85
87
87
89
89
91
91
93
93
95
95
97
97
99
99
101
101
103
103
105
105
107
107
109
109
111
111
113
113
115
115
117
117
119
119
121
121
123
123
125
125
127
127
129
129
131
131
133
133
135
135
137
137
139
139
141
141
143
143
145
GND1
146
PWR1
147
PWR1
151
Shield_G
152
Shield_G
153
Shield_G
154
Shield_G
155
Shield_G
156
Shield_G
JAE_WD2F144W B8-DT
JAE_WD2F144W B8-DT
3
CONN@
CONN@
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
GND2
PWR2
PWR2
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
Shield_G
WD2F144WB8
WD2F144WB8
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
148
149
150
157
158
159
160
161
162
DOCK_AC_OFF
DPB_CA_DET
DPB_DOCK_LANE_P0
DPB_DOCK_LANE_N0
DPB_DOCK_LANE_P1
DPB_DOCK_LANE_N1
DPB_DOCK_LANE_P2
DPB_DOCK_LANE_N2
DPB_DOCK_LANE_P3
DPB_DOCK_LANE_N3
DPB_DOCK_AUX
DPB_DOCK_AUX#
DPB_DOCK_HPD
SATA_PRX_DKTX_P0
SATA_PRX_DKTX_N0
SATA_PTX_DKRX_P0
SATA_PTX_DKRX_N0
DOCK_USBP0_D+
DOCK_USBP0_D-
DOCK_USBP5+ <32>
DOCK_USBP5- <32>
DOCK_USB3RN3 <32>
DOCK_DET_R#
0.1U_0603_50V7K
0.1U_0603_50V7K
C318
C318
1
2
DOCK_AC_OFF <48>
DOCK_LOM_SPD100LED_ORG# <28>
DPB_CA_DET <21,24>DPC_CA_DET<21,24>
1 2
R260 33_0402_5%R260 33_0402_5%
1 2
R261 33_0402_5%R261 33_0402_5%
1 2
R254 33_0402_5%R254 33_0402_5%
1 2
R256 33_0402_5%R256 33_0402_5%
1 2
R262 33_0402_5%R262 33_0402_5%
1 2
R264 33_0402_5%R264 33_0402_5%
1 2
R258 33_0402_5%R258 33_0402_5%
1 2
R267 33_0402_5%R267 33_0402_5%
DPB_DOCK_AUX <24>
DPB_DOCK_AUX# <24>
ACAV_DOCK_SRC# <48>
DAT_DDC2_DOCK <2 1>
CLK_DDC2_DOCK <21>
12
C312 .01U_0402_16V7KC312 .01U_0402_16V7K
12
C313 .01U_0402_16V7KC313 .01U_0402_16V7K
1 2
C314 .01U_0402_16V7KC314 .01U_0402_16V7K
1 2
C315 .01U_0402_16V7KC315 .01U_0402_16V7K
CLK_KBD <37>
DAT_KBD <37>
DOCK_USB3RP3 <32>
DOCK_USB3TN3 <32>
DOCK_USB3TP3 <3 2>
BREATH_LED# <36,40>
DOCK_LOM_ACTLED_YEL# <28>
DOCK_LOM_TRD0+ <28>
DOCK_LOM_TRD0- <28>
DOCK_LOM_TRD1+ <28>
DOCK_LOM_TRD1- <28>
+LOM_VCT
DOCK_LOM_TRD2+ <28>
DOCK_LOM_TRD2- <28>
DOCK_LOM_TRD3+ <28>
DOCK_LOM_TRD3- <28>
DOCK_DCIN_IS+ <47>
DOCK_DCIN_IS- <47>
DOCK_POR_RST# <37>
DAI_12MHZ# DAI_BCLK#
12
RE4
@RE4
@
10_0402_1%
10_0402_1%
1
CE8
@CE8
@
4.7P_0402_50V8C
4.7P_0402_50V8C
2
DPB_LANE_P0_C
DPB_LANE_N0_C
DPB_LANE_P1_C
DPB_LANE_N1_C
DPB_LANE_P2_C
DPB_LANE_N2_C
DPB_LANE_P3_C
DPB_LANE_N3_C
SATA_PRX_DKTX_P0_C <6>
SATA_PRX_DKTX_N0_C <6>
SATA_PTX_DKRX_P0_C <6>
SATA_PTX_DKRX_N0_C <6>
2
2
3
3
DLW21SN900SQ2L-0805_4P
DLW21SN900SQ2L-0805_4P
R269 0_0402_5%@R269 0_0402_5%@
R270 0_0402_5%@R270 0_0402_5%@
@L43
@
1
1
4
4
L43
12
12
EMI solution for E-Docking USB(EMC)
+LOM_VCT
1
@
@
C316
C316
1U_0402_6.3V6K
1U_0402_6.3V6K
2
D19
D19
21
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
12
RE5
@RE5
@
10_0402_1%
10_0402_1%
1
CE9
@CE9
@
4.7P_0402_50V8C
4.7P_0402_50V8C
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
12
C294 0.1U_0402_10V7KC294 0.1U_0402_10V7K
12
C296 0.1U_0402_10V7KC296 0.1U_0402_10V7K
12
C298 0.1U_0402_10V7KC298 0.1U_0402_10V7K
12
C303 0.1U_0402_10V7KC303 0.1U_0402_10V7K
12
C305 0.1U_0402_10V7KC305 0.1U_0402_10V7K
12
C307 0.1U_0402_10V7KC307 0.1U_0402_10V7K
12
C308 0.1U_0402_10V7KC308 0.1U_0402_10V7K
12
C309 0.1U_0402_10V7KC309 0.1U_0402_10V7K
1
2
DOCK_USBP0+ <33>
DOCK_USBP0- <33>
DOCK_DET#
1 2
R272 10K_0402_5%R272 10K_0402_5%
CLK_PCI_DOCK
12
R273
@R273
@
33_0402_5%
33_0402_5%
1
C319
@C319
@
12P_0402_50V8J
12P_0402_50V8J
2
1
DPB_LANE_P0 < 21>
DPB_LANE_N0 <21>
DPB_LANE_P1 < 21>
DPB_LANE_N1 <21>
DPB_LANE_P2 < 21>
DPB_LANE_N2 <21>
DPB_LANE_P3 < 21>
DPB_LANE_N3 <21>
0.033U_0402_16V7K
0.033U_0402_16V7K
ESD depop location(EMC)ESD depop location(EMC)
@
@
C311
C311
Close to DOCK
Its for Enhance ESD on dock issue.
DPB_DOCK_HPD
12
+3.3V_ALW
R271
R271
100K_0402_5%
100K_0402_5%
A A
EMI depop location(EMC)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
E series Dock Connector
E series Dock Connector
E series Dock Connector
LA-9431P
LA-9431P
LA-9431P
34 59Friday, May 17, 2013
34 59Friday, May 17, 2013
34 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 35
5
T94
T94
SW_LAN_TX1-< 28>
SW_LAN_TX1+<28>
D D
SW_LAN_TX0-< 28>
1
1
SW_LAN_TX0+<28>
C324
2
1
C C
2
C324
2
C323
C323
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
SW_LAN_TX3-< 28>
SW_LAN_TX3+<28>
1
C325
C325
2
0.47U_0603_10V7K
0.47U_0603_10V7K
SW_LAN_TX2-< 28>
C326
C326
SW_LAN_TX2+<28>
0.47U_0603_10V7K
0.47U_0603_10V7K
SW_LAN_TX1-
SW_LAN_TX1+
SW_LAN_TX0-
SW_LAN_TX0+
SW_LAN_TX3+
SW_LAN_TX2-
SW_LAN_TX2+
1
TD1+
2
TD1-
3
TDCT1
4
TDCT2
5
TD2+
6
TD2-
7
TD3+
8
TD3-
9
TDCT3
10
TDCT4
11
TD4+
12
TD4-
TAIMA_IH-115-F
TAIMA_IH-115-F
GND
GND
CHASSIS
CHASSIS
4
C327
EMC@C327
EMC@
1:1
1:1
1:1
1:1
1:1
1:1
1 2
1:1
1:1
TX1+
TX1-
TXCT1
TXCT2
TX2+
TX2-
TX3+
TX3-
TXCT3
TXCT4
TX4+
TX4-
150P_1808_2.5KV8J
150P_1808_2.5KV8J
24
NB_LAN_TX1-
23
NB_LAN_TX1+
22
Z2805
21
Z2807
20
NB_LAN_TX0-
19
NB_LAN_TX0+
18
NB_LAN_TX3-SW_LAN_TX3-
17
NB_LAN_TX3+
16
Z2806
15
Z2808
14
NB_LAN_TX2-
13
NB_LAN_TX2+
+GND_CHASSIS
use 40mil trace if necessary
3
RJ45 LOM circuit
LAN_ACTLED_YEL#<28>
NB_LAN_TX3-
NB_LAN_TX3+
NB_LAN_TX1-
NB_LAN_TX2-
NB_LAN_TX2+
NB_LAN_TX1+
NB_LAN_TX0-
NB_LAN_TX0+
12
12
12
12
R279 75_0402_1%R279 75_0402_1%
R277 75_0402_1%R277 75_0402_1%
R280 75_0402_1%R280 75_0402_1%
R278 75_0402_1%R278 75_0402_1%
LED_10_GRN#<28>
LED_100_ORG#<28>
R275 150_0402_5%R275 150_0402_5%
R276 150_0402_5%R276 150_0402_5%
470P_0402_50V7K
470P_0402_50V7K
1
2
1 2
150_0402_5%
150_0402_5%
1 2
1 2
C320
C320
R274
R274
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
C321
C321
2
LED_10_GRN_R#
LED_100_ORG_R#
+3.3V_LAN
LAN_ACTLED_YEL_R#
1
+3.3V_LAN:20mils
JLOM1
CONN@
JLOM1
CONN@
10
Yellow LED-
9
Yellow LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
11
Green LED-
13
Orange LED-
12
Green-Orange LED+
SANTA_130456-341
SANTA_130456-341
Symbol update OK
GND
GND
rev1
rev1
15
14
L55
EMC@L55
EMC@
USB3RN1<11>
USB3RP1<1 1>
B B
12
USB3TN1<11>
USB3TP1<11>
WIRELESS_ON#/OFF<36>
A A
C448 0.1U_0402_10V7KC448 0.1U_0402_10V7K
C449 0.1U_0402_10V7KC449 0.1U_0402_10V7K
USB3TN1_RP_C
12
USB3TP1_RP_C
CONN@
CONN@
JSF1
JSF1
1
1
2
2
3
3
4
4
GND1
GND2
ACES_50277-0040N-001
ACES_50277-0040N-001
4
4
1
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
1 2
R484 0_0402_5%@ R484 0_0402_5%@
1 2
R485 0_0402_5%@ R485 0_0402_5%@
L56
4
4
1
1
DLW21SN900HQ2L-0805_4P
DLW21SN900HQ2L-0805_4P
R486 0_0402_5%@ R486 0_04 02_5%@
R487 0_0402_5%@ R487 0_04 02_5%@
5
6
EMC@L56
EMC@
1 2
1 2
3
3
2
2
3
2
USB3RN1_D-
USB3RP1_D+ USB3RP1_D+ USB3RP1_D+
3
2
USB3TN1_D-
USB3TP1_D+
USB3RN1_D- USB3RN1_D-
USB3TN1_D- USB3TN 1_D-
USB3TP1_D+ USB3TP1_D+
USBP1+<11 >
USBP1-<11>
To Sniffer Board
5
4
D34
D34
EMC@
EMC@
1
2
4
5
3
TVWDF1004AD0_DFN 9
TVWDF1004AD0_DFN 9
1
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
9
8
7
6
L54 EMC@
L54 EMC@
1
4
DLW21HN900SQ2L_4P
DLW21HN900SQ2L_4P
1 2
R482 0_0402_5%@ R482 0_04 02_5%@
1 2
R483 0_0402_5%@ R483 0_04 02_5%@
2
3
2
3
USBP1_R_D+
USBP1_R_D-
+USB_SIDE_PWR
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
1
+
+
C444
C444
2
+5V_ALW
10U_0603_10V6M
10U_0603_10V6M
1
2
2
JUSB3 CONN@
JUSB3 CONN@
1
VBUS
0.1U_0402_25V6
0.1U_0402_25V6
1
C445
C445
2
3
2
1
0.1U_0402_25V6
0.1U_0402_25V6
1
C446
C446
C447
C447
2
USBP1_R_DÂUSBP1_R_D+
USB3RN1_DÂUSB3RP1_D+
L30ESDL5V0C3-2_SOT23-3
L30ESDL5V0C3-2_SOT23-3
EMC@D33
EMC@
USB3TN1_DÂUSB3TP1_D+
D33
ST change to PUBAUE-09FLBS1FF4H0
2
3
4
5
6
7
8
9
TAITW_PUBAUE-09FLBS 1FF4H0
TAITW_PUBAUE-09FLBS 1FF4H0
U52
U52
1
GND
VOUT
2
VOUT
VIN
VIN3VOUT
4
FLG
EN
G547I2P81U_MSOP8
G547I2P81U_MSOP8
DÂD+
GND
StdA-SSRXÂStdA-SSRX+
GND-DRAIN
StdA-SSTXÂStdA-SSTX+
+USB_SIDE_PWR
8
7
6
5
GND
GND
GND
GND
10
11
12
13
USB_OC1# <11>USB_SIDE_EN#<36>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
RJ45 and USBx1
RJ45 and USBx1
RJ45 and USBx1
LA-9431P
LA-9431P
LA-9431P
35 59Friday, May 17, 2013
35 59Friday, May 17, 2013
35 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 36
+3.3V_ALW
1 2
R281 10K_0402_5%R281 10K_0402_5%
1 2
R282 100K_0402_5%R282 100 K_0402_5%
1 2
R284 100K_0402_5%R284 100 K_0402_5%
1 2
R285 100K_0402_5%R285 100 K_0402_5%
D D
+3.3V_RUN
C C
B B
A A
1 2
R287 100K_0402_5%R287 100 K_0402_5%
1 2
R288 10K_0402_5%R288 10K_0402_5%
1 2
R289 100K_0402_5%R289 100 K_0402_5%
1 2
R291 100K_0402_5%R291 100 K_0402_5%
1 2
R292 100K_0402_5%R292 100 K_0402_5%
1 2
R293 100K_0402_5%R293 100 K_0402_5%
1 2
R295 100K_0402_5%R295 100 K_0402_5%
1 2
R298 100K_0402_5%R298 100 K_0402_5%
1 2
R304 10K_0402_5%@ R304 10K_04 02_5%@
1 2
R309 100K_0402_5%R309 100K_0402_5%
1 2
R310 10K_0402_5%R310 10K_0402_5%
1 2
R313 100K_0402_5%R313 100K_0402_5%
ME_FWP PCH has internal 20K PD.
(suspend power rail)
ME_FWP
5
ALS_INT#
HW_GPS_DISABLE2#
CPU_DETECT#
SLICE_BAT_PRES#
USB_PWR_SHR_E N#
USB_SIDE_EN#
WIGIG60GHZ_DIS#
USB_PWR_SHR_V BUS_EN
DOCK_SMB_ALERT#
WIRELESS_ON#/OFF
ESATA_USB_PWR _EN#
BT_RADIO_DIS#
SP_TPM_LPC_EN
LCD_TST
SYS_LED_MASK#
CHARGE_EN
12
R326
@R326
@
1K_0402_5%
1K_0402_5%
5
DOCKED_LIO_EN<33>
T97 PAD~D@ T97 PAD~ D@
PROCHOT_GATE<47>
DOCK_SMB_ALERT#<34,41,48>
T98 PAD~D@ T98 PAD~ D@
USB_SIDE_EN#<35>
EN_I2S_NB_CODEC#<26>
USH_PWR_STATE #<29>
EN_DOCK_PWR_BAR<4 8>
PANEL_BKEN_EC<22>
ENVDD_PCH<1 0,22>
LCD_TST<22>
PSID_DISABLE#<41>
PBAT_PRES#<41,48>
DOCKED<21,27,28,32>
DOCK_DET#<34,48>
AUD_NB_MUTE#<26>
MCARD_WW AN_PWREN<28>
LCD_VCC_TEST_EN<22>
AUD_HP_NB_SENSE<25,26>
ESATA_USB_PWR _EN#<33>
T106 PAD ~D@ T106 PAD~D@
SLICE_BAT_ON<48>
SLICE_BAT_PRES#<34,41,48>
T107 PAD ~D@ T107 PAD~D@
T110 PAD ~D@ T110 PAD~D@
WIGIG60GHZ_DIS#<31>
EC5048_TX<31,37>
mCARD_PCIE_SATA#<6>
CPU_DETECT#<9>
T115 PAD ~D@ T115 PAD~D@
BCM5882_ALERT#<29>
SUSACK#<12,9>
T118 PAD ~D@ T118 PAD~D@
SLP_ME_CSW_DE V#<12>
LAN_DISABLE#_R<28 >
SYS_LED_MASK#<40>
SIO_EXT_WAKE#<12,9>
WIRELESS_LED#<31,40>
USB_PWR_SHR_V BUS_EN<33>
WLAN_RADIO_DIS#<31>
WIRELESS_ON#/OFF<35> BC_CLK_ECE5048 <37>
BT_RADIO_DIS#<31>
WWAN_RA DIO_DIS#<31>
+3.3V_ALW
R317
R317
1 2
100K_0402_5%
100K_0402_5%
R320
100K_0402_5%
100K_0402_5%
@ R320
@
1 2
SYS_PWROK<9>
SIO_SLP_WLAN#<9>
PCH_DPWROK<9>
VGA_ID
Discrete
UMA 1
R319@ 0_0402_5%R319@ 0_0402_5%
VGA_ID0
T121 PAD~D@ T1 21 PAD~D@
4
MCARD_MISC_PW REN
PROCHOT_GATE
LID_CL_SIO#
DOCK_SMB_ALERT#
TOUCH_SCREEN_PD#
USB_SIDE_EN#
EN_I2S_NB_CODEC#
USH_PWR_STATE #
EN_DOCK_PWR_BAR
PANEL_BKEN_EC
ENVDD_PCH
LCD_TST
PSID_DISABLE#
PBAT_PRES#
DOCKED
DOCK_DET#
AUD_NB_MUTE#
MCARD_WW AN_PWREN
LCD_VCC_TEST_EN
CCD_OFF
AUD_HP_NB_SENSE
ESATA_USB_PWR _EN#
MODULE_ON
SLICE_BAT_ON
SLICE_BAT_PRES#
MODULE_BATT_PRES#
CHARGE_PBATT
WIGIG60GHZ_DIS#
mCARD_PCIE_SATA#
CPU_DETECT#
XFR_ID_BIT#
DP_HDMI_HPD
BCM5882_ALERT#
EDID_SELECT#
VGA_ID
SLP_ME_CSW_DE V#
LAN_DISABLE#_R
CHARGE_EN
SYS_LED_MASK#
ALS_INT#
WIRELESS_LED#
USB_PWR_SHR_V BUS_EN
WLAN_RADIO_DIS#
WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RA DIO_DIS#
SYS_PWROK
DGPU_SELECT#
CPU_VTT_ON
1 2
0
4
+3.3V_ALW +3.3V_ALW_U37
1
2
U37
U37
B52
GPIOA0
A49
GPIOA1
B53
GPIOA2
A50
GPIOA3
B54
GPIOA4
A51
GPIOA5
B55
GPIOA6
A52
GPIOA7
A33
GPIOB0
B36
GPIOB1
A34
GPOC2
B37
GPOC3
A35
GPOC4
B38
GPOC5
A36
GPOC6/TACH4
A37
GPIOC7
B40
GPIOD0
A38
GPIOC1
B41
GPIOC0
A39
GPIOB7
B42
GPIOB6
A40
GPIOB5
B43
GPIOB4
A41
GPIOB3
B44
GPIOB2
B32
GPIOD1
A31
GPIOD2
B33
GPIOD3
B15
GPIOD4
A15
GPIOD5
B16
GPIOD6
A16
GPIOD7
A1
GPIOE0/RXD
B2
GPIOE1/TXD
A2
GPIOE2/RTS#
B3
GPIOE3/DSR#
A3
GPIOE4/CTS#
B45
GPIOE5/DTR#
A42
GPIOE6/RI#
B4
GPIOE7/DCD#
A59
GPIOF0
B62
GPIOF1
A58
GPIOF2
B61
GPIOF3/TACH8
A56
GPIOF4/TACH7
B59
GPIOF5
A55
GPIOF6
B58
GPIOF7
B47
GPIOG0/TACH5
A45
GPIOG1
B48
GPIOG2
A46
GPIOG3
B49
GPIOG4
A47
GPIOG5
B50
GPIOG6
A48
GPIOG7/TACH6
B13
GPIOH0
A13
GPIOH1
A53
SYSOPT1/GPIOH2
B57
SYSOPT0/GPIOH3
B14
GPIOH4
A14
GPIOH5
B17
GPIOH6
B18
GPIOH7
PJP6
PJP6
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
C328
C328
10U_0603_6.3V6M
10U_0603_6.3V6M
B5
A17
B30
A43
A54
VCC1
VCC1
VCC1
VCC1
VCC1
ECE5048-LZY_DQFN132_11X11~D
ECE5048-LZY_DQFN132_11X11~D
3
GPIOI0
GPIOI1
GPIOI2/TACH0
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7
GPIOJ0
GPIOJ1/TACH1
GPIOJ2/TACH2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7
GPIOK0
GPIOK1/TACH3
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7
GPIOL0/PWM7
GPIOL1/PWM8
GPIOL2/PWM0
GPIOL3/PWM1
GPIOL4/PWM3
GPIOL5/PWM2
GPIOL6
GPIOL7/PWM5
GPIOM1
GPIOM3/PWM4
GPIOM4/PWM6
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ1#
SER_IRQ
14.318MHZ/GPIOM0
CLK32/GPIOM2
DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ
BC_INT#
BC_DAT
BC_CLK
PWRGD
OUT65
TEST_PIN
CAP_LDO
VSS
DB Version 0.4
DB Version 0.4
1
C329
C329
0.1U_0402_25V6
0.1U_0402_25V6
2
A23
B63
SIO_SLP_A#
A60
A61
B65
A62
B66
A63
B67
AUX_EN_WOW L
A64
A5
SIO_SLP_LAN#
B6
SIO_SLP_SUS#
A6
B7
MODC_EN
A7
DOCK_HP_DET
B8
DOCK_MIC_DET
A8
ME_FWP
B9
MASK_SATA_LED#
B10
USB_PWR_SHR_E N#
A10
LED_SATA_DIAG_OUT#
B11
A11
RUN_ON
B12
A12
B60
SUS_ON
A57
B64
BAT1_LED#
B68
A9
BAT2_LED#
B1
A18
A44
FP_POA_EN
B34
HW_GPS_DISABLE2#
B39
BREATH_LED#
B51
A27
LPC_LAD0
A26
LPC_LAD1
B26
LPC_LAD2
B25
LPC_LAD3
A21
LPC_LFRAME#
B22
PCH_PLTRST#_EC
A28
CLK_PCI_5048
B20
CLKRUN#
A22
LPC_LDRQ1#
B21
IRQ_SERIRQ
A32
B35
B29
D_LAD0
B28
D_LAD1
A25
D_LAD2
A24
D_LAD3
B23
D_LFRAME#
A19
D_CLKRUN#
B24
D_DLDRQ1#
A20
D_SERIRQ
A29
BC_INT#_ECE5048
B31
BC_DAT_ECE5048
A30
BC_CLK_ECE5048
A4
RUNPWROK
B56
SP_TPM_LPC_EN
B19
R321 1K_0402_5%R321 1K_0402_5%
B46
+CAP_LDO
B27
C1
EP
1 2
1
2
1
C330
C330
0.1U_0402_25V6
0.1U_0402_25V6
2
SIO_SLP_A# <39,44,9>
DOCK_AC_OFF_EC <48>
AUX_EN_WOW L <31>
WLAN_LAN_DISB# <28>
SIO_SLP_LAN# <28,9>
SIO_SLP_SUS# <9>
GPIO_PSID_SELECT <41>
DOCK_HP_DET <26>
DOCK_MIC_DET <26>
ME_FWP <6>
MASK_SATA_LED# <40>
USB_PWR_SHR_E N# <33>
LED_SATA_DIAG_OUT# <40 >
RUN_ON <26,37,39>
AC_DIS <41,48>CCD_OFF<22>
SPI_WP#_SEL <7>
SUS_ON <39,43>
HW_GPS_DISABLE2# <31>
LPC_LFRAME# <25,29,37,7>
RUNPWROK <37,9>
C336
C336
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
SIO_SLP_S4# <39,43,9>
SIO_SLP_S3# <39,43,9>
IMVP_PWRGD <46>
IMVP_VR_ON < 46>
T101PAD~D @T101PAD~D @
BAT1_LED# <40>
BAT2_LED# <40>
USH_PWR_ON <39>
T100PAD~D @T100PAD~D @
BREATH_LED# <34,40>
DIS_BAT_PROCHOT# <48>
LPC_LAD0 <25,29,37,7>
LPC_LAD1 <25,29,37,7>
LPC_LAD2 <25,29,37,7>
LPC_LAD3 <25,29,37,7>
PCH_PLTRST#_EC <25,29,31,37,9>
CLK_PCI_5048 <7>
CLKRUN# <10,29,37,9>
IRQ_SERIRQ <12,29,37>
EC_32KHZ_ECE5048 <37>
D_LAD0 <34>
D_LAD1 <34>
D_LAD2 <34>
D_LAD3 <34>
D_LFRAME# <3 4>
D_CLKRUN# <34>
D_DLDRQ1# <34>
D_SERIRQ <34>
BC_INT#_ECE5048 <37>
BC_DAT_ECE5048 <37>
SP_TPM_LPC_EN <29>
+CAP_LDO trace width 20 mils
2
1
C334
C334
0.1U_0402_10V7K
0.1U_0402_10V7K
2
trace width 20 mils
trace width 20 mils
1
2
CLK_PCI_5048
33_0402_5%
33_0402_5%
33P_0402_50V8J
33P_0402_50V8J
EMI depop location(EMC)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
C331
C331
0.1U_0402_25V6
0.1U_0402_25V6
12
R324
@R324
@
1
C339
@C339
@
2
1
1
C332
C332
0.1U_0402_25V6
0.1U_0402_25V6
2
+3.3V_ALW
18
27
36
45
+3.3V_RUN
12
12
12
12
12
12
12
LID_CL# <31,40>
LID_CL_SIO#
PROCHOT_GATE
XFR_ID_BIT#
WWAN_RA DIO_DIS#
SUS_ON
+3.3V_ALW
12
R322
R322
100K_0402_5%
100K_0402_5%
1
C337
C337
0.047U_0402_16V4Z
0.047U_0402_16V4Z
2
RP11
RP11
100K_0804_8P4R_5%
100K_0804_8P4R_5%
D_CLKRUN#
D_SERIRQ
D_DLDRQ1#
LPC_LDRQ1#
RUN_ON
CPU_VTT_ON
SLICE_BAT_ON
R325 10_0402_1%R325 10_0402_1%
R299 100K_0402_5%R299 100 K_0402_5%
R300 100K_0402_5%R300 100 K_0402_5%
R301 100K_0402_5%R301 100 K_0402_5%
R296 10K_0402_5%R296 10K_0402_5%
R303 100K_0402_5%R303 100 K_0402_5%
R305 100K_0402_5%R305 100 K_0402_5%
R307 100K_0402_5%R307 100 K_0402_5%
12
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SIO & GPIO ECE5048
SIO & GPIO ECE5048
SIO & GPIO ECE5048
LA-9431P
LA-9431P
LA-9431P
36 59Friday, May 17, 2013
36 59Friday, May 17, 2013
36 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 37
5
D D
+3.3V_ALW
1 2
PCIE_WAKE#
R340 10K_0402_ 5%R34 0 1 0K_0402_ 5%
1 2
BC_DAT_ECE5048
R343 100K_0402 _5%R343 100K_0402 _5%
1 2
BC_DAT_ECE1117
R344 100K_0402 _5%R344 100K_0402 _5%
1 2
PBAT_SMBDAT
R345 2.2K_0402 _5%R345 2 .2K_0402_ 5%
1 2
PBAT_SMBCLK
R339 2.2K_0402 _5%R339 2 .2K_0402_ 5%
1 2
CHARGER_SMBDAT
R348 10K_0402_ 5%R34 8 1 0K_0402_ 5%
1 2
CHARGER_SMBCLK
R350 10K_0402_ 5%R35 0 1 0K_0402_ 5%
+5V_RUN
1 2
R354 4.7K _0402_5%R354 4. 7K_0402_5 %
1 2
R355 4.7K _0402_5%R355 4. 7K_0402_5 %
1 2
R356 4.7K _0402_5%R356 4. 7K_0402_5 %
1 2
R357 4.7K _0402_5%R357 4. 7K_0402_5 %
+3.3V_RUN
1 2
R358 100K_ 0402_5%@ R358 100K_0 402_5%@
1 2
R360 100K_ 0402_5%@ R360 100K_0 402_5%@
1 2
R362 100K_ 0402_5%@ R362 100K_0 402_5%@
1 2
R408 10K_040 2_5%R408 10K_0402_ 5%
1 2
R376 10K_040 2_5%R376 10K_0402_ 5%
C C
1 2
R366 10K_040 2_5%R366 10K_0402_ 5%
1 2
R368 100K_04 02_5%R368 100K_ 0402_5%
1 2
R369 100K_04 02_5%R369 100K_ 0402_5%
1 2
R371 100K_04 02_5%R371 100K_ 0402_5%
1 2
R372 100K_04 02_5%R372 100K_ 0402_5%
1 2
R373 8.2K_040 2_5%@R3 73 8.2K_0402 _5%@
1 2
R377 10K_040 2_5%R377 10K_0402_ 5%
C455 0.1U_0402_25V6EMC@C455 0.1U_0402_25 V6EMC@
C456 0.1U_0402_25V6EMC@C456 0.1U_0402_25 V6EMC@
C457 0.1U_0402_25V6EMC@C457 0.1U_0402_25 V6EMC@
1 2
1 2
1 2
change to 10K by vendor feedback
DAT_KBD
CLK_MSE
DAT_MSE
VOL_MUTE
VOL_DOWN
VOL_UP
FAN1_PWM
FAN1_TACH
MSDATA
PCH_ALW_ON
DOCK_POR_RST#
EN_INVPWR
A_ON
RESET_OUT#
PCH_RSMRST#
VOL_UP_R
VOL_DOWN_R
VOL_MUTE_R
+RTC_CELL
1 2
R332 0_0402_5%@R 332 0_0402_5%@
10U_0603_6.3V6M
10U_0603_6.3V6M
PAD-OPEN1x1m
PAD-OPEN1x1m
C348
C348
PJP7
PJP7
1 2
R490 0_0402_5%@R 490 0_0402_5%@
1 2
R336 0 _0402_5%@R336 0_0402_5%@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
1
2
+3.3V_ALW_U38
+3.3V_ALW_U38
+3.3V_ALW +3.3V_ALW _U38
1
2
@
@
ESD Request XB use SA00005IH1L(S IC MEC5075-LZY-SAL00 DQFN 132P EC)
32 KHz Clock
1 2
22P_0402_50V8J
+3.3V_ALW
100K_0402_5%
100K_0402_5%
R380
R380
+3.3V_ALW
12
JTAG_TDI
JTAG_CLK
MSCLK
HOST_DEBUG_TX
49.9_0402_1%
49.9_0402_1%
R388
R388
12
JTAG_RST#
1U_0402_6.3V6K
1U_0402_6.3V6K
100_0402_1%
100_0402_1%
12
1
@
@
R384
R384
C362
C362
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
12
R385
R385
R391
R391
JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO
1 2
R400 0_0402_5%@R 400 0_0402_5%@
5
B B
1
JTAG1
@SHORT PADS~D
@SHORT PADS~D
1
CONN@JTAG1
CONN@
2
2
+3.3V_ALW
RP1
RP1
1 8
2 7
3 6
4 5
10K_8P4R_5 %
10K_8P4R_5 %
H=0.98
A A
CONN@
CONN@
JDEG1
JDEG1
12
GND2
11
GND1
10
10
9
9
8
8
7
7
6
6
5
MSCLK
5
4
MSDATA
4
3
3
2
2
1
1
ACES_50521-01 041-P01
ACES_50521-01 041-P01
pin define different with original part
22P_0402_50V8J
32.768KHZ_12 .5PF_Q13FC1 350000~D
32.768KHZ_12 .5PF_Q13FC1 350000~D
1
C364
C364
2
10_0402_1%
10_0402_1%
12
@R382
@
R382
Place close pin A29
EMI depop location(EMC)
+3.3V_ALW
100K_0402_5%
100K_0402_5%
10K_0402_5%
10K_0402_5%
12
12
@R398
@
R398
R397
R397
HOST_DEBUG_TXHOST_DEB_TX
Pin8 5075_TXD for EC Debug
pin9 5048_TXD for SBIOS debug
MEC_XTAL2MEC_ XTAL1
Y4
Y4
CLK_PCI_MEC
4.7P_0402_50V8C
4.7P_0402_50V8C
1
@C363
@
C363
2
5048_TX should be change Host_debug_tx
EC5048_TX <31,36>
4
+RTC_CELL_VBAT
0.1U_0402_25V6
0.1U_0402_25V6
1
C345
C345
2
+3.3V_VTR
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_25V6
0.1U_0402_25V6
1
1
C346
C346
C352
C352
2
2
+3.3V_VTR_ADC
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_25V6
0.1U_0402_25V6
1
1
C353
C353
C347
C347
2
2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
C355
C355
2
EC_32KHZ_ECE50 48<36>
DOCK_POR_RST#
0.1U_0402_25V6
0.1U_0402_25V6
C357
C357
1
2
0.1U_0402_25V6
1
1
C356
C356
2
2
1
1
C354
C354
C350
C350
C349
C349
2
2
22P_0402_50V8J
22P_0402_50V8J
1
C365
C365
2
Place close pin A21
R392 C368
240K 4700p
130K 4700p
62K
33K
8.2K
4.3K
2K
1K
*
BOARD_ID rise time is measured from 5%~68%.
4
C351
C351
SML1_SMBDATA<7>
SML1_SMBCLK<7>
CLK_TP_SIO<38>
DAT_TP_SIO<38>
CLK_KBD<34>
DAT_KBD<34>
CLK_MSE<34>
DAT_MSE<34>
PBAT_SMBDAT<41>
PBAT_SMBCLK<41>
DOCK_POR_RST#<34>
EC_WAKE#<12>
A_ON<39,44>
PCH_ALW_ON<39>
BIA_PWM_EC<22>
BC_CLK_ECE50 48<36>
BC_DAT_ECE5048<36>
BC_INT#_ECE5048<36>
ACAV_IN_NB<47, 48>
SIO_SLP_S5#<9>
BEEP<26>
BC_CLK_ECE11 17<38>
BC_DAT_ECE1117<38>
BC_INT#_ECE1117<38>
SIO_EXT_SMI#<12 >
SIO_RCIN#<12>
IRQ_SERIRQ<12,29,36>
PCH_PLTRST#_EC<25,29 ,31,36,9>
CLK_PCI_MEC<7>
LPC_LFRAME#<25,29,36 ,7>
LPC_LAD0<25,2 9,36,7>
LPC_LAD1<25,2 9,36,7>
LPC_LAD2<25,2 9,36,7>
LPC_LAD3<25,2 9,36,7>
CLKRUN#<10,29,36 ,9>
SIO_EXT_SCI#<12>
MEC_XTAL2 MEC_XTAL2_ R
4700p
4700p
4700p
4700p
4700p
4700p
12
1 2
R378 0_0402_5 %@R378 0_04 02_5%@
R379 0_0402_5 %@R379 0_04 02_5%@
REV
X00
X01
***
X02
***
***
***
A00
SML1_SMBDATA
SML1_SMBCLK
CLK_TP_SIO
DAT_TP_SIO
CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE
PBAT_SMBDAT
PBAT_SMBCLK
JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#
FAN1_TACH
A_ON
PCH_ALW_ON
BIA_PWM_EC
FAN1_PWM
BC_CLK_ECE50 48
BC_DAT_ECE5048
BC_INT#_ECE5048
ACAV_IN_NB
SIO_SLP_S5#
BEEP
BC_CLK_ECE11 17
BC_DAT_ECE1117
BC_INT#_ECE1117
SIO_EXT_SMI#
SIO_RCIN#
IRQ_SERIRQ
PCH_PLTRST#_EC
CLK_PCI_MEC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#
MEC_XTAL1
BOARD_ID
RUN_ON<26,36, 39>
+3.3V_ALW
12
B64
A22
A58
A11
A26
B35
A41
A52
A37
B40
A38
B41
A39
B42
B59
A56
A51
B55
B56
A53
A57
B22
A21
B23
B24
A23
B25
A24
A43
B45
A42
B20
A18
B19
A20
B21
A19
A27
A28
B30
A29
B31
A30
B32
A31
B33
A32
A33
A61
A62
B62
1K_0402_5%
1K_0402_5%
1
2
3
U38
U38
VBAT
H_VTR
VTR_ADC
B3
VTR
VTR
VTR
VTR
VTR
VTR
A5
GPIO007/I2C1D _DATA/PS2_CLK0B/I2 C3A_DATA/GANG_BUSY
B6
GPIO010/I2C1D _CLK/PS2_DAT0B/I2 C3A_CLK/GANG_ERROR
GPIO110/PS2_ CLK2/GPTP-IN6
GPIO111/PS2_ DAT2/GPTP-OUT6
GPIO112/PS2_ CLK1A
GPIO113/PS2_ DAT1A
GPIO114/PS2_ CLK0A
GPIO115/PS2_ DAT0A
GPIO154/I2C1C _DATA/PS2_CLK1B
GPIO155/I2C1C _CLK/PS2_DAT1B
GPIO145/I2C1K _DATA/JTAG_TDI
GPIO146/I2C1K _CLK/JTAG_TDO
GPIO147/I2C1J _DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J _CLK/I2C2C_ CLK/JTAG_TMS
JTAG_RST#
GPIO050/FAN_TACH1/GTACH
GPIO051/FAN_TACH2
GPIO052/FAN_TACH3
GPIO053/PW M0
GPIO054/PW M1
GPIO055/PW M2
GPIO056/PW M3/GPWM
GPIO123/BCM_A_CL K
GPIO122/BCM_A_DAT
GPIO121/BCM_A_INT#
GPIO032/BCM_E_ CLK
GPIO031/GPTP-OUT2/BCM_E _DAT
GPIO030/GPTP-IN2/BCM_ E_INT#
GPIO047/LSBCM_ D_CLK
GPIO046/LSBCM_ D_DAT
GPIO045/LSBCM_ D_INT#
A6
GPIO011/nSMI/GANG_DATA0
GPIO061/LPCPD#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/NEC_SCI
XTAL1
XTAL2
GPIO160/32KHZ_ OUT
AGND
VSS
VSS_ADC
VR_CAP
B66
B11
B60
+3.3V_ALW
2
12
61
G
G
SYSTEM_ID
B12
+VR_CAP
1
2
100K_0402_5%
100K_0402_5%
RUNPWROK
R36
R36
RUN_ON#
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Q5B
Q5B
D
D
S
S
+3.3V_ALW
1K_0402_5%
1K_0402_5%
12
R386
R386
4700P_0402_25V7K
4700P_0402_25V7K
1
2
15mil
driven low when +3.3V_RUN is OFF;
driven high when +3.3V_RUN is ON
R392
R392
4700P_0402_25V7K
4700P_0402_25V7K
C368
C368
CHIPSET_ID for BID function
3
+RTC_CELL
100K_0402_5%
100K_0402_5%
12
R327
R327
POWER_SW _IN#
B54
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C366
C366
1 2
R329 10K_04 02_5%R329 10K_ 0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C343
C343
2
GPIO014/GPTP-IN7/RC_ ID3
GPIO124/GPTP-OUT5/UART_RX
GPIO060/KBRST/BCM _B_INT#
GPIO101/ECGP_S CLK/GANG_DATA5
GPIO103/ECGP_MI SO/GANG_DATA7
GPIO102/BCM_C_ INT#/GANG_DATA6
GPIO116/MSDATA/V2P_COUT_LO/TAP_SE L_STRAP
GPIO117/MSCLK/ V2P_COUT_HI
GPIO015/GPTP-OUT7/GANG_DATA3
GPIO016/GPTP-IN8/GANG_DATA4
GPIO107/NRESET_OUT
GPIO003/I2C1A_D ATA/GANG_MODE
GPIO004/I2C1A_C LK/GANG_START
GPIO005/I2C1B _DATA/BCM_B_DAT/GANG_STROBE
GPIO006/I2C1B _CLK/BCM_B_CL K/GANG_FULL
GPIO012/I2C1H_D ATA/I2C2D_DATA/GANG_DATA1
GPIO013/I2C1H_C LK/I2C2D_CLK /GANG_DATA2
GPIO130/I2C2A_D ATA/BCM_C_DAT
GPIO131/I2C2A_C LK/BCM_C_CLK
GPIO141/I2C1F _DATA/I2C2B_DATA
GPIO142/I2C1F _CLK/I2C2B_ CLK
GPIO002/THERMTRIP3#
GPIO024/THSEL_STRAP
PROCHOT_IN#/PROCHOT_IO#
VSS_RO
H_VSS
EP
MEC5075-LZY_ DQFN132_11X1 1~D
MEC5075-LZY_ DQFN132_11X1 1~D
C1
B18
ESR <2ohms
+3.3V_RUN
10K_0402_5%
10K_0402_5%
12
R35
R35
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
34
D
D
G
G
5
Q5A
Q5A
S
S
C369
C369
FWP#
@C340
@
1 2
1U_0402_6.3 V6K
1U_0402_6.3 V6K
GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO025/UART_CLK
GPIO120/UART_TX
VCC_PWRGD
GPIO105/ECGP_MOS I
GPIO104
GPIO106
GPIO127/A20M
NFWP
GPIO156/LED0
GPIO157/LED1
GPIO153/LED2
GPIO027/GPTP-OUT1
GPIO026/GPTP-IN1
GPIO001/ECSPI_ CS1
GPIO017/GPTP-OUT8
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4
GPIO132/I2C1G _DATA
GPIO140/I2C1G _CLK
GPIO143/I2C1E _DATA
GPIO144/I2C1E _CLK
SYSPWR_PRES
VCI_OVRD_IN
VCI_OUT
VCI_IN0#
VCI_IN1#
VCI_IN2#
VCI_IN3#
VREF_PECI
PECI_DAT
DN1-THERM
DP1-VREF_T
THERMTRIP2#
V_ISYS
+3.3V_ALW
10K_0402_5%
10K_0402_5%
12
R393
R393
10K_0402_5%
10K_0402_5%
@R399
@
R399
1 2
2
+RTC_CELL
100K_0402_5%
100K_0402_5%
12
R328
DOCK_PWR_SW #
VOL_UP <40>
PCIE_WAKE# <31>
VOL_DOWN <40>
1.05V_A_PWRGD <44 >
VOL_MUTE <40>
100K_0402_5%
100K_0402_5%
12
R370
R370
PECI_EC <9>
R328
1 2
R330 10K_040 2_5%R330 10K_04 02_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C344
C344
2
1 2
R367 1K_0402_5%R367 1K_0402_ 5%
C340
POWER_SW #_MB <40,9> DOCK_PWR_BTN# <34>
A10
SYSTEM_ID
B10
BOARD_ID
DN2
DP2
DN3
DP3
DN4
DP4
VIN
VSET
VCP
B8
B27
B44
B46
B26
A25
B36
PCH_SATA_MOD_EN#
B37
B38
A34
DDR_HVREF_RST_GATE
A35
A36
A40
B43
A45
B65
B57
B1
A55
A1
ALW_PWRGD_ 3V_5V
B28
B2
A8
B9
A9
B39
A44
B47
A54
B58
A3
B4
A4
LCD_SMBDAT
B5
LCD_SMBCLK
B7
BAY_SMBDAT
A7
BAY_SMBCLK
B48
GPU_SMBDAT
B49
GPU_SMBCLK
A47
B50
B52
CARD_SMBDAT
A49
CARD_SMBCLK
B53
A50
A59
A64
A60
B67
A63
B63
B68
B51
A48
B13
REM_DIODE1_N
A13
REM_DIODE1_P
B14
REM_DIODE2_N
A14
REM_DIODE2_P
A15
B16
A16
REM_DIODE4_N
B17
REM_DIODE4_P
B15
A17
A12
B34
A2
B29
A46
B61
R381 4.7K_040 2_5%R381 4.7K_0402 _5%
VOL_UP_R
LAN_WAKE#
HOST_DEBUG_TX
HOST_DEBUG_RX
RUNPWROK
EN_INVPWR
PCIE_WAKE#
MSDATA
MSCLK
FWP#
VOL_DOWN_R
DEVICE_DET#
PS_ID
1.05V_A_PWRGDCLK_KBD
VOL_MUTE_R
1.35V_SUS_PWR GD
PM_APWROK
RESET_OUT#
PCH_PCIE_WAKE#
PCH_RSMRST#
AC_PRESENT
SIO_PWRBTN#
DOCK_SMB_DAT
DOCK_SMB_CLK
CHARGER_SMBDAT
CHARGER_SMBCLK
USH_SMBDAT
USH_SMBCLK
ACAV_IN
ALWON
POWER_SW _IN#
DOCK_PWR_SW #
VCI_IN2#
POA_WAKE#
+PECI_VREF
PECI_EC_RPE CI_EC_R
VSET_5075
THERMATRIP2#
THERMATRIP3#
THSEL_STRAP
PROCHOT#_EC
1 2
1 2
R338 10K_0402_5 %R33 8 10 K_0402_5%
LAN_WAKE# <12,28>
HOST_DEBUG_TX <31>
RUNPWROK <36,9>
EN_INVPWR <22>
@
T123PAD~D@T123PAD~D
SLICE_PERF_E N <48>
DYN_TUR_CURRNT_SET# <47>
SIO_SLP_S0# <9>
MSDATA <31>
MSCLK <31>
1 2
R349 10K_0402_5 %R34 9 10 K_0402_5%
PS_ID <41>
ALW_PWRGD_ 3V_5V <42>
1 2
R352 10K_0402_ 5%R35 2 1 0K_0402_ 5%
ME_SUS_PWR_ACK <9>
1.35V_SUS_PWR GD <43>
PM_APWROK <9>
RESET_OUT# <15,9>
PCH_PCIE_WAKE# <9 >
PCH_RSMRST# <38>
AC_PRESENT <12,9>
SIO_PWRBTN# <9>
DOCK_SMB_DAT <34>
DOCK_SMB_CLK <34>
CHARGER_SMBDAT <47>
CHARGER_SMBCLK <47 >
USH_SMBDAT <29>
USH_SMBCLK <29>
ACAV_IN <47,48>
ALWON <42>
1 2
R375 43_0402_5%R375 43_0402_5 %
1 2
C358 2200P_0402_50V7KC358 2 200P_0402 _50V7K
1 2
C359 2200P_0402_50V7KC359 2 200P_0402 _50V7K
1 2
C361 2200P_0402_50V7KC361 2 200P_0402 _50V7K
C283, C285, C286, C287 Place near U51
VCP <47>
V_SYS <47>
C342
@C342
@
1 2
1U_0402_6.3 V6K
1U_0402_6.3 V6K
PROCHOT#_EC
+3.3V_ALW2
R866 close to U51 at least 250mils
1 2
R374 0_0402_5%@R 374 0_0402_5%@
0.1U_0402_25V6
0.1U_0402_25V6
1
C360
C360
2
5075 Setting for Thermal Design
Align E5,P5 Fan module pin define
CONN@
CONN@
JFAN1
JFAN1
then swap pin define
6
Thermal diode mapping
Location
5075 Channel
DP1/DN1
CPU
DP2/DN2
DIMM
V.R
DP4/DN4
Place under CPU
Place C266 close to the Q11 as possible
100P_0402_50V8J
100P_0402_50V8J
@C370
@
C370
2
C
C
1
E
E
3 1
DP2/DN2 for SODIMM on Q13, place Q13 close
to SODIMM and C372 close to Q13
100P_0402_50V8J
100P_0402_50V8J
@C372
@
1
C
C
C372
2
E
E
3 1
DP4/DN4 for Skin on Q14, place Q14 close to Vcore VR choke.
100P_0402_50V8J
100P_0402_50V8J
@C373
@
C
C
C373
2
E
E
3 1
1
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Q11
Q11
B
B
MMBT3904WT1G_ SC70-3~D
MMBT3904WT1G_ SC70-3~D
2
Q13
Q13
B
B
MMBT3904WT1G_ SC70-3~D
MMBT3904WT1G_ SC70-3~D
2
Q14
Q14
B
B
MMBT3904WT1G_ SC70-3~D
MMBT3904WT1G_ SC70-3~D
2
REM_DIODE1_P
REM_DIODE1_N
REM_DIODE2_P
REM_DIODE2_N
REM_DIODE4_P
REM_DIODE4_N
GND2
5
GND1
4
4
3
3
2
2
1
1
ACES_50277-00 40N-001
ACES_50277-00 40N-001
Rest=1.58K , Tp=96 degree
FAN1_PWM
FAN1_TACH
22U_0805_6.3V6MC722U_0805_6.3V6M
C7
+1.05V_RUN
R403 2.2K_0402_5%R4 03 2 .2K_0402_ 5%
H_THERMTRIP#<12 >
0.1U_0402_25V6
0.1U_0402_25V6
1.58K_0402_1%
1.58K_0402_1%
12
1
C367
C367
2
1
2
R394
R394
1
+1.05V_RUN
10K_0402_5%
RB751V40_SC76-2
RB751V40_SC76-2
@
@
D1
D1
1 2
VSET_5075
10K_0402_5%
@R335
@
12
R335
100K_0402_5%
100K_0402_5%
@R342
@
R342
1 2
2 1
1 2
R334 0_0402_5%@R 334 0_0402_5%@
13
D
D
2
Q9
@
Q9
@
G
G
L2N7002WT1G_ SC-70-3
L2N7002WT1G_ SC-70-3
S
S
POA_WAKE#
VCI_IN2#
DOCK_SMB_DAT
DOCK_SMB_CLK
DYN_TUR_CURRNT_SET#
LCD_SMBDAT
LCD_SMBCLK
BAY_SMBDAT
BAY_SMBCLK
DDR_HVREF_RST_GATE
THERMATRIP3#
DEVICE_DET#
HOST_DEBUG_RX
CARD_SMBDAT
GPU_SMBDAT
GPU_SMBCLK
CARD_SMBCLK
+1.05V_RUN
+5V_RUN
+3.3V_ALW
8.2K_0402_5%
8.2K_0402_5%
R402
R402
12
THERMATRIP2#
C
C
2
Q12
Q12
B
B
MMST3904-7-F_SO T323-3
MMST3904-7-F_SO T323-3
E
E
3 1
THSEL_STRAP
R383 1K_0402_5 %R383 1K_04 02_5%
1: Channel 1 will provide Thermistor Readings
0: Channel 1 will provide Diode Readings
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Re v
Size Document Number Re v
Size Document Number Re v
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
H_PROCHOT# <46,47,4 8,9>
12
R346100K _0402_5% R34 6100K_04 02_5%
12
R347100K _0402_5% R34 7100K_04 02_5%
12
R3592.2K_ 0402_5% R3592. 2K_0402_5 %
12
R3612.2K_ 0402_5% R3612. 2K_0402_5 %
12
R363100K _0402_5% R36 3100K_04 02_5%
12
R4512.2K_ 0402_5% R4512. 2K_0402_5 %
12
R3872.2K_ 0402_5% R3872. 2K_0402_5 %
12
R4532.2K_ 0402_5% R4532. 2K_0402_5 %
12
R4522.2K_ 0402_5% R4522. 2K_0402_5 %
12
R353100K _0402_5% R35 3100K_04 02_5%
12
R364100K _0402_5% R36 4100K_04 02_5%
12
R365100K _0402_5% R36 5100K_04 02_5%
12
R40110K_0402_ 5% R40110 K_0402_5%
RP3
RP3
18
27
36
45
2.2K_0804_ 8P4R_5%
2.2K_0804_ 8P4R_5%
0.1U_0402_25V6
0.1U_0402_25V6
C371
C371
1
2
1 2
KBC & SIO MEC5075
KBC & SIO MEC5075
KBC & SIO MEC5075
LA-9431P
LA-9431P
LA-9431P
+RTC_CELL
+3.3V_ALW
37 59Friday, May 17 , 2013
37 59Friday, May 17 , 2013
37 59Friday, May 17 , 2013
0.3
0.3
0.3
Page 38
5
4
3
2
1
+3.3V_TP
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
R404
R404
12
D D
I2C1_SDA_TCH_PAD<1 2>
I2C1_SCL_TCH_PAD<12>
DAT_TP_SIO<3 7>
CLK_TP_SIO<37>
1 2
R450 0_0402_5%@ R450 0_0402_5%@
1 2
R449 0_0402_5%@ R449 0_0402_5%@
1 2
R441 0_0402_5%@ R441 0_0402_5%@
1 2
R444 0_0402_5%@ R444 0_0402_5%@
10P_0402_50V8J
10P_0402_50V8J
@
@
C377
C377
1
2
Touch Pad
R405
R405
12
10P_0402_50V8J
10P_0402_50V8J
1
@
@
C378
C378
2
KB_DET#<12,9>
TP_DATA
10P_0402_50V8J
10P_0402_50V8J
1
@
@
C379
C379
2
TP_CLK
10P_0402_50V8J
10P_0402_50V8J
1
@
@
C380
C380
2
+5V_RUN
+3.3V_ALW
BC_INT#_ECE1117<37>
BC_DAT_ECE1117<37>
BC_CLK_ECE1117<37>
+3.3V_TP
KB_DET#
TP_DATA
TP_CLK
EMI depop location(EMC) EMI depop location(EMC)
CONN@
CONN@
JKBTP1
JKBTP1
18
GND2
17
GND1
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E-T_6718K-Y16N-01L
E-T_6718K-Y16N-01L
+3.3V_TP
1
2
Place close to JKBTP1
C374
@C374
@
0.1U_0402_25V6
0.1U_0402_25V6
1
C375
@C375
@
0.1U_0402_25V6
0.1U_0402_25V6
2
+5V_RUN+3.3V_ALW
1
C376
@C376
@
0.1U_0402_25V6
0.1U_0402_25V6
2
ST change to 6718K-Y16N-01L
+3.3V_RUN +3.3V_TP
PJP8
PJP8
C C
B B
@R414
RSMRST circuit
+5V_ALW
12
R411
R411
33_0402_5%
33_0402_5%
+5V_ALW_U41
.01U_0402_16V7K
.01U_0402_16V7K
1
C387
C387
2
A A
U41
U41
1
VCC
RESET#
2
GND
RT9818A-44GU3_SC70-3~D
RT9818A-44GU3_SC70-3~D
change to E4 solution
3
RSMRST#
+3.3V_ALW
10K_0402_5%
10K_0402_5%
12
R440
R440
EC SIDE
PCH_RSMRST#<37>
0_0402_5%
0_0402_5%
+3.3V_ALW
1
B
2
A
@
1 2
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
R414
C386
@C386
@
1 2
0.1U_0402_25V6
0.1U_0402_25V6
5
U42
U42
P
4
O
R413 0_0402_5%@ R413 0_04 02_5%@
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
1 2
PCH_RSMRST#_Q <9>
eDP Cable (30P Normal)@
eDP Cable (30P Normal)@
Part Number Description
Part Number Description
DC02001PB00 H-CONN SET 0VM MB-EDP-LED-CAM
DC02001PB00 H-CONN SET 0VM MB-EDP-LED-CAM
eDP Cable (40P Touch Screen)@
eDP Cable (40P Touch Screen)@
Part Number Description
Part Number Description
DC02001PA00 H-CONN SET 0VM MB-EDP-LED-CAM-TS
DC02001PA00 H-CONN SET 0VM MB-EDP-LED-CAM-TS
Sniffer cable@
Sniffer cable@
Part Number Description
Part Number Description
DC02001P900
DC02001P900
H-CONN SET 0VM MB-SNIFFER
H-CONN SET 0VM MB-SNIFFER
TP_FFC@
TP_FFC@
Part Number Description
Part Number Description
NBX0001CV00
NBX0001CV00
FP FFC@
FP FFC@
Part Number
Part Number
NBX0001CX00 FFC 6P G P0.5 PAD=0.3 86.4MM USH/B-FP
NBX0001CX00 FFC 6P G P0.5 PAD=0.3 86.4MM USH/B-FP
USH FFC@
USH FFC@
Part Number
Part Number
NBX0001CT00 FFC 20P G P0.5 PAD=0.3 33.5MM MB-USH/B
NBX0001CT00 FFC 20P G P0.5 PAD=0.3 33.5MM MB-USH/B
NFC board _FFC@
NFC board _FFC@
Part Number
Part Number
NBX0001CU00 FFC 15P F P0.5 PAD=0.3 56.01MM MB-NFC
NBX0001CU00 FFC 15P F P0.5 PAD=0.3 56.01MM MB-NFC
Media Board FFC@
Media Board FFC@
Part Number
Part Number
NBX0001CS00 FFC 8P G P0.5 PAD=0.3 51.8MM MB-MEDIA/B
NBX0001CS00 FFC 8P G P0.5 PAD=0.3 51.8MM MB-MEDIA/B
SIM Board FFC + Hall Sensor FFC@
SIM Board FFC + Hall Sensor FFC@
Part Number
Part Number
NBX0001CR00 FFC 12P G P0.5 PAD=0.3 73.3MM MB-SIM+HALL/B
NBX0001CR00 FFC 12P G P0.5 PAD=0.3 73.3MM MB-SIM+HALL/B
FFC 16P F P0.5 PAD=0.3 104.4MM MB-KBTP
FFC 16P F P0.5 PAD=0.3 104.4MM MB-KBTP
Description
Description
Description
Description
Description
Description
Description
Description
Description
Description
RTC BATT@
RTC BATT@
Part Number Description
Part Number Description
Part Number Description
Part Number Description
Part Number Description
Part Number Description
Part Number Description
Part Number Description
BATT CR2032 3V
BATT CR2032 3V
GC20323MX00
GC20323MX00
220MAH MAXELL
220MAH MAXELL
Speak@
Speak@
SPK PACK ZJX 2.0W 4 OHM FG
SPK PACK ZJX 2.0W 4 OHM FG
PK230003Q0L
PK230003Q0L
Battery bridge cable@
Battery bridge cable@
H-CONN SET 0FD M/B-BATTERY 9PIN
H-CONN SET 0FD M/B-BATTERY 9PIN
DC020014Z10
DC020014Z10
UMA DC_IN wire cable@
UMA DC_IN wire cable@
CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
DC30100BN0
DC30100BN0
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
KB/TP/RSMRST
KB/TP/RSMRST
KB/TP/RSMRST
LA-9431P
LA-9431P
LA-9431P
38 59Friday, May 17, 2013
38 59Friday, May 17, 2013
38 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 39
5
4
3
2
1
DC/DC Interface
+3.3V_ALW_PCH/+1.05V_RUN source
+3.3V_ALW_PCH
12
PJP14
PJP14
PAD-OPEN1x1m
D D
U43
U43
+3.3V_ALW
PCH_ALW_ON<37>
+1.05V_MODPHY
Q125
+1.05V_M +1.05V_MODPHY
+5V_ALW
12
+3.3V_ALW2
12
R442
R442
100K_0402_5%
100K_0402_5%
MPHYP_PWR_EN#
DMN66D0LDW-7_SOT363-6
C C
MPHYP_PWR_EN<12>
1 2
R420 0_0402_5%@ R420 0_04 02_5%@
DMN66D0LDW-7_SOT363-6
Q124B
Q124B
61
D
D
G
G
2
S
S
R445
R445
5
10K_0402_5%
10K_0402_5%
34
Q124A
Q124A
D
D
G
G
S
S
1.05V_MODPHY_EN
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Q125
SI3456DDV-T1-GE3_TSOP6
SI3456DDV-T1-GE3_TSOP6
D
D
6
S
S
45
2
1
G
G
3
2200P_0402_50V7K
2200P_0402_50V7K
1
C412
C412
2
12
1
C413
C413
R447
2
@R447
@
10U_0603_6.3V6M
10U_0603_6.3V6M
20K_0402_5%
20K_0402_5%
SIO_SLP_S3#<36,43,9>
RUN_ON<26,36,37>
SIO_SLP_S3#
RUN_ON
USH_PWR_ON<36>
SIO_SLP_S4#<36,43,9>
SUS_ON<36,43>
SIO_SLP_A#<36,44,9>
A_ON<37,44>
R416 0_0402_5%@ R416 0 _0402_5%@
R417 0_0402_5%@ R417 0 _0402_5%@
R418 0_0402_5%@ R418 0 _0402_5%@
1 2
R439 0_0402_5%@ R439 0 _0402_5%@
1 2
R421 0_0402_5%@ R421 0 _0402_5%@
1 2
R422 0_0402_5%@ R422 0 _0402_5%@
1 2
R423 0_0402_5%@ R423 0 _0402_5%@
1 2
R424 0_0402_5%@ R424 0 _0402_5%@
1 2
1 2
1 2
+5V_ALW
+1.05V_M
+3.3V_SUS/+3.3V_M source
+5V_ALW
1
VIN1
2
VIN1
3
ON1
4
VBIAS
5
ON2
6
VIN2
7
VIN2
TPS22966DPUR_SON14_2X3~D
TPS22966DPUR_SON14_2X3~D
U45
U45
1
2
3
4
5
6
7
VOUT1
VIN1
VOUT1
VIN1
ON1
VBIAS
ON2
VIN2
VOUT2
VIN2
VOUT2
GPAD
TPS22966DPUR_SON14_2X3~D
TPS22966DPUR_SON14_2X3~D
CT1
GND
CT2
VOUT1
VOUT1
GND
VOUT2
VOUT2
GPAD
14
13
12
11
10
9
8
15
CT1
CT2
14
+3.3V_ALW_PCH_U43
13
12
C390 470P_0402_50V7KC390 470P_0402_50V7K
11
10
C391 470P_0402_50V7KC391 470P_0402_50V7K
9
8
+1.05V_RUN_U43
15
+3.3V_SUS_U45
1 2
C397
C397
1 2
C398
C398
+3.3V_M_U45
1 2
1 2
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
PAD-OPEN1x1m
1 2
C389 0.1U_0402_10V7KC389 0.1U_0402_10V7K
PJP15 PAD-OPEN1x1mP JP15 PAD -OPEN1x1m
1
C393
C393
0.1U_0402_10V7K
0.1U_0402_10V7K
2
+3.3V_SUS
12
PJP16
PJP16
PAD-OPEN1x1m
PAD-OPEN1x1m
1 2
C396 0.1U_0402_10V7KC396 0.1U_0402_10V7K
PJP17 PAD-OPEN1x1mP JP17 PAD-OPEN1x1m
1
C399
C399
0.1U_0402_10V7K
0.1U_0402_10V7K
2
12
+1.05V_RUN
12
+3.3V_M+3.3V_ALW
+3.3V_RUN/+5V_RUN source
B B
U46
U46
1
2
3
4
5
6
7
VOUT1
VIN1
VOUT1
VIN1
CT1
ON1
GND
VBIAS
ON2
CT2
VIN2
VOUT2
VIN2
VOUT2
GPAD
TPS22966DPUR_SON14_2X3~D
TPS22966DPUR_SON14_2X3~D
14
+5V_RUN_U46
13
12
11
10
9
8
15
1 2
C401
C401
1 2
C402
C402
+3.3V_RUN_U46
RUN_ON
1 2
R425 0_0402_5%@ R425 0 _0402_5%@
1 2
R426 0_0402_5%@ R426 0 _0402_5%@
+5V_ALW
+3.3V_ALW
SIO_SLP_S3#
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
POWER CONTROL
POWER CONTROL
POWER CONTROL
LA-9431P
LA-9431P
LA-9431P
+5V_RUN
470P_0402_50V7K
470P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1
12
PJP18
PJP18
PAD-OPEN1x1m
PAD-OPEN1x1m
1 2
C400 0.1U_0402_10V7KC400 0.1U_0402_10V7K
12
PJP19 PAD-OPEN1x1mP JP19 PAD-OPEN1x1m
1
C403
C403
0.1U_0402_10V7K
0.1U_0402_10V7K
2
39 59Friday, May 17, 2013
39 59Friday, May 17, 2013
39 59Friday, May 17, 2013
+3.3V_RUN
0.3
0.3
0.3
Page 40
5
4
3
2
1
+5V_ALW +5V_ALW
LED7
LED7
21
W
W
43
Y
Y
BATT_WHITE_LED# <22>
BATT_YELLOW_LED# <22>
Breath LED
+5V_ALW
BATT_WHITE#
BATT_YELLOW#
LTW-295DSKS-5A_YEL-WHITE
LTW-295DSKS-5A_YEL-WHITE
R434 150_0402_5%R434 150_0402_5%
Battery LED
1 2
BREATH_WHITE_LED# <22>
+3.3V_ALW
12
R428
R428
10K_0402_5%
Q24A
Q24A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
34
SGD
D D
C C
SATA_ACT#<6>
MASK_SATA_LED#<36>
LED_SATA_DIAG_OUT#<36>
WIRELESS_LED#<31,36>
SGD
5
10K_0402_5%
D23
D23
21
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
D24
D24
21
RB751S40T1G_SOD523-2
RB751S40T1G_SOD523-2
SYS_LED_MASK#
+3.3V_ALW
12
R432
R432
100K_0402_5%
100K_0402_5%
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
MASK_BASE_LEDS#
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
MASK_BASE_LEDS#
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Q25B
Q25B
61
S
D
S
D
G
G
2
Q25A
Q25A
Q24B
Q24B
SGD
SGD
5
2
HDD LED solution for White LED
+5V_ALW
Q15
Q15
PDTA114EU_SC70-3
2
61
S
D
S
D
G
G
2
34
2
PDTA114EU_SC70-3
1 3
1 2
R430 150_0402_5%R430 150_0402_5%
Q26
Q26
PDTA114EU_SC70-3
PDTA114EU_SC70-3
1 3
1 2
R438 220_0402_5%R438 220_0402_5%
WLAN LED solution for White LED
+5V_ALW
Q16
Q16
PDTA114EU_SC70-3
PDTA114EU_SC70-3
1 3
WLAN_LED
2 1
1 2
R435 150_0402_5%R435 150_0402_5%
LED6
LED6
2 1
SATA_LED
LTW-193ZDS5_WHITE
LTW-193ZDS5_WHITE
PANEL_HDD_LED# <22>
LED5
LED5
LTW-193ZDS5_WHITE
LTW-193ZDS5_WHITE
Q23A
Q23A
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
34
SGD
BAT2_LED#<36>
BAT1_LED#<36>
BREATH_LED#<34,36>
SGD
5
MASK_BASE_LEDS#
Q23B
Q23B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
61
S
D
S
D
G
G
2
MASK_BASE_LEDS#
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Q28B
Q28B
61
S
D
S
D
G
G
2
MASK_BASE_LEDS#
BAT2_LED#_Q
Q28A
Q28A
1 2
R427 150_0402_5%R427 150_0402_5%
1 2
150_0402_5%
150_0402_5%
BAT1_LED#_Q
SGD
SGD
5
1 2
R433
R433
150_0402_5%
150_0402_5%
1 2
34
LED1
LED1
LTW-193ZDS5_WHITE
LTW-193ZDS5_WHITE
Place LED1 close to SW1
1 2
R436 330_0402_5%R436 330_0402_5%
R431
R431
R429
R429
330_0402_5%
330_0402_5%
21
BREATH_WHITE_LED_SNIFFBREATH_LED#_Q
LED(white) current need to reach 2mA,
need to check current limit resistor
+3.3V_ALW
C404 0.1U_0402_25V6@ C404 0.1U_0402_25V6@
1 2
5
U47
U47
SYS_LED_MASK#<36>
B B
POWER_SW#_MB<37,9>
SYS_LED_MASK#
LID_CL#<31,36>
POWER & INSTANT ON SWITCH
Fiducial Mark
FD1
@FD1
@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
A A
FD2
@FD2
@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FD3
@FD3
@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
FD4
@FD4
@
1
FIDUCIAL MARK~D
FIDUCIAL MARK~D
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11
H4
@ H4
@H1
@
H_2P8
H_2P8
H1
@ H2
@
H_2P8
H_2P8
1
@
H3
@H3
@
H2
H_2P8
H_2P8
H_2P8
H_2P8
1
1
1
5
1
P
B
O
2
A
G
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
SW1
SW1
2
4
SKRBAAE010_4P
SKRBAAE010_4P
LED Circuit Control Table
H8
@ H8
@
H5
@H5
@
H_2P3
H_2P3
1
H_3P4
H_3P4
@ H9
@
H_3P4
H_3P4
1
4
MASK_BASE_LEDS#
1
3
MASK_BASE_LEDS# <28>
+COINCELL<31,41>
SYS_LED_MASK# LID_CL#
0
1 0
H10
@H10
@
H9
H_3P4
H_3P4
1
H12
@ H12
@
H13
@ H13
@
H14
@H14
@
@H15
H11
@H11
@
H_2P8
H_2P8
H_3P4
H_3P4
1
1
@
H_2P8
H_2P8
H_2P1
H_2P1
H_2P8
H_2P8
1
1
1
4
JRTC1
@JRT C1
@
1
3
1
G
4
22G
TYCO_2-1775293-2~D
TYCO_2-1775293-2~D
CONN@
CONN@
JMEDIA
JMEDIA
8
GND2
7
GND1
6
6
VOL_UP<37>
VOL_DOWN<37>
VOL_MUTE<37>
X
ST1
@ ST1
@
H18
@ H18
@1H17
@ H17
@
H16
@H16
@
H15
H_2P8
H_2P8
H_2P8
H_2P8
1
1
1
H_2P8
H_2P8
CLIP_C5P1
CLIP_C5P1
1
@ST2
@
H_2P8
H_2P8
ST2
1
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
ST update symbol to 6718K-Y06N-01L
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
5
4
4
3
3
2
2
1
1
E-T_6718K-Y06N-01L
E-T_6718K-Y06N-01L
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PAD & ME & LED
PAD & ME & LED
PAD & ME & LED
LA-9431P
LA-9431P
LA-9431P
1
40 59Friday, May 17, 2013
40 59Friday, May 17, 2013
40 59Friday, May 17, 2013
0.3
0.3
0.3
Page 41
5
4
3
2
1
+COINCELL
COIN RTC Battery
12
PR1
PR1
1K_0402_5%~D
+3.3V_RTC_LDO
D D
1
PD1
PD1
TVNST52302AB0_SOT523-3
TVNST52302AB0_SOT523-3
2
Primary Battery Connector
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
12
PC3
PC3
2200P_0402_50V7K~D
2200P_0402_50V7K~D
C C
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
GND
11
GND
@
@
PBATT1
PBATT1
Z4304
Z4305
Z4306
GND
3
1
PD2
PD2
TVNST52302AB0_SOT523-3
TVNST52302AB0_SOT523-3
2
3
PRP2
PRP2
100_0804_8P4R_5%
100_0804_8P4R_5%
PL1
PL1
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
1 2
PL2
PL2
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
PBATT+_C
@ PC2
@
0.1U_0603_25V7K~D
18
27
36
45
0.1U_0603_25V7K~D
PBAT_SMBCLK <37>
PBAT_SMBDAT <37>
1 2
12
PC2
+PBATT
SLICE_BAT_PRES#<34,36,48>
+3.3V_ALW
12
PR2
PR2
100K_0402_5%~D
100K_0402_5%~D
PD4
PD4
1 2
SDMK0340L-7-F_SOD323-2~D
SDMK0340L-7-F_SOD323-2~D
BAS40CW SOT-323
BAS40CW SOT-323
@
@
PR6
PR6
1 2
0_0402_5%
0_0402_5%
+5V_ALW
+3.3V_ALW
2
3
PD5
@ PD5
@
DA204U_SOT323~D
PR7
@ PR7
@
change from 0603 to 0402 size PN: SM010028600
PL3
PL3
BLM15AG102SN1D_2P
BLM15AG102SN1D_2P
NB_PSID
B B
12
PR10
PR10
100K_0402_1%~D
100K_0402_1%~D
15K_0402_1%~D
15K_0402_1%~D
PR12
PR12
1 2
1 2
1 2
0_0402_5%~D
0_0402_5%~D
D
D
1 3
G
G
2
C
C
2
PQ3
PQ3
B
B
MMST3904-7-F_SOT323~D
MMST3904-7-F_SOT323~D
E
E
3 1
S
S
PQ2
PQ2
FDV301N_G_NL_SOT23-3~D
FDV301N_G_NL_SOT23-3~D
DA204U_SOT323~D
PR9
PR9
33_0402_5%~D
33_0402_5%~D
1 2
1
+5V_ALW
12
PR11
PR11
10K_0402_1%~D
10K_0402_1%~D
GND
PR13
@ PR13
@
1 2
10K_0402_5%~D
10K_0402_5%~D
PR8
PR8
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2
DOCK_PSID<34> GPIO_PSID_SELECT <36>
NB_PSID_TS5A63157
PSID_DISABLE# <36>
1K_0402_5%~D
Z4012
2
3
PD3
PD3
1
PBAT_PRES# <36,48>
PQ1
PQ1
ME2301D-G 1P SOT-23-3
ME2301D-G 1P SOT-23-3
1 3
1
3
1
3
2
2
2
12
PC4
PC4
1500P_0402_7K~D
1500P_0402_7K~D
PU111
PU111
1
NO
2
GND
NC3COM
TS5A63157DCKR_SC70-6~D
TS5A63157DCKR_SC70-6~D
+COINCELL
+RTC_CELL
1
PC1
PC1
1U_0603_10V4Z~D
1U_0603_10V4Z~D
2
DOCK_SMB_ALERT# <34, 36,48>
6
IN
5
+5V_ALW
V+
4
PS_ID <37>
+COINCELL <31,40>
DC_IN+ Source
+DC_IN
PL4
PL4
FBMJ4516HS720NT_2P~D
FBMJ4516HS720NT_2P~D
1 2
PQ6B
PQ6B
2
16
12
PR16
PR16
@
@
4.7K_0805_5%~D
4.7K_0805_5%~D
DCX124EK-7-F PNP/NPN_SC74-6~D
DCX124EK-7-F PNP/NPN_SC74-6~D
PC9
PC9
1000P_0603_50V7K~D
1000P_0603_50V7K~D
@
@
12
@
@
PJP1
PJP1
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
1
12
PD6
PD6
2
PC11
PC11
@
@
VZ0603M260APT_0603
VZ0603M260APT_0603
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
ACES_50299-00501-003
ACES_50299-00501-003
7
GND
6
GND
5
-DCIN_JACK
5
4
4
3
+DCIN_JACK
3
A A
2
2
1
1
@
@
PJPDC1
PJPDC1
12
PC12
PC12
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
5
PQ6A
PQ6A
DCX124EK-7-F PNP/NPN_SC74-6~D
DCX124EK-7-F PNP/NPN_SC74-6~D
4 3
5
+DC_IN
PC5
PC5
1 2
0.022U_0805_50V7K~D
0.022U_0805_50V7K~D
AC_DIS <36,48>
4
12
PR14
PR14
1M_0402_5%~D
1M_0402_5%~D
FDMC6679AZ_MLP8-5
FDMC6679AZ_MLP8-5
1
2
3 5
PR17
PR17
1 2
10K_0402_5%~D
10K_0402_5%~D
12
PR18
PR18
1M_0402_5%~D
1M_0402_5%~D
PQ4
PQ4
4
SOFT_START_GC <48>
12
12
PC7
PC7
PC6
PC6
@
@
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
+DC_IN_SS
12
12
PC8
PC8
@
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
12
PC10
PC10
PR15
PR15
10U_0805_25V6K
10U_0805_25V6K
100K_0402_5%~D
100K_0402_5%~D
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+DCIN
+DCIN
+DCIN
LA-9591P
LA-9591P
LA-9591P
1
41 58Friday, May 17, 2013
41 58Friday, May 17, 2013
41 58Friday, May 17, 2013
0.3
0.3
0.3
Page 42
A
B
C
D
E
1 1
PJP100
@ PJP100
@
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PL100
PL100
1UH_PCMB053T-1R0MS_7A_ 20%
1UH_PCMB053T-1R0MS_7A_ 20%
2 2
+PWR_SRC
+3.3V_ALWP
12
PC112
PC112
@
@
3 3
PC113
PC113
0.1U_0603_25V7K
0.1U_0603_25V7K
+DC1_PWR_SRC
12
12
PC105
PC105
PC108
PC108
@
@
@
@
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
PL101
PL101
2.2UH_ETQP3W2R2W FN_8.5A_20%
2.2UH_ETQP3W2R2W FN_8.5A_20%
1
+
+
2
330U_D_6.3VM_R25M
330U_D_6.3VM_R25M
680P_0603_50V7K
680P_0603_50V7K
12
PC107
PC107
@
@
10U_0805_25V6K
10U_0805_25V6K
12
@
@
PC111
PC111
PR111
@ PR111
@
4.7_1206_5%
4.7_1206_5%
12
PC104
PC104
10U_0805_25V6K
10U_0805_25V6K
12
12
12
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
PQ100
PQ100
ALW_PWRGD_3V _5V<37>
3 5
241
PQ102
PQ102
FDMC7692S_POWER33 -8-5
FDMC7692S_POWER33 -8-5
3 5
241
+3.3V_ALW
100K_0402_1%~D
100K_0402_1%~D
@
@
PR108
PR108
1 2
0_0402_5%
0_0402_5%
PC109
PC109
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
PR107
PR107
+3.3V_ALW2
PR100
PR100
6.49K_0402_1%~D
6.49K_0402_1%~D
1 2
PR102
PR102
10K_0402_5%~D
10K_0402_5%~D
1 2
PR105
PR105
20K_0402_1%~D
20K_0402_1%~D
1 2
1 2
PR110
PR110
2.2_0603_5%
2.2_0603_5%
1 2
EN
PGOOD_3V_5V
UG_3V
BST_3V
SW2
LG_3V
+DC1_PWR_SRC
PU100
PU100
6
7
10
9
8
PR103
PR103
@
@
EN2
PGOOD
DRVH2
VBST2
SW2
0_0402_5%
0_0402_5%
12
PC100
PC100
1 2
4.7U_0603_10V6K
4.7U_0603_10V6K
2
3
4
5
CS2
VFB2
VREG3
TPS51285BRUKR QFN 20P
TPS51285BRUKR QFN 20P
DRVL211VIN12VREG5
13
20
EN
12
PC117
PC117
PC118
PC118
0.1U_0603_25V7K
0.1U_0603_25V7K
4.7U_0603_10V6K
4.7U_0603_10V6K
PR101
PR101
15K_0402_1%
15K_0402_1%
PR104
PR104
10K_0402_5%~D
10K_0402_5%~D
1
CS1
VFB1
VCLK
DRVH1
VBST1
SW1
DRVL1
EN1
15
12
1 2
PAD
VO1
12
12
PR106
PR106
16.9K_0402_1%
16.9K_0402_1%
21
14
19
16
UG_5V
17
BST_5V
18
SW1
LG_5V
+5V_ALW2
PR114
PR114
200_0402_1%
200_0402_1%
12
PR109
PR109
2.2_0603_5%
2.2_0603_5%
1 2
PC110
PC110
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
FDMC7692S_POWER33 -8-5
FDMC7692S_POWER33 -8-5
PQ103
PQ103
PQ101
PQ101
3 5
241
FDMC8884_POWER33-8-5
FDMC8884_POWER33-8-5
3 5
241
+DC1_PWR_SRC
12
12
PC102
PC102
PC106
PC106
PC101
PC101
@
@
@
@
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
3.3UH_ETQP3W3R3W FN_7A_20%
3.3UH_ETQP3W3R3W FN_7A_20%
1 2
12
@
@
PC114
PC114
680P_0603_50V7K
680P_0603_50V7K
12
@
@
PR112
PR112
4.7_1206_5%
4.7_1206_5%
12
10U_0805_25V6K
10U_0805_25V6K
PL102
PL102
12
PC103
PC103
@
@
10U_0805_25V6K
10U_0805_25V6K
+5V_ALWP
1
+
+
12
PC115
PC115
2
PC116
PC116
@
@
330U_D_6.3VM_R25M
330U_D_6.3VM_R25M
0.1U_0603_25V7K
0.1U_0603_25V7K
+3.3V_RTC_LDO
3VALWP
EN
TDC 6.7 A
Peak Current 8.1 A
OCP Current 9.72 A
ALWON<37>
Rds(on): 13.6m ohm (max)
4 4
A
B
@
@
PR113
PR113
0_0402_5%
0_0402_5%
PJP101
12
+5V_ALWP
+3.3V_ALWP
12
PC119
PC119
@
@
1U_0603_10V6K
1U_0603_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
PJP101
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
PJP102
PJP102
1 2
PAD-OPEN 1x3m
PAD-OPEN 1x3m
+5V_ALW
+3.3V_ALW
D
5VALWP
TDC 4.88 A
Peak Current 6.89 A
OCP Current 8.268 A
Rds(on):13.6m ohm (max)
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
+5V_ALW/3.3V_ALW
LA-9591P
LA-9591P
LA-9591P
42 58Friday, May 17, 2013
42 58Friday, May 17, 2013
42 58Friday, May 17, 2013
E
0.3
0.3
0.3
Page 43
5
4
3
2
1
1.35Volt +/- 5%
TDC: 7.2 A
Peak Current: 10 A
OCP current: 12 A
Rds(on): 13.6m ohm(max)
PJP200
+PWR_SRC
D D
+1.35V_MEN_P
C C
B B
Mode S3 S5 +1.5V_MEN +V_DDR_REF +0.75V_P
S5 L L off off off
S3 L H on on off(Hi-Z)
S0 H H on on on
PJP200
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
330U_D2_2VM_R15M
330U_D2_2VM_R15M
1
PC207
PC207
+
+
2
1.35V_B+
12
12
PC200
PC200
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
PL200
PL200
1UH_PCM B063T-1R0MS_1 2A_20%
1UH_PCM B063T-1R0MS_1 2A_20%
1 2
12
PC208
@ PC208
@
680P_06 03_50V7K
680P_06 03_50V7K
SNUB_1.35V
12
@
@
PR203
PR203
4.7_1206 _5%
4.7_1206 _5%
SIO_SLP_S 4#<36,39 ,9>
SUS_ON<36 ,39>
12
PC202
PC202
PC201
PC201
0.1U_0402_25V6
0.1U_0402_25V6
@
@
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
FDMC888 4_POWER33 -8-5
FDMC888 4_POWER33 -8-5
FDMC769 2S_POWER3 3-8-5
FDMC769 2S_POWER3 3-8-5
12
@
@
1.35V_SU S_PWRGD<37>
PC203
PC203
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PQ200
PQ200
PQ201
PQ201
PR207
@ PR2 07
@
0_0402_ 5%~D
0_0402_ 5%~D
1 2
PR208
@ PR208
@
1 2
0_0402_ 5%
0_0402_ 5%
3 5
241
3 5
241
100K_04 02_1%~D
100K_04 02_1%~D
12
PC215
@ PC2 15
@
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
1 2
PC204
PC204
0.22U_0603_16V7K~D
0.22U_0603_16V7K~D
+5V_ALW
+3.3V_ALW
12
PR204
PR204
PR200
PR200
1 2
2.2_0603 _5%~D
2.2_0603 _5%~D
PR202
PR202
1 2
5.1_0603 _5%~D
5.1_0603 _5%~D
S5_1.35V
BOOT_1.3 5V
PR201
PR201
23.7K_04 02_1%
23.7K_04 02_1%
1 2
1U_0603 _10V6K~D
1U_0603 _10V6K~D
PC211
PC211
1U_0603 _10V6K~D
1U_0603 _10V6K~D
DH_1.35V
SW_ 1.35V
DL_1.35V
CS_1.35V
PC209
PC209
VDD_1.35 V
1.35V_SU S_PWRGD
0.675V_D DR_VTT_ON<18 >
SIO_SLP_S 3#<36,39 ,9>
+5V_ALW
1.35V_B+
16
15
LGATE
14
PGND
13
CS
RT8207M ZQW_W QFN20_3X3
RT8207M ZQW_W QFN20_3X3
12
VDDP
11
VDD
10
PR206
PR206
1 2
1M_0402 _1%~D
1M_0402 _1%~D
PR210
@ PR210
@
1 2
0_0402_ 5%
0_0402_ 5%
PR211
@ PR21 1
@
1 2
0_0402_ 5%~D
0_0402_ 5%~D
+1.35V_M EN_P
PJP201
PJP201
+VLDOIN_1 .35V
18
17
PHASE
UGATE
PGOOD
TON
8
9
20
19
PU11
PU11
21
VTT
BOOT
S5
PAD
VTTGND
VTTSNS
GND
VTTREF
VDDQ
FB
6
1.35V_FB
1
2
3
4
5
VLDOIN
S3
7
12
+1.35V_MEN_P
PAD-OPEN 1x1m
PAD-OPEN 1x1m
+V_DDR_ REF
+1.35V_MEN_P
FB sense trace
when FB pull down to GND
PR205
PR205
8.06K_04 02_1%~D
8.06K_04 02_1%~D
12
PC213
PC213
100P_04 02_50V8J~D
100P_04 02_50V8J~D
12
PR209
PR209
10K_040 2_1%
10K_040 2_1%
1 2
12
@
@
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A
12
PC205
PC205
22U_0805_6.3V6M
22U_0805_6.3V6M
PC214
PC214
+0.675V_P
+V_DDR_REF
PC212
PC212
0.033U_0 402_16V7~D
0.033U_0 402_16V7~D
FB sense trace
PJP203
PJP203
2
112
JUMP_1x3m
JUMP_1x3m
PJP204
PJP204
+1.35V_MEN_P
A A
2
JUMP_1x3m
JUMP_1x3m
112
+1.35V_MEM
+0.675V_P
PJP202
PJP202
12
PAD-OPEN 1x1m
PAD-OPEN 1x1m
+0.675V_DDR_VTT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Documen t Number Rev
Size Documen t Number Rev
Size Documen t Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+1.35V_MEN/+0.675V_DDR_VTT
+1.35V_MEN/+0.675V_DDR_VTT
+1.35V_MEN/+0.675V_DDR_VTT
LA-9591P
LA-9591P
LA-9591P
43 58Friday, May 17, 2013
43 58Friday, May 17, 2013
43 58Friday, May 17, 2013
1
0.3
0.3
0.3
Page 44
5
D D
1.05V_A_PWRGD<37>
PR302
PR302
1 2
95.3K_0402_1%
95.3K_0402_1%
@
@
PR303
PR303
SIO_SLP_A#<36,39,9>
S0 mode be high level
C C
A_ON<37,39 >
1 2
0_0402_5%~D
0_0402_5%~D
@
@
PR304
PR304
1 2
0_0402_5%
0_0402_5%
0.1U_0402_16V7K
0.1U_0402_16V7K
12
@
@
PC308
PC308
+3.3V_ALW
TRIP_+V1.05SP
EN_+V1.05SP
FB_+V1.05SP
RF_+V1.05SP
12
PR305
PR305
470K_0402_1%
470K_0402_1%
12
PR300
PR300
100K_0402_1%~D
100K_0402_1%~D
4
PU300
PU300
1
2
3
4
5
VBST
PGOOD
TRIP
DRVH
EN
VFB
RF
TPS51212DSCR_SON10_ 3X3
TPS51212DSCR_SON10_ 3X3
SW
V5IN
DRVL
TP
10
9
8
7
6
11
BST_+V1.05SP
UG_+V1.05SP
SW_+V1.05SP
LG_+V1.05SP
+5V_ALW
12
PC305
PC305
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
3
PR301
PR301
2.2_0603_5%
2.2_0603_5%
1 2
PC304
PC304
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
PQ301
FDMC7692S_POWER33-8-5
FDMC7692S_POWER33-8-5
PQ301
PQ300
PQ300
FDMC8884_POWER33-8- 5
FDMC8884_POWER33-8- 5
3 5
241
3 5
241
2
+V1.05SP_B+
PC300
PC300
@
@
2.2UH_ETQP3W2R2 WFN_8.5A_20%
2.2UH_ETQP3W2R2 WFN_8.5A_20%
1 2
12
PC306
@ PC306
@
680P_0603_50V7K
680P_0603_50V7K
12
PR306
@ PR306
@
4.7_1206_5%
4.7_1206_5%
1
PJP300
PJP300
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
12
12
0.1U_0402_25V6
0.1U_0402_25V6
@
@
PL300
PL300
12
12
10U_0805_25V
PC301
PC301
PC302
PC302
2200P_0402_50V7K
2200P_0402_50V7K
@
@
10U_0805_25V
PC303
PC303
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
+PWR_SRC
+1.05V_MP
1
+
+
PC307
PC307
220U_B2_2.5VM_R15M
220U_B2_2.5VM_R15M
2
PR307
PR307
4.99K_0402_1%
4.99K_0402_1%
12
+1.05Volt +/- 5%
B B
A A
5
PR308
PR308
10K_0402_1%
10K_0402_1%
1 2
+1.05V_MP
2 1
PAD-OPEN 1x2m~D
PAD-OPEN 1x2m~D
+1.05V_M
PJP301
PJP301
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
TDC 3.67 A
Peak Current 5.25 A
OCP current 6.3 A
Rds(on): 13.6m ohm (max)
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+1.05V_M
+1.05V_M
+1.05V_M
LA-9591P
LA-9591P
LA-9591P
44 58Friday, May 17, 2013
44 58Friday, May 17, 2013
44 58Friday, May 17, 2013
1
0.3
0.3
0.3
Page 45
5
4
3
2
1
D D
+3.3V_RUN
PR400
PR400
1 2
100K_0402_5%~D
100K_0402_5%~D
@
@
PR401
PR401
47K_0402_5%
47K_0402_5%
C C
B B
12
12
@
@
0.1U_0402_16V7K
0.1U_0402_16V7K
PC402
PC402
7
POK
8
EN
+5V_ALW
6
VOUT
VCNTL
VOUT
GND
1
PJP400
PJP400
PAD-OPEN1x1m
PAD-OPEN1x1m
12
PC400
PC400
1U_0402_6.3V6K
1U_0402_6.3V6K
5
VIN
4
3
2
FB
9
VIN
PU400
PU400
APL5930KAI-TRG_SO8
APL5930KAI-TRG_SO8
+3.3V_RUN
12
12
PC401
PC401
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
PR402
PR402
1.54K_0402_1%
1.54K_0402_1%
+3.3V_ALW
12
@ PJP402
@
PAD-OPEN1x1m
PAD-OPEN1x1m
12
12
PR403
PR403
1.74K_0402_1%
1.74K_0402_1%
PJP402
1.5VSP
12
PC403
PC403
0.01U_0402_25V7K
0.01U_0402_25V7K
12
PC404
PC404
22U_0805_6.3V6M
22U_0805_6.3V6M
PJP401
PJP401
PAD-OPEN1x1m
PAD-OPEN1x1m
12
+1.5V_THERMAL
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
<Issued_Date> <Deciphered_Date>
<Issued_Date> <Deciphered_Date>
<Issued_Date> <Deciphered_Date>
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
+1.05VS_VTTP/+1.0VSP
+1.05VS_VTTP/+1.0VSP
+1.05VS_VTTP/+1.0VSP
Chief River VC
1
0.3
0.3
45 58Friday, May 17, 2013
45 58Friday, May 17, 2013
45 58Friday, May 17, 2013
0.3
Page 46
5
4
20120911 TI-Alex Note: Although there is no pulse-overlap in 1-phase mode, during USR, the pulse comes in immediately.
So, the problem with PR504 = DNP is that if there is a high ripple, and USR is faultily detected, you will get a double-pulse.
So, we want to make sure USR is not active if it is not necessary. So, I moved it all the way to highest level so PR504 works to 8.87k.
3
2
1
VREF
100K_0402_1%_NCP15WF104F03RC
100K_0402_1%_NCP15WF104F03RC
12
PH500
PR505
PR505
PU500
PU500
17
CSP1
18
CSN1
19
CSN2
20
CSP2
21
PU3
22
N/C
23
GFB
24
VFB
1 2
2.32K_0402_1%
2.32K_0402_1%
10_0603_1%
10_0603_1%
10K_0402_5%~D
10K_0402_5%~D
PR521
PR521
PR526
PR526
H_PROCHOT#<37,47,48,9>
1 2
VREF
PC507
PC507
PH500
12
PC501
PC501
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
15
16
14
13
VBAT
SLEWA
THERM
COMP26VCLK31V5A28DROP
GND
25
29
27
1 2
12
1 2
@
@
PR500
PR500
75_0402_1%
75_0402_1%
1 2
D D
+VCC_PWR_SRC
SLEWA
PR510
PR510
39K_0402_5%~D
39K_0402_5%~D
PR511
PR511
1 2
10K_0402_5%~D
10K_0402_5%~D
CSN1
1 2
CSP1
+3.3V_RUN
+3.3V_RUN
VFB
GFB
C C
PC506
@ PC506
@
1 2
100P_0402_50V8~D
100P_0402_50V8~D
PR523
PR523
1 2
10K_0402_5%~D
10K_0402_5%~D
1 2
1 2
PR535
PR535
4.87K_0402_1%
4.87K_0402_1%
PC512
PC512
1500P_0402_50V7K
1500P_0402_50V7K
0.33U_0603_10V7K~D
0.33U_0603_10V7K~D
+5V_ALW
+1.05V_VCCST
B B
12
12
PR527
PR527
54.9_0402_1%
VIDSCLK<15>
VIDALERT_N<15>
VIDSOUT<15>
54.9_0402_1%
12
12
PR529
PR529
PR528
PR528
@
@
75_0402_1%
75_0402_1%
110_0402_1%
110_0402_1%
1 2
PC500
PC500
4700P_0603_50V7K
4700P_0603_50V7K
12
11
10
9
IMON
OCP-I
F-IMAX
B-RAMP
ALERT#
GND
VR_HOT#30VREF
32
33
VR_HOT#
12
PC510
PC510
1U_0603_10V7K~D
1U_0603_10V7K~D
PC511
PC511
0.1U_0402_25V6
0.1U_0402_25V6
IMON
OCP-I
O-USR
VR_ON
SKIP#
PWM1
PWM2
N/C
PGOOD
VDD
VDIO
TPS51622RSM
TPS51622RSM
PR534
PR534
@
@
0_0402_5%
0_0402_5%
1 2
PC514
PC514
47P_0402_50V8J~D
47P_0402_50V8J~D
8
7
6
5
4
3
2
1
VIDSCLK
PR501
PR501
1 2
365K_0402_1%
365K_0402_1%
PR506
PR506
1 2
75K_0402_1%
75K_0402_1%
@
@
PR537 0_0402_5%
PR537 0_0402_5%
VIDSOUT
VIDALERT_N
B-RAMP
@
@
PR536
PR536
0_0402_5%
0_0402_5%
SKIP#
PWM1
1 2
@
@
PR502
PR502
1 2
75_0402_1%
75_0402_1%
F-IMAX
PR507
PR507
1 2
150K_0402_1%
150K_0402_1%
12
12
@
@
PR513
PR513
1 2
75_0402_1%
75_0402_1%
@ PR516
@
1 2
1.91K_0402_1%~D
1.91K_0402_1%~D
PR519
PR519
12
1_0603_5%
1_0603_5%
PC505
PC505
1U_0603_10V6K
1U_0603_10V6K
VCCSENSE<15>
from processor
VSSSENSE<17>
PR503
PR503
1M_0402_1%
1M_0402_1%
1 2
O-USR
PR508
PR508
1 2
150K_0402_1%
150K_0402_1%
H_VR_EN <15>
IMVP_VR_ON <36>
PR516
+3.3V_RUN
PR504
PR504
1 2
8.87K_0402_1%
8.87K_0402_1%
PR509
PR509
1 2
150K_0402_1%
150K_0402_1%
@
@
PR539
PR539
0_0402_5%
0_0402_5%
PR540
@ PR540
@
0_0402_5%
0_0402_5%
+3.3V_RUN
+PWR_SRC
12
H_VR_READY <15>
12
IMVP_PWRGD <36>
PWM1
@
@
PR531
PR531
0_0402_5%
0_0402_5%
PR532
@ PR532
@
0_0402_5%
0_0402_5%
PJP500
@ PJP500
@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
1 2
FBMA-L11-453215-121LMA90T
FBMA-L11-453215-121LMA90T
+VCC_PWR_SRC
PL501
PL501
PC503
PC503
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1 2
TI recommend 1nF
12
VFB
12
GFB
12
12
12
PC731
PC731
PC736
PC736
10U_0805_25V6K
10U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
PC504
PC504
1 2
0.1U_0402_25V6
0.1U_0402_25V6
0_0603_5%~D
0_0603_5%~D
CPU
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DCR: 0.82m +-5% ohm
PH500 B value: 4250k 1%
PH501 B value: 3435k 1%
12
PC732
PC732
PC734
PC734
22U_0805_25V6K
22U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
9
8
7
6
12
5
PR517
PR517
CSD97374CQ4M_SON8_3P5X4P5
CSD97374CQ4M_SON8_3P5X4P5
1
+
+
PC735
PC735
@
@
2
PU501
PU501
PGND2
PWM
VSW
BOOT
PGND1
BOOT_R
SKIP#
VIN
1U_0603_10V7K~D
1U_0603_10V7K~D
VDD
1
+
+
PC738
PC738
2
33U_D_25VM_R60M
33U_D_25VM_R60M
100U_D3L_20VM_R55M
100U_D3L_20VM_R55M
10K_0402_1%_TSM0A103F34D1RZ
10K_0402_1%_TSM0A103F34D1RZ
CSP1
1 2
PC502
PC502
0.068U_0402_16V7K
0.068U_0402_16V7K
+VCC_CORE
1 2
PC513
PC513
0.068U_0402_16V7K
0.068U_0402_16V7K
CSN1
4
3
2
1
PC509
PC509
@PR520
@
0_0402_5%
0_0402_5%
1 2
1 2
PR520
SKIP#SKIP#1
+5V_RUN
0.22UH_FDUE0640J-H-R22M=P3_25A_20%
0.22UH_FDUE0640J-H-R22M=P3_25A_20%
4
12
3
PR522
PR522
4.7_1206_5%~D
4.7_1206_5%~D
12
PC508
PC508
820P_0603_50V7K~D
820P_0603_50V7K~D
PR512
PR512
2.1K_0402_1%~D
2.1K_0402_1%~D
12
12
PR514
PR514
43.2K_0402_1%
43.2K_0402_1%
PL500
PL500
1
2
12
PH501
PH501
12
PR515
PR515
3.01K_0402_1%
3.01K_0402_1%
A A
DELL CONFIDENTIAL/PROPRIETARY
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
+VCC_CORE
+VCC_CORE
+VCC_CORE
LA-9591P
LA-9591P
LA-9591P
46 58Friday, May 17, 2013
46 58Friday, May 17, 2013
46 58Friday, May 17, 2013
1
0.3
0.3
0.3
Page 47
5
PQ700 V30415-T1-GE3 1P POWERPAK1212-8PQ700 V30415-T1-GE3 1P POWERPAK1212-8
+DC_IN_SS
D D
1
2
35
4
PR701
@ PR701
@
1 2
0_0402_5%
0_0402_5%
+DOCK_PWR_BAR
+CHGR_DC_IN<48>
+SDC_IN
PR713
PR713
261K_0402_1%
261K_0402_1%
PR714
PR714
49.9K_0402_1%~D
49.9K_0402_1%~D
C C
ACAV_IN<37,47,48>
PR747
PR747
100K_0402_1%~D
100K_0402_1%~D
PR746
PR746
121K_0402_1%~D
121K_0402_1%~D
GNDA_CHG
BQ24715_REGN
12
12
V_SYS<37>
GNDA_CHG
12
12
PC708 0.1U_0402_25V6PC708 0.1U_0402_25V6
CHARGER_SMBDAT<37>
CHARGER_SMBCLK<37>
PR717
@ PR717
@
1 2
0_0402_5%
0_0402_5%
1 2
GNDA_CHG
CHARGER_CELL_PIN<48>
+3.3V_ALW2
B B
DYN_TUR_CURRENT_SET#
PC724
45W
65W
DYN_TUR_CURRNT_SET#<37>
A A
High
Low
PQ712A
DMN66D0LDW-7 2N SOT363-6
DMN66D0LDW-7 2N SOT363-6
PQ712A
+3.3V_ALW2
12
PR730
PR730
150K_0402_1%
150K_0402_1%
12
12
PR734
PR734
210K_0402_1%
210K_0402_1%
61
2
12
PR735
PR735
PC726
PC726
69.8K_0402_1%
69.8K_0402_1%
100P_0402_50V8J~D
100P_0402_50V8J~D
PR732
PR732
20K_0402_1%~D
20K_0402_1%~D
1 2
VCP
+5V_ALW
PC724
@
@
12
Adapter Protection Circuit for Turbo Mode
5
DC_BLOCK_GC <48>
CSS_GC< 48>
+DC_IN_SS
1 2
+3.3V_ALW
PC719
PC719
100P_0402_50V8J~D
100P_0402_50V8J~D
12
PC725
PC725
@
@
100P_0402_50V8J~D
100P_0402_50V8J~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
PC727
PC727
220P_0402_50V8J~D
220P_0402_50V8J~D
4
+SDC_IN
BAT54CW_SOT323~D
BAT54CW_SOT323~D
@
@
1 2
1_0805_1%~D
1_0805_1%~D
PC706
PC706
10U_0805_25V6K
10U_0805_25V6K
BQ24715_REGN
12
8
3
P
+
2
-
G
4
4
@ PR702
@
1 2
0_0402_5%
0_0402_5%
PD701
PD701
2
3
PR708
PR708
12
+SDC_IN
221K_0402_1%~D
221K_0402_1%~D
PR729
PR729
1.8M_0402_1%
1.8M_0402_1%
1 2
PU2A
PU2A
1
O
LM393DR_SO8~D
LM393DR_SO8~D
220P_0402_50V8J
220P_0402_50V8J
PR702
1
PR726
PR726
@
@
1 2
10K_0402_1%~D
10K_0402_1%~D
PR711
PR711
1 2
10K_0402_1%~D
10K_0402_1%~D
@
@
PR750
PR750
1 2
0_0402_5%
0_0402_5%
@
@
PR751
PR751
1 2
10K_0402_1%~D
10K_0402_1%~D
PR727
PR727
PC740
PC740
@
@
@
@
12
PC700
PC700
NTR4502PT1G_SOT23-3~D
NTR4502PT1G_SOT23-3~D
PC703
PC703
1U_0603_25V6K
1U_0603_25V6K
1 2
12
PR745
PR745
GNDA_CHG
10_1206_5%~D
10_1206_5%~D
+DCIN
PR725
PR725
@
@
1 2
0_0402_5%
0_0402_5%
+5V_ALW
1 2
2
12
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
2
G
G
PQ702
PQ702
PR704
PR704
PU700
PU700
20
VCC
3
CMSRC
4
ACDRV
6
ACDET
8
SDA
9
SCL
5
ACOK
7
IOUT
10
CELL
BQ24715RGRR_QFN
BQ24715RGRR_QFN
GNDA_CHG
PR728
@ PR728
@
0_0402_5%
0_0402_5%
1 2
DMN66D0LDW-7 2N SOT363-6
DMN66D0LDW-7 2N SOT363-6
PQ710A
PQ710A
61
PR700
PR700
0.01_1206_1%~D
0.01_1206_1%~D
4
3
13
D
D
S
S
CSSP_1
PR703
PR703
10K_0402_5%~D
10K_0402_5%~D
12
10_0402_5%~D
10_0402_5%~D
PC704
PC704
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1 2
2
ACP
GNDA_CHG
3
5
4
21
3
+PWR_SRC_AC
1
2
13
D
D
2
PQ701
PQ701
G
NTR4502PT1G_SOT23-3~D
G
NTR4502PT1G_SOT23-3~D
S
S
CSSN_1
12
12
PR705
PR705
PR706
PR706
10_0402_5%~D
10_0402_5%~D
PC705
PC705
1 2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
BQ24715_REGN
REGN16ACN
17
PR715
PR715
BTST
2.2_0603_5%
2.2_0603_5%
1 2
18
HIDRV
19
PHASE
15
LODRV
14
GND
13
SRP
12
SRN
PR722
PR722
4.02K_0402_1%
4.02K_0402_1%
1 2
11
/BATDRV
TP
PJP701
PJP701
1 2
PAD-OPEN1x1m
PAD-OPEN1x1m
H_PROCHOT# <37,46,48,9>
DMN66D0LDW-7 2N SOT363-6
DMN66D0LDW-7 2N SOT363-6
PQ710B
PQ710B
+3.3V_ALW
PC728
PC728
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
12
5
PU3
PU3
1
P
B
4
O
2
A
G
3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
3
2
PL700
PL700
1UH_PCMB042T-1R0MS_4.5A_20%
PQ703A
PQ703A
SI3993CDV-T1-GE3_TSOP6~D
SI3993CDV-T1-GE3_TSOP6~D
S
S
D
D
65
G
G
1
SI3993CDV-T1-GE3_TSOP6~D
SI3993CDV-T1-GE3_TSOP6~D
12
12
100K_0402_1%~D
100K_0402_1%~D
PR707
PR707
100K_0402_1%~D
100K_0402_1%~D
GNDA_CHG
1 2
CHG_UGATE
12
PC713
PC713
CHG_LGATE
0.047U_0603_25V7M
0.047U_0603_25V7M
1UH_PCMB042T-1R0MS_4.5A_20%
S
S
PD702
PD702
BAT54HT1G_SOD323-2~D
BAT54HT1G_SOD323-2~D
12
@
@
PJP700
PJP700
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
PQ703B
PQ703B
D
D
42
G
G
3
@
@
PR709
PR709
1 2
0_0402_5%
0_0402_5%
PC709
PC709
1 2
1U_0603_10V6K~D
1U_0603_10V6K~D
PQ706
PQ706
SIRA06DP-T1-GE3_POWERPAKSO-8
SIRA06DP-T1-GE3_POWERPAKSO-8
5
4
123
5
4
123
CHAGER_SRC
DOCK_DCIN_IS+ <34>
DOCK_DCIN_IS- <34>
DK_CSS_GC <48>
12
PC707
PC707
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PQ704
PQ704
SIRA14DP-T1GE3_POWERPAK-SO8-5
SIRA14DP-T1GE3_POWERPAK-SO8-5
PL701
12
PC714
PC714
820P_0603_50V7K~D
820P_0603_50V7K~D
1 2
PR724
PR724
4.7_1206_5%~D
4.7_1206_5%~D
BATDRV# <48>
PL701
PC720
@PC720
@
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1 2
GNDA_CHG
12
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
12
PC711
PC711
22U_0805_25V6M
22U_0805_25V6M
+PWR_SRC
12
PC737
PC737
10U_0805_25V6K
10U_0805_25V6K
12
PC716
PC716
+SDC_IN
PC712
PC712
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
12
PC741
PC741
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
PR716
PR716
0.01_1206_1%~D
0.01_1206_1%~D
4
3
PR718
PR718
@
@
1 2
0_0402_5%
0_0402_5%
10U_0805_25V6K
10U_0805_25V6K
PC721
PC721
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1 2
PC733
PC733
12
@
@
+3.3V_ALW2
+3.3V_ALW
12
PR740
PR740
100K_0402_5%~D
100K_0402_5%~D
PROCHOT_GATE <36>
3
5
ACAV_IN <37,47,48>
PQ712B
PQ712B
4
DMN66D0LDW-7 2N SOT363-6
DMN66D0LDW-7 2N SOT363-6
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
+DC_IN
12
12
PR737
PR737
PR738
PR738
48.7K_0402_1%
48.7K_0402_1%
232K_0402_1%~D
232K_0402_1%~D
12
12
PC729
PC729
100P_0402_50V8J~D
100P_0402_50V8J~D
12
PR742
PR742
PR743
PR743
22.6K_0402_1%~D
22.6K_0402_1%~D
42.2K_0402_1%~D
42.2K_0402_1%~D
2
PR736
PR736
1M_0402_1%~D
1M_0402_1%~D
1 2
+5V_ALW
8
PU2B
PU2B
5
P
+
O
6
-
G
LM393DR_SO8~D
LM393DR_SO8~D
4
12
PC730
PC730
100P_0402_50V8J~D
100P_0402_50V8J~D
1
sense adapter
PR710
@ PR710
@
0_0402_5%
VCP<37>
12
0_0402_5%
1 2
PU703
PU703
1
Out
REF
2
IN-
GND
3
V+
IN+
INA199A1DCKR_SC70-6~D
INA199A1DCKR_SC70-6~D
6
PR748
PR748
44.2_0402_1%~D
44.2_0402_1%~D
5
4
12
Discrete current monitor circuit
12
PC742
PC742
22U_0805_25V6M
22U_0805_25V6M
+VCHGR
1
2
PR719
PR719
1 2
0_0402_5%
0_0402_5%
@
@
PC722
PC722
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PC715
PC715
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1 2
12
12
12
PC718
PC718
PC717
PC717
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
GNDA_CHG
BQ24715_REGN
12
PR739
PR739
10K_0402_1%~D
10K_0402_1%~D
PR741
@PR741
@
7
1 2
0_0402_5%
0_0402_5%
12
PR744
PR744
10K_0402_1%~D
10K_0402_1%~D
ACAV_IN_NB <37,48>
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
+GPU_CORE
+GPU_CORE
+GPU_CORE
LA-9591P
LA-9591P
LA-9591P
1
PR749
PR749
59_0402_1%
59_0402_1%
CSSN_1
12
CSSP_1
0.3
0.3
47 58Friday, May 17, 2013
47 58Friday, May 17, 2013
47 58Friday, May 17, 2013
0.3
Page 48
5
+BATT_SUM
PR813
PD800
PD800
PDS5100H-13_POWERDI5-3~D
+VCHGR
+3.3V_ALW2
PDS5100H-13_POWERDI5-3~D
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
1
2
3 6
BATDRV#<47>
+DC_IN
ACAV_DOCK_SRC#<34>
+SDC_IN
ACAV_IN<37,47,48>
+3.3V_ALW2
1
PQ800
PQ800
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
1 2
47_0805_5%~D
47_0805_5%~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
PR846
PR846
SOFT_START_GC<41>
1 2
100K_0402_5%~D
100K_0402_5%~D
PR854
@ PR854
@
1 2
0_0402_5%
0_0402_5%
DC_BLOCK_GC<47>
@
@
PR859
PR859
1 2
0_0402_5%
0_0402_5%
@
@
PR862
PR862
1 2
0_0402_5%
0_0402_5%
D D
C C
B B
A A
PR813
100K_0402_5%~D
3
2
PR835
PR835
100K_0402_5%~D
8
7
5
PD811
PD811
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
PQ812A
PQ812A
PBAT_PRES#<36 ,41>
12
PC813
PC813
@
@
PR847
PR847
1 2
ACAVDK_SRCACAVDK_SRC
0_0402_5%
0_0402_5%
PC815
PC815
5
1
SI4835DDY-T1-GE3_SO8~D
SI4835DDY-T1-GE3_SO8~D
1
2
3 6
1 2
12
PR815
PR815
10K_0402_5%~D
10K_0402_5%~D
1 2
61
2
+DC_IN_SS
+CHGR_DC_IN<47>
CD3301_DCIN
ERC1
12
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PD806
PD806
PDS5100H-13_POWERDI5-3~D
PDS5100H-13_POWERDI5-3~D
3
2
PQ809
PQ809
8
7
5
4
+3.3V_ALW2
PR816
PR816
100K_0402_5%~D
100K_0402_5%~D
1 2
3
5
PQ812B
PQ812B
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PR831
PR831
@
@
0_0402_5%
0_0402_5%
1 2
1 2
PR833
PR833
@
@
0_0402_5%
0_0402_5%
PU800
PU800
1
DC_IN
2
SS_GC
3
ERC1
4
ACAVDK_SRC
5
GND
6
SDC_IN
7
DC_BLK_GC
8
ACAVIN
ACAV_IN
9
P33ALW2
P33ALW2
37
TP
CSS_GC<47>
DK_CSS_GC<47>
12
PC816
PC816
0.047U_0603_25V7M
0.047U_0603_25V7M
+PBATT
SLICE_BAT_ON <36,48>
+3.3V_ALW2
+3.3V_ALW
SLICE_BAT_PRES#<34,36,41,48>
CHGVR_DCIN
DK_PWRBAR
DC_IN_SS
DSCHRG_MOSFET_GC
29
30NC31
33
34
35
36
32
NC
GND
DC_IN_SS
DK_PWRBAR
DK_AC_OFF_EN
BLK_MOSFET_GC
CHARGERVR_DCIN
DSCHRG_MOSFET_GC
DK_AC_OFF_EN
BLKNG_MOSFET_GC
SS_DCBLK_GC
CSS_GC10DK_CSS_GC11ERC312ERC213GND14PWR_SRC
EN_DK_PWRBAR17P33ALW
16
15
ERC2
ERC3
EN_DK_PWRBAR
12
STSTART_DCBLOCK_GC
PC817
PC817
@
@
3301_PWRSRC
0.1U_0402_25V4Z~D
0.1U_0402_25V4Z~D
AC_DIS<36,41>
PR832
@ PR832
@
0_0402_5%
0_0402_5%
@
@
PR841
PR841
0_0402_5%
0_0402_5%
@
@
0_0402_5%
0_0402_5%
28
PBatt+
P50ALW
PBATT_OFF
ACAV_IN_NB
SL_BAT_PRES#
NBDK_DCINSS
18
P33ALW
PR838
PR838
GND
PQ811
PQ811
1
2
3 6
@ PR894
@
1 2
0_0402_5%~D
0_0402_5%~D
1 2
@
@
0_0402_5%
0_0402_5%
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
12
12
3301_DSCHRG_FET_GC
12
27
26
25
24
23
22
21
20
19
CD3301BRHHR_QFN36_6X6~D
CD3301BRHHR_QFN36_6X6~D
@
@
PR868
PR868
1 2
0_0402_5%
0_0402_5%
@
@
PR877
PR877
1 2
0_0402_5%
0_0402_5%
+PBATT_IN_SS
FDS6679AZ-G_SO8~D
FDS6679AZ-G_SO8~D
4
PR821
PR821
820_0603_5%~D
820_0603_5%~D
1 2
12
PC811
PC811
0.01U_0603_25V7K~D
0.01U_0603_25V7K~D
PR894
PR895
PR895
100K_0402_5%~D
100K_0402_5%~D
PD820
PD820
1 2
PR828
PR828
1 2
10K_0402_5%~D
10K_0402_5%~D
+DOCK_PWR_BAR
+PBATT
P50ALW
CD_PBATT_OFF
DK_AC_OFF
DK_AC_OFF_ENCD3301_SDC_IN
SL_BAT_PRES#
+3.3V_ALW
PR874
PR874
1 2
1M_0402_5%~D
1M_0402_5%~D
4
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
8
PR817
PR817
1 2
7
330K_0402_5%~D
330K_0402_5%~D
5
SI2301CDS-T1-GE3 1P_SOT23-3
SI2301CDS-T1-GE3 1P_SOT23-3
PR830
PR830
2
G
G
PR843
PR843
@
@
0_0402_5%
0_0402_5%
1 2
@
@
PR850
PR850
1 2
0_0402_5%
0_0402_5%
3301_ACAV_IN_NB
+PWR_SRC_AC
4
PD807
PD807
12
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
3301_DSCHRG_FET_GC
PQ829
PQ829
1
3
1
3
13
2
2
12
2
13
PQ832
PQ832
D
D
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
S
S
+5V_ALW
SLICE_BAT_ON <36,48>
PR855
@ PR855
@
0_0402_5%
0_0402_5%
1 2
1 2
@
@
PR857
PR857
0_0402_5%
0_0402_5%
PR860
PR860
@
@
0_0402_5%
0_0402_5%
1 2
@
@
PR863
PR863
1 2
0_0402_5%
0_0402_5%
13
D
D
S
S
NTR4502PT1G 1P SOT23-3
NTR4502PT1G 1P SOT23-3
PR802
PR802
1 2
12
+3.3V_ALW2
PR804
PR804
61
2
PQ807A
PQ807A
PQ807B
PQ807B
+DOCK_PWR_BAR
PD815
PD815
2
3
BAT54CW_SOT323~D
BAT54CW_SOT323~D
PR858
PR858
1 2
1M_0402_5%~D
1M_0402_5%~D
SLICE_BAT_PRES# <34,36,41,48>
PR866
PR866
@
@
0_0402_5%
0_0402_5%
12
PR856
@ PR856
@
0_0402_5%~D
0_0402_5%~D
2
G
G
@
@
PQ827
PQ827
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
PQ801
PQ801
1
3
1
3
13
2
2
2
12
PR808
PR808
100K_0402_5%~D
100K_0402_5%~D
3
5
SLICE_BAT_PRES# <34,36,41,48>
4
PDS5100H-13_POWERDI5-3~D
PDS5100H-13_POWERDI5-3~D
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PQ813B
PQ813B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
PR848
PR848
@
@
1 2
0_0402_5%~D
0_0402_5%~D
SLICE_PERF_EN<37,48>
1
DOCK_AC_OFF <34>
12
PR844
@ PR844
@
10K_0402_5%~D
10K_0402_5%~D
ACAV_IN_NB <37,47>
DOCK_AC_OFF_EC <36>
EN_DOCK_PWR_BAR <36>
DOCK_DET# <34,36,48>
12
+NBDOCK_DC_IN_SS
PD808
PD808
2
FDS6679AZ-G_SO8~D
FDS6679AZ-G_SO8~D
PQ813A
PQ813A
61
100K_0402_5%~D
100K_0402_5%~D
2
3
PR829
PR829
100K_0402_5%~D
100K_0402_5%~D
5
PR853
PR853
SLICE_BAT_PRES# <34,36,41,48>
@
@
1 2
0_0402_5%
0_0402_5%
1 2
DOCK_DET#<34,36,48>
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
PQ821B
PQ821B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
5
1 2
SLICE_PERF_EN<37,48>
ME2301D-G 1P SOT-23-3
ME2301D-G 1P SOT-23-3
SLICE_PERF_EN<37,48>
3
+PWR_SRC_AC
PC803
PC803
1 2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
PC806
PC806
1 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
PC807
PC807
1 2
0.47U_0805_25V7K~D
0.47U_0805_25V7K~D
36
241
1
578
3
5
123
36
241
PQ815
PQ815
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
PR826
PR826
12
12
+3.3V_ALW2
1 2
100K_0402_5%~D
100K_0402_5%~D
G
G
2
@
@
PR861
PR861
0_0402_5%
0_0402_5%
PQ821A
PQ821A
2
3
100K_0402_5%~D
100K_0402_5%~D
@
@
PR851
PR851
0_0402_5%~D
0_0402_5%~D
DOCK_DET#<34,36,48>
PQ823
@
PQ823
@
3
3
2
2
@
@
PR869
PR869
1 2
240K_0402_5%~D
240K_0402_5%~D
+3.3V_ALW2
3
PQ810
PQ810
FDS6679AZ-G_SO8~D
FDS6679AZ-G_SO8~D
PR814
PR814
330K_0402_5%~D
330K_0402_5%~D
PQ826
PQ826
FDMC6679AZ_MLP8-5
FDMC6679AZ_MLP8-5
4
1500P_0402_7K~D
1500P_0402_7K~D
578
PD813
PD813
2
2
2
PR827
PR827
S
S
PQ828
PQ828
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
D
D
1 3
PR839
PR839
61
100K_0402_5%~D
100K_0402_5%~D
PR849
PR849
12
+3.3V_ALW2
PR852
@ PR852
@
0_0402_5%
0_0402_5%
1 2
1
1
13
2
@
@
PR870
PR870
1 2
47K_0402_5%~D
47K_0402_5%~D
1 2
PR875
@ PR875
@
100K_0402_5%~D
100K_0402_5%~D
PR811
@ PR811
@
12
0_0402_5%
0_0402_5%
STSTART_DCBLOCK_GC
12
@
@
12
PC809
PC809
PR818
PR818
1 2
100K_0402_5%~D
100K_0402_5%~D
12
PR822
PR822
10K_0402_5%~D
10K_0402_5%~D
13
D
D
S
S
PQ816
PQ816
12
AO3418_SOT23-3
AO3418_SOT23-3
13
1
1
PQ814
PQ814
3
3
NTR4502PT1G 1P SOT23-3
NTR4502PT1G 1P SOT23-3
+NBDOCK_DC_IN_SS
12
2
2
2
PR840
PR840
1 2
100K_0402_5%~D
100K_0402_5%~D
+DC_IN_SS
+NBDOCK_DC_IN_SS
PQ824A
PQ824A
@
@
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
61
@
@
2
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
Purpose: Trigger PROCHOT# when
active battery is removed from
system.
Allows EC to re-establish
system performance for battery
next in line.
SLICE_BAT_ON
DIS_BAT_PROCHOT#<36>
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
1 2
PD810
PD810
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
2
G
G
PD814
PD814
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
1 2
PD819
PD819
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
1 2
12
PD816
PD816
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
13
1
1
PQ822
PQ822
NTR4502PT1G 1P SOT23-3
NTR4502PT1G 1P SOT23-3
3
3
12
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
13
1
1
PQ830
PQ830
3
3
NTR4502PT1G_SOT23-3~D
NTR4502PT1G_SOT23-3~D
+PBATT
PQ824B
PQ824B
3
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
+3.3V_ALW
12
PR810
PR810
100K_0402_5%~D
100K_0402_5%~D
3
PQ806B
PQ806B
5
4
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
+3.3V_ALW2
PC810
PC810
PU806
PU806
0.1U_0402_10V7K
0.1U_0402_10V7K
5
1
P
B
4
O
2
A
G
3
+3.3V_ALW2
PU807
PU807
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
4
O
DOCK_SMB_ALERT# <34,36,41>
PD821
PD821
2
2
2
PR837
PR837
100K_0402_5%~D
100K_0402_5%~D
12
PR836
PR836
100K_0402_5%~D
100K_0402_5%~D
2
PC801
PC801
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
SLICE_BAT_PRES#
SLICE_BAT_ON
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
0.1U_0402_10V7K
0.1U_0402_10V7K
PBAT_PRES#
PR812
@ PR812
@
1 2
0_0402_5%
0_0402_5%
PU805
PU805
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
4
12
PR820
@ PR820
@
1 2
ACAV_IN#
0_0402_5%
0_0402_5%
PC812
PC812
0.1U_0402_10V7K
0.1U_0402_10V7K
12
5
1
P
SLICE_BAT_ON <36,48>
B
@ PR825
@
1 2
2
A
G
0_0402_5%
0_0402_5%
3
PQ831
PQ831
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
1 3
12
D
S
D
S
G
G
2
+3.3V_ALW
1
B
2
A
PU801
PU801
+3.3V_ALW
PC805
PC805
1 2
1
2
+3.3V_ALW2
0.1U_0402_10V7K
0.1U_0402_10V7K
5
P
B
O
A
G
3
PR825
+3.3V_ALW2
4
O
5
P
4
O
G
3
5
P
B
4
O
A
G
PU804
PU804
3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
PC808
PC808
12
1
SLICE_BAT_PRES# <34,36,41,48>
1 2
2
100K_0402_5%~D
100K_0402_5%~D
13
D
D
2
G
G
PQ817
PQ817
S
S
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
+3.3V_ALW2
PR823
PR823
100K_0402_5%~D
100K_0402_5%~D
1 2
13
D
D
2
G
G
S
S
PQ818
PQ818
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
PC814
PC814
0.1U_0402_10V7K
0.1U_0402_10V7K
12
5
1
P
SLICE_BAT_PRES# <34,36,41,48>
B
2
A
G
PU808
PU808
3
TC7SH08FU_SSOP5~D
TC7SH08FU_SSOP5~D
61
PQ802A
PQ802A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
2
61
PQ806A
PQ806A
2
PR819
PR819
DOCK_DET# <34,36 ,48>
@
@
PR834
PR834
1 2
0_0402_5%
0_0402_5%
DOCK_DET# <34,36 ,48>
PR801
PR801
100K_0402_5%~D
100K_0402_5%~D
12
+3.3V_ALW
+3.3V_ALW
12
PR807
PR807
100K_0402_5%~D
100K_0402_5%~D
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
5
61
PQ805A
PQ805A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
2
@
@
PD818
PD818
SDMK0340L-7-F_SOD323-2 ~D
SDMK0340L-7-F_SOD323-2 ~D
1 2
Purpose: Turn on the PQ817
for primary or module bay
battery to provide power to
dock side without AC exist.
+3.3V_ALW2
+3.3V_ALW2
Purpose: Turn on the PQ817
for Slice battery discharge
without AC exist
@
@
PR824
PR824
100K_0402_5%~D
100K_0402_5%~D
1 2
3
5
ACAV_IN#
PQ819B
PQ819B
@
@
4
61
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
2
SLICE_PERF_EN <37,48>
@
@
PQ819A
PQ819A
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
SLICE_BAT_PRES# <34,36,41,48>
@
@
PR872
PR872
ACAV_IN<37,47,48>
1 2
0_0402_5%
0_0402_5%
DMN65D8LW-7_SOT323-3~D
DMN65D8LW-7_SOT323-3~D
DELL CONFIDENTI AL/PROPRIETARY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
H_PROCHOT# <37,46,47,9>
3
PQ805B
PQ805B
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D
4
CHARGER_CELL_PIN <47>
+3.3V_ALW2
12
PR864
PR864
100K_0402_5%~D
100K_0402_5%~D
ACAV_IN#
13
D
D
2
G
G
S
S
PQ825
PQ825
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Selector
Selector
Selector
LA-9591P
LA-9591P
LA-9591P
1
0.3
0.3
48 5 8Friday, May 17, 2013
48 5 8Friday, May 17, 2013
48 5 8Friday, May 17, 2013
0.3
Page 49
5
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE
4
3
2
1
D D
C C
B B
1
PC900
PC900
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC905
PC905
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
@
@
PC910
PC910
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC915
PC915
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC920
PC920
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC925
PC925
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
@
@
PC901
PC901
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC906
PC906
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
@
@
PC911
PC911
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC916
PC916
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC921
PC921
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC926
PC926
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
@
@
PC902
PC902
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
@
@
PC907
PC907
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC912
PC912
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC917
PC917
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC922
PC922
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC927
PC927
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC903
PC903
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC908
PC908
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC913
PC913
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
@
@
PC918
PC918
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC923
@
PC923
@
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC928
PC928
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC904
PC904
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC909
PC909
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC914
PC914
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
@
@
PC919
PC919
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
@
@
PC924
PC924
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC929
PC929
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size Documen t Number Rev
Size Documen t Number Rev
Size Documen t Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
PROCESSOR DECOUPLING
LA-9591P
LA-9591P
LA-9591P
49 58Friday, May 17, 2013
49 58Friday, May 17, 2013
49 58Friday, May 17, 2013
1
0.3
0.3
0.3
Page 50
5
R e qu est
R e qu est
Item
Item Issu e D es c ript io n
ItemI te m
P a ge # T it le
P a ge #P ag e #
Title
TitleT itle
D at e
D at eD at e
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
4
V ersio n C hange List ( P . I. R . L ist )
V ersio n C hange List ( P . I. R . L ist )
V ersio n C hange List ( P . I. R . L ist )V ersio n C hange List ( P . I. R . L ist )
Issu e D es c ript io nD at e
Issu e D es c ript io nIssu e D esc r ip tio n
3
Page 1
Page 1
Page 1P ag e 1
2
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io n R e v.
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1
R e v.P a ge #
R e v.R e v.
P45 1.5VSP
1
D D
2
P42 +5V/+3.3V
3
P47 Charger
4
P46 Vcore
5
P48 Selector
P43
6
P42
7
C C
8
P44
1.35V/0.675V 8/17
+5V/+3.3V
+1.05V_MP
+5V/+3.3VP429
B B
10
P47
P48
Charger
Selector
ChargerP4711
12
A A
P46
Vcore
8/17 Compal
8/17 Compal
8/17 Compal
8/17 Compal
8/17 Compal
Compal
10/22
10/22
10/22
10/22
10/22
11/02
Compal
Compal
Compal
Compal
Compal
Compal
Base power budget request, add 1.5V powre rail Add PU400
reserver PR114 for TPS51282 application
schematic control error cause can't set OCP add Vref net for correct connect
in order to meet latest multi-battery request
chagne OCP setting
Reserve 0ohm for 3v5v enable debug
+1.05V_MP EA for ripple portion can't meet
spec. 31.5mv, after change from 1u to 2.2u test is pass
Original 3v5v IC -TPS51225 can't support 2cell battery
follow TI suggestion, When TPS51285A/B is used,
please update the below four components.
1)VREG5 cap to 4.7uF
2)VREG3 cap to 4.7uF
3)CS1 resistor to 1/5 of the Tps51275’s value
4)CS2 resistor to 1/5 of the Tps51275’s value
5)VCLK connection (when not be used): add 200-ohm to GND
To avoid HW and Power SMT materials can't entirely
replace
follow E5- Salado 14"15" schematic 1) @PQ819, @PQ824
follow TI suggestion modify setting value to meet Intel
VR12.6(ULV) validation EA
1) Imon
2) Loadline
3) transient
ADD @PR114
modify SMBus net for correct connectEC can't detect charger IC cause can't charger
change control signal for meet E5 request
change PR201 from 20k to 24.9k.
Change PR113
from SD03420018L (S RES 1/16W 2K +-1% 0402)
to SD028000080 (S RES 1/16W 0 +-5% 0402)
Change PL300
from SH00000PJ00 (S COIL 1UH +-20% PCMB063T-1R0MS 12A)
to SH00000MR00 (S COIL 2.2UH +-20% ETQP3W2R2WFN 8.5A)
Change PU100
from SA00005LS00 (S IC TPS51225CRUKR QFN 20P PWM)
to SA000064T00 (S IC TPS51285BRUKR QFN 20P PWM)
1)2)Change PC118(VREG5 Cap) and PC100(VREG3 Cap)
from SE080105K80(S CER CAP 1U 10V K X5R 0603)
to SE00000MA00(S CER CAP 4.7U 10V K X5R 0603)
3) Change PR106(for CS1)
from SD03484528L (S RES 1/16W 84.5K +-1% 0402)
to SD034169280 (S RES 1/16W 16.9K +-1% 0402)
4) Change PR105(for CS2)
from SD03410038L (S RES 1/16W 100K +-1% 0402)
to SD034200280 (S RES 1/16W 20K +-1% 0402)
5) Add PR114 SD034200080(S RES 1/16W 200 +-1% 0402)
Change PU3,PU801,PU804,PU805,PU806,PU807
from SA74108040L(S IC 74AHC1G08GW SOT353 AND)
to SA00708012L(S IC TC7SH08FU SSOP 5P AND)
2) EMI request for add PL700
SH00000IW00(S COIL 1UH +-20% PCMB042T-1R0MS 4.5A)
1) Change PR501
from SD034422380 (S RES 1/16W 422K +-1% 0402)
to SD034365380 (S RES 1/16W 365K +-1% 0402)
2) Change PR521
from SD000009M80 (S RES 1/16W 2.61K +-1% 0402)
to SD00000WS8L(S RES 1/16W 2.32K +-1% 0402)
3) @PC506 100p_0402 and change PR535
from SD02810028L(S RES 1/16W 10K +-5% 0402)
to SD034487100 (S RES 1/16W 4.87K +-1% 0402 (LF))
X01
X01
X01
X01
X01
X01
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 1
PWR_PIR 1
PWR_PIR 1
LA-9591P
LA-9591P
LA-9591P
50 58Friday, May 17, 2013
50 58Friday, May 17, 2013
50 58Friday, May 17, 2013
1
0.3
0.3
0.3
Page 51
5
R e qu est
R e qu est
Item
Item Issu e D es c ript io n
ItemI te m
D D
C C
P a ge # T it le
P a ge #P ag e #
P47 Charger
13 Compal
14
P42
15
16
17
P47 Charger
P47 Charger 11/05
P44
Title
TitleT itle
+5V/+3.3V
+1.05VTTP
D at e
D at eD at e
11/05
11/05
11/05 X01
11/05
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
4
V ersio n C hange List ( P . I. R . L ist )
V ersio n C hange List ( P . I. R . L ist )
V ersio n C hange List ( P . I. R . L ist )V ersio n C hange List ( P . I. R . L ist )
Issu e D es c ript io nD at e
Issu e D es c ript io nIssu e D esc r ip tio n
1) TI suggestion BQ24715 cell pin pull high 3.3V change
to V_regn(6v) for sequence issue
2) Reserve 0 ohm for debug
Compal
Compal
Compal
Compal
-QAD team
-Huang.Hanks
(PCP)
follow E5- Salado 14"15" schematic
Improve charger efficiency
follow E5- Salado 14"15" schematic
Support QAD WCEPTA analysis, to modify 1.05 OCP Rtrip
resistance to 95K, Cpk value will pass specification.
3
2
Page 1
Page 1
Page 1P ag e 1
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io n R e v.
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1) Change PR711
from SD02800008L (S RES 1/16W 0 +-5% 0402)
to SD034100280 (S RES 1/16W 10K +-1% 0402)
,add PR750 SD028000080(S RES 1/16W 0 +-5% 0402)
2) Add @PR751
1) @PR863, @PR870, @PR869, @PR824, @PR875, @PQ823
2) Add @PR848, @PR851
and add PR834, PR852, PR853, all is
SD028000080(S RES 1/16W 0 +-5% 0402)
3) Add PR874 SD028100480(S RES 1/16W 1M +-5% 0402)
4) Add PD819 SCS0340L01L(S SCH DIO SDMK0340L-7-F SOD-323)
Change PR715
from SD028200A80 (S RES 1/16W 20 +-5% 0402)
to SD013220B80 (S RES 1/10W 2.2 +-5% 0603)
Delete @PR731, @PR733, @PU702
Change PR302
from SD00000H880 (S RES 1/16W 54.9K +-1% 0402)
to SD034953280 (S RES 1/16W 95.3K +-1% 0402 )
1
R e v.P a ge #
R e v.R e v.
X01
X01
X01
X01
18
P48
+5V/+3.3V
1.35V/0.675V
11/05
Compal
- EMC team
Wen. Andy
EMC team suggestion
@PC105, @PC203, @PC301
X01
+1.05V_MP
19
B B
20
P47 Charger
P48
A A
21
P41
SelectorP48
Selector
+DCIN
5
11/15
12/12
2013
/01/11
Compal
Compal
CompalÂESD team
follow E5- Salado 14"15" schematic
for undock shutdown issue
ESD team's PD1 vendor(NXP) proposal PD1 pin 5
connected to the VCC (5V or 3.3V).
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
Add
PQ827 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3),
@PR856 SD028000080 (S RES 1/16W 0 +-5% 0402),
PQ816 SB534020000 (S TR AO3402 1N SOT-23),
PQ828 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3),
PR861 SD028000080 (S RES 1/16W 0 +-5% 0402)
PR802, PR827, PR840 change
from SD028240380 (S RES 1/16W 240K +-5% 0402)
to SD028470280 (S RES 1/16W 47K +-5% 0402),
PR804, PR826, PR839 change
from SD028470280 (S RES 1/16W 47K +-5% 0402),
to SD028240380 (S RES 1/16W 240K +-5% 0402)
Change PR713
from SD034294380 (S RES 1/16W 294K +-1% 0402)
to SD034261380 (S RES 1/16W 261K +-1% 0402)
@PR844
PD1 pin5 connect to +3.3V_ALW
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 2
PWR_PIR 2
PWR_PIR 2
LA-9591P
LA-9591P
LA-9591P
1
X01
X01
X01_2
51 58Friday, May 17, 2013
51 58Friday, May 17, 2013
51 58Friday, May 17, 2013
0.3
0.3
0.3
Page 52
5
R e qu est
R e qu est
P a ge #
Item
Item Issu e D es c ript io n
ItemI te m
D D
P a ge # T it le
P a ge #P ag e #
P48
22
Title
TitleT itle
Selector
D at e
D at eD at e
2013/
01/23
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
4
V ersio n C hange List ( P . I. R . L ist )
V ersio n C hange List ( P . I. R . L ist )
V ersio n C hange List ( P . I. R . L ist )V ersio n C hange List ( P . I. R . L ist )
Issu e D es c ript io nD at e
Issu e D es c ript io nIssu e D esc r ip tio n
Compal
To avoid +DOCK_PWR_BAR leakage voltage when system
only with main battery
3
2
Page 1
Page 1
Page 1P ag e 1
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1). Add PU808
P/N: SA007080120 (S IC TC7SH08FU SSOP 5P AND)
2). Add PQ830
P/N: SB000007900 (S TR NTR4502PT1G 1P SOT23-3)
3). Add PQ831
P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3)
4). Add PD821
P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323)
5). Add PR836, PR837
P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
6). Add PC814
P/N: SE102104K00 (S CER CAP 0.1U 10V +-10% X7R 0402)
1
R e v.
R e v.
R e v.R e v.
X01_2
23
24
25
P41
P48
P41
C C
B B
+DCIN
Selector
+DCIN
2013
/02/07
2013/
02/18
2013/
Compal
Compal
Compal-ME
02/18
26
Selector
2013/
CompalP48
PPM-Jovins_Chang and Sourcer-Willie_Zeng highlight
SB000009N8L will shortage after 2013/05
GPIO net - AC_DIS# is high active. Corrent net name.
AC_DIS circuit modify to improve output voltage level.
DFX highlight Battery connetor(locattion:PBATT1)
hard to insert.
layout spec limit
02/18
27
P46
P48
Vcore
Selector
2013/
02/18
CompalÂESD team
Add snubber component by ESD team request
Hsu. Matt
Change PQ6
From : SB000009N8L (S TR IMD2AT-108 PNP/NPN SC74-62)
To : SB000009P80 (TR DCX124EK-7-F PNP/NPN SC74R-6)
1). Change PQ6A.5 and PR828.1 net name from AC_DIS#
to AC_DIS
2). Add PQ829
P/N: SB00000H500 (S TR SI2301CDS-T1-GE3 1P SOT23-3)
, PQ832
P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3)
, PD820
P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323)
, @PR894
, PR895
P/N: SD028000080 (S RES 1/16W 0 +-5% 0402)
3). modify PR828,PR830
4). Delete PQ820
5). Delete PL5, add PJP1
Battery connetor(locattion:PBATT1) footprint follow
ME team Iris requesti to change
from SUYIN_200277GR009M262ZR_9P-T
to ALLTO_C144LS-109A9-L_9P-T
Delete PD817, modify PD815 footprint same as PD701,
from SDMK0340L-7-F_SOD323-2
to RB717F_SOT323-3
Add
PC508, PC714
P/N:SE025821K80 (S CER CAP 820P 50V K X7R 0603)
PR522, PR724
P/N:SD001470B80 (S RES 1/4W 4.7 +-5% 1206 )
X02
X02
X02
X02
X02
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 3
PWR_PIR 3
PWR_PIR 3
LA-9431P
LA-9431P
LA-9431P
52 58Friday, May 17, 2013
52 58Friday, May 17, 2013
52 58Friday, May 17, 2013
1
0.3
0.3
0.3
Page 53
5
R e qu est
R e qu est
P a ge #
Item
Item Issu e D es c ript io n
ItemI te m
D D
P a ge # T it le
P a ge #P ag e #
P48
28
Title
TitleT itle
Selector
D at e
D at eD at e
2013/
02/21
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
4
V ersio n C hange List ( P . I. R . L ist )
V ersio n C hange List ( P . I. R . L ist )
V ersio n C hange List ( P . I. R . L ist )V ersio n C hange List ( P . I. R . L ist )
Issu e D es c ript io nD at e
Issu e D es c ript io nIssu e D esc r ip tio n
Compal
follow E5- Salado 14"15" schematic
3
1) For Input current sense stablilze
2) To provent charger into sleep mode dual
AC transient.
3) Fine tune ACOK response time.
4) Adapter protect rating setting
Page 1
Page 1
Page 1P ag e 1
1). Change PC703 from 0.1U to 1U
P/N: SE000006900 (S CER CAP 1UF 25V K X5R 0603)
2). Change PC706 from 1U to 0.1U
P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25)
3). Change PC708 from 0.01U to 10U
P/N: SE00000G880 (S CER CAP 0.1U 25V K X5R 0402)
4). Change PR734 from 100K ohm to 210K ohm
P/N: SD034210380 (S RES 1/16W 210K +-1% 0402)
Change PR735 from 46.4K ohm to 69.8K ohm
P/N: SD034698280 (S RES 1/16W 69.8K +-1% 0402)
2
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1
R e v.
R e v.
R e v.R e v.
X02
5) Fine tune H_PROCHOT# response time.
6) Improve ACAV_IN_NB ref voltage accuracy.
C C
29
P46
Vcore
2013/
02/26
CompalÂESD team
7) Improve current sense accuracy.
Add 22U_0805 by ESD team request
Hsu. Matt
B B
30
P48
Selector
2013/
Compal
02/27
31
P47
Charger
2013/
Compal
03/18
32
P42
P43
P44
33
A A
P46
+5V/+3.3V
1.35V/0.675V
+1.05V_MP
Vcore
5
03/20
2013/
03/21
Compal2013/
Compal
Modify resistor value to meet voltage
tolerence
follow E5- Salado 14"15" schematic to
add charger input MLCC to 88u
support DFX team change choke layout pad
to avoid soldering issue
Support acoustic team to reduce noise
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
5). Add @PC740
6). Change PR738.pin1 from BQ24715_REGN connect to +3.3V_ALW2.
Change PR738 from 118K ohm to 48.7K ohm
P/N: SD034487280 (S RES 1/16W 48.7K +1% 0402)
Change PR744 from 12K ohm to 10K ohm
P/N: SD034100280 (S RES 1/16W 10K +-1%
7). Change PR748 from 6.8 ohm to 210K ohm
P/N: SD034442A80 (S RES 1/16W 44.2 +-1% 0402)
Change PR749 from 10 ohm to 69.8K ohm
P/N: SD00000W200 (S RES 1/16W 59 +-1% 0402)
53 58Friday, May 17, 2013
53 58Friday, May 17, 2013
53 58Friday, May 17, 2013
X02
X02
X02_1
X02_1
X02_1
Change PC732, PC736 from 10U to 22U
from
P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25)
to
P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
1). Change PR802,PR827,PR840 from 47K ohm to 100K
P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
2). Change PR804,PR826,PR839 from 240K to 100K
P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
1). Add PC741, PC742
P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
2). Due to space limit, so delete @PC701, @PC702,
@PC710
1). Change PL101, PL102, PL200, PL300 PCB FootPrint
change
from CYNTE_PCMC063T-2R2MN_2P
to CYNTE_PCMB064T-3R3MS_2P
3). Change PC738
from 33U(SGA00005M00) to 100U
P/N: SGA00008R00 (S POLY C 100U 20V M D ESR55M
(D3L_H=2.8mm)
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PWR_PIR 4
PWR_PIR 4
PWR_PIR 4
LA-9431P
LA-9431P
LA-9431P
1
0.3
0.3
0.3
Page 54
5
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )V ersion C han ge L ist ( P. I . R . L ist )
R e qu est
R e qu est
Title
Item
ItemI te m
D D
C C
10 39 +1.05V_MODPHY can't meet INTEL timing spec change +1.05V_MODPHY to MOS solutionCOMPALHW 11/12/2012 0.2(X01)
11 HW18 19 11/12/2012 COMPAL Remove DIMM VERF power rail from power side Remove RD2, RD4, RD8 and RD9 0.2(X01)
13 HW COMPAL26 refer salado 14" to change PCBEEP circuit remove C132,C146,R146,R138,C133 and C143 than add C145,C146,R147,R151
14 HW COMPAL26 If doesn't has external power, Sleeve will
15 HW COMPAL37 11/12/2012 Change board ID to X01 change R392 form 240K to 130Kohm 0.2(X01)
16 HW COMPAL21 11/12/2012 Vendor update schematic for power saving
B B
17 COMPAL21 HW 11/12/2012 change VMM2320 config remove DP to VGA PTN3392 circuit and add 0ohm pop option for 2320 config 0.2(X01)
20 0.2(X01)
21
A A
P a ge # R e v.
P a ge #P ag e #
26,34
3 HW COMPAL 0.2(X01)37 11/05/2012 Based on align E5,P5 Fan module pin define Swap JFAN1 pin define
26
1919 change RC68, RC126 and RC173 from 2.2 to 2ohm 1%
,38,40
TitleP a ge#
TitleT itle
ESD 11/05/20121 ESD team request22,40,38
Safty2 COMPAL 0.2(X01)27 11/05/2012 Safty team request Pop F2 and reserve R160
HW4 22,40,38
HW COMPAL26 Remove EMI solution at Speaker side Remove R132, R133, R134 and R1356 11/09/2012 0.2(X01)
HW COMPAL37,36,12 11/13/2012 GPIO map update to 2.7 version Move EC_WAKE# from ECE5048[L]5 to MEC5075 GPIO52.
D at e
D at e Issu e D es c ript io n
D at eD at e
11/06/2012 To avoid PT phase occurs ESD issue and
11/12/2012 0.2(X01)
11/13/2012HW COMPAL18 Add Mic power and remove DBC function22 Add 3.3V_RUN for Mic power and remove DBC function at JeDP.2 0.2(X01)
11/13/2012HW COMPAL 0.2(X01)
11/13/2012 change JmDP1,JNFC1,JMEDIA,JKBTP1,JUSH1ME change connectorCOMPALME 0.2(X01)20,27,29
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
COMPAL 0.2(X01)Remove D3,D27,D22,DE1,DE2
COMPAL Reserve D3,D27,D22,DE1,DE2 0.2(X01)
DELL DELL drop ALS function Remove ALS interface from EC and CPU side than move touch screen
COMPAL change Webcam power enable from PCH pop R106 and de-pop R102HW 11/09/2012228 0.2(X01)
COMPAL Schmatic error and remove eDP backlight
COMPAL12 HW remove D10 R160 F2 and add U50 de-pop C383change miniDP OCP solution 27 11/12/2012 0.2(X01)
4
Issu e D es c ript io nItem
Issu e D es c ript io nIssu e D esc r ip tio n
change back ESD request
DELL drop Media LED function Remove backlight LED function and change connector to 6pin40 36 DELLHW 11/08/20125 0.2(X01)
control pull up resistor
be floating mode and no reference GND.
refer PDG1.0 to change SODIMM control
circuit resistor
3
Reserve D20
signal to eDP side
Remove RC150 0.2(X01)HW9 10 11/09/2012
and de-pop R194 R153
Add AUD_NB_MUTE# to control Sleeve pin.11/12/2012 0.2(X01)
change +1.05V_RUN_VMM power enable signal from LP_EN to DOCKED and add
+3.3V_RUN_VMM for DP2320 series 3.3V power rail
remove L3 and move U6.E5 to +1.05V_VMM_VDD power rail
change U6.J4 to +3.3V_RUN_VDDA
R85 change to 3.74K_1%
remove LP_EN, R232 and U6A.A5 to NC
remove R55 and pop-option R207 when use VMM2310
change RC67,RC69,RC130,RC132,RC217 and RC221 from 1.82K to 1.8Kohm 1%
Change name: 1.5V_SUS_PWRGD to 1.35V_SUS_PWRGD for DDR3L.
Add NFC_DET# ECE5048 GPIOL[5] to NFC moudle & add R38 PU
align AUX/DDC SW voltage with DP Hub to +3.3V_RUN_VMMVendor update schematic for power savingCOMPAL11/14/2012HW2422 0.2(X01)
2
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1
R e v.So lu tio n D esc r ipt io n
R e v.R e v.
0.2(X01)HW12,22,37 11/09/20127
0.2(X01)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (1/6)
EE P.I.R (1/6)
EE P.I.R (1/6)
LA-9431P
LA-9431P
LA-9431P
54 59Friday, May 17, 2013
54 59Friday, May 17, 2013
54 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 55
5
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )V ersion C han ge L ist ( P. I . R . L ist )
R e qu est
R e qu est
Title
Item
ItemI te m
D D
24 HW 11/15/201212 Pop RC301 to link LAN_WAKE# and EC_WAKE#Add LAN_WAKE# T-topology COMPAL 0.2(X01)
30 HW COMPAL22 11/15/2012 change LCDVDD power control circuit change U9 from TPS22966 to APL3512 solution 0.2(X01)
31 HW COMPAL31,32 11/15/2012 remove TPS22965 solution remove U51(TPS22965) and U34(TPS22965) than add U3(TPS22966) 0.2(X01)
32 10,27 HW 11/15/2012 COMPAL ESD solution for black screen issue Add CC450 on EDP_CPU_HPD to GND and C451 on DPC_HPD to GND 0.2(X01)
C C
33 40 ME 11/16/2012 COMPAL ME change drawing Add H18 and H10,H11 change size from 2.3 to 3.4 ,
35 ME COMPAL40 11/16/2012 ME request change SW1 to SKRBAAE010 0.2(X01)
B B
42 COMPALHW37 11/19/2012 change thermal OTP to 98 degree change R394 from 1.24K to 1.82K_1% 0.2(X01)
43 31 HW 11/20/2012 COMPAL Intel notice remove HDD_DEVSLP function on
44 28 HW 11/20/2012 COMPAL LOM LED issue reverse Q32,Q33 of C & D gate 0.2(X01)
45 22 HW 11/20/2012 COMPAL 0.2(X01)ME change connector change JLED1
47 15 HW 11/22/2012 COMPAL Per Intel CRB updated change VCCST_PWRGD pull high value from 10K ohm to 1K ohm 0.2(X01)
P a ge # R e v.
P a ge #P ag e #
31,39
TitleP a ge#
TitleT itle
HW 11/15/201223 update SATA topology fro Mainstream CPU 2,3,6,34 COMPAL 0.2(X01)exchange SATA1&SATA2 topology
HW COMPAL11/15/20121525 change RC252 to PJP11(1mm jumper-short)remove RC252 for cost saving 0.2(X01)
HW26 16 11/15/2012 INTEL MOW_WW46 request change for VCCUSB3PLL and
HW34 COMPAL remove D4,D5,D6,D7 and add D10,D21change diode to daul-diode fro cost saving11/16/201222 0.2(X01)
HW40 COMPAL Change JAPS1.11 net name from SIO_PWRBTN# to POWER_SW#_MBchange APS pin 11 net_name for DELL APS debug11/19/20129 0.2(X01)
HW COMPAL41 support TLS confidentility 11/19/201212,28
HW3546 COMPAL11/21/2012 change L54 pat to DLW21SN900SQ2L that same with L42, L39Align EMI part 0.2(X01)
D at e
D at e Issu e D es c ript io n
D at eD at e
11/15/201238,12 remove U40, R458,C424 and C423remove +3.3V_TP power load switch solutionCOMPALHW29 0.2(X01)
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
COMPAL27 Change U20, U26, U29 and U30 from SA74108040L to SA00708012L change AND gate to same source11/15/2012HW20,28,30,31 0.2(X01)
COMPAL34 11/15/2012 ME change Docking connector change JDOCK1 that Pin145 from PWR1 to GND1 & Pin148 from PWR2 to GND228 ME 0.2(X01)
COMPALHW37 Add PJP12~25 for +1.05V_RUN_VMM,+3.3V_RUN_VMM,+3.3V_ALW_PCH,+1.05V_RUN,
COMPALHW38 change Q11,Q13 and Q14 form SB000008P0L to SB33904510Lchange thermal diode for cost saving11/19/201237 0.2(X01)
COMPALHW39 11/19/201238,26,30,22
4
Issu e D es c ript io nItem
Issu e D es c ript io nIssu e D esc r ip tio n
VCCSATA3PLL
For EA rework request11/16/201221,26,28,
change Bead for cost reduce
WWAN JMINI port
3
change CC42 and CC49 from 1u_0402 to 22u_0603
change CC76 and CC77 from 100u_1206 to 22u_0603
H5 change size from 2.8 to 2.3
change SD1ME change connectorCOMPAL11/16/2012ME3036 0.2(X01)
+3.3V_SUS,+3.3V_M,+5V_RUN,+3.3V_RUN,+3.3V_LAN,+3.3V_mSATA_WWAN,+3.3V_HDD
,+3.3V_WLAN,+5V_RUN_AUDIO,+3.3V_RUN_AUDIO
change L44 and L45 from SM01000558L to SM01000C500
change L35 and L36 from SM01000AM0L to SM01000C500
change LE1 from SM01000DH0L to SM01000BV00
change L21 from SM01001788L to SM010005N00
change net name from HOST_ALERT1_R_N to PCH_GPIO15, and pop RC190
remove R188
remove HDD_DEVSLP from JMINI2.44
de pop HDD_DEVSLP pull up resistor R155
2
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1
R e v.So lu tio n D esc r ipt io n
R e v.R e v.
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
A A
49 6,12,25,31 HW 11/26/2012 DELL For support DEVSLP on WWAN JMINI2 & mSATA
5
JMINI3
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
SATA HDD change from port0 to port1, and connect HDD_DEVSLP
Dock change from port1 to port2, and connect mSATA_DEVSLP
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (2/6)
EE P.I.R (2/6)
EE P.I.R (2/6)
LA-9431P
LA-9431P
LA-9431P
1
0.2(X01)48 26 HW 11/22/2012 COMPAL Universal Jack no longer supported on X5 Remove D9,D11,R209,R210,C195,C196,R198,R199
0.2(X01)
55 59Friday, May 17, 2013
55 59Friday, May 17, 2013
55 59Friday, May 17, 2013
0.3
0.3
0.3
Page 56
5
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )V ersion C han ge L ist ( P. I . R . L ist )
R e qu est
R e qu est
Title
Item
ItemI te m
D D
51 31 HW 11/26/2012 COMPAL change WWAN power control signal Change U3.5 from 3.3_1.5V_WLAN_E to SIO_SLP_WLAN# 0.2(X01)
P a ge # R e v.
P a ge #P ag e #
TitleP a ge#
TitleT itle
HW 11/26/201250 change Bead for cost reduce21,26 COMPAL 0.2(X01)L6 and L7 from SM01000GG0L to BLM15PX471SN1D(SM01000M700)
D at e
D at e Issu e D es c ript io n
D at eD at e
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
4
Issu e D es c ript io nItem
Issu e D es c ript io nIssu e D esc r ip tio n
3
L22, L23, L24 and L25 from SM010028800 to BLM15PX121SN1D(SM01000L300)
2
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1
R e v.So lu tio n D esc r ipt io n
R e v.R e v.
52 NFC_DET# change to PCH side GPIO5912,36 HW 11/27/2012 COMPAL UC1.AT5 change from PCH_GPIO59 to NFC_DET#
53 HW 11/27/2012 COMPAL 0.2(X01)Remove ESD reserve location Per ESD experiment, D3,D27,D22,DE1,DE2 can be remove22,26,38,40
54 33 HW 11/27/2012 COMPAL Per USB2.0 EA result Change U42 from SM01002080L(DLW21SN900SQ2L) to SM070001600(OCE2012120YZF)0.2(X01)
55 6,12,25,31 HW 11/27/2012 DELL Per Dell requset, only JMINI3(mSATA )
31
57
C C
58 34 HW 11/28/2012 COMPAL For EMI request, change to 33 ohm for
59 21 HW 11/28/2012 COMPAL For use IDT2320, need change EEPROM PN U7 change from SA00003FL10(W25X10BVSNIG) to SA00006HH00(W25X10CLSNIG) 0.2(X01)
60 HW 11/28/2012 COMPAL22 change Bead for cost reduce LE1 change from SM01000DH0L(BLM18BB221SN1D)to SM01000BV00(BLM15BB221SN1D)0.2(X01)
61 6,25,31 HW DELL11/29/2012 To support mainstream and Premium CPU,
62 12,31,34 HW 11/29/2012 DELL To support the SATA DevSLP function for
63 33 HW 01/10/2013 COMPAL For USB3.0 EA result L37 & L38 change to SM070000S80(S COM FI_ CHENG HANN WCM2012F2SF-670T04) 0.3(X02)
64 40 HW 01/10/2013 COMPAL For ME team force test result SW1 change to SN111005800(S TACK SW BCL31 SKRBAAE010 SPST) 0.3(X02)
B B
65 9 HW 01/17/2013 COMPAL PCH_RSMRST#_R add RC136 10K pull dowm 0.3(X02)For U42 2nd source (MC74VHC1G08DFT2G)can't
66 28 HW 01/17/2013 COMPAL For meet INTEL LAN SPEC Y3 change to SJ10000JC00(S CRYSTAL 25MHZ 18PF +-30PPM 7V25000034) 0.3(X02)
28 HW 11/28/2012 COMPAL change +3.3V_mSATA_WWAN control from WWAN_mSATA_EN to MCARD_WWAN_PWRENchange +3.3V_mSATA_WWAN control 0.2(X01)
HW 11/28/2012 COMPAL change +3.3V_WLAN PWR control from SIO_SLP_WLAN# to AUX_EN_WOWLchange +3.3V_WLAN PWR control 0.2(X01)56
support DEVSLP
docking DVI noise
change to SATA port assignment.
new SATA port assignment.
boot issue
U37.B1 change to NC
SATA HDD use port0 ,Dock use port1 0.2(X01)
R252/R253/R254/R255/R256/R257/R258/R259/R260/
R261/R262/R263/R264/R265/R266/R267 change to 33ohm from 0 ohm
SATA HDD change from port0 to port1, and connect HDD_DEVSLP
Dock change from port1 to port0, and connect mSATA_DEVSLP
Change DEVSLP0/GPIO33 to mSATA_DEVSLP
and DEVSLP1 to HDD_DEVSLP
0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
67 HW 01/17/2013 COMPAL For trial run U9 2nd source U9 pin 4 & pin5 connect to +3.3V_ALW 0.3(X02)22
1.change R435 from 1.8k to 150(SD028150080)
2.R430/R438/R436 from 2.2k to 150(SD028150080)
68 HW 01/17/2013 COMPAL40 For LED light test result
69 HW 01/17/2013 COMPAL For prevent EDP pin shift then cause
A A
22
broken issue
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
3.R434 change from 220 to 150(SD028150080)
4.R427 change from 1K to 150 ohm(SD028150080)
5.R429 change from 620 to 330 ohm(SD028330080)
6.R431/R433 change from 330 to150 ohm(SD028150080)
1. modify JEDP1 pin assignment
2. pin 29 (IO_LOOP) add 1k pull down
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EE P.I.R (3/6)
EE P.I.R (3/6)
EE P.I.R (3/6)
LA-9431P
LA-9431P
LA-9431P
56 59Friday, May 17, 2013
56 59Friday, May 17, 2013
56 59Friday, May 17, 2013
1
0.3(X02)
0.3(X02)
0.3
0.3
0.3
Page 57
5
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )V ersion C han ge L ist ( P. I . R . L ist )
R e qu est
R e qu est
Title
Item
ItemI te m
D D
71 37 HW 12/07/2012 COMPAL Change Board ID for ST R392 change to 33K ohm from 130k ohm 0.3(X02)
72 HW 02/19/2012 COMPAL Change connector tyoe
P a ge # R e v.
P a ge #P ag e #
TitleP a ge#
TitleT itle
HW 12/05/201270 For Audio Presison result25,26 COMPAL
D at e
D at e Issu e D es c ript io n
D at eD at e
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
4
Issu e D es c ript io nItem
Issu e D es c ript io nIssu e D esc r ip tio n
3
1.L22/L23/L24/L25 change to SM010019400 from SM01000L300
2.L51/L52 change to SM01000FV00 from SM01000AM0L
3.Delete L50/L53 & add R491/R492 0 ohm-short
1. JNFC1 change to 6718K-Y15N-01L
2. JKBTP1 change to 6718K-Y16N-01L
3. JUSH1 change to 6718K-Y20N-00L
4. JUSB3 change to PUBAUE-09FLBS1FF4H0
5.JMEDIA change to 6718K-Y06N-01L
6. SH1 change to 6718K-Y12N-01L
2
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1
R e v.So lu tio n D esc r ipt io n
R e v.R e v.
0.3(X02)
0.3(X02)
73 37 HW 02/21/2012 COMPAL For OTP issue, & change OTP to 96 degree
C C
74 7 HW 02/21/2012 COMPAL change JTAA1 connector type JTAA1 change to PANAS_AXK820145WG from ACES_50185-02041-001 0.3(X02)
75 38 HW 02/21/2012 COMPAL Per EMI Test result Remove L44 & L45 0.3(X02)
3876 HW 02/21/2012 COMPAL Per ESD Test result 0.3(X02)Pop C141 & C142 & C143
77 9 HW 02/21/2012 COMPAL change XDP circuit to XDP@add XDP@ for XDP component 0.3(X02)
78 9 HW 02/21/2012 COMPAL update XDP circuit for INTEL ITE can't boot remove RC121 and pop RC102 0.3(X02)
79 9,11,35 HW 02/21/2012 COMPAL Fixed 2 USB Port use the same OC# signal
80 9,11,35 HW 02/21/2012 COMPAL Add jumper for clock buffer co-layout add PJP26, PJP27 and PJP28 beween UC5 0.3(X02)
B B
82 33 HW 02/22/2013 COMPAL
83 For LID & AOAC S3 wake up issue9,12 HW 02/25/2013 COMPAL Change Net name to SIO_EXT_SMI# from USB_OC3# and change to
A A
from 98 degree
issue
Per EMI test result
Per ESD test result
1. Q11/Q13/Q14 change to SB000008P00(S TR MMBT3904WT1G NPN SC70-3)
from SB33904510L(S TR PMST3904 NPN SOT323-3)
2. R394 chagne to SD00000SJ80(S RES 1/16W 1.58K +-1% 0402) from
SD034182180(S RES 1/16W 1.82K +-1% 0402)
1.change JUSB3 OC# from USB_OC0# to USB_OC1#
2.change USB_OC1#/3# to USB_OC1#, USB_OC3# and add RC166 for OC1# pull
up resistor
1.L42 change to SM070003N00(CHILISIN CMM0805-20Y-N)from SM070001600(
SUPERWORLD OCE2012120YZF)
2.L37/L38 change to SM070001R00(MURATA DLW21SN670HQ2L)
from SM070001E0L(MURATA DLW21SN900HQ2L)
3.L8/L39/L54 change to SM070001N00(MURATA DLW21HN900SQ2L)from
SM01002080L(MURATA DLW21SN900SQ2L)
1. Pop CC71 & CC72 & CC73
2. Add C452 & C453 & C454(@) 22uF 0603 size
3. R338 & R349 & R352 change to 10k ohm from 1k ohm
4. Add C455 & C456 & C457 0.1UF
PCH_GPIO45 from SIO_EXT_SMI#
0.3(X02)
0.3(X02)
0.3(X02)HW3381 COMPAL02/21/2013
0.3(X02)
0.3(X02)
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (4/6)
EE P.I.R (4/6)
EE P.I.R (4/6)
LA-9431P
LA-9431P
LA-9431P
57 59Friday, May 17, 2013
57 59Friday, May 17, 2013
57 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 58
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V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )V ersion C han ge L ist ( P. I . R . L ist )
R e qu est
R e qu est
Title
Item
ItemI te m
D D
P a ge # R e v.
P a ge #P ag e #
TitleP a ge#
TitleT itle
HW 02/25/201384 add RF noise solution at clock buffer7 COMPAL 0.3(X02)
D at e
D at e Issu e D es c ript io n
D at eD at e
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
4
Issu e D es c ript io nItem
Issu e D es c ript io nIssu e D esc r ip tio n
3
1. add CC86~CC90 between clock signal
2. add RC62 for UC5 power rail
3. change RC100 from 0ohm short to 10ohm
4. change UC5 from IDT_5V60034DCG8 to CYPRESS_CY2304SXI-1T
2
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1
R e v.So lu tio n D esc r ipt io n
R e v.R e v.
85 23 HW 02/25/2013 COMPAL refer INTEL MOW to upfate HDMI cost reduce
86 33 HW 02/25/2013 COMPAL change USB charge solution for SAMSUNG phone change U39 from SA00004VH00 to SA00006L600 0.3(X02)
COMPAL02/27/2013HW2687 change R154 from PCH_AUDIO_EN to RUN_ONfor Fixed BIOS fliah HOTSOS issue 0.3(X02)
02/28/2013 COMPAL88 9 HW For ESD request Add CC149(@) on H_PROCHOT# near CPU side 0.3(X02)
02/28/2013 COMPAL89 9 HW Follow INTEL CRB XDP schematic CC68 change to 0.1uF from 0.01uF 0.3(X02)
90 7 02/28/2013 COMPALHW For RF 24MHz issue 1. remove UC5 CC25,CC57,CC80,CC86~CC90,CC22,RC62,RC100,CC23
C C
91 9 02/28/2013 COMPALHW For Touch panel issue 1.TOUCH_PANEL_INTR# add RC181(@) PU & RC180 PD 0.3(X02)
92 7,29 HW 03/01/2013 COMPAL refer GPIO3.0 to add PCH_TPM_LPC_EN 0.3(X02)1. add RC56 for pull up enable signal and add R198 for pop option
93 7 03/12/2013 COMPALHW Base on INTEL EDS SPEC Update Rev 1.5.1 1. LANCLK_REQ# change to UC1.AD1 from UC1.Y5
94 7 HW 03/14/2013 COMPAL For PCIE CLK & PCIE CLK REQ signal mapping 1. CLK_PCIE_LAN change CLKOUT_PCIE port2
B B
level shifter main link
with SD card inserted incompletely issue.
change R462~R469 resistor from 680(SD034680080) to 470ohm(SD034470080) 0.3(X02)
2. Change RC65 to 0 ohm-short
2. change R193 form 0hm to 10ohm
2. MINI1CLK_REQ# change to UC1.T2 from UC1.U2
3. MINI2CLK_REQ# change to UC1.N1 from UC1.T2
4. MMICLK_REQ# change to UC1.U5 from UC1.AD1
5. PCH_TPM_LPC_EN change to UC1.Y5 from UC1.U5
2. CLK_PCIE_MINI2 change CLKOUT_PCIE port3
3. CLK_PCIE_MMI change CLKOUT_PCIE port4
4. CLK_PCIE_MINI1 change CLKOUT_PCIE port5
1. SD/MMCCD# add C256(0.1uF) & R493(1M) pull-down to GND
2. C222 change to 1uF(SE000000K80) from 0.1u(SE00000G880)
0.3(X02)
0.4(X02)
0.4(X02)
0.4(X02)95 30 HW 03/14/2013 COMPAL For O2 enters into test mode unexpectedly
96 21 HW 03/15/2013 COMPAL For Synaptics vender request 1. Delete VMM2310 co-lay related schematic 0.4(X02)
97 21 HW 03/15/2013 COMPAL For ESD request 1. Add C458(@) &C459(@) &C460(@) &C461(@) 22uF 0603 size 0.4(X02)
98 7 HW 03/18/2013 COMPAL For INTEL request PCIECLK_REQ0# add RC57(10k) pull-high to+3.3V_RUN 0.4(X02)
99 21 HW 03/20/2013 COMPAL For Synaptics vender request 1. Delete R78/R80/R82
100 21 HW 03/20/2013 COMPAL For ME request 0.4(X02)ST2 change to H_2P8 from CLIP_C5P1
101 9, 12, 15 HW 03/22/2013 COMPAL For ESD request 1. H_CPUPWRGD add CC90 100pF(@) to GND
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2. add C132
2. H_THERMTRIP# add CC91 100pF(@) to GND
3. H_VCCST_PWRGD add CC22 100pF(@) to GND
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (5/6)
EE P.I.R (5/6)
EE P.I.R (5/6)
LA-9431P
LA-9431P
LA-9431P
1
0.4(X02)
0.4(X02)
58 59Friday, May 17, 2013
58 59Friday, May 17, 2013
58 59Friday, May 17, 2013
0.3
0.3
0.3
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V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )
V ersion C han ge L ist ( P. I . R . L ist )V ersion C han ge L ist ( P. I . R . L ist )
R e qu est
R e qu est
Title
Item
ItemI te m
D D
102 9 HW 03/27/2013 COMPAL For Touch panel issue pop RC181 and depop RC180(@) 0.4(X02)
P a ge # R e v.
P a ge #P ag e #
TitleP a ge#
TitleT itle
D at e
D at e Issu e D es c ript io n
D at eD at e
R e qu estReq u est
O w ner
O w ner
O w nerO wn e r
4
Issu e D es c ript io nItem
Issu e D es c ript io nIssu e D esc r ip tio n
3
2
So lu tio n D esc r ipt io n
So lu tio n D esc r ipt io nSo lu tio n D esc r ipt io n
1
R e v.So lu tio n D esc r ipt io n
R e v.R e v.
103 9 HW 03/27/2013 COMPAL
104 32 HW 04/24/2013 COMPAL For USB S3 wake up issue U33 power rail change from +3.3V_RUN to +3.3V_SUS 1.0(A00)
105
106 37 HW 04/25/2013 COMPAL Change Board ID for A00 R392 change from33K ohm to 1K ohm 1.0(A00)
108 28 HW 04/25/2013 COMPAL for support Vpro reset pin depop U20 and add R145
109 12 HW 04/25/2013 COMPAL reserve for support non vpro pop option pin reserve RC292 100 ohm pull down 1.0(A00)
C C
110 COMPALHW 05/13/2013 For Crystal EA result & RTC time fail issue 1. CC1 & CC2 change from 18pF to 15pF 1.0(A00)6
111 16 HW 05/17/2013 COMPAL For ESD request Depop CC71/CC72/CC73 1.0(A00)
B B
9 04/24/2013 For XDP signal should be contact to PCH change RC97 and RC135 to 0ohm short
40
HW
HW COMPAL107
COMPAL
04/25/2013
For XDP SPEC
For LED EA
pop RC97 & RC135 0.4(X02)
1.0(A00)
R436 change from150 ohm to 330 ohm;R438 change from 150 ohm to 220 ohm
1.0(A00)
1.0(A00)
A A
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
EE P.I.R (6/6)
EE P.I.R (6/6)
EE P.I.R (6/6)
LA-9431P
LA-9431P
LA-9431P
59 59Friday, May 17, 2013
59 59Friday, May 17, 2013
59 59Friday, May 17, 2013
1
0.3
0.3
0.3
Page 60
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