Compal LA-9371P Afterburn MXM, ZBook 17 Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

Intel Haswell rPGA Processor with Lynx Point-H

Afterburn MXM

LA-9371P

3 3

2012-09-28

REV : 0.2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-9371P

E

0.2

1 53Friday, September 28, 2012

0.2

A

B

C

D

E

Compal Confidential

Model Name : Afterburn

File Name : LA-9371P

1 1

Ch B

DDR3-SO-DIMM2, 3

BANK 0, 1, 2, 3

Page 12

eDP Panel Conn.

P Switch

D PI3VDP124

Dock Conn DPD

Page 33

DP Conn

2 2

3 3

daughter board

sub/B Page 6

Mini DP Conn.

sub/B Page 4

daughter board

Port 8

Card Reader

Realtek RTS5237

LS-9373P Page 4

SD/MMC Slot

LS-9373P Page 4

Dock Conn

Page 33

GLAN Intel Clarkville

Page 29

Lan Switch PI3L500

Page 29

ThunderBolt Cactus Ridge

sub/B Page 2,3,4

X4

Port 3,4

daughter board

RJ45 Conn.

Page 29

Port 5Port 6

Expresscard

sub/B Page 7

Super I/O

Port 6

SMSC LPC47N217

Accelerometer ST HP3DC2

Page 28

FAN conn.

Page 24

4 4

RTC CKT.

Power On/Off CKT.

DC/DC interface CKT.

Page 13

LS-9376P Page 4

Page 34

A

Page 36

Dock Conn

VGA Conn

Port 7

WLAN (MINI card)

Page 25

Port 13

Page 32

Page 22

DPC

D

Page 33

Page 36

ODD Conn.

Page 23 Page 23

TPM1.2

Infineon SLB9656

SMBus (PCH)

B

eDP MUX PS8321

Page 36

eDPF

MXM3.0 Conn NVidia:

PE

CRT

VGA Switch 2 to 2

CRT

MAX14885EETL

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

Port 1

mSATA Conn.

Page 35

CRT

Port 2

SATA HDD Conn. (Secondary)

Page 36

Port 4

(GEN1 1.5Gb/S GEN2 3Gb/S GEN3 6Gb/S)

Page 23

PEGx16

SATAx4

USB 2.0 Bus

KBC

Page 28

Touch Pad

SMSC MES1132

PS2

eDP

CRT

100MHz

Port 0

SATA HDD Conn. (primary)

Page 23

Int.KBD

Intel

Haswell

rPGA Processor

rPGA947

37.5mm*37.5mm

Page 4,5,6,7,8,9,10

100MHz

2.7GT/s

Intel

Lynx Point

PCH

695pin BGA

20mm*20mm

Page 13,14,15,16,17,18,19,20,21

LPC BUS

33MHz

SPI(PCH)

Page 30

Page 38Page 38

C

DMI x4FDI x2

100MHz

5GT/s

SPI

BIOS SPI ROM x1, 16 MB

EC ROM 2MB

DDR3L 1333MHz 1.35V

USB 3.0 x4

USB 2.0 x 11

HD Audio

Page 16

HDA Codec IDT 92HD91

Page 30

DDR3-SO-DIMM0, 1

BANK 0, 1, 2, 3

Ch A

Digital MIC

Page 22

Page 26

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

Combo Jack

LS-9373P Page 4

SPK conn

Page 27

2012/06/11 2013/06/11

D

Page 11

Port 1,4,5,9

Compal Secret Data

Deciphered Date

Port 1

Docking x 1

Port 2,5,6

USB conn x 3 (For I/O)

Port 0,11

Docking x 2

USB conn x 4(For I/O)

Port 6

Expresscard

Smart card Controller

Port 7

AU9540A51

FPR

Port 8

Validity VFM471

Port 10

Webcam

Port 12

WWAN SIM Card

Port 13

WLAN

Page 33

page 39

Page 33

page 39

sub/B Page 7

Page 37

Page 28

Page 22

Page 25 Page 25

daughter board

Docking connector: RJ45 USB30*1 USB20*1 DP*2 Parallel port Serial port PS/2 Line in/Line out SATAx2 VGA

Compal Electronics, Inc.

Custom

Compal Electronics, Inc.

Block Diagrams

LA-9371P

E

2 53Friday, September 28, 2012

Title

Size Document Number Rev

Date: Sheet of

0.2

5

4

3

2

1

Voltage Rails

D D

State

S0

C C

SMBUS Control Table

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

( O MEANS ON X MEANS OFF )

+RTCVCC

power plane

O

Symbol Note :

B+

O

X

+5VDS

+3VDS

OO

O

X

X X X

+1.35V

+0.675VS

O

X X

X

+5VS

+3VS

+1.5VS

+VCC_CORE

+1.05VS

1.05VM

+

OO

X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

AMT@ : means just install for support iAMT CONN@ : means ME part.

Layout Notes

L

07/24 update

: Question Area Mark.(Wait check)

Install below 45 level BOM structure for ver. 0.1

45@ : means just put it in the BOM of 45 level.

Install below 43 level BOM structure for ver. 0.1

DEBUG@ : means just build when PCIE port 80 CARD function enable.

Remove before MP

SOURCE

B B

A A

I2C_MAIN_CLK I2C_MAIN_DAT

I2C_BAY_CLK I2C_BAY_DAT

MEM_SMBCLK MEM_SMBDATA

LAN_SMBCLK LAN_SMBDATA

SML1_SMBCLK SML1_SMBDATA

Stapping O ptions Fla sh

GPIO 51 Bit 1

0

0 1

1

1 1

SMSC1126

Haswell

GPIO 19 Bit 0

0

5

Haswell

H

aswell

Boot BIOS Destination

2nd

BATT

X

V

X

V

X

X X

X X X

Reserved

RSVD

SPI

LPC

XDP

X

V

SODIMM

X

V

X X

G-SENSOR

X

V

X X

4

X

TP

V

X

NIC

X

V

X

NFC

EC

MXM

X

X X

X

V

Issued Date

X

X X

X

V

Compal Secret Data

2012/06/11 2013/06/11

3

Compal Secret Data

Deciphered Date

2

X

X X

V

X

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-9371P

3 53Friday, September 28, 2012

1

0.2

5

D D

DMI_CRX_PTX_N0<14> DMI_CRX_PTX_N1<14> DMI_CRX_PTX_N2<14> DMI_CRX_PTX_N3<14>

DMI_CRX_PTX_P0<14> DMI_CRX_PTX_P1<14> DMI_CRX_PTX_P2<14> DMI_CRX_PTX_P3<14>

DMI_CTX_PRX_N0<14> DMI_CTX_PRX_N1<14> DMI_CTX_PRX_N2<14> DMI_CTX_PRX_N3<14>

DMI_CTX_PRX_P0<14> DMI_CTX_PRX_P1<14>

C C

B B

DMI_CTX_PRX_P2<14> DMI_CTX_PRX_P3<14>

FDI_CSYNC<14> FDI_INT<14>

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CSYNC FDI_INT

4

Haswell rPGA EDS

JCPU1A

D21

DMI_RXN_0

C21

DMI_RXN_1

B21

DMI_RXN_2

A21

DMI_RXN_3

D20

DMI_RXP_0

C20

DMI_RXP_1

B20

DMI_RXP_2

A20

DMI_RXP_3

D18

DMI_TXN_0

C17

DMI_TXN_1

B17

DMI_TXN_2

A17

DMI_TXN_3

D17

DMI_TXP_0

C18

DMI_TXP_1

B18

DMI_TXP_2

A18

DMI_TXP_3

H29

FDI_CSYNC

J29

DISP_INT

I

NTEL_HASWELL_HA SWELL

CONN@

3

+VCCIOA_OUT

PEG_COMP

CAD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils.

E23

PEG_RCOMP

PEG_RXN_0 PEG_RXN_1 PEG_RXN_2 PEG_RXN_3 PEG_RXN_4 PEG_RXN_5 PEG_RXN_6

PEG

PEG_RXN_7

DMI FDI

1 OF 9

PEG_RXN_8

PEG_RXN_9 PEG_RXN_10 PEG_RXN_11 PEG_RXN_12 PEG_RXN_13 PEG_RXN_14 PEG_RXN_15

PEG_RXP_0 PEG_RXP_1 PEG_RXP_2 PEG_RXP_3 PEG_RXP_4 PEG_RXP_5 PEG_RXP_6 PEG_RXP_7 PEG_RXP_8

PEG_RXP_9 PEG_RXP_10 PEG_RXP_11 PEG_RXP_12 PEG_RXP_13 PEG_RXP_14 PEG_RXP_15

PEG_TXN_0

PEG_TXN_1

PEG_TXN_2

PEG_TXN_3

PEG_TXN_4

PEG_TXN_5

PEG_TXN_6

PEG_TXN_7

PEG_TXN_8

PEG_TXN_9 PEG_TXN_10 PEG_TXN_11 PEG_TXN_12 PEG_TXN_13 PEG_TXN_14 PEG_TXN_15

PEG_TXP_0

PEG_TXP_1

PEG_TXP_2

PEG_TXP_3

PEG_TXP_4

PEG_TXP_5

PEG_TXP_6

PEG_TXP_7

PEG_TXP_8

PEG_TXP_9 PEG_TXP_10 PEG_TXP_11 PEG_TXP_12 PEG_TXP_13 PEG_TXP_14 PEG_TXP_15

PEG_COMP

M29

PEG_CRX_GTX_N0

K28

PEG_CRX_GTX_N1

M31

PEG_CRX_GTX_N2

L30

PEG_CRX_GTX_N3

M33

PEG_CRX_GTX_N4

L32

PEG_CRX_GTX_N5

M35

PEG_CRX_GTX_N6

L34

PEG_CRX_GTX_N7

E29

PEG_CRX_GTX_N8

D28

PEG_CRX_GTX_N9

E31

PEG_CRX_GTX_N10

D30

PEG_CRX_GTX_N11

E35

PEG_CRX_GTX_N12

D34

PEG_CRX_GTX_N13

E33

PEG_CRX_GTX_N14

E32

PEG_CRX_GTX_N15

L29

PEG_CRX_GTX_P0

L28

PEG_CRX_GTX_P1

L31

PEG_CRX_GTX_P2

K30

PEG_CRX_GTX_P3

L33

PEG_CRX_GTX_P4

K32

PEG_CRX_GTX_P5

L35

PEG_CRX_GTX_P6

K34

PEG_CRX_GTX_P7

F29

PEG_CRX_GTX_P8

E28

PEG_CRX_GTX_P9

F31

PEG_CRX_GTX_P10

E30

PEG_CRX_GTX_P11

F35

PEG_CRX_GTX_P12

E34

PEG_CRX_GTX_P13

F33

PEG_CRX_GTX_P14

D32

PEG_CRX_GTX_P15

H35

PEG_CTX_GRX_C_N0

H34

PEG_CTX_GRX_C_N1

J33

PEG_CTX_GRX_C_N2

H32

PEG_CTX_GRX_C_N3

J31

PEG_CTX_GRX_C_N4

G30

PEG_CTX_GRX_C_N5

C33

PEG_CTX_GRX_C_N6

B32

PEG_CTX_GRX_C_N7

B31

PEG_CTX_GRX_C_N8

A30

PEG_CTX_GRX_C_N9

B29

PEG_CTX_GRX_C_N10

A28

PEG_CTX_GRX_C_N11

B27

PEG_CTX_GRX_C_N12

A26

PEG_CTX_GRX_C_N13

B25

PEG_CTX_GRX_C_N14

A24

PEG_CTX_GRX_C_N15

J35

PEG_CTX_GRX_C_P0

G34

PEG_CTX_GRX_C_P1

H33

PEG_CTX_GRX_C_P2

G32

PEG_CTX_GRX_C_P3

H31

PEG_CTX_GRX_C_P4

H30

PEG_CTX_GRX_C_P5

B33

PEG_CTX_GRX_C_P6

A32

PEG_CTX_GRX_C_P7

C31

PEG_CTX_GRX_C_P8

B30

PEG_CTX_GRX_C_P9

C29

PEG_CTX_GRX_C_P10

B28

PEG_CTX_GRX_C_P11

C27

PEG_CTX_GRX_C_P12

B26

PEG_CTX_GRX_C_P13

C25

PEG_CTX_GRX_C_P14

B24

PEG_CTX_GRX_C_P15

12

RC124.9_0402_1% RC124.9_0402_1%

2

PEG_CRX_GTX_P[0..15]

PEG_CRX_GTX_N[0..15]

PEG_CTX_GRX_P[0..15]

PEG_CTX_GRX_N[0..15]

PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_N0 PEG_CTX_GRX_N0

PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_N1

PEG_CTX_GRX_C_P2 PEG_CTX_GRX_C_N2

PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_N3

PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_N4

PEG_CTX_GRX_C_P5 PEG_CTX_GRX_C_N5

PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_N6

PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_N7

PEG_CTX_GRX_C_P8 PEG_CTX_GRX_C_N8

PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_N9

PEG_CTX_GRX_C_P10 PEG_CTX_GRX_C_N10

PEG_CTX_GRX_C_P11 PEG_CTX_GRX_C_N11

PEG_CTX_GRX_C_P12 PEG_CTX_GRX_C_N12

PEG_CTX_GRX_C_P13 PEG_CTX_GRX_C_N13

PEG_CTX_GRX_C_P14 PEG_CTX_GRX_C_N14

PEG_CTX_GRX_C_P15 PEG_CTX_GRX_C_N15

12

CC1 0.22U_0402_6.3V6KCC1 0.22U_0402_6.3V6K

12

CC2 0.22U_0402_6.3V6KCC2 0.22U_0402_6.3V6K

12

CC3 0.22U_0402_6.3V6KCC3 0.22U_0402_6.3V6K

12

CC4 0.22U_0402_6.3V6KCC4 0.22U_0402_6.3V6K

12

CC5 0.22U_0402_6.3V6KCC5 0.22U_0402_6.3V6K

12

CC6 0.22U_0402_6.3V6KCC6 0.22U_0402_6.3V6K

12

CC7 0.22U_0402_6.3V6KCC7 0.22U_0402_6.3V6K

12

CC8 0.22U_0402_6.3V6KCC8 0.22U_0402_6.3V6K

12

CC9 0.22U_0402_6.3V6KCC9 0.22U_0402_6.3V6K

12

CC10 0.22U_0402_6.3V6KCC10 0.22U_0402_6.3V6K

12

CC11 0.22U_0402_6.3V6KCC11 0.22U_0402_6.3V6K

12

CC12 0.22U_0402_6.3V6KCC12 0.22U_0402_6.3V6K

12

CC13 0.22U_0402_6.3V6KCC13 0.22U_0402_6.3V6K

12

CC14 0.22U_0402_6.3V6KCC14 0.22U_0402_6.3V6K

12

CC15 0.22U_0402_6.3V6KCC15 0.22U_0402_6.3V6K

12

CC16 0.22U_0402_6.3V6KCC16 0.22U_0402_6.3V6K

1 2

CC17 0.22U_0402_6.3V6KCC17 0.22U_0402_6.3V6K

1 2

CC18 0.22U_0402_6.3V6KCC18 0.22U_0402_6.3V6K

1 2

CC19 0.22U_0402_6.3V6KCC19 0.22U_0402_6.3V6K

1 2

CC20 0.22U_0402_6.3V6KCC20 0.22U_0402_6.3V6K

1 2

CC21 0.22U_0402_6.3V6KCC21 0.22U_0402_6.3V6K

1 2

CC22 0.22U_0402_6.3V6KCC22 0.22U_0402_6.3V6K

1 2

CC23 0.22U_0402_6.3V6KCC23 0.22U_0402_6.3V6K

1 2

CC24 0.22U_0402_6.3V6KCC24 0.22U_0402_6.3V6K

1 2

CC25 0.22U_0402_6.3V6KCC25 0.22U_0402_6.3V6K

1 2

CC26 0.22U_0402_6.3V6KCC26 0.22U_0402_6.3V6K

1 2

CC27 0.22U_0402_6.3V6KCC27 0.22U_0402_6.3V6K

1 2

CC28 0.22U_0402_6.3V6KCC28 0.22U_0402_6.3V6K

1 2

CC29 0.22U_0402_6.3V6KCC29 0.22U_0402_6.3V6K

1 2

CC30 0.22U_0402_6.3V6KCC30 0.22U_0402_6.3V6K

1 2

CC31 0.22U_0402_6.3V6KCC31 0.22U_0402_6.3V6K

1 2

CC32 0.22U_0402_6.3V6KCC32 0.22U_0402_6.3V6K

PEG_CRX_GTX_P[0..15] <35>

PEG_CRX_GTX_N[0..15] <35>

PEG_CTX_GRX_P[0..15] <35>

PEG_CTX_GRX_N[0..15] <35>

PEG_CTX_GRX_P0

PEG_CTX_GRX_P1 PEG_CTX_GRX_N1

PEG_CTX_GRX_P2 PEG_CTX_GRX_N2

PEG_CTX_GRX_P3 PEG_CTX_GRX_N3

PEG_CTX_GRX_P4 PEG_CTX_GRX_N4

PEG_CTX_GRX_P5 PEG_CTX_GRX_N5

PEG_CTX_GRX_P6 PEG_CTX_GRX_N6

PEG_CTX_GRX_P7 PEG_CTX_GRX_N7

PEG_CTX_GRX_P8 PEG_CTX_GRX_N8

PEG_CTX_GRX_P9 PEG_CTX_GRX_N9

PEG_CTX_GRX_P10

PEG_CTX_GRX_N10

PEG_CTX_GRX_P11

PEG_CTX_GRX_N11

PEG_CTX_GRX_P12

PEG_CTX_GRX_N12

PEG_CTX_GRX_P13

PEG_CTX_GRX_N13

PEG_CTX_GRX_P14

PEG_CTX_GRX_N14

PEG_CTX_GRX_P15

PEG_CTX_GRX_N15

1

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DMI,PEG

LA-9371P

1

4 53Friday, September 28, 2012

0.2

of

5

SM_DRAMPWROK with DDR Power Gating Topology

+5VDS

CC35

1 2

0.1U_0402_10V6K

UC1

20120923 HP's request 20120810 HP's request

D D

C C

KBC_PROC_HOT#

PM_DRAM_PWRGD<14>

1 2

+3VS

RC9 100K_0402_1%RC9 100K_0402_1%

+VCCIO_OUT

RC23 62_0402_5%RC23 62_0402_5%

13

D

2

G

Q59

G

Q59

S

2N7002KW_SOT323-3

PWR_GD<30,31,46>

1 2

CLK_CPU_SSC_DPLL#<15> CLK_CPU_SSC_DPLL<15>

KBC_PROC_HOT

PCH_THERMTRIP#_R<18,35>

H_PM_SYNC<14>

H_CPUPWRGD<18>

CPU_PLTRST#<18>

CLK_CPU_DPLL#<15> CLK_CPU_DPLL<15>

CLK_CPU_DMI#<15> CLK_CPU_DMI<15>

KBC_PROC_HOT_R<24,46>

UC1

1

2

RUN_ON_CPU1.5VS3#<9>

RC26 56_0402_5%RC26 56_0402_5% RC27

RC27

5

P

B

4

O

A

G

74AHC1G09GW_TSSOP5

3

Part Number = SA00003Y000

2

G

KBC_PROC_HOT_R

T120PAD @T120PAD @

T118PAD @T118PAD @

H_PECI<30>

1 2

390_0402_1%

1 2

20120911 Delete RC30 as HP's request

4

+1.35VS

12

RC5

1.8K_0402_1%

12

39_0402_5%

RC10

@

3.3K_0402_1%

RC12

1 2

13

D

QC1

2N7002K_SOT23-3

S

CPU_DETECT#

H_CATERR# H_PECI

T1PAD @T1PAD @

KBC_PROC_HOT_R H_THERMTRIP#

H_PM_SYNC H_CPUPWRGD PM_DRAM_PWRGD_CPU CPU_PLTRST#

PM_DRAM_PWRGD_CPU

Haswell rPGA EDS

CONN@

JCPU1B

AP32

SKTOCC

AN32

CATERR

AR27

PECI

AK31

FC_AK31

AM30

PROCHOT

AM35

THERMTRIP

AT28

PM_SYNC

AL34

PWRGOO D

AC10

SM_DRAMPW ROK

AT26

PLTRSTIN

G28

DPLL_REF _CLKN

H28

DPLL_REF _CLKP

F27

SSC_DPLL _REF_CLKN

E27

SSC_DPLL _REF_CLKP

D26

BCLKN

E26

BCLKP

INTEL_HASWELL_HASWELL

3

+VCCIO_OUT

Place near JXDP1

ON/OFFBTN#<13,14,30>

CPU_PWR_DEBUG<9>

DDR_XDP_WAN_SMBDAT<11,12,13,16,28,38> DDR_XDP_WAN_SMBCLK<11,12,13,16,28,38>

H_CPUPWRGD H_CPUPWRGD_XDP

PM_PWROK<14,30>

0.1U_0402_16V4Z

1

CC34

CC33

2

RC5 need to close to JCPU1

1 2

RC13 1K_0402_1%RC13 1K_0402_1%

1 2

RC107

20120925 HP's request

0_0402_5%

CFG0<8> CFG1<8>

CFG2<8> CFG3<8>

CFG4<8> CFG5<8>

CFG6<8> CFG7<8>

XDP_PREQ# XDP_PRDY#

CFG0 CFG1

CFG2 CFG3

XDP_OBS0 XDP_OBS1

CFG4 CFG5

CFG6 CFG7

PM_PWROK_XDP

XDP_TCLK

2

+VCCIO_OUT +VCCIO_OUT

JXDP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A 0

11

OBSDATA_A 1

13

GND4

15

OBSDATA_A 2

17

OBSDATA_A 3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B 0

29

OBSDATA_B 1

31

GND10

33

OBSDATA_B 2

35

OBSDATA_B 3

37

GND12

39

PWRGOO D/HOOK0

41

HOOK1

43

VCC_OBS_ AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

ITPCLK#/HO OK5

RESET#/HOO K6

GND1 OBSFN_C0 OBSFN_C1

GND3

OBSDATA_C0 OBSDATA_C1

GND5

OBSDATA_C2 OBSDATA_C3

GND7 OBSFN_D0 OBSFN_D1

GND9

OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK 4

VCC_OBS_ CD

DBR#/HOOK 7

GND15

TRST#

GND17

CONN@

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

TD0

54 56

TDI

58

TMS

60

CFG17 CFG16

CFG8 CFG9

CFG10 CFG11

CFG19 CFG18

CFG12 CFG13

CFG14 CFG15

XDP_RST#_R XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

RC105 1K_0402_1%RC105 1K_0402_1%

1

CFG17 <8> CFG16 <8>

CFG8 <8> CFG9 <8>

CFG10 <8> CFG11 <8>

CFG19 <8> CFG18 <8>

CFG12 <8> CFG13 <8>

CFG14 <8> CFG15 <8>

12

RC16 1K_0402_1%RC16 1K_0402_1%

PLT_RST#

12

CFG3

PLT_RST# <13,14,25,28,29,30,35,37,39>

#4/16 change by HP requirement

1 2

@

RC22 0_0402_5%

MISC

THERMAL

DDR3

PWR

CLOCK

2 OF 9

SM_RCOMP_ 0 SM_RCOMP_ 1 SM_RCOMP_ 2 SM_DRAMRST

JTAG

BPM_N_0 BPM_N_1 BPM_N_2 BPM_N_3 BPM_N_4 BPM_N_5 BPM_N_6 BPM_N_7

AP3

SM_RCOMP0

AR3

SM_RCOMP1

AP2

SM_RCOMP2

AN3

DDR3_DRAMRST#_CPU

AR29

XDP_PRDY#

PRDY

AT29

XDP_PREQ#

PREQ

AM34

XDP_TCLK

TCK

AN33

XDP_TMS

TMS

AM33

XDP_TRST#

TRST

AM31

XDP_TDI

TDI

AL33

XDP_TDO

TDO

AP33

XDP_DBRESET#

DBR

AR30

XDP_OBS0

AN31

XDP_OBS1

AN29

XDP_OBS2_R

AP31

XDP_OBS3_R

AP30

XDP_OBS4_R

AN28

XDP_OBS5_R

AP29

XDP_OBS6_R

AP28

XDP_OBS7_R

For ESD concern, please place close to CPU

RC36 0_0402_5%@RC36 0_0402_5%@ RC38 0_0402_5%@RC38 0_0402_5%@ RC40 0_0402_5%@RC40 0_0402_5%@ RC43 0_0402_5%@RC43 0_0402_5%@ RC45 0_0402_5%@RC45 0_0402_5%@ RC47 0_0402_5%@RC47 0_0402_5%@

XDP_DBRESET# <13,14>

1 2 1 2 1 2 1 2 1 2 1 2

DDR3_DRAMRST#_CPU

KBC_DS3_EN<25,29,30,44,9>

RC22 0_0402_5%

BSS138W-7-F_SOT323-3

S

4.99K_0402_1%

G

2

12

RC28

2

G

QC2

D

13

1 2

RC25 3.3K_0402_5%RC25 3.3K_0402_5%

13

D

QC3

2N7002K_SOT23-3

S

CPU_DRAM_RST# <11>

20120725 for S3 resume as HP's request

DDR_RST_EN <16>

PU/PD for JTAG signals

SSC CLOCK TERMINATION, IF NOT USED, stuff RC20,RC21

H_CPUPWRGD

B B

CAD Note: Avoid stub in the PWRGD path

20120911 Delete RC66 as HP's request

A A

5

4

while placing resistors RC25 & RC130

12

RC55

RC55 10K_0402_1%

10K_0402_1%

CRB Rev 0.7 is depop

3

CRB Rev 0.7 no pull up

DDR3 COMPENSATION SIGNALS

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

RC59 100_0402_1%RC59 100_0402_1%

1 2

RC61 75_0402_1%RC61 75_0402_1%

1 2

RC65 100_0402_1%RC65 100_0402_1%

Compal Secret Data

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

2

XDP_DBRESET#

RC52 1K_0402_1%RC52 1K_0402_1%

XDP_TDO

RC57 51_0402_1%RC57 51_0402_1%

XDP_TCLK

RC60 51_0402_1%RC60 51_0402_1%

XDP_TRST#

RC62 51_0402_1%RC62 51_0402_1%

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PM,XDP,CLK

12

LA-9371P

1

+3VS

+1.05VS

0.2

5 53Friday, September 28, 2012

0.2

5

D D

DDR_A_D[0..63]<11>

C C

B B

+SM_VREF_CA +DIMM01_VREF_DQ +DIMM23_VREF_DQ

20120710 Change by HP request

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AR15

SA_DQ_0

AT14

SA_DQ_1

AM14

SA_DQ_2

AN14

SA_DQ_3

AT15

SA_DQ_4

AR14

SA_DQ_5

AN15

SA_DQ_6

AM15

SA_DQ_7

AM9

SA_DQ_8

AN9

SA_DQ_9

AM8

SA_DQ_10

AN8

SA_DQ_11

AR9

SA_DQ_12

AT9

SA_DQ_13

AR8

SA_DQ_14

AT8

SA_DQ_15

AJ9

SA_DQ_16

AK9

SA_DQ_17

AJ6

SA_DQ_18

AK6

SA_DQ_19

AJ10

SA_DQ_20

AK10

SA_DQ_21

AJ7

SA_DQ_22

AK7

SA_DQ_23

AF4

SA_DQ_24

AF5

SA_DQ_25

AF1

SA_DQ_26

AF2

SA_DQ_27

AG4

SA_DQ_28

AG5

SA_DQ_29

AG1

SA_DQ_30

AG2

SA_DQ_31

J1

SA_DQ_32

J2

SA_DQ_33

J5

SA_DQ_34

H5

SA_DQ_35

H2

SA_DQ_36

H1

SA_DQ_37

J4

SA_DQ_38

H4

SA_DQ_39

F2

SA_DQ_40

F1

SA_DQ_41

D2

SA_DQ_42

D3

SA_DQ_43

D1

SA_DQ_44

F3

SA_DQ_45

C3

SA_DQ_46

B3

SA_DQ_47

B5

SA_DQ_48

E6

SA_DQ_49

A5

SA_DQ_50

D6

SA_DQ_51

D5

SA_DQ_52

E5

SA_DQ_53

B6

SA_DQ_54

A6

SA_DQ_55

E12

SA_DQ_56

D12

SA_DQ_57

B11

SA_DQ_58

A11

SA_DQ_59

E11

SA_DQ_60

D11

SA_DQ_61

B12

SA_DQ_62

A12

SA_DQ_63

AM3

SM_VREF

F16

SA_DIMM_VREFDQ

F13

SB_DIMM_VREFDQ

I

NTEL_HASWELL_HASWELL

3 OF 9

4

Haswell rPGA EDS

JCPU1C

CONN@

SA_CK_N_0 SA_CK_P_0

SA_CKE_0 SA_CK_N_1 SA_CK_P_1

SA_CKE_1 SA_CK_N_2 SA_CK_P_2

SA_CKE_2 SA_CK_N_3 SA_CK_P_3

SA_CKE_3

SA_CS_N_0 SA_CS_N_1 SA_CS_N_2 SA_CS_N_3

SA_ODT_0

SA_ODT_1

SA_ODT_2

SA_ODT_3

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS

SA_WE

SA_CAS

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_DQS_N_0 SA_DQS_N_1 SA_DQS_N_2 SA_DQS_N_3 SA_DQS_N_4 SA_DQS_N_5 SA_DQS_N_6 SA_DQS_N_7 SA_DQS_P_0 SA_DQS_P_1 SA_DQS_P_2 SA_DQS_P_3 SA_DQS_P_4 SA_DQS_P_5 SA_DQS_P_6 SA_DQS_P_7

RSVD

VSS

AC7 U4

M_CLK_A_DDR#0

V4

M_CLK_A_DDR0

AD9

DDR_CKE0_DIMMA

U3

M_CLK_A_DDR#1

V3

M_CLK_A_DDR1

AC9

DDR_CKE1_DIMMA

U2

M_CLK_A_DDR#2

V2

M_CLK_A_DDR2

AD8

DDR_CKE2_DIMMA

U1

M_CLK_A_DDR#3

V1

M_CLK_A_DDR3

AC8

DDR_CKE3_DIMMA

M7

DDR_CS0_DIMMA#

L9

DDR_CS1_DIMMA#

M9

DDR_CS2_DIMMA#

M10

DDR_CS3_DIMMA#

M8

M_A_ODT0

L7

M_A_ODT1

L8

M_A_ODT2

L10

M_A_ODT3

V5

DDR_A_BS0

U5

DDR_A_BS1

AD1

DDR_A_BS2

V10 U6

DDR_A_RAS#

U7

DDR_A_WE#

U8

DDR_A_CAS#

V8

DDR_A_MA0

AC6

DDR_A_MA1

V9

DDR_A_MA2

U9

DDR_A_MA3

AC5

DDR_A_MA4

AC4

DDR_A_MA5

AD6

DDR_A_MA6

AC3

DDR_A_MA7

AD5

DDR_A_MA8

AC2

DDR_A_MA9

V6

DDR_A_MA10

AC1

DDR_A_MA11

AD4

DDR_A_MA12

V7

DDR_A_MA13

AD3

DDR_A_MA14

AD2

DDR_A_MA15

AP15

DDR_A_DQS#0

AP8

DDR_A_DQS#1

AJ8

DDR_A_DQS#2

AF3

DDR_A_DQS#3

J3

DDR_A_DQS#4

E2

DDR_A_DQS#5

C5

DDR_A_DQS#6

C11

DDR_A_DQS#7

AP14

DDR_A_DQS0

AP9

DDR_A_DQS1

AK8

DDR_A_DQS2

AG3

DDR_A_DQS3

H3

DDR_A_DQS4

E3

DDR_A_DQS5

C6

DDR_A_DQS6

C12

DDR_A_DQS7

M_CLK_A_DDR#0 <11> M_CLK_A_DDR0 <11> DDR_CKE0_DIMMA <11> M_CLK_A_DDR#1 <11> M_CLK_A_DDR1 <11> DDR_CKE1_DIMMA <11> M_CLK_A_DDR#2 <11> M_CLK_A_DDR2 <11> DDR_CKE2_DIMMA <11> M_CLK_A_DDR#3 <11> M_CLK_A_DDR3 <11> DDR_CKE3_DIMMA <11>

DDR_CS0_DIMMA# <11> DDR_CS1_DIMMA# <11> DDR_CS2_DIMMA# <11> DDR_CS3_DIMMA# <11>

M_A_ODT0 <11> M_A_ODT1 <11> M_A_ODT2 <11>

M_A_ODT3 <11> DDR_A_BS0 <11> DDR_A_BS1 <11> DDR_A_BS2 <11>

DDR_A_RAS# <11> DDR_A_WE# <11> DDR_A_CAS# <11>

DDR_A_MA[0..15] <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

3

DDR_B_D[0..63]<12>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AR18

SB_DQ_0

AT18

SB_DQ_1

AM17

SB_DQ_2

AM18

SB_DQ_3

AR17

SB_DQ_4

AT17

SB_DQ_5

AN17

SB_DQ_6

AN18

SB_DQ_7

AT12

SB_DQ_8

AR12

SB_DQ_9

AN12

SB_DQ_10

AM11

SB_DQ_11

AT11

SB_DQ_12

AR11

SB_DQ_13

AM12

SB_DQ_14

AN11

SB_DQ_15

AR5

SB_DQ_16

AR6

SB_DQ_17

AM5

SB_DQ_18

AM6

SB_DQ_19

AT5

SB_DQ_20

AT6

SB_DQ_21

AN5

SB_DQ_22

AN6

SB_DQ_23

AJ4

SB_DQ_24

AK4

SB_DQ_25

AJ1

SB_DQ_26

AJ2

SB_DQ_27

AM1

SB_DQ_28

AN1

SB_DQ_29

AK2

SB_DQ_30

AK1

SB_DQ_31

L2

SB_DQ_32

M2

SB_DQ_33

L4

SB_DQ_34

M4

SB_DQ_35

L1

SB_DQ_36

M1

SB_DQ_37

L5

SB_DQ_38

M5

SB_DQ_39

G7

SB_DQ_40

J8

SB_DQ_41

G8

SB_DQ_42

G9

SB_DQ_43

J7

SB_DQ_44

J9

SB_DQ_45

G10

SB_DQ_46

J10

SB_DQ_47

A8

SB_DQ_48

B8

SB_DQ_49

A9

SB_DQ_50

B9

SB_DQ_51

D8

SB_DQ_52

E8

SB_DQ_53

D9

SB_DQ_54

E9

SB_DQ_55

E15

SB_DQ_56

D15

SB_DQ_57

A15

SB_DQ_58

B15

SB_DQ_59

E14

SB_DQ_60

D14

SB_DQ_61

A14

SB_DQ_62

B14

SB_DQ_63

I

NTEL_HASWELL_HASWELL

JCPU1D

4 OF 9

CONN@

2

Haswell rPGA EDS

RSVD

SB_CKN0

SB_CK0

SB_CKE_0

SB_CKN1

SB_CK1

SB_CKE_1

SB_CKN2

SB_CK2

SB_CKE_2

SB_CKN3

SB_CK3

SB_CKE_3

SB_CS_N_0 SB_CS_N_1 SB_CS_N_2 SB_CS_N_3

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS

SB_WE

SB_CAS

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SB_DQS_N_0 SB_DQS_N_1 SB_DQS_N_2 SB_DQS_N_3 SB_DQS_N_4 SB_DQS_N_5 SB_DQS_N_6 SB_DQS_N_7 SB_DQS_P_0 SB_DQS_P_1 SB_DQS_P_2 SB_DQS_P_3 SB_DQS_P_4 SB_DQS_P_5 SB_DQS_P_6 SB_DQS_P_7

VSS

AG8 Y4

M_CLK_B_DDR#0

AA4

M_CLK_B_DDR0

AF10

DDR_CKE0_DIMMB

Y3

M_CLK_B_DDR#1

AA3

M_CLK_B_DDR1

AG10

DDR_CKE1_DIMMB

Y2

M_CLK_B_DDR#2

AA2

M_CLK_B_DDR2

AG9

DDR_CKE2_DIMMB

Y1

M_CLK_B_DDR#3

AA1

M_CLK_B_DDR3

AF9

DDR_CKE3_DIMMB

P4

DDR_CS0_DIMMB#

R2

DDR_CS1_DIMMB#

P3

DDR_CS2_DIMMB#

P1

DDR_CS3_DIMMB#

R4

M_B_ODT0

R3

M_B_ODT1

R1

M_B_ODT2

P2

M_B_ODT3

R7

DDR_B_BS0

P8

DDR_B_BS1

AA9

DDR_B_BS2

R10 R6

DDR_B_RAS#

P6

DDR_B_WE#

P7

DDR_B_CAS#

R8

DDR_B_MA0

Y5

DDR_B_MA1

Y10

DDR_B_MA2

AA5

DDR_B_MA3

Y7

DDR_B_MA4

AA6

DDR_B_MA5

Y6

DDR_B_MA6

AA7

DDR_B_MA7

Y8

DDR_B_MA8

AA10

DDR_B_MA9

R9

DDR_B_MA10

Y9

DDR_B_MA11

AF7

DDR_B_MA12

P9

DDR_B_MA13

AA8

DDR_B_MA14

AG7

DDR_B_MA15

AP18

DDR_B_DQS#0

AP11

DDR_B_DQS#1

AP5

DDR_B_DQS#2

AJ3

DDR_B_DQS#3

L3

DDR_B_DQS#4

H9

DDR_B_DQS#5

C8

DDR_B_DQS#6

C14

DDR_B_DQS#7

AP17

DDR_B_DQS0

AP12

DDR_B_DQS1

AP6

DDR_B_DQS2

AK3

DDR_B_DQS3

M3

DDR_B_DQS4

H8

DDR_B_DQS5

C9

DDR_B_DQS6

C15

DDR_B_DQS7

T3 PAD~D@T3 PA D~D@

M_CLK_B_DDR#0 <12> M_CLK_B_DDR0 <12> DDR_CKE0_DIMMB <12> M_CLK_B_DDR#1 <12> M_CLK_B_DDR1 <12> DDR_CKE1_DIMMB <12> M_CLK_B_DDR#2 <12> M_CLK_B_DDR2 <12> DDR_CKE2_DIMMB <12> M_CLK_B_DDR#3 <12> M_CLK_B_DDR3 <12> DDR_CKE3_DIMMB <12>

DDR_CS0_DIMMB# <12> DDR_CS1_DIMMB# <12> DDR_CS2_DIMMB# <12> DDR_CS3_DIMMB# <12>

M_B_ODT0 <12> M_B_ODT1 <12> M_B_ODT2 <12>

M_B_ODT3 <12> DDR_B_BS0 <12> DDR_B_BS1 <12> DDR_B_BS2 <12>

DDR_B_RAS# <12> DDR_B_WE# <12> DDR_B_CAS# <12>

1

DDR_B_MA[0..15] <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

+SM_VREF_CA +DIMM23_VREF_DQ+DIMM01_VREF_DQ

0.1U_0402_16V4Z

1

CC84

2

Layout Notes

A A

5

L

Place CC84,CC85,CC86 close to JCPU1

0.1U_0402_16V4Z

1

CC85

2

0.1U_0402_16V4Z

1

CC86

2

20120802 HP's request

4

20120710 Change by HP request

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRIII

LA-9371P

6 53Friday, September 28, 2012

1

0.2

5

D D

4

3

2

1

COMPENSATION PU FOR eDP

+VCCIOA_OUT

EDP_COMP

CAD Note:Trace width=20 mils ,Spacing=25mil,

Haswell rPGA EDS

T28

DDIB_TXBN_0

U28

DDIB_TXBP_0

T30

C C

DDIB_TXBN_1

U30

DDIB_TXBP_1

U29

DDIB_TXBN_2

V29

DDIB_TXBP_2

U31

DDIB_TXBN_3

V31

DDIB_TXBP_3

T34

DDIC_TXCN_0

U34

DDIC_TXCP_0

U35

DDIC_TXCN_1

V35

DDIC_TXCP_1

U32

DDIC_TXCN_2

T32

DDIC_TXCP_2

U33

DDIC_TXCN_3

V33

DDIC_TXCP_3

P29

DDID_TXDN_0

R29

DDID_TXDP_0

N28

DDID_TXDN_1

P28

DDID_TXDP_1

P31

DDID_TXDN_2

R31

DDID_TXDP_2

N30

DDID_TXDN_3

P30

DDID_TXDP_3

INTEL_HASWELL_HAS WELL

eDP

CONN@

EDP_AUXN EDP_AUXP

EDP_HPD

EDP_RCOMP

EDP_DISP_UT IL

EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1

FDI_TXN_0 FDI_TXP_0 FDI_TXN_1 FDI_TXP_1

DDI

8 OF 9

JCPU1H

M27

EDP_CPU_C_AUX#

N27

EDP_CPU_C_AUX

P27

EDP_HPD

E24

EDP_COMP

R27

P35

EDP_CPU_C_LANE_N0

R35

EDP_CPU_C_LANE_P0

N34

EDP_CPU_C_LANE_N1

P34

EDP_CPU_C_LANE_P1

P33 R33 N32 P32

C126 0.1U_0402_25V6C126 0.1U_0402_25V6 C127 0.1U_0402_25V6C127 0.1U_0402_25V6

T119 PAD@T119 PAD@

C128 0.1U_0402_25V6C128 0.1U_0402_25V6 C129 0.1U_0402_25V6C129 0.1U_0402_25V6 C130 0.1U_0402_25V6C130 0.1U_0402_25V6 C131 0.1U_0402_25V6C131 0.1U_0402_25V6

1 2 1 2

1 2 1 2 1 2 1 2

Max length=100 mils.

FDI_CTX_PRX_N0 FDI_CTX_PRX_P0 FDI_CTX_PRX_N1 FDI_CTX_PRX_P1

+VCCIO_OUT

HPD INVERSION FOR EDP

B B

CPU_EDP_HPD#<36>

2

G

100K_0402_5%

12

RC79

12

RC7724.9_0402_1% RC7724.9_0402_1%

EDP_CPU_AUX# <36> EDP_CPU_AUX <36>

EDP_CPU_LANE_N0 <36> EDP_CPU_LANE_P0 <36> EDP_CPU_LANE_N1 <36> EDP_CPU_LANE_P1 <36> FDI_CTX_PRX_N0 <14> FDI_CTX_PRX_P0 <14> FDI_CTX_PRX_N1 <14> FDI_CTX_PRX_P1 <14>

12

RC78

RC78 10K_0402_5%

10K_0402_5%

20120807 Change RC78 to 10K as HP's request

EDP_HPD

13

D

QH1

QH1 BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

S

SB000002X00

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

CPU-FDI,eDP,DDI

LA-9371P

1

7 53Friday, September 28, 2012

0.2

of

5

4

3

2

1

CFG STRAPS for CPU

CFG2

D D

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition 0:Lane Reversed

Haswell rPGA EDS

JCPU1I

AT1

RSVD_TP

AT2

RSVD_TP

AD10

RSVD

A34

RSVD_TP

A35

RSVD_TP

T15 PAD~D@T15 PAD ~D@ T12 PAD~D@T12 PAD ~D@

T16 PAD~D@T16 PAD ~D@

C C

12

B B

RC84 49.9_0402_1%RC84 49.9_0402_1%

RC85 49.9_0402_1%RC85 49.9_0402_1%

RC86 49.9_0402_1%RC86 49.9_0402_1%

H_CPU_TESTLO

12

CFG_RCOMP

12

H_CPU_RSVD

T17 PAD~D@T17 PAD~D@

T26 PAD~D@T26 PAD ~D@ T28 PAD~D@T28 PAD ~D@

CFG0<5> CFG1<5> CFG2<5> CFG3<5> CFG4<5> CFG5<5> CFG6<5> CFG7<5> CFG8<5> CFG9<5> CFG10<5> CFG11<5> CFG12<5> CFG13<5> CFG14<5> CFG15<5>

+VCC_CORE

H_CPU_RSVD

H_CPU_TESTLO

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

W29

RSVD_TP

W28

RSVD_TP

G26

TESTLO_G26

W33

RSVD

AL30

RSVD

AL29

RSVD

F25

VCC

C35

RSVD_TP

B35

RSVD_TP

AL25

RSVD_TP

W30

RSVD_TP

W31

RSVD_TP

W34

TESTLO

AT20

CFG_0

AR20

CFG_1

AP20

CFG_2

AP22

CFG_3

AT22

CFG_4

AN22

CFG_5

AT25

CFG_6

AN23

CFG_7

AR24

CFG_8

AT23

CFG_9

AN20

CFG_10

AP24

CFG_11

AP26

CFG_12

AN25

CFG_13

AN26

CFG_14

AP25

CFG_15

INTEL_HASWELL_HAS WELL

CONN@

CFG_RCOMP

9 OF 9

RSVD_TP RSVD_TP RSVD_TP RSVD_TP

CFG_16 CFG_18 CFG_17 CFG_19

RSVD

FC_G6

RSVD RSVD RSVD RSVD RSVD

RSVD

RSVD RSVD

RSVD

RSVD_TP

RSVD_TP RSVD_TP

RSVD RSVD

VSS VSS

C23 B23 D24 D23

AT31

CFG_RCOMP

AR21

CFG16

AR23

CFG18

AP21

CFG17

AP23

CFG19

AR33 G6 AM27 AM26 F5 AM2 K6

E18

U10 P10

B1

NC

A2 AR1

E21 E20

AP27 AR26

AL31 AL32

CFG16 < 5> CFG18 < 5> CFG17 < 5> CFG19 < 5>

20120710 Delete RC106/RC107

CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port

11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2

CFG[6:5]

disabled 01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)

CFG4

Display Port Presence Strap

CFG6

CFG5

PCIE Port Bifurcation Straps

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG9

1K_0402_1%

12

@RC106

@

RC106

CFG7

1K_0402_1%

12

RC80

1K_0402_1%

12

RC81

1K_0402_1%

12

@RC83

@RC82

@

RC82

@

RC83

1K_0402_1%

12

@RC87

@

RC87

2012/09/21 For a Intel Sighting

PEG DEFER TRAINING

1: (Default) PEG Train immediately

CFG7

following xxRESETB de assertion 0: PEG Wait for BIOS for training

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU-RSVD,CFG

LA-9371P

1

8 53Friday, September 28, 2012

0.2

5

+1.35VS Source

4

3

2

1

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VCC VCC VCC VCC

VCC VCC

AA26 AA28 AA34 AA30 AA32 AB26 AB29 AB25 AB27 AB28 AB30 AB31 AB33 AB34 AB32 AC26 AB35 AC28 AD25 AC30 AD28 AC32 AD31 AC34 AD34 AD26 AD27 AD29 AD30 AD32 AD33 AD35 AE26 AE32 AE28 AE30 AG28 AG34 AE34 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 AF35 AG26 AH26 AH29 AG30 AG32 AH32 AH35 AH25 AH27 AH28 AH30 AH31 AH33 AH34 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AJ35 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25

U25 U26 V25 V26

W26 W27

+VCC_CORE

B+

4/20 change by HP requirement

D D

C C

SVID ALERT

KBC_DS3_EN<25,29,30,44,5>

SLP_S3#<14,30,31,34,39,44>

RC90 4.7K_0402_5%RC90 4.7K_0402_5%

1 2

20120911 Delete RC93 as HP's request

20K_0402_5%

5

CAD Note: Place the PU resistors close to CPU RC60 close to CPU 300 - 1500mils

12

R461

RUN_ON_CPU1.5VS3#

34

DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6 QC5B

QC5B

SVID DATA

CAD Note: Place the PU resistors close to CPU RC63 close to CPU 300 - 1500mils

+VCC_CORE

100_0402_1%

B B

VCC_SENSE

VCCSENSE<46>

VSSSENSE<10,46>

100_0402_1%

12

RC101

CAD Note: RC102 SHOULD BE PLACED CLOSE TO CPU

VCCSENSE

20120911 Delete RC102, RC103 as HP's request

100_0402_1%

12

CAD Note: RC103 SHOULD BE PLACED CLOSE TO CPU

RC104

VSSSENSE

B+ +1.35VS

12

RC88

@

RC88 100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3

61

DMN66D0LDW-7_SOT363-6

2

QC5A

RUN_ON_CPU1.5VS3# <5>

+1.35V

SI7326DN-T1-GE3_PAK1212-8-5

5

RC92

330K_0402_5%

QC4

12

1 2 3

12

4

1

CC39

2

0.1U_0402_25V6

RUN_ON_CPU1.5VS3 <11,12>

R6

@

20K_0402_5%

D

S

RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES

+1.35VS

RC89

RC89 470_0603_5%

470_0603_5%

1 2

13

10U_0603_6.3V6M

1

2

G

Q2

Q2 2N7002K_SOT23-3

2N7002K_SOT23-3

CC42

2

RUN_ON_CPU1.5VS3#

20120725 HP's request

VDDQ DECOUPLING

10U_0603_6.3V6M

1

CC43

CC44

2

Haswell rPGA EDS

CONN@

JCPU1E

K27

RSVD

L27

RSVD

T27

RSVD

V27

+1.35VS

CC38 0.1U_0402_10V6KCC38 0.1U_0402_10V6K

12

CC40 0.1U_0402_10V6KCC40 0.1U_0402_10V6K

12

+VCC_CORE

VCCSENSE

+VCCIO_OUT

T54

@ T54

@

PAD~D

+VCCIOA_OUT

VR_SVID_ALRT#<46> VR_SVID_CLK<46>

+1.05VS

12

RC98

RC98 150_0402_1%

150_0402_1%

CPU_PWR_DEBUG

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

1

CC45

CC46

2

10U_0603_6.3V6M

1

CC47

CC48

CC49

2

VR_SVID_DAT<46>

CPU_PWR_DEBUG<5>

T50 PAD~D@T50 PAD~D@ T51 PAD~D@T51 PAD~D@ T52 PAD~D@T52 PAD~D@ T53 PAD~D@T53 PAD~D@

10U_0603_6.3V6M

1

2

330U_D2_2V_Y

1

+

CC41

CC51

CC50

2

VR_SVID_ALRT# VR_SVID_CLK VR_SVID_DAT

+VCC_CORE

330U_D2_2V_Y

1

+

CC87

2

@

20120806 Add CC87 as Intel's reply

RSVD

AB11

VDDQ

AB2

VDDQ

AB5

VDDQ

AB8

VDDQ

AE11

VDDQ

AE2

VDDQ

AE5

VDDQ

AE8

VDDQ

AH11

VDDQ

K11

VDDQ

N11

VDDQ

N8

VDDQ

T11

VDDQ

T2

VDDQ

T5

VDDQ

T8

VDDQ

W11

VDDQ

W2

VDDQ

W5

VDDQ

W8

VDDQ

N26

RSVD

K26

VCC

AL27

RSVD

AK27

RSVD

AL35

VCC_SENSE

E17

RSVD

AN35

VCCIO_OUT

A23

RSVD

F22

VCOMP_OUT

W32

RSVD

AL16

RSVD

J27

RSVD

AL13

RSVD

AM28

VIDALERT

AM29

VIDSCLK

AL28

VIDSOUT

AP35

VSS

H27

PWR_DEBUG

AP34

VSS

AT35

RSVD_TP

AR35

RSVD_TP

AR32

RSVD_TP

AL26

RSVD_TP

AT34

VSS

AL22

VSS

AT33

VSS

AM21

VSS

AM25

VSS

AM22

VSS

AM20

VSS

AM24

VSS

AL19

VSS

AM23

VSS

AT32

VSS

Y25

VCC

Y26

VCC

Y27

VCC

Y28

VCC

Y29

VCC

Y30

VCC

Y31

VCC

Y32

VCC

Y33

VCC

Y34

VCC

Y35

VCC

I

NTEL_HASWELL_HASWELL

5 OF 9

22U_0805_6.3V6M

CH2

CH1

1

2

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

22U_0805_6.3V6M

CH3

CH4

1

2

22U_0805_6.3V6M

CH5

CH6

1

2

2012/06/11 2013/06/11

22U_0805_6.3V6M

CH8

CH7

1

2

Compal Secret Data

22U_0805_6.3V6M

CH10

CH9

1

2

Deciphered Date

22U_0805_6.3V6M

CH11

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU- PWR

LA-9371P

1

9 53Friday, September 28, 2012

0.2

of

5

4

3

2

1

D D

C C

B B

Haswell rPGA EDS

A10

VSS

A13

VSS

A16

VSS

A19

VSS

A22

VSS

A25

VSS

A27

VSS

A29

VSS

A3

VSS

A31

VSS

A33

VSS

A4

VSS

A7

VSS

AA11

VSS

AA25

VSS

AA27

VSS

AA31

VSS

AA29

VSS

AB1

VSS

AB10

VSS

AA33

VSS

AA35

VSS

AB3

VSS

AC25

VSS

AC27

VSS

AB4

VSS

AB6

VSS

AB7

VSS

AB9

VSS

AC11

VSS

AD11

VSS

AC29

VSS

AC31

VSS

AC33

VSS

AC35

VSS

AD7

VSS

AE1

VSS

AE10

VSS

AE25

VSS

AE29

VSS

AE3

VSS

AE27

VSS

AE35

VSS

AE4

VSS

AE6

VSS

AE7

VSS

AE9

VSS

AF11

VSS

AF6

VSS

AF8

VSS

AG11

VSS

AG25

VSS

AE31

VSS

AG31

VSS

AE33

VSS

AG6

VSS

AH1

VSS

AH10

VSS

AH2

VSS

AG27

VSS

AG29

VSS

AH3

VSS

AG33

VSS

AG35

VSS

AH4

VSS

AH5

VSS

AH6

VSS

AH7

VSS

AH8

VSS

AH9

VSS

AJ11

VSS

AJ5

VSS

AK11

VSS

AK25

VSS

AK26

VSS

AK28

VSS

AK29

VSS

AK30

VSS

AK32

VSS

E19

VSS

NTEL_HASWELL_HA SWELL

I

JCPU1F

6 OF 9

CONN@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK34 AK5 AL1 AL10 AL11 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 E22 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AM10 AM13 AM16 AM19 E25 AM32 AM4 AM7 AN10 AN13 AN16 AN19 AN2 AN21 AN24 AN27 AN30 AN34 AN4 AN7 AP1 AP10 AP13 AP16 AP19 AP4 AP7 W25 AR10 AR13 AR16 AR19 AR2 AR22 AR25 AR28 AR31 AR34 AR4 AR7 AT10 AT13 AT16 AT19 AT21 AT24 AT27 AT3 AT30 AT4 AT7 B10 B13 B16 B19 B2 B22

Haswell rPGA EDS

B34

VSS

B4

VSS

B7

VSS

C1

VSS

C10

VSS

C13

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C24

VSS

C26

VSS

C28

VSS

C30

VSS

C32

VSS

C34

VSS

C4

VSS

C7

VSS

D10

VSS

D13

VSS

D16

VSS

D19

VSS

D22

VSS

D25

VSS

D27

VSS

D29

VSS

D31

VSS

D33

VSS

D35

VSS

D4

VSS

D7

VSS

E1

VSS

E10

VSS

E13

VSS

E16

VSS

E4

VSS

E7

VSS

F10

VSS

F11

VSS

F12

VSS

F14

VSS

F15

VSS

F17

VSS

F18

VSS

F20

VSS

F21

VSS

F23

VSS

F24

VSS

F26

VSS

F28

VSS

F30

VSS

F32

VSS

F34

VSS

F4

VSS

F6

VSS

F7

VSS

F8

VSS

F9

VSS

G1

VSS

G11

VSS

G2

VSS

G27

VSS

G29

VSS

G3

VSS

G31

VSS

G33

VSS

G35

VSS

G4

VSS

G5

VSS

H10

VSS

H26

VSS

H6

VSS

H7

VSS

J11

VSS

J26

VSS

J28

VSS

J30

VSS

J32

VSS

J34

VSS

J6

VSS

K1

VSS

NTEL_HASWELL_HA SWELL

I

JCPU1G

7 OF 9

CONN@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS_SENSE

RSVD

K10 K2 K29 K3 K31 K33 K35 K4 K5 K7 K8 K9 L11 L26 L6 M11 M26 M28 M30 M32 M34 M6 N1 N10 N2 N29 N3 N31 N33 N35 N4 N5 N6 N7 N9 P11 P26 P5 R11 R26 R28 R30 R32 R34 R5 T1 T10 T29 T3 T31 T33 T35 T4 T6 T7 T9 U11 U27 V11 V28 V30 V32 V34 W1 W10 W3 W35 W4 W6 W7 W9 Y11 H11 AL24 F19 T26 AK35 AK33

VSSSENSE <46,9>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

CPU-VSS

LA-9371P

1

10 53Friday, September 28, 2012

0.2

5

Populate RD1, De-Populate RD7 for Intel DDR3 VREFDQ multiple methods M1 Populate RD7, De-Populate RD1 for Intel DDR3

10U_0603_6.3V6M

CD14

1U_0402_6.3V6K

CD24

S

1

2

G

2

10U_0603_6.3V6M

@

13

D

+1.35V

1

CD15

+

2

SGA000 04400

VREFDQ multiple methods M3

QD1

QD1 2N7002K W_SOT 323-3

2N7002K W_SOT 323-3

1 2

RD24 1K_040 2_1%RD24 1K_040 2_1%

All VREF traces should have 10 mil trace width

CD16

CD16 330U_B2 _2.5VM_R 15M

330U_B2 _2.5VM_R 15M

+DIMM_A_D Q

2.2U_0402_6.3V6M

0.1U_0402_16V4Z

1K_0402_1%

1

12

CD3

CD4

RD23

2

DDR_CK E0_DIMMA<6>

DDR_A_ BS2<6>

M_CLK_A _DDR0<6> M_CLK_A _DDR#0<6>

DDR_A_ BS0<6>

DDR_A_ WE#<6> DDR_A_ CAS#<6>

DDR_CS 1_DIMMA#<6>

+3VS

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

1

+0.675VS

CD28

1

CD27

2

RUN_ON_CPU1 .5VS3< 12,9>

+1.35V

1U_0402_6.3V6K

1

CD5

2

+1.35V

10U_0603_6.3V6M

CD10

CD9

1

2

Layout Note: Place near JDIMM1.203,204

+0.675VS

1U_0402_6.3V6K

1

2

+DIMM01_V REF_D Q

Layout Note: Place near JDIMM1

1U_0402_6.3V6K

1

CD7

CD6

2

10U_0603_6.3V6M

CD11

1

2

1U_0402_6.3V6K

1

CD22

CD21

2

1U_0402_6.3V6K

1

CD8

2

10U_0603_6.3V6M

CD13

CD12

1

2

1U_0402_6.3V6K

1

CD23

2

D D

DDR_A_ D[0..63]<6>

DDR_A_ DQS[0..7]<6>

DDR_A_ DQS#[0..7 ]<6>

DDR_A_ MA[0..15]<6>

C C

B B

A A

4

JDIMM1 H=5.2 mm TOP

+1.35V +1.35V

JDIMM1

1 3

DDR_A_ D0 DDR_A_ D1

DDR_A_ D2 DDR_A_ D3

DDR_A_ D8 DDR_A_ D9 DDR_A_ D13

DDR_A_ DQS#1 DDR_A_ DQS1

DDR_A_ D10 DDR_A_ D11

DDR_A_ D17

DDR_A_ DQS#2 DDR_A_ DQS2

DDR_A_ D18 DDR_A_ D19

DDR_A_ D24 DDR_A_ D25

DDR_A_ D26 DDR_A_ D27

DDR_CK E0_DIMMA

DDR_A_ BS2

DDR_A_ MA12 DDR_A_ MA9

DDR_A_ MA8 DDR_A_ MA5

DDR_A_ MA3 DDR_A_ MA1

M_CLK_A _DDR0 M_CLK_A _DDR#0

DDR_A_ MA10 DDR_A_ BS0

DDR_A_ WE# DDR_A_ CAS#

DDR_A_ MA13 DDR_CS 1_DIMMA#

DDR_A_ D32 DDR_A_ D33

DDR_A_ DQS#4 DDR_A_ DQS4

DDR_A_ D34 DDR_A_ D35

DDR_A_ D40 DDR_A_ D41

DDR_A_ D42 DDR_A_ D43

DDR_A_ D48 DDR_A_ D49

DDR_A_ DQS#6 DDR_A_ DQS6

DDR_A_ D50 DDR_A_ D51

DDR_A_ D56 DDR_A_ D57

DDR_A_ D58 DDR_A_ D59

5 7 9

11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205 207

VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1

RESET# VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST

VREF_CA VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0

EVENT# VDDSPD SA1 VTT

GND1 BOSS1

LCN_DAN0 6-K4406 -0103

CONN@

BOSS2

2

VSS

4

DDR_A_ D4

DQ4

6

DDR_A_ D5

DQ5

8

VSS

10

DDR_A_ DQS#0

DQS0#

12

DDR_A_ DQS0

DQS0

14

VSS

16

DDR_A_ D6

DQ6

18

DDR_A_ D7

DQ7

20

VSS

22

DDR_A_ D12

DQ12

24

DQ13

26

VSS

28

DM1

30

DDR3_D RAMRST# _R

32

VSS

34

DDR_A_ D14

DQ14

36

DDR_A_ D15

DQ15

38

VSS

40

DDR_A_ D20DDR_A_ D16

DQ20

42

DDR_A_ D21

DQ21

44

VSS

46

DM2

48

VSS

50

DDR_A_ D22

DQ22

52

DDR_A_ D23

DQ23

54

VSS

56

DDR_A_ D28

DQ28

58

DDR_A_ D29

DQ29

60

VSS

62

DDR_A_ DQS#3

DQS3#

64

DDR_A_ DQS3

DQS3

66

VSS

68

DDR_A_ D30

DQ30

70

DDR_A_ D31

DQ31

72

VSS

74

DDR_CK E1_DIMMA

CKE1

76

VDD

78

DDR_A_ MA15

A15

80

DDR_A_ MA14

A14

82

VDD

84

DDR_A_ MA11

A11

86

DDR_A_ MA7

A7

88

VDD

90

DDR_A_ MA6

A6

92

DDR_A_ MA4

A4

94

VDD

96

DDR_A_ MA2

A2

98

DDR_A_ MA0

A0

100

VDD

102

M_CLK_A _DDR1

CK1

104

M_CLK_A _DDR#1

CK1#

106

VDD

108

DDR_A_ BS1

BA1

110

DDR_A_ RAS#

RAS#

112

VDD

114

DDR_CS 0_DIMMA#

S0#

116

M_A_ODT 0

ODT0

118

VDD

120

M_A_ODT 1

ODT1

122

NC

124

VDD

126 128

VSS

130

DDR_A_ D36

DQ36

132

DDR_A_ D37

DQ37

134

VSS

136

DM4

138

VSS

140

DDR_A_ D38

DQ38

142

DDR_A_ D39

DQ39

144

VSS

146

DDR_A_ D44

DQ44

148

DDR_A_ D45

DQ45

150

VSS

152

DDR_A_ DQS#5

DQS5#

154

DDR_A_ DQS5

DQS5

156

VSS

158

DDR_A_ D46

DQ46

160

DDR_A_ D47

DQ47

162

VSS

164

DDR_A_ D52

DQ52

166

DDR_A_ D53

DQ53

168

VSS

170

DM6

172

VSS

174

DDR_A_ D54

DQ54

176

DDR_A_ D55

DQ55

178

VSS

180

DDR_A_ D60

DQ60

182

DDR_A_ D61

DQ61

184

VSS

186

DDR_A_ DQS#7

DQS7#

188

DDR_A_ DQS7

DQS7

190

VSS

192

DDR_A_ D62

DQ62

194

DDR_A_ D63

DQ63

196

VSS

198 200

SDA

202

SCL

204

VTT

206

GND2

208

+0.675VS

DDR3_D RAMRST# _R<12>

DDR_CK E1_DIMMA <6>

M_CLK_A _DDR1 <6> M_CLK_A _DDR#1 <6>

DDR_A_ BS1 <6> DDR_A_ RAS# <6>

DDR_CS 0_DIMMA# <6> M_A_ODT 0 <6>

+DIMM_VRE F_CA

M_A_ODT 1 <6>

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

1K_0402_1%

12

CD19

1

RD25

2

DDR_XD P_WAN_ SMBDAT <1 2,13,16,2 8,38,5> DDR_XD P_WAN_ SMBCLK <12,13,16,28 ,38,5>

RD26 1K_0402_1%RD2 6 1K_040 2_1%

CD20

1 2

1 3

D

2

3

RD6 33_04 02_5%RD6 33_ 0402_5 %

S

QD2

G

2N7002K W_SOT 323-3

RUN_ON_CPU1 .5VS3

1 2

+1.35V

+SM_VREF _CA

+1.35V

1K_0402_5%

12

RD2

CPU_DRA M_RST# <5>

20120802 Change RD6 to 33Ohm as HP's request

All VREF traces should have 10 mil trace width

+3VS

0.1U_0402_16V4Z

1

CD25

2

1

JDIMM3 H=4.0mm BOT

+DIMM_A_D Q

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

1

CD1

2

DDR_CK E2_DIMMA<6>

M_CLK_A _DDR2<6> M_CLK_A _DDR#2<6>

DDR_CS 3_DIMMA#<6>

2.2U_0402_6.3V6M

1

CD26

2

+1.35V +1.35V

JDIMM3

VREF_DQ1VSS1

DDR_A_ D0 DDR_A_ D1

CD2

DDR_A_ D2 DDR_A_ D3

DDR_A_ D8 DDR_A_ D9 DDR_A_ D13

DDR_A_ DQS#1 DDR_A_ DQS1

DDR_A_ D10 DDR_A_ D11

DDR_A_ D17

DDR_A_ DQS#2 DDR_A_ DQS2

DDR_A_ D18 DDR_A_ D19

DDR_A_ D24 DDR_A_ D25

DDR_A_ D26 DDR_A_ D27

DDR_CK E2_DIMMA

DDR_A_ BS2

DDR_A_ MA12 DDR_A_ MA9

DDR_A_ MA8 DDR_A_ MA5

DDR_A_ MA3 DDR_A_ MA1

M_CLK_A _DDR2 M_CLK_A _DDR#2

DDR_A_ MA10 DDR_A_ BS0

DDR_A_ WE# DDR_A_ CAS#

DDR_A_ MA13 DDR_CS 3_DIMMA#

DDR_A_ D32 DDR_A_ D33

DDR_A_ DQS#4 DDR_A_ DQS4

DDR_A_ D34 DDR_A_ D35

DDR_A_ D40 DDR_A_ D41

DDR_A_ D42 DDR_A_ D43

DDR_A_ D48 DDR_A_ D49

DDR_A_ DQS#6 DDR_A_ DQS6

DDR_A_ D50 DDR_A_ D51

DDR_A_ D56 DDR_A_ D57

DDR_A_ D58 DDR_A_ D59

+0.675VS +0 .675VS

VSS23DQ4 DQ05DQ5 DQ17VSS3 VSS49DQS#0 DM011DQS0 VSS513VSS6 DQ215DQ6 DQ317DQ7 VSS719VSS8 DQ821DQ12 DQ923DQ13 VSS925VSS10 DQS#127DM1 DQS129RESET# VSS1131VSS12 DQ1033DQ14 DQ1135DQ15 VSS1337VSS14 DQ1639DQ20 DQ1741DQ21 VSS1543VSS16 DQS#245DM2 DQS247VSS17 VSS1849DQ22 DQ1851DQ23 DQ1953VSS19 VSS2055DQ28 DQ2457DQ29 DQ2559VSS21 VSS2261DQS#3 DM363DQS3 VSS2365VSS24 DQ2667DQ30 DQ2769DQ31 VSS2571VSS26

CKE073CKE1 VDD175VDD2 NC177A15 BA279A14 VDD381VDD4 A12/BC#83A11

85

A9 VDD587VDD6

89

A8

91

A5 VDD793VDD8

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

GND1

FOX_AS 0A626-U4 S6-7H

FOX_AS 0A626-U4 S6-7H C

C

2 4

DDR_A_ D4

6

DDR_A_ D5

8 10

DDR_A_ DQS#0

12

DDR_A_ DQS0

14 16

DDR_A_ D6

18

DDR_A_ D7

20 22

DDR_A_ D12

24 26 28 30

DDR3_D RAMRST# _R

32 34

DDR_A_ D14

36

DDR_A_ D15

38 40

DDR_A_ D20DDR_A_ D16

42

DDR_A_ D21

44 46 48 50

DDR_A_ D22

52

DDR_A_ D23

54 56

DDR_A_ D28

58

DDR_A_ D29

60 62

DDR_A_ DQS#3

64

DDR_A_ DQS3

66 68

DDR_A_ D30

70

DDR_A_ D31

72

74

DDR_CK E3_DIMMA

76 78

DDR_A_ MA15

80

DDR_A_ MA14

82 84

DDR_A_ MA11

86

DDR_A_ MA7

A7

88 90

DDR_A_ MA6

A6

92

DDR_A_ MA4

A4

94 96

DDR_A_ MA2

A2

98

DDR_A_ MA0

A0

100 102

M_CLK_A _DDR3

CK1

104

M_CLK_A _DDR#3

CK1#

106

VDD12

108

DDR_A_ BS1

BA1

110

DDR_A_ RAS#

RAS#

112

VDD14

114

DDR_CS 2_DIMMA#

S0#

116

M_A_ODT 2

ODT0

118

VDD16

120

M_A_ODT 3

ODT1

122

NC2

124

VDD18

126

VREF_CA

128

VSS28

130

DDR_A_ D36

DQ36

132

DDR_A_ D37

DQ37

134

VSS30

136

DM4

138

VSS31

140

DDR_A_ D38

DQ38

142

DDR_A_ D39

DQ39

144

VSS33

146

DDR_A_ D44

DQ44

148

DDR_A_ D45

DQ45

150

VSS35

152

DDR_A_ DQS#5

DQS#5

154

DDR_A_ DQS5

DQS5

156

VSS38

158

DDR_A_ D46

DQ46

160

DDR_A_ D47

DQ47

162

VSS40

164

DDR_A_ D52

DQ52

166

DDR_A_ D53

DQ53

168

VSS42

170

DM6

172

VSS43

174

DDR_A_ D54

DQ54

176

DDR_A_ D55

DQ55

178

VSS45

180

DDR_A_ D60

DQ60

182

DDR_A_ D61

DQ61

184

VSS47

186

DDR_A_ DQS#7

DQS#7

188

DDR_A_ DQS7

DQS7

190

VSS50

192

DDR_A_ D62

DQ62

194

DDR_A_ D63

DQ63

196

VSS52

198

EVENT#

200

DDR_XD P_WAN_ SMBDAT

SDA

202

DDR_XD P_WAN_ SMBCLK

SCL

204

VTT2

206

GND2

ONN@

DDR_CK E3_DIMMA <6>

M_CLK_A _DDR3 <6> M_CLK_A _DDR#3 <6 >

DDR_CS 2_DIMMA# <6> M_A_ODT 2 <6>

M_A_ODT 3 <6>

2.2U_0402_6.3V6M

1

2

+DIMM_VRE F_CA

0.1U_0402_16V4Z

CD17

1

2

CD18

Standard

Reverse

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Dat a

2012/06/11 2013/06 /11

Deciphered Date

Compal Electronics, Inc.

Title

DDRIII DIMM1&2

Size Document Number Rev

Custom

LA-9371P

Date: Sheet

LA-9371P

1

of

11 53Friday, Septem ber 28, 2 012

of

11 53Friday, Septem ber 28, 2 012

of

11 53Friday, Septem ber 28, 2 012

0.2

5

Populate RD4, De-Populate RD8 for Intel DDR3 VREFDQ multiple methods M1 Populate RD8, De-Populate RD4 for Intel DDR3 VREFDQ multiple methods M3

+DIMM_B_D Q

2.2U_0402_6.3V6M

D D

All VREF traces should

10U_0603_6.3V6M

1

2

1

@

CD43

+

2

have 10 mil trace width

CD44

CD44 330U_B2 _2.5VM_R 15M

330U_B2 _2.5VM_R 15M

DDR_B_ D[0..63]<6>

DDR_B_ DQS[0..7]<6>

DDR_B_ DQS#[0..7 ]<6>

DDR_B_ MA[0..15]<6>

Layout Note: Place near JDIMM2

+1.35V

1U_0402_6.3V6K

+1.35V

10U_0603_6.3V6M

1

2

+0.675VS

1U_0402_6.3V6K

1

CD33

2

10U_0603_6.3V6M

CD38

CD37

1

2

Layout Note: Place near JDIMM2.203,204

1U_0402_6.3V6K

1

CD49

2

C C

B B

A A

1U_0402_6.3V6K

1

CD34

CD36

CD35

2

10U_0603_6.3V6M

CD39

CD41

CD42

CD40

1

2

1U_0402_6.3V6K

1

2

CD52

CD51

CD50

2

2.2U_0402_6.3V6M

0.1U_0402_16V4Z

CD31

1

CD32

2

DDR_CK E0_DIMMB<6>

DDR_B_ BS2<6>

M_CLK_B _DDR0<6> M_CLK_B _DDR#0<6>

DDR_B_ BS0<6>

DDR_B_ WE#<6> DDR_B_ CAS#<6>

DDR_CS 1_DIMMB#<6>

+3VS

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

CD56

1

CD55

2

4

JDIMM2 H=9.2mm TOP

+1.35V +1.35V

DDR_B_ D0 DDR_B_ D1

DDR_B_ D2 DDR_B_ D3

DDR_B_ D8 DDR_B_ D9

DDR_B_ DQS#1 DDR_B_ DQS1

DDR_B_ D10 DDR_B_ D11

DDR_B_ D16 DDR_B_ D17

DDR_B_ DQS#2 DDR_B_ DQS2

DDR_B_ D18 DDR_B_ D19

DDR_B_ D24 DDR_B_ D25

DDR_B_ D26 DDR_B_ D27

DDR_CK E0_DIMMB

DDR_B_ BS2

DDR_B_ MA12 DDR_B_ MA9

DDR_B_ MA8 DDR_B_ MA5

DDR_B_ MA3 DDR_B_ MA1

M_CLK_B _DDR0 M_CLK_B _DDR#0

DDR_B_ MA10 DDR_B_ BS0

DDR_B_ WE# DDR_B_ CAS#

DDR_B_ MA13 DDR_CS 1_DIMMB#

DDR_B_ D32 DDR_B_ D33

DDR_B_ DQS#4 DDR_B_ DQS4

DDR_B_ D34 DDR_B_ D35

DDR_B_ D40 DDR_B_ D41

DDR_B_ D42 DDR_B_ D43

DDR_B_ D48 DDR_B_ D49

DDR_B_ DQS#6 DDR_B_ DQS6

DDR_B_ D50 DDR_B_ D51

DDR_B_ D56 DDR_B_ D57

DDR_B_ D58 DDR_B_ D59

+0.675VS

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

JDIMM2

VREF_DQ1VSS1 VSS23DQ4 DQ05DQ5 DQ17VSS3 VSS49DQS#0 DM011DQS0 VSS513VSS6 DQ215DQ6 DQ317DQ7 VSS719VSS8 DQ821DQ12 DQ923DQ13 VSS925VSS10 DQS#127DM1 DQS129RESET# VSS1131VSS12 DQ1033DQ14 DQ1135DQ15 VSS1337VSS14 DQ1639DQ20 DQ1741DQ21 VSS1543VSS16 DQS#245DM2 DQS247VSS17 VSS1849DQ22 DQ1851DQ23 DQ1953VSS19 VSS2055DQ28 DQ2457DQ29 DQ2559VSS21 VSS2261DQS#3 DM363DQS3 VSS2365VSS24 DQ2667DQ30 DQ2769DQ31 VSS2571VSS26

CKE073CKE1 VDD175VDD2 NC177A15 BA279A14 VDD381VDD4 A12/BC#83A11 A985A7 VDD587VDD6 A889A6 A591A4 VDD793VDD8 A395A2 A197A0 VDD999VDD10 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST

VREF_CA VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0

EVENT# VDDSPD SA1 VTT1

G1

LCN_DAN0 6-K4806 -0103

LCN_DAN0 6-K4806 -0103 C

C

ONN@

Reverse

3

RUN_ON_CPU1 .5VS3< 11,9>

+DIMM23_V REF_D Q

2 4

DDR_B_ D4

6

DDR_B_ D5

8 10

DDR_B_ DQS#0

12

DDR_B_ DQS0

14 16

DDR_B_ D6

18

DDR_B_ D7

20 22

DDR_B_ D12

24

DDR_B_ D13

26 28 30

DDR3_D RAMRST# _R

32 34

DDR_B_ D14

36

DDR_B_ D15

38 40

DDR_B_ D20

42

DDR_B_ D21

44 46 48 50

DDR_B_ D22

52

DDR_B_ D23

54 56

DDR_B_ D28

58

DDR_B_ D29

60 62

DDR_B_ DQS#3

64

DDR_B_ DQS3

66 68

DDR_B_ D30

70

DDR_B_ D31

72

74

DDR_CK E1_DIMMB

76 78

DDR_B_ MA15

80

DDR_B_ MA14

82 84

DDR_B_ MA11

86

DDR_B_ MA7

88 90

DDR_B_ MA6

92

DDR_B_ MA4

94 96

DDR_B_ MA2

98

DDR_B_ MA0

100 102

M_CLK_B _DDR1

CK1

104

M_CLK_B _DDR#1

CK1#

106

VDD12

108

DDR_B_ BS1

BA1

110

DDR_B_ RAS#

RAS#

112

VDD14

114

DDR_CS 0_DIMMB#

S0#

116

M_B_ODT 0

ODT0

118

VDD16

120

M_B_ODT 1

ODT1

122

NC2

124

VDD18

126 128

VSS28

130

DDR_B_ D36

DQ36

132

DDR_B_ D37

DQ37

134

VSS30

136

DM4

138

VSS31

140

DDR_B_ D38

DQ38

142

DDR_B_ D39

DQ39

144

VSS33

146

DDR_B_ D44

DQ44

148

DDR_B_ D45

DQ45

150

VSS35

152

DDR_B_ DQS#5

DQS#5

154

DDR_B_ DQS5

DQS5

156

VSS38

158

DDR_B_ D46

DQ46

160

DDR_B_ D47

DQ47

162

VSS40

164

DDR_B_ D52

DQ52

166

DDR_B_ D53

DQ53

168

VSS42

170

DM6

172

VSS43

174

DDR_B_ D54

DQ54

176

DDR_B_ D55

DQ55

178

VSS45

180

DDR_B_ D60

DQ60

182

DDR_B_ D61

DQ61

184

VSS47

186

DDR_B_ DQS#7

DQS#7

188

DDR_B_ DQS7

DQS7

190

VSS50

192

DDR_B_ D62

DQ62

194

DDR_B_ D63

DQ63

196

VSS52

198 200

SDA

202

SCL

204

VTT2

206

G2

+0.675VS

20120710 Change by HP's request

DDR3_D RAMRST# _R <11 >

DDR_CK E1_DIMMB <6>

M_CLK_B _DDR1 <6> M_CLK_B _DDR#1 <6 >

DDR_B_ BS1 <6> DDR_B_ RAS# <6>

DDR_CS 0_DIMMB# <6> M_B_ODT 0 <6>

+DIMM_VRE F_CA

M_B_ODT 1 <6>

2.2U_0402_6.3V6M

CD47

1

2

DDR_XD P_WAN_ SMBDAT <1 1,13,16,2 8,38,5> DDR_XD P_WAN_ SMBCLK <11,13,16,28 ,38,5>

G

2

QD3

QD3 2N7002K W_SOT 323-3

2N7002K W_SOT 323-3

13

D

S

D

S

1 2

+1.35V

RD27 1K_04 02_1%RD27 1K_04 02_1%

All VREF traces should have 10 mil trace width

0.1U_0402_16V4Z

CD48

1

2

+DIMM_B_D Q

1K_0402_1%

12

RD28

2.2U_0402_6.3V6M

0.1U_0402_16V4Z

CD29

1

CD30

2

DDR_CK E2_DIMMB<6>

M_CLK_B _DDR2<6> M_CLK_B _DDR#2<6>

DDR_CS 3_DIMMB#<6>

+3VS

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

CD54

1

CD53

2

JDIMM4 H=4.0mm BOT

+1.35V +1.35V

DDR_B_ D0 DDR_B_ D1

DDR_B_ D2 DDR_B_ D3

DDR_B_ D8 DDR_B_ D9

DDR_B_ DQS#1 DDR_B_ DQS1

DDR_B_ D10 DDR_B_ D11

DDR_B_ D16 DDR_B_ D17

DDR_B_ DQS#2 DDR_B_ DQS2

DDR_B_ D18 DDR_B_ D19

DDR_B_ D24 DDR_B_ D25

DDR_B_ D26 DDR_B_ D27

DDR_CK E2_DIMMB

DDR_B_ BS2

DDR_B_ MA12 DDR_B_ MA9

DDR_B_ MA8 DDR_B_ MA5

DDR_B_ MA3 DDR_B_ MA1

M_CLK_B _DDR2 M_CLK_B _DDR#2

DDR_B_ MA10 DDR_B_ BS0

DDR_B_ WE# DDR_B_ CAS#

DDR_B_ MA13 DDR_CS 3_DIMMB#

DDR_B_ D32 DDR_B_ D33

DDR_B_ DQS#4 DDR_B_ DQS4

DDR_B_ D34 DDR_B_ D35

DDR_B_ D40 DDR_B_ D41

DDR_B_ D42 DDR_B_ D43

DDR_B_ D48 DDR_B_ D49

DDR_B_ DQS#6 DDR_B_ DQS6

DDR_B_ D50 DDR_B_ D51

DDR_B_ D56 DDR_B_ D57

DDR_B_ D58 DDR_B_ D59

+0.675VS

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97 99

FOX_AS 0A626-U4 RN-7F

JDIMM4

CONN@

VREF DQ Vss DQ0 DQ1 Vss DM0 Vss DQ2 DQ3 Vss DQ8 DQ9 Vss DQS1# DQS1 Vss DQ10 DQ11 Vss DQ16 DQ17 Vss DQS2# DQS2 Vss DQ18 DQ19 Vss DQ24 DQ25 Vss DM3 Vss DQ26 DQ27 Vss

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST Vss DQ32 DQ33 Vss DQS4# DQS4 Vss DQ34 DQ35 Vss DQ40 DQ41 Vss DM5 Vss DQ42 DQ43 Vss DQ48 DQ49 Vss DQS6# DQS6 Vss DQ50 DQ51 Vss DQ56 DQ57 Vss DM7 Vss DQ58 DQ59 Vss SA0 VDD SPD SA1 Vtt

GND

DQS0#

RESET#

DQS3#

VREF CA

DQS5#

DQS7#

EVENT#

2

Vss

4

DDR_B_ D4

DQ4

6

DDR_B_ D5

DQ5

8

Vss

10

DDR_B_ DQS#0

12

DDR_B_ DQS0

DQS0

14

Vss

16

DDR_B_ D6

DQ6

18

DDR_B_ D7

DQ7

20

Vss

22

DDR_B_ D12

DQ12

24

DDR_B_ D13

DQ13

26

Vss

28

DM1

30

DDR3_D RAMRST# _R

32

Vss

34

DDR_B_ D14

DQ14

36

DDR_B_ D15

DQ15

38

Vss

40

DDR_B_ D20

DQ20

42

DDR_B_ D21

DQ21

44

Vss

46

DM2

48

Vss

50

DDR_B_ D22

DQ22

52

DDR_B_ D23

DQ23

54

Vss

56

DDR_B_ D28

DQ28

58

DDR_B_ D29

DQ29

60

Vss

62

DDR_B_ DQS#3

64

DDR_B_ DQS3

DQS3

66

Vss

68

DDR_B_ D30

DQ30

70

DDR_B_ D31

DQ31

72

Vss

74

DDR_CK E3_DIMMB

CKE1

76

VDD

78

DDR_B_ MA15

A15

80

DDR_B_ MA14

A14

82

VDD

84

DDR_B_ MA11

A11

86

DDR_B_ MA7

A7

88

VDD

90

DDR_B_ MA6

A6

92

DDR_B_ MA4

A4

94

VDD

96

DDR_B_ MA2

A2

98

DDR_B_ MA0

A0

100

VDD

102

M_CLK_B _DDR3

CK1

104

M_CLK_B _DDR#3

CK1#

106

VDD

108

DDR_B_ BS1

BA1

110

DDR_B_ RAS#

RAS#

112

VDD

114

DDR_CS 2_DIMMB#

S0#

116

M_B_ODT 2

ODT0

118

VDD

120

M_B_ODT 3

ODT1

122

NC

124

VDD

126 128

Vss

130

DDR_B_ D36

DQ36

132

DDR_B_ D37

DQ37

134

Vss

136

DM4

138

Vss

140

DDR_B_ D38

DQ38

142

DDR_B_ D39

DQ39

144

Vss

146

DDR_B_ D44

DQ44

148

DDR_B_ D45

DQ45

150

Vss

152

DDR_B_ DQS#5

154

DDR_B_ DQS5

DQS5

156

Vss

158

DDR_B_ D46

DQ46

160

DDR_B_ D47

DQ47

162

Vss

164

DDR_B_ D52

DQ52

166

DDR_B_ D53

DQ53

168

Vss

170

DM6

172

Vss

174

DDR_B_ D54

DQ54

176

DDR_B_ D55

DQ55

178

Vss

180

DDR_B_ D60

DQ60

182

DDR_B_ D61

DQ61

184

Vss

186

DDR_B_ DQS#7

188

DDR_B_ DQS7

DQS7

190

Vss

192

DDR_B_ D62

DQ62

194

DDR_B_ D63

DQ63

196

Vss

198 200

DDR_XD P_WAN_ SMBDAT

SDA

202

DDR_XD P_WAN_ SMBCLK

SCL

204

Vtt

GND

+0.675VS

206

DDR_CK E3_DIMMB <6>

M_CLK_B _DDR3 <6> M_CLK_B _DDR#3 <6 >

DDR_CS 2_DIMMB# <6> M_B_ODT 2 <6>

+DIMM_VRE F_CA

M_B_ODT 3 <6>

2.2U_0402_6.3V6M

CD45

1

2

0.1U_0402_16V4Z

CD46

1

2

1

Reverse

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

Compal Secret Dat a

2012/06/11 2013/06 /11

Deciphered Date

Compal Electronics, Inc.

Title

DDRIII DIMM3&4

Size Document Number Rev

Custom

LA-9371P

Date: Sheet

LA-9371P

1

of

12 5 3Friday, Septe mber 28 , 2012

of

12 5 3Friday, Septe mber 28 , 2012

of

12 5 3Friday, Septe mber 28 , 2012

0.2

5

+RTCVCC

330K_0402_5%

12

RH6

PCH_INTVRMEN

D D

INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE High - Enable Internal VRs Low - Enable External VRs

USB_OC0#_R<17>

USB_OC1#_R<17>

USB_OC2#<17>

USB_OC3#<17>

USB_OC4#_R<17>

dGPU_HPD_INTR<17,35>

LED_LINK_LAN#_R<17,29>

USB_OC7#<17>

mSATA_DET#<18,23>

PCH_GPIO37<18> KBL_DET#<18,38> DGPU_PRSNT#<18,35> FN14<15> FN15<15>

PCH_GPIO8<18> Sec_HDD_DET<18> PM_RSMRST#<14,30>

#4/18 change by HP requirement

+3VS

1 2

RH29 10K_0402_5%@RH29 10K_0402_5%@

NO REBOOT STRAP

DISABLED WHEN LOW (DEFAULT) ENABLED WHEN HIGH

1 2

RH33 100K_0402_5%RH33 100K_0402_5%

20120802 HP's request

C C

B B

HDA_SYNC Isolation Circuit

HDA_SPKR

+3V_PCH

RH30

HDD_HALTLED

CMOS_CLR1

Shunt Clear CMOS

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

1 2

RH30

FLASH DESCRIPTOR SECURITY OVERRIDE

LOW = DESABLED (DEFAULT) HIGH = ENABLED

CMOS setting

Keep CMOS

TPM setting

Keep ME RTC Registers

+5VS

G

2

QH2

S

SB000002X00

BSS138W-7-F_SOT323-3

RH43

RH43 1M_0402_5%

1M_0402_5%

PLT_RST#<14,25,28,29,30,35,37,39,5> BAT_GRNLED# <30,39>

1

D

1 2

5

G

QH11B

4 3

S

MESS84DW-G_SC88-6

+RTCVCC

2

1 2

13

HDA_SYNCHDA_SYNC_R

D

2.2K_0402_5%

2

G

QH11A

1 6

S

MESS84DW-G_SC88-6

1

@

ME1 SHORT PADS

CH15 1U_0402_6.3V6KCH15 1U_0402_6.3V6K

RTC Circuit

RH233

1 2

1K_0402_5%

+BATT1.1+RTCVCC +3VDS

W=20mils

1 2 3 4

ACES_50273-0020N-001

CONN@

A A

W=20mils

CH102

1

1U_0603_10V4Z

2

Place near PCH

D40

1

DAN202U_SC70

5

2

3

+BATT_D

W=20mils

4

USB_OC0#_R USB_OC1#_R USB_OC2# USB_OC3# USB_OC4#_R dGPU_HPD_INTR LED_LINK_LAN#_R USB_OC7# SG_IN FN9 mSATA_DET# PCH_GPIO37 KBL_DET# DGPU_PRSNT# FN14 FN15 PCH_GPIO8 Sec_HDD_DET PM_RSMRST# RSMRST#_XDP PLT_RST# RESET_OUT#_R

HDA_SDOUT

D

20120709 Change by HP request

20120919 Change QH11 to PMOS

1 2

RH34 20K_0402_5%RH34 20K_0402_5%

1 2

RH35 1M_0402_5%RH35 1M_0402_5%

1 2

RH36 20K_0402_5%RH36 20K_0402_5%

+3V_PCH

#4/18 change by HP requirement

JBATT1

1 2 G1 G2

4

RH4 33_0402_5%PXDP@ RH4 33_0402_5%PXDP@ RH5 33_0402_5%PXDP@ RH5 33_0402_5%PXDP@ RH7 33_0402_5%PXDP@ RH7 33_0402_5%PXDP@ RH8 33_0402_5%PXDP@ RH8 33_0402_5%PXDP@ RH3 33_0402_5%PXDP@ RH3 33_0402_5%PXDP@ RH9 33_0402_5%PXDP@ RH9 33_0402_5%PXDP@ RH10 33_0402_5%PXDP@ RH10 33_0402_5%PXDP@ RH11 33_0402_5%PXDP@ RH11 33_0402_5%PXDP@ RH12 33_0402_5%PXDP@ RH12 33_0402_5%PXDP@ RH13 33_0402_5%PXDP@ RH13 33_0402_5%PXDP@ RH14 33_0402_5%PXDP@ RH14 33_0402_5%PXDP@ RH15 33_0402_5%PXDP@ RH15 33_0402_5%PXDP@ RH17 33_0402_5%PXDP@ RH17 33_0402_5%PXDP@ RH18 33_0402_5%PXDP@ RH18 33_0402_5%PXDP@ RH19 33_0402_5%PXDP@ RH19 33_0402_5%PXDP@ RH20 33_0402_5%PXDP@ RH20 33_0402_5%PXDP@ RH21 33_0402_5%PXDP@ RH21 33_0402_5%PXDP@ RH22 33_0402_5%PXDP@ RH22 33_0402_5%PXDP@ RH23 1K_0402_1%PXDP@ RH23 1K_0402_1%PXDP@ RH25 1K_0402_1%PXDP@ RH25 1K_0402_1%PXDP@

WWAN_DET#<25>

1

@

CMOS1 SHORT PADS

CH16

CMOS place near DIMM

2

1 2

1U_0402_6.3V6K

RH39 51_0402_1%

@

1 2

RH40

@

1 2

RH41

@

1 2

RH44

@

2012/09/21 HP's request

HDA_BITCLK_AUDIO<26>

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

12

200_0402_5%

HDA_SDOUT_AUDIO<26>

HDA_SYNC_AUDIO<26>

HDA_RST_AUDIO#<26>

1 2

RH28 10M_0402_5%RH28 10M_0402_5%

18P_0402_50V8J

1

CH13

2

YH1

RH230 0_0402_5%RH230 0_0402_5%

20120703

1

OSC4OSC

NC3NC

2

1 2

PCH_RTCRST#<14>

100_0402_1%

12

@

XDP_FN0 XDP_FN1 XDP_FN2 XDP_FN3 XDP_FN4 XDP_FN5 XDP_FN6 XDP_FN7 XDP_FN8 XDP_FN9 XDP_FN10 XDP_FN11 XDP_FN12 XDP_FN13 XDP_FN14 XDP_FN15 XDP_FN16 XDP_FN17

32.768K 12.5PF Q13MC1462001700

12

RH46

HDD_HALTLED<39>

100_0402_1%

RH47

@

1

CH14

CH14 18P_0402_50V8J

18P_0402_50V8J

2

HDA_SPKR<26>

HDA_SDI0<26>

ISO_PREP#<33,36>

100_0402_1%

12

@

27P_0402_50V8J

1

2

3

DDR_XDP_WAN_SMBDAT<11,12,16,28,38,5> DDR_XDP_WAN_SMBCLK<11,12,16,28,38,5>

PCH_RTCX1

PCH_RTCX2

PCH_RTCX1

PCH_RTCX2

SRTCRST#

INTRUDER#

PCH_INTVRMEN

PCH_RTCRST#

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDI0

HDA_SDOUT

HDD_HALTLED

ISO_PREP#

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

1 2

RH45 0_0402_5%RH45 0_0402_5%

RH48

1 2

3

HDA_SDOUT

HDA_SYNC_R

HDA_RST#

HDA_BIT_CLK

RH50 33_0402_5%RH50 33_0402_5%

RH51 33_0402_5%RH51 33_0402_5%

RH52 33_0402_5%RH52 33_0402_5%

RH53 33_0402_5%RH53 33_0402_5%

@CH17

@

CH17

2

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

BC8

SATA_PRX_DTX_N0

BE8

SATA_PRX_DTX_P0

AW8

SATA_PTX_DRX_N0

AY8

SATA_PTX_DRX_P0

BC10

SATA_PRX_DTX_N1

BE10

SATA_PRX_DTX_P1

AV10

SATA_PTX_DRX_N1

AW10

SATA_PTX_DRX_P1

BB9

SATA_PRX_DTX_N2

BD9

SATA_PRX_DTX_P2

AY13

SATA_PTX_DRX_N2

AW13

SATA_PTX_DRX_P2

BC12

SATA_PRX_DTX_N3

BE12

SATA_PRX_DTX_P3

AR13

SATA_PTX_DRX_N3

AT13

SATA_PTX_DRX_P3

BD13

SATA_PRX_DTX_N4

BB13

SATA_PRX_DTX_P4

AV15

SATA_PTX_DRX_N4

AW15

SATA_PTX_DRX_P4

BC14

SATA_PRX_DTX_N5

BE14

SATA_PRX_DTX_P5

AP15

SATA_PTX_DRX_N5

AR15

SATA_PTX_DRX_P5

AY5

SATA_COMP

AP3

SATA_ACT#

AT1

SG_IN

AU2

FN9

BD4

SATA_IREF

BA2

BB2

SATA_COMP

PCH XDP

JXDP2

1 2

RH42 0_0402_5%RH42 0_0402_5%

1 2

+3V_PCH

0.1U_0402_16V4Z

1

CH12

2

PXDP@

1 2

PXDP@

ON/OFFBTN#<14,30,5>

RH37

10K_0402_5%

+3VS

UH1A

B5

RTCX1

B4

RTCX2

B9

SRTCRST#

A8

INTRUDER#

G10

INTVRMEN

D9

RTCRST#

B25

HDA_BCLK

A22

HDA_SYNC

AL10

SPKR

C24

HDA_RST#

L22

HDA_SDI0

K22

HDA_SDI1

G22

HDA_SDI2

F22

HDA_SDI3

A24

HDA_SDO

B17

DOCKEN#/GPIO33

C22

HDA_DOCK_RST #/GPIO13

AB3

JTAG_TCK

AD1

JTAG_TMS

AE2

JTAG_TDI

AD3

JTAG_TDO

F8

PCH_TP25

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

TP25

C26

TP22

AB6

TP20

LYNXPOINT_BGA695

PXDP@

RH24 0_0402_5%

RH26 0_0402_5%

1 2

PXDP@

1 2

PXDP@

RH27 0_0402_5%

RH38

RH38 10K_0402_5%

10K_0402_5%

1 2

LPT_PCH_M_EDS

JTAGRTC AZALIA

2012/06/11 2013/06/11

DDR_XDP_WAN_SMBDAT_R2 DDR_XDP_WAN_SMBCLK_R2

REV = 5

SATA

1 OF 11

Compal Secret Data

Deciphered Date

+3V_PCH

XDP_FN0 XDP_FN1

XDP_FN2 XDP_FN3

XDP_FN4 XDP_FN5

XDP_FN6 XDP_FN7

RSMRST#_XDP ON/OFFBTN#_XDP

SATA_RXN_0 SATA_RXP_0

SATA_TXN_0 SATA_TXP_0

SATA_RXN_1 SATA_RXP_1

SATA_TXN_1 SATA_TXP_1

SATA_RXN_2 SATA_RXP_2

SATA_TXN_2 SATA_TXP_2

SATA_RXN_3 SATA_RXP_3

SATA_TXN_3 SATA_TXP_3

SATA_RXN4/PERN1 SATA_RXP4/PERP1

SATA_TXN4/PETN1 SATA_TXP4/PETP1

SATA_RXN5/PERN2 SATA_RXP5/PERP2

SATA_TXN5/PETN2 SATA_TXP5/PETP2

SATA_RCOMP

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

SATA_IREF

TP9

TP8

SATA Impedance Compensation

CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins.

2

1

2

GND1

4

OBSFN_C0 OBSFN_C1

GND3 OBSDATA_C0 OBSDATA_C1

GND5 OBSDATA_C2 OBSDATA_C3

GND7

OBSFN_D0 OBSFN_D1

GND9 OBSDATA_D0 OBSDATA_D1

GND11 OBSDATA_D2 OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

CONN@

SATA_PRX_DTX_N0 <23> SATA_PRX_DTX_P0 <23>

SATA_PTX_DRX_N0 <23> SATA_PTX_DRX_P0 <23>

SATA_PRX_DTX_N1 <23> SATA_PRX_DTX_P1 <23>

SATA_PTX_DRX_N1 <23> SATA_PTX_DRX_P1 <23>

SATA_PRX_DTX_N2 <33> SATA_PRX_DTX_P2 <33>

SATA_PTX_DRX_N2 <33> SATA_PTX_DRX_P2 <33>

SATA_PRX_DTX_N3 <33> SATA_PRX_DTX_P3 <33>

SATA_PTX_DRX_N3 <33> SATA_PTX_DRX_P3 <33>

SATA_PRX_DTX_N4 <23> SATA_PRX_DTX_P4 <23>

SATA_PTX_DRX_N4 <23> SATA_PTX_DRX_P4 <23>

SATA_PRX_DTX_N5 <23> SATA_PRX_DTX_P5 <23>

SATA_PTX_DRX_N5 <23> SATA_PTX_DRX_P5 <23>

1 2

R463 10K_0402_5%R463 10K_0402_5%

SATA_ACT# <33,39>

SG_IN <22>

T72PAD~D @T72PAD~D @

+1.5VS

RH497.5K_0402_1% RH497.5K_0402_1%

Title

Size Document Number Rev

Custom

Date: Sheet of

XDP_FN16

6

XDP_FN17

8 10

XDP_FN8

12

XDP_FN9

14 16

XDP_FN10

18

XDP_FN11

20 22 24 26 28

XDP_FN12

30

XDP_FN13

32 34

XDP_FN14

36

XDP_FN15

38 40 42 44 46

RESET_OUT#_R

48

XDP_DBRESET#

50 52

PCH_JTAG_TDO

TD0

54 56

PCH_JTAG_TDI

TDI

58

PCH_JTAG_TMSPCH_JTAG_TCK

60

+1.5VS

1 2

+3VS

10K_0402_5%

PLT_RST#

Compal Electronics, Inc.

PCH-RTC,HDA,SATA,XDP

LA-9371P

RH237

+3VS

1

+1.05VS

+3V_PCH

XDP_DBRESET# <14,5>

0.1U_0402_16V4Z

1

CH103

2

PXDP@

HDD_Primary

ODD

DOCK_SATA2

DOCK_SATA3

HDD_Secondary

mSATA

+3VS

UMA@

13

D

Q70

2

2N7002KW _SOT323-3

G

S

13 53Friday, September 28, 2012

12

10K_0402_5%

10K_0402_5% R7

R7

12

10K_0402_5%

10K_0402_5% R8

R8

0.2

5

+3V_PCH

1 2

RH63 10K_ 0402_5%RH63 10K_0 402_5%

1 2

RH64 10K_ 0402_5%RH64 10K_0 402_5%

1 2

RH72 10K_ 0402_5%RH72 10K_0 402_5%

1 2

RH75 10K_ 0402_5%RH75 10K_0 402_5%

+3VS

D D

XDP_DBRE SET#<13,5>

VCC1_PW RGD<3 0>

DMI_CTX_PRX _N0<4> DMI_CTX_PRX _N1<4>

DMI_CTX_PRX _N2<4> DMI_CTX_PRX _N3<4>

DMI_CTX_PRX _P0<4> DMI_CTX_PRX _P1<4>

DMI_CTX_PRX _P2<4>

C C

PCH_PW ROK_R

B B

A A

DMI_CTX_PRX _P3<4>

DMI_CRX_P TX_N0<4> DMI_CRX_P TX_N1<4>

DMI_CRX_P TX_N2<4> DMI_CRX_P TX_N3<4>

DMI_CRX_P TX_P0<4> FDI_CSYNC <4> DMI_CRX_P TX_P1<4>

DMI_CRX_P TX_P2<4> DMI_CRX_P TX_P3<4>

+1.5VS

SUSACK#<30>

PM_PWR OK<30,5>

PM_APW ROK<30,31>

PM_DRAM_P WRGD<5>

PM_RSMRST#<13 ,30>

SUS_PW R_ACK<30>

ON/OFFBTN#

AC_PRES_ OUT<30,35>

20120911 Change BT_OFF to GPIO61

1 2

RH78 8.2K _0402_5%RH78 8.2K _0402_5%

1 2

RH70 1 0K_0402_5 %RH70 10K_040 2_5%

PCH_DPW ROK

RH246

@ RH246

@

1 2

0_0402_ 5%

20120810 HP's request

1 2

RH88 0_04 02_5%RH8 8 0_0402_5 %

1 2

RH90 7.5K _0402_1%RH90 7.5K _0402_1%

SIO_SLP _SUS# SUSACK #

1 2

RH92 0_04 02_5%RH9 2 0_0402_5 %

1 2

RH93 0_04 02_5%RH9 3 0_0402_5 %

1 2

RH221 0 _0402_5%RH221 0 _0402_5%

1 2

RH94

1 2

RH95 0_0402_5 %RH95 0_0402 _5%

1 2

RH97 0_0402_5%RH97 0 _0402_5%

SLP_W LAN#<25,44>

20120913 Delete UH7, RH235. Move RH236, CH106 to page 31

SUS_PW R_ACK

PCH_PCIE_ WAKE#

PCH_RI#

BT_OFF

PM_CLKRUN #

SLP_LAN #

1 2

RH54 0_04 02_5%RH5 4 0_0402_5 %

1 2

RH67 0_04 02_5%RH6 7 0_0402_5 %

DMI_CTX_PRX _N0 DMI_CTX_PRX _N1

DMI_CTX_PRX _N2 DMI_CTX_PRX _N3

DMI_CTX_PRX _P0 DMI_CTX_PRX _P1

DMI_CTX_PRX _P2 DMI_CTX_PRX _P3

DMI_CRX_P TX_N0 DMI_CRX_P TX_N1

DMI_CRX_P TX_N2 DMI_CRX_P TX_N3

DMI_CRX_P TX_P0 DMI_CRX_P TX_P1

DMI_CRX_P TX_P2 DMI_CRX_P TX_P3

DMI_IREF

DMI_RCOMP

20120911 HP's request

1 2

@

R230 0_0402_5%

@T90

@

T150 PAD~D@ T150 PAD~D@

T90

0_0402_ 5%

PAD~D

SYS_RESE T#

SYS_PW ROK_R

PCH_PW ROK

PM_APW ROK_R

PM_DRAM_P WRGD_R

PCH_RSMRST# _R

ME_SUS_P WR_ACK_R

ON/OFFBTN#

AC_PRES_ OUT

GPIO72

PCH_RI#

SLP_W LAN#

SYS_RESE T#

PM_RSMRST#

UH1B

AW22

DMI_RXN_0

AR20

DMI_RXN_1

AP17

DMI_RXN_2

AV20

DMI_RXN_3

AY22

DMI_RXP_0

AP20

DMI_RXP_1

AR17

DMI_RXP_2

AW20

DMI_RXP_3

BD21

DMI_TXN_0

BE20

DMI_TXN_1

BD17

DMI_TXN_2

BE18

DMI_TXN_3

BB21

DMI_TXP_0

BC20

DMI_TXP_1

BB17

DMI_TXP_2

BC18

DMI_TXP_3

BE16

DMI_IREF

AW17

TP12

AV17

TP7

AY17

DMI_RCOMP

R6

SUSACK#

AM1

SYS_RESET#

AD7

SYS_PWROK

F10

PWROK

AB7

APWROK

H3

DRAMPWROK

J2

RSMRST#

J4

SUSWARN#/SUSPWRNACK/GPIO30

K1

PWRBTN#

E6

ACPRESENT/GPIO31

K7

BATLOW#/GPIO72

N4

RI#

AB10

TP21

D2

SLP_WLAN#/GPIO29

LYNXPOINT_B GA695

PCH_RTCRST#<13>

20120920 Add ME debug circuit for HP's request

LPT_PCH_M_EDS

DMI

System Power

Management

2 OF 11

4

+3VDS

SLP_S3#

SLP_S5# SLP_S4# SIO_SLP _A#

PCH_RTCRST#

ON/OFFBTN#

SYS_RESE T#

FCI_1005 1922-1410E LF

REV = 5

AJ35

FDI_RXN_0

AL35

FDI_RXN_1

AJ36

FDI_RXP_0

FDI

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

FDI_RXP_1

TP16

TP15

TP10

FDI_CSYNC

FDI_INT

FDI_IREF

TP17

TP13

FDI_RCOMP

DSWVRMEN

DPWROK

WAKE#

CLKRUN#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN#

AL36

AV43

AY45

TP5

AV45

AW44

AL39

AL40

AT45

AU42

AU44

AR44

C8

L13

K3

AN7

U7

Y6

Y7

C6

H1

F3

F1

AY3

G5

Boot BIOS Strap

PCH_GPIO51

SATA1GP/ GPIO19

0 1 Reserved (NAND)

1 0

JME1

1

2

3

4

5

6

7

16

7

G2

8

15

8

G1

9

10

11

12

13

14

CONN@

FDI_CTX_PRX _N0

FDI_CTX_PRX _N1

FDI_CTX_PRX _P0

FDI_CTX_PRX _P1

FDI_CSYNC

FDI_INT

FDI_IREF

RH86 0_04 02_5%RH8 6 0_0402_5 %

FDI_RCOMP

DSWODV REN

PCH_DPW ROK

PCH_PCIE_ WAKE#

PM_CLKRUN #

BT_OFF

SUSCLK_K BC

SLP_S5#

SLP_S4#

SLP_S3#

SIO_SLP _A#

SIO_SLP _SUS#

H_PM_SYNC

SLP_LAN #

Boot BIOS Location

00 LPC

1 2

PCI

FDI_CTX_PRX _N0 <7>

FDI_CTX_PRX _N1 <7>

FDI_CTX_PRX _P0 <7>

FDI_CTX_PRX _P1 <7>

FDI_INT <4>

+1.5VS

12

+1.5VS

RH897. 5K_0402_1 % RH897 .5K_0402_ 1%

PCH_PCIE_ WAKE# <25,39 >

PM_CLKRUN # <28,30 ,32>

BT_OFF <25>

20120911 HP request

SUSCLK_K BC <30>

T85 PAD~D @T85 PAD~D@

@

T86 PAD ~D

SLP_S4# <44>

SLP_S3# <30,31,34 ,39,44,9>

SIO_SLP _A# <30 ,31,45>

T88 PAD ~D

@

SIO_SLP _SUS# <34>

T89 PAD~D

@

H_PM_SYNC <5>

SLP_LAN # <29, 30>

3

DSWODV REN

1 2

RH98 150_ 0402_1%RH98 1 50_0402_1 %

1 2

RH99 150_ 0402_1%RH99 1 50_0402_1 %

1 2

RH100 1 50_0402_ 1%RH100 150_ 0402_1%

1 2

RH101 1 00K_0402 _5%RH101 1 00K_0402 _5%

PCH_CRT_BLU<36>

PCH_CRT_GRN<36>

PCH_CRT_RED<36>

PCH_CRT_DDC_ CLK<3 6>

PCH_CRT_DDC_ DAT<36>

PCH_CRT_HSYNC<36>

PCH_CRT_VSYN C<36 >

BKL_PW M_PCH<35>

PANEL_B KEN_PCH<35>

DGPU_HOL D_RST#<35 >

DGPU_SEL ECT#<35,36 >

DGPU_PW R_EN<15,35>

+3VS

Camera_ON<22>

CR_SX_W ARN#<3 9>

20120718 Add QH12 to invertion PCH_GPIO56 signal 20120723 Delete QH12 as HP's request

PCH_CRT_BLU

PCH_CRT_GRN

PCH_CRT_RED

PCH_CRT_DDC_ CLK

PCH_CRT_DDC_ DAT

1 2

DGPU_HOL D_RST#

DGPU_SELECT#

DGPU_PW R_EN

1 2

Camera_ON

CR_SX_W ARN#

20120723

HSYNC

VSYNC

CRT_IREF

BKL_PW M_PCH

ENVDD_PCH

PCI_PIRQA #

PCI_PIRQB #

PCI_PIRQC #

PCI_PIRQD #

PCH_GPIO 51

20120920

RH84 2 0_0402_1%RH84 20_0 402_1%

RH85 2 0_0402_1%RH85 20_0 402_1%

RH87 6 49_0402_1 %RH87 64 9_0402_1 %

ENVDD_PCH<35>

RH147 1 00K_0402 _5%RH147 1 00K_0402 _5%

+RTCVCC

330K_0402_5%

RH55

1 2

PCH_CRT_BLU

PCH_CRT_GRN

PCH_CRT_RED

ENVDD_PCH

T45

VGA_BLUE

U44

VGA_GREEN

V45

VGA_RED

M43

VGA_DDC_CLK

M45

VGA_DDC_DATA

N42

VGA_HSYNC

N44

VGA_VSYNC

U40

DAC_IREF

U39

VGA_IRTN

N36

EDP_BKLTCTL

K36

EDP_BKLTEN

G36

EDP_VDDEN

H20

PIRQA#

L20

PIRQB#

K17

PIRQC#

M20

PIRQD#

A12

GPIO50

B13

GPIO52

C12

GPIO54

C10

GPIO51

A10

GPIO53

AL6

GPIO55

LYNXPOINT_B GA695

2

DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT) LOW = DISABLED

A16 SWAP OVERRIDE STRAP

STP_A16OVR

LPT_PCH_M_EV

LVDSCRT

5 OF 11

PCI

LOW = A16 SWAP OVERRIDE HIGH = DEFAULT

REV = 5UH1E

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPD_CTRLCLK

DDPD_CTRLDATA

DISPLAY

PLTRST#

MC74VHC1G 08DFT2G_SC70 -5

R40

R39

R35

R36

N40

N38

H45

DDPB_AUXN

K43

DDPC_AUXN

J42

DDPD_AUXN

H43

DDPB_AUXP

K45

DDPC_AUXP

J44

DDPD_AUXP

K40

DDPB_HPD

K38

DDPC_HPD

H39

DDPD_HPD

G17

PIRQE#/GPIO2

F17

PIRQF#/GPIO3

L15

PIRQG#/GPIO4

M15

PIRQH#/GPIO5

AD10

PME#

Y11

PLTRST#

20120810 HP's request

1

2

PWRSV_ SEL#

ODD_DA#

NMI_SMI_DB G#

ACCEL_INT_ R#

PLTRST#

+3V_PCH

0.1U_040 2_16V4Z

5

IN1

VCC

IN2

GND

3

1

PCI_PIRQA #

PCI_PIRQB #

PCI_PIRQC #

PCI_PIRQD #

PWRSV_ SEL#

DGPU_HOL D_RST#

DGPU_PW R_EN

ODD_DA#

NMI_SMI_DB G#

PCH_CRT_DDC_ CLK

PCH_CRT_DDC_ DAT

DGPU_SEL ECT#

Camera_ON

ACCEL_INT_ R#

CR_SX_W ARN#

20120705 Correct net name to follow GPIO table

PWRSV_ SEL# <37>

ODD_DA# <23>

NMI_SMI_DB G# <30>

12

T87 PAD~D@T87 PAD~D@

CH20

1 2

UH3

OUT

RH960_0402 _5% RH960_0402 _5%

4

PLT_RST#

1

@

CH107

22P_040 2_50V8J

2

20120713 Add for ESD's request

PLT_RST# <13,25,2 8,29,30,35 ,37,39,5>

12

RH568.2K_040 2_5% RH568.2K_ 0402_5%

12

RH578.2K_040 2_5% RH578.2K_ 0402_5%

12

RH598.2K_040 2_5% RH598.2K_ 0402_5%

12

RH608.2K_040 2_5% RH608.2K_ 0402_5%

12

RH6210K_ 0402_5% RH621 0K_0402_ 5%

12

RH6610K_ 0402_5% RH661 0K_0402_ 5%

12

RH6910K_ 0402_5% RH691 0K_0402_ 5%

12

RH7110K_ 0402_5% RH711 0K_0402_ 5%

12

RH74100K_0402_5 % RH74100K_0402_5 %

12

20120920 HP's request

RH762.2K _0402_5% RH762.2K _0402_5%

12

RH772.2K _0402_5% RH772.2K _0402_5%

12

RH8010K_ 0402_5% RH801 0K_0402_ 5%

12

RH8210K_ 0402_5% RH821 0K_0402_ 5%

12

RH838.2K _0402_5% RH838 .2K_0402_ 5%

12

RH24510K_040 2_5% RH24510K_0 402_5%

20120723 HP's request

ACCEL_INT# <28>

+3VS

11 SPI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Numb er Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCH -DMI,FDI,PM,DP,CRT

LA-9371P

1

of

14 53Friday, Septemb er 28, 2012

0.2

5

D D

4

3

2

+3V_PCH

10K_0402_5%

RH106

1

1 2

GFX_CLK_REQ#

FN14<13> FN15<13>

+3V_PCH

CLK_PCIE_CR#<39> CLK_PCIE_CR<39>

+3VS

CR_CLK_REQ#<39>

CLK_TB_REFCLK#<39>

CLK_TB_REFCLK<39>

+3VS

C C

B B

TB_CLKREQ#<39>

+3V_PCH

CLK_PCIE_EXP#<39> CLK_PCIE_EXP<39>

CLKREQ_EXP#<39>

+3V_PCH CLK_PCIE_LAN#< 29> CLK_PCIE_LAN<29>

CLK_PCIE_LAN_REQ1#<29>

CLK_PCI_DEBUG_KBC<30>

+3V_PCH CLK_PCIE_MINI1#<25>

CLK_PCIE_MINI1<25>

+3V_PCH

MINI1_CLKREQ#< 25>

CLK_PCI_KBC<30> CLK_PCI_SIO<32>

CLK_PCI_TPM<28>

CLK_PCI_DEBUG<25>

FN14 FN15

RH104 10K_0402_5%RH104 10K _0402_5%

RH105 10K_0402_5%RH105 10K _0402_5% RH203 0_0402_5%RH203 0_0402_5%

RH113 10K_0402_5%RH113 10K _0402_5% RH205 0_0402_5%RH205 0_0402_5%

RH118 10K_0402_5%RH118 10K _0402_5%

RH121 10K_0402_5%RH121 10K _0402_5%

RH125 10K_0402_5%RH125 10K _0402_5%

RH128 10K_0402_5%RH128 10K _0402_5%

RH131 10K_0402_5%RH131 10K _0402_5%

RH135 10_0402_5%RH135 10_0402_5% RH137 10_0402_5%RH137 10_0402_5%

RH138 22_0402_5%RH138 22_0402_5%

RH139 22_0402_5%RH139 22_0402_5%

RH141 22_0402_5%RH141 22_0402_5%

RH234 22_0402_5%RH234 22_0402_5%

12

20120911 HP's request

12 12

20120911 HP's request

12 12

12

20120911 HP's request

12

20120911 HP's request

12

20120911 HP's request

12

12 12

12

CLK_PCIE_CR# CLK_PCIE_CR

FN14

CLK_TB_REFCLK#

CLK_TB_REFCLK

FN15

CLK_PCIE_EXP# CLK_PCIE_EXP CLKREQ_EXP#

CLK_PCIE_LAN# CLK_PCIE_LAN

CLK_PCIE_LAN_REQ1#

CLK_PCIE_MINI1#

CLK_PCIE_MINI1

MINI1_CLKREQ#

CLK_PCI0

PCI_LOOPBACKOUTCLK_PCI_LOOPBACK

CLK_PCI2

CLK_PCI4

UH1C

Y43

CLKOUT_PCIE_N_0

Y45

CLKOUT_PCIE_P_0

AB1

PCIECLKRQ0#/GPIO73

AA44

CLKOUT_PCIE_N_1

AA42

CLKOUT_PCIE_P_1

AF1

PCIECLKRQ1#/GPIO18

AB43

CLKOUT_PCIE_N_2

AB45

CLKOUT_PCIE_P_2

AF3

PCIECLKRQ2#/GPIO20/SMI#

AD43

CLKOUT_PCIE_N_3

AD45

CLKOUT_PCIE_P_3

T3

PCIECLKRQ3#/GPIO25

AF43

CLKOUT_PCIE_N_4

AF45

CLKOUT_PCIE_P_4

V3

PCIECLKRQ4#/GPIO26

AE44

CLKOUT_PCIE_N5

AE42

CLKOUT_PCIE_P_5

AA2

PCIECLKRQ5#/GPIO44

AB40

CLKOUT_PCIE_N_6

AB39

CLKOUT_PCIE_P_6

AE4

PCIECLKRQ6#/GPIO45

AJ44

CLKOUT_PCIE_N_7

AJ42

CLKOUT_PCIE_P_7

Y3

PCIECLKRQ7#/GPIO46

AH43

CLKOUT_ITPXDP

AH45

CLKOUT_ITPXDP_P

D44

CLKOUT_33MHZ0

E44

CLKOUT_33MHZ1

B42

CLKOUT_33MHZ2

F41

CLKOUT_33MHZ3

A40

CLKOUT_33MHZ4

CLOCK SIGNAL

LPT_PCH_M_EDS

LYNXPOINT_BGA695

2 OF 11

REV = 5

CLKOUT_PEG_A

CLKOUT_PEG_A_P

PEGA_CLKRQ#/GPIO47

CLKOUT_PEG_B

CLKOUT_PEG_B_P

PEGB_CLKRQ#/GPIO56

CLKOUT_DMI

CLKOUT_DMI_P

CLKOUT_DP

CLKOUT_DP_P

CLKOUT_DPNS

CLKOUT_DPNS_P

CLKIN_DMI

CLKIN_DMI_P

CLKIN_GND

CLKIN_GND_P

CLKIN_DOT96N

CLKIN_DOT96P

CLKIN_SATA

CLKIN_SATA_P

REFCLK14IN

CLKIN_33MHZLOOPBACK

XTAL25_IN

XTAL25_OUT

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

ICLK_IREF

TP19 TP18

DIFFCLK_BIASREF

AB35

CLK_PCIE_VGA#

AB36

CLK_PCIE_VGA

AF6

GFX_CLK_REQ#

20120703 Follow HP's GPIO table

Y39

Y38

U4

WLAN_TRAMSIT_OFF#

AF39

CLK_CPU_DMI#

AF40

CLK_CPU_DMI

AJ40

CLK_CPU_SSC_DPLL#

AJ39

CLK_CPU_SSC_DPLL

AF35

CLK_CPU_DPLL#

AF36

CLK_CPU_DPLL

AY24

CLK_BUF_DMI#

AW24

CLK_BUF_DMI

AR24

CLK_BUF_BCLK#

AT24

CLK_BUF_BCLK

H33

CLK_BUF_DOT96#

G33

CLK_BUF_DOT96

BE6

CLK_BUF_CKSSCD#

BC6

CLK_BUF_CKSSCD

F45

CLK_PCH_14M

D17

CLK_PCI_LOOPBACK

AM43 AL44

20120807 Corret pin name as Intel's specification

C40

F38

SIO_14M

F36

F39

AM45

ICLK_IREF

AD39 AD38

AN44

PCH_CLK_BIASREF

CLK_PCIE_VGA# <35>

CLK_PCIE_VGA <35>

RH109

10K_0402_5%

WLAN_TRAMSIT_OFF# <25>

CLK_CPU_DMI# <5>

CLK_CPU_DMI <5>

CLK_CPU_SSC_DPLL# <5>

CLK_CPU_SSC_DPLL <5>

CLK_CPU_DPLL# <5>

CLK_CPU_DPLL <5>

T91PAD~D @T91PAD~D @

T92PAD~D @T92PAD~D @

1 2

12

RH1400_0402_5% RH1400_0402_5%

RH1427.5K_0402_1% RH1427.5K_0402_1%

RH136 22_0402_5%RH136 22_0402_5%

2

1 3

D

Q55

XTAL25_IN XTAL25_OUT

CLK_SIO_14M <32>

Q55

12

+3V_PCH

+1.5VS

DGPU_PWR_EN <14,35>

G

2N7002KW_SOT323-3

S

PEG_CLK_REQ# <35>

RH132 1M_0402_5%RH132 1M_0402_5%

25MHZ_20PF_7A25000012

18P_0402_50V8J

1

2

1 2

CH21

YH2

12

18P_0402_50V8J

1

CH22

2

PCIECLK REQ Pull UP Power Rail: SUS Rail : 0 3 4 5 6 7 Core Rail: 1 2

A A

CLK_BUF_DMI# CLK_BUF_DMI

CLK_BUF_BCLK# CLK_BUF_BCLK

CLK_BUF_DOT96# CLK_BUF_DOT96

CLK_BUF_CKSSCD# CLK_BUF_CKSSCD

CLK_PCH_14M

1 2

RH108 10K_0402_5%R H108 10K_0402_5%

1 2

RH110 10K_0402_5%R H110 10K_0402_5%

1 2

RH111 10K_0402_5%R H111 10K_0402_5%

1 2

RH112 10K_0402_5%R H112 10K_0402_5%

1 2

RH115 10K_0402_5%R H115 10K_0402_5%

1 2

RH117 10K_0402_5%R H117 10K_0402_5%

1 2

RH119 10K_0402_5%R H119 10K_0402_5%

1 2

RH120 10K_0402_5%R H120 10K_0402_5%

1 2

RH123 10K_0402_5%R H123 10K_0402_5%

CLOCK TERMINATION for FCIM and need close to PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

PCH- CLK

LA-9371P

1

15 53Friday, September 28, 2012

0.2

of

5

D D

+3VS

1 2

RH145 10K_0402_5%RH145 10K_0402_5%

C C

PCH_SPI_CLK<30>

PCH_SPI_CS0#<30>

PCH_SPI_SI<30>

PCH_SPI_SO<30>

PCH_SPI_WP#<30>

PCH_SPI_HOLD#<30>

B B

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

PCH_SPI_SO

PCH_SPI_WP#

PCH_SPI_HOLD#

SIRQ

LPC_LAD0<25,28,30,32>

LPC_LAD1<25,28,30,32>

LPC_LAD2<25,28,30,32>

LPC_LAD3<25,28,30,32>

LPC_LFRAME#<25,28,30,32>

LPC_LDRQ0#<32>

SIRQ<28,30,32>

1 2

RH154

1 2

RH155 4.99_0402_1%RH155 4.99_0402_1%

RH156

RH157 4.99_0402_1%RH157 4.99_0402_1%

RH243

RH244

LPC_LAD0

LPC_LAD1

LPC_LAD2

LPC_LAD3

LPC_LFRAME#

SIRQ

PCH_SPI_CLK_R

4.99_0402_1%

PCH_SPI_CS0#_R

12

PCH_SPI_SI_R

4.99_0402_1%

12

PCH_SPI_SO_R

12

PCH_SPI_WP#_R

15_0402_5%

12

PCH_SPI_HOLD#_R

15_0402_5%

20120719 HP's request 20120726 HP's request

A20

LAD_0

C20

LAD_1

A18

LAD_2

C18

LAD_3

B21

LFRAME#

D21

LDRQ0#

G20

LDRQ1#/GPIO23

AL11

SERIRQ

AJ11

SPI_CLK

AJ7

SPI_CS0#

AL7

SPI_CS1#

AJ10

SPI_CS2#

AH1

SPI_MOSI

AH3

SPI_MISO

AJ4

SPI_IO2

AJ2

SPI_IO3

LYNXPOINT_BGA695

4

LPT_PCH_M_EDS

REV = 5UH1D

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK

CL_DATA

CL_RST#

TD_IREF

N7

R10

U11

N8

U8

R7

H6

K6

N11

AF11

AF10

AF7

BA45

TP1

BC45

TP2

BE43

TP4

BE44

TP3

AY43

SMBus

SPILPC

4 OF 11

C-Link

Thermal

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

3

FPR_OFF

MEM_SMBCLK

MEM_SMBDATA

DDR_RST_EN

LAN_SMBCLK

LAN_SMBDATA

NFC_RST#

SML1_SMBCLK

SML1_SMBDATA

CL_CLK1

CL_DATA1

CL_RST1#

1 2

PCH_TD_IREF

RH158 8.2K_0402_1%RH158 8.2K_0402_1%

FPR_OFF <28>

DDR_RST_EN <5>

LAN_SMBCLK <29>

LAN_SMBDATA <29>

NFC_RST# <39>

20120703 Add for NFC

CL_CLK1 <25>

CL_DATA1 <25>

CL_RST1# <25>

MEM_SMBCLK

MEM_SMBDATA

LAN_SMBCLK

LAN_SMBDATA

SML1_SMBCLK

SML1_SMBDATA

+3VS

3 4

QH3B

+3VS

DMN66D0LDW-7_SOT363-6

2

6 1

DMN66D0LDW-7_SOT363-6

QH10A

@

2

6 1

DMN66D0LDW-7_SOT363-6

QH3A

5

DMN66D0LDW-7_SOT363-6

5

QH10B

@

3 4

DMN66D0LDW-7_SOT363-6

QH9A

2

QH9B

34

DMN66D0LDW-7_SOT363-6

5

FPR_OFF

MEM_SMBCLK

MEM_SMBDATA

DDR_RST_EN

NFC_RST#

SML1_SMBCLK

SML1_SMBDATA

LAN_SMBCLK

LAN_SMBDATA

@

RH238

2.2K_0402_5%

@

RH239

2.2K_0402_5%

61

12

RH14310K_0402_5% RH14310K_0402_5%

12

RH1442.2K_0402_5% RH1442.2K_0402_5%

12

RH1462.2K_0402_5% RH1462.2K_0402_5%

12

RH1482.2K_0402_5% RH1482.2K_0402_5%

12

RH14910K_0402_5% RH14910K_0402_5%

1 2

RH1502.2K_0402_5% RH1502.2K_0402_5%

1 2

RH1512.2K_0402_5% RH1512.2K_0402_5%

12

RH1522.2K_0402_5% RH1522.2K_0402_5%

12

RH1532.2K_0402_5% RH1532.2K_0402_5%

DDR_XDP_WAN_SMBCLK <11,12,13,28,38,5>

DDR_XDP_WAN_SMBDAT <11,12,13,28,38,5>

12

+3VS

NFC_3S_SMBCLK <39>

12

+3VS

NFC_3S_SMBDAT <39>

20120703 Add for NFC 20120920 Uninstall QH10, RH238, RH239

PCH_KBC_I2CLK <30,35>

+3V_PCH

PCH_KBC_I2CDAT <30,35>

+3V_PCH

1

+3V_PCH

20120807 Change RH148 to 2.2K as HP's request

20120703 Add RH149 for NFC

+3VM_LAN

Screw Hole

H19

H18

H17

H5

H3

H_3P0

HOLEA

@

1

H28

H27

H24

H_3P0

HOLEA

20120709 Delete by HP's request

ZZZ2

ZZZ1

A A

45@

DCIN

PCB

MB

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

@

1

H42

H43

H_3P0

HOLEA

@

1

2012/06/11 2013/06/11

H_3P0

HOLEA

@

1

@

1

H34

H_6P0X7P0

HOLEA

@

1

H_3P0

HOLEA

@

1

H38

H_3P0

HOLEA

1

Compal Secret Data

@

Stand Off CPU Bracket

H11

H33

H20

H21

H10

H9

H_3P3

HOLEA

@

1

H4

H1

H_3P8

HOLEA

@

1

H30

H15

H_3P8

HOLEA

@

1

Deciphered Date

2

H_3P3

HOLEA

@

1

H8

H6

H_3P8

HOLEA

@

1

H39

H_3P8

HOLEA

@

1

H_4P0

H_3P3

HOLEA

@

1

H7

H_3P8

HOLEA

1

@

1

H37

H_2P1N

HOLEA

1

FD1

FD1 FIDUCIAL_C40M80

FIDUCIAL_C40M80

FD3

FD3 FIDUCIAL_C40M80

FIDUCIAL_C40M80

H13

H12

H_4P0

H_3P7

HOLEA

@

1

H46

H41

H_2P6X2P1N

H_3P3N

HOLEA

@

1

@

1

@

1

FD2

FD2 FIDUCIAL_C40M80

FIDUCIAL_C40M80

1

FD4

FD4 FIDUCIAL_C40M80

FIDUCIAL_C40M80

1

Title

Size Document Number Rev

Custom

Date: Sheet of

Keyboard

H14

H_4P0

HOLEA

1

@

H32

H_6P0

HOLEA

@

H36

H_3P6X2P1N

HOLEA

@

1

@

1

Travel BATT

H44

H_3P0N

HOLEA

@

1

Compal Electronics, Inc.

PCH - SPI, SMBUS,LPC

LA-9371P

H26

H_6P0

HOLEA

1

H45

H_3P0N

HOLEA

1

@

0.2

16 53Friday, September 28, 2012

0.2

5

D D

PCIE_PRX_DTX_N1<39> PCIE_PRX_DTX_P1<39>

PCIE_PTX_C_DRX_N1<39> PCIE_PTX_C_DRX_P1<39>

PCIE_PRX_DTX_N2<39> PCIE_PRX_DTX_P2<39>

PCIE_PTX_C_DRX_N2<39> PCIE_PTX_C_DRX_P2<39>

ThunderBolt

C C

Express card slot

GIGA LAN

WLAN

Card Reader

B B

PCIE_PRX_DTX_N3<39> PCIE_PRX_DTX_P3<39>

PCIE_PTX_C_DRX_N3<39> PCIE_PTX_C_DRX_P3<39>

PCIE_PRX_DTX_N4<39> PCIE_PRX_DTX_P4<39>

PCIE_PTX_C_DRX_N4<39> PCIE_PTX_C_DRX_P4<39>

PCIE_PRX_EXPTX_N5<39> PCIE_PRX_EXPTX_P5<39>

PCIE_PTX_EXPRX_N5<39> PCIE_PTX_EXPRX_P5<39>

PCIE_PRX_DTX_N6<29> PCIE_PRX_DTX_P6<29>

PCIE_PTX_C_DRX_N6<29> PCIE_PTX_C_DRX_P6<29>

PCIE_PRX_DTX_N7<25> PCIE_PRX_DTX_P7<25>

PCIE_PTX_C_DRX_N7<25> PCIE_PTX_C_DRX_P7<25>

PCIE_PRX_DTX_N8<39> PCIE_PRX_DTX_P8<39>

PCIE_PTX_C_DRX_N8<39> PCIE_PTX_C_DRX_P8<39>

1 2

CH108 0.1U_0402_10V7KCH1 08 0.1U_0402_10V7K

1 2

CH109 0.1U_0402_10V7KCH1 09 0.1U_0402_10V7K

1 2

CH110 0.1U_0402_10V7KCH1 10 0.1U_0402_10V7K

1 2

CH111 0.1U_0402_10V7KCH1 11 0.1U_0402_10V7K

1 2

CH27 0.1U_0402_10V 7KCH27 0.1U_0402_10V7K

1 2

CH28 0.1U_0402_10V 7KCH28 0.1U_0402_10V7K

1 2

CH29 0.1U_0402_10V7KCH29 0.1U_0402_10V7K

1 2

CH30 0.1U_0402_10V7KCH30 0.1U_0402_10V7K

1 2

CH100 0.1U_0402_10V7KCH100 0.1U_0402_10V7K

1 2

CH99 0.1U_0402_10V7KCH99 0.1U_0402_10V7K

1 2

CH31 0.1U_0402_10V7KCH31 0.1U_0402_10V7K

1 2

CH32 0.1U_0402_10V7KCH32 0.1U_0402_10V7K

1 2

CH33 0.1U_0402_10V 7KCH33 0.1U_0402_10V7K

1 2

CH34 0.1U_0402_10V 7KCH34 0.1U_0402_10V7K

1 2

CH35 0.1U_0402_10V7KCH35 0.1U_0402_10V7K

1 2

CH36 0.1U_0402_10V7KCH36 0.1U_0402_10V7K

+1.5VS

4

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1

PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2

PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

20120718 HP's request

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3

PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4

PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

PCIE_PRX_EXPTX_N5 PCIE_PRX_EXPTX_P5

PCIE_PTX_EXPRX_N5_C PCIE_PTX_EXPRX_P5_C

PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6

PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6

PCIE_PRX_DTX_N7 PCIE_PRX_DTX_P7

PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7

PCIE_PRX_DTX_N8 PCIE_PRX_DTX_P8

PCIE_PTX_DRX_N8 PCIE_PTX_DRX_P8

1 2

RH160 0_0402_5%RH160 0_0402_5%

1 2

RH164 7.5K_0402_1%RH164 7.5K_0402_1%

PCH_PCIE_IREF

PCH_PCIE_RCOMP

AW31

AY31

BE32 BC32

AT31

AR31

BD33 BB33

AW33

AY33

BE34 BC34

AT33

AR33

BE36 BC36

AW36

AV36

BD37 BB37

AY38

AW38

BC38 BE38

AT40 AT39

BE40 BC40

AN38 AN39

BD42 BD41

BE30

BC30

BB29

BD29

PERN1/USB3RN3 PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

PERN_3 PERP_3

PETN_3 PETP_3

PERN_4 PERP_4

PETN_4 PETP_4

PERN_5 PERP_5

PETN_5 PETP_5

PERN_6 PERP_6

PETN_6 PETP_6

PERN_7 PERP_7

PETN_7 PETP_7

PERN_8 PERP_8

PETN_8 PETP_8

PCIE_IREF

TP11

TP6

PCIE_RCOMP

L

YNXPOINT_BGA695

LPT_PCH_M_EDS

PCIe

9 OF 11

3

REV = 5UH1I

USB

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC6#/GPIO10 OC7#/GPIO14

USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7 USB2N8 USB2P8 USB2N9

USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13

USB3RN1

USB3RP1 USB3TN1 USB3TP1

USB3RN2

USB3RP2 USB3TN2 USB3TP2

USB3RN5

USB3RP5 USB3TN5 USB3TP5

USB3RN6

USB3RP6 USB3TN6 USB3TP6

USBRBIAS#

USBRBIAS

TP24 TP23

OC5#/GPIO9

B37 D37 A38 C38 A36 C36 A34 C34 B33 D33 F31 G31 K31 L31 G29 H29 A32 C32 A30 C30 B29 D29 A28 C28 G26 F26 F24 G24

AR26 AP26 BE24 BD23 AW26 AV26 BD25 BC24 AW29 AV29 BE26 BC26 AR29 AP29 BD27 BE28

K24 K26

M33 L33

P3

USB_OC0#_R

V1

USB_OC1#_R

U2

USB_OC2#

P1

USB_OC3#

M3

USB_OC4#_R

T1

dGPU_HPD_INTR

N2 M1

USB_OC7#_R

USBP0USBP0+ USBP1USBP1+

USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+ USBP8USBP8+ USBP9USBP9+ USBP10USBP10+ USBP11USBP11+ USBP12USBP12+ USBP13USBP13+

USB3RN1 USB3RP1 USB3TN1 USB3TP1 USB3RN2 USB3RP2 USB3TN2 USB3TP2 USB3RN5 USB3RP5 USB3TN5 USB3TP5 USB3RN6 USB3RP6 USB3TN6 USB3TP6

USBRBIAS

RH165 0_0402_5%

RH242 0_0402_5%RH242 0_0402_5%

USBP0- <33>

USBP0+ <33>

USBP1- <39>

USBP1+ <39>

USBP4- <39>

USBP4+ <39>

USBP5- <39>

USBP5+ <39>

USBP6- <39>

USBP6+ <39>

USBP7- <37>

USBP7+ <37>

USBP8- <28>

USBP8+ <28>

USBP9- <39>

USBP9+ <39>

USBP10- <22>

USBP10+ <22>

USBP11- <33>

USBP11+ <33>

USBP12- <25>

USBP12+ <25>

USBP13- <25>

USBP13+ <25>

USB3RN1 <33>

USB3RP1 <33 >

USB3TN1 <33>

USB3TP1 <33>

USB3RN2 <39>

USB3RP2 <39 >

USB3TN2 <39>

USB3TP2 <39>

USB3RN5 <39>

USB3RP5 <39 >

USB3TN5 <39>

USB3TP5 <39>

USB3RN6 <39>

USB3RP6 <39 >

USB3TN6 <39>

USB3TP6 <39>

1 2

@

1 2

20120718 HP's request

2

----->Docking USB 3.0

----->USB 3.0 Walkup port 1

----->NA

----->USB 3.0 Walkup port 2

----->USB 3.0 Walkup port 3

----->Express card slot

----->Smart card reader

----->Finger Print Reader

----->Walkup USB 2.0/ USB Charging port

----->USB Camera

----->Docking USB 2.0 port

----->WWAN

----->BT/WLAN Combo

----->Docking USB 3.0

----->USB 3.0 Walkup port 2

----->USB 3.0 Walkup port 5

----->USB 3.0 Walkup port 6

USB_OC0#_R <13> USB_OC1#_R <13> USB_OC2# < 13> USB_OC3# < 13> USB_OC4#_R <13>

dGPU_HPD_INTR <13,35> LED_LINK_LAN#_R <13 ,29> USB_OC7# < 13>

TB_HOT_PLUG# <39>

1

USBRBIAS

CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.

22.6_0402_1%

12

RH159

USB_OC0#_R dGPU_HPD_INTR USB_OC2# USB_OC1#_R

USB_OC4#_R USB_OC7#_R

LED_LINK_LAN#_R

USB_OC3#

+3V_PCH

RPH1

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

RPH2

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

20120702 Swap for layout routing

20120911 For DB1-R platform ID

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2012/06/11 2013/06/11

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH-PCIE,USB

LA-9371P

1

17 53Friday, September 28, 2012

0.2