COMPAL LA-8611P Schematics

A

B

C

D

E

1 1

Compal Confidential

2 2

QAWGH Schematics Document

AMD APU Trinity FS1r2 + FCH Hudson-M3 + GPU Seymourr XT

2011-10-07

3 3

4 4

A

B

REV:0.1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA8611P

LA8611P

LA8611P

151Friday, November 04, 2011

151Friday, November 04, 2011

151Friday, November 04, 2011

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Compal confidential

File Name :

1 1

LVDS
translator

RTDS2132S

QAWGH

page 24

AMD Seymour XT

VRAM
64M16/128M16
DDR3 x 4

HDMI Conn.

page 26

B

page 17 ~ 23

Gen2PCIE x 16

DP Port0

DP Port2
DP Port1

C

AMD FS1r2 APU

Trinity
uPGA 722 pin
35mm x 35mm

page 5,~9

D

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1866

ZZZ

ZZZ

LA8611P

DA_PCB

DA_PCB

DA80000S600

DA80000S600

QAWGH

LS7986P CardReader/B
LS7982P USB/B
LS7983P PWR/B
LS8612P LED/B
LS7985P ODD/B
LS8617P Cap Sensor/B

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2

page 10,11

E

4 * x1 PCI-E 2.0

LVDS Conn.

page 25

2 2

PCI Express

GPP1

USB(WiMAX)

Mini Card Slot 1

WLAN/WiMAX

3 3

page 32

GPP0

LAN

AR8161/8162

page 28~29

CRT Conn.

page 27

SPI ROM

page 13

Cap Sensor

Sub-board

FCH CRT (VGA DAC)

4 * x1 PCI-E 2.0

Touch Pad Int. KBD

page 35 page 35

x4 UMI Gen. 1

2.5GT/s per lane

Hudson M3

uFCBGA-656

24.5mm x 24.5mm

page 12~16

LPC Bus

EC

ENE KB930/ KB9012

page 34

AZALIA

4*USB3.0,10*USB2.0

6*SATA serial

SATA0

Audio Codec

CX20671-21Z

page 30

CMOS Camera
BlueTooth Conn
USB Port 3.0 x2(Left)
USB Port 2.0 x 1 (Right)

Card Reader
USB 2.0 x 1

RTS5178

Sub-board

SATA 3.0 HDD Conn.

page 25

page 31

page 31

2Channel Speaker

Internal MIC

Audio Jacks

page 37,38

Sub-board

2 in 1 Conn.

SD/SDXC/MMC

page 30

page 30

Sub-board

SATA1

SATA ODD Conn.

page 31

Thermal Sensor

EMC1403

4 4

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 32

Compal Secret Data

Compal Secret Data

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

LA8611P

LA8611P

LA8611P

251Friday, November 04, 2011

251Friday, November 04, 2011

251Friday, November 04, 2011

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Voltage Rails

Power Plane

VIN
B+
+APU_CORE
+APU_CORE_NB

1 1

+1.5V ON
+0.75VS
+1.2VS ON
+2.5VS
+1.1VALW
+1.1VS
+1.5VS
+VGA_CORE
+1.5VGS
+1.8VGS
+1.0VGS ON
+3VALW
+3V_LAN ON ON
+3VS
+5VALW
+5VS

2 2

+VSB ON ON*
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device

Smart Battery

Description

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for APU
Voltage for On-die VGA of APU

1.5V power rail for APU VDDIO and DDR

1.2V (VDDR, VDDP) switched power rail for APU

2.5V for APU VDDA

1.1V switched power rail for FCH

1.5V switched power rail

0.95-1.2V switched power rail

1.5V switched power rail

1.8V switched power rail

3.3V always on power rail

3.3V power rail for LAN

3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power

EC SM Bus2 address

Address Address

0001-011xb

HEX

15H

Device

EMC1403(VGA, DDR,WLAN)
SB-TSI (default)
VGA Thermal
Cap Sensor
RTDS2132S-E

S1 S3 S5

N/A N/A N/A

ON
ON

ON
ON ON*ON
ON
ON
ON
ON

ON

ON
ON
ON
ON
ON

1001-101xb
1001-100xb
1000-001xb
1000-0000b
1010-1000b

N/AN/AN/A

OFF

OFF
OFF OFF
ON

OFF
OFFONOFF0.75V switched power rail for DDR terminator
OFF OFF
OFF

OFF

OFF OFF1.1V switched power rail for FCH
OFF

OFF

OFFOFF
OFF

OFF
OFFONOFF
OFF OFF1.0V switched power rail for VGA
ON ON*

ON*
OFF

OFF
ON

ON*
OFF

OFF

ONON

HEX

9AH

98H

82H

80H

A8H

FCH Hudson-M2/3
SATA Port List

SATA0
SATA1
SATA2
SATA3
SATA4
SATA5

NC
HDD
ODD
NC
NC
NC

BOM Structure

UMA@ : UMA only
PX@ : DIS muxluss

CMOS@ : USB camera
HDMI@ : HDMI function
nonHDMI@ : w/o HDMI function
BT@ : BT function

Comal
PCIE Port List

LAN
WLAN
NC
NC
NC
NC
NC
NC

APUFCH

PCIE0
PCIE1
PCIE2
PCIE3
PCIE0
PCIE1
PCIE2
PCIE3

ME@ : ME components

3 3

SM Bus Controller 0

Device Address

(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)

HEX

X76@ : VRAM
45@ : 45 Level
PX4@ : PX4
PX5@ : PX5
8162@ : 10/100 LAN
GIGA@ : giga LAN
14@ : G 14"
15@ : G 15"
BBH@ : Best Buy high-end
nonBBH@ : non Best Buy high-end

SM Bus Controller 1

Device Address

DDR DIMM1 (FCH_SMB0)
DDR DIMM2 (FCH_SMB0)
WLAN (FCH_SMB0)

4 4

(FCH_SMB0)

1001-000xb
1001-001xb

HEX

90H

92H

AN@ : Apple & Nokia combo
A@ : Apple only

FCH Hudson-M2/3
USB Port List

USB1.1

Port0
Port1

USB2.0

Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port8
Port9
Port10
Port11
Port12
Port13

NC
NC

Right USB1
Right USB2
Mini PCIE
USB Camera

BT

Card Reader

NC
NC
NC

NC
USB3.0 LP1
USB3.0 LP2

NC

NC

FCH Hudson-M2/3
USB OC PIN

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#NCNC

USB3.0 (LP1, LP2)
USB2.0 (RP1)
USB2.0 (RP2)

NC
NC
NC

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Notes List

Notes List

Notes List
LA8611P

LA8611P

LA8611P

351Friday, November 04, 2011

351Friday, November 04, 2011

351Friday, November 04, 2011

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Power-Up/Down Sequence

"Seymour" has the following requirements with regards to power-supply sequencing
to avoid damaging the ASIC:

‧

All the ASIC supplies, except for VDDR3, must fully reach their respective

nominal voltages within 20 ms of the start of the ramp-up sequence, though a

D D

shorter ramp-up duration is preferred. There is no timing requirement on the
ramp up of VDDR3 relative to other power rails.

‧

The external pull-up resistors on the DDC/AUX signals (if applicable) should

ramp up before or after both VDDC and VDD_CT have ramped up.

‧

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa). For BACO
enabled designs, VDDC must ramp up before VDD_CT at system power up.

‧

For power down, reversing the ramp-up sequence is recommended

VDDR3(3.3VGS)

WithoutBACOoption:

PE_GPIO0(PXS_RST#):Low‐>ResetdGPU;High‐>Normaloperation
PE_GPIO1(PXS_PWREN):Low‐>dGPUPowerOFF;High‐>dGPUPowerON

BACOoption:

PE_GPIO0(PXS_RST#):High‐>Normaloperation(dGPUisnotresetonBACOmode)
PE_GPIO1(PXS_PWREN):Low‐>dGPUPowerOFF;High‐>dGPUPowerON(alwaysHigh)

dGPUPowerPins Maxcurrent

PCIE_PVDD,PCIE_VDDR,TSVDD,VDDR4,VDD_CT,
DPE_PVDD,DP[F:E]_VDD18,DP[D:A]_PVDD,
DP[D:A]_VDD18,AVDD,VDD1DI,A2VDDQ,VDD2DI,
DPLL_PVDD,MPV18,andSPV18

DP[F:E]_VDD10,DP[D:A]_VDD10,DPLL_VDDC,and
SPV10

PCIE_VDDC

VDDR3

BIF_VDDC(currentconsumption=55mA@1.0V,in
BACOmode)

VDDR1

VDDC/VDDCI

Voltage

1.8V

1.0V

1.0V

3.3V

Sameas
VDDC

1.5V

TBD

PX3.0

OFF

OFF

OFF

OFF

OFF

OFF

OFF

BACOMode

ON

ON

ON

ON

ON
Sameas
PCIE_VDDC

OFF

OFF

1679mA

775mA

1.1A

60mA

70mA

1.2A

28

PCIE_VDDC(1.0V)

PX4.0

C C

B B

VDDR1(1.5VGS)

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

PERSTb

REFCLK

Straps Reset

Straps Valid

Global ASIC Reset

T4+16clock

PX5.0

iGPU

iGPU

PE_GPIO0(PXS_RST#) PE_EN

PE_GPIO1(PXS_PWREN)

+3.3VALW

+1.5V

+5VLAW

PE_GPIO0(PXS_RST#)

PE_GPIO1(PXS_PWREN)

MOS

LDO

Regulator

dGPU

1

2

5

dGPU

BIF_VDDC

+3.3VGS

+1.0VGS

+1.8VGS

PX_mode

B+

BIF_VDDC

BACOSwitch

+B

Regulator

Regulator

+VGA_CORE

3

4

+1.5VGS

+VGA_CORE

PWRGOOD

+3.3VALW

MOS

+1.5V

LDO

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

+5VLAW

Deciphered Date

Deciphered Date

Deciphered Date

2

Regulator

+3.3VGS

1

+1.0VGS

2

+1.8VGS

5

Short PX_MODE and PX_PWREN

B+

Regulator

+B

Regulator

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+1.5VGS

3

+VGA_CORE

4

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

dGPU Notes List

dGPU Notes List

dGPU Notes List

LA8611P

LA8611P

LA8611P

1

451Friday, November 04, 2011

451Friday, November 04, 2011

451Friday, November 04, 2011

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PCIE_CRX_GTX_P[0..15]<17>

JCPU1A

JCPU1A

PCI EXPRESS

1 1

LAN

WLAN

2 2

PCIE_CRX_DTX_P0<28>
PCIE_CRX_DTX_N0<28>
PCIE_CRX_DTX_P1<32>
PCIE_CRX_DTX_N1<32>

UMI_RXP0<12>
UMI_RXN0<12>
UMI_RXP1<12>
UMI_RXN1<12>
UMI_RXP2<12>
UMI_RXN2<12>
UMI_RXP3<12>
UMI_RXN3<12>

+1.2VS

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15

P_ZVDDP

1 2

R1 196_0402_1%R1 196_0402_1%

AG11

AB8
AB7
AA9
AA8
AA5
AA6

AE5
AE6
AD8
AD7
AC9
AC8
AC5
AC6

AG8
AG9
AG6
AG5
AF7
AF8
AE8
AE9

Y8

Y7
W9
W8
W5
W6

V8

V7

U9

U8

U5

U6

T8

T7

R9

R8

R5

R6

P8

P7

N9

N8

N5

N6
M8
M7

P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

P_ZVDDP

PCI EXPRESS

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

GPP GRAPHICS

GPP GRAPHICS

UMI

UMI

B

P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9

P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

P_ZVSS

PCIE_CTX_C_GRX_P0

AB2

PCIE_CTX_C_GRX_N0

AB1

PCIE_CTX_C_GRX_P1

AA3

PCIE_CTX_C_GRX_N1

AA2

PCIE_CTX_C_GRX_P2

Y5

PCIE_CTX_C_GRX_N2

Y4

PCIE_CTX_C_GRX_P3

Y2

PCIE_CTX_C_GRX_N3

Y1

PCIE_CTX_C_GRX_P4

W3

PCIE_CTX_C_GRX_N4

W2

PCIE_CTX_C_GRX_P5

V5

PCIE_CTX_C_GRX_N5

V4

PCIE_CTX_C_GRX_P6

V2

PCIE_CTX_C_GRX_N6

V1

PCIE_CTX_C_GRX_P7

U3

PCIE_CTX_C_GRX_N7

U2

PCIE_CTX_C_GRX_P8

T5

PCIE_CTX_C_GRX_N8

T4

PCIE_CTX_C_GRX_P9

T2

PCIE_CTX_C_GRX_N9

T1

PCIE_CTX_C_GRX_P10

R3

PCIE_CTX_C_GRX_N10

R2

PCIE_CTX_C_GRX_P11

P5

PCIE_CTX_C_GRX_N11

P4

PCIE_CTX_C_GRX_P12

P2

PCIE_CTX_C_GRX_N12

P1

PCIE_CTX_C_GRX_P13

N3

PCIE_CTX_C_GRX_N13

N2

PCIE_CTX_C_GRX_P14

M5

PCIE_CTX_C_GRX_N14

M4

PCIE_CTX_C_GRX_P15

M2

PCIE_CTX_C_GRX_N15

M1

PCIE_CTX_C_DRX_P0

AD5

PCIE_CTX_C_DRX_N0

AD4

PCIE_CTX_C_DRX_P1

AD2

PCIE_CTX_C_DRX_N1

AD1
AC3
AC2
AB5
AB4

UMI_TXP0_C

AG2

UMI_TXN0_C

AG3

UMI_TXP1_C

AF4

UMI_TXN1_C

AF5

UMI_TXP2_C

AF1

UMI_TXN2_C

AF2

UMI_TXP3_C

AE2

UMI_TXN3_C

AE3

P_ZVSS

AH11

C1 0.1U_0402_16V7KPX@C1 0.1U_0402_16V7KPX@
C2 0.1U_0402_16V7KPX@C2 0.1U_0402_16V7KPX@
C3 0.1U_0402_16V7KPX@C3 0.1U_0402_16V7KPX@
C4 0.1U_0402_16V7KPX@C4 0.1U_0402_16V7KPX@
C5 0.1U_0402_16V7KPX@C5 0.1U_0402_16V7KPX@
C6 0.1U_0402_16V7KPX@C6 0.1U_0402_16V7KPX@
C7 0.1U_0402_16V7KPX@C7 0.1U_0402_16V7KPX@
C8 0.1U_0402_16V7KPX@C8 0.1U_0402_16V7KPX@
C9 0.1U_0402_16V7KPX@C9 0.1U_0402_16V7KPX@
C10 0.1U_0402_16V7KPX@C10 0.1U_0402_16V7KPX@
C11 0.1U_0402_16V7KPX@C11 0.1U_0402_16V7KPX@
C12 0.1U_0402_16V7KPX@C12 0.1U_0402_16V7KPX@
C13 0.1U_0402_16V7KPX@C13 0.1U_0402_16V7KPX@
C14 0.1U_0402_16V7KPX@C14 0.1U_0402_16V7KPX@
C15 0.1U_0402_16V7KPX@C15 0.1U_0402_16V7KPX@
C16 0.1U_0402_16V7KPX@C16 0.1U_0402_16V7KPX@
C17 0.1U_0402_16V7KPX@C17 0.1U_0402_16V7KPX@
C18 0.1U_0402_16V7KPX@C18 0.1U_0402_16V7KPX@
C19 0.1U_0402_16V7KPX@C19 0.1U_0402_16V7KPX@
C20 0.1U_0402_16V7KPX@C20 0.1U_0402_16V7KPX@
C21 0.1U_0402_16V7KPX@C21 0.1U_0402_16V7KPX@
C22 0.1U_0402_16V7KPX@C22 0.1U_0402_16V7KPX@
C23 0.1U_0402_16V7KPX@C23 0.1U_0402_16V7KPX@
C24 0.1U_0402_16V7KPX@C24 0.1U_0402_16V7KPX@
C25 0.1U_0402_16V7KPX@C25 0.1U_0402_16V7KPX@
C26 0.1U_0402_16V7KPX@C26 0.1U_0402_16V7KPX@
C27 0.1U_0402_16V7KPX@C27 0.1U_0402_16V7KPX@
C28 0.1U_0402_16V7KPX@C28 0.1U_0402_16V7KPX@
C29 0.1U_0402_16V7KPX@C29 0.1U_0402_16V7KPX@
C30 0.1U_0402_16V7KPX@C30 0.1U_0402_16V7KPX@
C31 0.1U_0402_16V7KPX@C31 0.1U_0402_16V7KPX@
C32 0.1U_0402_16V7KPX@C32 0.1U_0402_16V7KPX@

1 2

R2 196_0402_1%R2 196_0402_1%

C

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

C33 0.1U_0402_16V7KC33 0.1U_0402_16V7K

1 2

C34 0.1U_0402_16V7KC34 0.1U_0402_16V7K

1 2

C35 0.1U_0402_16V7KC35 0.1U_0402_16V7K

1 2

C36 0.1U_0402_16V7KC36 0.1U_0402_16V7K

1 2

C37 0.1U_0402_16V7KC37 0.1U_0402_16V7K

1 2

C38 0.1U_0402_16V7KC38 0.1U_0402_16V7K

1 2

C39 0.1U_0402_16V7KC39 0.1U_0402_16V7K

1 2

C40 0.1U_0402_16V7KC40 0.1U_0402_16V7K

1 2

C41 0.1U_0402_16V7KC41 0.1U_0402_16V7K

1 2

C42 0.1U_0402_16V7KC42 0.1U_0402_16V7K

1 2

C43 0.1U_0402_16V7KC43 0.1U_0402_16V7K

1 2

C44 0.1U_0402_16V7KC44 0.1U_0402_16V7K

1 2

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P[0..15] <17>
PCIE_CTX_GRX_N[0..15] <17>PCIE_CRX_GTX_N[0..15]<17>

PCIE_CTX_DRX_P0 <28>
PCIE_CTX_DRX_N0 <28>
PCIE_CTX_DRX_P1 <32>
PCIE_CTX_DRX_N1 <32>

UMI_TXP0 <12>
UMI_TXN0 <12>
UMI_TXP1 <12>
UMI_TXN1 <12>
UMI_TXP2 <12>
UMI_TXN2 <12>
UMI_TXP3 <12>
UMI_TXN3 <12>

D

E

3 3

Power Sequence of APU

+1.5V

+2.5VS

+1.5VS

+APU_CORE

4 4

+APU_CORE_NB

+1.2VS

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

FS1r2 PCIE/UMI

FS1r2 PCIE/UMI

FS1r2 PCIE/UMI

LA8611P

LA8611P

LA8611P

E

551Friday, November 04, 2011

551Friday, November 04, 2011

551Friday, November 04, 2011

Group A

Group B

of

of

of

0.1

0.1

0.1

A

B

C

D

E

1 1

JCPU1B

JCPU1B

MEMORY CHANNEL A

DDRA_SMA[15..0]<10>

DDRA_SBS0#<10>
DDRA_SBS1#<10>
DDRA_SBS2#<10>
DDRA_SDM[7..0]<10>

2 2

DDRA_SDQS0<10>
DDRA_SDQS0#<10>
DDRA_SDQS1<10>
DDRA_SDQS1#<10>
DDRA_SDQS2<10>
DDRA_SDQS2#<10>
DDRA_SDQS3<10>
DDRA_SDQS3#<10>
DDRA_SDQS4<10>
DDRA_SDQS4#<10>
DDRA_SDQS5<10>
DDRA_SDQS5#<10>
DDRA_SDQS6<10>
DDRA_SDQS6#<10>
DDRA_SDQS7<10>
DDRA_SDQS7#<10>

DDRA_CLK0<10>
DDRA_CLK0#<10>
DDRA_CLK1<10>
DDRA_CLK1#<10>

DDRA_CKE0<10>
DDRA_CKE1<10>

DDRA_ODT0<10>
DDRA_ODT1<10>

3 3

DDRA_SCS0#<10>
DDRA_SCS1#<10>

DDRA_SRAS#<10>
DDRA_SCAS#<10>
DDRA_SWE#<10>

MEM_MA_RST#<10>
MEM_MA_EVENT#<10>

+MEM_VREF

+1.5V

Place them close to APU within 1"

15mil

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15

DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

DDRA_CKE0
DDRA_CKE1

DDRA_ODT0
DDRA_ODT1

DDRA_SCS0#
DDRA_SCS1#

DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#

MEM_MA_RST#

MEM_MA_EVENT#

M_ZVDDIO

1 2

R3 39.2_0402_1%R3 39.2_0402_1%

M21
M22

AA25

AD27
AC23
AD19
AC15

AE26
AD26
AB22
AA22
AB18
AA18
AA14
AA15

AA27

AA26

W24
W23

W20
W21

U20
R20
R21
P22
P21
N24
N23
N20
N21

U23
L24
L21

L20
U24

U21
L23

E14

J17
E21
F25

G14
H14
G18
H18

J21
H21
E27
E26

T21
T22
R23
R24

H28
H27

Y25

V22

V21

H25
T24

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1

MA_CKE0
MA_CKE1

MA_ODT0
MA_ODT1

MA_CS_L0
MA_CS_L1

MA_RAS_L
MA_CAS_L
MA_WE_L

MA_RESET_L
MA_EVENT_L

M_VREF
M_ZVDDIO

MEMORY CHANNEL A

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39

MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

E13
J13
H15
J15
H13
F13
F15
E15

H17
F17
E19
J19
G16
H16
H19
F19

H20
F21
J23
H23
G20
E20
G22
H22

G24
E25
G27
G26
F23
H24
E28
F27

AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25

Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21

AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17

AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47

DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

DDRA_SDQ[63..0] <10>

DDRB_SMA[15..0]<11>

DDRB_SBS0#<11>
DDRB_SBS1#<11>
DDRB_SBS2#<11>
DDRB_SDM[7..0]<11>

DDRB_SDQS0<11>
DDRB_SDQS0#<11>
DDRB_SDQS1<11>
DDRB_SDQS1#<11>
DDRB_SDQS2<11>
DDRB_SDQS2#<11>
DDRB_SDQS3<11>
DDRB_SDQS3#<11>
DDRB_SDQS4<11>
DDRB_SDQS4#<11>
DDRB_SDQS5<11>
DDRB_SDQS5#<11>
DDRB_SDQS6<11>
DDRB_SDQS6#<11>
DDRB_SDQS7<11>
DDRB_SDQS7#<11>

DDRB_CLK0<11>
DDRB_CLK0#<11>
DDRB_CLK1<11>
DDRB_CLK1#<11>

DDRB_CKE0<11>
DDRB_CKE1<11>

DDRB_ODT0<11>
DDRB_ODT1<11>

DDRB_SCS0#<11>
DDRB_SCS1#<11>

DDRB_SRAS#<11>
DDRB_SCAS#<11>
DDRB_SWE#<11>

MEM_MB_RST#<11>
MEM_MB_EVENT#<11>

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

DDRB_CKE0
DDRB_CKE1

DDRB_ODT0
DDRB_ODT1

DDRB_SCS0#
DDRB_SCS1#

DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#

MEM_MB_RST#
MEM_MB_EVENT#

M28
M27
M24
M25

W26

AF25
AG22
AH18
AD14

AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14

W27

T27
P24
P25
N27
N26

L26
U26
L27
K27

K25
K24

U27
T28
K28

D14
A18
A22
C25

C15
B15
E18
D18
E22
D22
B26
A26

R26
R27
P27
P28

J26
J27

Y28
V25

Y27
V24

V27
V28

J25
T25

JCPU1C

JCPU1C

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1

MB_CKE0
MB_CKE1

MB_ODT0
MB_ODT1

MB_CS_L0
MB_CS_L1

MB_RAS_L
MB_CAS_L
MB_WE_L

MB_RESET_L
MB_EVENT_L

MEMORY CHANNEL B

MEMORY CHANNEL B

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7

MB_DATA8

MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15

MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23

MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31

MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39

MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47

MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55

MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

A14
B14
D16
E16
B13
C13
B16
A16

C17
B18
B20
A20
E17
B17
B19
C19

C21
B22
C23
A24
D20
B21
E23
B23

E24
B25
B27
D28
B24
D24
D26
C27

AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24

AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20

AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16

AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7

DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15

DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23

DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31

DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39

DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47

DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55

DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

DDRB_SDQ[63..0] <11>

EVENT# pull high 0.75V reference voltage

+1.5V

4 4

R5 1K_0402_5%R5 1K_0402_5%

1 2

R6 1K_0402_5%R6 1K_0402_5%

1 2

MEM_MA_EVENT#
MEM_MB_EVENT# +MEM_VREF

A

R4

R4

1K_0402_1%

1K_0402_1%

R7

R7

1K_0402_1%

1K_0402_1%

+1.5V

1 2

1 2

B

1

C45

C45
1000P_0402_50V7K

1000P_0402_50V7K

2

15mil

2

C46

C46

0.1U_0402_16V7K

0.1U_0402_16V7K

1

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

FS1r2 DDRIII Memory I/F

FS1r2 DDRIII Memory I/F

FS1r2 DDRIII Memory I/F

LA8611P

LA8611P

LA8611P

651Friday, November 04, 2011

651Friday, November 04, 2011

651Friday, November 04, 2011

E

of

of

of

0.1

0.1

0.1

A

Place near APU

C56 0.1U_0402_16V7KC56 0.1U_0402_16V7K

DP0_TXP0_C<24>
DP0_TXN0_C<24>

1 2

C48 0.1U_0402_16V7KC48 0.1U_0402_16V7K

1 2

Place near APU

C63 0.1U_0402_16V7KC63 0.1U_0402_16V7K

1 1

ML_VGA_TXP0<13>
ML_VGA_TXN0<13>

ML_VGA_TXP1<13>
ML_VGA_TXN1<13>

ML_VGA_TXP2<13>
ML_VGA_TXN2<13>

ML_VGA_TXP3<13>
ML_VGA_TXN3<13>

HDMI_TX2P<26>
HDMI_TX2N<26>

HDMI_TX1P<26>
HDMI_TX1N<26>

HDMI_TX0P<26>
HDMI_TX0N<26>

HDMI_CLKP<26>
HDMI_CLKN<26>

C58 0.1U_0402_16V7KHDMI@C58 0.1U_0402_16V7KHDMI@
C53 0.1U_0402_16V7KHDMI@C53 0.1U_0402_16V7KHDMI@

C59 0.1U_0402_16V7KHDMI@C59 0.1U_0402_16V7KHDMI@
C54 0.1U_0402_16V7KHDMI@C54 0.1U_0402_16V7KHDMI@

C55 0.1U_0402_16V7KHDMI@C55 0.1U_0402_16V7KHDMI@
C60 0.1U_0402_16V7KHDMI@C60 0.1U_0402_16V7KHDMI@

C61 0.1U_0402_16V7KHDMI@C61 0.1U_0402_16V7KHDMI@
C62 0.1U_0402_16V7KHDMI@C62 0.1U_0402_16V7KHDMI@

Place near Connector

2 2

Route as differential
with VSS_SENSE

3 3

APU_VDDNB_SEN_H<47>

1 2

C64 0.1U_0402_16V7KC64 0.1U_0402_16V7K

1 2

C65 0.1U_0402_16V7KC65 0.1U_0402_16V7K

1 2

C66 0.1U_0402_16V7KC66 0.1U_0402_16V7K

1 2

C67 0.1U_0402_16V7KC67 0.1U_0402_16V7K

1 2

C68 0.1U_0402_16V7KC68 0.1U_0402_16V7K

1 2

C69 0.1U_0402_16V7KC69 0.1U_0402_16V7K

1 2

C70 0.1U_0402_16V7KC70 0.1U_0402_16V7K

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

APU_CLK<12>
APU_CLK#<12>

APU_DISP_CLK<12>
APU_DISP_CLK#<12>

APU_SVC<47>
APU_SVD<47>

APU_SVT<47>

APU_RST#<12>

APU_PWRGD<12,47>

APU_PROCHOT#<12>

APU_VDD_SEN_L<47>

APU_VDD_SEN_H<47>

APU_SIC
APU_SID

APU_THERMTRIP#
ALERT_L

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

DP0_TXP0
DP0_TXN0

DP1_TXP0
DP1_TXN0

DP1_TXP1
DP1_TXN1

DP1_TXP2
DP1_TXN2

DP1_TXP3
DP1_TXN3

DP2_TXP0
DP2_TXN0

DP2_TXP1
DP2_TXN1

DP2_TXP2
DP2_TXN2

DP2_TXP3
DP2_TXN3

AE11
AD11

AB11
AA11

AG12
AH12

AF10
AB12

AC10
AE12
AF12

H10
F10

G10

B

L3
L2

K5
K4

K2
K1

J3
J2

H5
H4

H2
H1

G3
G2

F2
F1

L9
L8

L5
L6

K8
K7

J6
J5

B3
A3

C3

J10

F9
G9
H9

B4
C5
A4
A5
C4
B5

ANALOG/DISPLAY/MISC

ANALOG/DISPLAY/MISC

DP0_TXP0
DP0_TXN0

DP0_TXP1
DP0_TXN1

DP0_TXP2
DP0_TXN2

DP0_TXP3
DP0_TXN3

DP1_TXP0
DP1_TXN0

DP1_TXP1
DP1_TXN1

DP1_TXP2
DP1_TXN2

DP1_TXP3
DP1_TXN3

DP2_TXP0
DP2_TXN0

DP2_TXP1
DP2_TXN1

DP2_TXP2
DP2_TXN2

DP2_TXP3
DP2_TXN3

CLKIN_H
CLKIN_L

DISP_CLKIN_H
DISP_CLKIN_L

SVC
SVD

SVT
SIC

SID
RESET_L

PWROK
PROCHOT_L

THERMTRIP_L
ALERT_L

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

VSS_SENSE
VDDP_SENSE
VDDNB_SENSE
VDDIO_SENSE
VDD_SENSE
VDDR_SENSE

LVDS

To FCH

HDMI

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

LOTES_ACA-ZIF-109-P12-A_FS1R2ME@

JCPU1D

JCPU1D

DISPLAY PORT 0

DISPLAY PORT 0

DISPLAY PORT 2 DISPLAY PORT 1

DISPLAY PORT 2 DISPLAY PORT 1

CTRL SER. CLK

CTRL SER. CLK

JTAG

JTAG

SENSE

SENSE

DISPLAY PORT MISC.

DISPLAY PORT MISC.

DP_VARY_BL

DP_AUX_ZVSS

TEST

TEST

DMAACTIVE_L

RSVD

RSVD

DP0_AUXP
DP0_AUXN

DP1_AUXP
DP1_AUXN

DP2_AUXP
DP2_AUXN

DP3_AUXP
DP3_AUXN

DP4_AUXP
DP4_AUXN

DP5_AUXP
DP5_AUXN

DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD

DP_BLON

DP_DIGON

TEST6

TEST9
TEST10
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST24

TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L

TEST31

TEST32_H
TEST32_L

TEST35

FS1R2

TEST4

TEST5

RSVD1
RSVD2
RSVD3
RSVD4

DP0_AUXP

D1

DP0_AUXN

D2

ML_VGA_AUXP

E1

ML_VGA_AUXN

E2
D5

D6
E5

E6
F5

F6
G5

G6
D3

E3
D7
E7
F7
G7

C6
B6
A6

DP_AUX_ZVSS

C1
AD12

M18
N18
F11
G11
H11
J11

APU_TEST18

F12

APU_TEST19

G12

APU_TEST20

J12

APU_TEST24

H12

TEST25_H

AE10

TEST25_L

AD10
L10
M10
P19
R19

APU_TEST31

K22
T19
N19

APU_TEST35

AA12

FS1R2

W10
AC12

P18
R18

Y10
AA10
Y12
K21

C

C47 0.1U_0402_16V7KC47 0.1U_0402_16V7K

1 2

C49 0.1U_0402_16V7KC49 0.1U_0402_16V7K

1 2

C57 0.1U_0402_16V7KC57 0.1U_0402_16V7K

1 2

C52 0.1U_0402_16V7KC52 0.1U_0402_16V7K

1 2

LVDS_HPD <24>
FCH_CRT_HPD <13>
HDMI_DET <26>

DP_INT_PWM <9>

R16 150_0402_1%R16 150_0402_1%

1 2

T5T5
T6T6
T66T66
T67T67
T3T3
T4T4

R18 1K_0402_5%R18 1K_0402_5%

1 2

R19 1K_0402_5%R19 1K_0402_5%

1 2

R21 1K_0402_5%R21 1K_0402_5%

1 2

R22 1K_0402_5%R22 1K_0402_5%

1 2

R23 510_0402_1%R23 510_0402_1%

1 2

R24 510_0402_1%R24 510_0402_1%

1 2

T7T7
T8T8

R27 39.2_0402_1%R27 39.2_0402_1%

1 2

R28 300_0402_5%HDMI@R28 300_0402_5%HDMI@

1 2

R29 300_0402_5%nonHDMI@R29 300_0402_5%nonHDMI@

1 2

R30 10K_0402_5%R30 10K_0402_5%

1 2

ALLOW_STOP <12>

T11T11
T12T12

DP0_AUXP_C <24>
DP0_AUXN_C <24>

ML_VGA_AUXP_C <13>
ML_VGA_AUXN_C <13>

HDMI_CLK <26>
HDMI_DATA <26>

+1.2VS

+1.5V
+3VALW

D

To LVDS
Translater

To FCH

To HDMI

APU_PROCHOT#

THERMTRIP shutdown
temperature: 115 degree

1K_0402_5%

1K_0402_5%

APU_THERMTRIP#

R13

R13

1K_0402_5%

1K_0402_5%

+1.5V

R20

R20

1 2

E

E

3 1

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

1 2

Q1

Q1

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

R868 0_0402_5%

R868 0_0402_5%

12

R17

R17
10K_0402_5%

10K_0402_5%

B

B

2

Q2

Q2

C

C

DP0_AUXP
DP0_AUXN
ML_VGA_AUXP
ML_VGA_AUXN

+3VS+1.5V

12

R14

R14
10K_0402_5%

10K_0402_5%

2

B

B

E

E

31

C

C

@

@

1 2

Indicates to the FCH that a thermal trip
has occurred. Its assertion will cause the FCH to
transition the system to S5 immediately

1 2

R55 0_0402_5%R55 0_0402_5%

1 2

R56 0_0402_5%

R56 0_0402_5%

@

@

R57 1.8K_0402_5%R57 1.8K_0402_5%
R25 1.8K_0402_5%R25 1.8K_0402_5%
R10 1.8K_0402_5%R10 1.8K_0402_5%
R11 1.8K_0402_5%R11 1.8K_0402_5%

12

R12

R12
10K_0402_5%

10K_0402_5%

E

12
12
12
12

Asserted as an input to force the
processor into the HTC-active state

H_PROCHOT# <33,40,47>

H_THERMTRIP# <14>

MAINPWON <33,40,42>

ESD request

@

APU_PWRGD

+1.5V

R42 1K_0402_5%R42 1K_0402_5%

1 2

R44 1K_0402_5%R44 1K_0402_5%

1 2

R46 1K_0402_5%R46 1K_0402_5%

1 2

R48 1K_0402_5%R48 1K_0402_5%

1 2

+1.5VS

R52 300_0402_5%R52 300_0402_5%

1 2

R54 300_0402_5%R54 300_0402_5%

4 4

1 2

R36 1K_0402_5%@R36 1K_0402_5%@

1 2

R39 1K_0402_5%@R39 1K_0402_5%@

1 2

R41 1K_0402_5%@R41 1K_0402_5%@

1 2

@

C1033 100P_0402_50V8J

C1033 100P_0402_50V8J

1 2

APU_SIC
APU_SID
ALERT_L
ALLOW_STOP

APU_RST#
APU_PWRGD
APU_SVT
APU_SVC
APU_SVD

A

CPU TSI interface level shift

@

@

C71 0.1U_0402_16V4Z

C71 0.1U_0402_16V4Z

1 2

R31

+3VS

1 2

31.6K_0402_1%

31.6K_0402_1%

APU_SID

APU_SIC

R31

B

R32

R32

1 2

30K_0402_1%

30K_0402_1%

G

G

2

Q3

Q3

13

D

S

D

S

BSH111 1N_SOT23-3

BSH111 1N_SOT23-3

G

G

2

Q4

Q4

13

D

S

D

S

BSH111 1N_SOT23-3

BSH111 1N_SOT23-3

BSH111, the Vgs is:
min = 0.4V
Max = 1.3V

R37

R37
1K_0402_5%

1K_0402_5%

1 2

EC_SMB_DA2_SUS <33>

EC_SMB_CK2_SUS <33>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

To EC

To EC

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

C

APU_TRST#

Compal Secret Data

Compal Secret Data

Compal Secret Data

R45 10K_0402_5%R45 10K_0402_5%
R47 10K_0402_5%R47 10K_0402_5%
R49 10K_0402_5%R49 10K_0402_5%

Deciphered Date

Deciphered Date

Deciphered Date

1 2
1 2
1 2

D

+1.5V

HDT Debug conn

JHDT1

JHDT1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

SAMTE_ASP-136446-07-B

SAMTE_ASP-136446-07-B

ME@

ME@

APU_TCK

2

2

APU_TMS

4

4

APU_TDI

6

6

APU_TDO

8

8

APU_PWRGD

10

10

APU_RST#

12

12

APU_DBRDY

14

14

APU_DBREQ#

16

16

R51 0_0402_5%R51 0_0402_5%

18

18

R53 0_0402_5%R53 0_0402_5%

20

20

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

R35 1K_0402_5%R35 1K_0402_5%

1 2

R38 1K_0402_5%R38 1K_0402_5%

1 2

R40 1K_0402_5%R40 1K_0402_5%

1 2

R50 1K_0402_5%R50 1K_0402_5%

1 2
1 2
1 2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

FS1r2 Display/MISC/HDT

FS1r2 Display/MISC/HDT

FS1r2 Display/MISC/HDT

APU_TEST19
APU_TEST18

LA8611P

LA8611P

LA8611P

E

+1.5V+1.5V

0.1

0.1

0.1

of

of

of

751Monday, November 07, 2011

751Monday, November 07, 2011

751Monday, November 07, 2011

A

Power Name

VDD
+APU_CORE

VDDNB
+APU_CORE_NB

VDDIO
+1.5V

VDDP / VDDR
+1.2VS

VDDA

1 1

+2.5VS

2 2

3 3

Consumption

5A / 3.5A

VDDP decoupling

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

C106

C106

C105

C105

1

1

2

2

60A
29A

3.2A

0.5A

C107

C107

1

2

+1.2VS

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

C108

C108

+APU_CORE_NB

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

1

2

+1.5V

+APU_CORE

F8

VDD_1

H6

VDD_2

J1

VDD_3

J14

VDD_4

P6

VDD_5

P10

VDD_6

J16

VDD_7

J18

VDD_8

J9

VDD_9

K19

VDD_10

K3

VDD_11

K17

VDD_12

M3

VDD_13

K6

VDD_14

V10

VDD_15

V18

VDD_16

V3

VDD_17

F3

VDD_18

L18

VDD_19

V6

VDD_20

W1

VDD_21

T18

VDD_22

Y14

VDD_23

AA1

VDD_24

AB6

VDD_25

AC1

VDD_26

R1

VDD_27

P3

VDD_28

K10

VDD_29

H3

VDD_30

M19

VDD_31

C8

VDDNB_1

D10

VDDNB_2

B8

VDDNB_3

B12

VDDNB_4

C9

VDDNB_5

A9

VDDNB_6

A10

VDDNB_7

A8

VDDNB_8

A11

VDDNB_9

E10

VDDNB_10

E11

VDDNB_11

C10

VDDNB_12

H26

VDDIO_1

K20

VDDIO_2

J28

VDDIO_3

K23

VDDIO_4

K26

VDDIO_5

L22

VDDIO_6

L25

VDDIO_7

L28

VDDIO_8

M20

VDDIO_9

M23

VDDIO_10

M26

VDDIO_11

N22

VDDIO_12

N25

VDDIO_13

N28

VDDIO_14

P20

VDDIO_15

P23

VDDIO_16

P26

VDDIO_17

AA28

VDDIO_18

AH6

VDDP_1

AH5

VDDP_2

AH4

VDDP_3

AH3

VDDP_4

AH7

VDDP_5

AB10

VDDA

LOTES_ACA-ZIF-109-P12-A_FS1R2

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

ME@

JCPU1E

JCPU1E

VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62

VDDNB_13
VDDNB_14
VDDNB_15
VDDNB_16
VDDNB_17
VDDNB_18
VDDNB_19
VDDNB_20
VDDNB_21
VDDNB_22
VDDNB_23

VDDNB_CAP_1
VDDNB_CAP_2

VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36

VDDR_1
VDDR_2
VDDR_3
VDDR_4

B

+APU_CORE

R11
T10
H8
G1
U11
W11
W13
W15
W17
W19
AB3
AD3
AD6
AE1
L1
Y6
M6
N11
N1
T3
T6
U19
U1
Y16
Y18
Y3
D4
F4
AF6
AF3
L11

C11

+APU_CORE_NB

C12
D9
D8
D12
D11
B11
A12
B10

Module design without +APU_CORE_NB

E12

power plane only Decoupling cap

B9
K13

K12

T23

+1.5V

T26
U22
U25
U28
Y26
T20
R28
R25
R22
V20
V23
V26
W22
W25
W28
Y24
G28

AG10
AH8
AH9
AH10

Northbridge Power Pins
for Remote Decoupling

+APU_CORE

+APU_CORE_NB

@

+VDDNB_CAP

C168 22U_0603_6.3V6MC168 22U_0603_6.3V6M

C169 22U_0603_6.3V6MC169 22U_0603_6.3V6M

1

1

2

2

C110

C110

C109

180P_0402_50V8J

C109

180P_0402_50V8J

1

2

C75

0.22U_0402_6.3V6K

C75

0.22U_0402_6.3V6K

C72

0.22U_0402_6.3V6K

C72

0.22U_0402_6.3V6K

1

1

2

2

C80

0.22U_0402_6.3V6K

C80

0.22U_0402_6.3V6K

C79

0.22U_0402_6.3V6K

C79

0.22U_0402_6.3V6K

1

1

2

2

+1.5V

C85

22U_0603_6.3V6M

C85

22U_0603_6.3V6M

C84

22U_0603_6.3V6M@C84

22U_0603_6.3V6M

1

1

2

2

C145 180P_0402_50V8JC145 180P_0402_50V8J

1

2

VDDR decoupling

180P_0402_50V8J

180P_0402_50V8J

C111

1000P_0402_50V7K

C111

1000P_0402_50V7K

1

1

2

2

C115

C115

C

C77

0.01U_0402_16V7K

C77

0.01U_0402_16V7K

C74

180P_0402_50V8J

C74

C73

0.01U_0402_16V7K

C73

0.01U_0402_16V7K

C76

0.01U_0402_16V7K

C76

0.01U_0402_16V7K

1

2

C81

180P_0402_50V8J

C81

180P_0402_50V8J

1

2

1

1

2

2

C82

180P_0402_50V8J

C82

180P_0402_50V8J

C83

180P_0402_50V8J

C83

180P_0402_50V8J

1

1

2

2

180P_0402_50V8J

C78

180P_0402_50V8J

C78

180P_0402_50V8J

1

1

2

2

(330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00)

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

C86

22U_0603_6.3V6M

C86

22U_0603_6.3V6M

C87

22U_0603_6.3V6M

C87

22U_0603_6.3V6M

1

1

2

2

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

C116

0.22U_0402_6.3V6K

C116

0.22U_0402_6.3V6K

1

1

2

2

4.7U_0603_6.3V6K

C88

22U_0603_6.3V6M

C88

22U_0603_6.3V6M

C90

C90

C89

C89

1

2

1

1

2

2

+1.2VS

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

C93

C93

C92

C92

C91

C91

1

1

2

1

2

2

+1.5V

C101

0.22U_0402_6.3V6K

C101

0.22U_0402_6.3V6K

1

2

C95

C95

C94

0.22U_0402_6.3V6K

C94

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

C102

C102

1

1

2

2

C103

180P_0402_50V8J

C103

180P_0402_50V8J

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

1

1

2

2

D

C97

C97

C96

0.22U_0402_6.3V6K

C96

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

1

1

2

2

Across VDDIO and VSS
split

C104

180P_0402_50V8J

C104

180P_0402_50V8J

1

2

E

JCPU1F

JCPU1F

J20

VSS_1

L4

VSS_2

R7

VSS_3

W18

VSS_4

A15

VSS_5

AB17

VSS_6

AC22

VSS_7

AE21

VSS_8

AF24

VSS_9

AH23

VSS_10

AH25

VSS_11

B7

VSS_12

C14

VSS_13

C16

VSS_14

C2

VSS_15

C20

VSS_16

C22

VSS_17

C24

VSS_18

C26

VSS_19

C28

VSS_20

D13

VSS_21

D15

VSS_22

D17

VSS_23

D19

VSS_24

D23

VSS_25

D25

VSS_26

D27

VSS_27

E4

VSS_28

E9

VSS_29

F14

VSS_30

F16

VSS_31

F18

VSS_32

F20

VSS_33

F22

VSS_34

C98

0.22U_0402_6.3V6K

C98

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

C99

180P_0402_50V8J

C99

180P_0402_50V8J

C100

330U_2.5V_M+C100

330U_2.5V_M

1

2

1

1

+

2

2

F26

VSS_35

F28

VSS_36

G13

VSS_37

G15

VSS_38

G17

VSS_39

G19

VSS_40

G21

VSS_41

G23

VSS_42

G25

VSS_43

G4

VSS_44

J22

VSS_45

J24

VSS_46

J4

VSS_47

J7

VSS_48

K11

VSS_49

K14

VSS_50

K9

VSS_51

AC11

VSS_52

L19

VSS_53

L7

VSS_54

M11

VSS_55

AF11

VSS_56

V19

VSS_57

V9

VSS_58

W16

VSS_59

W4

VSS_60

W7

VSS_61

Y11

VSS_62

Y20

VSS_63

Y22

VSS_64

Y9

VSS_65

A17

VSS_66

A13

VSS_67

K16

VSS_68

F24

VSS_69

G8

VSS_70

H7

VSS_71

J8

VSS_72

LOTES_ACA-ZIF-109-P12-A_FS1R2

LOTES_ACA-ZIF-109-P12-A_FS1R2

ME@

ME@

VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143

A19
A21
A23
A25
A7
AA4
AA7
AB13
AB15
AB19
AB21
AB23
AB25
AB27
AB9
AC14
AC16
AC18
AC20
AC24
AC26
AC28
AC4
AC7
AD9
AE13
AE15
AE17
M9
N10
N4
N7
R10
R4
T11
T9
U10
U18
U4
U7
V11
AE19
AE23
AE25
AE27
AE4
AE7
AF14
AF16
AF18
AF20
AF22
AF26
AF28
AF9
AG4
AG7
AH13
AH15
AH17
AH19
AH21
P9
C18
D21
W14
P11
C7
E8
K18
W12

Demo Board Capacitor

APU_CORE
22uF x 10

0.22uF x 2

0.01uF x 3
180pF x 2

CORE_NB
22uF x 2
10uF x 1

0.22uF x 2
180pF x 3

CORE_NB_CAP
22uF x 2
180pF x 1

VDDIO_SUS
(CPU side)
22uF x 4

4.7uF x 4

0.22uF x 6 +2(split)
180pF x 1 + 2(split)

4 4

+2.5VS

L1

L1
FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

12

C117

3300P_0402_50V7K

C117

3300P_0402_50V7K

C118

0.22U_0402_6.3V6K

C118

0.22U_0402_6.3V6K

1

12

2

A

C119

C119

40mil

+VDDA

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1

2

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

VDDP

0.22uF x 2
180pF x 2

VDDR

0.22uF x 2
1nF x 1
180pF x 2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

VDDA

4.7uF x 1

0.22uF x 1

3.3nF x 1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

FS1r2 PWR/GND

FS1r2 PWR/GND

FS1r2 PWR/GND

LA8611P

LA8611P

LA8611P

E

VDDIO_SUS
(DIMM x2)
100uF x 2

0.1uF x 12

851Monday, November 07, 2011

851Monday, November 07, 2011

851Monday, November 07, 2011

0.1

0.1

0.1

of

of

of

5

4

3

2

1

Panel PWM

+3VS

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

2

G

G

12

R77

R77

4.7K_0402_5%

4.7K_0402_5%

13

D

D

Q11

Q11
2N7002K_SOT23-3

2N7002K_SOT23-3

S

S

12

@

@

R884

R884
0_0402_5%

0_0402_5%

APU_INVT_PWM <24>

12

D D

R76

R76
47K_0402_5%

47K_0402_5%

C

C

Q12

Q12

DP_INT_PWM<7>

C C

1 2

R78 2.2K_0402_5%R78 2.2K_0402_5%

12

R79

R79

4.7K_0402_5%

4.7K_0402_5%

2

B

B

E

E

3 1

12

R885

R885
0_0402_5%

0_0402_5%

B B

A A

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

FS1r2 Signal Level Shifter

FS1r2 Signal Level Shifter

FS1r2 Signal Level Shifter

LA8611P

LA8611P

LA8611P

1

951Friday, November 04, 2011

951Friday, November 04, 2011

951Friday, November 04, 2011

of

of

of

0.1

0.1

0.1

A

B

C

D

E

+VREF_DQ

DDRA_SDQ0

1 1

DDRA_SDQS1#<6>
DDRA_SDQS1<6>

DDRA_SDQS2#<6>
DDRA_SDQS2<6>

DDRA_CKE0<6>

2 2

3 3

+3VS

4 4

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

DDRA_SBS2#<6>

DDRA_CLK0<6>
DDRA_CLK0#<6>

DDRA_SBS0#<6>

DDRA_SWE#<6>

DDRA_SCAS#<6> DDRA_ODT0 <6>

DDRA_SCS1#<6>

DDRA_SDQS4#<6>
DDRA_SDQS4<6>

DDRA_SDQS6#<6>
DDRA_SDQS6<6>

1

2

1

C131

C131

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C130

C130

DDRA_SDQ1
DDRA_SDM0
DDRA_SDQ2

DDRA_SDQ3
DDRA_SDQ8

DDRA_SDQ9
DDRA_SDQS1#

DDRA_SDQS1
DDRA_SDQ10

DDRA_SDQ11
DDRA_SDQ16

DDRA_SDQ17
DDRA_SDQS2#

DDRA_SDQS2
DDRA_SDQ18

DDRA_SDQ19
DDRA_SDQ24

DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26

DDRA_SDQ27

DDRA_CKE0

DDRA_SBS2#
DDRA_SMA12

DDRA_SMA9
DDRA_SMA8

DDRA_SMA5
DDRA_SMA3

DDRA_SMA1
DDRA_CLK0

DDRA_CLK0#
DDRA_SMA10

DDRA_SBS0#
DDRA_SWE#

DDRA_SCAS# DDRA_ODT0
DDRA_SMA13

DDRA_SCS1#

DDRA_SDQ32
DDRA_SDQ33

DDRA_SDQS4#
DDRA_SDQS4

DDRA_SDQ34
DDRA_SDQ35

DDRA_SDQ40
DDRA_SDQ41

DDRA_SDM5
DDRA_SDQ42

DDRA_SDQ43
DDRA_SDQ48

DDRA_SDQ49
DDRA_SDQS6#

DDRA_SDQS6
DDRA_SDQ50

DDRA_SDQ51
DDRA_SDQ56

DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58

DDRA_SDQ59

R84 10K_0402_5%

R84 10K_0402_5%

1 2

A

+1.5V +1.5V

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

12

R85

R85
10K_0402_5%

10K_0402_5%

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

LCN_DAN06-K4406-0103

Reverse H:4mm

<Address: 00>

ME@JDIMM1

ME@

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

ODT0
ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

EVENT#

GND2

BOSS2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

CKE1

VDD

VDD

VDD

VDD

VDD
CK1

CK1#

VDD
BA1

RAS#

VDD

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SDA

SCL
VTT

2

DDRA_SDQ4

4

DDRA_SDQ5

6
8

DDRA_SDQS0#

10

DDRA_SDQS0

12
14

DDRA_SDQ6

16

DDRA_SDQ7

18
20

DDRA_SDQ12

22

DDRA_SDQ13

24
26

DDRA_SDM1

28

MEM_MA_RST#

30
32

DDRA_SDQ14

34

DDRA_SDQ15

36
38

DDRA_SDQ20

40

DDRA_SDQ21

42
44

DDRA_SDM2

46
48

DDRA_SDQ22

50

DDRA_SDQ23

52
54

DDRA_SDQ28

56

DDRA_SDQ29

58
60

DDRA_SDQS3#

62

DDRA_SDQS3

64
66

DDRA_SDQ30

68

DDRA_SDQ31

70
72

DDRA_CKE1

74
76

DDRA_SMA15

78

A15
A14

A11

A7
A6

A4
A2

A0

S0#

NC

B

DDRA_SMA14

80
82

DDRA_SMA11

84

DDRA_SMA7

86
88

DDRA_SMA6

90

DDRA_SMA4

92
94

DDRA_SMA2

96

DDRA_SMA0

98
100

DDRA_CLK1

102

DDRA_CLK1#

104
106

DDRA_SBS1#

108

DDRA_SRAS#

110
112

DDRA_SCS0#

114
116
118

DDRA_ODT1

120
122
124
126
128

DDRA_SDQ36

130

DDRA_SDQ37

132
134

DDRA_SDM4

136
138

DDRA_SDQ38

140

DDRA_SDQ39

142
144

DDRA_SDQ44

146

DDRA_SDQ45

148
150

DDRA_SDQS5#

152

DDRA_SDQS5

154
156

DDRA_SDQ46

158

DDRA_SDQ47

160
162

DDRA_SDQ52

164

DDRA_SDQ53

166
168

DDRA_SDM6

170
172

DDRA_SDQ54

174

DDRA_SDQ55

176
178

DDRA_SDQ60

180

DDRA_SDQ61

182
184

DDRA_SDQS7#

186

DDRA_SDQS7

188
190

DDRA_SDQ62

192

DDRA_SDQ63

194
196

MEM_MA_EVENT#

198
200
202
204

206
208

+0.75VS

DDRA_SDQS0# <6>
DDRA_SDQS0 <6>

MEM_MA_RST# <6>

DDRA_SDQS3# <6>
DDRA_SDQS3 <6>

DDRA_CKE1 <6>

DDRA_CLK1 <6>
DDRA_CLK1# <6>

DDRA_SBS1# <6>
DDRA_SRAS# <6>

DDRA_SCS0# <6>

DDRA_ODT1 <6>

+VREF_CA

DDRA_SDQS5# <6>
DDRA_SDQS5 <6>

DDRA_SDQS7# <6>
DDRA_SDQS7 <6>

MEM_MA_EVENT# <6>

FCH_SDATA0 <11,14,32>
FCH_SCLK0 <11,14,32>

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

Issued Date

Issued Date

C

DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]

+1.5V

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VREF_DQ

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

DDRA_SDQ[0..63] <6>

DDRA_SDM[0..7] <6>

DDRA_SMA[0..15] <6>

Place near DIMM1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C120

C120

C121

C121

1

+VREF_DQ +VREF_CA

1

C126

C126

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

C122

C122

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C129

C129

2

1000P_0402_50V7K

1000P_0402_50V7K

Deciphered Date

Deciphered Date

Deciphered Date

0.1U_0402_16V4Z

2

C123

C123

1

+1.5V

R80

R80
1K_0402_1%

1K_0402_1%

1 2

R82

R82
1K_0402_1%

1K_0402_1%

1 2

2

C124

C124

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

D

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C125

C125

1

+VREF_CA

+1.5V

R81

R81
1K_0402_1%

1K_0402_1%

15mil15mil

1

C127

C127

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1000P_0402_50V7K

1000P_0402_50V7K

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1 2

1

2

R83

R83

C128

C128

1K_0402_1%

1K_0402_1%

1 2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDRIII SO-DIMM 1

DDRIII SO-DIMM 1

DDRIII SO-DIMM 1

LA8611P

LA8611P

LA8611P

0.1

0.1

0.1

of

of

of

10 51Friday, November 04, 2011

10 51Friday, November 04, 2011

10 51Friday, November 04, 2011

E

A

B

C

D

E

DQ4
DQ5

VSS3

VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2
DQ22

DQ23
DQ28

DQ29

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1
CK1#

BA1
RAS#

NC2

DQ36
DQ37

DM4
DQ38

DQ39
DQ44

DQ45

DQ46
DQ47

DQ52
DQ53

DM6
DQ54

DQ55
DQ60

DQ61

DQ62
DQ63

SDA

SCL
VTT2

+1.5V+1.5V

2

DDRB_SDQ4

4

DDRB_SDQ5

6
8

DDRB_SDQS0#

10

DDRB_SDQS0

12
14

DDRB_SDQ6

16

DDRB_SDQ7

18
20

DDRB_SDQ12

22

DDRB_SDQ13

24
26

DDRB_SDM1

28

MEM_MB_RST#

30
32

DDRB_SDQ14

34

DDRB_SDQ15

36
38

DDRB_SDQ20

40

DDRB_SDQ21

42
44

DDRB_SDM2

46
48

DDRB_SDQ22

50

DDRB_SDQ23

52
54

DDRB_SDQ28

56

DDRB_SDQ29

58
60

DDRB_SDQS3#

62

DDRB_SDQS3

64
66

DDRB_SDQ30

68

DDRB_SDQ31

70
72

DDRB_CKE1

74
76

DDRB_SMA15

78

A15
A14

A11

A7
A6

A4
A2

A0

S0#

G2

DDRB_SMA14

80
82

DDRB_SMA11

84

DDRB_SMA7

86
88

DDRB_SMA6

90

DDRB_SMA4

92
94

DDRB_SMA2

96

DDRB_SMA0

98
100

DDRB_CLK1

102

DDRB_CLK1#

104
106

DDRB_SBS1#

108

DDRB_SRAS#

110
112

DDRB_SCS0#

114

DDRB_ODT0DDRB_SCAS#

116
118

DDRB_ODT1

120
122
124
126
128

DDRB_SDQ36

130

DDRB_SDQ37

132
134

DDRB_SDM4

136
138

DDRB_SDQ38

140

DDRB_SDQ39

142
144

DDRB_SDQ44

146

DDRB_SDQ45

148
150

DDRB_SDQS5#

152

DDRB_SDQS5

154
156

DDRB_SDQ46

158

DDRB_SDQ47

160
162

DDRB_SDQ52

164

DDRB_SDQ53

166
168

DDRB_SDM6

170
172

DDRB_SDQ54

174

DDRB_SDQ55

176
178

DDRB_SDQ60

180

DDRB_SDQ61

182
184

DDRB_SDQS7#

186

DDRB_SDQS7

188
190

DDRB_SDQ62

192

DDRB_SDQ63

194
196

MEM_MB_EVENT#

198
200
202
204

206

+0.75VS

DDRB_SDQS0# <6>
DDRB_SDQS0 <6>

MEM_MB_RST# <6>

DDRB_SDQS3# <6>
DDRB_SDQS3 <6>

DDRB_CKE1 <6>

DDRB_CLK1 <6>
DDRB_CLK1# <6>

DDRB_SBS1# <6>
DDRB_SRAS# <6>

DDRB_SCS0# <6>
DDRB_ODT0 <6>

DDRB_ODT1 <6>

+VREF_CA

DDRB_SDQS5# <6>
DDRB_SDQS5 <6>

DDRB_SDQS7# <6>
DDRB_SDQS7 <6>

MEM_MB_EVENT# <6>

FCH_SDATA0 <10,14,32>
FCH_SCLK0 <10,14,32>

DDRB_SDQ[0..63]
DDRB_SDM[0..7]

DDRB_SMA[0..15]

DDRB_SDQ[0..63] <6>

DDRB_SDM[0..7] <6>

DDRB_SMA[0..15] <6>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C142

C142

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VREF_DQ

15mil 15mil

+VREF_DQ +VREF_CA

1000P_0402_50V7K

1000P_0402_50V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C132

C132

C133

C133

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C137

C137

1

1

C143

C143

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2

2

C138

C138

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

1

+1.5V

1

2

2

C136

C136

1

+0.75VS

2

1

+VREF_CA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C139

C139

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K

C134

C134

1

C135

C135

2

Place near DIMM2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

1

C140

C140

+1.5V

1

1

+

+

2

@

@

C141

C141

C144

C144
220U_6.3V_M

220U_6.3V_M

SF000002Y00

+VREF_DQ

DDRB_SDQ0

+3VS

DDRB_SDQ1
DDRB_SDM0
DDRB_SDQ2

DDRB_SDQ3
DDRB_SDQ8

DDRB_SDQ9
DDRB_SDQS1#

DDRB_SDQS1
DDRB_SDQ10

DDRB_SDQ11
DDRB_SDQ16

DDRB_SDQ17
DDRB_SDQS2#

DDRB_SDQS2
DDRB_SDQ18

DDRB_SDQ19
DDRB_SDQ24

DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26

DDRB_SDQ27

DDRB_CKE0

DDRB_SBS2#
DDRB_SMA12

DDRB_SMA9
DDRB_SMA8

DDRB_SMA5
DDRB_SMA3

DDRB_SMA1
DDRB_CLK0

DDRB_CLK0#
DDRB_SMA10

DDRB_SBS0#
DDRB_SWE#

DDRB_SMA13
DDRB_SCS1#

DDRB_SDQ32
DDRB_SDQ33

DDRB_SDQS4#
DDRB_SDQS4

DDRB_SDQ34
DDRB_SDQ35

DDRB_SDQ40
DDRB_SDQ41

DDRB_SDM5
DDRB_SDQ42

DDRB_SDQ43
DDRB_SDQ48

DDRB_SDQ49
DDRB_SDQS6#

DDRB_SDQS6
DDRB_SDQ50

DDRB_SDQ51
DDRB_SDQ56

DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58

DDRB_SDQ59

R86 10K_0402_5%

R86 10K_0402_5%

1 2

12

R87

R87

10K_0402_5%

10K_0402_5%

1 1

DDRB_SDQS1#<6>
DDRB_SDQS1<6>

DDRB_SDQS2#<6>
DDRB_SDQS2<6>

DDRB_CKE0<6>

2 2

3 3

4 4

DDRB_SBS2#<6>

DDRB_CLK0<6>
DDRB_CLK0#<6>

DDRB_SBS0#<6>

DDRB_SWE#<6>

DDRB_SCAS#<6>

DDRB_SCS1#<6>

DDRB_SDQS4#<6>
DDRB_SDQS4<6>

DDRB_SDQS6#<6>
DDRB_SDQS6<6>

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103

LCN_DAN06-K4806-0103

ME@JDIMM2

ME@

DQS#0

DQS0

VSS10

VSS17

VSS19

VSS21

DQS3

VDD10

VDD12

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

VSS30
VSS31

VSS33

VSS35
DQS#5

DQS5

VSS38

VSS40

VSS42
VSS43

VSS45

VSS47
DQS#7

DQS7

VSS50

VSS52

EVENT#

Reserve H:8mm

<Address: 01>

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

DDRIII SO-DIMM 2

DDRIII SO-DIMM 2

DDRIII SO-DIMM 2

LA8611P

LA8611P

LA8611P

11 51Friday, November 04, 2011

11 51Friday, November 04, 2011

11 51Friday, November 04, 2011

E

of

of

of

0.1

0.1

0.1

A

C146 150P_0402_50V8JC146 150P_0402_50V8J

+VDDAN_11_PCIE

+1.1VS_CKVDD

CLK_PCIE_VGA<17>
CLK_PCIE_VGA#<17>

CLK_PCIE_WLAN<32>
CLK_PCIE_WLAN#<32>

CLK_PCIE_LAN<28>
CLK_PCIE_LAN#<28>

CLK_LAN_48M<28>

1

2

1 2

UMI_RXP0<5>
UMI_RXN0<5>
UMI_RXP1<5>
UMI_RXN1<5>
UMI_RXP2<5>
UMI_RXN2<5>
UMI_RXP3<5>
UMI_RXN3<5>

UMI_TXP0<5>
UMI_TXN0<5>
UMI_TXP1<5>
UMI_TXN1<5>
UMI_TXP2<5>
UMI_TXN2<5>
UMI_TXP3<5>
UMI_TXN3<5>

C158

C158

22P_0402_50V8J

22P_0402_50V8J

20M_0402_5%

20M_0402_5%

C159

C159

22P_0402_50V8J

22P_0402_50V8J

PLT_RST#

C147 0.1U_0402_16V7KC147 0.1U_0402_16V7K
C148 0.1U_0402_16V7KC148 0.1U_0402_16V7K
C149 0.1U_0402_16V7KC149 0.1U_0402_16V7K
C150 0.1U_0402_16V7KC150 0.1U_0402_16V7K
C151 0.1U_0402_16V7KC151 0.1U_0402_16V7K
C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K
C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K
C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K

R94 590_0402_1%R94 590_0402_1%
R88 2K_0402_1%R88 2K_0402_1%

R95 2K_0402_1%R95 2K_0402_1%

R98 0_0402_5%PX@R98 0_0402_5%PX@
R99 0_0402_5%PX@R99 0_0402_5%PX@

R102 0_0402_5%R102 0_0402_5%
R103 0_0402_5%R103 0_0402_5%

R100 0_0402_5%R100 0_0402_5%
R101 0_0402_5%R101 0_0402_5%

R680 22_0402_5%@R680 22_0402_5%@

1 2

12

R107

R107

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

1 2

C146 place close to FCH

1 1

2 2

WLAN

3 3

25M_X1
25M_X2

4 4

C157

C157

22P_0402_50V8J

22P_0402_50V8J

LAN

1 2

R106 1M_0402_5%R106 1M_0402_5%

3

NC

OSC

2

OSC

NC

Y4

Y4

25MHZ_20PF_FSX3M-25.M20FDO

25MHZ_20PF_FSX3M-25.M20FDO

1

22P_0402_50V8J

2

22P_0402_50V8J

A

4
1

C155

C155

B

APU_DISP_CLK<7>
APU_DISP_CLK#<7>

B

APU_PCIE_RST#_C

APU_CLK<7>
APU_CLK#<7>

CLK_PCIE_VGA_R
CLK_PCIE_VGA#_R

CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

CLK_LAN_25M_R

32K_X1

32K_X2

R89 33_0402_5%R89 33_0402_5%

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

Y1

Y1

32.768KHZ_12.5PF_CM31532768DZFT

32.768KHZ_12.5PF_CM31532768DZFT

1 2

A_RST#
UMI_RXP0_C

UMI_RXN0_C
UMI_RXP1_C
UMI_RXN1_C
UMI_RXP2_C
UMI_RXN2_C
UMI_RXP3_C
UMI_RXN3_C

PCIE_CALRP
PCIE_CALRN

CLK_CALRN

25M_X1

25M_X2

C

U2A

U2A

HUDSON-2

AE2

PCIE_RST#

AD5

A_RST#

AE30

UMI_TX0P

AE32

UMI_TX0N

AD33

UMI_TX1P

AD31

UMI_TX1N

AD28

UMI_TX2P

AD29

UMI_TX2N

AC30

UMI_TX3P

AC32

UMI_TX3N

AB33

UMI_RX0P

AB31

UMI_RX0N

AB28

UMI_RX1P

AB29

UMI_RX1N

Y33

UMI_RX2P

Y31

UMI_RX2N

Y28

UMI_RX3P

Y29

UMI_RX3N

AF29

PCIE_CALRP

AF31

PCIE_CALRN

V33

GPP_TX0P

V31

GPP_TX0N

W30

GPP_TX1P

W32

GPP_TX1N

AB26

GPP_TX2P

AB27

GPP_TX2N

AA24

GPP_TX3P

AA23

GPP_TX3N

AA27

GPP_RX0P

AA26

GPP_RX0N

W27

GPP_RX1P

V27

GPP_RX1N

V26

GPP_RX2P

W26

GPP_RX2N

W24

GPP_RX3P

W23

GPP_RX3N

F27

CLK_CALRN

G30

PCIE_RCLKP

G28

PCIE_RCLKN

R26

DISP_CLKP

T26

DISP_CLKN

H33

DISP2_CLKP

H31

DISP2_CLKN

T24

APU_CLKP

T23

APU_CLKN

J30

SLT_GFX_CLKP

K29

SLT_GFX_CLKN

H27

GPP_CLK0P

H28

GPP_CLK0N

J27

GPP_CLK1P

K26

GPP_CLK1N

F33

GPP_CLK2P

F31

GPP_CLK2N

E33

GPP_CLK3P

E31

GPP_CLK3N

M23

GPP_CLK4P

M24

GPP_CLK4N

M27

GPP_CLK5P

M26

GPP_CLK5N

N25

GPP_CLK6P

N26

GPP_CLK6N

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

21807-A13-HUDSON-M3_FCBGA656

21807-A13-HUDSON-M3_FCBGA656

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCI CLKS

PCI CLKS

PCICLK4/14M_OSC/GPO39

PCI EXPRESS INTERFACES

PCI EXPRESS INTERFACES

PCI INTERFACE

PCI INTERFACE

REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

CLOCK GENERATOR

CLOCK GENERATOR

LPCAPUS5 PLUS

LPCAPUS5 PLUS

LDRQ1#/CLK_REQ6#/GPIO49

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

C

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38

PCIRST#

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8

AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31

CBE0#
CBE1#
CBE2#
CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#
STOP#

PERR#
SERR#
REQ0#

REQ1#/GPIO40

GNT0#

GNT1#/GPO44

CLKRUN#

LOCK#

INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

LPCCLK0
LPCCLK1

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#

SERIRQ/GPIO48

DMA_ACTIVE#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

S5_CORE_EN

RTCCLK

INTRUDER_ALERT#

VDDBT_RTC_G

32K_X1

32K_X2

AF3
AF1
AF5
AG2
AF6

AB5

AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10

PAR

AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9

AF18
AE18
AC16
AD18

B25
D25

D27
C28
A26
A29
A31
B27
AE27
AE19

G25
E28
E26
G26
F26

H7
F1
F3
E6

G2

G4

Compal Secret Data

Compal Secret Data

Compal Secret Data

APU_PCIE_RST#_C

Module design have reserve GPIO44,45 for
VGA power enable and reset

R891 0_0402_5%R891 0_0402_5%

1 2

APU_PROCHOT#_R

32K_X1

32K_X2

Deciphered Date

Deciphered Date

Deciphered Date

APU_PCIE_RST #: Reset PCIE device on APU

T14T14

T69T69

D

PCI_CLK1 <16>
PCI_CLK3 <16>

PCI_CLK4 <16>

MC74VHC1G08DFT2G SC70 5P

MC74VHC1G08DFT2G SC70 5P

R692

@R692

@

1 2

33_0402_5%

33_0402_5%

C790

C790

150P_0402_50V8J

150P_0402_50V8J

12

1

@

@

2

R692/ C790 close to FCH

PCI_AD23 <16>
PCI_AD24 <16>
PCI_AD25 <16>
PCI_AD26 <16>
PCI_AD27 <16>

@

@

1 2

R670

W=20mils

1

C156

C156

2

R670

0_0402_5%

0_0402_5%

LPC_CLK1 <16>
LPC_AD0 <32,33>
LPC_AD1 <32,33>
LPC_AD2 <32,33>
LPC_AD3 <32,33>
LPC_FRAME# <32,33>

SERIRQ <33>

R15 0_0402_5%@R15 0_0402_5%@

1 2

APU_PWRGD <7,47>
APU_RST# <7>

RTC_CLK <16,33>

1U_0402_6.3V6K

1U_0402_6.3V6K

D

E

+3VALW

C789

@C789

@

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5

2

P

B

1

A

@

@

R693

R693

8.2K_0402_5%

8.2K_0402_5%

1 2

R105 510_0402_5%R105 510_0402_5%

3

@

@

R695

@R695

@

1 2

0_0402_5%

0_0402_5%

CLK_PCI_EC <16,33>
CLK_PCI_DB <32>

ALLOW_STOP <7>
APU_PROCHOT# <7>

Y

G

U43

U43

+RTCBATT

12

4

CLRP1
SHORT PADS

SHORT PADS

@CLRP1

@

1 2

R866

R866
0_0402_5%

0_0402_5%

APU_PCIE_RST# <17,28,32>

PLT_RST# <33>

for Clear CMOS

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RTC

FCH PCIE/CLK/PCI/LPC/RTC

FCH PCIE/CLK/PCI/LPC/RTC

LA8611P

LA8611P

LA8611P

12 51Monday, November 07, 2011

12 51Monday, November 07, 2011

12 51Monday, November 07, 2011

E

0.1

0.1

0.1

of

of

of

A

B

C

D

E

4MB SPI ROM
& Non-share ROM.

+3VALW

1 2

1 2

1
2
3
4

SPI_WP#

3.3K_0402_5%

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

3.3K_0402_5%

U4

U4

CS#
SO/SIO1
WP#
GND

MX25L3206EM2I-12G_SO8

MX25L3206EM2I-12G_SO8

SA00003K800

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

+3VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C165

C165

1 2

R110

8

VCC

SPI_HOLD#

7

HOLD#
SI/SIO0

SPI_CLK_FCH

6

SCLK

SPI_SI

5

GBE_PHY_INTR

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

FCH SATA/SPI/VGA/HWM/SD

FCH SATA/SPI/VGA/HWM/SD

R110

0_0402_5%

0_0402_5%

1 2
1 2

0_0402_5%

0_0402_5%

R119

R119

R110 place close to FCH

R121 10K_0402_5%R121 10K_0402_5%

LA8611P

LA8611P

LA8611P

1 2

E

R112

U2B

U2B

1 1

C161 0.01U_0402_16V7KC161 0.01U_0402_16V7K

SATA_FTX_DRX_P1<31>

HDD

ODD

2 2

3 3

1 2

R888 10K_0402_5%R888 10K_0402_5%

no Zero Power ODD function,
Thus, pull-down needs to be poped

4 4

SATA_FTX_DRX_N1<31>

SATA_FRX_C_DTX_N1<31>
SATA_FRX_C_DTX_P1<31>

SATA_FTX_C_DRX_P2<31>
SATA_FTX_C_DRX_N2<31>

SATA_FRX_C_DTX_N2<31>
SATA_FRX_C_DTX_P2<31>

+AVDD_SATA

ODD_EN

1 2

C162 0.01U_0402_16V7KC162 0.01U_0402_16V7K

1 2

+3VS

BT_DISABLE#<32>

1 2

BT_ON#<31>

WL_OFF#<32>

ODD_EN<31>

A

SATA_FTX_C_DRX_P1
SATA_FTX_C_DRX_N1

SATA_CALRP

R1281K_0402_1% R1281K_0402_1%

12

SATA_CALRN

R130931_0402_1% R130931_0402_1%

12

R13310K_0402_5% R13310K_0402_5%

1 2

R146 10K_0402_5%R146 10K_0402_5%

1 2

R149 10K_0402_5%R149 10K_0402_5%

1 2

R151 10K_0402_5%R151 10K_0402_5%

AK19

SATA_TX0P

AM19

SATA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

T48T48

B

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

21807-A13-HUDSON-M3_FCBGA656

21807-A13-HUDSON-M3_FCBGA656

HUDSON-2

HUDSON-2

SERIAL ATA

SERIAL ATA

HW MONITOR

HW MONITOR

GBE_COL

GBE_CRS

GBE_MDCK

GBE_MDIO
GBE_RXD3

GBE_RXD2
GBE_RXD1
GBE_RXD0

GBE_TXCLK

GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0

VGA_RED

VGA_BLUE

AUXCAL

NC1
NC2
NC3
NC4
NC5

C

AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14

AC4
AD3
AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7

GBE_PHY_INTR

W9

SPI_SO_R

V6

SPI_SI_R

V5

SPI_CLK_FCH_R

V3

SPI_SB_CS0#_R

T6

SPI_WP#

V1

L30

R125 150_0402_1%R125 150_0402_1%

L32

M29

M28
N30

M33
N32

K31

V28
V29

U28
T31

T33
T29
T28
R32
R30
P29
P28

C29

N2
M3
L2
N4
P1
P3
M1
M5

AG16
AH10
A28
G27
L4

1 2

R126 150_0402_1%R126 150_0402_1%

1 2

R127 150_0402_1%R127 150_0402_1%

1 2

R131 715_0402_1%R131 715_0402_1%

1 2

AUXCAL

R134 100_0402_1%R134 100_0402_1%

1 2

1 2

R137 10K_0402_5%R137 10K_0402_5%

1 2

R138 10K_0402_5%R138 10K_0402_5%

@

@

1 2

R139 10K_0402_5%

R139 10K_0402_5%

@

@

1 2

R142 10K_0402_5%

R142 10K_0402_5%

@

@

1 2

R143 10K_0402_5%

R143 10K_0402_5%

@

@

1 2

R145 10K_0402_5%

R145 10K_0402_5%

@

@

1 2

R147 10K_0402_5%

R147 10K_0402_5%

1 2

R148 10K_0402_5%R148 10K_0402_5%

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

SPI_SB_CS0#_R
SPI_SO_R SPI_SO_L

CRT_HSYNC <27>
CRT_VSYNC <27>

CRT_DDC_DATA <27>
CRT_DDC_CLK <27>

ML_VGA_AUXP_C <7>
ML_VGA_AUXN_C <7>

ML_VGA_TXP0 <7>
ML_VGA_TXN0 <7>
ML_VGA_TXP1 <7>
ML_VGA_TXN1 <7>
ML_VGA_TXP2 <7>
ML_VGA_TXN2 <7>
ML_VGA_TXP3 <7>
ML_VGA_TXN3 <7>

FCH_CRT_HPD <7>

Need to enable internal
pull down to leave
unconnected

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

R115

R115

0_0402_5%

0_0402_5%

1 2
1 2

0_0402_5%

0_0402_5%

R117

R117

DAC_RED <27>

DAC_GRN <27>

DAC_BLU <27>

+VDDAN_11_ML

SD_CLK/SCLK_2/GPIO73

SD_CMD/SLOAD_2/GPIO74

SD_CD/GPIO75

SD_WP/GPIO76

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

SD_DATA2/GPIO79
SD_DATA3/GPIO80

GBE_RXCLK

GBE_RXCTL/RXDV

GBE_RXERR

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

ROM_RST#/SPI_WP#/GPIO161

VGA_GREEN

VGA_HSYNC/GPO68

VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P

AUX_VGA_CH_N

ML_VGA_L0P
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N

ML_VGA_HPD/GPIO229

VIN0/GPIO175
VIN1/GPIO176

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R112

R108

R108

SPI_SB_CS0#

+FCH_VDDAN_33_DAC

12

R61410K_0402_5% R61410K_0402_5%

D

SPI_WP#

SPI_CLK_FCH

33_0402_5%

33_0402_5%

22P_0402_50V8J

22P_0402_50V8J

SPI_CLK_FCH_R
SPI_SI_R

13 51Friday, November 04, 2011

13 51Friday, November 04, 2011

13 51Friday, November 04, 2011

R111

R111

of

of

of

@

@

C160

C160

@

@

+3VALW

12

0.1

0.1

0.1

A

1 1

+3VALW

+3VALW

For FCH internal debug use

R179 2.2K_0402_5%@R179 2.2K_0402_5%@

1 2

R181 2.2K_0402_5%@R181 2.2K_0402_5%@

1 2

R183 2.2K_0402_5%@R183 2.2K_0402_5%@

2 2

+3VALW

3 3

+3VS

4 4

1 2

R883 10K_0402_5%@R883 10K_0402_5%@

1 2

R624 10K_0402_5%R624 10K_0402_5%

1 2

R625 10K_0402_5%R625 10K_0402_5%

1 2

R174 10K_0402_5%R174 10K_0402_5%

1 2

R618 10K_0402_5%@R618 10K_0402_5%@

1 2

R649 10K_0402_5%@R649 10K_0402_5%@

1 2

R620 10K_0402_5%@R620 10K_0402_5%@

1 2

R163 10K_0402_5%@R163 10K_0402_5%@

1 2

R164 10K_0402_5%@R164 10K_0402_5%@

1 2

R169 100K_0402_5%@R169 100K_0402_5%@

1 2

R170 10K_0402_5%@R170 10K_0402_5%@

1 2

R896 10K_0402_5%R896 10K_0402_5%

1 2

R171 2.2K_0402_5%R171 2.2K_0402_5%

1 2

R172 2.2K_0402_5%R172 2.2K_0402_5%

1 2

R175 10K_0402_5%R175 10K_0402_5%

1 2

R173 8.2K_0402_5%R173 8.2K_0402_5%

1 2

R176 8.2K_0402_5%R176 8.2K_0402_5%

1 2

R166 10K_0402_5%R166 10K_0402_5%

1 2

R168 10K_0402_5%R168 10K_0402_5%

1 2

R177 2.2K_0402_5%R177 2.2K_0402_5%

1 2

R178 10K_0402_5%@R178 10K_0402_5%@

1 2

R180 10K_0402_5%@R180 10K_0402_5%@

1 2

R182 10K_0402_5%PX@R182 10K_0402_5%PX@

1 2

ODD_DA#_FCH
ODD_DETECT#

H_THERMTRIP#

EC_LID_OUT#

FCH_PCIE_WAKE#

FCH_SCLK0

FCH_SDATA0

WD_PWRGD

WLAN_CLKREQ#

LAN_CLKREQ#

FCH_SCLK1
FCH_SDATA1
EC_RSMRST#
HDA_BITCLK
HDA_SDIN0

PEG_CLKREQ#_R

A

TEST0
TEST1
TEST2

USB_OC7#
USB_OC2#
USB_OC1#
USB_OC0#

USB_OC5#
USB_OC3#

CPPE#_R

12

UMA@

UMA@

12

PX@

PX@

+3VALW+3VALW

12

UMA@

UMA@

R685

R685

10K_0402_5%

10K_0402_5%

12

PX@

PX@

R682

R682

10K_0402_5%

10K_0402_5%

HDA_BITCLK_AUDIO<30>
HDA_SDOUT_AUDIO<30>

HDA_SDIN0<30>

HDA_SYNC_AUDIO<30>

HDA_RST_AUDIO#<30>

R684

R684

10K_0402_5%

10K_0402_5%

R683

R683

10K_0402_5%

10K_0402_5%

PEG_CLKREQ#<18>

VGA_GATE#<33>

GPIO189
GPIO190

PXS_RST#<17>
PXS_PWREN<19,43,46>

B

PCIE_RST2 : Reset PCIE device on Hudson 3

EC_LID_OUT#<33>
PM_SLP_S3#<33>

PM_SLP_S5#<33>
PBTN_OUT#<33>

FCH_PWRGD<33,47>

GATEA20<33>
KBRST#<33>

EC_SCI#<33>
EC_SMI#<33>

R155 10K_0402_5%@R155 10K_0402_5%@

1 2

FCH_PCIE_WAKE#<28,32>

H_THERMTRIP#<7>

EC_RSMRST#<33>

LAN_CLKREQ#<28>

FCH_SPKR<30>
FCH_SCLK0<10,11,32>
FCH_SDATA0<10,11,32>

WLAN_CLKREQ#<32>

VGA_PWRGD<17,19,46>

R156 0_0402_5%@R156 0_0402_5%@

ODD_DA#_FCH<31>

ODD_DETECT#<31>

USB_OC2#<35>
USB_OC1#<36>
USB_OC0#<37>

R159 33_0402_5%R159 33_0402_5%
R160 33_0402_5%R160 33_0402_5%

R161 33_0402_5%R161 33_0402_5%
R162 33_0402_5%R162 33_0402_5%

2

G

G

BOARD
Config.

GPIO189 GPIO190

1 2
1 2

1 2
1 2

13

D

D

S

S

00

12

12
12

PX@

PX@

Q112

Q112

2N7002K_SOT23-3

2N7002K_SOT23-3

FCH_PWRGD

11

B

TEST0
TEST1
TEST2

CPPE#_R
SYS_RESET#

WD_PWRGD

FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1

PEG_CLKREQ#_R

USB_OC7#
USB_OC5#
USB_OC3#

USB_OC2#
USB_OC1#
USB_OC0#

R960_0402_5% PX@ R960_0402_5% PX@
R970_0402_5% PX@ R970_0402_5% PX@

10
01

T17T17

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

HDA_SYNC
HDA_RST#

T61T61
T19T19

GPIO189
GPIO190

Function

PX4

Reserved

DIS
UMA

C

U2D

U2D

HUDSON-2

AB6

PCIE_RST2#/PCI_PME#/GEVENT4#

R2

RI#/GEVENT22#

W7

SPI_CS3#/GBE_STAT1/GEVENT21#

T3

SLP_S3#

W2

SLP_S5#

J4

PWR_BTN#

N7

PWR_GOOD

T9

TEST0

T10

TEST1/TMS

V9

TEST2

AE22

GA20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVENT2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN#/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

21807-A13-HUDSON-M3_FCBGA656

21807-A13-HUDSON-M3_FCBGA656

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

HUDSON-2

EMBEDDED CTRL

EMBEDDED CTRL

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

USBCLK/14M_25M_48M_OSC

USB MISCUSB 1.1USB 2.0USB 3.0

USB MISCUSB 1.1USB 2.0USB 3.0

USB_FSD1P/GPIO186

USB_FSD0P/GPIO185

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

SCL3_LV/GPIO195

SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198

EC_PWM2/EC_TIMER2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER3/GPIO200

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

USB_RCOMP

USB_FSD1N

USB_FSD0N

USB_HSD13P

USB_HSD13N
USB_HSD12P

USB_HSD12N
USB_HSD11P

USB_HSD11N
USB_HSD10P

USB_HSD10N

USB_HSD9P

USB_HSD9N

USB_HSD8P

USB_HSD8N

USB_HSD7P

USB_HSD7N

USB_HSD6P

USB_HSD6N

USB_HSD5P

USB_HSD5N

USB_HSD4P

USB_HSD4N

USB_HSD3P

USB_HSD3N

USB_HSD2P

USB_HSD2N

USB_HSD1P

USB_HSD1N

USB_HSD0P

USB_HSD0N

USBSS_CALRP
USBSS_CALRN

USB_SS_TX3P

USB_SS_TX3N
USB_SS_RX3P

USB_SS_RX3N

USB_SS_TX2P

USB_SS_TX2N
USB_SS_RX2P

USB_SS_RX2N

USB_SS_TX1P

USB_SS_TX1N
USB_SS_RX1P

USB_SS_RX1N

USB_SS_TX0P

USB_SS_TX0N
USB_SS_RX0P

USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

D

G8
B9
H1

H3
H6

H5
H10

G10
K10

J12
G12

F12
K12

K13
B11

D11
E10

F10
C10

A10
H9

G9
A8

C8
F8

E8
C6

A6
C5

A5
C1

C3
E1

E3
C16

A16
A14

C14
C12

A12
D15

B15
E14

F14
F15

G15
H13

G13
J16

H16
J15

K15

H19
G19
G22
G21
E22
H22
J22
H21

K21
K22
F22
F24
E24
B23
C24
F18

D

USB_RCOMP

USBSS_CALRP
USBSS_CALRN

USB30_FTX_DRX_P1
USB30_FTX_DRX_N1

USB30_FRX_DTX_P1
USB30_FRX_DTX_N1

USB30_FTX_DRX_P0
USB30_FTX_DRX_N0

USB30_FRX_DTX_P0
USB30_FRX_DTX_N0

R165 10K_0402_5%R165 10K_0402_5%
R167 10K_0402_5%R167 10K_0402_5%
R227 10K_0402_5%R227 10K_0402_5%
R228 10K_0402_5%R228 10K_0402_5%

EC_PWM2

R154 11.8K_0402_1%R154 11.8K_0402_1%

1 2

USB30_P11 <37>
USB30_N11 <37>

USB30_P10 <37>
USB30_N10 <37>

T74T74
T75T75

USB20_P5 <35>
USB20_N5 <35>

USB20_P4 <31>
USB20_N4 <31>

USB20_P3 <25>
USB20_N3 <25>

USB20_P2 <32>
USB20_N2 <32>

USB20_P1 <35>
USB20_N1 <35>

USB20_P0 <36>
USB20_N0 <36>

R864 1K_0402_1%R864 1K_0402_1%
R865 1K_0402_1%R865 1K_0402_1%

1 2
1 2
1 2
1 2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1 2
1 2

LP2

LP1

CR

BT

CMOS

WLAN

RP2

RP1

+FCH_VDD_11_SSUSB_S

USB30_FTX_DRX_P1 <37>
USB30_FTX_DRX_N1 <37>

USB30_FRX_DTX_P1 <37>
USB30_FRX_DTX_N1 <37>

USB30_FTX_DRX_P0 <37>
USB30_FTX_DRX_N0 <37>

USB30_FRX_DTX_P0 <37>
USB30_FRX_DTX_N0 <37>

EC_PWM2 <16>

strap pin

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

FCH-ACPI/USB/HDA/GPIO

FCH-ACPI/USB/HDA/GPIO

FCH-ACPI/USB/HDA/GPIO

LA8611P

LA8611P

LA8611P

E

Root

Root

Root

LP2

LP1

0.1

0.1

0.1

of

of

of

14 51Friday, November 04, 2011

14 51Friday, November 04, 2011

14 51Friday, November 04, 2011

E

A

B

C

D

E

+3VS

+FCH_VDDAN_33_DAC

1 1

+3VS +FCH_VDDAN_33_DAC

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

2 2

+3VALW

+VDDAN_33_USB

3 3

+3VS

+3VS

4 4

L4

L4

1 2

MBK1608221YZF_2P

MBK1608221YZF_2P

220 ohm

1 2

R186 0_0402_5%R186 0_0402_5%

L2

L2

L6

L6

1 2

220 ohm

L7

L7

1 2

220 ohm

L10

L10

1 2

220 ohm

L12

L12

1 2

220 ohm

30mil

+VDDPL_33_SSUSB_S

A

1 2

220 ohm

MBK1608221YZF_2P

MBK1608221YZF_2P

MBK1608221YZF_2P

MBK1608221YZF_2P

MBK1608221YZF_2P

MBK1608221YZF_2P

MBK1608221YZF_2P

MBK1608221YZF_2P

+VDDPL_33_SYS

C181

2.2U_0402_6.3V6M

C181

2.2U_0402_6.3V6M

1

2

+VDDPL_33_MLDAC

0.1U_0402_16V7K

0.1U_0402_16V7K

C180

C180

1

2

C166

2.2U_0603_6.3V4Z

C166

2.2U_0603_6.3V4Z

C167

C167

1

2

C198

2.2U_0402_6.3V6M

C198

2.2U_0402_6.3V6M

1

2

+VDDPL_33_USB_S

C210

2.2U_0402_6.3V6M

C210

2.2U_0402_6.3V6M

1

2

+VDDPL_33_PCIE

+VDDPL_33_SATA

C182

0.1U_0402_16V7K

C182

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C188

C188

1

VDDPL_33_SSUSB_S

2

For Hudson3 USB3.0 only
For Hudson2, connect to GND

LDO_CAP: Internally generated 1.8V
supply for the RGB outputs

+1.1VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C200

0.1U_0402_16V7K

C200

0.1U_0402_16V7K

1

2

C211

0.1U_0402_16V7K

C211

0.1U_0402_16V7K

1

2

C218

2.2U_0402_6.3V6M

C218

2.2U_0402_6.3V6M

1

2

C227

2.2U_0402_6.3V6M

C227

2.2U_0402_6.3V6M

1

+1.1VALW

2

+3VS

+VDDPL_33_MLDAC

1 2

MBK1608221YZF_2P

MBK1608221YZF_2P

220 ohm/2A

+3VALW

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

+1.1VALW

+1.1VALW

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

42 ohm/4A

1 2

R185 0_0603_5%R185 0_0603_5%

L5

L5

L8

L8

1 2

220 ohm/2A

L11

L11

1 2

MBK1608221YZF_2P

MBK1608221YZF_2P

220 ohm

L13

L13

1 2

MBK1608221YZF_2P

MBK1608221YZF_2P

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

L15

L15

12

22U_0603_6.3V6M

22U_0603_6.3V6M

C176

C176

C178

C178

1

1

2

2

+VDDPL_33_SYS

R188 0_0402_5%R188 0_0402_5%

1 2

R189 0_0402_5%R189 0_0402_5%

1 2

+VDDPL_33_USB_S
+VDDPL_33_PCIE
+VDDPL_33_SATA

R192 0_0402_5%R192 0_0402_5%

1 2

R193 0_0603_5%R193 0_0603_5%

1 2

R199

R199

1 2

0_0603_5%

0_0603_5%

R201

R201

1 2

0_0603_5%

0_0603_5%

B

C212

C212

C219

C219

C223

C223

10U_0603_6.3V6M

10U_0603_6.3V6M

C213

C213

1

1

2

2

C220

C220

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

1

2

2

C224

C224

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

2

2

C199

C199

1

2

R196 0_0402_5%R196 0_0402_5%

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C229

C229

1

2

C237

C237

1

2

+VDDIO_33_PCIGP

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C187

C187

1

2

+VDDPL_33_DAC
+VDDPL_33_ML

@

@

+VDDPL_11_DAC

0.1U_0402_16V7K

0.1U_0402_16V7K

C202

C202

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C215

C215

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C230

0.1U_0402_16V7K

C230

0.1U_0402_16V7K

1

2

C238

1U_0402_6.3V6K

C238

1U_0402_6.3V6K

1

2

0.1U_0402_16V7K

C179

C179

1

2

+VDDAN_11_ML

0.1U_0402_16V7K

0.1U_0402_16V7K

C216

C216

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

C231

0.1U_0402_16V7K

C231

0.1U_0402_16V7K

1

2

C239

C239

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

+FCH_VDDAN_33_DAC
+VDDPL_33_SSUSB_S

1 2

C194 2.2U_0603_6.3V4Z

C194 2.2U_0603_6.3V4Z

C201

C201

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1 2

+VDDAN_33_USB

C214

C214

1

2

+VDDAN_11_USB_S+VDDAN_11_USB_S

+VDDCR_11V_USB

C225

C225

1

2

+VDDAN_11_SSUSB

1U_0402_6.3V6K

1U_0402_6.3V6K

+VDDCR_11_SSUSB

10U_0603_6.3V6M

10U_0603_6.3V6M

U2C

U2C

HUDSON-2

102mA

AB17

VDDIO_33_PCIGP_1

AB18

VDDIO_33_PCIGP_2

AE9

VDDIO_33_PCIGP_3

AD10

VDDIO_33_PCIGP_4

AG7

VDDIO_33_PCIGP_5

AC13

VDDIO_33_PCIGP_6

AB12

VDDIO_33_PCIGP_7

AB13

VDDIO_33_PCIGP_8

AB14

VDDIO_33_PCIGP_9

AB16

VDDIO_33_PCIGP_10

47mA

H24

VDDPL_33_SYS

20mA

V22

VDDPL_33_DAC

12mA

U22

VDDPL_33_ML

30mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

D7

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

G7

VDDAN_33_USB_S_1

H8

0.1U_0402_16V7K

0.1U_0402_16V7K

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

21807-A13-HUDSON-M3_FCBGA656

21807-A13-HUDSON-M3_FCBGA656

0.1U_0402_16V7K

0.1U_0402_16V7K

C240

0.1U_0402_16V7K

C240

0.1U_0402_16V7K

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HUDSON-2

PCI/GPIO I/O

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

USB SS USB MAIN LINKGBE LAN

POWER

POWER

C

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8

CORE S0

CORE S0

VDDCR_11_9

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7
VDDAN_11_CLK_8

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
VDDAN_11_SATA_8
VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1
VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM_S

VDDIO_AZ_S

2011/10/12 2013/10/12

2011/10/12 2013/10/12

2011/10/12 2013/10/12

1007mA

C183

C183

T14
T17

1
T20
U16
U18

2
V14

V17
V20
Y17

340mA

H26
J25

C189

C189

K24
L22

1
M22
N21
N22

2
P22

1088mA

AB24
Y21
AE25

C195

C195

AD24
AB23

1
AA22
AF26
AG27

2

1337mA

AA21
Y20
AB21

C203

C203

AB22
AC22

1
AC21
AA20
AA18

2
AB20

AC19

59mA

N18
L19

C207

C207

M18
V12

1
V13
Y12
Y13

2
W11

5mA

G24

C217

C217

1

2

187mA

N20
M20

C221

C221

1

2

70mA

J24

C226

C226

1

2

12mA

M8

C232

1

@

2

26mA

AA4

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+VCC_VDDCR_11

0.1U_0402_16V7K

0.1U_0402_16V7K

C184

C184

1

2

+1.1VS_CKVDD

C190

C190

0.1U_0402_16V7K

0.1U_0402_16V7K

1

2

+VDDAN_11_PCIE

C196

C196

0.1U_0402_16V7K

0.1U_0402_16V7K

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C204

C204

1

2

+VDDIO_33_S

1U_0402_6.3V6K

1U_0402_6.3V6K

C208

C208

1

2

+VDDXL_3.3V

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

+VDDCR_1.1V

C222

C222

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

+VDDPL_11_SYS_S

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C228

C228

1

2

+VDDAN_33_HWM

C233

2.2U_0402_6.3V6M@C232

2.2U_0402_6.3V6M

1

@

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C185

C185

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C191

C191

1

2

C197

C197

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

C205

C205

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C209

C209

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K@C233

0.1U_0402_16V7K

+VDDIO_AZ

C236 2.2U_0402_6.3V6MC236 2.2U_0402_6.3V6M

D

1U_0402_6.3V6K

1U_0402_6.3V6K

C186

C186

1

2

+1.1VS_CKVDD

C192

C192

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

+VDDAN_11_PCIE

22U_0603_6.3V6M

22U_0603_6.3V6M

+AVDD_SATA

C206

C206

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1 2

C177

C177

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C193

C193

1

2

22U_0603_6.3V6M

22U_0603_6.3V6M

R195 0_0402_5%R195 0_0402_5%

R198 0_0402_5%R198 0_0402_5%

R200 0_0402_5%R200 0_0402_5%

1 2

R184 0_0805_5%R184 0_0805_5%

10U_0603_6.3V6M

10U_0603_6.3V6M

42ohm @ 100MHz

1 2

R187 0_0603_5%R187 0_0603_5%

22U_0603_6.3V6M

22U_0603_6.3V6M

42ohm @ 100MHz

1 2

R191 0_0805_5%R191 0_0805_5%

42ohm @ 100MHz

1 2

R194 0_0805_5%R194 0_0805_5%

1 2

L9

L9

1 2

MBK1608221YZF_2P

MBK1608221YZF_2P

220 ohm

1 2

R197 0_0603_5%R197 0_0603_5%

L14

L14

1 2

MBK1608221YZF_2P

MBK1608221YZF_2P

220 ohm

1 2

1 2

+1.1VS

+1.1VS

+1.1VS

+1.1VS

+3VALW

+3VALW

+VDDXL_3.3V
Tie to +3.3V_S5 rail if USB3 Wake
is supported; otherwise, tie to
+3.3V_S0 rail.
Hudson-2 designs: Tie to +3.3V_S0
rail.

+1.1VALW

+1.1VALW

+3VALW

AMD reply:
VDDAN_33_HWM_S: Please connect
it to +3.3V_S5 directly if HWM is not used.

+3VS

VDDIO_AZ_S should be tied to
+3.3/1.5V_S5 rail if Wake on Ring
is supported

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

FCH PWR

FCH PWR

FCH PWR

LA8611P

LA8611P

LA8611P

15 51Friday, November 04, 2011

15 51Friday, November 04, 2011

15 51Friday, November 04, 2011

E

of

of

of

0.1

0.1

0.1

5

4

3

2

1

U2E

U2E

HUDSON-2

A3

A33

B7

B13

D D

C C

B B

D13
E12

E16
E29

F11
F13
F16
F17
F19
F23
F25
F29

G16
G32

H12
H15
H29

K16
K27
K28

L12
L13
L15
L16

L21
M13
M16
M21
M25

N11

N13

N23

N24

P12

P18

P20

P21

P31

P33

R11

R25

R28

T11

T16

T18

K25

H25

D9
E5

F7
F9

G6

J6

J9
J10
J13
J28
J32

K7

L6

N6

R4

N8

HUDSON-2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSAN_HWM
VSSXL
VSSPL_SYS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GROUND

GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSPL_DAC

VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33

T21
L28
K33
N28

R6

STRAP PINS

PCI_CLK1

ALLOW

PULL

PCIE GEN2

HIGH

DEFAULT

FORCE

PULL

PCIE GEN1

LOW

PCI_CLK1<12>
PCI_CLK3<12>
PCI_CLK4<12>
CLK_PCI_EC<12,33>
LPC_CLK1<12>
EC_PWM2<14>
RTC_CLK<12,33>

PCI_CLK3

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAP

DEFAULT

12

12

@

@

PCI_CLK4

NON_FUSION
CLOCK MODE

FUSION
CLOCK
MODE

DEFAULT

R202 10K_0402_5%R202 10K_0402_5%

12

@

@

R214 10K_0402_5%

R214 10K_0402_5%

12

R203 10K_0402_5%

R203 10K_0402_5%

12

@

@

R215 10K_0402_5%R215 10K_0402_5%

12

CLK_PCI_EC

EC
ENABLED

EC
DISABLED

DEFAULT

R205 10K_0402_5%

R205 10K_0402_5%

R204 10K_0402_5%

R204 10K_0402_5%

12

@

@

R217 10K_0402_5%R217 10K_0402_5%

R216 10K_0402_5%R216 10K_0402_5%

12

12

12

@

@

LPC_CLK1

CLKGEN
ENABLED

DEFAULT

CLKGEN
DISABLE

R206 10K_0402_5%R206 10K_0402_5%

12

@

@

R218 10K_0402_5%

R218 10K_0402_5%

12

EC_PWM2

LPC ROM

SPI ROM

DEFAULT

+3VALW+3VALW+3VALW+3VALW+3VS+3VS+3VS

R207 10K_0402_5%

R207 10K_0402_5%

12

R219 2.2K_0402_5%R219 2.2K_0402_5%

12

@

@

R208 10K_0402_5%R208 10K_0402_5%

R220 2.2K_0402_5%

R220 2.2K_0402_5%

RTC_CLK

S5 PLUS
MODE
DISABLED

DEFAULT

S5 PLUS
MODE
ENABLED

DEBUG STRAPS

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

PCI_AD27 PCI_AD26

@

@

R209 2.2K_0402_5%

R209 2.2K_0402_5%

12

DISABLE
ILA
AUTORUN

DEFAULT

ENABLE
ILA
AUTORUN

PULL
HIGH

PULL
LOW

PCI_AD27<12>
PCI_AD26<12>
PCI_AD25<12>
PCI_AD24<12>
PCI_AD23<12>

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

PCI_AD25 PCI_AD24

USE FC
PLL

BYPASS
FC PLL

R210 2.2K_0402_5%

R210 2.2K_0402_5%

12

@

@

@

@

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

R211 2.2K_0402_5%

R211 2.2K_0402_5%

12

@

@

R212 2.2K_0402_5%

R212 2.2K_0402_5%

12

PCI_AD23

DISABLE PCI
MEM BOOT

DEFAULTDEFAULT

ENABLE PCI
MEM BOOT

R213 2.2K_0402_5%

R213 2.2K_0402_5%

12

@

@

21807-A13-HUDSON-M3_FCBGA656

A A

21807-A13-HUDSON-M3_FCBGA656

5

Security Classification

Security Classification

Security Classification

2011/10/12 2013/10/12

2011/10/12 2013/10/12

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/10/12 2013/10/12

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

FCH-VSS/Strap

FCH-VSS/Strap

FCH-VSS/Strap

LA8611P

LA8611P

LA8611P

16 51Friday, November 04, 2011

16 51Friday, November 04, 2011

16 51Friday, November 04, 2011

1

0.1

0.1

0.1

of

of

of