Compal LA-8581P QAQ10, G585, LA-8581P QAQ11 Schematic
5
D D
4
3
2
1
Compal Confidential
C C
QAQ10/11
LA-8581P
B B
SchematicREV0.1
Intel Ivy Bridge/Pather Point
UMA&OPT
2011-09-28 Rev 0.1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/09/23 2011/12/30
2011/09/23 2011/12/30
2011/09/23 2011/12/30
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
Wednesday, November 23, 2011
Wednesday, November 23, 2011
Wednesday, November 23, 2011
1
1 59
1 59
1 59
0.1
0.1
0.1
5
4
3
2
1
Compal Confidential
Model Name : QAQ10/11
File Name : LA-8581P
PEG(DIS)
PCI-E 2.0x16 5GT/s PER LANE100MHz
133MHz
Mobile
Ivy Bridge
Fan Control
page 6
CPU Dual Core
D D
VGA (DDR3)
Socket-rPGA988B
37.5mm*37.5mm
page 5,6,7,8,9,10
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 1066/1333
204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
page 11,12
NVIDIA N13P-GLP, 128bit with 1GB/2GB
page 13,14,15,16,17,18,19,20,21
page 22
OPT & UMA
CRT
HDMI Conn.
page 24
page 23
OPT & UMA
LCD Conn.
C C
port 4
PCIeMini Card
WLAN &BT
USB Port 13
PCIe Port 2
port 2 port 1
port 6
PCIe Mini Card WWAN
&SIM
PCIe Port 3
USB Port 12
page 36
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
port 3
port 5
RTL8111E&Intel 82579
PCIe port 1
page 36
100MHz
page 35,42
page 25 ~ 32
25mm*25mm
DMI X4
Intel
Panther Point-M
989pin FCBGA
HM76
RJ45
JMB385/388 Card Reader
&1394
PCIe Port 6
B B
page 37
Express Card
PCIe Port 5
USB port 8
page 39
page 39
LPC BUS
33MHz
FDI
USB/B Right
USB port 3,4
USB
Smart Card
SATA port 0
5V 1.5GHz(150MB/s)
SATA port 2
5V 1.5GHz(150MB/s)
SATA port 4
5V 1.5GHz(150MB/s)
page 44
USB port 9
page 39
SATA HDD0
SATA ODD
E-SATA
USB port 3
HD Audio
USB Left Port
USB port 1,2
page 43
Int. Camera
USB port 10
page 23
page 34
page 34
page 43
3.3V 24.576MHz/48Mhz
USB3.0
USB port 0
Finger Print
USB port 11
HDA Codec
ALC259
page 38
page 40
page 40
BIOS ROM
page 33
USB&Function/B
Power/B
Touch Pad/B
page 43
page 43
page 43
SIO
Page 47
Touch Pad
ENE KB9012
page 43
page 41
Int.KBD
page 40
TPM 1.2
page 34
MIC
Int.
page 38
MIC CONN
page 38
HP CONN
page 38
SPK CONN
page 38
RTC CKT.
page 25,47
A A
DC/DC Interface
page 45
Security Classification
Security Classification
Power Circuit DC/DC
page 51,52,53,54,55,56,57,58,59,60
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EC ROM
page 33
Compal Secret Data
Compal Secret Data
2011/09/23 2011/12/30
2011/09/23 2011/12/30
2011/09/23 2011/12/30
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
2 59Wednesday, November 23, 2011
2 59Wednesday, November 23, 2011
2 59Wednesday, November 23, 2011
1
0.1
0.1
0.1
B+
5
Ipeak=5A, Imax=3.5A, Iocp min=7.9
4
DESIGN CURRENT 5A
3
+5VALW
2
1
SUSP
N-CHANNEL
SI4800
DESIGN CURRENT 4A
+5VS
SUSP#
D D
SY8033BDBC
DESIGN CURRENT 2A
+1.8VS
RT8205
Ipeak=5A, Imax=3.5A, Iocp min=7.7
WOL_EN#
P-CHANNEL
AO-3413
SUSP
N-CHANNEL
SI4800
P-CHANNEL
AO-3413
P-CHANNEL
AO-3413
C C
P-CHANNEL
AO-3413
VR_ON
ISL95831CRZ
DESIGN CURRENT 5A
DESIGN CURRENT 330mA
DESIGN CURRENT 4A
VGA_ENVDD
DESIGN CURRENT 1.5A
BT_PWR#
DESIGN CURRENT 180mA
PCIE_OK
DESIGN CURRENT 100mA
DESIGN CURRENT 52A
+3VALW
+3V_LAN
+3VS
+LCD_VDD
+BT_VCC
+3VS_DELAY
+CPU_CORE
DESIGN CURRENT 30A
+GFX_CORE
DGPU_PWR_EN / SUSP#
APW7138
DESIGN CURRENT 26A
+VGA_CORE
SUSP#
B B
G5603RU1U
SYSON
Ipeak=18A, Imax=12.6A, Iocp min=19.8
Ipeak=15A, Imax=10.5A, Iocp min=16.5
DESIGN CURRENT 18A
DESIGN CURRENT 15A
+1.05VS_VCCP
+1.5V
+1.5V_CPU
G5603RU1U
CPU1.5V_S3_GATE / SUSP
APL5336
DESIGN CURRENT 2A
SUSP
SI4856
DESIGN CURRENT 12A
SUSP#
A A
G5603RU1U
5
4
DESIGN CURRENT 6A
+0.75VS
+1.5VS
+VCCSA
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/09/23 2011/12/30
2011/09/23 2011/12/30
2011/09/23 2011/12/30
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Power Map
Power Map
Power Map
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
3 59Wednesday, November 23, 2011
3 59Wednesday, November 23, 2011
3 59Wednesday, November 23, 2011
1
0.1
0.1
0.1
5
Voltage Rails
Power Plane Description
VIN
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+
D D
+CPU_CORE
+VGA_CORE
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
+1.05VS_VCCP
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH
+1.5V
+1.5VS
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
+3VALW +3VALW always on power rail
+3VALW_EC +3VALW always to KBC ON ON ON*
+3V_LAN
+3VALW_PCH
C C
+3VS
+5VALW
+5VALW_PCH
+5VS +5VALW to +5VS switched power rail OFFON OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON*
+RTCVCC RTC power
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
Core voltage for GPU
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
+1.5VP to +1.5V power rail for DDRIII ON ON OFF
+1.5V to +1.5VS switched power rail
+3VALW to +3V_LAN power rail for LAN
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
+3VALW to +3VS power rail
+5VALWP to +5VALW power rail
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
4
S1
S3 S5
N/A N/A N/A
N/AN/AN/A
ON
ON
OFF
OFF
OFF
OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF
OFF
ON
ON
ON ON
ON ON
ON
ON
ON ON
OFF
ON ON*
ON*
ON*
OFF
OFF
ON ON*
ON*
ON
ON
ONON
3
2
BOM configu table
SKU Description Bom config
QAQ00 UMA GIGA W/HDMI
1
QAQ01 DIS DU N12GE2G W/HDMI
2
QAQ02 UMA VPRO W/HDMI
3
4
5
6
7
8
DA8@/8111E@/PCH@/UMA@/385@/IN_TPM@/TPM@/SM@/USB30@/OPT@/388@/USB20@/VPRO@/WB_TPM@
DA8@/8111E@/PCH@/UMA@/385@/IN_TPM@
TPM@/SM@/USB30@ 4619F230L01
DA8@/8111E@/PCH@/OPT@/388@/USB20@/12GE@
DA8@/VPRO@/385@/USB20@/TPM@/IN_TPM@/SM@
4619F230L11
4619F230L21
X76 AND VGA configu table
SKU Description Config
1
4619F230L11
2
3
4
SAM1G8@ ZZZ
SAM 1G
ZZZ
SAM1G8@ ZZZ
SAM 1G
ZZZ
SAM2G@
SAM 2G
Hynix 1G
Hynix 1G
ZZZ
Hynix 2G
5
6
7
HY1G8@
HY1G8@
HY2G@
UV1
12GE@ZZZ
N12P-GE
UV1
12GV2@
N12P-GV2
UV1
12GE@
N12P-GE
QAQ01 DIS DU N12GE2G W/HDMI
1
Device
Device
PCH
Clock Generator
DDR DIMMA
DDR DIMMB
Slot#1--WLAN
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
LOW LOW LOW LOW
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
EC SM Bus2 address
+3VS EC KB930+3VL EC KB930
0001 011x b
+3VS GPU Thermal Sensor
Address
1101 001x b
1001 000x b
1001 010x b
5
Device
PCH+3VALW
4
AddressAddress
ON ON
ON
OFF
OFF
OFF
LOW
OFF
OFF
OFF
Board ID Table
Board ID Rb / Rd / Rf V min Vtyp Vmax PCB Revision
0
1
2
3
4
5
6
7
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
Ra/Rc/Re VCC
100K +/- 5% 3.3V +/- 5%
100K +/- 5%
100K +/- 5%
100K +/- 5%
100K +/- 5%
100K +/- 5%
100K +/- 5%
100K +/- 5%
3.3V +/- 5%
3.3V +/- 5%
3.3V +/- 5%
3.3V +/- 5%
3.3V +/- 5%
3.3V +/- 5%
3.3V +/- 5%
0V
0.216 V0V0.250 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
0V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
0.1
0.2
0.3
0.4
1.0
VPRO
PCH And PCBA table
UPCH1
PCH
BD82HM65 SLH9D B2 FCBGA 989P PCH
PCH@
PCB
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/09/23 2011/12/30
2011/09/23 2011/12/30
2011/09/23 2011/12/30
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
UPCH1
BD82QM67 SLJ4M B3 FCBGA 989P PCH
VPRO@
ZZZ
DA8@
PCB LA-7661P REV01
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date:
Date:
Date:
Compal Electronics, Inc.
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
Wednesday, November 23, 2011
Wednesday, November 23, 2011
Wednesday, November 23, 2011
Notes List
Notes List
Notes List
1
Sheet
Sheet
Sheet
of
of
of
4 59
4 59
4 59
0.1
0.1
0.1
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
B B
S4 (Suspend to Disk)
S5 (Soft OFF)
EC SM Bus1 address
Power Power
+3VL Smart Battery
PCH SM Bus address
Power
A A
+3VALW
+3VS
+3VS
+3VS
+3VS
V
VY BRIDGE
SS
1
F22
VSS234
F19
V
SS235
E30
SS236
V
E27
V
SS237
E24
SS238
V
E21
V
SS239
E18
SS240
V
VSS241
V
SS242
SS243
V
V
SS244
SS245
V
V
SS246
SS247
V
SS248
V
V
SS249
SS250
V
V
SS251
SS252
V
V
SS253
SS254
V
SS255
V
V
SS256
SS257
V
V
SS258
SS259
V
VSS260
SS261
V
SS262
V
V
SS263
SS264
V
V
SS265
SS266
V
VSS267
V
SS268
SS269
V
V
SS270
SS271
V
V
SS272
SS273
V
VSS274
V
V
V
V
V
V
VSS281
V
V
V
V
SS275
SS276
SS277
SS278
SS279
SS280
SS282
SS283
SS284
SS285
D
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
C
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
B
5
CPU1A
J
D
C
+
1.05VS_VCCP
1.05VS_VCCP
+
B
DMI_CRX_PTX_N0<27>
D
MI_CRX_PTX_N1<27>
D
MI_CRX_PTX_N2<27>
D
MI_CRX_PTX_N3<27>
D
MI_CRX_PTX_P0<27>
MI_CRX_PTX_P1<27>
D
MI_CRX_PTX_P2<27>
D
D
MI_CRX_PTX_P3<27>
MI_CTX_PRX_N0<27>
D
MI_CTX_PRX_N1<27>
D
D
MI_CTX_PRX_N2<27>
D
MI_CTX_PRX_N3<27>
DMI_CTX_PRX_P0<27>
MI_CTX_PRX_P1<27>
D
MI_CTX_PRX_P2<27>
D
MI_CTX_PRX_P3<27>
D
DI_CTX_PRX_N0<27>
F
F
DI_CTX_PRX_N1<27>
DI_CTX_PRX_N2<27
>
F
DI_CTX_PRX_N3<27>
F
F
DI_CTX_PRX_N4<27>
DI_CTX_PRX_N5<27>
F
F
DI_CTX_PRX_N6<27>
DI_CTX_PRX_N7<27>
F
FDI_CTX_PRX_P0<27 >
F
DI_CTX_PRX_P1<27>
DI_CTX_PRX_P2<27>
F
F
DI_CTX_PRX_P3<27>
DI_CTX_PRX_P4<27>
F
F
DI_CTX_PRX_P5<27>
DI_CTX_PRX_P6<27>
F
FDI_CTX_PRX_P7<27 >
F
DI_FSYNC0<27>
DI_FSYNC1<27>
F
F
DI_INT<27>
DI_LSYNC0<27>
F
F
DI_LSYNC1<27>
R
C4 24.9_0402_1%
1
2
10K_0402_5%
R
88
@
DI_CTX_PRX_N0
F
F
DI_CTX_PRX_N1
FDI_CTX_PRX_N2
F
DI_CTX_PRX_N3
DI_CTX_PRX_N4
F
DI_CTX_PRX_N5
F
DI_CTX_PRX_N6
F
F
DI_CTX_PRX_N7
DI_CTX_PRX_P0
F
F
DI_CTX_PRX_P1
F
DI_CTX_PRX_P2
DI_CTX_PRX_P3
F
DI_CTX_PRX_P4
F
F
DI_CTX_PRX_P5
DI_CTX_PRX_P6
F
DI_CTX_PRX_P7
F
F
DI_FSYNC0
FDI_FSYNC1
F
DI_INT
F
DI_LSYNC0
DI_LSYNC1
F
2
DP_COMP
E
1
E
DP_HPD#
B27
D
B25
D
A25
D
B24
D
B28
D
B26
DMI_RX[1]
A24
D
B23
D
G21
D
E22
D
F21
D
D21
D
G22
DMI_TX[0]
D22
D
F20
D
C21
D
A21
F
H19
F
E19
F
F18
F
B21
F
C20
F
D18
F
E17
F
A22
FDI0_TX[0]
G19
F
E20
F
G18
F
B20
F
C19
F
D19
F
F17
FDI1_TX[3]
J18
F
J17
F
H20
F
J19
F
H17
F
A18
eDP_COMPIO
A17
e
B16
e
C15
e
D15
e
C17
e
F16
eDP_TX[1]
C16
e
G15
e
C18
e
E16
e
D16
e
F15
e
TYCO_2013620-2_I
CONN@
MI_RX#[0]
MI_RX#[1]
MI_RX#[2]
MI_RX#[3]
MI_RX[0]
MI_RX[2]
MI_RX[3]
MI_TX#[0]
MI_TX#[1]
MI_TX#[2]
MI_TX#[3]
MI_TX[1]
MI_TX[2]
MI_TX[3]
DI0_TX#[0]
DI0_TX#[1]
DI0_TX#[2]
DI0_TX#[3]
DI1_TX#[0]
DI1_TX#[1]
DI1_TX#[2]
DI1_TX#[3]
DI0_TX[1]
DI0_TX[2]
DI0_TX[3]
DI1_TX[0]
DI1_TX[1]
DI1_TX[2]
DI0_FSYNC
DI1_FSYNC
DI_INT
DI0_LSYNC
DI1_LSYNC
DP_ICOMPO
DP_HPD#
DP_AUX
DP_AUX#
DP_TX[0]
DP_TX[2]
DP_TX[3]
DP_TX#[0]
DP_TX#[1]
DP_TX#[2]
DP_TX#[3]
4
EG_ICOMPI
P
EG_ICOMPO
P
P
EG_RCOMPO
P
P
P
PEG_RX#[3]
P
P
P
P
DMI
P
P
PEG_RX#[10]
P
EG_RX#[11]
EG_RX#[12]
P
P
EG_RX#[13]
EG_RX#[14]
P
P
EG_RX#[15]
P
CS
P
P
P
P
P
PEG_RX[6]
P
P
P
P
P
PEG_RX[13]
P
P
P
P
P
P
P
P
Intel(R) FDI
P
P
P
PEG_TX#[9]
EG_TX#[10]
P
EG_TX#[11]
P
CI EXPRESS* - GRAPHI
P
EG_TX#[12]
P
EG_TX#[13]
P
P
EG_TX#[14]
EG_TX#[15]
P
DP
P
e
P
P
P
P
P
VY BRIDGE
EG_RX#[0]
EG_RX#[1]
EG_RX#[2]
EG_RX#[4]
EG_RX#[5]
EG_RX#[6]
EG_RX#[7]
EG_RX#[8]
EG_RX#[9]
EG_RX[0]
EG_RX[1]
EG_RX[2]
EG_RX[3]
EG_RX[4]
EG_RX[5]
EG_RX[7]
EG_RX[8]
P
EG_RX[9]
EG_RX[10]
EG_RX[11]
EG_RX[12]
EG_RX[14]
EG_RX[15]
EG_TX#[0]
EG_TX#[1]
EG_TX#[2]
EG_TX#[3]
EG_TX#[4]
EG_TX#[5]
EG_TX#[6]
EG_TX#[7]
EG_TX#[8]
PEG_TX[0]
P
EG_TX[1]
EG_TX[2]
P
P
EG_TX[3]
EG_TX[4]
P
P
EG_TX[5]
EG_TX[6]
P
PEG_TX[7]
P
EG_TX[8]
EG_TX[9]
P
EG_TX[10]
EG_TX[11]
EG_TX[12]
EG_TX[13]
EG_TX[14]
EG_TX[15]
J22
J21
H22
K33
M35
L34
P
CIE_GTX_C_CRX_N0
J35
CIE_GTX_C_CRX_N1
P
J32
P
CIE_GTX_C_CRX_N2
H34
P
CIE_GTX_C_CRX_N3
H31
CIE_GTX_C_CRX_N4
P
G33
CIE_GTX_C_CRX_N5
P
G30
CIE_GTX_C_CRX_N6
P
F35
CIE_GTX_C_CRX_N7
P
E34
P
CIE_GTX_C_CRX_N8
E32
CIE_GTX_C_CRX_N9
P
D33
CIE_GTX_C_CRX_N10
P
D31
P
CIE_GTX_C_CRX_N11
B33
CIE_GTX_C_CRX_N12
P
C32
CIE_GTX_C_CRX_N13
P
PCIE_GTX_C_CRX_N14
J33
P
CIE_GTX_C_CRX_N15
L35
K34
P
CIE_GTX_C_CRX_P0
H35
P
CIE_GTX_C_CRX_P1
H32
CIE_GTX_C_CRX_P2
P
G34
P
CIE_GTX_C_CRX_P3
G31
CIE_GTX_C_CRX_P4
P
F33
P
CIE_GTX_C_CRX_P5
F30
CIE_GTX_C_CRX_P6
P
E35
CIE_GTX_C_CRX_P7
P
E33
PCIE_GTX_C_CRX_P8
F32
P
CIE_GTX_C_CRX_P9
D34
P
CIE_GTX_C_CRX_P10
E31
CIE_GTX_C_CRX_P11
P
C33
CIE_GTX_C_CRX_P12
P
B32
CIE_GTX_C_CRX_P13
P
P
CIE_GTX_C_CRX_P14
M29
CIE_GTX_C_CRX_P15
P
M32
M31
CIE_CTX_GRX_N0
P
L32
CIE_CTX_GRX_N1
P
L29
P
CIE_CTX_GRX_N2
K31
CIE_CTX_GRX_N3
P
K28
P
CIE_CTX_GRX_N4
J30
PCIE_CTX_GRX_N5
J28
CIE_CTX_GRX_N6
P
H29
CIE_CTX_GRX_N7
P
CIE_CTX_GRX_N8
G27
P
E29
P
CIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
F27
D28
P
CIE_CTX_GRX_N11
CIE_CTX_GRX_N12
P
F26
P
CIE_CTX_GRX_N13
E25
CIE_CTX_GRX_N14
P
PCIE_CTX_GRX_N15
M28
M33
CIE_CTX_GRX_P0
P
M30
CIE_CTX_GRX_P1
P
L31
CIE_CTX_GRX_P2
P
L28
P
CIE_CTX_GRX_P3
K30
P
CIE_CTX_GRX_P4
K27
PCIE_CTX_GRX_P5
J29
CIE_CTX_GRX_P6
P
J27
P
CIE_CTX_GRX_P7
H28
P
CIE_CTX_GRX_P8
G28
CIE_CTX_GRX_P9
P
E28
P
CIE_CTX_GRX_P10
F28
CIE_CTX_GRX_P11
P
D27
PCIE_CTX_GRX_P12
E26
P
CIE_CTX_GRX_P13
D25
CIE_CTX_GRX_P14
P
P
CIE_CTX_GRX_P15
EG_COMP
P
24.9_0402_1%
3
+1.05VS_VCCP
1
R
C2
2
P
EG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
CIE_GTX_C_CRX_N[0..1
P
CIE_GTX_C_CRX_P[0..1
P
2
1
222 0.1U_0402_16 V7KOPT@
C
2
136 0.1U_0402_16V7KOPT@
1
C
2
1
C
60 0.1U_0402_16V7 KOPT@
2
1
75 0.1U_0402_16V7 KOPT@
C
2
1
67 0.1U_0402_16V7KOPT@
C
2
1
C220 0.1U_0402_16V7KOPT@
2
1
C
118 0.1U_0402_16V7KOPT@
2
1
C
62 0.1U_0402_16 V7KOPT@
2
1
59 0.1U_0402_16V7KOPT@
C
2
1
115 0.1U_0402 _16V7KOPT@
C
2
70 0.1U_0402_16V7KOPT@
1
C
2
1
C
197 0.1U_0402_16V7 KOPT@
2
61 0.1U_0402_16 V7KOPT@
1
C
2
1
C
223 0.1U_0402_16V7KOPT@
2
1
C88 0.1U_0402_16V7 KOPT@
2
1
68 0.1U_0402_16V7KOPT@
C
2
1
209 0.1U_0402_16V7 KOPT@
C
2
1
66 0.1U_0402_16 V7KOPT@
C
2
1
C
224 0.1U_0402_16V7KOPT@
2
1
C
89 0.1U_0402_16 V7KOPT@
2
1
C
69 0.1U_0402_16V7KOPT@
2
1
C
221 0.1U_0402 _16V7KOPT@
2
1
C
135 0.1U_0402_16V7KOPT@
2
1
71 0.1U_0402_16 V7KOPT@
C
2
1
C
74 0.1U_0402_16 V7KOPT@
2
1
72 0.1U_0402_16V7KOPT@
C
2
1
C
214 0.1U_0402_16V7 KOPT@
2
1
C117 0.1U_0402_16V7KOPT@
2
1
C78 0.1U_0402_16V7KOPT@
2
1
87 0.1U_0402_16V7 KOPT@
C
2
1
79 0.1U_0402_16V7KOPT@
C
2
1
111 0.1U_0402_16V7KOPT@
C
5] <13>
nals swapped at VGA side.
PEG sig
5] <13>
P
CIE_CTX_C_GRX_N0
P
CIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
CIE_CTX_C_GRX_N3
P
CIE_CTX_C_GRX_N4
P
P
CIE_CTX_C_GRX_N5
CIE_CTX_C_GRX_N6
P
CIE_CTX_C_GRX_N7
P
P
CIE_CTX_C_GRX_N8
CIE_CTX_C_GRX_N9
P
CIE_CTX_C_GRX_N10
P
P
CIE_CTX_C_GRX_N11
P
CIE_CTX_C_GRX_N12
P
CIE_CTX_C_GRX_N13
CIE_CTX_C_GRX_N14
P
CIE_CTX_C_GRX_N15
P
P
CIE_CTX_C_GRX_P0
CIE_CTX_C_GRX_P1
P
P
CIE_CTX_C_GRX_P2
CIE_CTX_C_GRX_P3
P
CIE_CTX_C_GRX_P4
P
CIE_CTX_C_GRX_P5
P
PCIE_CTX_C_GRX_P6
CIE_CTX_C_GRX_P7
P
CIE_CTX_C_GRX_P8
P
CIE_CTX_C_GRX_P9
P
CIE_CTX_C_GRX_P10
P
P
CIE_CTX_C_GRX_P11
P
CIE_CTX_C_GRX_P12
CIE_CTX_C_GRX_P13
P
P
CIE_CTX_C_GRX_P14
CIE_CTX_C_GRX_P15
P
2
P
CIE_CTX_C_GRX_N[0..1
CIE_CTX_C_GRX_P[0..15] <13>
P
5] <13>
CPU1I
J
T35
VSS161
T34
V
T33
V
T32
V
T31
V
T30
V
T29
V
T28
VSS168
T27
V
T26
V
P9
V
P8
V
P6
V
P5
V
P3
V
P2
V
N35
V
N34
V
N33
V
N32
V
N31
V
N30
V
N29
V
N28
V
N27
V
N26
V
M34
VSS187
L33
V
L30
V
L27
V
L9
V
L8
V
L6
V
L5
VSS194
L4
V
L3
V
L2
V
L1
V
K35
V
K32
V
K29
VSS201
K26
V
J34
V
J31
V
H33
V
H30
V
H27
V
H24
V
H21
V
H18
V
H15
V
H13
V
H10
V
H9
V
H8
V
H7
V
H6
V
H5
V
H4
V
H3
VSS220
H2
V
H1
V
G35
V
G32
V
G29
V
G26
V
G23
VSS227
G20
V
G17
V
G11
V
F34
V
F31
V
F29
V
TYCO_2013620-2_I
CONN@
SS162
SS163
SS164
SS165
SS166
SS167
SS169
SS170
SS171
SS172
SS173
SS174
SS175
SS176
SS177
SS178
SS179
SS180
SS181
SS182
SS183
SS184
SS185
SS186
SS188
SS189
SS190
SS191
SS192
SS193
SS195
SS196
SS197
SS198
SS199
SS200
SS202
SS203
SS204
SS205
SS206
SS207
SS208
SS209
SS210
SS211
SS212
SS213
SS214
SS215
SS216
SS217
SS218
SS219
SS221
SS222
SS223
SS224
SS225
SS226
SS228
SS229
SS230
SS231
SS232
SS233
A
ecurity Classificati
ecurity Classificati
ecurity Classificati
Issued Date
I
ssued Date
ssued Date
I
HIS SHEET OF ENGINEE
HIS SHEET OF ENGINEE
3
on
on
on
011/09/23 2012/12/31
2
011/09/23 2012/12/31
2
2
011/09/23 2012/12/31
RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ompal Secret Data
C
ompal Secret Data
C
C
ompal Secret Data
Deciphered Date
D
eciphered Date
eciphered Date
D
2
C
ompal Elec
itle
T
T
itle
T
itle
Size Document Number
Custom
QAQ10 LA-8581P M/B
Date: Sheet
Date: Sheet
Date: Sheet
Wednesday, November 23, 2011
tronics, Inc.
1
5 60
5 60
5 60
S
S
S
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
T
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Rev
0.1
o
f
f
o
f
o
5
D D
4
3
PM_DRAM_PWRGD<27>
SYSTEM_PWROK<27>
2
R289
200_0402_1%
+3VALW +3VS
12
R104
0_0402_5%
RC21 0_0402_5%
D_PWG
RUN_ON_CPU1.5VS3#<10,45>
RC13
@
10K_0402_5%
SUSP<11,40,43,45>
+3VALW
U5
5
74AHC1G08DCKR_SC70-5
1
P
B
O
2
A
G
3
1 2
RC17
0_0402_5%
1 2
RC16
0_0402_5%
1
0.1U_0402_16V4Z
C85
4
@
@
2
G
+1.5V_CPU_VDDQ
R110
39_0402_1%
@
13
D
@
Q5
2N7002_SOT23-3
S
R81
200_0402_1%
VDDPWRGOOD
+3VS
0.1U_0402_16V4Z
5
C C
PLT_RST#<28,34,35,36,37,39,41,42,44>
PROC_SELECT#:
Sandy Bridge---output high;
Processor Pullups
H_PROCHOT#
B B
A A
1 2
220P_0402_25V8J
R47
62_0402_5%
CC62
@
H_CPUPWRGD_R
+1.05VS_VCCP
H_PROCHOT#<41,47>
H_THERMTRIP#<29>
220P_0402_25V8J
Ivy Bridge---output low.
H_SNB_IVB#<29>
T0501
H_PECI<29,41>
H_PROCHOT#
Place R58 close to CPU.
H_PM_SYNC<27>
H_CPUPWRGD<29>
VDDPWRGOOD
H_CATERR#
1 2
RC44
43_0402_1%
R58
1 2
56_0402_5%
1 2
R14 0_0402_5%
R15
1 2
0_0402_5%
R16
1 2
0_0402_5%
R79
1 2
130_0402_1%
R5010K_0402_5%
C379
@
H_PECI_R
H_PROCHOT#_R
H_THERMTRIP#_R
H_PM_SYNC_R
H_CPUPWRGD_R
VDDPWRGOOD_R
BUF_CPU_RST#
JCPU1B
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
TYCO_2013620-2_IVY BRIDGE
CONN@
BCLK
BCLK#
MISCTHERMALPWR MANAGEMENT
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
PRDY#
PREQ#
TCK
TMS
TRST#
TDI
TDO
DBR#
BPM#[0]
BPM#[1]
JTAG & BPM
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
A28
A27
A16
A15
R8
AK1
A5
A4
AP29
AP27
AR26
AR27
AP30
AR28
AP26
AL35
XDP_DBRESET#
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
CLK_CPU_DMI_R
CLK_CPU_DMI#_R
CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R
H_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI_R
XDP_TDO_R
1 2
R138 0_0402_5%
1 2
R139 0_0402_5%
1 2
R126 1K_0402_5%
1 2
R115 1K_0402_5%
H_DRAMRST# <7>
DDR3 Compensation Signals
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
EN_DFAN1<41>
CLK_CPU_DMI <26>
CLK_CPU_DMI# <26>
+1.05VS_VCCP
1A
+5VS
+FAN1
1
10mil
2
1 2
1 2
1 2
U58
1
EN
2
VIN
3
VOUT
4
VSET
G996P11U SOP 8P
C1
10U_0805_10V4Z
RC42140_0402_1%
RC4325.5_0402_1%
RC45200_0402_1%
10U_0805_10V4Z
GND
GND
GND
GND
8
7
6
5
U3
1
P
NC
4
Y
2
A
G
SN74LVC1G07DCKR_SC70-5
3
PU/PD for JTAG signals
XDP_TMS_R
XDP_TDI_R
XDP_PREQ#_R
XDP_TDO_R
XDP_TCK_R
XDP_TRST#_R
FAN Control Circuit
2
C863
1
+1.05VS_VCCP
12
C84
BUFO_CPU_RST# BUF_CPU_RST#
+FAN1
2
C864
@
1000P_0402_50V7K
1
R64
75_0402_5%
R72
43_0402_1%
RC4651_0402_5%
RC4751_0402_5%
RC4851_0402_5% @
RC4951_0402_5%
RC5751_0402_5%
RC5551_0402_5%
JFAN
1
2
3
4
5
R3 10K_0402_5%
1
C865
@
0.01U_0402_25V7K
2
12
+1.05VS_VCCP
1
2
3
GND
GND
ACES_85205-03001
CONN@
12
FAN_SPEED <41>
@
R73
0_0402_5%
+3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(2/6) PM,XDP,CLK
PROCESSOR(2/6) PM,XDP,CLK
PROCESSOR(2/6) PM,XDP,CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
6 59Wednesday, November 23, 2011
6 59Wednesday, November 23, 2011
6 59Wednesday, November 23, 2011
0.1
0.1
0.1
5
4
3
2
1
JCPU1C
DDR_A_D[0..63]<11>
D D
C C
B B
DDR_A_BS0<11>
DDR_A_BS1<11>
DDR_A_BS2<11>
DDR_A_CAS#<11>
DDR_A_RAS#<11>
DDR_A_WE#<11>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C5
SA_DQ[0]
D5
SA_DQ[1]
D3
SA_DQ[2]
D2
SA_DQ[3]
D6
SA_DQ[4]
C6
SA_DQ[5]
C2
SA_DQ[6]
C3
SA_DQ[7]
F10
SA_DQ[8]
F8
SA_DQ[9]
G10
SA_DQ[10]
G9
SA_DQ[11]
F9
SA_DQ[12]
F7
SA_DQ[13]
G8
SA_DQ[14]
G7
SA_DQ[15]
K4
SA_DQ[16]
K5
SA_DQ[17]
K1
SA_DQ[18]
J1
SA_DQ[19]
J5
SA_DQ[20]
J4
SA_DQ[21]
J2
SA_DQ[22]
K2
SA_DQ[23]
M8
SA_DQ[24]
N10
SA_DQ[25]
N8
SA_DQ[26]
N7
SA_DQ[27]
M10
SA_DQ[28]
M9
SA_DQ[29]
N9
SA_DQ[30]
M7
SA_DQ[31]
AG6
SA_DQ[32]
AG5
SA_DQ[33]
AK6
SA_DQ[34]
AK5
SA_DQ[35]
AH5
SA_DQ[36]
AH6
SA_DQ[37]
AJ5
SA_DQ[38]
AJ6
SA_DQ[39]
AJ8
SA_DQ[40]
AK8
SA_DQ[41]
AJ9
SA_DQ[42]
AK9
SA_DQ[43]
AH8
SA_DQ[44]
AH9
SA_DQ[45]
AL9
SA_DQ[46]
AL8
SA_DQ[47]
AP11
SA_DQ[48]
AN11
SA_DQ[49]
AL12
SA_DQ[50]
AM12
SA_DQ[51]
AM11
SA_DQ[52]
AL11
SA_DQ[53]
AP12
SA_DQ[54]
AN12
SA_DQ[55]
AJ14
SA_DQ[56]
AH14
SA_DQ[57]
AL15
SA_DQ[58]
AK15
SA_DQ[59]
AL14
SA_DQ[60]
AK14
SA_DQ[61]
AJ15
SA_DQ[62]
AH15
SA_DQ[63]
AE10
SA_BS[0]
AF10
SA_BS[1]
V6
SA_BS[2]
AE8
SA_CAS#
AD9
SA_RAS#
AF9
SA_WE#
TYCO_2013620-2_IVY BRIDGE
CONN@
DDR SYSTEM MEMORY A
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDRA_CLK0 <11>
DDRA_CLK0# <11>
DDRA_CKE0 <11>
DDRA_CLK1 <11>
DDRA_CLK1# <11>
DDRA_CKE1 <11>
DDRA_SCS0# <11>
DDRA_SCS1# <11>
DDRA_ODT0 <11>
DDRA_ODT1 <11>
DDR_A_DQS#[0..7] <11>
DDR_A_DQS[0..7] <11>
DDR_A_MA[0..15] <11>
DDR_B_D[0..63]<12>
DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>
DDR_B_CAS#<12>
DDR_B_RAS#<12>
DDR_B_WE#<12>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
JCPU1D
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
AM5
SB_DQ[32]
AM6
SB_DQ[33]
AR3
SB_DQ[34]
AP3
SB_DQ[35]
AN3
SB_DQ[36]
AN2
SB_DQ[37]
AN1
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
AN9
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
AN8
SB_DQ[45]
AR6
SB_DQ[46]
AR5
SB_DQ[47]
AR9
SB_DQ[48]
AJ11
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
AH11
SB_DQ[52]
AR8
SB_DQ[53]
AJ12
SB_DQ[54]
AH12
SB_DQ[55]
AT11
SB_DQ[56]
AN14
SB_DQ[57]
AR14
SB_DQ[58]
AT14
SB_DQ[59]
AT12
SB_DQ[60]
AN15
SB_DQ[61]
AR15
SB_DQ[62]
AT15
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
AA10
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
TYCO_2013620-2_IVY BRIDGE
CONN@
AE2
SB_CLK[0]
AD2
SB_CLK#[0]
R9
SB_CKE[0]
AE1
SB_CLK[1]
AD1
SB_CLK#[1]
R10
SB_CKE[1]
AB2
RSVD_TP[11]
AA2
RSVD_TP[12]
T9
RSVD_TP[13]
AA1
RSVD_TP[14]
AB1
RSVD_TP[15]
T10
RSVD_TP[16]
AD3
SB_CS#[0]
AE3
SB_CS#[1]
AD6
RSVD_TP[17]
AE6
RSVD_TP[18]
AE4
SB_ODT[0]
AD4
SB_ODT[1]
AD5
RSVD_TP[19]
AE5
RSVD_TP[20]
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
DDRB_CLK0 <12>
DDRB_CLK0# <12>
DDRB_CKE0 <12>
DDRB_CLK1 <12>
DDRB_CLK1# <12>
DDRB_CKE1 <12>
DDRB_SCS0# <12>
DDRB_SCS1# <12>
DDRB_ODT0 <12>
DDRB_ODT1 <12>
DDR_B_DQS#[0..7] <12>
DDR_B_DQS[0..7] <12>
DDR_B_MA[0..15] <12>
+1.5V
@
R124 0_0402_5%
QC3
BSS138_SOT23
D
S
13
H_DRAMRST#<6>
A A
R119
4.99K_0402_1%
5
G
2
C86
0.047U_0402_16V4Z
DDR3_DRAMRST#_RH_DRAMRST#
DRAMRST_CNTRL
R123
1K_0402_5%
R129 1K_0402_5%
R118 0_0402_5%
4
SM_DRAMRST# <11,12>
DRAMRST_CNTRL_PCH <10,26>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(3/6) DDRIII
PROCESSOR(3/6) DDRIII
PROCESSOR(3/6) DDRIII
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
1
of
of
of
7 59Wednesday, November 23, 2011
7 59Wednesday, November 23, 2011
7 59Wednesday, November 23, 2011
0.1
0.1
0.1
5
4
3
2
1
CFG Straps for Processor
D D
JCPU1E
CFG[1:0]: reserved configuration lane.
CFG[3]: reserved
CFG[17:7]: reserved configuration lanes.
CFG[17:0]:
Processor internal pull up 5~15Kohm to VCCIO
C C
B B
T266 PAD
T251 PAD
T252 PAD
T253 PAD
T254 PAD
T255 PAD
T256 PAD
T257 PAD
T258 PAD
T259 PAD
T260 PAD
T261 PAD
T267 PAD
T268 PAD
T269 PAD
T270 PAD
T262 PAD
T263 PAD
T245 PAD
T246 PAD
T247 PAD
T248 PAD
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
TYCO_2013620-2_IVY BRIDGE
CONN@
CFG
RESERVED
VCC_DIE_SENSE
VSS_DIE_SENSE
RSVD_NCTF10
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
KEY
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
CLK_RES_ITP <26>
CLK_RES_ITP# <26>
CFG[6:5]
CFG2
RC51
1K_0402_1%
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2
definition matches socket pin map definition
0:Lane Reversed
CFG4
RC52
@
1K_0402_1%
Display Port Presence Strap
1 : Disabled; No Physical Display Port
CFG4
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
CFG5
RC53
@
RC54
@
1K_0402_1%
1K_0402_1%
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
RC56
@
1K_0402_1%
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7
following RESETB de assertion
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0: PEG Wait for BIOS for training
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
PROCESSOR(4/6) RSVD,CFG
PROCESSOR(4/6) RSVD,CFG
PROCESSOR(4/6) RSVD,CFG
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
8 59Wednesday, November 23, 2011
8 59Wednesday, November 23, 2011
8 59Wednesday, November 23, 2011
1
0.1
0.1
0.1
of
of
of
5
4
3
2
1
JCPU1H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
D D
C C
B B
A A
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
TYCO_2013620-2_IVY BRIDGE
CONN@
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
+VCC_CORE
97A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
JCPU1F
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
TYCO_2013620-2_IVY BRIDGE
CONN@
POWER
PEG AND DDR
CORE SUPPLY
VSS_SENSE_VCCIO
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
8.5A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
AJ30
AJ28
AJ35
AJ34
B10
A10
+1.05VS_VCCP
VCCSENSE_R
VSSSENSE_R
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
+1.05VS_VCCP
0.1U_0402_16V4Z
CC49
12
RC61
43_0402_1%
+1.05VS_VCCP
RC137
130_0402_1%
H_CPU_SVIDDAT
Place the PU resistors
R53, R54 close to CPU
R51 0_0402_5%
R52 0_0402_5%
R168
1 2
10_0402_1%
12
R158
10_0402_1%
Package Sensing Recommendations--PDDG P30
Sense Trace Impedance Trace Length Match
VCC_SENSE /
VSS_SENSE
VCCAXG_SENSE /
VSSAXG_SENSE
VCCIO_SENSE /
VSS_SENSE_VCCIO
VCCSA
H_CPU_SVIDCLK
RC60
75_0402_5%
+1.05VS_VCCP
VCCIO_SENSE <51>
RC59 0_0402_5%
Place the PU resistors
RC60, RC137 close to CPU.
0.1U_0402_16V4Z
CC50
RC65 0_0402_5%
+VCC_CORE
12
12
R53
100_0402_1%
R54
100_0402_1%
25.5-34.5ohm
55ohm
VR_SVID_ALRT# <54>
VR_SVID_DAT <54>
VCCSENSE <54>
VSSSENSE <54>
<25 mils
VR_SVID_CLK <54>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(5/6) PWR,BYPASS
PROCESSOR(5/6) PWR,BYPASS
PROCESSOR(5/6) PWR,BYPASS
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
9 59Wednesday, November 23, 2011
9 59Wednesday, November 23, 2011
9 59Wednesday, November 23, 2011
1
0.1
0.1
0.1
5
4
3
2
1
+1.5V_CPU_VDDQ
+1.5V +1.5V_CPU_VDDQ
Q7
+VSB+3VALW
12
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCIO_SEL
R135
100K_0402_5%
3
Q208B
5
2N7002DW-T/R7_SOT363-6
4
AK35
AK34
AL1
B4
D1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
RUN_ON_CPU1.5VS3
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_SENSE
VSS_AXG_SENSE
+V_SM_VREF_CNT
VREFDQ_DIMMA_CPU
VREFDQ_DIMMB_CPU
+1.5V_CPU_VDDQ
6A
12
D D
R132
SUSP#<39,41,45,50,51,52,57>
CPU1.5V_S3_GATE<41>
+GFX_CORE
C C
B B
R133
@
0_0402_5%
0_0402_5%
33A
AR24
AR23
AR21
AR20
AR18
AR17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AH24
AH23
AH21
AH20
AH18
AH17
AT24
AT23
AT21
AT20
AT18
AT17
AP24
AP23
AP21
AP20
AP18
AP17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
+1.8VS +1.8VS_VCCPLL
RC120
0_0805_5%
A A
10U_0805_6.3V6M
1U_0402_6.3V6K
1
1
CC58
CC59
2
2
1.5A
B6
A6
330U_X_2VM_R6M
1U_0402_6.3V6K
CC60
A2
1
CC61
+
2
R134
100K_0402_5%
61
Q208A
2
2N7002DW-T/R7_SOT363-6
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VCCPLL1
VCCPLL2
VCCPLL3
POWER
GRAPHICS
1.8V RAIL
JCPU1G
TYCO_2013620-2_IVY BRIDGE
CONN@
RUN_ON_CPU1.5VS3#
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
DDR3 -1.5V RAILS
SA RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
8
7
6
5
Close to CPU
1 2
R89 10_0402_5%
1 2
R86 10_0402_5%
CC178
10A
10U_0805_6.3V6M
CC51
10U_0805_6.3V6M
H_VCCSA_VID0 <53>
H_VCCSA_VID1 <53>
RC113
@
0_0402_5%
AO4728L_SO8
1
2
3
4
12
C196
R136
0.1U_0603_50V7K
330K_0402_1%
+GFX_CORE
VCC_AXG_SENSE <54>
VSS_AXG_SENSE <54>
RC76 0_0402_5%
2
1
2
0.1U_0402_16V4Z
10U_0805_6.3V6M
10U_0805_6.3V6M
CC53
CC52
3
@
QC5
1
AP2302GN-HF_SOT23-3
RUN_ON_CPU1.5VS3
10U_0805_6.3V6M
10U_0805_6.3V6M
CC54
CC55
12
@
@
C107
CC38
10U_0805_10V4Z
+V_SM_VREF should
have 20 mil trace width
+V_SM_VREF
10U_0805_6.3V6M
1
CC56
+
CC57
330U_X_2VM_R6M
2
0.1U_0402_10V6K
+1.5V_CPU_VDDQ
check Confirm QC6, QC7 is low Rdson or not--Joyce 0929
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0603_6.3V6M
1
@
+
CC41
CC40
RC111
@
0_0402_5%
CC44
CC42
CC43
330U_X_2VM_R6M
2
+VCCSA_SENSE <53>
VCCSA_VID Configuration --CPU EDS Page99.
+VCCSA
VCCSA_VID[0] output default logic state is low for Sandy Bridge processors
+3VS
RC112
10K_0402_5%
@
1 2
+1.5V_CPU_VDDQ
R131
220_0402_5%
13
D
2
RUN_ON_CPU1.5VS3#
G
Q8
S
2N7002E-T1-GE3_SOT23-3
+1.5V_CPU_VDDQ +1.5V
C199 0.1U_0402_10V7K
C201 0.1U_0402_10V7K
CC47 0.1U_0402_10V7K
CC48 0.1U_0402_10V7K
Intel future processor compatibility design. --DG1.5 P113
RC118
1K_0402_1%
RC119
1K_0402_1%
VREFDQ_DIMMA_CPU
VREFDQ_DIMMB_CPU
@
RC121
1K_0402_1%
RC122
1K_0402_1%@
VCCSA: 0.675V (Min) ~ 0.9V (Max)
SA: System Agent
(Memory controller, DMI, PCIE controllers, and display engine)
R92
+VCCSA_SENSE
@
1 2
100_0402_1%
+VCCSA
RC77 0_0402_5%
@
2
QC6
1
AP2302GN-HF_SOT23-3
DRAMRST_CNT
RC78 0_0402_5%
@
2
QC7
1
AP2302GN-HF_SOT23-3
DRAMRST_CNT
RUN_ON_CPU1.5VS3# <6,45>
+1.5V_CPU_VDDQ
J3
2
JUMP_43X118@
J2
2
JUMP_43X118@
+V_DDR_REFA
RC79
3
0_0402_5%
R120
0_0402_5%
+V_DDR_REFB +VREF_CB
RC80
3
0_0402_5%
+1.5VS
112
+1.5V
112
+VREF_CA
RC83
@
0_0402_5%
DRAMRST_CNTRL_PCH <7,26>
RC84
@
0_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(6/6) PWR,VSS
PROCESSOR(6/6) PWR,VSS
PROCESSOR(6/6) PWR,VSS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
10 59Wednesday, November 23, 2011
10 59Wednesday, November 23, 2011
10 59Wednesday, November 23, 2011
1
0.1
0.1
0.1
D
C
B
A
+
V_DDR_REF
5
1
1.5V
+
55
R
K_0402_1%
2
1
1
1
%
A
R57
2
1K_0402_1
>
>
7>
>
>
7>
7>
1
1
0V6K
_10V6K
33
2
C1
D
DRA_CKE0<7
DR_A_BS2<7
D
DDRA_CLK0<7>
DRA_CLK0#<
D
D
DR_A_BS0<7
DR_A_WE#<7
D
D
DR_A_CAS#<
DRA_SCS1#<
D
+
_6.3V4Z
34
2
2
C1
CD1
0.1U_0402
.1U_0402_1
2.2U_0603
0
1
3VS
_6.3V4Z
1
_10V6K
60
2
C1
61
2
C1
2.2U_0603
0.1U_0402
5
DDR_
A_D0
DDR_A_D1
A_DM0
DDR_
D
DR_A_D2
DR_A_D3
D
DR_A_D8
D
DDR_A_D9
DR_A_DQS#
D
DDR_A_DQS1
DR_A_D1
D
D
DR_A_D11
DR_A_D16
D
D
DR_A_D17
DR_A_DQS#
D
A_DQS2
DDR_
D
DR_A_D18
A_D19
DDR_
DR_A_D24
D
D
DR_A_D25
DR_A_DM3
D
DR_A_D26
D
D
DR_A_D27
_CKE0
DDRA
D
DR_A_BS2
D
DR_A_MA12
D
DR_A_MA9
D
DR_A_MA8
DDR_A_MA5
A_MA3
DDR_
DR_A_MA1
D
DRA_CLK0
D
D
DRA_CLK0#
D
DR_A_MA10
DDR_A_BS0
DDR_
A_WE#
D
DR_A_CAS#
DR_A_MA13
D
_SCS1#
DDRA
D
DR_A_D32
DDR_
A_D33
DR_A_DQS#
D
D
DR_A_DQS4
D
DR_A_D34
DR_A_D35
D
DR_A_D40
D
D
DR_A_D41
DDR_A_DM5
DDR_A_D42
DR_A_D43
D
DR_A_D48
D
DR_A_D49
D
DR_A_DQS#
D
DR_A_DQS6
D
DR_A_D50
D
DDR_
A_D51
DR_A_D56
D
DDR_
A_D57
DR_A_DM7
D
DDR_
A_D58
DDR_
A_D59
1
5%
7
R6
2
10K_0402_
1
0
2
4
6
1
5%
8
R6
2
10K_0402_
1.5V
+
3A@1.5V
3A@1.5V
3A@1.5V3A@1.5V
D
DR3 SO-DIM
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
7
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
4
1.5V
+
J
DDRL
1
REF_DQ
V
3
SS2
V
5
Q0
D
7
D
Q1
9
V
SS4
D
M0
SS5
V
Q2
D
Q3
D
V
SS7
D
Q8
D
Q9
VSS9
QS#1
D
QS1
D
SS11
V
D
Q10
D
Q11
VSS13
Q16
D
Q17
D
SS15
V
D
QS#2
D
QS2
V
SS18
Q18
D
Q19
D
SS20
V
D
Q24
D
Q25
V
SS22
DM3
SS23
V
Q26
D
Q27
D
V
SS25
KE0
C
V
DD1
N
C1
9
B
A
DD3
V
A
12/BC#
A9
DD5
V
8
A
5
A
DD7
V
3
A
A
1
V
DD9
CK0
K0#
C
DD11
V
10/AP
A
B
A0
V
DD13
W
AS#
C
DD15
V
13
A
1#
S
V
DD17
N
CTEST
VSS27
Q32
D
Q33
D
SS29
V
D
QS#4
D
QS4
V
SS32
Q34
D
Q35
D
SS34
V
Q40
D
D
Q41
V
SS36
DM5
SS37
V
Q42
D
Q43
D
V
SS39
D
Q48
D
Q49
SS41
V
QS#6
D
QS6
D
SS44
V
D
Q50
D
Q51
VSS46
Q56
D
Q57
D
SS48
V
D
V
SS49
D
D
SS51
V
A0
S
DDSPD
V
S
A1
V
TT1
G1
CONN@
2
E#
M7
Q58
Q59
LCN_DA
V
SS1
D
Q4
DQ5
SS3
V
QS#0
D
QS0
D
V
SS6
D
Q6
DQ7
SS8
V
Q12
D
Q13
D
V
SS10
D
M1
R
ESET#
SS12
V
Q14
D
Q15
D
V
SS14
D
Q20
D
Q21
VSS16
M2
D
SS17
V
Q22
D
D
Q23
V
SS19
DQ28
Q29
D
SS21
V
QS#3
D
D
QS3
V
SS24
D
Q30
Q31
D
SS26
V
CKE1
DD2
V
15
A
14
A
V
DD4
11
A
A
V
DD6
A
A
VDD8
A
A
DD10
V
C
K1
C
K1#
V
DD12
BA1
AS#
R
DD14
V
0#
S
O
DT0
V
DD16
ODT1
C2
N
DD18
V
REF_CA
V
V
SS28
D
Q36
D
Q37
VSS30
M4
D
SS31
V
Q38
D
D
Q39
V
SS33
DQ44
Q45
D
SS35
V
QS#5
D
D
QS5
V
SS38
D
Q46
DQ47
SS40
V
Q52
D
Q53
D
V
SS42
D
M6
VSS43
Q54
D
Q55
D
SS45
V
D
Q60
D
Q61
V
SS47
DQS#7
QS7
D
SS50
V
Q62
D
D
Q63
V
SS52
E
VENT#
DA
S
S
TT2
V
G
N06-K4526-0101
4
M A
7
6
4
2
0
CL
2
2
4
6
A_D4
DDR_
8
DDR_A_D5
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
0
5
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DR_A_DQS#
D
A_DQS0
DDR_
DDR_
A_D6
D
DR_A_D7
A_D12
DDR_
DR_A_D13
D
DDR_
A_DM1
S
M_DRAMRST#
DR_A_D14
D
D
DR_A_D15
D
DR_A_D20
DR_A_D21
D
A_DM2
DDR_
DR_A_D22
D
DDR_A_D23
A_D28
DDR_
D
DR_A_D29
DR_A_DQS#
D
A_DQS3
DDR_
DDR_
A_D30
DDR_
A_D31
DRA_CKE1
D
A_MA15
DDR_
DR_A_MA14
D
D
DR_A_MA11
DDR_
A_MA7
DR_A_MA6
D
D
DR_A_MA4
DR_A_MA2
D
A_MA0
DDR_
DRA_CLK1
D
DDRA_CLK1#
DDR_
A_BS1
A_RAS#
DDR_
DRA_SCS0#
D
DRA_ODT0
D
D
DRA_ODT1
DR_A_D36
D
DR_A_D37
D
A_DM4
DDR_
DR_A_D38
D
A_D39
DDR_
A_D44
DDR_
DR_A_D45
D
DDR_
A_DQS#5
DR_A_DQS5
D
DDR_A_D46
DR_A_D47
D
D
DR_A_D52
D
DR_A_D53
D
DR_A_DM6
D
DR_A_D54
D
DR_A_D55
D
DR_A_D60
D
DR_A_D61
D
DR_A_DQS#
A_DQS7
DDR_
DR_A_D62
D
DR_A_D63
D
P
M_SMBDATA
PM_SMBCLK
0
3
7
+
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
0.75VS
SM_DRAMRST
D
DRA_CKE1 <
D
DRA_CLK1 <
DRA_CLK1#
D
DR_A_BS1 <
D
D
DR_A_RAS#
DRA_SCS0# <7>
D
DRA_ODT0 <
D
D
DRA_ODT1 <
P
M_SMBDATA
M_SMBCLK <
P
3
DR_A_D[0..63]<7>
D
0..7]< 7>
DR_A_DQS[
D
D
DR_A_DQS#[0..7]<7>
D
..15]<7>
DR_A_MA[0
# <7,12>
V_DDR_REF
A
+
R
C81 0_0402
VREF_CA
+
R
C82 0_0402_5%
7>
7>
<7>
+
1.5V
1
R
7>
<7>
7>
7>
1
_10V6K
38
2
C1
39
0.1U_0402
C1
<12,26,36,39>
12,26,36,39>
lassification
ecurity C
S
S
lassification
ecurity C
lassification
ecurity C
S
I
ssued Dat
ssued Dat
I
ssued Dat
I
T
HIS SHEET O
F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET O
F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
T
F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET O
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
56
1%
1K_0402_
2
+
VREF_CA
1
1
_6.3V4Z
60
R
1K_0402_
2
2.2U_0603
e
e
e
3
1%
2
+
1.05VSP_P
011/09/23 2012/12/31
2
2011/09/23 2
2
011/09/23 2
+
V_DDR_REF
_5%
@
+
VREF_CB
@
.75VR_EN#
0
2>
.75VR_EN<5
0
WRGOOD<51,53>
SUSP<6,40,43,45>
ompal Sec
C
C
ompal Sec
ompal Sec
C
100K_0
2N700
2DW-T/R7_SOT363-6
ret Data
ret Data
ret Data
D
eciphered
eciphered
D
eciphered
D
2
L
ayout Not
e:
10U_0603_
Place near JDDRL
C1
10U_0603_
1.5V
+
B
+3VALW
5
0
.75VR_EN
5535
R
402_5%
6
Q
5520A
2
USP
S
1
012/12/31
012/12/31
Date
Date
Date
2
1
43
1
6.3V6M
+
2
D2 LESR9M
40
2
C1
330U 2V Y
R
6
553
100K_
402_5%
0
3
Q
5520B
2DW-T/R7_SOT363-6
2N700
4
r
efer to QAL51, need confirm. --Joyce 0929/2011
10U_0603_
C1
C1
1
44
1
45
6.3V6M
6.3V6M
2
2
L
ayout Not
Command and Control signals of JDDRL
+
1.5V
Layout Note:
Place near JDD RL.203,204
0.75VS
+
C
Compal Electronics, Inc.
C
Title
T
itle
Title
cument Number Rev
Size Do
cument Number Rev
Size Do
Size Docum ent Number Rev
ustom
C
Custom
C
ustom
Date: Sheet
Date: Sheet
Date: Sheet
Wednesday, November 23, 2011
1
10U_0603_
10U_0603_
C1
1
46
6.3V6M
2
10U_0603_
C1
C1
1
47
1
48
47P_0402
C1
6.3V6M
2
CD1
53
6.3V6M
5
1
2
_50V8J
@
2
e: Place these 4 Caps near
0.1U_0402
1
C1
1
51
2
_10V6K
2
1U_0402_6.3V6K
C362
C3
60
1
1
2
2
ctronics, Inc.
11 60
11 60
11 60
1
0.1U_0402
C1
52
_10V6K
1U_0402_6
.3V6K
0.1U_0402
0.1U_0402
C1
C1
1
49
1
50
_10V6K
_10V6K
2
2
C3
1U_0402_6.3V6K
1U_0402_6
61
1
1
.3V6K
2
2
ompal Electronics, Inc.
ompal Ele
QAQ10 LA-8581P M/B
D
10U_0603_6
1
.3V6M
2
C
C3
59
C3
22U_0805_
69
1
6.3V6M
2
B
A
0.1
f
o
f
o
o
f
1
10U_0603_
C1
1
75
6.3V6M
2
0.1U_0402
C1
C1
79
1
80
_10V6K
2
1U_0603_1
C1
C183
1
84
0V4Z
2
ctronics, Inc.
ctronics, Inc.
1
10U_0603_
C1
CD4
1
76
8
6.3V6M
@
2
22U_0805_
C3
70
1
6.3V6M
2
2 60
1
2 60
1
1
2 60
10U_0603_
C174
1
6.3V6M
2
0.1U_0402
1
_10V6K
2
1U_0603_1
1U_0603_1
C1
1
82
1
0V4Z
0V4Z
2
2
ompal Electronics, Inc.
ompal Ele
ompal Ele
QAQ10 LA-8581P M/B
10U_0603_6
10U_0603_6
CD4
1
1
9
.3V6M
.3V6M
@
2
2
D
C
B
A
Rev
0.1
o
f
f
o
f
o
Date
Date
Date
2
2
012/12/31
012/12/31
+
1.5V
10U_0603_
1
C1
C1
+
1
71
D2 LESR9M
41
C1
330U 2V Y
72
6.3V6M
2
2
Layout Note: Place these 4 Caps near
Command and Control signals of JDDRH
Layout Note:
Place near JDDRH.203 and 204
L
ayout Note:
10U_0603_
Place near JDDRH
C1
10U_0603_
1
73
6.3V6M
1
2
6.3V6M
2
1.5V
+
0.1U_0402
C1
0.1U_0402
1
77
C178
1
_10V6K
2
_10V6K
2
+
0.75VS
1U_0603_1
C1
1
81
0V4Z
2
C
C
C
itle
T
T
e
itl
Tit
le
cument Number
Size Do
SizeD
cument Number
o
Size Docume nt Number
Date: Sheet
Date: Sheet
Date: Sheet
Wednesday, November 23, 2011
3
D
DR_B_D[0.
.63]<7>
0..7]<7>
DR_B_DQS[
D
DR_B_DQS#
[0..7]<7>
D
DR_B_MA[0
..15]<7>
D
+
1.5V
1
R
D12
_1%
1K_0402
2
VREF_CB
+
1
D13
R
1K_0402
_1%
2
ecurity C
lassification
S
Security C
lassification
S
lassification
ecurity C
I
ssued Dat
e
I
e
ssued Dat
ssued Dat
e
I
T
HIS SHEET O
F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
T
F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET O
F ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HIS SHEET O
T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
011/09/23 2012/12/31
2
011/09/23 2
2
2
011/09/23 2
3
ompal Sec
ret Data
C
Compal Secret Data
C
ret Data
ompal Sec
D
eciphered
D
eciphered
eciphered
D
V_DDR_REFB
+
1
10V6K
7
2
CD2
0.1U_0402_
C1
85
5
1.5V
+
3A@1.5V
3A@1.5V
3A@1.5V3A@1.5V
J
DDRH
1
REF_DQ
1
6.3V4Z
8
DR_B_D0
D
2
DR_B_D1
D
CD2
DR_B_DM0
D
2.2U_0603_
D
DR_B_D2
DR_B_D3
D
DR_B_D8
D
DR_B_D9
D
DR_B_DQS#
D
DR_B_DQS1
D
D
DR_B_D10
DR_B_D11
D
D
DR_B_D16
DR_B_D17
D
DR_B_DQS#
D
D
DR_B_DQS2
DR_B_D18
D
DR_B_D19
D
D
DR_B_D24
DDR_B_D25
DDR_B_DM3
DR_B_D26
D
DDR_B_D27
DDRB_CKE0
DR_B_BS2
D
DR_B_MA12
D
DDR_B_MA9
D
DR_B_MA8
D
DR_B_MA5
D
DR_B_MA3
DR_B_MA1
D
DRB_CLK0
D
D
DRB_CLK0#
DR_B_MA10
D
DR_B_BS0
D
D
DR_B_WE#
DR_B_CAS#
D
D
DR_B_MA13
DRB_SCS1#
D
DDR_B_D32
DR_B_D33
D
D
DR_B_DQS#
DR_B_DQS4
D
DR_B_D34
D
DR_B_D35
D
DR_B_D40
D
D
DR_B_D41
DR_B_DM5
D
D
DR_B_D42
D
DR_B_D43
D
DR_B_D48
D
DR_B_D49
D
DR_B_DQS#6
D
DR_B_DQS6
D
DR_B_D50
DR_B_D51
D
D
DR_B_D56
D
DR_B_D57
DDR_B_DM7
D
DR_B_D58
D
DR_B_D59
2
1
76
R
0.1U_0402
2.2U_0603
10K_0402
_5%
1
1
_6.3V4Z
2
1
C1
77 10K_040
R
_10V6K
86
2
5
V
3
SS2
V
5
D
Q0
7
D
Q1
9
D
VSS4
11
M0
D
13
SS5
V
15
Q2
D
17
D
Q3
19
V
SS7
21
D
Q8
23
Q9
D
25
SS9
V
27
QS#1
D
29
1
31
33
35
37
39
41
43
45
47
2
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
8
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
4
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
2
205
2_5%
R
D
QS1
V
SS11
D
Q10
DQ11
SS13
V
Q16
D
Q17
D
V
SS15
D
QS#2
DQS2
SS18
V
Q18
D
Q19
D
V
SS20
D
Q24
D
Q25
D
SS22
V
M3
D
SS23
V
D
Q26
D
Q27
V
SS25
C
KE0
V
DD1
NC1
A2
B
DD3
V
A12/BC#
9
A
DD5
V
9
8
A
5
A
V
DD7
A
3
A
1
DD9
V
K0
C
K0#
C
V
DD11
A
10/AP
B
A0
VDD13
E#
W
AS#
C
DD15
V
A
13
S
1#
VDD17
V
CTEST
REF_CA
N
SS27
V
Q32
D
D
Q33
V
SS29
D
QS#4
DQS4
SS32
V
Q34
D
Q35
D
V
SS34
D
Q40
DQ41
SS36
V
M5
D
SS37
V
D
Q42
D
Q43
V
SS39
DQ48
Q49
D
SS41
V
QS#6
D
D
QS6
V
SS44
DQ50
Q51
D
SS46
V
Q56
D
D
Q57
V
SS48
D
M7
VSS49
Q58
D
Q59
D
SS51
V
E
S
A0
V
DDSPD
SA1
TT1
V
1
G
N06-K4926-0101
LCN_DA
CONN@
1
+
1.5V
R
D10
2
1K_0402_1%
1
%
1
10V6K
1
RD11
2
2
CD5
1K_0402_1
D
0.1U_0402_
C
DRB_CKE0<7>
D
D
DR_B_BS2<7
>
>
DRB_CLK0<7
D
D
DRB_CLK0#<
7>
>
DR_B_BS0<7
D
D
>
DR_B_WE#<7
DR_B_CAS#<
7>
D
DDRB_SCS1#<7>
B
A
+
3VS
V
V
QS#0
D
V
V
D
D
V
SS10
ESET#
SS12
V
D
D
V
SS14
D
D
SS16
V
V
D
D
VSS19
D
D
V
QS#3
D
VSS24
D
D
V
C
V
V
V
V
V
V
R
V
V
V
V
V
V
V
V
D
D
VSS38
V
V
V
V
V
D
V
V
VENT#
4
+1.5V
2
SS1
4
Q4
D
6
D
DR_B_D4
Q5
D
8
SS3
D
DR_B_D5
10
12
QS0
D
0
DR_B_DQS#
14
DR_B_DQS0
D
SS6
16
DQ6
18
Q7
D
DM1
D
SS17
SS21
SS26
DD10
CK1#
DD12
DD14
O
DD16
O
DD18
SS28
DQ36
D
SS30
SS31
D
D
SS33
D
D
SS35
QS#5
D
D
SS40
D
D
SS42
SS43
D
D
SS45
D
DQ61
SS47
QS#7
D
SS50
D
D
SS52
V
DR_B_D6
D
20
D
DR_B_D7
SS8
22
Q12
24
Q13
DR_B_D12
D
26
D
DR_B_D13
28
30
DDR_B_DM1
32
34
Q14
36
Q15
38
40
Q20
42
Q21
44
46
M2
48
50
Q22
52
Q23
54
56
Q28
58
Q29
60
62
64
QS3
66
68
Q30
70
Q31
72
74
KE1
76
DD2
78
A
15
80
A
14
82
DD4
84
A
11
86
A
7
88
DD6
90
6
A
92
A4
94
DD8
96
2
A
98
0
A
100
102
C
K1
104
106
108
A1
B
110
AS#
112
114
S
0#
116
DT0
118
120
DT1
122
C2
N
124
126
128
130
132
Q37
134
136
M4
D
138
140
Q38
142
Q39
144
146
Q44
148
Q45
150
152
154
QS5
156
158
Q46
160
Q47
162
164
Q52
166
Q53
168
170
M6
D
172
174
Q54
176
Q55
178
180
Q60
182
184
186
188
QS7
190
192
Q62
194
Q63
196
198
200
DA
S
202
CL
S
204
TT2
206
G
2
M_DRAMRST
S
D
DR_B_D14
DR_B_D15
D
DR_B_D20
D
D
DR_B_D21
DR_B_DM2
D
DR_B_D22
D
DR_B_D23
D
D
DR_B_D28
DR_B_D29
D
DR_B_DQS#
D
DR_B_DQS3
D
DDR_B_D30
D
DR_B_D31
DRB_CKE1
D
DR_B_MA15
D
DDR_B_MA14
DR_B_MA11
D
DR_B_MA7
D
DR_B_MA6
D
DR_B_MA4
D
DDR_B_MA2
D
DR_B_MA0
D
DRB_CLK1
DRB_CLK1#
D
DR_B_BS1
D
D
DR_B_RAS#
DRB_SCS0#
D
D
DRB_ODT0
DDRB_ODT1
+
VREF_CB
D
DR_B_D36
DR_B_D37
D
DR_B_DM4
D
D
DR_B_D38
D
DR_B_D39
DR_B_D44
D
D
DR_B_D45
D
DR_B_DQS#
DR_B_DQS5
D
DR_B_D46
D
D
DR_B_D47
DR_B_D52
D
DR_B_D53
D
DR_B_DM6
D
DR_B_D54
D
D
DR_B_D55
D
DR_B_D60
DR_B_D61
D
D
DR_B_DQS#
D
DR_B_DQS7
DR_B_D62
D
DR_B_D63
D
M_SMBDATA
P
P
M_SMBCLK
4
#
3
5
7
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
S
DRB_CKE1 <
D
D
DRB_CLK1 <
DRB_CLK1#
D
DDR_B_BS1 <
D
DR_B_RAS# <7>
DRB_SCS0#
D
D
DRB_ODT0 <
DRB_ODT1 <
D
1
C1
67
2
P
M_SMBDATA
M_SMBCLK <
P
0.75VS
+
M_DRAMRST
7>
7>
<7>
7>
<7>
7>
7>
0.1U_0402
_10V6K
C1
68
<11,26,36,39>
11,26,36,39>
# <7,11>
2.2U_0603
1
_6.3V4Z
2
A
PCIE_GTX_C_CRX_P[0..15]<5>
PCIE_GTX_C_CRX_N[0..15]<5>
PCIE_CTX_C_GRX_P[0..15]<5>
PCIE_CTX_C_GRX_N[0..15]<5>
1 1
PCIE:80ohm+_10%
45~50ohm+_10%
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
2 2
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
+3VS_DGPU
termination
3 3
RV36 default unmount
1 2
RV48 10K_0402_5%
PEG_CLKREQ#<26>
PCIE_GTX_C_CRX_P[0..15]
PCIE_GTX_C_CRX_N[0..15]
PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_N[0..15]
C16 0.1U_0402_16V7KOPT@
C17 0.1U_0402_16V7KOPT@
C18 0.1U_0402_16V7KOPT@
C19 0.1U_0402_16V7KOPT@
C20 0.1U_0402_16V7KOPT@
C21 0.1U_0402_16V7KOPT@
C22 0.1U_0402_16V7KOPT@
C23 0.1U_0402_16V7KOPT@
C24 0.1U_0402_16V7KOPT@
C25 0.1U_0402_16V7KOPT@
C26 0.1U_0402_16V7KOPT@
C27 0.1U_0402_16V7KOPT@
C28 0.1U_0402_16V7KOPT@
C29 0.1U_0402_16V7KOPT@
C30 0.1U_0402_16V7KOPT@
C31 0.1U_0402_16V7KOPT@
C32 0.1U_0402_16V7KOPT@
C33 0.1U_0402_16V7KOPT@
C34 0.1U_0402_16V7KOPT@
C35 0.1U_0402_16V7KOPT@
C36 0.1U_0402_16V7KOPT@
C37 0.1U_0402_16V7KOPT@
C38 0.1U_0402_16V7KOPT@
C39 0.1U_0402_16V7KOPT@
C40 0.1U_0402_16V7KOPT@
C45 0.1U_0402_16V7KOPT@
C46 0.1U_0402_16V7KOPT@
C48 0.1U_0402_16V7KOPT@
C116 0.1U_0402_16V7KOPT@
C213 0.1U_0402_16V7KOPT@
C226 0.1U_0402_16V7KOPT@
C47 0.1U_0402_16V7KOPT@
OPT@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
PLTRST_VGA#<28>
CLK_PCIE_VGA<26>
CLK_PCIE_VGA#<26>
RV36 200_0402_1%@
RV37 2.49K_0402_1%OPT@
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12
PCIE_GTX_CRX_P11PCIE_GTX_C_CRX_P11
PCIE_GTX_CRX_N11
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
PCIE_GTX_CRX_P7
PCIE_GTX_CRX_N7
PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
PCIE_GTX_CRX_P5
PCIE_GTX_CRX_N5
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_N4
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
PEX_TSTCLK_OUT+
PEX_TSTCLK_OUT-
PEX_TREMP
PEX_TERMP: used for internal calibration.
VID Default setup is
+3VS_DGPU
for boot voltage 0.9V
12
12
12
@
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
4 4
1 2
RV165 0_0402_5%OPT@
1 2
RV166 0_0402_5%OPT@
1 2
RV167 0_0402_5%OPT@
1 2
RV168 0_0402_5%OPT@
1 2
RV169 0_0402_5%OPT@
1 2
RV170 0_0402_5%OPT@
RV159 10K_0402_5%
12
RV17110K_0402_5%
OPT@
A
12
12
@
RV160 10K_0402_5%
12
RV17210K_0402_5%
OPT@
12
@
@
OPT@
OPT@
RV162 10K_0402_5%
RV161 10K_0402_5%
RV163 10K_0402_5%
RV164 10K_0402_5%
GPU_VID0 <57>
GPU_VID1 <57>
GPU_VID2 <57>
GPU_VID3 <57>
GPU_VID4 <57>
GPU_VID5 <57>
12
12
12
12
RV17610K_0402_5%
RV17310K_0402_5%
RV17510K_0402_5%
RV17410K_0402_5%
@
@
OPT@
OPT@
B
UV1A
AN12
PEX_RX0
AM12
PEX_RX0_N
AN14
PEX_RX1
AM14
PEX_RX1_N
AP14
PEX_RX2
AP15
PEX_RX2_N
AN15
PEX_RX3
AM15
PEX_RX3_N
AN17
PEX_RX4
AM17
PEX_RX4_N
AP17
PEX_RX5
AP18
PEX_RX5_N
AN18
PEX_RX6
AM18
PEX_RX6_N
AN20
PEX_RX7
AM20
PEX_RX7_N
AP20
PEX_RX8
AP21
PEX_RX8_N
AN21
PEX_RX9
AM21
PEX_RX9_N
AN23
PEX_RX10
AM23
PEX_RX10_N
AP23
PEX_RX11
AP24
PEX_RX11_N
AN24
PEX_RX12
AM24
PEX_RX12_N
AN26
PEX_RX13
AM26
PEX_RX13_N
AP26
PEX_RX14
AP27
PEX_RX14_N
AN27
PEX_RX15
AM27
PEX_RX15_N
AK14
PEX_TX0
AJ14
PEX_TX0_N
AH14
PEX_TX1
AG14
PEX_TX1_N
AK15
PEX_TX2
AJ15
PEX_TX2_N
AL16
PEX_TX3
AK16
PEX_TX3_N
AK17
PEX_TX4
AJ17
PEX_TX4_N
AH17
PEX_TX5
AG17
PEX_TX5_N
AK18
PEX_TX6
AJ18
PEX_TX6_N
AL19
PEX_TX7
AK19
PEX_TX7_N
AK20
PEX_TX8
AJ20
PEX_TX8_N
AH20
PEX_TX9
AG20
PEX_TX9_N
AK21
PEX_TX10
AJ21
PEX_TX10_N
AL22
PEX_TX11
AK22
PEX_TX11_N
AK23
PEX_TX12
AJ23
PEX_TX12_N
AH23
PEX_TX13
AG23
PEX_TX13_N
AK24
PEX_TX14
AJ24
PEX_TX14_N
AL25
PEX_TX15
AK25
PEX_TX15_N
AJ11
PEX_WAKE_N
AL13
PEX_REFCLK
AK13
PEX_REFCLK_N
AK12
PEX_CLKREQ_N
AJ26
PEX_TSTCLK_OUT
AK26
PEX_TSTCLK_OUT_N
AJ12
PEX_RST_N
AP29
PEX_TERMP
N13P-GLP-A1 FCBGA 908P GPU
OPT@
CV46
18P_0402_50V8J
I2CS_SCL
DMN66D0LDW-7_SOT363-6
OPT@
I2CS_SDA
B
Part 1 of 7
PCI EXPRESS
RV55 1M_0402_5%
1
OPT@
+3VS_DGPU
2
OPT@
61
QV6A
+3VS_DGPU
@
5
34
QV6B
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
DACA_RED
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC
DACs
DACA_VDD
DACA_VREF
DACA_RSET
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2C
I2CC_SDA
I2CS_SCL
I2CS_SDA
PLLVDD
SP_PLLVDD
VID_PLLVDD
XTAL_IN
CLK
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN
@
GND
2
OPT@
I2CS_SCL
I2CS_SDA
0_0402_5%
3
GND
4
EC_SMB_CK2 <26,41>
EC_SMB_DA2 <26,41>
1
YV1
27MHZ_16PF_7V27000011
RV35 0_0402_5%@
RV40
P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
AK9
AL10
AL9
AM9
AN9
AG10
AP9
AP8
R4
R5
R7
R6
R2
R3
T4
T3
AD8
AE8
AD7
H3
H2
J4
H1
XTALINXTALOUT XTALIN
3
OPT@
C
猁ㄩ
LV10
+PLLVDD
60mA
CV41 under GPU
close to ball : AD8
LV18
猁ㄩ
+GPU_PLLVDD
ACIN_BUF
OPT@
CH751H-40PT_SOD323-2
VGA_PWROK <26,29,45,57>
VGA_HDMI_HPD <24>
VGA_CRT_CLK
VGA_CRT_DATA
I2CB_SCL
I2CB_SDA
VGA_LCD_CLK
VGA_LCD_DATA
I2CS_SCL
I2CS_SDA
30ohm, ESR=0.05
CV41
OPT@
0.1U_0402_16V4Z
180ohm, ESR=0.2
VID_4
VID_3
VID_1
VID_2
VID_0
ACIN_BUF
VID_5
dGPU_HDMI_HPD
RH172
10K_0402_5%
VGA_CRT_CLK
VGA_CRT_DATA
I2CB_SCL
I2CB_SDA
VGA_LCD_CLK
VGA_LCD_DATA
I2CS_SCL
I2CS_SDA
+PLLVDD
XTALIN
XTALOUT
XTAL_OUTBUFF
XTAL_SSIN
RV29 10K_0402_5%OPT@
RV30 10K_0402_5%OPT@
RH168 330K_0402_5%OPT@
@
U13
4
Y
OPT@
12
+PLLVDD
+GPU_PLLVDD
+3VS_DGPU
@
1 2
0.1U_0402_16V4Z
5
2
P
B
1
A
G
3
NC7SZ08P5X_NL_SC70-5
+3VS_DGPU
+3VS_DGPU
CV197
I2CA/B/C: Master
I2CS: Slaver (for Internal Thermal Sensor)
+GPU_PLLVDD
90mA
CV40
CV38,CV40 under
GPU
close to ball :
AE8,AD7
CV47
18P_0402_50V8J
XTAL_OUTBUFF
XTAL_SSIN
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
1 2
RV45 10K_0402_5%OPT@
1 2
RV52 10K_0402_5%OPT@
CV38
OPT@
OPT@
0.1U_0402_16V4Z
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0.1U_0402_16V4Z
D
UV2
4
Y
2 1
DV6
RV38 2.2K_0402_5%OPT@
RV39 2.2K_0402_5%OPT@
RV41 2.2K_0402_5%OPT@
RV42 2.2K_0402_5%OPT@
RV43 2.2K_0402_5%OPT@
RV44
RV46 2.2K_0402_5%OPT@
RV47
CV42
@
OPT@
4.7U_0402_6.3V6M
CV311
OPT@
4.7U_0402_6.3V6M
D
5
3
CV43
OPT@
+3VS_DGPU
2
P
B
1
A
G
NC7SZ08P5X_NL_SC70-5@
ACIN <27,41,48>
PSI: Phase shedding
+3VS_DGPU
2.2K_0402_5%OPT@
2.2K_0402_5%OPT@
SM010018510--SM01000FE00-SM010007W00--
30R@100MHz(ESR=0.5)
LV10
OPT@
1 2
BLM18PG330SN1D_0603
CV42, CV43,
CV44
LV10
22U_0805_6.3V6M
Near GPU
拸
DG
1 2
BLM18PG181SN1D_2P
CV310
22U_0805_6.3V6M
PFH: Pixel-Clock Frequency Hopping Interface.
PFH can be implemented in system software with
NVAPI to reduce interference between graphic
and wireless networking modems.
Refer to SP-04941-001
+1.05VS_DGPU
CV44
OPT@
CV42ㄛCV44
LV18
OPT@
+1.05VS_DGPU
CV311,
CV310,
LV18
Near GPU
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
GPIO I/O USAGE
O
GPIO0
GPIO1
O
O
GPIO2
O
GPIO3
O
GPIO4
GPIO5
O
O
GPIO6
O
GPIO7
GPIO8
I/O
I/O
GPIO9
O
GPIO10
O
GPIO11
GPIO12
I
GPIO13
O
GPIO14
I
GPIO15
I
GPIO16
O
GPIO17
I
GPIO18
I
GPIO19
I
GPIO20
GPIO21
22U_0805_6.3V6M
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
N13P PEG 1/9
N13P PEG 1/9
N13P PEG 1/9
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
E
GPU Core VID4
GPU Core VID3
LCD_BL_PWM
LCD_VCC or PSI
LCD_BLEN
GPU Core VID1
GPU Core VID2
3D Vision
OVERT
ALERT
MEM_VREF_CTL
GPU Core VID0
PWR_LEVEL
GPU Core VID5
HPD_AB
HPD_C
MEM_VDD_CTL or PSI
HPD_D
HPD_E
HPD_F
Reserved
Reserved
13 59Wednesday, November 23, 2011
13 59Wednesday, November 23, 2011
E
13 59Wednesday, November 23, 2011
0.1
0.1
0.1
A
MDA[15..0]
MDA[31..16]
MDA[47..32]
MDA[63..48]
U30
CMDA0
T31
CMDA1
U29
CMDA2
R34
CMDA3
R33
CMDA4
U32
CMDA5
U33
CMDA6
U28
CMDA7
V28
CMDA8
V29
CMDA9
V30
CMDA10
U34
CMDA11
U31
CMDA12
V34
CMDA13
V33
CMDA14
Y32
CMDA15
AA31
CMDA16
AA29
CMDA17
AA28
CMDA18
AC34
CMDA19
AC33
CMDA20
AA32
CMDA21
AA33
CMDA22
Y28
CMDA23
Y29
CMDA24
W31
CMDA25
Y30
CMDA26
AA34
CMDA27
Y31
CMDA28
Y34
CMDA29
Y33
CMDA30
V31
R32
AC32
R28
FBA_DEBUG0
AC28
FBA_DEBUG1
R30
R31
AB31
AC31
K31
L30
H34
FB_CLAMP:
J34
Leave as NC for N13P-PES/-GL/-GLP/-NS1
AG30
and N13M-GE1/NS1;
AG31
AJ34
Pull down with a 10K on N13P-GV, N13M-GS,
AK34
N13E-GE,N13P-GT/-GS/-LP and N14-Q1/-Q3.
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
E1
K27
U27
H26
@
66mA
CV49
0.1U_0402_16V4Z
OPT@
CV49 Under GPU
close to ball : U27
CMDA[30..0] <18,19>
RV57, RV58, RV59, RV60 change BS from
"OPT@" to "@".--Design Guide. Joyce 1018
RV57 60.4_0402_1%@
RV59 60.4_0402_1%@
CLKA0 <18>
CLKA0# <18>
CLKA1# <19>
RV152
10K_0402_5%
+FB_PLLAVDD
12
12
+1.5VSDGPU
+FB_PLLAVDD
CV50
OPT@
0.1U_0402_16V4Z
CV50 Under GPU
close to ball : K27
MDC[15..0]<20>
MDC[31..16]<20>
MDC[47..32]<21>
MDC[63..48]<21>
UV1C
MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
DQMC[3..0]<20>
DQMC[7..4]<21>
DQSC[3..0]<20>
DQSC[7..4]<21>
DQSC#[3..0]<20>
DQSC#[7..4]<21>
MDC63
DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7
DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7
DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7
G9
FBB_D0
E9
FBB_D1
G8
FBB_D2
F9
FBB_D3
F11
FBB_D4
G11
FBB_D5
F12
FBB_D6
G12
FBB_D7
G6
FBB_D8
F5
FBB_D9
E6
FBB_D10
F6
FBB_D11
F4
FBB_D12
G4
FBB_D13
E2
FBB_D14
F3
FBB_D15
C2
FBB_D16
D4
FBB_D17
D3
FBB_D18
C1
FBB_D19
B3
FBB_D20
C4
FBB_D21
B5
FBB_D22
C5
FBB_D23
A11
FBB_D24
C11
FBB_D25
D11
FBB_D26
B11
FBB_D27
D8
FBB_D28
A8
FBB_D29
C8
FBB_D30
B8
FBB_D31
F24
FBB_D32
G23
FBB_D33
E24
FBB_D34
G24
FBB_D35
D21
FBB_D36
E21
FBB_D37
G21
FBB_D38
F21
FBB_D39
G27
FBB_D40
D27
FBB_D41
G26
FBB_D42
E27
FBB_D43
E29
FBB_D44
F29
FBB_D45
E30
FBB_D46
D30
FBB_D47
A32
FBB_D48
C31
FBB_D49
C32
FBB_D50
B32
FBB_D51
D29
FBB_D52
A29
FBB_D53
C29
FBB_D54
B29
FBB_D55
B21
FBB_D56
C23
FBB_D57
A21
FBB_D58
C21
FBB_D59
B24
FBB_D60
C24
FBB_D61
B26
FBB_D62
C26
FBB_D63
E11
FBB_DQM0
E3
FBB_DQM1
A3
FBB_DQM2
C9
FBB_DQM3
F23
FBB_DQM4
F27
FBB_DQM5
C30
FBB_DQM6
A24
FBB_DQM7
D10
FBB_DQS_WP0
D5
FBB_DQS_WP1
C3
FBB_DQS_WP2
B9
FBB_DQS_WP3
E23
FBB_DQS_WP4
E28
FBB_DQS_WP5
B30
FBB_DQS_WP6
A23
FBB_DQS_WP7
D9
FBB_DQS_RN0
E4
FBB_DQS_RN1
B2
FBB_DQS_RN2
A9
FBB_DQS_RN3
D22
FBB_DQS_RN4
D28
FBB_DQS_RN5
A30
FBB_DQS_RN6
B23
FBB_DQS_RN7
N13P-GLP-A1 FCBGA 908P
OPT@
Part 2 of 7
MEMORY INTERFACE
A
MDA[15..0]<18>
MDA[31..16]<18>
MDA[47..32]<19>
MDA[63..48]<19>
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD_RFU0
FBA_CMD_RFU1
FBA_DEBUG0
FBA_DEBUG1
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
FB_CLAMP
FB_DLL_AVDD
FBA_PLL_AVDD
FB_VREF
VRAM Interface
UV1B
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
1 1
DQMA[3..0]<18>
DQMA[7..4]<19>
DQSA[3..0]<18>
DQSA[7..4]<19>
DQSA#[3..0]<18>
DQSA#[7..4]<19>
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
DQMA0
DQMA1
DQMA2DQMA2
DQMA3
DQMA4DQMA4
DQMA5
DQMA6
DQMA7
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
L28
FBA_D0
M29
FBA_D1
L29
FBA_D2
M28
FBA_D3
N31
FBA_D4
P29
FBA_D5
R29
FBA_D6
P28
FBA_D7
J28
FBA_D8
H29
FBA_D9
J29
FBA_D10
H28
FBA_D11
G29
FBA_D12
E31
FBA_D13
E32
FBA_D14
F30
FBA_D15
C34
FBA_D16
D32
FBA_D17
B33
FBA_D18
C33
FBA_D19
F33
FBA_D20
F32
FBA_D21
H33
FBA_D22
H32
FBA_D23
P34
FBA_D24
P32
FBA_D25
P31
FBA_D26
P33
FBA_D27
L31
FBA_D28
L34
FBA_D29
L32
FBA_D30
L33
FBA_D31
AG28
FBA_D32
AF29
FBA_D33
AG29
FBA_D34
AF28
FBA_D35
AD30
FBA_D36
AD29
FBA_D37
AC29
FBA_D38
AD28
FBA_D39
AJ29
FBA_D40
AK29
FBA_D41
AJ30
FBA_D42
AK28
FBA_D43
AM29
FBA_D44
AM31
FBA_D45
AN29
FBA_D46
AM30
FBA_D47
AN31
FBA_D48
AN32
FBA_D49
AP30
FBA_D50
AP32
FBA_D51
AM33
FBA_D52
AL31
FBA_D53
AK33
FBA_D54
AK32
FBA_D55
AD34
FBA_D56
AD32
FBA_D57
AC30
FBA_D58
AD33
FBA_D59
AF31
FBA_D60
AG34
FBA_D61
AG32
FBA_D62
AG33
FBA_D63
P30
FBA_DQM0
F31
FBA_DQM1
F34
FBA_DQM2
M32
FBA_DQM3
AD31
FBA_DQM4
AL29
FBA_DQM5
AM32
FBA_DQM6
AF34
FBA_DQM7
M31
FBA_DQS_WP0
G31
FBA_DQS_WP1
E33
FBA_DQS_WP2
M33
FBA_DQS_WP3
AE31
FBA_DQS_WP4
AK30
FBA_DQS_WP5
AN33
FBA_DQS_WP6
AF33
FBA_DQS_WP7
M30
FBA_DQS_RN0
H30
FBA_DQS_RN1
E34
FBA_DQS_RN2
M34
FBA_DQS_RN3
AF30
FBA_DQS_RN4
AK31
FBA_DQS_RN5
AM34
FBA_DQS_RN6
AF32
FBA_DQS_RN7
N13P-GLP-A1 FCBGA 908P GPU
OPT@
Part 3 of 7
MDC[15..0]
MDC[31..16]
MDC[47..32]
MDC[63..48]
FBB_CMD_RFU0
FBB_CMD_RFU1
FBB_DEBUG0
FBB_DEBUG1
MEMORY INTERFACE B
FBB_CLK0_N
FBB_CLK1_N
FBB_WCK01_N
FBB_WCK23_N
FBB_WCK45_N
FBB_WCK67_N
FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N
FBB_PLL_AVDD
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CLK0
FBB_CLK1
FBB_WCK01
FBB_WCK23
FBB_WCK45
FBB_WCK67
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
C12
C20
G14
G20
D12
E12
E20
F20
F8
E8
A5
A6
D24
D25
B27
C27
D6
D7
C6
B6
F26
E26
A26
A27
H17
CMDC0
CMDC1
CMDC2
CMDC3
CMDC4
CMDC5
CMDC6
CMDC7
CMDC8
CMDC9
CMDC10
CMDC11
CMDC12
CMDC13
CMDC14
CMDC15
CMDC16
CMDC17
CMDC18
CMDC19
CMDC20
CMDC21
CMDC22
CMDC23
CMDC24
CMDC25
CMDC26
CMDC27
CMDC28
CMDC29
CMDC30
FBB_DEBUG0
FBB_DEBUG1
+FB_PLLAVDD
66mA35mA
OPT@
CMDC[30..0] <20,21>
12
RV58 60.4_0402_1%@
12
RV60 60.4_0402_1%@
CLKC0 <20>
CLKC0# <20>
CLKC1 <21>
CLKC1# <21>CLKA1 <19>
+FB_PLLAVDD
+FB_PLLAVDD
CV48
CV48 Under GPU
close to ball : H17
0.1U_0402_16V4Z
+1.5VSDGPU
+FB_PLLAVDD
FBB_PLL_AVDD Design Guide:
100nF X7R 0402 1pcs per pin under GPU
22uF X5R 0805 1pcs per pin Near GPU
300mA
LV11
1 2
MPZ1608S300AT 0603
1
CV51
CV52
2
OPT@
OPT@
1U_0402_6.3V6K
22U_0805_6.3V6M
+1.05VS_DGPU
OPT@
CV53
OPT@
1U_0402_6.3V6K
30ohm@100M // ESR=0.01
SM01000EQ00-SM010031100--
bead--30ohm@100MHz (ESR=0.01ohm) 0603 1pcs Near GPU
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
N13P VRAM 2/9
N13P VRAM 2/9
N13P VRAM 2/9
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
14 59Wednesday, November 23, 2011
14 59Wednesday, November 23, 2011
14 59Wednesday, November 23, 2011
0.1
0.1
0.1
5
UV1D
AM6
IFPA_TXC
AN6
IFPA_TXC_N
AP3
IFPA_TXD0
AN3
IFPA_TXD0_N
AN5
IFPA_TXD1
AM5
IFPA_TXD1_N
AL6
IFPA_TXD2
AK6
IFPA_TXD2_N
AJ6
IFPA_TXD3
AH6
D D
RV140
@
VGA_HDMI_TX2+
VGA_HDMI_TX2VGA_HDMI_TX1+
VGA_HDMI_TX1-
VGA_HDMI_TX0+
VGA_HDMI_TX0VGA_HDMI_TXC+
VGA_HDMI_TXC-
+3VS_DGPU
12
12
RV149
4.7K_0402_5%
@
VGA_HDMI_TX2+<24>
VGA_HDMI_TX2-<24>
VGA_HDMI_TX1+<24>
VGA_HDMI_TX1-<24>
VGA_HDMI_TX0+<24>
VGA_HDMI_TX0-<24>
VGA_HDMI_TXC+<24>
VGA_HDMI_TXC-<24>
C C
4.7K_0402_5%
VGA_HDMI_CLK<24>
VGA_HDMI_DATA<24>
B B
IFPA_TXD3_N
AJ9
IFPB_TXC
AH9
IFPB_TXC_N
AP6
IFPB_TXD4
AP5
IFPB_TXD4_N
AM7
IFPB_TXD5
AL7
IFPB_TXD5_N
AN8
IFPB_TXD6
AM8
IFPB_TXD6_N
AK8
IFPB_TXD7
AL8
IFPB_TXD7_N
AK1
IFPC_L0
AJ1
IFPC_L0_N
AJ3
IFPC_L1
AJ2
IFPC_L1_N
AH3
IFPC_L2
AH4
IFPC_L2_N
AG5
IFPC_L3
AG4
IFPC_L3_N
AM1
IFPD_L0
AM2
IFPD_L0_N
AM3
IFPD_L1
AM4
IFPD_L1_N
AL3
IFPD_L2
AL4
IFPD_L2_N
AK4
IFPD_L3
AK5
IFPD_L3_N
AD2
IFPE_L0
AD3
IFPE_L0_N
AD1
IFPE_L1
AC1
IFPE_L1_N
AC2
IFPE_L2
AC3
IFPE_L2_N
AC4
IFPE_L3
AC5
IFPE_L3_N
AE3
IFPF_L0
AE4
IFPF_L0_N
AF4
IFPF_L1
AF5
IFPF_L1_N
AD4
IFPF_L2
AD5
IFPF_L2_N
AG1
IFPF_L3
AF1
IFPF_L3_N
AG3
IFPC_AUX_I2CW_SCL
AG2
IFPC_AUX_I2CW_SDA_N
AK3
IFPD_AUX_I2CX_SCL
AK2
IFPD_AUX_I2CX_SDA_N
AB3
IFPE_AUX_I2CY_SCL
AB4
IFPE_AUX_I2CY_SDA_N
AF3
IFPF_AUX_I2CZ_SCL
AF2
IFPF_AUX_I2CZ_SDA_N
N13P-GLP-A1 FCBGA 908P
OPT@
Part 4 of 7
LVDS/TMDS
MULTI_STRAP_REF0_GND
NC
VDD_SENSE
GND_SENSE
TEST
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
SERIAL
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO
GENERAL
BUFRST_N
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
THERMDP
THERMDN
4
P8
NC
AC6
NC
AJ28
NC
AJ4
NC
AJ5
NC
AL11
NC
C15
NC
D19
NC
D20
NC
D23
NC
D26
NC
H31
NC
T8
NC
V32
NC
L4
L5
@
PAD
TV5
1 2
RV177 0_0402_5%OPT@
1 2
RV178 0_0402_5%OPT@
RV88 10K_0402_5%@
DG: RV88 for XOR tree testing. --Joyce 1026
AK11
AM10
AM11
AP12
AP11
AN11
H6
H4
H5
H7
ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST
RV84 10K_0402_5%
RV82 10K_0402_5%OPT@
RV83 10K_0402_5%OPT@
OPT@
RV85 10K_0402_5%
OPT@
ROM support: 512Kbit or greater, up to 50MHz.
CEC: Place a 10K pull up resistor to 3.3V on
N13P-PES/-GL/-GLP/-NS1 and N13M-NS1
CEC
L2
L3
J1
J2
J7
J6
J5
J3
K3
K4
MULTI_STRAP_REF0_GND
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
RV153 10K_0402_5%@
RV86 10K_0402_5%OPT@
1 2
RV87 40.2K_0402_1%OPT@
PAD
TV1
PAD
TV2
PAD
TV3
PAD
TV4
+3VS_DGPU
3
VCCSENSE_VGA <57>
VSSSENSE_VGA <57>
+3VS_DGPU
@
@
@
@
+3VS_DGPU
STRAP1
STRAP2
12
Straps
12
MULTI LEVEL STRAPS
RV64
45.3K_0402_1%
RV72
@
4.99K_0402_1%
12
12
Physical
strapping pin
ROM_SCLK
ROM_SI
ROM_SO
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
SUB_VENDOR
01No VBIOS ROM
BIOS ROM is present (Default)
FB [1:0]: N13x FB Aperture Size
0
RESERVED
1
RESERVED
256 MB (Default)
2
3 RESERVED
USER Straps
1111
EDID is used
others: DG-05587 Page195
3GIO_PAD_CFG
0000--0101 RESERVED
0110 Notebook (default)
0111--1111 RESERVED
2
+3VS_DGPU
RV65
@
4.99K_0402_1%
RV73
45.3K_0402_1%
12
RV66
4.99K_0402_1%
12
RV74
10K_0402_1%
12
12
@
RV68
@
30K_0402_1%
RV67
34.8K_0402_1%
STRAP3
STRAP4
12
12
@
RV76
RV75
20K_0402_1%
4.99K_0402_1%
@
@
ROM_SISTRAP0
ROM_SO
ROM_SCLK
12
RV69
@
4.99K_0402_1%
12
RV77
@
45.3K_0402_1%
X76-
Logical
Strapping Bit3
PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
RAM_CFG[3]
FB [1]
USER [3]
3GIO_PAD_CFG_ADR[3]
PCI-DEVID [3]
SOR3_EXPOSED
RESERVED PCIE_SPEED_
Logical
Strapping Bit2
RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
FB [0] VGA_DEVICE
USER [2] USER [1] USER [0]
3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
PCI-DEVID [2] PCI-DEVID [1] PCI-DEVID [0]
SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
CHANGE_GEN3
PEX_PLL_EN_TERM:
PLL termination setting
0
Disable (Default)
1 Enable
Logical
Strapping Bit1
SMB_ALT_ADDR
PCIE_MAX_SPEED DP_PLL_VDD33V
Logical
Strapping Bit0
PCIE_MAX_SPEED
01Limited to PCIE GEN 1
PCIE GEN 2/3 capable
1
12
RV70
@
4.99K_0402_1%
12
RV78
10K_0402_1%
Resistor
Values
5K
10K
15K
20K
25K
30K
35K
45K
+3VS_DGPU
12
RV71
@
4.99K_0402_1%
12
RV79
15K_0402_1%
Pull up
Pull down
to 3V
to GND
1000 0000
1001 0001
1010 0010
1011 0011
1100 0100
1101 0101
1110 0110
1111 0111
For N13P-GLP strap table
For N13P-PES :
Strap 0 : PU45
Strap 1 : PD35
Strap 2 : PU35
ROM_SCLK : PU15
A A
5
4
ROM_SI : PD35
ROM_SO : PD10
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
N13P-GLP
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
Memory SizeFrenq. strap4strap3GPU
64M* 16* 8
900 MHz
1GB
64M* 16* 8
900 MHz
1GB
128M* 16* 8
900 MHz
2GB
128M* 16* 8
900 MHz
2GB
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Memory Config
Hynix
SA000041S20
Samsung
SA00004GS00
Hynix
SA00003YO00
Samsung
SA000047Q00
RV64
PD 45K
PU 45K
RV64
RV73
PU 45K
PD 45K
RV64
RV73
PU 45K
PD 45K
RV64
RV73
PU 45K
PD 45K
2
NC
PU 5K
RV74
NC
PU 5K
RV74
NC
PU 5K
RV74
NC
PU 5K
Title
Title
Title
N13P LVDS 3/9
N13P LVDS 3/9
N13P LVDS 3/9
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
Date: Sheet
Date: Sheet
Date: Sheet of
RV74
RV73
ROM_SIstrap2strap1strap0 ROM_SCLKROM_SO
RV77
PD 15K
RV77
PD 20K
RV77
PD 35K
RV77
PD 45K
RV70
PD 30K
RV70
PD 30K
RV70
PD 30K
RV70
PD 30K
1
NC
NC
NC
NC
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
RV71
PD 15K
RV71
PD 15K
RV71
PD 15K
RV71
PD 15K
15 59Wednesday, November 23, 2011
15 59Wednesday, November 23, 2011
15 59Wednesday, November 23, 2011
0.1
0.1
0.1
of
of
5
+1.5VSDGPU
FBVDDQ Decouping Design Guide:
D D
0.1uF X7R 0402 8pcs under GPU
1uF X7R 0603 2pcs under GPU
4.7uF X6S 0603 2pcs under GPU
10uF X5R 0805 4pcs Near GPU
CV61
OPT@
4.7U_0603_6.3V6K
CV69
OPT@
4.7U_0603_6.3V6K
Near GPU
1
1
2
OPT@
C C
+1.5VSDGPU
+1.5VSDGPU
Calibration Pin
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
B B
DDR3 GDDR5
40.2ohm
42.2ohm
51.1ohm
40.2ohm
40.2ohm
60.4ohm
1
CV84
CV83
2
2
OPT@
OPT@
10U_0603_6.3V6M
10U_0603_6.3V6M
4
Design guide no define
Under GPU
CV64
CV63
CV62
OPT@
OPT@
OPT@
1U_0402_6.3V6K
OPT@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
7200mA
CV66
CV65
OPT@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Under GPU
CV70
OPT@
1U_0402_6.3V6K
CV85
10U_0603_6.3V6M
CV71
CV79
OPT@
OPT@
0.1U_0402_16V4Z
1
CV86
2
OPT@
10U_0603_6.3V6M
RV91 10_0402_5%
RV93 10_0402_5%
RV96 40.2_0402_1%
RV98 42.2_0402_1%
RV101 51.1_0402_1%
0.1U_0402_16V4Z
OPT@
OPT@
OPT@
OPT@
OPT@
CV72
OPT@
0.1U_0402_16V4Z
12
12
12
12
12
CV73
OPT@
0.1U_0402_16V4Z
FB_VDDQ_SENSE
FB_GND_SENSE
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
M27
N27
R27
W27
W30
W33
H27
H25
UV1E
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
P27
T27
T30
T33
V27
Y27
F1
F2
J27
Part 5 of 7
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
FB_VDDQ_SENSE
FB_GND_SENSE
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
3
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_PLL_HVDD
PEX_SVDD_3V3
POWER
PEX_PLLVDD
IFPAB_PLLVDD
IFPAB_RSET
IFPA_IOVDD
IFPB_IOVDD
IFPC_PLLVDD
IFPC_IOVDD
IFPD_PLLVDD
IFPD_IOVDD
IFPEF_PLVDD
IFPEF_RSET
IFPE_IOVDD
VDD33_0
VDD33_1
VDD33_2
VDD33_3
IFPC_RSET
IFPD_RSET
IFPF_IOVDD
AG19
AG21
AG22
AG24
AH21
AH25
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
AH12
AG12
AG26
J8
K8
L8
M8
AH8
AJ8
AG8
AG9
AF7
AF8
AF6
AG7
AN2
AG6
AB8
AD6
AC7
AC8
3300 mA
CV80,CV198 Under GPU
close to ball
@
CV80 0.1U_0402_16V4Z
OPT@
CV198 0.1U_0402_16V4Z
+PEX_PLLVDD
+VDD33
+VDD33
120mA
Design guide no define
+IFPAB_PLLVDD
+IFPAB_IOVDD
+IFPC_PLLVDD
+IFPC_IOVDD
+IFPD_PLLVDD
+IFPD_IOVDD
+IFPEF_PLLVDD
+IFPEF_IOVDD
+IFPEF_IOVDD
Under GPU
CV54
OPT@
1 2
RV102 10K_0402_5%OPT@
RV90 1K_0402_5%@
1 2
RV104 10K_0402_5%OPT@
1 2
RV92 10K_0402_5%OPT@
RV94 1K_0402_5%@
1 2
RV95 10K_0402_5%OPT@
1 2
RV97 10K_0402_5%OPT@
RV99 1K_0402_5%@
1 2
RV100 10K_0402_5%OPT@
1 2
RV114 10K_0402_5%OPT@
@
RV103 1K_0402_5%
1 2
RV126 10K_0402_5%OPT@
1U_0402_6.3V6K
210mA
150mA
CV55
OPT@
1U_0402_6.3V6K
210mA
Near GPU
2
1
1
CV58
CV57
CV56
2
2
OPT@
OPT@
OPT@
Under GPU
PEX_PLL_HVDD:
N13P-GLP/PES :NC
N13P-LP : power.
10U_0603_6.3V6M
4.7U_0603_6.3V6K
Near GPU
CV75
CV74
OPT@
OPT@
1U_0402_6.3V6K
OPT@
1U_0402_6.3V6K
Under GPU
OPT@
Under GPU
OPT@
10U_0603_6.3V6M
CV87
CV90
OPT@
CV76
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CV59
22U_0805_6.3V6M
1
2
OPT@
Near GPU
CV88
OPT@
CV91
OPT@
+1.05VS_DGPU
CV68
OPT@
22U_0805_6.3V6M
1
+1.05VS_DGPU
CV60
OPT@
22U_0805_6.3V6M
1
CV77
2
OPT@
10U_0603_6.3V6M
CV78
CV67
OPT@
22U_0805_6.3V6M
10U_0603_6.3V6M
Near GPU
CV82
CV81
OPT@
OPT@
LV12
BLM18PG121SN1D_0603
CV89
OPT@
1U_0402_6.3V6K
CV92
OPT@
0.1U_0402_16V4Z
OPT@
猁
:120ohm@100MHz, ESR=0.18ohm 0603
LV12
LV12 stuff a 0ohm resistor instead for
N13E-GE, N13P-GT/-GS/-LP/-GV, N13M-GS,
4.7U_0603_6.3V6K
N14P-Q1/-Q3
CV95
OPT@
OPT@
1U_0402_6.3V6K
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
12
CV96
CV97
OPT@
1U_0402_6.3V6K
4.7U_0603_6.3V6K
+3VS_DGPU
420mA
+1.05VS_DGPU
OPT@
RV89
0_0603_5%
+3VS_DGPU
PEX_IOVVD/Q
N13P-GLP-A1 FCBGA 908P
OPT@
+IFPC_PLLVDD
1
CV215
0.1U_0402_16V4Z
@
2
+IFPC_IOVDD
110mA
50mA
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
LV7
@
LV13
@
Near GPU
12
1
CV203
@
2
4.7U_0603_6.3V6K
12
4.7U_0603_6.3V6K
1
CV205
@
2
1U_0402_6.3V4Z
1
2
1U_0402_6.3V4Z
+3VS_DGPU
BLM18PG181SN1D_0603
300ohm 100MHz, ESR=0.25ohm
+1.05VS_DGPU
A A
BLM18PG181SN1D_0603
220ohm 100MHz, ESR=0.05ohm
5
Under GPU
0.1U_0402_16V4Z
1
2
CV199
@
1
CV200
@
2
0.1U_0402_16V4Z
1
2
CV202
@
Under GPU(below 150mils)
0.1U_0402_16V4Z
1
1
2
CV204
@
CV206
0.1U_0402_16V4Z
@
2
CV201
@
4
Capacitor Type Footprint Population Location
1.0uF X6S 0402 4
4.7uF
10uF
22uF
X6S
X5R
X5R
0603
0805
0805
2
4
4
PEX_PLLVDD
Capacitor Type Footprint Population Location
100nF X6S 0402 1
X5R
1.0uF
4.7uF X5R
0603
0805
1
1
PEX_SVDD/PLL_HVDD
Capacitor Type Footprint Population Location
X5R
0.1uF 0402 1
X5R
4.7uF 0603 2 Near GPU
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Under GPU
Near GPU
Midway between GPU and Power Supply
Midway between GPU and Power Supply
Under GPU
Near GPU
Near GPU
Near GPU
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
N13P POWER & GND 4/9
N13P POWER & GND 4/9
N13P POWER & GND 4/9
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
1
16 59Wednesday, November 23, 2011
16 59Wednesday, November 23, 2011
16 59Wednesday, November 23, 2011
0.1
0.1
0.1
5
4
3
2
1
UV1F
D D
C C
B B
A A
5
A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
N13P-GLP-A1 FCBGA 908P
OPT@
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
Part 6 of 7
GND
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
60A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
UV1G
AA12
VDD_0
AA14
VDD_1
AA16
VDD_2
AA19
VDD_3
AA21
VDD_4
AA23
VDD_5
AB13
VDD_6
AB15
VDD_7
AB17
VDD_8
AB18
VDD_9
AB20
VDD_10
AB22
VDD_11
AC12
VDD_12
AC14
VDD_13
AC16
VDD_14
AC19
VDD_15
AC21
VDD_16
AC23
VDD_17
M12
VDD_18
M14
VDD_19
M16
VDD_20
M19
VDD_21
M21
VDD_22
M23
VDD_23
N13
VDD_24
N15
VDD_25
N17
VDD_26
N18
VDD_27
N20
VDD_28
N22
VDD_29
P12
VDD_30
P14
VDD_31
P16
VDD_32
P19
VDD_33
P21
VDD_34
P23
VDD_35
R13
VDD_36
R15
VDD_37
R17
VDD_38
R18
VDD_39
R20
VDD_40
R22
VDD_41
T12
VDD_42
T14
VDD_43
T16
VDD_44
T19
VDD_45
T21
VDD_46
T23
VDD_47
U13
VDD_48
U15
VDD_49
U17
VDD_50
U18
VDD_51
U20
VDD_52
U22
VDD_53
V13
VDD_54
V15
VDD_55
N13P-GLP-A1 FCBGA 908P GPU
OPT@
Part 7 of 7
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
POWER
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
Title
Title
Title
N13P POWER & GND 5/9
N13P POWER & GND 5/9
N13P POWER & GND 5/9
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
Date: Sheet
Date: Sheet of
Date: Sheet of
+VGA_CORE+VGA_CORE
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
1
0.1
0.1
0.1
of
17 59Wednesday, November 23, 2011
17 59Wednesday, November 23, 2011
17 59Wednesday, November 23, 2011
5
4
3
2
1
VRAM DDR3 chips (1GB)
D D
C C
B B
64Mx16 DDR3 *8==>1GB
128Mx16 DDR3 *8==>2GB
OPT@
OPT@
OPT@
OPT@
CLKA0
12
RV15
OPT@
160_0402_1%
CLKA0#
DQSA[7..0]
DQSA#[7..0]
DQMA[7..0]
MDA[63..0]
CMDA[30..0]
+MEM_VREF0
OPT@
+MEM_VREF1
OPT@
1 2
RV109
@
80.6_0402_1%
1 2
RV118
@
80.6_0402_1%
DQSA[7..0]<14,19>
DQSA#[7..0]<14,19>
DQMA[7..0]<14,19>
MDA[63..0]<14,19>
CMDA[30..0]<14,19>
+1.5VSDGPU
RV105
1.33K_0402_1%
RV106
1.33K_0402_1%
+1.5VSDGPU
RV107
1.33K_0402_1%
RV108
1.33K_0402_1%
CLKA0<14>
CLKA0#<14>
NV recommand 0720
UV3
X76@
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
CMDA12
CMDA27
CMDA26
CLKA0
CLKA0#
CMDA3
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
DQSA1
DQSA2
DQMA1
DQMA2
DQSA#1
DQSA#2
CMDA5
12
OPT@
M8
VREFCA
H1
VREFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
310mA
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
+MEM_VREF0
1
2
CV109
0.1U_0402_16V4Z
1
2
CV110
0.1U_0402_16V4Z
RV110
243_0402_1%
1
@
CV111
0.01U_0402_16V7K
2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
MDA12
MDA14
MDA8
MDA15
MDA9
MDA13
MDA10
MDA11
MDA17
MDA21
MDA18
MDA23
MDA19
MDA22
MDA16
MDA20
+1.5VSDGPU
+1.5VSDGPU
swap 0329
Group1
Group2
RV111
243_0402_1%
+MEM_VREF1
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
CMDA12
CMDA27
CMDA26
CLKA0
CLKA0#
CMDA3
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
DQSA0
DQSA3
DQMA0
DQMA3
DQSA#0
DQSA#3
CMDA5
ZQ1ZQ0
12
OPT@
UV4
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
C7
E7
D3
G3
B7
T2
L8
J1
L1
J9
L9
X76@
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
310mA
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
MDA3
F7
MDA4
F2
MDA2
F8
MDA7
H3
MDA0
H8
MDA5
G2
MDA1
H7
MDA6
D7
MDA27
C3
MDA29
C8
MDA25
C2
MDA30
A7
MDA24
A2
MDA28
B8
MDA26
A3
MDA31
+1.5VSDGPU
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
CMDA2
CMDA3
CMDA5
CMDA18
CMDA19
Group0
Group3
RV112 10K_0402_5%OPT@
RV113 10K_0402_5%OPT@
RV115 10K_0402_5%OPT@
RV116 10K_0402_5%OPT@
RV117 10K_0402_5%OPT@
1 2
1 2
1 2
1 2
1 2
Mode D
Address
CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21 A8
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD30
Not Available
Command Bit Default Pull-down
ODTx 10k
CKEx
DDR3
RST 10k
CS* No Termination
0..31
32..63
CS0_L#
ODT_L
CKE
A14
RST
A9
A7
A2
A0
A4
A1
BA0
WE*
A15
CAS*
CS0_H#
ODT_H
CKE_H
A13
A8
A6
A11
A5
A3
BA2
BA1
A12
A10
RAS*
LOW HIGH
10k
A14
RST
A9
A7
A2
A0
A4
A1
BA0
WE*
A15
CAS*
A13
A6
A11
A5
A3
BA2
BA1
A12
A10
RAS*
+1.5VSDGPU
1
1
CV112
2
A A
2
OPT@
0.1U_0402_16V4Z
5
close to UV3 close to UV4
1
CV113
OPT@
0.1U_0402_16V4Z
CV115
CV114
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
CV117
CV116
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV118
CV119
2
OPT@
0.1U_0402_16V4Z
4
CV120
2
OPT@
OPT@
0.1U_0402_16V4Z
1U_0402_6.3V6K
CV122
CV121
OPT@
1U_0402_6.3V6K
CV123
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.5VSDGPU
1
1U_0402_6.3V6K
Deciphered Date
Deciphered Date
Deciphered Date
1
CV134
CV130
2
OPT@
0.1U_0402_16V4Z
CV135
2
OPT@
0.1U_0402_16V4Z
2
CV136
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CV124
CV125
CV126
CV127
CV128
2
2
OPT@
OPT@
OPT@
0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
OPT@
0.1U_0402_16V4Z
1U_0402_6.3V6K
1U_0402_6.3V6K
2011/09/23 2012/12/31
2011/09/23 2012/12/31
2011/09/23 2012/12/31
CV129
OPT@
OPT@
1U_0402_6.3V6K
Compal Secret Data
Compal Secret Data
Compal Secret Data
CV137
CV138
OPT@
OPT@
1U_0402_6.3V6K
1U_0402_6.3V6K
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet of
Compal Electronics, Inc.
N13P DDR3 6/9
N13P DDR3 6/9
N13P DDR3 6/9
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
QAQ10 LA-8581P M/B
1
0.1
0.1
18 59Wednesday, November 23, 2011
18 59Wednesday, November 23, 2011
18 59Wednesday, November 23, 2011
0.1
of
of
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