COMPAL LA-8581P Schematics

5

4

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

3

2

1

D

D

Compal Confidential

C

C

QAQ10/11

LA-8581P

B

Intel Ivy Bridge/Pather Point

UMA&OPT

2012-04-23 Rev 1.0

SchematicREV1.0

B

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2011/09/23 2011/12/30

2011/09/23 2011/12/30

2011/09/23 2011/12/30

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

4019IE

4019IE

4019IE

Friday, August 24, 2012

Friday, August 24, 2012

Friday, August 24, 2012

1 60

of

1 60

of

1 60

of

1

A

B

B

B

Compal Confidential
Model Name : QAQ10/11
File Name : LA-8581P

D

C

port 4

PCIeMini Card
WLAN &BT

USB Port 13

PCIe Port 2

page 36

B

USB&Function/B

page 43

Power/B

page 43

Touch Pad/B

page 43

5

4

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

page 22

page 23

PCI-E 2.0x16 5GT/s PER LANE100MHz

CRT

LCD Conn.

port 5

page 39

RTL8111E&Intel 82579

PCIe port 1

PEG(DIS)

VGA (DDR3)

NVIDIA N13P-GLP, 128bit with 1GB/2GB

page 13,14,15,16,17,18,19,20,21

HDMI Conn.

page 24

PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)

port 2 port 1

port 6

JMB385/388 Card Reader
&1394
PCIe Port 6

port 3

PCIe Mini Card WWAN
&SIM

PCIe Port 5

USB Port 12

page 36

page 37

Express Card
PCIe Port 3

USB port 8

133MHz

OPT & UMA

OPT & UMA

page 35,42

RJ45

page 39

SIO

Page 47

Mobile

37.5mm*37.5mm

100MHz

Touch Pad

3

Ivy Bridge

CPU Dual Core

Socket-rPGA988B/989

page 5,6,7,8,9,10

DMI X4

Intel
Panther Point-M

989pin FCBGA

HM76

page 25 ~ 32

25mm*25mm

LPC BUS

33MHz

ENE KB9012

page 41

page 43

Memory BUS(DDRIII)

FDI

USB

SATA port 0

5V 1.5GHz(150MB/s)

SATA port 2

5V 1.5GHz(150MB/s)

SATA port 4

5V 1.5GHz(150MB/s)

TPM 1.2

Int.KBD

page 40

2

Dual Channel

1.5V DDRIII 1333/1600

USB/B Right

USB port 3,4

page 44

Smart Card

USB port 2

page 39

SATA HDD0

SATA ODD

E-SATA

USB port 3

HD Audio

page 34

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

USB Left Port

USB port 1,9

page 43

Int. Camera

USB port 10

page 23

page 34

page 34

page 43

3.3V 24.576MHz/48Mhz

Int.

page 38

MIC

USB3.0

USB port 0

Finger Print

USB port 11

HDA Codec

ALC259

page 38

MIC CONN

page 38

page 40

page 40

1

page 11,12

BIOS ROM

HP CONN

page 38

Fan Control

page 6

page 33

SPK CONN

page 38

D

C

B

RTC CKT.

page 25,47

A

DC/DC Interface

page 45

Power Circuit DC/DC

page 46,47,48,49,50,51 ,52,53,54,55,56,57,58

5

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRON ICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

4

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2011/09/23 2011/12/30

2011/09/23 2011/12/30

2011/09/23 2011/12/30

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

4019IE

4019IE

4019IE

2 60Friday, August 24, 2012

2 60Friday, August 24, 2012

2 60Friday, August 24, 2012

1

B

B

B

of

of

of

3

+5VALW

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

+5VS

+1.8VS

SI4800

4

SUSP

SUSP#

DESIGN CURRENT 5A

DESIGN CURRENT 4A

DESIGN CURRENT 2A

5

B+

Ipeak=5A, Ima x=3.5A, Iocp min=7.9

N-CHANNEL

D

SY8033BDBC

2

1

D

RT8205

Ipeak=5A, Ima x=3.5A, Iocp min=7.7

WOL_EN#

P-CHANNEL

N-CHANNEL

C

VR_ON

SUSP

SI4800

AO-3413

P-CHANNEL

AO-3413

P-CHANNEL

AO-3413

P-CHANNEL

AO-3413

ISL95831CRZ

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 4A

VGA_ENVDD

DESIGN CURRENT 1.5A

BT_PWR#

DESIGN CURRENT 180mA

PCIE_OK

DESIGN CURRENT 100mA

DESIGN CURRENT 52A

+3VALW

+3V_LAN

+3VS

+LCD_VDD

+BT_VCC

+3VS_DELAY

+CPU_CORE

C

DESIGN CURRENT 30A

DGPU_PWR_EN / SUSP#

APW7138

SUSP#

G5603RU1U

B

SYSON

G5603RU1U

Ipeak=18A, Im ax=12.6A, Ioc p min=19.8

Ipeak=15A, Im ax=10.5A, Ioc p min=16.5

CPU1.5V_S3_GATE / SUSP

APL5336

SUSP

SUSP#

A

G5603RU1U

5

SI4856

4

DESIGN CURRENT 26A

DESIGN CURRENT 18A

DESIGN CURRENT 15A

DESIGN CURRENT 2A

DESIGN CURRENT 12A

DESIGN CURRENT 6A

+GFX_CORE

+VGA_CORE

+1.05VS_VCCP

+1.5V

+1.5V_CPU

+0.75VS

+1.5VS

+VCCSA

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/09/23 2011/12/30

2011/09/23 2011/12/30

2011/09/23 2011/12/30

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

4019IE

4019IE

4019IE

3 60Friday, August 24, 2012

3 60Friday, August 24, 2012

3 60Friday, August 24, 2012

1

of

of

of

B

A

B

B

B

Voltage Rails

Power Plane Description

VIN

BATT+ Battery power supply (12.6V) N/A N/A N/A

B+

+VCC_CORE

D

+VGA_CORE

+VGFX_CORE Core voltage for UMA graphic ON OFF OFF

+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator

+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU

+1.05VS_VCCP

+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH

+1.5V

+1.5VS

+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF

+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU

+3VALW +3VALW always on power rail

+3VALW_EC + 3VALW always to KBC ON ON ON*

+3V_LAN

+3VALW_PCH

+3VS

C

+5VALW

+5VALW_PCH

+5VS + 5VALW to +5VS switched power rail OFFON OFF

+VSB +VSBP to +VSB always on power rail for sequence control ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

B

S5 (Soft OFF)

EC SM Bus1 address

Power Power

+3VL Smart Battery

5

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

Core voltage for GPU

+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU

+1.5VP to +1.5V power rail for DDRIII ON ON OFF

+1.5V to +1.5VS switched power rail

+3VALW to +3V_LAN power rail for LAN

+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5VALW_PCH power rail for PCH (Short resister)

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Device

HIGH HIGH HIGH HIGH

LOW

LOW

HIGH

LOW

LOWLOWLOW

LOW LOW LOW LOW

EC SM Bus2 address

0x12

0x16

+3VS VGA(N13P-GLP)+3VL charger

+3VS PCH

HIGHHIGHHIGH

HIGH

HIGH

Device

ON

ON

ON

ON

ON

PCH SM Bus address

Power

Device

PCH

+3VALW

A

+3VS

+3VS

+3VS

+3VS

Clock Generator

DDR DIMMA

DDR DIMMB

Slot#1--WLAN

Address

1101 001x b

1001 000x b

1001 010x b

5

4

S1

N/A N/A N/A

ON

ON

ON OFF OFF

ON OFF OFF

ON OFF OFF

ON OFF OFF

ON OFF OFF

ON

ON

ON ON

ON ON

ON

ON

ON ON

ONONON ON

ON

OFF

OFF

AddressAddress

0X9E

0x96

4

S3 S5

OFF

OFF

OFF

ON ON*

OFF

ON ON*

ON

OFF

OFF

OFF

3

2

1

BOM configu table

SKU Description B om config

QAQ10 UMA GIGA W/HDMI

N/AN/AN/A

OFF

OFF

1

QAQ11 DIS N13PGLP1G W/HDMI

2

QAQ13 DIS GLP2G W/HDMI/TPM

3

DA8@/8111E@/UMA@/TF@/10@/WIN8@/388@/COM@

DA8@/8111E@/OPT@/TF@/11@/WIN8@/388@/COM@

DA8@/8111E@/OPT@/030@/13@/WIN8@/388@/COM@
/TPM@/IN_TPM@

4

5

6

7

8

OFF

ON*

ON*

OFF

ON*

ONONONON

LOW

OFF

OFF

OFF

DA8@/8111E@/PCH@/UMA@/OPT@ /385@/388@/389@/IN_TPM@/TP M@/WB_TPM@/SM@/COM@/030@/T F@
/WIN8@/10@/11@/12@/13@/Rev 02@/Rev03@/Rev04@/Rev10@/V PRO@

388@: with 1394;
389@: without 1394.

IN_TPM@: TPM chip from vendor "INFINEON";
WB_TPM@: TPM chip from vendor "Nuvoton"
With TPM SKUs: mount "TPM@ and IN_TPM@ " or "TPM@ and WB_TPM@".

If has Vpro@, no 8111E@, Rev02@,Rev03@, Rev04@ and Rev10@.

X76 AND VGA configu table

SKU Description Config

Board ID Table

Board ID Rb V min Vtyp Vmax PCB Revision

0

1

2

3

4

5

6

7

4619IE30L11

1
2
3

4619IE30L21
4
5

Ra VCC

0

8.2K +/- 5%

18K +/- 5%

33K +/- 5%

56K +/- 5%

100K +/- 5%

200K +/- 5%

NC

100K +/- 5% 3.3V +/- 5%

100K +/- 5%

100K +/- 5%

100K +/- 5%

100K +/- 5%

100K +/- 5%

100K +/- 5%

100K +/- 5%

ZZZ
SAM 1G

ZZZ
SAM 2G

SAM1G@

SAM2G@

3.3V +/- 5%

3.3V +/- 5%

3.3V +/- 5%

3.3V +/- 5%

3.3V +/- 5%

3.3V +/- 5%

3.3V +/- 5%

ZZZ

HY1G@

Hynix 1G

ZZZ

HY2G@

Hynix 2G

0V

0.216 V0V0.250 V

0.503 V

0.436 V

0.819 V

0.712 V

1.185 V

1.036 V

1.650 V

1.453 V

2.200 V

1.935 V

3.300 V

2.500 V

0V

0.289 V

0.538 V

0.875 V

1.264 V

1.759 V

2.341 V

3.300 V

4619IE30L01

4619IE30L11

4619IE30L21

QAQ11 DIS N13P-GLP

QAQ13 DIS N13P-GLP

0.1

0.2

0.3

0.4

1.0

VPRO

D

C

B

PCH And PCBA table

UPCH1
BD82HM76 SLJ8E C1 BGA 989P PCH 030!

PCH

8111E@

PCB

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/09/23 2011/12/30

2011/09/23 2011/12/30

2011/09/23 2011/12/30

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

UPCH1
BD82QM77 QPRE C1 BGA 989P PCH

VPRO@

ZZZ

DA8@

PCB LA-8581P REV1 M/B

2

ZZZ

DAZ@

PCB QAQ10

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

4019IE

4019IE

4019IE

4 60Friday, August 24, 2012

4 60Friday, August 24, 2012

4 60Friday, August 24, 2012

1

of

of

of

A

B

B

B

VSS

1

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

VSS241

VSS242

VSS243

VSS244

VSS245

VSS246

VSS247

VSS248

VSS249

VSS250

VSS251

VSS252

VSS253

VSS254

VSS255

VSS256

VSS257

VSS258

VSS259

VSS260

VSS261

VSS262

VSS263

VSS264

VSS265

VSS266

VSS267

VSS268

VSS269

VSS270

VSS271

VSS272

VSS273

VSS274

VSS275

VSS276

VSS277

VSS278

VSS279

VSS280

VSS281

VSS282

VSS283

VSS284

VSS285

D

E15

E13

E10

E9

E8

E7

E6

E5

E4

E3

E2

E1

D35

D32

D29

D26

D20

D17

C34

C31

C28

C27

C25

C23

C10

C1

B22

B19

B17

B15

B13

B11

C

B9

B8

B7

B5

B3

B2

A35

A32

A29

A26

A23

A20

A3

B

5

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

JCPU1A

D

C

+1.05VS_VCCP

+1.05VS_VCCP

B

DMI_CRX_PTX_N0<27>

DMI_CRX_PTX_N1<27>

DMI_CRX_PTX_N2<27>

DMI_CRX_PTX_N3<27>

DMI_CRX_PTX_P0<27>

DMI_CRX_PTX_P1<27>

DMI_CRX_PTX_P2<27>

DMI_CRX_PTX_P3<27>

DMI_CTX_PRX_N0<27>

DMI_CTX_PRX_N1<27>

DMI_CTX_PRX_N2<27>

DMI_CTX_PRX_N3<27>

DMI_CTX_PRX_P0<27>

DMI_CTX_PRX_P1<27>

DMI_CTX_PRX_P2<27>

DMI_CTX_PRX_P3<27>

FDI_CTX_PRX_N0<27>

FDI_CTX_PRX_N1<27>

FDI_CTX_PRX_N2<27>

FDI_CTX_PRX_N3<27>

FDI_CTX_PRX_N4<27>

FDI_CTX_PRX_N5<27>

FDI_CTX_PRX_N6<27>

FDI_CTX_PRX_N7<27>

FDI_CTX_PRX_P0<27 >

FDI_CTX_PRX_P1<27 >

FDI_CTX_PRX_P2<27 >

FDI_CTX_PRX_P3<27 >

FDI_CTX_PRX_P4<27 >

FDI_CTX_PRX_P5<27 >

FDI_CTX_PRX_P6<27 >

FDI_CTX_PRX_P7<27 >

FDI_FSYNC0<27>

FDI_FSYNC1<27>

FDI_INT<27>

FDI_LSYNC0<27>

FDI_LSYNC1<27>

RC4 24.9_0402_1%

2

1

2

1

10K_0402_5%
R88

@

FDI_CTX_PRX_N0

FDI_CTX_PRX_N1

FDI_CTX_PRX_N2

FDI_CTX_PRX_N3

FDI_CTX_PRX_N4

FDI_CTX_PRX_N5

FDI_CTX_PRX_N6

FDI_CTX_PRX_N7

FDI_CTX_PRX_P0

FDI_CTX_PRX_P1

FDI_CTX_PRX_P2

FDI_CTX_PRX_P3

FDI_CTX_PRX_P4

FDI_CTX_PRX_P5

FDI_CTX_PRX_P6

FDI_CTX_PRX_P7

FDI_FSYNC0

FDI_FSYNC1

FDI_INT

FDI_LSYNC0

FDI_LSYNC1

EDP_COMP

EDP_HPD#

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

CONN@

4

J22

PEG_ICOMPI

J21

PEG_ICOMPO

H22

PEG_RCOMPO

K33

PEG_RX#[0]

M35

PEG_RX#[1]

L34

PEG_RX#[2]

J35

PEG_RX#[3]

J32

PEG_RX#[4]

H34

PEG_RX#[5]

H31

PEG_RX#[6]

G33

PEG_RX#[7]

PCI EXPRESS* - GRAPHICS

PEG_RX#[8]

PEG_RX#[9]

PEG_RX#[10]

PEG_RX#[11]

PEG_RX#[12]

PEG_RX#[13]

PEG_RX#[14]

PEG_RX#[15]

PEG_RX[0]

PEG_RX[1]

PEG_RX[2]

PEG_RX[3]

PEG_RX[4]

PEG_RX[5]

PEG_RX[6]

PEG_RX[7]

PEG_RX[8]

PEG_RX[9]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]

PEG_TX#[10]

PEG_TX#[11]

PEG_TX#[12]

PEG_TX#[13]

PEG_TX#[14]

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

G30

F35

E34

E32

D33

D31

B33

C32

J33

L35

K34

H35

H32

G34

G31

F33

F30

E35

E33

F32

D34

E31

C33

B32

M29

M32

M31

L32

L29

K31

K28

J30

J28

H29

G27

E29

F27

D28

F26

E25

M28

M33

M30

L31

L28

K30

K27

J29

J27

H28

G28

E28

F28

D27

E26

D25

DMI

Intel(R) FDI

eDP

24.9_0402_1%

PEG_COMP

PCIE_GTX_C_CRX_N0

PCIE_GTX_C_CRX_N1

PCIE_GTX_C_CRX_N2

PCIE_GTX_C_CRX_N3

PCIE_GTX_C_CRX_N4

PCIE_GTX_C_CRX_N5

PCIE_GTX_C_CRX_N6

PCIE_GTX_C_CRX_N7

PCIE_GTX_C_CRX_N8

PCIE_GTX_C_CRX_N9

PCIE_GTX_C_CRX_N10

PCIE_GTX_C_CRX_N11

PCIE_GTX_C_CRX_N12

PCIE_GTX_C_CRX_N13

PCIE_GTX_C_CRX_N14

PCIE_GTX_C_CRX_N15

PCIE_GTX_C_CRX_P0

PCIE_GTX_C_CRX_P1

PCIE_GTX_C_CRX_P2

PCIE_GTX_C_CRX_P3

PCIE_GTX_C_CRX_P4

PCIE_GTX_C_CRX_P5

PCIE_GTX_C_CRX_P6

PCIE_GTX_C_CRX_P7

PCIE_GTX_C_CRX_P8

PCIE_GTX_C_CRX_P9

PCIE_GTX_C_CRX_P10

PCIE_GTX_C_CRX_P11

PCIE_GTX_C_CRX_P12

PCIE_GTX_C_CRX_P13

PCIE_GTX_C_CRX_P14

PCIE_GTX_C_CRX_P15

PCIE_CTX_GRX_N0

PCIE_CTX_GRX_N1

PCIE_CTX_GRX_N2

PCIE_CTX_GRX_N3

PCIE_CTX_GRX_N4

PCIE_CTX_GRX_N5

PCIE_CTX_GRX_N6

PCIE_CTX_GRX_N7

PCIE_CTX_GRX_N8

PCIE_CTX_GRX_N9

PCIE_CTX_GRX_N10

PCIE_CTX_GRX_N11

PCIE_CTX_GRX_N12

PCIE_CTX_GRX_N13

PCIE_CTX_GRX_N14

PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0

PCIE_CTX_GRX_P1

PCIE_CTX_GRX_P2

PCIE_CTX_GRX_P3

PCIE_CTX_GRX_P4

PCIE_CTX_GRX_P5

PCIE_CTX_GRX_P6

PCIE_CTX_GRX_P7

PCIE_CTX_GRX_P8

PCIE_CTX_GRX_P9

PCIE_CTX_GRX_P10

PCIE_CTX_GRX_P11

PCIE_CTX_GRX_P12

PCIE_CTX_GRX_P13

PCIE_CTX_GRX_P14

PCIE_CTX_GRX_P15

3

+1.05VS_VCCP

1

RC2

2

PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

PCIE_GTX_C_CRX_N[0..15] <13>

PEG signals swapped at VGA side.

PCIE_GTX_C_CRX_P[0..15] <13>

2

1

C222 0.1U_0402_16V7KOPT@

2

1

C136 0.1 U_0402_16V7KOPT@

2

1

C60 0.1U_0402_16V7 KOPT@

2

1

C75 0.1U_0402_16V7 KOPT@

2

1

C67 0.1U_0402_16V7KOPT@

2

1

C220 0.1U_0402_16V7KOPT@

2

1

C118 0.1U_ 0402_16V7KOPT@

2

1

C62 0.1U_0402_16 V7KOPT@

2

1

C59 0.1U_0402_16V7KOPT@

2

1

C115 0.1U_0402_16V7 KOPT@

2

1

C70 0.1U_0402_16V7KOPT@

2

1

C197 0.1U_0402_16V7KOPT@

2

1

C61 0.1U_0402_16 V7KOPT@

2

1

C223 0.1U_0 402_16V7KOPT@

2

1

C88 0.1U_0402_16 V7KOPT@

2

1

C68 0.1U_0402_16V7KOPT@

2

1

C209 0.1U_0402_16V7KOPT@

2

1

C66 0.1U_0402_16 V7KOPT@

2

1

C224 0.1U_0 402_16V7KOPT@

2

1

C89 0.1U_0402_16 V7KOPT@

2

1

C69 0.1U_0402_16V7KOPT@

2

1

C221 0.1U_0402_16V7 KOPT@

2

1

C135 0 .1U_0402_16V7KOPT@

2

1

C71 0.1U_0402_16 V7KOPT@

2

1

C74 0.1U_0402_16 V7KOPT@

2

1

C72 0.1U_0402_16V7KOPT@

2

1

C214 0.1U_0402_16V7KOPT@

2

1

C117 0.1 U_0402_16V7KOPT@

2

1

C78 0.1U_0402_16V7KOPT@

2

1

C87 0.1U_0402_16V7 KOPT@

2

1

C79 0.1U_0402_16V7KOPT@

2

1

C111 0.1U_0 402_16V7KOPT@

PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_N7

PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_N9

PCIE_CTX_C_GRX_N10

PCIE_CTX_C_GRX_N11

PCIE_CTX_C_GRX_N12

PCIE_CTX_C_GRX_N13

PCIE_CTX_C_GRX_N14

PCIE_CTX_C_GRX_N15

PCIE_CTX_C_GRX_P0

PCIE_CTX_C_GRX_P1

PCIE_CTX_C_GRX_P2

PCIE_CTX_C_GRX_P3

PCIE_CTX_C_GRX_P4

PCIE_CTX_C_GRX_P5

PCIE_CTX_C_GRX_P6

PCIE_CTX_C_GRX_P7

PCIE_CTX_C_GRX_P8

PCIE_CTX_C_GRX_P9

PCIE_CTX_C_GRX_P10

PCIE_CTX_C_GRX_P11

PCIE_CTX_C_GRX_P12

PCIE_CTX_C_GRX_P13

PCIE_CTX_C_GRX_P14

PCIE_CTX_C_GRX_P15

2

PCIE_CTX_C_GRX_N[0..15] <13>

PCIE_CTX_C_GRX_P[0..15] <13>

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

TYCO_2013620-2_IVY BRIDGE

CONN@

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sheet

Date: Sheet

2

Date: Sheet

5 60Friday, August 24, 2012

5 60Friday, August 24, 2012

5 60Friday, August 24, 2012

1

A

B

B

B

of

of

of

4

1

0_0402_5%

1

0.1U_0402_16V4Z

C85

+1.5V_CPU_VDDQ

R81
200_0402_1%

VDDPWRGOOD

R110
39_0402_1%

@

2

@

1

D

@

2

Q5
2N7002_SOT23-3

G

2

@

S

3

D

5

4

3

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

D

2

SYSTEM_PWROK<27>

1

R104

0_0402_5%

short@

2

RC21 0_0 402_5%

short@

RUN_ON_CPU1.5VS3#<10,45>

+3VS

D_PWG

+3VALW

R289

200_0402_1%

PM_DRAM_PWRGD<27>

RC13

@

10K_0402_5%

SUSP<11,40,43,45>

+3VALW

5

1

P

B

2

A

G

3

RC17

RC16

U5
74AHC1G08DCKR_SC70-5

O

1

0_0402_5%

C

Processor Pullups

H_PROCHOT#

B

A

1

R47
62_0402_5%

CC62

@

220P_0402_25V8J

H_CPUPWRGD_R

5

+1.05VS_VCCP

2

H_PROCHOT#<41,47>

H_THERMTRIP#<29>

PROC_SELECT#:
Sandy Bridge---output high;
Ivy Bridge---output low.

T0501

H_PECI<29,41>

H_PROCHOT#

H_PM_SYNC<27>

H_CPUPWRGD<29>

VDDPWRGOOD

220P_0402_25V8J

H_SNB_IVB#<29>

H_CATERR#

2

1

RC44
43_0402_1%

H_PECI_R

R58

2

1

H_PROCHOT#_R

56_0402_5%

Place R58 close to CPU.

2

1

H_THERMTRIP#_R

R14 0_0402_5%

short@

R15

2

1

H_PM_SYNC_R

0_0402_5%

short@

R16

2

1

H_CPUPWRGD_R

0_0402_5%

short@

R79

2

1

130_0402_1%

VDDPWRGOOD_R

BUF_CPU_RST#

R5010K_0402_5%

C379

@

JCPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

TYCO_2013620-2_IVY BRIDGE

CONN@

4

BCLK

BCLK#

MISCTHERMALPWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]

SM_RCOMP[1]

SM_RCOMP[2]

DDR3

MISC

PRDY#

PREQ#

TCK

TMS

TRST#

TDI

TDO

DBR#

BPM#[0]

BPM#[1]

BPM#[2]

JTAG & BPM

BPM#[3]

BPM#[4]

BPM#[5]

BPM#[6]

BPM#[7]

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

A28

A27

A16

A15

R8

AK1

A5

A4

AP29

AP27

AR26

AR27

AP30

AR28

AP26

AL35

AT28

AR29

AR30

AT30

AP32

AR31

AT31

AR32

XDP_DBRESET#

CLK_CPU_DMI_R

CLK_CPU_DMI#_R

CLK_CPU_DPLL_R

CLK_CPU_DPLL#_R

H_DRAMRST#

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

XDP_PRDY#_R

XDP_PREQ#_R

XDP_TCK_R

XDP_TMS_R

XDP_TRST#_R

XDP_TDI_R

XDP_TDO_R

short@

2

1

R138 0_040 2_5%

2

1

R139 0_040 2_5%

short@

2

1

R126 1K_04 02_5%

2

1

R115 1K_040 2_5%

H_DRAMRST# <7>

Compal Secret Data

Compal Secret Data

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

Compal Secret Data

PLT_RST#<28,34,35,36,37,39,41,42,44>

CLK_CPU_DMI <26>

CLK_CPU_DMI# <26>

+1.05VS_VCCP

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

EN_DFAN1<41>

Deciphered Date

Deciphered Date

Deciphered Date

+FAN1

10mil

+5VS

2

1

1

1

1A

1

C1
10U_0805_10V4Z

2

2

2

2

U58

1

EN

2

VIN

3

VOUT

4

VSET

G996P11U SOP 8P

+3VS

5

U3

1

P

NC

Y

2

A

G

3

+1.05VS_VCCP

0.1U_0402_16V4Z

C84

4

BUFO_CPU_RST#

SN74LVC1G07DCKR_SC70-5

PU/PD for JTAG signals

XDP_TMS_R

XDP_TDI_R

XDP_PREQ#_R

RC42140_0402_1%

RC4325.5_0402_1%

RC45200_0402_1%

XDP_TDO_R

XDP_TCK_R

XDP_TRST#_R

FAN Control Circuit

2

C863

10U_0805_10V4Z

8

GND

7

GND

6

GND

5

GND

+FAN1

1

2

C864

@

1000P_0402_50V7K

1

Compal Electronics, Inc.

Title

Title

Title

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sheet

Date: Sheet

Date: Sheet

1

R64
75_0402_5%

2

R72

43_0402_1%

1

C865

0.01U_0402_25V7K

2

1

BUF_CPU_RST#

+1.05VS_VCCP

RC4651_0402_5%

RC4751_0402_5%

RC4851_0402_5% @

RC4951_0402_5%

RC5751_0402_5%

RC5551_0402_5%

JFAN

1

1

2

2

3

3

4

GND

5

GND

ACES_85205-03001

CONN@

R3 1 0K_0402_5%

2

@

1

@

R73
0_0402_5%

2

1

+3VS

FAN_SPEED <41>

6 60Friday, August 24, 2012

of

6 60Friday, August 24, 2012

of

6 60Friday, August 24, 2012

of

C

B

A

B

B

B

5

4

3

2

1

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

DDR_A_D[0..63]<11>

D

C

DDR_A_BS0<11>

DDR_A_BS1<11>

DDR_A_BS2<11>

B

DDR_A_CAS#<11>

DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D0

DDR_A_D1

DDR_A_D2

DDR_A_D3

DDR_A_D4

DDR_A_D5

DDR_A_D6

DDR_A_D7

DDR_A_D8

DDR_A_D9

DDR_A_D10

DDR_A_D11

DDR_A_D12

DDR_A_D13

DDR_A_D14

DDR_A_D15

DDR_A_D16

DDR_A_D17

DDR_A_D18

DDR_A_D19

DDR_A_D20

DDR_A_D21

DDR_A_D22

DDR_A_D23

DDR_A_D24

DDR_A_D25

DDR_A_D26

DDR_A_D27

DDR_A_D28

DDR_A_D29

DDR_A_D30

DDR_A_D31

DDR_A_D32

DDR_A_D33

DDR_A_D34

DDR_A_D35

DDR_A_D36

DDR_A_D37

DDR_A_D38

DDR_A_D39

DDR_A_D40

DDR_A_D41

DDR_A_D42

DDR_A_D43

DDR_A_D44

DDR_A_D45

DDR_A_D46

DDR_A_D47

DDR_A_D48

DDR_A_D49

DDR_A_D50

DDR_A_D51

DDR_A_D52

DDR_A_D53

DDR_A_D54

DDR_A_D55

DDR_A_D56

DDR_A_D57

DDR_A_D58

DDR_A_D59

DDR_A_D60

DDR_A_D61

DDR_A_D62

DDR_A_D63

JCPU1C

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]

G10

SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]

M10

SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]

AG6

SA_DQ[32]

AG5

SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]

AH5

SA_DQ[36]

AH6

SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]

AH8

SA_DQ[44]

AH9

SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]

AP11

SA_DQ[48]

AN11

SA_DQ[49]

AL12

SA_DQ[50]

AM12

SA_DQ[51]

AM11

SA_DQ[52]

AL11

SA_DQ[53]

AP12

SA_DQ[54]

AN12

SA_DQ[55]

AJ14

SA_DQ[56]

AH14

SA_DQ[57]

AL15

SA_DQ[58]

AK15

SA_DQ[59]

AL14

SA_DQ[60]

AK14

SA_DQ[61]

AJ15

SA_DQ[62]

AH15

SA_DQ[63]

AE10

SA_BS[0]

AF10

SA_BS[1]

V6

SA_BS[2]

AE8

SA_CAS#

AD9

SA_RAS#

AF9

SA_WE#

TYCO_2013620-2_IVY BRIDGE

CONN@

AB6

SA_CLK[0]

AA6

SA_CLK#[0]

V9

SA_CKE[0]

AA5

SA_CLK[1]

AB5

SA_CLK#[1]

V10

SA_CKE[1]

AB4

RSVD_TP[1]

AA4

RSVD_TP[2]

W9

RSVD_TP[3]

AB3

RSVD_TP[4]

AA3

RSVD_TP[5]

W10

RSVD_TP[6]

AK3

SA_CS#[0]

AL3

AG1

SA_CS#[1]

RSVD_TP[7]

AH1

RSVD_TP[8]

AH3

SA_ODT[0]

AG3

AG2

SA_ODT[1]

RSVD_TP[9]

AH2

RSVD_TP[10]

C4

SA_DQS#[0]

G6

SA_DQS#[1]

J3

SA_DQS#[2]

DDR_A_DQS#0

M6

SA_DQS#[3]

DDR_A_DQS#1

AL6

SA_DQS#[4]

DDR_A_DQS#2

AM8

SA_DQS#[5]

DDR_A_DQS#3

AR12

SA_DQS#[6]

DDR_A_DQS#4

AM15

SA_DQS#[7]

DDR_A_DQS#5

DDR_A_DQS#6

DDR_A_DQS#7

D4

SA_DQS[0]

F6

SA_DQS[1]

K3

SA_DQS[2]

DDR_A_DQS0

N6

SA_DQS[3]

DDR_A_DQS1

AL5

SA_DQS[4]

DDR_A_DQS2

AM9

SA_DQS[5]

DDR_A_DQS3

AR11

SA_DQS[6]

DDR_A_DQS4

AM14

SA_DQS[7]

DDR_A_DQS5

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10]

SA_MA[11]

SA_MA[12]

SA_MA[13]

SA_MA[14]

SA_MA[15]

AD10

W1

W2

W7

V3

V2

W3

W6

V1

W5

AD8

V4

W4

AF8

V5

V7

DDR_A_DQS6

DDR_A_DQS7

DDR_A_MA0

DDR_A_MA1

DDR_A_MA2

DDR_A_MA3

DDR_A_MA4

DDR_A_MA5

DDR_A_MA6

DDR_A_MA7

DDR_A_MA8

DDR_A_MA9

DDR_A_MA10

DDR_A_MA11

DDR_A_MA12

DDR_A_MA13

DDR_A_MA14

DDR_A_MA15

DDR SYSTEM MEMORY A

DDRA_CLK0 <11>

DDRA_CLK0# <11>

DDRA_CKE0 <11>

DDRA_CLK1 <11>

DDRA_CLK1# <11>

DDRA_CKE1 <11>

DDRA_SCS0# <11>

DDRA_SCS1# <11>

DDRA_ODT0 <11>

DDRA_ODT1 <11>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR_B_D[0..63]<12>

DDR_B_BS0<12>

DDR_B_BS1<12>

DDR_B_BS2<12>

DDR_B_CAS#<12>

DDR_B_RAS#<12>

DDR_B_WE#<12>

DDR_B_D0

DDR_B_D1

DDR_B_D2

DDR_B_D3

DDR_B_D4

DDR_B_D5

DDR_B_D6

DDR_B_D7

DDR_B_D8

DDR_B_D9

DDR_B_D10

DDR_B_D11

DDR_B_D12

DDR_B_D13

DDR_B_D14

DDR_B_D15

DDR_B_D16

DDR_B_D17

DDR_B_D18

DDR_B_D19

DDR_B_D20

DDR_B_D21

DDR_B_D22

DDR_B_D23

DDR_B_D24

DDR_B_D25

DDR_B_D26

DDR_B_D27

DDR_B_D28

DDR_B_D29

DDR_B_D30

DDR_B_D31

DDR_B_D32

DDR_B_D33

DDR_B_D34

DDR_B_D35

DDR_B_D36

DDR_B_D37

DDR_B_D38

DDR_B_D39

DDR_B_D40

DDR_B_D41

DDR_B_D42

DDR_B_D43

DDR_B_D44

DDR_B_D45

DDR_B_D46

DDR_B_D47

DDR_B_D48

DDR_B_D49

DDR_B_D50

DDR_B_D51

DDR_B_D52

DDR_B_D53

DDR_B_D54

DDR_B_D55

DDR_B_D56

DDR_B_D57

DDR_B_D58

DDR_B_D59

DDR_B_D60

DDR_B_D61

DDR_B_D62

DDR_B_D63

JCPU1D

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

TYCO_2013620-2_IVY BRIDGE

CONN@

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

R9

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

AB2

RSVD_TP[11]

AA2

RSVD_TP[12]

T9

RSVD_TP[13]

AA1

RSVD_TP[14]

AB1

RSVD_TP[15]

T10

RSVD_TP[16]

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6

RSVD_TP[17]

AE6

RSVD_TP[18]

AE4

SB_ODT[0]

AD4

AD5

SB_ODT[1]

RSVD_TP[19]

AE5

RSVD_TP[20]

D7

SB_DQS#[0]

F3

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10]

SB_MA[11]

SB_MA[12]

SB_MA[13]

SB_MA[14]

SB_MA[15]

K6

N3

AN5

AP9

AK12

AP15

C7

G3

J6

M3

AN6

AP8

AK11

AP14

AA8

T7

R7

T6

T2

T4

T3

R2

T5

R3

AB7

R1

T1

AB10

R5

R4

DDR_B_DQS#0

DDR_B_DQS#1

DDR_B_DQS#2

DDR_B_DQS#3

DDR_B_DQS#4

DDR_B_DQS#5

DDR_B_DQS#6

DDR_B_DQS#7

DDR_B_DQS0

DDR_B_DQS1

DDR_B_DQS2

DDR_B_DQS3

DDR_B_DQS4

DDR_B_DQS5

DDR_B_DQS6

DDR_B_DQS7

DDR_B_MA0

DDR_B_MA1

DDR_B_MA2

DDR_B_MA3

DDR_B_MA4

DDR_B_MA5

DDR_B_MA6

DDR_B_MA7

DDR_B_MA8

DDR_B_MA9

DDR_B_MA10

DDR_B_MA11

DDR_B_MA12

DDR_B_MA13

DDR_B_MA14

DDR_B_MA15

SB_DQS#[1]

SB_DQS#[2]

SB_DQS#[3]

SB_DQS#[4]

SB_DQS#[5]

SB_DQS#[6]

SB_DQS#[7]

DDR SYSTEM MEMORY B

DDRB_CLK0 <12>

DDRB_CLK0# <12>

DDRB_CKE0 <12>

DDRB_CLK1 <12>

DDRB_CLK1# <12>

DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDRB_SCS1# <12>

DDRB_ODT0 <12>

DDRB_ODT1 <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

D

C

B

+1.5V

@

R124 0_0402_5%

QC3

BSS138_SOT23

D

S

3

H_DRAMRST#<6>

A

H_DRAMRST#

4.99K_0402_1%

5

R119

1

G

2

C86

0.047U_0402_16V4Z

DDR3_DRAMRST#_R

DRAMRST_CNTRL

R123
1K_0402_5%

R129 1K_0402_5%

short@

R118 0_0402_5%

4

SM_DRAMRST# <11,12>

DRAMRST_CNTRL_PCH <10,26>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

Compal Electronics, Inc.

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sh eet

Date: Sh eet

Date: She et

7 60Friday, August 24, 2012

of

7 60Friday, August 24, 2012

of

7 60Friday, August 24, 2012

1

of

A

B

B

B

5

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

D

CFG[1:0]: reserved configuration lane.

CFG[3]: reserved

CFG[17:7]: reserved configuration lanes.

CFG[17:0]:
Processor internal pull up 5~15Kohm to VCCIO

C

B

T266 PAD

T251 PAD

T252 PAD

T253 PAD

T254 PAD

T255 PAD

T256 PAD

T257 PAD

T258 PAD

T259 PAD

T260 PAD

T261 PAD

T267 PAD

T268 PAD

T269 PAD

T270 PAD

T262 PAD

T263 PAD

T245 PAD

T246 PAD

T247 PAD

T248 PAD

CFG0

CFG1

CFG2

CFG3

CFG4

CFG5

CFG6

CFG7

CFG8

CFG9

CFG10

CFG11

CFG12

CFG13

CFG14

CFG15

CFG16

CFG17

4

JCPU1E

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

CONN@

CFG

RESERVED

VCC_DIE_SENSE

VSS_DIE_SENSE

RSVD28

RSVD29

RSVD30

RSVD31

RSVD32

RSVD33

RSVD34

RSVD35

RSVD37

RSVD38

RSVD39

RSVD40

RSVD_NCTF1

RSVD_NCTF2

RSVD_NCTF3

RSVD_NCTF4

RSVD_NCTF5

RSVD_NCTF6

RSVD_NCTF7

RSVD_NCTF8

RSVD_NCTF9

RSVD_NCTF10

RSVD51

RSVD52

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11

RSVD_NCTF12

RSVD_NCTF13

3

2

1

CFG Straps for Processor

CFG2

AH27

AH26

L7

AG7

AE7

AK2

W8

AT26

AM33

AJ27

T8

J16

H16

G16

AR35

AT34

AT33

AP35

AR34

B34

A33

A34

B35

C35

AJ32

AK32

AN35

AM35

AT2

AT1

AR1

B1

KEY

CLK_RES_ITP <26>

CLK_RES_ITP# <26>

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition
0:Lane Reversed

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2

CFG[6:5]

disabled
01: Reserved - (Device 1 function 1 disabled ; function

2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG4

CFG6

CFG5

1K_0402_1%

CFG7

RC51
1K_0402_1%

RC52

@

1K_0402_1%

RC54

@

RC53

@

1K_0402_1%

RC56

@

1K_0402_1%

D

C

B

PEG DEFER TRAINING

1: (Default) PEG Train immediately

CFG7

following RESETB de assertion

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

0: PEG Wait for BIOS for training

2

Compal Electronics, Inc.

Title

Title

Title

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sheet

Date: Sheet

Date: Sheet

8 60Friday, August 24, 201 2

8 60Friday, August 24, 201 2

8 60Friday, August 24, 201 2

1

A

B

B

B

of

of

of

5

4

3

2

1

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

D

C

B

A

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

TYCO_2013620-2_IVY BRIDGE

CONN@

VSS

VSS81

VSS82

VSS83

VSS84

VSS85

VSS86

VSS87

VSS88

VSS89

VSS90

VSS91

VSS92

VSS93

VSS94

VSS95

VSS96

VSS98

VSS99

VSS100

VSS101

VSS102

VSS103

VSS104

VSS105

VSS106

VSS107

VSS108

VSS109

VSS110

VSS111

VSS112

VSS113

VSS114

VSS115

VSS116

VSS117

VSS118

VSS119

VSS120

VSS121

VSS122

VSS123

VSS124

VSS125

VSS126

VSS127

VSS128

VSS129

VSS130

VSS131

VSS132

VSS133

VSS134

VSS135

VSS136

VSS137

VSS138

VSS139

VSS140

VSS141

VSS142

VSS143

VSS144

VSS145

VSS146

VSS147

VSS148

VSS149

VSS150

VSS151

VSS152

VSS153

VSS154

VSS155

VSS156

VSS157

VSS158

VSS159

VSS160

AJ22

AJ19

AJ16

AJ13

AJ10

AJ7

AJ4

AJ3

AJ2

AJ1

AH35

AH34

AH32

AH30

AH29

AH28

AH25

AH22

AH19

AH16

AH7

AH4

AG9

AG8

AG4

AF6

AF5

AF3

AF2

AE35

AE34

AE33

AE32

AE31

AE30

AE29

AE28

AE27

AE26

AE9

AD7

AC9

AC8

AC6

AC5

AC3

AC2

AB35

AB34

AB33

AB32

AB31

AB30

AB29

AB28

AB27

AB26

Y9

Y8

Y6

Y5

Y3

Y2

W35

W34

W33

W32

W31

W30

W29

W28

W27

W26

U9

U8

U6

U5

U3

U2

+VCC_CORE

97A

AG35

AG34

AG33

AG32

AG31

AG30

AG29

AG28

AG27

AG26

AF35

AF34

AF33

AF32

AF31

AF30

AF29

AF28

AF27

AF26

AD35

AD34

AD33

AD32

AD31

AD30

AD29

AD28

AD27

AD26

AC35

AC34

AC33

AC32

AC31

AC30

AC29

AC28

AC27

AC26

AA35

AA34

AA33

AA32

AA31

AA30

AA29

AA28

AA27

AA26

Y35

Y34

Y33

Y32

Y31

Y30

Y29

Y28

Y27

Y26

V35

V34

V33

V32

V31

V30

V29

V28

V27

V26

U35

U34

U33

U32

U31

U30

U29

U28

U27

U26

R35

R34

R33

R32

R31

R30

R29

R28

R27

R26

P35

P34

P33

P32

P31

P30

P29

P28

P27

P26

POWER

JCPU1F

VCC1

VCC2

VCC3

VCC4

VCC5

VCC6

VCC7

VCC8

VCC9

VCC10

VCC11

VCC12

VCC13

VCC14

VCC15

VCC16

VCC17

VCC18

VCC19

VCC20

VCC21

VCC22

VCC23

VCC24

VCC25

VCC26

VCC27

VCC28

VCC29

VCC30

VCC31

VCC32

VCC33

VCC34

VCC35

VCC36

VCC37

VCC38

VCC39

VCC40

VCC41

VCC42

VCC43

VCC44

VCC45

VCC46

VCC47

VCC48

VCC49

VCC50

VCC51

VCC52

VCC53

VCC54

VCC55

VCC56

VCC57

VCC58

VCC59

VCC60

VCC61

VCC62

VCC63

VCC64

VCC65

VCC66

VCC67

VCC68

VCC69

VCC70

VCC71

VCC72

VCC73

VCC74

VCC75

VCC76

VCC77

VCC78

VCC79

VCC80

VCC81

VCC82

VCC83

VCC84

VCC85

VCC86

VCC87

VCC88

VCC89

VCC90

VCC91

VCC92

VCC93

VCC94

VCC95

VCC96

VCC97

VCC98

VCC99

VCC100

TYCO_2013620-2_IVY BRIDGE

CONN@

PEG AND DDR

VIDALERT#

VIDSCLK

CORE SUPPLY

VIDSOUT

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO8

VCCIO9

VCCIO10

VCCIO11

VCCIO12

VCCIO13

VCCIO14

VCCIO15

VCCIO16

VCCIO17

VCCIO18

VCCIO19

VCCIO20

VCCIO21

VCCIO22

VCCIO23

VCCIO24

VCCIO25

VCCIO26

VCCIO27

VCCIO28

VCCIO29

VCCIO30

VCCIO31

VCCIO32

VCCIO33

VCCIO34

VCCIO35

VCCIO36

VCCIO37

VCCIO38

VCCIO39

VCCIO40

AH13

8.5A

AH10

AG10

AC10

Y10

U10

P10

L10

J14

J13

J12

J11

H14

H12

H11

G14

G13

G12

F14

F13

F12

F11

E14

E12

E11

D14

D13

D12

D11

C14

C13

C12

C11

B14

B12

A14

A13

A12

A11

J23

AJ29

AJ30

AJ28

AJ35

AJ34

B10

A10

VCCSENSE_R

VSSSENSE_R

+1.05VS_VCCP

H_CPU_SVIDALRT#

H_CPU_SVIDCLK

H_CPU_SVIDDAT

+1.05VS_VCCP

0.1U_0402_16V4Z

CC49

RC61

43_0402_1%

+1.05VS_VCCP

RC137

130_0402_1%

H_CPU_SVIDDAT

Place the PU resistors
R53, R54 close to CPU

short@

R52 0_0402_5%short@

R51 0_0402_5%

R168

2

1

10_0402_1%

1

R158
10_0402_1%

2

Package Sensing Recommendations--PDDG P30

Sense Trace Impedance Trace Length Match

H_CPU_SVIDCLK

1

RC60
75_0402_5%

2

0.1U_0402_16V4Z

RC65 0_0402_5%

+1.05VS_VCCP

VCCIO_SENSE <51>

CC50

VCC_SENSE /
VSS_SENSE

VCCAXG_SENSE /
VSSAXG_SENSE

VCCIO_SENSE /
VSS_SENSE_VCCIO

VCCSA

RC59 0_0402_5%

Place the PU resistors
RC60, RC137 close to CPU.

short@

short@

+VCC_CORE

1

2

1

R53
100_0402_1%

2

R54
100_0402_1%

25.5-34.5ohm

55ohm

VR_SVID_ALRT# <54>

VCCSENSE <54>

VSSSENSE <54>

VR_SVID_DAT <54>

D

<25 mils

C

VR_SVID_CLK <54>

B

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sheet

Date: Sheet

2

Date: Sheet

1

B

B

B

9 60Friday, August 24, 201 2

of

9 60Friday, August 24, 201 2

of

9 60Friday, August 24, 20 12

of

5

4

3

2

1

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

VAXG_SENSE

VSSAXG_SENSE

SM_VREF

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

VCCSA1

VCCSA2

VCCSA3

VCCSA4

VCCSA5

VCCSA6

VCCSA7

VCCSA8

VCCSA_SENSE

VCCSA_VID[0]

VCCSA_VID[1]

VCCIO_SEL

1

+VSB

2

3

Q208B

5

2N7002DW-T/R7_SOT363-6

4

AK35

AK34

AL1

B4

D1

AF7

AF4

AF1

AC7

AC4

AC1

Y7

Y4

Y1

U7

U4

U1

P7

P4

P1

M27

M26

L26

J26

J25

J24

H26

H25

H23

C22

C24

A19

R135
100K_0402_5%

+V_SM_VREF_CNT

VREFDQ_DIMMA_CPU

VREFDQ_DIMMB_CPU

+1.5V_CPU_VDDQ

6A

+3VALW

1

R134

D

R132

@

+GFX_CORE

1U_0402_6.3V6K

1

2

0_0402_5%

R133

0_0402_5%

AT24

33A

AT23

AT21

AT20

AT18

AT17

AR24

AR23

AR21

AR20

AR18

AR17

AP24

AP23

AP21

AP20

AP18

AP17

AN24

AN23

AN21

AN20

AN18

AN17

AM24

AM23

AM21

AM20

AM18

AM17

AL24

AL23

AL21

AL20

AL18

AL17

AK24

AK23

AK21

AK20

AK18

AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17

AH24

AH23

AH21

AH20

AH18

AH17

1.5A

B6

A6

330U_X_2VM_R6M

A2

1

CC60

CC61

+

2

SUSP#<39,41,45,50,51 ,52,57>

CPU1.5V_S3_GATE<41>

C

B

10U_0805_6.3V6M

CC58

+1.8VS_VCCPLL

1U_0402_6.3V6K

1

CC59

2

+1.8VS

RC120

0_0805_5%

A

100K_0402_5%

2

6

Q208A

2

2N7002DW-T/R7_SOT363-6

1

POWER

JCPU1G

VAXG1

VAXG2

VAXG3

VAXG4

VAXG5

VAXG6

VAXG7

VAXG8

VAXG9

VAXG10

VAXG11

VAXG12

VAXG13

VAXG14

VAXG15

VAXG16

VAXG17

VAXG18

VAXG19

VAXG20

VAXG21

VAXG22

VAXG23

VAXG24

VAXG25

VAXG26

VAXG27

VAXG28

VAXG29

VAXG30

VAXG31

VAXG32

VAXG33

VAXG34

VAXG35

VAXG36

VAXG37

VAXG38

VAXG39

VAXG40

VAXG41

VAXG42

VAXG43

VAXG44

VAXG45

VAXG46

VAXG47

VAXG48

VAXG49

VAXG50

VAXG51

VAXG52

VAXG53

VAXG54

VCCPLL1

VCCPLL2

VCCPLL3

1.8V RAIL

TYCO_2013620-2_IVY BRIDGE

CONN@

RUN_ON_CPU1.5VS3#

SENSE

LINES

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

VREFMISC

GRAPHICS

DDR3 -1.5V RAILS

SA RAIL

+1.5V

RUN_ON_CPU1.5VS3

VCC_AXG_SENSE

VSS_AXG_SENSE

VCC_AXG_SENSE

VSS_AXG_SENSE

10A

H_VCCSA_VID0 <53>

H_VCCSA_VID1 <53>

+1.5V_CPU_VDDQ

Q7

AO4728L_SO8

8

7

6

5

1

R136

2

330K_0402_1%

R89

Close to CPU

100_0402_1%

2

1

R86 1 00_0402_1%

2

1

VCC_AXG_SENSE <54>

VSS_AXG_SENSE <54>

1

CC178

2

10U_0805_6.3V6M

10U_0805_6.3V6M

CC51

CC52

10U_0805_6.3V6M

10U_0805_6.3V6M

CC40

10K_0402_5%

RC113

0_0402_5%

@

+1.5V_CPU_VDDQ

1

2

3

4

C196

0.1U_0603_50V7K

+GFX_CORE

RC76 0_04 02_5%

2

@

QC5

1

AP2302GN-HF_SOT23-3

RUN_ON_CPU1.5VS3

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

CC53

3

10U_0805_6.3V6M

CC54

1

@

@

2

C107

CC38

10U_0805_10V4Z

+V_SM_VREF should
have 20 mil trace width

+V_SM_VREF

10U_0805_6.3V6M

1

+

CC56

CC55

CC57
330U_X_2VM_R6M

2

0.1U_0402_10V6K

+1.5V_CPU_VDDQ

check Confirm QC6, QC7 is low Rdson or not--Joyce 0929

10U_0805_6.3V6M

10U_0603_6.3V6M

@

1

CC43

+

CC44

CC42

CC41

@

0_0402_5%

330U_X_2VM_R6M

2

+VCCSA_SENSE <53>

RC111

VCCSA_VID Configuration --CPU EDS Page99.

VCCSA_VID[0] output default logic state is low for Sandy Bridge processors

+3VS

2

RC112

@

1

+VCCSA

+VCCSA_SENSE

+1.5V_CPU_VDDQ

R131
220_0402_5%

1

D

2

G

Q8

RUN_ON_CPU1.5VS3#

+1.5V_CPU_VDDQ

S

3

2N7002E-T1-GE3_SOT23 -3

C199 0 .1U_0402_10V7K

C201 0 .1U_0402_10V7K

CC47 0.1U_0402_10V7K

CC48 0.1U_0402_10V7K

+1.5V

RUN_ON_CPU1.5VS3# <6,45>

+1.5V_CPU_VDDQ

Intel future processor compatibility design. --DG1.5 P113

RC77 0_0402_5%

@

RC118
1K_0402_1%

RC119
1K_0402_1%

VREFDQ_DIMMA_CPU

VREFDQ_DIMMB_CPU

RC121

@

1K_0402_1%

RC78 0_0402_5%

RC122
1K_0402_1%@

2

@

2

1

3

QC6

1

AP2302GN-HF_SOT23-3

DRAMRST_CNT

3

QC7
AP2302GN-HF_SOT23-3

DRAMRST_CNT

0_0402_5% short@

0_0402_5%

VCCSA: 0.675V (Min) ~ 0.9V (Max)

SA: System Agent
(Memory controller, DMI, PCIE controllers, and display engine)

R92

@

2

1

+VCCSA

100_0402_1%

J3

2

JUMP_43X118@

2

RC79

R120

0_0402_5%

short@

RC80

2

J2

2

JUMP_43X118

@

+V_DDR_REFA

+V_DDR_REFB

short@

1

1

+1.5VS

1

1

+1.5V

+VREF_CA

RC83

@

0_0402_5%

DRAMRST_CNTRL_PCH <7,26>

+VREF_CB

RC84

@

0_0402_5%

D

C

B

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Title

Title

Title

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sheet

Date: Sheet

2

Date: Sheet

10 60Friday, August 24, 2012

10 60Friday, August 24, 2012

10 60Friday, August 24, 2012

1

B

B

B

of

of

of

+V_DDR_REFA

D

C

B

A

5

1

+1.5V

R55

2

1K_0402_1%

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

1

1

1

R57

1

2

2

2

C133

2

1K_0402_1%

C134

CD1

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

DDRA_CKE0<7>

DDR_A_BS2<7>

DDRA_CLK0<7>

DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

1

+3VS

5

1

2

C160

2

C161

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

DDR_A_D0

DDR_A_D1

DDR_A_DM0

DDR_A_D2

DDR_A_D3

DDR_A_D8

DDR_A_D9

DDR_A_DQS#1

DDR_A_DQS1

DDR_A_D10

DDR_A_D11

DDR_A_D16

DDR_A_D17

DDR_A_DQS#2

DDR_A_DQS2

DDR_A_D18

DDR_A_D19

DDR_A_D24

DDR_A_D25

DDR_A_DM3

DDR_A_D26

DDR_A_D27

DDRA_CKE0

DDR_A_BS2

DDR_A_MA12

DDR_A_MA9

DDR_A_MA8

DDR_A_MA5

DDR_A_MA3

DDR_A_MA1

DDRA_CLK0

DDRA_CLK0#

DDR_A_MA10

DDR_A_BS0

DDR_A_WE#

DDR_A_CAS#

DDR_A_MA13

DDRA_SCS1#

DDR_A_D32

DDR_A_D33

DDR_A_DQS#4

DDR_A_DQS4

DDR_A_D34

DDR_A_D35

DDR_A_D40

DDR_A_D41

DDR_A_DM5

DDR_A_D42

DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_DQS#6

DDR_A_DQS6

DDR_A_D50

DDR_A_D51

DDR_A_D56

DDR_A_D57

DDR_A_DM7

DDR_A_D58

DDR_A_D59

1

R67

2

10K_0402_5%

+1.5V

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

DDR3 SO-DIMM A

1

3

5

7

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

201

203

1

205

R68

2

10K_0402_5%

JDDRL

VREF_DQ

VSS2

DQ0

DQ1

9

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1

DQS1

VSS11

DQ10

DQ11

VSS13

DQ16

DQ17

VSS15

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25

VSS22

DM3

VSS23

DQ26

DQ27

VSS25

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

A9

VDD5

A8

A5

VDD7

A3

A1

VDD9

CK0

CK0#

VDD11

A10/AP

BA0

VDD13

WE#

CAS#

VDD15

A13

S1#

VDD17

NCTEST

VSS27

DQ32

DQ33

VSS29

DQS#4

DQS4

VSS32

DQ34

DQ35

VSS34

DQ40

DQ41

VSS36

DM5

VSS37

DQ42

DQ43

VSS39

DQ48

DQ49

VSS41

DQS#6

DQS6

VSS44

DQ50

DQ51

VSS46

DQ56

DQ57

VSS48

DM7

VSS49

DQ58

DQ59

VSS51

SA0

VDDSPD

SA1

VTT1

G1

LCN_DAN06-K4526-0101

CONN@

4

DQS#0

DQS0

VSS10

RESET#

VSS12

VSS14

VSS16

VSS17

VSS19

VSS21

DQS#3

VSS24

VSS26

VDD10

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35

DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47

DQS#7

VSS50

VSS52

EVENT#

4

VSS1

VSS3

VSS6

VSS8

DQ12

DQ13

DQ14

DQ15

DQ20

DQ21

DQ22

DQ23

DQ28

DQ29

DQS3

DQ30

DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

DQ36

DQ37

DQ38

DQ39

DQ44

DQ45

DQS5

DQ46

DQ47

DQ52

DQ53

DQS7

1

10U_0603_6.3V6M

10U_0603_6.3V6M

C146

1

2

0.1U_0402_10V6K
C149

1

2

C361

1U_0402_6.3V6K

1

2

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

4019IE

4019IE

4019IE

10U_0603_6.3V6M

C147

C148

1

1

C153

47P_0402_50V8J

1

2

2

2

0.1U_0402_10V6K
C150

1

2

1U_0402_6.3V6K

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K

1

C151

1

2

2

C362

1U_0402_6.3V6K

C360

1

1

2

2

11 60Friday, August 24, 2012

11 60Friday, August 24, 2012

11 60Friday, August 24, 2012

1

D

10U_0603_6.3V6M

CD15

1

@

2

C152

C

C359

1U_0402_6.3V6K

C369

22U_0805_6.3V6M

1

2

B

A

B

B

B

of

of

of

R5535

SUSP

0.75VR_EN

Q5520A

2

2

Layout Note:

10U_0603_6.3V6M

Place near JDDRL

C143

10U_0603_6.3V6M

+1.5V

+3VALW

5

6

1

1

+

2

2

C140

330U 2V Y D2 LESR9M

R5536
100K_0402_5%

3

Q5520B

2N7002DW-T/R7_SOT363-6

4

10U_0603_6.3V6M

C144

C145

1

1

2

2

refer to QAL51, need confirm. --Joyce 0929/2011

1

Title

Title

Title

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Layout Note: Place these 4 Caps near
Command and Control signals of JDDRL

+1.5V

Layout Note:
Place near JDD RL.203,204

+0.75VS

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

3

+1.5V

2

4

DQ4

6

DQ5

DDR_A_D4

8

DDR_A_D5

10

12

DDR_A_DQS#0

14

16

DDR_A_DQS0

DQ6

18

DQ7

20

DDR_A_D6

DDR_A_D7

22

24

26

DDR_A_D12

DDR_A_D13

28

DM1

30

32

DDR_A_DM1

34

SM_DRAMRST#

36

DDR_A_D14

38

DDR_A_D15

40

42

DDR_A_D20

44

DDR_A_D21

46

DM2

48

50

DDR_A_DM2

52

DDR_A_D22

54

DDR_A_D23

56

58

60

DDR_A_D28

62

DDR_A_D29

64

DDR_A_DQS#3

66

68

DDR_A_DQS3

70

72

DDR_A_D30

DDR_A_D31

74

76

DDRA_CKE1

78

A15

80

A14

82

DDR_A_MA15

DDR_A_MA14

84

A11

86

DDR_A_MA11

A7

88

90

DDR_A_MA7

A6

92

A4

94

DDR_A_MA6

DDR_A_MA4

96

A2

98

DDR_A_MA2

A0

100

102

DDR_A_MA0

CK1

104

DDRA_CLK1

106

DDRA_CLK1#

108

BA1

110

112

DDR_A_BS1

114

DDR_A_RAS#

S0#

116

118

DDRA_SCS0#

DDRA_ODT0

120

122

NC2

DDRA_ODT1

124

126

128

130

132

DDR_A_D36

134

136

DDR_A_D37

DM4

138

140

DDR_A_DM4

142

DDR_A_D38

144

146

DDR_A_D39

148

150

DDR_A_D44

152

DDR_A_D45

154

156

DDR_A_DQS#5

158

DDR_A_DQS5

160

162

DDR_A_D46

DDR_A_D47

164

166

168

DDR_A_D52

DDR_A_D53

170

DM6

172

DDR_A_DM6

174

DQ54

176

DQ55

178

DDR_A_D54

DDR_A_D55

180

DQ60

182

DQ61

184

DDR_A_D60

DDR_A_D61

186

188

190

DDR_A_DQS#7

192

DDR_A_DQS7

DQ62

194

DQ63

DDR_A_D62

196

DDR_A_D63

198

200

SDA

202

SCL

PM_SMBDATA

204

VTT2

PM_SMBCLK

206

G2

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

+0.75VS

SM_DRAMRST# <7,12>

DDRA_CKE1 <7>

DDRA_CLK1 <7>

DDRA_CLK1# <7>

DDR_A_BS1 <7>

DDR_A_RAS# <7 >

DDRA_SCS0# <7 >

DDRA_ODT0 <7>

DDRA_ODT1 <7>

PM_SMBDATA <12,26,36,39>

PM_SMBCLK <12,26,36,39>

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

1

2

C138

0.1U_0402_10V6K

Issued Date

Issued Date

Issued Date

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_DQS#[0..7]<7>

DDR_A_MA[0..15]<7>

+V_DDR_REFA

RC81 0_0402_5%

+VREF_CA

RC82 0_0402_5%

+1.5V

1

R56
1K_0402_1%

2

+VREF_CA

1

1

R60
1K_0402_1%

2

2

C139

2.2U_0603_6.3V4Z

+1.05VSP_PWRGOOD<51,53>

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

3

@

@

Compal Secret Data

Compal Secret Data

Compal Secret Data

+V_DDR_REFB

+VREF_CB

0.75VR_EN#

0.75VR_EN<52>

100K_0402_5%

2N7002DW-T/R7_SOT363-6

SUSP<6,40,43,45>

Deciphered Date

Deciphered Date

Deciphered Date

3

DDR_B_D[0..63]<7>

DDR_B_DQS[0..7]<7>

DDR_B_DQS#[0..7]<7>

DDR_B_MA[0..15]<7>

+1.5V

1

RD12
1K_0402_1%

2

+VREF_CB

1

RD13
1K_0402_1%

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DQS#0

VSS10

VSS12

VSS14

VSS16

VSS17

VSS19

VSS21

DQS#3

VSS24

VSS26

VDD10

VDD12

VDD14

VDD16

VDD18

VSS28

VSS30

VSS31

VSS33

VSS35

DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47

DQS#7

VSS50

VSS52

VSS1

VSS3

DQS0

VSS6

VSS8

DQ12

DQ13

DQ14

DQ15

DQ20

DQ21

DQ22

DQ23

DQ28

DQ29

DQS3

DQ30

DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

DQ36

DQ37

DQ38

DQ39

DQ44

DQ45

DQS5

DQS7

4

+1.5V

2

4

DQ4

6

DDR_B_D4

DQ5

8

DDR_B_D5

10

12

DDR_B_DQS#0

14

DDR_B_DQS0

16

DQ6

18

DQ7

DDR_B_D6

20

DDR_B_D7

22

24

DDR_B_D12

26

DDR_B_D13

28

DM1

30

DDR_B_DM1

32

34

SM_DRAMRST#

36

DDR_B_D14

38

DDR_B_D15

40

42

DDR_B_D20

44

DDR_B_D21

46

DM2

48

DDR_B_DM2

50

52

54

DDR_B_D22

DDR_B_D23

56

58

DDR_B_D28

60

DDR_B_D29

62

64

DDR_B_DQS#3

66

DDR_B_DQS3

68

70

DDR_B_D30

72

DDR_B_D31

74

76

78

DDRB_CKE1

A15

80

A14

82

DDR_B_MA15

DDR_B_MA14

84

A11

86

DDR_B_MA11

A7

88

DDR_B_MA7

90

A6

92

A4

DDR_B_MA6

94

DDR_B_MA4

96

A2

98

DDR_B_MA2

A0

100

102

DDR_B_MA0

CK1

104

DDRB_CLK1

106

DDRB_CLK1#

108

BA1

110

112

DDR_B_BS1

DDR_B_RAS#

114

S0#

116

DDRB_SCS0#

118

DDRB_ODT0

120

122

DDRB_ODT1

NC2

124

126

128

+VREF_CB

130

132

134

DDR_B_D36

DDR_B_D37

136

DM4

138

DDR_B_DM4

140

142

DDR_B_D38

144

146

DDR_B_D39

148

DDR_B_D44

150

DDR_B_D45

152

154

156

DDR_B_DQS#5

DDR_B_DQS5

158

DQ46

160

DQ47

162

DDR_B_D46

DDR_B_D47

164

DQ52

166

DQ53

DDR_B_D52

168

DDR_B_D53

170

DM6

172

174

DDR_B_DM6

DQ54

176

DQ55

DDR_B_D54

178

DDR_B_D55

180

DQ60

182

DQ61

DDR_B_D60

184

DDR_B_D61

186

188

DDR_B_DQS#7

190

192

DDR_B_DQS7

DQ62

194

DQ63

DDR_B_D62

196

198

DDR_B_D63

200

SDA

202

SCL

204

PM_SMBDATA

VTT2

PM_SMBCLK

206

G2

0.65A@0.75V

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

4

SM_DRAMRST# <7,11>

DDRB_CKE1 <7>

DDRB_CLK1 <7>

DDRB_CLK1# <7>

DDR_B_BS1 <7>

DDR_B_RAS# <7 >

DDRB_SCS0# <7 >

DDRB_ODT0 <7>

DDRB_ODT1 <7>

PM_SMBDATA <11,26,36,39>

PM_SMBCLK <11,26,36,39>

+0.75VS

2.2U_0603_6.3V4Z

0.1U_0402_10V6K

1

1

C168

C167

2

2

1

+1.5V

RD10

2

1K_0402_1%

1

1

RD11

2

2

CD51

1K_0402_1%

D

0.1U_0402_10V6K

C

DDRB_CKE0<7>

DDR_B_BS2<7>

DDRB_CLK0<7>

DDRB_CLK0#<7>

DDR_B_BS0<7>

DDR_B_WE#<7>

DDR_B_CAS#<7>

DDRB_SCS1#<7>

B

A

+3VS

5

+1.5V

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

+V_DDR_REFB

1

1

2

CD27

0.1U_0402_10V6K

C185

DDR_B_D0

2

DDR_B_D1

CD28

DDR_B_DM0

2.2U_0603_6.3V4Z

DDR_B_D2

DDR_B_D3

DDR_B_D8

DDR_B_D9

DDR_B_DQS#1

DDR_B_DQS1

DDR_B_D10

DDR_B_D11

DDR_B_D16

DDR_B_D17

DDR_B_DQS#2

DDR_B_DQS2

DDR_B_D18

DDR_B_D19

DDR_B_D24

DDR_B_D25

DDR_B_DM3

DDR_B_D26

DDR_B_D27

DDRB_CKE0

DDR_B_BS2

DDR_B_MA12

DDR_B_MA9

DDR_B_MA8

DDR_B_MA5

DDR_B_MA3

DDR_B_MA1

DDRB_CLK0

DDRB_CLK0#

DDR_B_MA10

DDR_B_BS0

DDR_B_WE#

DDR_B_CAS#

DDR_B_MA13

DDRB_SCS1#

DDR_B_D32

DDR_B_D33

DDR_B_DQS#4

DDR_B_DQS4

DDR_B_D34

DDR_B_D35

DDR_B_D40

DDR_B_D41

DDR_B_DM5

DDR_B_D42

DDR_B_D43

DDR_B_D48

DDR_B_D49

DDR_B_DQS#6

DDR_B_DQS6

DDR_B_D50

DDR_B_D51

DDR_B_D56

DDR_B_D57

DDR_B_DM7

DDR_B_D58

DDR_B_D59

1

R76

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

10K_0402_5%

1

1

2

1

C186

R77 10K_0402_5%

2

5

3A@1.5V

3A@1.5V

3A@1.5V3A@1.5V

JDDRH

1

VREF_DQ

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

83

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

2

199

201

203

2

205

DQS1

VSS11

DQ10

DQ11

VSS13

DQ16

DQ17

VSS15

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25

VSS22

DM3

VSS23

DQ26

DQ27

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

CK0

CK0#

VDD11

A10/AP

BA0

VDD13

WE#

CAS#

VDD15

A13

S1#

VDD17

NCTEST

VSS27

DQ32

DQ33

VSS29

DQS#4

DQS4

VSS32

DQ34

DQ35

VSS34

DQ40

DQ41

VSS36

DM5

VSS37

DQ42

DQ43

VSS39

DQ48

DQ49

VSS41

DQS#6

DQS6

VSS44

DQ50

DQ51

VSS46

DQ56

DQ57

VSS48

DM7

VSS49

DQ58

DQ59

VSS51

SA0

VDDSPD

SA1

VTT1

G1

LCN_DAN06-K4926-0101

CONN@

RESET#

VREF_CA

EVENT#

2

+1.5V

1

+

2

C141

330U 2V Y D2 LESR9M

2

Layout Note:

10U_0603_6.3V6M

Place near JDDRH

10U_0603_6.3V6M

C171

1

2

C173

10U_0603_6.3V6M

1

C172

1

2

2

Layout Note: Place these 4 Caps near
Command and Control signals of JDDRH

+1.5V

0.1U_0402_10V6K
C177

0.1U_0402_10V6K

1

C178

1

2

2

Layout Note:
Place near JDDRH.203 and 204

+0.75VS

1U_0603_10V4Z

C181

1

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

1

10U_0603_6.3V6M

C174

1

2

0.1U_0402_10V6K

1

2

1U_0603_10V4Z

1U_0603_10V4Z

C182

1

1

2

2

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

4019IE

4019IE

4019IE

10U_0603_6.3V6M

10U_0603_6.3V6M

C176

C175

1

1

2

2

0.1U_0402_10V6K

C179

C180

1

2

1U_0603_10V4Z

C370

22U_0805_6.3V6M

C184

C183

1

1

2

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

CD49

CD48

1

1

@

@

2

2

D

C

B

A

B

B

12 60Friday, August 24, 2012

12 60Friday, August 24, 2012

12 60Friday, August 24, 2012

B

of

of

of

PCIE_GTX_C_CRX_P[0..15]<5>

PCIE_GTX_C_CRX_N[0..15]<5>

PCIE_CTX_C_GRX_P[0..15]<5>

PCIE_CTX_C_GRX_N[0..15]<5>

1

PCIE:80ohm+_10%
45~50ohm+_10%

PCIE_GTX_C_CRX_P15

PCIE_GTX_C_CRX_N15

PCIE_GTX_C_CRX_P14

PCIE_GTX_C_CRX_N14

PCIE_GTX_C_CRX_P13

PCIE_GTX_C_CRX_N13

PCIE_GTX_C_CRX_P12

PCIE_GTX_C_CRX_N12

PCIE_GTX_C_CRX_P11

PCIE_GTX_C_CRX_N11

2

PCIE_GTX_C_CRX_P10

PCIE_GTX_C_CRX_N10

PCIE_GTX_C_CRX_P9

PCIE_GTX_C_CRX_N9

PCIE_GTX_C_CRX_P8

PCIE_GTX_C_CRX_N8

PCIE_GTX_C_CRX_P7

PCIE_GTX_C_CRX_N7

PCIE_GTX_C_CRX_P6

PCIE_GTX_C_CRX_N6

PCIE_GTX_C_CRX_P5

PCIE_GTX_C_CRX_N5

PCIE_GTX_C_CRX_P4

PCIE_GTX_C_CRX_N4

PCIE_GTX_C_CRX_P3

PCIE_GTX_C_CRX_N3

PCIE_GTX_C_CRX_P2

PCIE_GTX_C_CRX_N2

PCIE_GTX_C_CRX_P1

PCIE_GTX_C_CRX_N1

PCIE_GTX_C_CRX_P0

PCIE_GTX_C_CRX_N0

+3VS_DGPU

termination

3

RV36 default unmount




RV165 0_0402_5%OPT@

RV166 0_0402_5%OPT@

VID_0

RV167 0_0402_5%OPT@

VID_1

RV168 0_0402_5%OPT@

VID_2

RV169 0_0402_5%OPT@

VID_3

RV170 0_0402_5%OPT@

VID_4

VID_5

4

A

1

@

2

1

OPT@

2

1

@

2

RV161 10 K_0402_5%

RV17310K_0402_5%

1

OPT@

2

CLK_PCIE_VGA<26>

CLK_PCIE_VGA#<26>

RV36 200_0402 _1%@

RV37 2.49K_0402_1%O PT@

+3VS_DGPU

1

OPT@

2

RV162 10K_0 402_5%

1

@

RV17410K_ 0402_5%

2

1

OPT@

2

RV163 10 K_0402_5%

RV164 10K_0 402_5%

1

RV17610K_0402_5%

RV17510K_0402_5%

@

2

PCIE_CTX_C_GRX_P15

PCIE_CTX_C_GRX_N15

PCIE_CTX_C_GRX_P14

PCIE_CTX_C_GRX_N14

PCIE_CTX_C_GRX_P13

PCIE_CTX_C_GRX_N13

PCIE_CTX_C_GRX_P12

PCIE_CTX_C_GRX_N12

PCIE_CTX_C_GRX_P11

PCIE_CTX_C_GRX_N11

PCIE_CTX_C_GRX_P10

PCIE_CTX_C_GRX_N10

PCIE_CTX_C_GRX_P9

PCIE_CTX_C_GRX_N9

PCIE_CTX_C_GRX_P8

PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_P7

PCIE_CTX_C_GRX_N7

PCIE_CTX_C_GRX_P6

PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P5

PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P4

PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P3

PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P2

PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P1

PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P0

PCIE_CTX_C_GRX_N0

PCIE_GTX_CRX_P15

PCIE_GTX_CRX_N15

PCIE_GTX_CRX_P14

PCIE_GTX_CRX_N14

PCIE_GTX_CRX_P13

PCIE_GTX_CRX_N13

PCIE_GTX_CRX_P12

PCIE_GTX_CRX_N12

PCIE_GTX_CRX_P11

PCIE_GTX_CRX_N11

PCIE_GTX_CRX_P10

PCIE_GTX_CRX_N10

PCIE_GTX_CRX_P9

PCIE_GTX_CRX_N9

PCIE_GTX_CRX_P8

PCIE_GTX_CRX_N8

PCIE_GTX_CRX_P7

PCIE_GTX_CRX_N7

PCIE_GTX_CRX_P6

PCIE_GTX_CRX_N6

PCIE_GTX_CRX_P5

PCIE_GTX_CRX_N5

PCIE_GTX_CRX_P4

PCIE_GTX_CRX_N4

PCIE_GTX_CRX_P3

PCIE_GTX_CRX_N3

PCIE_GTX_CRX_P2

PCIE_GTX_CRX_N2

PCIE_GTX_CRX_P1

PCIE_GTX_CRX_N1

PCIE_GTX_CRX_P0

PCIE_GTX_CRX_N0

PEX_TSTCLK_OUT+

PEX_TSTCLK_OUT-

PEX_TREMP

GPU_VID0 <57>

GPU_VID1 <57>

GPU_VID2 <57>

GPU_VID3 <57>

GPU_VID4 <57>

GPU_VID5 <57>

PCIE_GTX_C_CRX_P[0..15]

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

PCIE_GTX_C_CRX_N[0..15]

PCIE_CTX_C_GRX_P[0..15]

PCIE_CTX_C_GRX_N[0..15]

2

1

C16 0.1U_0402_16V7KOPT@

2

1

C17 0.1U_0402_16V7KOPT@

2

1

C20 0.1U_0402 _16V7KOPT@

2

1

C18 0.1U_0402_16V7KOPT@

2

1

C19 0.1U_0402_16V7KOPT@

2

1

C21 0.1U_0402_16V7KOPT@

2

1

C22 0.1U_0402_16V7KOPT@

2

1

C23 0.1U_0402_16V7KOPT@

2

1

C24 0.1U_0402_16V7KOPT@

2

1

C25 0.1U_0402_16V7 KOPT@

2

1

C26 0.1U_0402_16V7KOPT@

2

1

C28 0.1U_0402 _16V7KOPT@

2

1

C29 0.1U_040 2_16V7KOPT@

2

1

C27 0.1U_0402_16V7KOPT@

2

2

1

1

C32 0.1U_040 2_16V7KOPT@

C30 0.1U_0402_16V7KOPT@

2

1

C31 0.1U_0402_16V7KOPT@

2

1

C33 0.1U_0402_16V7KOPT@

2

1

C35 0.1U_0402_ 16V7KOPT@

2

1

C34 0.1U_0402_16V7KOPT@

2

1

C37 0.1U_0402 _16V7KOPT@

2

1

C36 0.1U_0402_16V7KOPT@

2

1

C39 0.1U_0402_ 16V7KOPT@

2

1

C38 0.1U_0402_16V7KOPT@

2

1

C40 0.1U_0402 _16V7KOPT@

2

1

C45 0.1U_0402_ 16V7KOPT@

2

1

C46 0.1U_0402_16V7 KOPT@

2

1

C116 0.1U_0402_16V7KOPT@

2

1

C48 0.1U_0402_16V7KOPT@

2

1

C213 0.1U_0402_16V7KOPT@

2

1

C226 0.1U_0402_16V7KOPT@

2

1

C47 0.1U_0402_16V7KOPT@

2

1

OPT@

RV48 10K_040 2_5%

PEG_CLKREQ#<26>

PLTRST_VGA#<28>

PEX_TERMP: used for internal calibration.

1

1

@

@

2

2

RV160 10 K_0402_5%

RV159 10 K_0402_5%

2

1

2

1

2

1

2

1

2

1

2

1

1

1

RV17110K_0402_5%

RV17210K_04 02_5%

OPT@

OPT@

2

2

A

B

UV1A

AN12

PEX_RX0

AM12

PEX_RX0_N

AN14

PEX_RX1

AM14

PEX_RX1_N

AP14

PEX_RX2

AP15

PEX_RX2_N

AN15

PEX_RX3

AM15

PEX_RX3_N

AN17

PEX_RX4

AM17

PEX_RX4_N

AP17

PEX_RX5

AP18

PEX_RX5_N

AN18

PEX_RX6

AM18

PEX_RX6_N

AN20

PEX_RX7

AM20

PEX_RX7_N

AP20

PEX_RX8

AP21

PEX_RX8_N

AN21

PEX_RX9

AM21

PEX_RX9_N

AN23

PEX_RX10

AM23

PEX_RX10_N

AP23

PEX_RX11

AP24

PEX_RX11_N

AN24

PEX_RX12

AM24

PEX_RX12_N

AN26

PEX_RX13

AM26

PEX_RX13_N

AP26

PEX_RX14

AP27

PEX_RX14_N

AN27

PEX_RX15

AM27

PEX_RX15_N

AK14

PEX_TX0

AJ14

PEX_TX0_N

AH14

PEX_TX1

AG14

PEX_TX1_N

AK15

PEX_TX2

AJ15

PEX_TX2_N

AL16

PEX_TX3

AK16

PEX_TX3_N

AK17

PEX_TX4

AJ17

PEX_TX4_N

AH17

PEX_TX5

AG17

PEX_TX5_N

AK18

PEX_TX6

AJ18

PEX_TX6_N

AL19

PEX_TX7

AK19

PEX_TX7_N

AK20

PEX_TX8

AJ20

PEX_TX8_N

AH20

PEX_TX9

AG20

PEX_TX9_N

AK21

PEX_TX10

AJ21

PEX_TX10_N

AL22

PEX_TX11

AK22

PEX_TX11_N

AK23

PEX_TX12

AJ23

PEX_TX12_N

AH23

PEX_TX13

AG23

PEX_TX13_N

AK24

PEX_TX14

AJ24

PEX_TX14_N

AL25

PEX_TX15

AK25

PEX_TX15_N

AJ11

PEX_WAKE_N

AL13

PEX_REFCLK

AK13

PEX_REFCLK_N

AK12

PEX_CLKREQ_N

AJ26

PEX_TSTCLK_OUT

AK26

PEX_TSTCLK_OUT_N

AJ12

PEX_RST_N

AP29

PEX_TERMP

N13P-GLP-A1 FCBGA 908P GPU

OPT@

XTALOUT

10P_0402_50V8J

1

I2CS_SCL

DMN66D0LDW-7_SOT363-6

OPT@

4

I2CS_SDA

B

OPT@

2

QV6A

5

QV6B

Part 1 of 7

4

1

CV46

+3VS_DGPU

OPT@

+3VS_DGPU

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC

DACA_VSYNC

DACs

DACA_VDD

DACA_VREF

DACA_RSET

I2CA_SCL

I2CA_SDA

PCI EXPRESS

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2CC_SDA

I2C

I2CS_SCL

I2CS_SDA

PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

CLK

XTAL_OUTBUFF

XTAL_SSIN

@

RV55 1M_0402_5%

YV1

Crystal

3

GND

OUT

2

GND

IN

27MHZ_10PF_7V2700005 0

OPT@

6

EC_SMB_CK2 <26,41>

RV35 0_0402_5%@

I2CS_SCL

RV40

@

0_0402_5%

I2CS_SDA

3

EC_SMB_DA2 <26,41>

P6

M3

L6

P5

P7

VID_4

L7

VID_3

M7

N8

M1

M2

VID_1

L1

VID_2

M5

N3

M4

N4

P2

VID_0

R8

GPS_DOWN#

VID_5

M6

R1

P3

P4

P1

AK9

AL10

AL9

AM9

AN9

AG10

AP9

AP8

R4

R5

R7

VGA_CRT_CLK

R6

VGA_CRT_DATA

R2

R3

T4

VGA_LCD_CLK

T3

VGA_LCD_DATA

AD8

AE8

+PLLVDD

AD7

H3

H2

J4

H1

XTAL_OUTBUFF

XTAL_SSIN

XTALIN

XTALIN

OPT@

CV47

10P_0402_50V8J

C

RV30 10K_0402 _5%OPT@

RV29 10K_0402_5 %OPT@

RH168 3 30K_0402_5%OPT@

GPS_DOWN#

RH172

OPT@

2

1

10K_0402_5%

I2CB_SCL

I2CB_SDA

I2CS_SCL

I2CS_SDA

+PLLVDD

+GPU_PLLVDD

XTALIN

XTALOUT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+3VS_DGPU

+3VS_DGPU

5

UV2

1

P

IN1

4

O

2

IN2

G

TC7SH08FU(TE85L,F)

@

3

2

CH751H-40PT_SOD323-2

R270

@

2

1

0_0402_5%

2

1

R268 0_040 2_5%OPT@

I2CA/B/C: Master
I2CS: Slaver (for Internal Thermal Sensor)

+3VS_DGPU

DV6

@

LV10

+PLLVDD

@

2

R2660_0402_5%

2

R2670_0402_5%

@

1

EC_GPS_DOWN# <41>

猁ㄩ

30ohm, ESR=0.05

1

1

VGA_CRT_CLK

VGA_CRT_DATA

I2CB_SCL

I2CB_SDA

VGA_LCD_CLK

VGA_LCD_DATA

I2CS_SCL

I2CS_SDA

60mA




LV18

猁ㄩ

+GPU_PLLVDD

OPT@

2

1

2

1

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

180ohm, ESR=0.2

CV38

CV40

OPT@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+GPU_PLLVDD

90mA






RV45 10K_0 402_5%OPT@

RV52 10K_0402_5 %OPT@

XTAL_OUTBUFF

XTAL_SSIN

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

D

PSI: Phase shedding

PWR_GPS_DOWN# <41,5 7>

ACIN <27,41,48>

OPT@

2.2K_0402_5%

2.2K_0402_5%OPT@

LV10

拸

CV42ㄛCV44

1

BLM18PG181SN1D_2P



22U_0805_6.3V6M





+3VS_DGPU

+1.05VS_DGPU

2

LV18

OPT@

2

+1.05VS_DGPU

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

RV39 2.2K_0402 _5%OPT@

RV38 2.2K_0402_5%OPT@

RV41 2.2K_0402_5%OPT@

RV42 2.2K_0402_5%OPT@

RV44

RV43 2.2K_0402_5%OPT@

RV46 2.2K_0402_5%OPT@

RV47

SM010018510--­SM01000FE00-­SM010007W00--

OPT@

30R@100MHz(ESR=0.5)

1

CV41

OPT@

BLM18PG330SN1D_0603

CV42

@

CV43

0.1U_0402_16V4Z

4.7U_0402_6.3V6M

OPT@



22U_0805_6.3V6M





DG

CV310

CV311

OPT@

OPT@

4.7U_0402_6.3V6M

PFH: Pixel-Clock Frequency Hopping Interface.
PFH can be implemented in system software with
NVAPI to reduce interference between graphic
and wireless networking modems.
Refer to SP-04941-001

D

GPIO I/O USAGE

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

CV44

OPT@

22U_0805_6.3V6M

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

4019IE

4019IE

4019IE

E

GPU Core VID4

O

GPU Core VID3

O

O

LCD_BL_PWM

O

LCD_VCC or PSI

O

LCD_BLEN

O

GPU Core VID1

O

GPU Core VID2

O

3D Vision

OVERT

I/O

I/O

ALERT

O

MEM_VREF_CTL

O

GPU Core VID0

I

PWR_LEVEL

GPU Core VID5

O

I

HPD_AB

HPD_C

I

O

MEM_VDD_CTL or PSI

HPD_D

I

HPD_E

I

HPD_F

I

Reserved

Reserved

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

13 60Friday, August 24, 2012

of

13 60Friday, August 24, 2012

of

13 60Friday, August 24, 2012

E

of

1

2

3

4

B

B

B

MDA[15..0]<18>

Part 2 of 7

MEMORY INTERFACE

MDA[31..16]<18>

MDA[47..32]<19>

MDA[63..48]<19>

FBA_CMD_RFU0

FBA_CMD_RFU1

A

FBA_WCK01_N

FBA_WCK23_N

FBA_WCK45_N

FBA_WCK67_N

FBA_WCKB01_N

FBA_WCKB23_N

FBA_WCKB45_N

FBA_WCKB67_N

FB_DLL_AVDD

FBA_PLL_AVDD

FBA_CMD0

FBA_CMD1

FBA_CMD2

FBA_CMD3

FBA_CMD4

FBA_CMD5

FBA_CMD6

FBA_CMD7

FBA_CMD8

FBA_CMD9

FBA_CMD10

FBA_CMD11

FBA_CMD12

FBA_CMD13

FBA_CMD14

FBA_CMD15

FBA_CMD16

FBA_CMD17

FBA_CMD18

FBA_CMD19

FBA_CMD20

FBA_CMD21

FBA_CMD22

FBA_CMD23

FBA_CMD24

FBA_CMD25

FBA_CMD26

FBA_CMD27

FBA_CMD28

FBA_CMD29

FBA_CMD30

FBA_CMD31

FBA_DEBUG0

FBA_DEBUG1

FBA_CLK0_N

FBA_CLK1_N

FBA_WCK01

FBA_WCK23

FBA_WCK45

FBA_WCK67

FBA_WCKB01

FBA_WCKB23

FBA_WCKB45

FBA_WCKB67

FB_CLAMP

VRAM Interface

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

UV1B

L28

FBA_D0

M29

FBA_D1

L29

MDA0

MDA1

MDA2

MDA3

MDA4

MDA5

MDA6

MDA7

MDA8

MDA9

MDA10

MDA11

MDA12

MDA13

MDA14

MDA15

MDA16

MDA17

MDA18

MDA19

MDA20

MDA21

MDA22

MDA23

MDA24

MDA25

MDA26

MDA27

MDA28

MDA29

MDA30

MDA31

MDA32

MDA33

MDA34

MDA35

MDA36

MDA37

MDA38

MDA39

MDA40

MDA41

MDA42

MDA43

MDA44

MDA45

1

DQMA[3..0]<18>

DQMA[7..4]<19>

DQSA[3..0]<18>

DQSA[7..4]<19>

DQSA#[3..0]<18>

DQSA#[7..4]<19>

MDA46

MDA47

MDA56

MDA57

MDA58

MDA59

MDA60

MDA61

MDA62

MDA63

MDA48

MDA49

MDA50

MDA51

MDA52

MDA53

MDA54

MDA55

DQMA0

DQMA1

DQMA2DQMA2

DQMA3

DQMA4DQMA4

DQMA5

DQMA6

DQMA7

DQSA0

DQSA1

DQSA2

DQSA3

DQSA4

DQSA5

DQSA6

DQSA7

DQSA#0

DQSA#1

DQSA#2

DQSA#3

DQSA#4

DQSA#5

DQSA#6

DQSA#7

FBA_D2

M28

FBA_D3

N31

FBA_D4

P29

FBA_D5

R29

FBA_D6

P28

FBA_D7

J28

FBA_D8

H29

FBA_D9

J29

FBA_D10

H28

FBA_D11

G29

FBA_D12

E31

FBA_D13

E32

FBA_D14

F30

FBA_D15

C34

FBA_D16

D32

FBA_D17

B33

FBA_D18

C33

FBA_D19

F33

FBA_D20

F32

FBA_D21

H33

FBA_D22

H32

FBA_D23

P34

FBA_D24

P32

FBA_D25

P31

FBA_D26

P33

FBA_D27

L31

FBA_D28

L34

FBA_D29

L32

FBA_D30

L33

FBA_D31

AG28

FBA_D32

AF29

FBA_D33

AG29

FBA_D34

AF28

FBA_D35

AD30

FBA_D36

AD29

FBA_D37

AC29

FBA_D38

AD28

FBA_D39

AJ29

FBA_D40

AK29

FBA_D41

AJ30

FBA_D42

AK28

FBA_D43

AM29

FBA_D44

AM31

FBA_D45

AN29

FBA_D46

AM30

FBA_D47

AN31

FBA_D48

AN32

FBA_D49

AP30

FBA_D50

AP32

FBA_D51

AM33

FBA_D52

AL31

FBA_D53

AK33

FBA_D54

AK32

FBA_D55

AD34

FBA_D56

AD32

FBA_D57

AC30

FBA_D58

AD33

FBA_D59

AF31

FBA_D60

AG34

FBA_D61

AG32

FBA_D62

AG33

FBA_D63

P30

FBA_DQM0

F31

FBA_DQM1

F34

FBA_DQM2

M32

FBA_DQM3

AD31

FBA_DQM4

AL29

FBA_DQM5

AM32

FBA_DQM6

AF34

FBA_DQM7

M31

FBA_DQS_WP0

G31

FBA_DQS_WP1

E33

FBA_DQS_WP2

M33

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AK30

FBA_DQS_WP5

AN33

FBA_DQS_WP6

AF33

FBA_DQS_WP7

M30

FBA_DQS_RN0

H30

FBA_DQS_RN1

E34

FBA_DQS_RN2

M34

FBA_DQS_RN3

AF30

FBA_DQS_RN4

AK31

FBA_DQS_RN5

AM34

FBA_DQS_RN6

AF32

FBA_DQS_RN7

N13P-GLP-A1 FCBGA 908P GPU

OPT@

FBA_CLK0

FBA_CLK1

FB_VREF

U30

T31

U29

R34

R33

U32

U33

U28

V28

V29

V30

U34

U31

V34

V33

Y32

AA31

AA29

AA28

AC34

AC33

AA32

AA33

Y28

Y29

W31

Y30

AA34

Y31

Y34

Y33

V31

R32

AC32

R28

AC28

R30

R31

AB31

AC31

K31

L30

H34

J34

AG30

AG31

AJ34

AK34

J30

J31

J32

J33

AH31

AJ31

AJ32

AJ33

E1

K27

U27

H26

MDA[15..0]

MDA[31..16]

MDA[47..32]

MDA[63..48]

CMDA[30..0] <18,19>

CMDA0

CMDA1

CMDA2

CMDA3

CMDA4

CMDA5

CMDA6

CMDA7

CMDA8

CMDA9

CMDA10

CMDA11

CMDA12

CMDA13

CMDA14

CMDA15

CMDA16

CMDA17

CMDA18

CMDA19

CMDA20

CMDA21

CMDA22

CMDA23

CMDA24

CMDA25

CMDA26

CMDA27

CMDA28

CMDA29

CMDA30

RV57, RV58, RV59, RV60 change BS from
"OPT@" to "@".--Design Guide. Joyce 1018

2

1

RV57 60.4_0402 _1%@

FBA_DEBUG0

2

FBA_DEBUG1

RV59 60.4_0402_1%@

FB_CLAMP:
Leave as NC for N13P-PES/-GL/-GLP/-NS1
and N13M-GE1/NS1;
Pull down with a 10K on N13P-GV, N13M-GS,
N13E-GE,N13P-GT/-GS/-LP and N14-Q1/-Q3.

RV152

@

10K_0402_5%

+FB_PLLAVDD

66mA

CV49

0.1U_0402_16V4Z

OPT@

CV49 Under GPU
close to ball : U27

1

CLKA0 <18>

CLKA0# <18>

CLKA1 <19>

CLKA1# <19>

OPT@

+1.5VSDGPU

+FB_PLLAVDD

CV50

0.1U_0402_16V4Z

CV50 Under GPU
close to ball : K27

A

MDC0

MDC1

MDC2

MDC3

MDC4

MDC5

MDC6

MDC7

MDC8

MDC9

MDC10

MDC11

MDC12

MDC13

MDC14

MDC15

MDC16

MDC17

MDC18

MDC19

MDC20

MDC21

MDC22

MDC23

MDC24

MDC25

MDC26

MDC27

MDC28

MDC29

MDC30

MDC31

MDC32

MDC33

MDC34

MDC35

MDC36

MDC37

MDC38

MDC39

MDC40

MDC41

MDC42

MDC43

MDC44

MDC45

MDC46

MDC47

MDC48

MDC49

MDC50

MDC51

MDC52

MDC53

MDC54

MDC55

MDC56

MDC57

MDC58

MDC59

MDC60

MDC61

MDC62

DQMC[3..0]<20>

DQMC[7..4]<21>

DQSC[3..0]<20>

DQSC[7..4]<21>

DQSC#[3..0]<20>

DQSC#[7..4]<21>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

MDC63

DQMC0

DQMC1

DQMC2

DQMC3

DQMC4

DQMC5

DQMC6

DQMC7

DQSC0

DQSC1

DQSC2

DQSC3

DQSC4

DQSC5

DQSC6

DQSC7

DQSC#0

DQSC#1

DQSC#2

DQSC#3

DQSC#4

DQSC#5

DQSC#6

DQSC#7

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

MDC[15..0]<20>

MDC[31..16]<20>

MDC[47..32]<21>

MDC[63..48]<21>

UV1C

G9

FBB_D0

E9

FBB_D1

G8

FBB_D2

F9

FBB_D3

F11

FBB_D4

G11

FBB_D5

F12

FBB_D6

G12

FBB_D7

G6

FBB_D8

F5

FBB_D9

E6

FBB_D10

F6

FBB_D11

F4

FBB_D12

G4

FBB_D13

E2

FBB_D14

F3

FBB_D15

C2

FBB_D16

D4

FBB_D17

D3

FBB_D18

C1

FBB_D19

B3

FBB_D20

C4

FBB_D21

B5

FBB_D22

C5

FBB_D23

A11

FBB_D24

C11

FBB_D25

D11

FBB_D26

B11

FBB_D27

D8

FBB_D28

A8

FBB_D29

C8

FBB_D30

B8

FBB_D31

F24

FBB_D32

G23

FBB_D33

E24

FBB_D34

G24

FBB_D35

D21

FBB_D36

E21

FBB_D37

G21

FBB_D38

F21

FBB_D39

G27

FBB_D40

D27

FBB_D41

G26

FBB_D42

E27

FBB_D43

E29

FBB_D44

F29

FBB_D45

E30

FBB_D46

D30

FBB_D47

A32

FBB_D48

C31

FBB_D49

C32

FBB_D50

B32

FBB_D51

D29

FBB_D52

A29

FBB_D53

C29

FBB_D54

B29

FBB_D55

B21

FBB_D56

C23

FBB_D57

A21

FBB_D58

C21

FBB_D59

B24

FBB_D60

C24

FBB_D61

B26

FBB_D62

C26

FBB_D63

E11

FBB_DQM0

E3

FBB_DQM1

A3

FBB_DQM2

C9

FBB_DQM3

F23

FBB_DQM4

F27

FBB_DQM5

C30

FBB_DQM6

A24

FBB_DQM7

D10

FBB_DQS_WP0

D5

FBB_DQS_WP1

C3

FBB_DQS_WP2

B9

FBB_DQS_WP3

E23

FBB_DQS_WP4

E28

FBB_DQS_WP5

B30

FBB_DQS_WP6

A23

FBB_DQS_WP7

D9

FBB_DQS_RN0

E4

FBB_DQS_RN1

B2

FBB_DQS_RN2

A9

FBB_DQS_RN3

D22

FBB_DQS_RN4

D28

FBB_DQS_RN5

A30

FBB_DQS_RN6

B23

FBB_DQS_RN7

N13P-GLP-A1 FCBGA 908P GPU

OPT@

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Part 3 of 7

MDC[15..0]

MDC[31..16]

MDC[47..32]

MDC[63..48]

MEMORY INTERFACE B

FBB_CMD0

FBB_CMD1

FBB_CMD2

FBB_CMD3

FBB_CMD4

FBB_CMD5

FBB_CMD6

FBB_CMD7

FBB_CMD8

FBB_CMD9

FBB_CMD10

FBB_CMD11

FBB_CMD12

FBB_CMD13

FBB_CMD14

FBB_CMD15

FBB_CMD16

FBB_CMD17

FBB_CMD18

FBB_CMD19

FBB_CMD20

FBB_CMD21

FBB_CMD22

FBB_CMD23

FBB_CMD24

FBB_CMD25

FBB_CMD26

FBB_CMD27

FBB_CMD28

FBB_CMD29

FBB_CMD30

FBB_CMD31

FBB_CMD_RFU0

FBB_CMD_RFU1

FBB_DEBUG0

FBB_DEBUG1

FBB_CLK0

FBB_CLK0_N

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

FBB_PLL_AVDD

D13

E14

F14

A12

CMDC0

B12

CMDC1

C14

CMDC2

B14

CMDC3

G15

CMDC4

F15

CMDC5

E15

CMDC6

D15

CMDC7

A14

CMDC8

D14

CMDC9

A15

CMDC10

B15

CMDC11

C17

CMDC12

D18

CMDC13

E18

CMDC14

F18

CMDC15

A20

CMDC16

B20

CMDC17

C18

CMDC18

B18

CMDC19

G18

CMDC20

G17

CMDC21

F17

CMDC22

D16

CMDC23

A18

CMDC24

D17

CMDC25

A17

CMDC26

B17

CMDC27

E17

CMDC28

CMDC29

CMDC30

C12

C20

G14

G20

FBB_DEBUG0

FBB_DEBUG1

D12

E12

E20

F20

F8

E8

A5

A6

D24

D25

B27

C27

D6

D7

C6

B6

F26

E26

A26

A27

H17

+FB_PLLAVDD

66mA35mA

FBB_PLL_AVDD Design Guide:

100nF X7R 0402 1pcs per pin under GPU

22uF X5R 0805 1pcs per pin Near GPU

bead--30ohm@100MHz (ESR=0.01ohm) 0603 1pcs Near GPU

CMDC[30..0] <20,21>

2

1

RV58 60.4_0402 _1%@

2

RV60 60.4_0402_ 1%@

CV48

OPT@

0.1U_0402_16V4Z

CV48 Under GPU
close to ball : H17

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

+1.5VSDGPU

1

CLKC0 <20>

CLKC0# <20>

CLKC1 <21>

CLKC1# <21>

+FB_PLLAVDD

+FB_PLLAVDD

+FB_PLLAVDD

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

4019IE

4019IE

4019IE

300mA

CV51

OPT@

1U_0402_6.3V6K

LV11

1

MPZ1608S300AT 0603

1

CV52

2

OPT@

22U_0805_6.3V6M

30ohm@100M // ESR=0.01
SM01000EQ00-­SM010031100--

1

OPT@

+1.05VS_DGPU

2

CV53

OPT@

1U_0402_6.3V6K

B

B

B

14 60Friday, August 24, 2012

of

14 60Friday, August 24, 2012

of

14 60Friday, August 24, 2012

of

1

RV69

@

4.99K_0402_1%

2

1

RV77

@

45.3K_0402_1%

2

1

1

RV70

@

4.99K_0402_1%

2

1

RV78

10K_0402_1%

2

Resistor
Values

5K

10K

15K

20K

25K

30K

35K

45K

+3VS_DGPU

1

2

1

2

Pull up
to 3V

1000 0000

1001 0001

1010 0010

1011 0011

1100 0100

1101 0101

1110 0110

1111 0111

RV71

@

4.99K_0402_1%

RV79

15K_0402_1%

Pull down
to GND

D

C

B

2

+3VS_DGPU

1

RV66

4.99K_0402_1%

2

1

RV74

@

10K_0402_1%

2

1

1

RV68

@

@

30K_0402_1%

2

2

RV67

34.8K_0402_1%

STRAP3

STRAP4

1

1

2

RV75

2

RV76

20K_0402_1%

4.99K_0402_1%

@

@

Logical
Strapping Bit2

RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]

FB [0] VGA_DEVICE

USER [2] USER [1] USER [0]

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]

PCI-DEVID [2] PCI-DEVID [1] PCI-DEVID [0]

SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED

CHANGE_GEN3

PEX_PLL_EN_TERM:
PLL termination setting

0

Disable (Default)

1 Enable

ROM_SI

ROM_SO

ROM_SCLK

Logical
Strapping Bit1

SMB_ALT_ADDR

PCIE_MAX_SPEED DP_PLL_VDD33V

Logical
Strapping Bit0

PCIE_MAX_SPEED

01Limited to PCIE GEN 1

PCIE GEN 2/3 capable

X76-

PAD

PAD

PAD

PAD

+3VS_DGPU

3

VCCSENSE_VGA <57>

VSSSENSE_VGA <57>

+3VS_DGPU

@

TV1

@

TV2

@

TV3

@

TV4

+3VS_DGPU

STRAP0

STRAP1

STRAP2

Straps

MULTI LEVEL STRAPS

1

RV64

45.3K_0402_1%

2

1

RV72

@

4.99K_0402_1%

2

Physical
strapping pin

ROM_SCLK

ROM_SI

ROM_SO

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

SUB_VENDOR

01No VBIOS ROM

BIOS ROM is present (Default)

FB [1:0]: N13x FB Aperture Size

0

RESERVED

1

RESERVED

256 MB (Default)

2

3 RESERVED

USER Straps

1111

EDID is used

others: DG-05587 Page195

3GIO_PAD_CFG

0000--0101 RESERVED

0110 Notebook (default)

0111--1111 RESERVED

1

RV65

@

4.99K_0402_1%

2

1

RV73

45.3K_0402_1%

2

Logical
Strapping Bit3

PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM

RAM_CFG[3]

FB [1]

USER [3]

3GIO_PAD_CFG_ADR[3]

PCI-DEVID [3]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

5

D

C

B

UV1D

AM6

IFPA_TXC

AN6

IFPA_TXC_N

AP3

IFPA_TXD0

AN3

IFPA_TXD0_N

AN5

IFPA_TXD1

AM5

IFPA_TXD1_N

AL6

IFPA_TXD2

AK6

IFPA_TXD2_N

AJ6

IFPA_TXD3

AH6

IFPA_TXD3_N

AJ9

IFPB_TXC

AH9

IFPB_TXC_N

AP6

IFPB_TXD4

AP5

IFPB_TXD4_N

AM7

IFPB_TXD5

AL7

IFPB_TXD5_N

AN8

IFPB_TXD6

AM8

IFPB_TXD6_N

AK8

IFPB_TXD7

AL8

IFPB_TXD7_N

AK1

IFPC_L0

AJ1

IFPC_L0_N

AJ3

IFPC_L1

AJ2

IFPC_L1_N

AH3

IFPC_L2

AH4

IFPC_L2_N

AG5

IFPC_L3

AG4

IFPC_L3_N

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AG3

IFPC_AUX_I2CW_SCL

AG2

IFPC_AUX_I2CW_SDA_N

AK3

IFPD_AUX_I2CX_SCL

AK2

IFPD_AUX_I2CX_SDA_N

AB3

IFPE_AUX_I2CY_SCL

AB4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

N13P-GLP-A1 FCBGA 908P GPU

OPT@

Part 4 of 7

LVDS/TMDS

4

NC

VDD_SENSE

GND_SENSE

TEST

TESTMODE

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST_N

SERIAL

ROM_CS_N

ROM_SCLK

ROM_SI

ROM_SO

GENERAL

BUFRST_N

MULTI_STRAP_REF0_GND

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

THERMDP

THERMDN

P8

NC

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

H31

NC

T8

NC

V32

NC

L4

L5

AK11

AM10

AM11

AP12

AP11

AN11

H6

H4

ROM_CS#

H5

ROM_SCLK

H7

ROM_SI

ROM_SO

ROM support: 512Kbit or greater, up to 50MHz.

CEC: Place a 10K pull up resistor to 3.3V on
N13P-PES/-GL/-GLP/-NS1 and N13M-NS1

L2

L3

CEC

J1

MULTI_STRAP_REF0_GND

J2

J7

J6

J5

J3

K3

K4

@

PAD

TV5

2

1

RV177 0_0402_5%OPT@

2

1

RV178 0_0402_5%OPT@

RV88 10K_04 02_5%@

DG:

啎啎

RV88 for XOR tree testing. --Joyce 1026

RV82 10K_0402_5%OPT@

RV83 10K_0402_5%OPT@

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST

OPT@

RV84 10K_0402_5%

RV85 10K_04 02_5%

OPT@

RV153 10K_0402_5%@

RV86 10K_04 02_5%OPT@

2

1

RV87 40.2K_04 02_1%OPT@

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

For N13P-GLP strap table

For N13P-PES :
Strap 0 : PU45
Strap 1 : PD35
Strap 2 : PU35
ROM_SCLK : PU15
ROM_SI : PD35

A

5

4

ROM_SO : PD10

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

900 MHz

900 MHz

N13P-GLP

900 MHz

900 MHz

Compal Secret Data

Compal Secret Data

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

Compal Secret Data

Memory SizeFrenq . strap4strap3GPU

64M* 16* 8
1GB

64M* 16* 8
1GB

128M* 16* 8
2GB

128M* 16* 8
2GB

Deciphered Date

Deciphered Date

Deciphered Date

Memory Config

Hynix
SA000041S20

Samsung
SA00004GS00

Hynix
SA00003YO00

Samsung
SA000047Q00

ROM_SIstrap 2strap1strap0 ROM_SCLKROM_SO

RV77

RV73

RV64
PU 45K

RV64
PU 45K

RV64
PU 45K

RV64
PU 45K

2

RV74
PU 5K

PD 45K

RV73
PD 45K

RV73
PD 45K

RV73
PD 45K

RV74
PU 5K

RV74
PU 5K

RV74
PU 5K

NC

NC

NC

NC

NC

NC

NC

NC

Title

Title

Title

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sheet

Date: Sheet

Date: Sheet

RV70

PD 15K

PD 30K

RV70

RV77

PD 30K

PD 20K

RV70

RV77

PD 30K

PD 35K

RV70

RV77

PD 30K

PD 45K

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

RV71
PD 15K

RV71
PD 15K

RV71
PD 15K

RV71
PD 15K

15 60Frid ay, August 24, 2012

15 60Frid ay, August 24, 2012

15 60Fr iday, August 24, 2012

A

B

B

B

of

of

of

FBVDDQ Decouping Design Guide:

D

0.1uF X7R 0402 8pcs under GPU
1uF X7R 0603 2pcs under GPU

4.7uF X6S 0603 2pcs under GPU
10uF X5R 0805 4pcs Near GPU

C

Calibration Pin

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

B

A

5

4

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

DDR3 GDDR5

40.2ohm

40.2ohm

40.2ohm

42.2ohm

60.4ohm

51.1ohm

300ohm 100MHz, ESR=0.25ohm

220ohm 100MHz, ESR=0.05ohm

5

+1.5VSDGPU

1

2

OPT@

+1.5VSDGPU

+1.5VSDGPU

+3VS_DGPU

2

BLM18PG181SN1D_0603

+1.05VS_DGPU

2

BLM18PG181SN1D_0603

CV83

10U_0603_6.3V6M

LV7

@

LV13

@

CV61

OPT@

4.7U_0603_6.3V6K

CV69

OPT@

4.7U_0603_6.3V6K

Near GPU

1

CV84

OPT@

2

OPT@

10U_0603_6.3V6M

Near GPU

1

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1

Under GPU

CV62

CV63

CV64

OPT@

OPT@

1U_0402_6.3V6K

OPT@

0.1U_0402_16V4Z

Under GPU

CV79

CV71

CV70

OPT@

OPT@

OPT@

1U_0402_6.3V6K

0.1U_0402_16V4Z

1

1

CV85

CV86

2

2

10U_0603_6.3V6M

OPT@

10U_0603_6.3V6M

2

RV91 10_0402_5%

2

RV93 10_0402_5%

2

RV96 40.2_0402_1%

2

RV98 42.2_0402_1%

2

RV101 51.1_0402_1%

1U_0402_6.3V4Z

1

1

CV203

CV199

@

2

@

2

Under GPU(below 150mils)

0.1U_0402_16V4Z

1

1

CV205

CV201

@

@

2

2

1U_0402_6.3V4Z

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

OPT@

OPT@

OPT@

OPT@

OPT@

0.1U_0402_16V4Z

Design guide no define

7200mA

CV65

CV66

OPT@

OPT@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CV72

CV73

OPT@

OPT@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

FB_VDDQ_SENSE

1

FB_GND_SENSE

1

FB_CAL_PD_VDDQ

1

FB_CAL_PU_GND

1

FB_CAL_TERM_GND

Under GPU

0.1U_0402_16V4Z

1

1

CV202

CV200

@

2

@

2

1

1

CV206

CV204

0.1U_0402_16V4Z

@

2

@

2

UV1E

AA27

FBVDDQ_0

AA30

FBVDDQ_1

AB27

FBVDDQ_2

AB33

FBVDDQ_3

AC27

FBVDDQ_4

AD27

FBVDDQ_5

AE27

FBVDDQ_6

AF27

FBVDDQ_7

AG27

FBVDDQ_8

B13

FBVDDQ_9

B16

FBVDDQ_10

B19

FBVDDQ_11

E13

FBVDDQ_12

E16

FBVDDQ_13

E19

FBVDDQ_14

H10

FBVDDQ_15

H11

FBVDDQ_16

H12

FBVDDQ_17

H13

FBVDDQ_18

H14

FBVDDQ_19

H15

FBVDDQ_20

H16

FBVDDQ_21

H18

FBVDDQ_22

H19

FBVDDQ_23

H20

FBVDDQ_24

H21

FBVDDQ_25

H22

FBVDDQ_26

H23

FBVDDQ_27

H24

FBVDDQ_28

H8

FBVDDQ_29

H9

FBVDDQ_30

L27

FBVDDQ_31

M27

FBVDDQ_32

N27

FBVDDQ_33

P27

FBVDDQ_34

R27

FBVDDQ_35

T27

FBVDDQ_36

T30

FBVDDQ_37

T33

FBVDDQ_38

V27

FBVDDQ_39

W27

FBVDDQ_40

W30

FBVDDQ_41

W33

FBVDDQ_42

Y27

FBVDDQ_43

F1

FB_VDDQ_SENSE

F2

FB_GND_SENSE

J27

FB_CAL_PD_VDDQ

H27

FB_CAL_PU_GND

H25

FB_CAL_TERM_GND

N13P-GLP-A1 FCBGA 908P GPU

OPT@

+IFPC_PLLVDD

1

CV215

0.1U_0402_16V4Z

@

2

+IFPC_IOVDD

CV54

OPT@

1U_0402_6.3V6K

210mA

210mA

150mA

2

RV102 10K_0402_5%OPT@

RV90 1K_040 2_5%@

2

RV104 10K_0402_5%OPT@

2

RV92 10K_04 02_5%OPT@

RV94 1K_0402 _5%@

2

2

RV97 10K_04 02_5%OPT@

RV99 1K_040 2_5%@

2

2

RV114 10K_0402_5%OPT@

RV103 1K_0402_5%

2

RV126 10K_0402_5%OPT@

X6S

X5R

X5R

X5R

X5R

X5R

2

Near GPU

CV56

CV55

OPT@

1U_0402_6.3V6K

4.7U_0603_6.3V6K

Under GPU

CV74

OPT@

PEX_PLL_HVDD:
N13P-GLP/PES :NC
N13P-LP : power.

0603

0805

0805

0603

080511

2

1

2

OPT@

1U_0402_6.3V6K

CV57

1

2

10U_0603_6.3V6M

OPT@

CV75

OPT@

Under GPU

Under GPU

2

4

4

CV58

10U_0603_6.3V6M

Near GPU

OPT@

1U_0402_6.3V6K

CV87

OPT@

OPT@

3

Part 5 of 7

POWER

PEX_IOVDD_0

PEX_IOVDD_1

PEX_IOVDD_2

PEX_IOVDD_3

PEX_IOVDD_4

PEX_IOVDD_5

PEX_IOVDDQ_0

PEX_IOVDDQ_1

PEX_IOVDDQ_2

PEX_IOVDDQ_3

PEX_IOVDDQ_4

PEX_IOVDDQ_5

PEX_IOVDDQ_6

PEX_IOVDDQ_7

PEX_IOVDDQ_8

PEX_IOVDDQ_9

PEX_IOVDDQ_10

PEX_IOVDDQ_11

PEX_IOVDDQ_12

PEX_IOVDDQ_13

PEX_PLL_HVDD

PEX_SVDD_3V3

PEX_PLLVDD

VDD33_0

VDD33_1

VDD33_2

VDD33_3

IFPAB_PLLVDD

IFPAB_RSET

IFPA_IOVDD

IFPB_IOVDD

IFPC_PLLVDD

IFPC_RSET

IFPC_IOVDD

IFPD_PLLVDD

IFPD_RSET

IFPD_IOVDD

IFPEF_PLVDD

IFPEF_RSET

IFPE_IOVDD

IFPF_IOVDD

AG19

AG21

AG22

AG24

AH21

AH25

AG13

AG15

AG16

AG18

AG25

AH15

AH18

AH26

AH27

AJ27

AK27

AL27

AM28

AN28

AH12

AG12

AG26

J8

K8

L8

M8

AH8

AJ8

AG8

AG9

AF7

AF8

AF6

AG7

AN2

AG6

AB8

AD6

AC7

AC8

CV198 0.1U_0402 _16V4Z

+PEX_PLLVDD

+VDD33

+VDD33

+IFPAB_PLLVDD

+IFPAB_IOVDD

+IFPC_PLLVDD

+IFPC_IOVDD

+IFPD_PLLVDD

+IFPD_IOVDD

+IFPEF_PLLVDD

+IFPEF_IOVDD

+IFPEF_IOVDD

110mA

50mA

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

Under GPU

OPT@

3300 mA

CV80,CV198 Under GPU
close to ball

@

CV80 0.1U_0402_16V4Z

OPT@

120mA

Design guide no define

1

1

1

1

RV95 10K_040 2_5%OPT@

1

1

RV100 10K_0402_5%OPT@

1

@

1

PEX_IOVVD/Q

Capacitor Type Footprint Population Location

1.0uF X6S 0402 4

4.7uF

10uF

22uF

PEX_PLLVDD

Capacitor Type Footprint Population Location

100nF X6S 0402 1

1.0uF

4.7uF X5R

PEX_SVDD/PLL_HVDD

Capacitor Type Footprint Population Location

0.1uF 0402 1

4.7uF 0603 2 Near GPU

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

+1.05VS_DGPU

CV59

CV60

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

1

CV76

0.1U_0402_16V4Z

CV90

0.1U_0402_16V4Z

CV67

1

CV77

2

OPT@

2

4.7U_0603_6.3V6K

Near GPU

Under GPU

Near GPU

Midway between GPU and Power Supply

Midway between GPU and Power Supply

Under GPU

Near GPU

Near GPU

10U_0603_6.3V6M

OPT@

10U_0603_6.3V6M

BLM18PG121SN1D_0603

CV89

CV88

LV12

OPT@

OPT@

1U_0402_6.3V6K

4.7U_0603_6.3V6K

LV12 stuff a 0ohm resistor instead for
N13E-GE, N13P-GT/-GS/-LP/-GV, N13M-GS,
N14P-Q1/-Q3

CV91

CV92

OPT@

OPT@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

OPT@

1

+1.05VS_DGPU

CV78

CV68

OPT@

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

Near GPU

CV81

CV82

OPT@

OPT@

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

LV12

2

1

OPT@

猁

:120ohm@100MHz, ESR=0.18ohm 0603

CV97

CV96

CV95

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

Near GPU

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sheet

Date: Sheet

Date: Sheet

1

420mA

+1.05VS_DGPU

OPT@

RV89

0_0603_5%

4.7U_0603_6.3V6K

+3VS_DGPU

16 60Frid ay, August 24, 2012

16 60Fr iday, August 24, 2012

16 60Fr iday, August 24, 2012

+3VS_DGPU

of

of

of

D

C

B

A

B

B

B

5

4

3

2

1

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

UV1F

Part 6 of 7

A2

GND_0

AA17

GND_1

D

C

B

A

5

AA18

GND_2

AA20

GND_3

AA22

GND_4

AB12

GND_5

AB14

GND_6

AB16

GND_7

AB19

GND_8

AB2

GND_9

AB21

GND_10

A33

GND_11

AB23

GND_12

AB28

GND_13

AB30

GND_14

AB32

GND_15

AB5

GND_16

AB7

GND_17

AC13

GND_18

AC15

GND_19

AC17

GND_20

AC18

GND_21

AA13

GND_22

AC20

GND_23

AC22

GND_24

AE2

GND_25

AE28

GND_26

AE30

GND_27

AE32

GND_28

AE33

GND_29

AE5

GND_30

AE7

GND_31

AH10

GND_32

AA15

GND_33

AH13

GND_34

AH16

GND_35

AH19

GND_36

AH2

GND_37

AH22

GND_38

AH24

GND_39

AH28

GND_40

AH29

GND_41

AH30

GND_42

AH32

GND_43

AH33

GND_44

AH5

GND_45

AH7

GND_46

AJ7

GND_47

AK10

GND_48

AK7

GND_49

AL12

GND_50

AL14

GND_51

AL15

GND_52

AL17

GND_53

AL18

GND_54

AL2

GND_55

AL20

GND_56

AL21

GND_57

AL23

GND_58

AL24

GND_59

AL26

GND_60

AL28

GND_61

AL30

GND_62

AL32

GND_63

AL33

GND_64

AL5

GND_65

AM13

GND_66

AM16

GND_67

AM19

GND_68

AM22

GND_69

AM25

GND_70

AN1

GND_71

AN10

GND_72

AN13

GND_73

AN16

GND_74

AN19

GND_75

AN22

GND_76

AN25

GND_77

AN30

GND_78

AN34

GND_79

AN4

GND_80

AN7

GND_81

AP2

GND_82

AP33

GND_83

B1

GND_84

B10

GND_85

B22

GND_86

B25

GND_87

B28

GND_88

B31

GND_89

B34

GND_90

B4

GND_91

B7

GND_92

C10

GND_93

C13

GND_94

C19

GND_95

C22

GND_96

C25

GND_97

C28

GND_98

C7

GND_99

N13P-GLP-A1 FCBGA 908P GPU

OPT@

GND

GND_100

GND_101

GND_102

GND_103

GND_104

GND_105

GND_106

GND_107

GND_108

GND_109

GND_110

GND_111

GND_112

GND_113

GND_114

GND_115

GND_116

GND_117

GND_118

GND_119

GND_120

GND_121

GND_122

GND_123

GND_124

GND_125

GND_126

GND_127

GND_128

GND_129

GND_130

GND_131

GND_132

GND_133

GND_134

GND_135

GND_136

GND_137

GND_138

GND_139

GND_140

GND_141

GND_142

GND_143

GND_144

GND_145

GND_146

GND_147

GND_148

GND_149

GND_150

GND_151

GND_152

GND_153

GND_154

GND_155

GND_156

GND_157

GND_158

GND_159

GND_160

GND_161

GND_162

GND_163

GND_164

GND_165

GND_166

GND_167

GND_168

GND_169

GND_170

GND_171

GND_172

GND_173

GND_174

GND_175

GND_176

GND_177

GND_178

GND_179

GND_180

GND_181

GND_182

GND_183

GND_184

GND_185

GND_186

GND_187

GND_188

GND_189

GND_190

GND_191

GND_192

GND_193

GND_194

GND_195

GND_196

GND_197

GND_198

GND_199

GND_OPT

GND_OPT

D2

D31

D33

E10

E22

E25

E5

E7

F28

F7

G10

G13

G16

G19

G2

G22

G25

G28

G3

G30

G32

G33

G5

G7

K2

K28

K30

K32

K33

K5

K7

M13

M15

M17

M18

M20

M22

N12

N14

N16

N19

N2

N21

N23

N28

N30

N32

N33

N5

N7

P13

P15

P17

P18

P20

P22

R12

R14

R16

R19

R21

R23

T13

T15

T17

T18

T2

T20

T22

AG11

T28

T32

T5

T7

U12

U14

U16

U19

U21

U23

V12

V14

V16

V19

V21

V23

W13

W15

W17

W18

W20

W22

W28

Y12

Y14

Y16

Y19

Y21

Y23

AH11

C16

W32

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

+VGA_CORE

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

UV1G

60A

AA12

AA14

AA16

AA19

AA21

AA23

AB13

AB15

AB17

AB18

AB20

AB22

AC12

AC14

AC16

AC19

AC21

AC23

M12

M14

M16

M19

M21

M23

N13

N15

N17

N18

N20

N22

2

VDD_0

VDD_1

VDD_2

VDD_3

VDD_4

VDD_5

VDD_6

VDD_7

VDD_8

VDD_9

VDD_10

VDD_11

VDD_12

VDD_13

VDD_14

VDD_15

VDD_16

VDD_17

VDD_18

VDD_19

VDD_20

VDD_21

VDD_22

VDD_23

VDD_24

VDD_25

VDD_26

VDD_27

VDD_28

VDD_29

P12

VDD_30

P14

VDD_31

P16

VDD_32

P19

VDD_33

P21

VDD_34

P23

VDD_35

R13

VDD_36

R15

VDD_37

R17

VDD_38

R18

VDD_39

R20

VDD_40

R22

VDD_41

T12

VDD_42

T14

VDD_43

T16

VDD_44

T19

VDD_45

T21

VDD_46

T23

VDD_47

U13

VDD_48

U15

VDD_49

U17

VDD_50

U18

VDD_51

U20

VDD_52

U22

VDD_53

V13

VDD_54

V15

VDD_55

N13P-GLP-A1 FCBGA 908P GPU

OPT@

Part 7 of 7

POWER

Title

Title

Title

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sheet

Date: Sheet

Date: Sheet

+VGA_CORE

V17

VDD_56

V18

VDD_57

V20

VDD_58

V22

VDD_59

W12

VDD_60

W14

VDD_61

W16

VDD_62

W19

VDD_63

W21

VDD_64

W23

VDD_65

Y13

VDD_66

Y15

VDD_67

Y17

VDD_68

Y18

VDD_69

Y20

VDD_70

Y22

VDD_71

U1

XVDD_1

U2

XVDD_2

U3

XVDD_3

U4

XVDD_4

U5

XVDD_5

U6

XVDD_6

U7

XVDD_7

U8

XVDD_8

V1

XVDD_9

V2

XVDD_10

V3

XVDD_11

V4

XVDD_12

V5

XVDD_13

V6

XVDD_14

V7

XVDD_15

V8

XVDD_16

W2

XVDD_17

W3

XVDD_18

W4

XVDD_19

W5

XVDD_20

W7

XVDD_21

W8

XVDD_22

Y1

XVDD_23

Y2

XVDD_24

Y3

XVDD_25

Y4

XVDD_26

Y5

XVDD_27

Y6

XVDD_28

Y7

XVDD_29

Y8

XVDD_30

AA1

XVDD_31

AA2

XVDD_32

AA3

XVDD_33

AA4

XVDD_34

AA5

XVDD_35

AA6

XVDD_36

AA7

XVDD_37

AA8

XVDD_38

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

1

D

C

B

A

B

B

B

17 60F riday, August 24, 2012

of

17 60Friday, August 24, 2012

of

17 60Friday, August 24, 2012

of

5

4

3

2

1

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ

DDR3

CV138

1U_0402_6.3V6K

Mode D
Address

0..31

CS0_L#

CMD0

CMD1

ODT_L

CMD2

CKE

CMD3

A14

CMD4

RST

CMD5

A9

CMD6

A7

CMD7

A2

CMD8

A0

CMD9

A4

CMD10

A1

CMD11

BA0

CMD12

WE*

CMD13

CMD14

A15

CAS*

CMD15

CMD16

CMD17

CMD18

CMD19

A13

CMD20

A8

CMD21 A8

A6

CMD22

A11

CMD23

A5

CMD24

A3

CMD25

BA2

CMD26

BA1

CMD27

A12

CMD28

A10

CMD29

RAS*

CMD30

Not Available

LOW HIGH

Command Bit Default Pull-down

ODTx 10k

10k

CKEx

RST 10k

CS* No Termination

32..63

A14

RST

A9

A7

A2

A0

A4

A1

BA0

WE*

A15

CAS*

CS0_H#

ODT_H

CKE_H

A13

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS*

D

C

B

A

VRAM DDR3 chips (1GB)

D

C

B

A

64Mx16 DDR3 *8==>1GB
128Mx16 DDR3 *8==>2GB

DQSA[7..0]<14,19>

DQSA#[7..0]<14,19>

DQMA[7..0]<14,19>

MDA[63..0]<14,19>

CMDA[30..0]<14,19>

+1.5VSDGPU

RV105

1.33K_0402_1%

OPT@

RV106

1.33K_0402_1%

OPT@

+1.5VSDGPU

RV107

1.33K_0402_1%

OPT@

+MEM_VREF1

RV108

1.33K_0402_1%

OPT@

1

1

CLKA0<14>

CLKA0#<14>

CLKA0

RV15

OPT@

160_0402_1%

2

CLKA0#

NV recommand 0720

+1.5VSDGPU

80.6_0402_1%

1

80.6_0402_1%

1

2

DQSA[7..0]

DQSA#[7..0]

DQMA[7..0]

MDA[63..0]

CMDA[30..0]

+MEM_VREF0

1

2

OPT@

1

2

OPT@

RV109

@

RV118

@

CV112

OPT@

0.1U_0402_16V4Z

UV3

X76@

M8

VREFCA

H1

CMDA9

CMDA11

CMDA8

CMDA25

CMDA10

CMDA24

CMDA22

CMDA7

CMDA21

CMDA6

CMDA29

CMDA23

CMDA28

CMDA20

CMDA4

CMDA14

CMDA12

CMDA27

CMDA26

CLKA0

CLKA0#

CMDA3

CMDA2

CMDA0

CMDA30

CMDA15

CMDA13

DQSA1

DQSA2

DQMA1

DQMA2

DQSA#1

DQSA#2

CMDA5

1

2

ZQ0

OPT@

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

N7

A11

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

M3

BA1

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4B1G1646E-HC12_FBGA96

1

1

CV119

CV118

2

2

OPT@

OPT@

0.1U_0402_16V4Z

+MEM_VREF0

CV109

0.1U_0402_16V4Z

CV110

0.1U_0402_16V4Z

2

2

1

CV111

0.01U_0402_16V7K

2

RV110

243_0402_1%

@

close to UV3 close to UV4

1

CV114

CV115

CV113

2

OPT@

0.1U_0402_16V4Z

CV116

OPT@

1U_0402_6.3V6K

CV117

OPT@

OPT@

1U_0402_6.3V6K

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

310mA

0.1U_0402_16V4Z

E3

DQL0

MDA12

swap 0329

F7

DQL1

MDA14

F2

DQL2

MDA8

F8

DQL3

MDA15

H3

DQL4

MDA9

H8

DQL5

MDA13

G2

DQL6

MDA10

H7

DQL7

MDA11

D7

DQU0

C3

MDA17

DQU1

C8

MDA21

DQU2

C2

MDA18

DQU3

A7

MDA23

DQU4

A2

MDA19

DQU5

B8

MDA22

DQU6

A3

MDA16

DQU7

MDA20

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

D2

VDDQ

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

CV121

CV120

CV122

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

OPT@

1U_0402_6.3V6K

+1.5VSDGPU

+1.5VSDGPU

CV123

OPT@

1U_0402_6.3V6K

Group1

Group2

243_0402_1%

RV111

+1.5VSDGPU

+MEM_VREF1

CMDA9

CMDA11

CMDA8

CMDA25

CMDA10

CMDA24

CMDA22

CMDA7

CMDA21

CMDA6

CMDA29

CMDA23

CMDA28

CMDA20

CMDA4

CMDA14

CMDA12

CMDA27

CMDA26

CLKA0

CLKA0#

CMDA3

CMDA2

CMDA0

CMDA30

CMDA15

CMDA13

DQSA0

DQSA3

DQMA0

DQMA3

DQSA#0

DQSA#3

CMDA5

ZQ1

1

OPT@

2

1

CV124

2

OPT@

M2

N8

K3

1

CV125

2

OPT@

0.1U_0402_16V4Z

UV4

X76@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

N7

A11

A12

T3

A13

T7

A14

M7

A15/BA3

BA0

M3

BA1

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

CAS

L3

WE

F3

DQSL

C7

DQSU

310mA

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL
SDRAM DDR3

K4B1G1646E-HC12_FBGA96

CV127

CV126

0.1U_0402_16V4Z

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

E3

DQL0

F7

DQL1

F2

MDA3

DQL2

F8

MDA4

DQL3

H3

MDA2

DQL4

H8

MDA7

DQL5

G2

MDA0

DQL6

H7

MDA5

DQL7

MDA1

MDA6

D7

DQU0

C3

DQU1

C8

MDA27

DQU2

C2

MDA29

DQU3

A7

MDA25

DQU4

A2

MDA30

DQU5

B8

MDA24

DQU6

A3

MDA28

DQU7

MDA26

MDA31

B2

VDD

D9

VDD

G7

VDD

K2

VDD

K8

VDD

N1

VDD

N9

VDD

R1

VDD

R9

VDD

A1

VDDQ

A8

VDDQ

C1

VDDQ

C9

D2

VDDQ

VDDQ

E9

VDDQ

F1

VDDQ

H2

VDDQ

H9

VDDQ

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1

VSSQ

B9

VSSQ

D1

VSSQ

D8

VSSQ

E2

VSSQ

E8

VSSQ

F9

VSSQ

G1

VSSQ

G9

VSSQ

CV129

CV128

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.5VSDGPU

+1.5VSDGPU

CMDA2

CMDA3

CMDA5

CMDA18

CMDA19

Group0

Group3

2

1

RV112 10K_0402_5%OPT@

2

1

RV115 10K_0402_5%OPT@

2

1

RV113 10K_0402_5%OPT@

1

1

CV130

CV134

2

2

OPT@

OPT@

0.1U_0402_16V4Z

RV116 10K_0402_5%OPT@

1

RV117 10K_0402_5%OPT@

CV135

OPT@

0.1U_0402_16V4Z

2

1

2

CV137

CV136

OPT@

OPT@

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2011/09/23 2012/12/31

2011/09/23 2012/12/31

2011/09/23 2012/12/31

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

SCHEMATICS, MB A8581

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

4019IE

4019IE

4019IE

Date: Sheet

Date: Sheet

2

Date: Sheet

1

B

B

B

18 60Friday, August 24, 2012

of

18 60Friday, August 24, 2012

of

18 60Friday, August 24, 2012

of