Compal LA-8381P Schematics Rev1.0

A

smd.db-x7.ru

B

C

D

E

MODEL NAME :

PCB NO :

LA-8381P

BOM P/N :

QBLB0

4319H631L01 (Samsung 1G)
4319H631L02(Samsung 2G)

1 1

4319H631L03(Hynix 1G)
4319H631L04(Hynix 2G)

Dell/Compal Confidential

Schematic Document

2 2

Specter MLK (Chief River)

Ivy Bridge(PGA) + Panther Point(standard)

DISCRETE VGA N13P-GT (optimus)

2011-10-26

3 3

Highlight the short pad for 0 ohm

Rev: X01

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-8381P

LA-8381P

LA-8381P

E

1 63Thursday, January 12, 2012

1 63Thursday, January 12, 2012

1 63Thursday, January 12, 2012

1.0

1.0

1.0

A

smd.db-x7.ru

B

C

D

E

Compal Confidential

Project Code : QBLB0

VRAM x 8
GDDR5

Page 27, 28, 29, 30

64Mb*16 x8 =1GB
128Mb*16 x8 =2GB

FFS

P.45 P.43

Fan Control

CPU XDP
Conn.

P.6

File Name : LA-8381P

Intel

1 1

Nvidia

PEGx16

N13P-GT

DP(DIS)

Page 22, 23, 24, 25, 26

LVDS

P.33

Conn.

HDMI

P.36

Conn.

CRT

P.34

Conn.

2 2

miniDP

P.35

Conn.

Mini Card (Full)
# mSATA
# WWAN
# DMC(DP or HDMI)

DMC/Daughter Board

3 3

# : Choose ONE from three.

HDMI
Re-Driver

DP
Redriver

DP
Re-Driver

(Half)
WLAN

v1.1

v1.2

v1.14a

P.38

P.36

P.35

P.37

LAN(GbE)

AR8151-BL1A

P.39

RJ45

P.39

Card ReaderMini Card

RTS5209

9 in 1
Socket

LVDS

HDMI

CRT

DP

PCI-E 2.0

P.40

P.40

Ivy Bridge
Processor

4C 45W
2C 35W

rPGA 989 Socket

100MHz 100MHz

2.7GT/s

Page 6, 7, 8, 9, 10, 11

DMI x4FDI x2

5GT/s

Intel

Panther Point

PCH

BGA 989 Balls

Page 14, 15, 16, 17, 18, 19, 20, 21

SPI

LPC Bus

Memory Bus (DDRIII)

Dual Channel

1.5V DDRIII 1333/1600 MHz

SATA
Redriver

SATA2.0

SATA3.0

PCI-E 2.0

USB2.0

USB3.0

HD Audio

SATA
Redriver

204pin DDRIII SO-DIMM x2

BANK 0, 1, 2, 3

Page 12, 13

SATA ODD Conn.

SATA HDD Conn.

P.38

MUX

P.38

Mini Card (Full)
# mSATA
# WWAN
# DMC(DP or HDMI)

Mini Card (Half)

USB 2.0 Conn. x1

( USB Charger )

Digital Camera

AlienFX/ELC

VPK

BT 4.0

USB 3.0
Combo Conn. x2

Audio Codec Malcolm-EX

P.46

P.38

P.43

P.33

P.48, 49, 50

WLAN

DMC/Daughter Board

P.44

P.45

P.45P.45

TPA6211A

SIM Card

P.38

P.38

P.42P.41

RTC conn.

Power On/Off CKT.

DC/DC Interface CKT. Power Circuit DC/DC

P.52

P.46

P.32 P.51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61

SPI ROM

64Mbit

P.14

ENE 3810

P.47

ENE KB930

Touch Pad Int.KBD

P.49

P.46

P.47

BIOS ROM

1Mbit

P.47

TI TPA6017A2

Int. Speaker

P.42

P.42

sub-woofer conn.

Audio Jack x3

( Combo Jack x1, HP x1, MIC x1)

P.41, 42

Digital MIC

P.42

P.42

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2011/02/23 2012/02/23

2011/02/23 2012/02/23

2011/02/23 2012/02/23

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

LA-8381P

LA-8381P

LA-8381P

E

2 63Thursday, January 12, 2012

2 63Thursday, January 12, 2012

2 63Thursday, January 12, 2012

1.0

1.0

1.0

A

smd.db-x7.ru

B

C

D

E

Compal Confidential

Project Code : QBLB0

ile Name : LA-8381P

F

LA-8381P M/B

1 1

Camera

40 pin

LS-8382P

80 pin

LS-8384P

INDICATOR/B

Led-Wireless

Led-CapsLock

2 2

Touch Pad

FFC

4 pin

Wire

6 pin

Lid

FFC

20 pin

TP LED/B

LS-8383P

Led x 6

4 pin4 pin

BTB conn.

WLAN WWAN/DMC

LOGO LIGHT GUIDE/B

Wire

6 pin

DMC/B

LS-8388P

Led x 6

FFC

12 pin

LS-8385P

POWER BUTTON/B

Led x 3

on/off SW

14 pin

Wire

Wire

12 pin

Wire

20 pin

LS-8381P

FPC

LCD Panel

Blue Tooth

HDD

ODD

WireWire

LS-8386P

3 3

FRONT LIGHT L/B

Led x 2 Led x 2

FRONT LIGHT R/B

LS-8387P

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

E

3 63Thursday, January 12, 2012

3 63Thursday, January 12, 2012

3 63Thursday, January 12, 2012

1.0

1.0

1.0

A

smd.db-x7.ru

B

C

D

E

+3V_PCH

+3VS

+3V_PCH

2.2K

2.2K

+3VS

DMN66D0

DMN66D0

2.2K

2.2K

PCH_SMBCLK

PCH_SMBDATA

202

200

202

200

30

32

30

32

DIMMA

DIMMB

G Sensor

XDP

WLAN

mSATA/ WWAN/ DMC

SMBUS Address [A0]

SMBUS Address [A0]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

SMBUS Address [TBD]

1 1

SMBUS Address [0x9a]

C9

H14

SMBCLK

SMBDATA

2.2K

PCH

2.2K

2.2K

2.2K

SML0CLK

SML0DATA

+3V_PCH

C8

G12

E14M16

2 2

SML1CLK

SML1DATA

76/78

F8

B8

Power
Thermal

Thermal

Thermal

TS3A225E
HP detect

VPK

+3V_GPU

DMN66D0

DMN66D0

I2CS_SCL

I2CS_SDA

+3VSDGPU

2.2K

2.2K

D9

GPU

D8

SMBUS Address [0x9E]

DMN66D0 DMN66D0

A6 B8

3 3

KBC

+3VS

EC_SMB_CK2

EC_SMB_DA2

8.2K

8.2K

+3VS

EC_SMB_CK2

EC_SMB_DA2

+3VSDGPU

2.2K

+3V_GPU

DMN66D0

DMN66D0

A8

EC_SMB_CK1

A7

EC_SMB_DA1

100 ohm

100 ohm

4

5

BATTERY
CONN

SMBUS Address [TBD]

EC_SMB_CK2_PX

EC_SMB_DA2_PX

2.2K

GPU_Thermal

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

E

4 63Thursday, January 12, 2012

4 63Thursday, January 12, 2012

4 63Thursday, January 12, 2012

1.0

1.0

1.0

A

smd.db-x7.ru

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%

100K +/- 5%
200K +/- 5%

NC

SMBUS Control Table

MINI1

SOURCE

(WLAN)

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SML0CLK PCH
PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

MEM_SMBCLK
MEM_SMBDATA

KB930

KB930

PCH

PCH

V V

Board ID Table for AD channel

AD_BID

0.168 V

0.375 V 0.503 V
.634 V

0

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

MINI2
(DMC)

V typ

AD_BID

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

BATT SODIMM

0 V 0.155 V

Thermal
Sensor 1

V

V V

V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

Thermal
Sensor 2

max

EC AD3

0x00-0x0C
0x0D-0x1C
0x1D-0x30
0x31-0x49
0x4A-0x69
0x6A-0x8E
0x8F-0xBB
0xBC-0xFF

VGA Thermal

FFS VGA

Sensor

V

V

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

XDP

V

V

PCB Revision

SSI_X00
PT_X01
ST_X02
QT_A00

Charger

V

HP detect

V

Link

PCH

USB PORT#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

JUSB2 (v3.0 Ext Right Side)

JUSB3 (v3.0 Ext Right side)

None

None

JMINI1 (WLAN)

JMINI2 (WWAN/DMC)

ELC 8051

None

Bluetooth

JUSB1 (2.0 Ext Left Side)

None

None

CAMERA

VPK

DESTINATION

PM TABLE

+5VS

+3VS

POWER STATES

1 1

State

S0 (Full ON) / M0

S5 (SOFT OFF) / M-OFF

Signal

SLP
S3#

HIGH

LOW HIGH

LOW

SLP

SLP
S4#

HIGH ON

LOW LOW LOW LOW ON

S5#

HIGH

S4
STATE#

HIGHHIGH

HIGH LOW ONS3 (Suspend to RAM) / M-OFF

LOW

SLP
M#

HIGH

LOW ONLOW LOWS4 (Suspend to DISK) / M-OFF

ALWAYS
PLANE

DESTINATIONDIFFERENTIAL

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLK

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

None

10/100/1G LAN

MINI CARD-2 WWAN

MINI CARD-1 WLAN

CARD READER

None

None

CLKOUT_PCIE7 None

CLKOUT_PEG_B

None

RUN

SUS
PLANE

ON

OFF

PLANE

ON ON

OFFOFF OFF

CLOCKS

OFFOFFON

OFFOFF

S0

S3

S5 S4/AC

S5 S4/AC don't exist

FLEX CLOCKS DESTINATION

CLKOUTFLEX0 None

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

None

None

State

power
plane

+5VALW

+3VALW

+3VLP

+3V_PCH

ON

ON OFF

ON

OFF

+1.5V

Symbol Note :

: means Digital Ground

: means Analog Ground

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

+1.8VS

+1.5VS

+1.5V_CPU_VDDQ

+VCCP = +1.05VS

+VCC_CORE

+VCC_GFXCORE_AXG

+VCCSA

+0.75VS

+3VSDGPU

+1.5VSDGPU

+VGA_CORE

ONON

ON

OFF

OFF

OFF

OFF

CLKOUT

PCI0

PCI1

PCI2

PCI3

PCI4

Compal Secret Data

Compal Secret Data

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8 None

DESTINATION

PCH_LOOPBACK

EC LPC

None

None

None

DESTINATION

10/100/1G LAN

MINI CARD-2 WWAN/DMC

MINI CARD-1 WLAN

CARD READER

None

None

None

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

LA-8381P

LA-8381P

LA-8381P

Date: Sheet of

Date: Sheet of

Date: Sheet of

DESTINATION

HDD

m-SATA

ODD

None

None

None

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

5 63Thursday, January 12, 2012

5 63Thursday, January 12, 2012

5 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

DMI_CRX_PTX_N0(16)
DMI_CRX_PTX_N1(16)
DMI_CRX_PTX_N2(16)

D D

C C

eDP_COMPIO (A18)

DMI_CRX_PTX_N3(16)

DMI_CRX_PTX_P0(16)
DMI_CRX_PTX_P1(16)
DMI_CRX_PTX_P2(16)
DMI_CRX_PTX_P3(16)

DMI_CTX_PRX_N0(16)
DMI_CTX_PRX_N1(16)
DMI_CTX_PRX_N2(16)
DMI_CTX_PRX_N3(16)

DMI_CTX_PRX_P0(16)
DMI_CTX_PRX_P1(16)
DMI_CTX_PRX_P2(16)
DMI_CTX_PRX_P3(16)

FDI_CTX_PRX_N0(16)
FDI_CTX_PRX_N1(16)
FDI_CTX_PRX_N2(16)
FDI_CTX_PRX_N3(16)
FDI_CTX_PRX_N4(16)
FDI_CTX_PRX_N5(16)
FDI_CTX_PRX_N6(16)
FDI_CTX_PRX_N7(16)

FDI_CTX_PRX_P0(16)
FDI_CTX_PRX_P1(16)
FDI_CTX_PRX_P2(16)
FDI_CTX_PRX_P3(16)
FDI_CTX_PRX_P4(16)
FDI_CTX_PRX_P5(16)
FDI_CTX_PRX_P6(16)
FDI_CTX_PRX_P7(16)

FDI_FSYNC0(16)
FDI_FSYNC1(16)

FDI_INT(16)

FDI_LSYNC0(16)
FDI_LSYNC1(16)

+VCCP

Trace length Max is 500 mils

4

1 2

RC36 24.9_0402_1%RC36 24.9_0402_1%

R_COMP place close to CPU

width 4 mils

width 12 mils

Trace length Max is 500 mils

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

+EDP_COM

VCC_IO

R_COMPeDP_ICOMPO (A17)

PEG_RCOMPO (H22)

PEG_ICOMPI (J22)

PEG_ICOMPO (J21)

JCPU1A

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

CONN@

CONN@

R_COMP place close to CPU

width 4 mils

width 12 mils

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

DMI

DMI

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

Intel(R) FDI

Intel(R) FDI

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[10]

eDP

eDP

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

3

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]

VCC_IO

R_COMP

J22
J21
H22

PEG_GTX_C_HRX_N15

K33

PEG_GTX_C_HRX_N14

M35

PEG_GTX_C_HRX_N13

L34

PEG_GTX_C_HRX_N12

J35

PEG_GTX_C_HRX_N11

J32

PEG_GTX_C_HRX_N10

H34

PEG_GTX_C_HRX_N9

H31

PEG_GTX_C_HRX_N8

G33

PEG_GTX_C_HRX_N7

G30

PEG_GTX_C_HRX_N6

F35

PEG_GTX_C_HRX_N5

E34

PEG_GTX_C_HRX_N4

E32

PEG_GTX_C_HRX_N3

D33

PEG_GTX_C_HRX_N2

D31

PEG_GTX_C_HRX_N1

B33

PEG_GTX_C_HRX_N0

C32

PEG_GTX_C_HRX_P15

J33

PEG_GTX_C_HRX_P14

L35

PEG_GTX_C_HRX_P13

K34

PEG_GTX_C_HRX_P12

H35

PEG_GTX_C_HRX_P11

H32

PEG_GTX_C_HRX_P10

G34

PEG_GTX_C_HRX_P9

G31

PEG_GTX_C_HRX_P8

F33

PEG_GTX_C_HRX_P7

F30

PEG_GTX_C_HRX_P6

E35

PEG_GTX_C_HRX_P5

E33

PEG_GTX_C_HRX_P4

F32

PEG_GTX_C_HRX_P3

D34

PEG_GTX_C_HRX_P2

E31

PEG_GTX_C_HRX_P1

C33

PEG_GTX_C_HRX_P0

B32

PEG_HTX_GRX_N15

M29

PEG_HTX_GRX_N14

M32

PEG_HTX_GRX_N13

M31

PEG_HTX_GRX_N12

L32

PEG_HTX_GRX_N11

L29

PEG_HTX_GRX_N10

K31

PEG_HTX_GRX_N9

K28

PEG_HTX_GRX_N8

J30

PEG_HTX_GRX_N7

J28

PEG_HTX_GRX_N6

H29

PEG_HTX_GRX_N5

G27

PEG_HTX_GRX_N4

E29

PEG_HTX_GRX_N3

F27

PEG_HTX_GRX_N2

D28

PEG_HTX_GRX_N1

F26

PEG_HTX_GRX_N0

E25

PEG_HTX_GRX_P15

M28

PEG_HTX_GRX_P14

M33

PEG_HTX_GRX_P13

M30

PEG_HTX_GRX_P12

L31

PEG_HTX_GRX_P11

L28

PEG_HTX_GRX_P10

K30

PEG_HTX_GRX_P9

K27

PEG_HTX_GRX_P8

J29

PEG_HTX_GRX_P7

J27

PEG_HTX_GRX_P6

H28

PEG_HTX_GRX_P5

G28

PEG_HTX_GRX_P4

E28

PEG_HTX_GRX_P3

F28

PEG_HTX_GRX_P2

D27

PEG_HTX_GRX_P1

E26

PEG_HTX_GRX_P0

D25

+VCCP

12

RC2

RC2

24.9_0402_1%

24.9_0402_1%

PEG_COMP

CC200 0.22U_0402_16V7K~DCC200 0.22U_0402_16V7K~D

1 2

CC199 0.22U_0402_16V7K~DCC199 0.22U_0402_16V7K~D

1 2

CC198 0.22U_0402_16V7K~DCC198 0.22U_0402_16V7K~D

1 2

CC197 0.22U_0402_16V7K~DCC197 0.22U_0402_16V7K~D

1 2

CC196 0.22U_0402_16V7K~DCC196 0.22U_0402_16V7K~D

1 2

CC195 0.22U_0402_16V7K~DCC195 0.22U_0402_16V7K~D

1 2

CC194 0.22U_0402_16V7K~DCC194 0.22U_0402_16V7K~D

1 2

CC193 0.22U_0402_16V7K~DCC193 0.22U_0402_16V7K~D

1 2

CC192 0.22U_0402_16V7K~DCC192 0.22U_0402_16V7K~D

1 2

CC191 0.22U_0402_16V7K~DCC191 0.22U_0402_16V7K~D

1 2

CC190 0.22U_0402_16V7K~DCC190 0.22U_0402_16V7K~D

1 2

CC189 0.22U_0402_16V7K~DCC189 0.22U_0402_16V7K~D

1 2

CC188 0.22U_0402_16V7K~DCC188 0.22U_0402_16V7K~D

1 2

CC187 0.22U_0402_16V7K~DCC187 0.22U_0402_16V7K~D

1 2

CC186 0.22U_0402_16V7K~DCC186 0.22U_0402_16V7K~D

1 2

CC185 0.22U_0402_16V7K~DCC185 0.22U_0402_16V7K~D

1 2

CC216 0.22U_0402_16V7K~DCC216 0.22U_0402_16V7K~D

1 2

CC215 0.22U_0402_16V7K~DCC215 0.22U_0402_16V7K~D

1 2

CC214 0.22U_0402_16V7K~DCC214 0.22U_0402_16V7K~D

1 2

CC213 0.22U_0402_16V7K~DCC213 0.22U_0402_16V7K~D

1 2

CC212 0.22U_0402_16V7K~DCC212 0.22U_0402_16V7K~D

1 2

CC211 0.22U_0402_16V7K~DCC211 0.22U_0402_16V7K~D

1 2

CC210 0.22U_0402_16V7K~DCC210 0.22U_0402_16V7K~D

1 2

CC209 0.22U_0402_16V7K~DCC209 0.22U_0402_16V7K~D

1 2

CC208 0.22U_0402_16V7K~DCC208 0.22U_0402_16V7K~D

1 2

CC207 0.22U_0402_16V7K~DCC207 0.22U_0402_16V7K~D

1 2

CC206 0.22U_0402_16V7K~DCC206 0.22U_0402_16V7K~D

1 2

CC205 0.22U_0402_16V7K~DCC205 0.22U_0402_16V7K~D

1 2

CC204 0.22U_0402_16V7K~DCC204 0.22U_0402_16V7K~D

1 2

CC203 0.22U_0402_16V7K~DCC203 0.22U_0402_16V7K~D

1 2

CC202 0.22U_0402_16V7K~DCC202 0.22U_0402_16V7K~D

1 2

CC201 0.22U_0402_16V7K~DCC201 0.22U_0402_16V7K~D

1 2

2

PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

PEG_GTX_C_HRX_N[0..15] (22)
PEG_GTX_C_HRX_P[0..15] (22)

PEG_HTX_C_GRX_N[0..15] (22)
PEG_HTX_C_GRX_P[0..15] (22)

PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0

PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0

1

B B

XDP Connector ( Merged CPU-PCH )

+VCCP

JXDP1

JXDP1

1

XDP_PREQ#_R(7)

XDP_PRDY#_R(7)

XDP_BPM#0(7)
XDP_BPM#1(7)

XDP_BPM#2(7)
XDP_BPM#3(7)

XDP_BPM#4(7)
XDP_BPM#5(7)

XDP_BPM#6(7)

H_CPUPWRGD(7,18)

A A

H_CPUPWRGD H_CPUPWRGD_XDP

PBTN_OUT#(16,47)

CFG0(9)

VGATE(16,59)

PCH_SMBDATA(12,13,15,38,45)

PCH_SMBCLK(12,13,15,38,45)

PCH_JTAG_TCK(14)

XDP_TCK_R(7)

5

XDP_BPM#7(7)

1 2

1 2

SHORT

SHORT

1 2

SHORT

SHORT

1 2

Item2_X02

XDP_PREQ#_R
XDP_PRDY#_R

XDP_BPM#0
XDP_BPM#1

XDP_BPM#2
XDP_BPM#3

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

RC221K_0402_5%~D @ RC221K_0402_5%~D @

RC241K_0402_5%~D @ RC241K_0402_5%~D @

SYS_PWROK_XDP

RC260_0402_5%~D

RC260_0402_5%~D

XDP_TCK1

RC300_0402_5%~D

RC300_0402_5%~D

XDP_TCK_R

The resistor
for HOOK2 should be
placed such that the
stub is very small
on CFG0 net

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

SAMTE_BSH-030-01-L-D-A

CONN@

CONN@

4

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND1

GND3

GND5

GND7

GND9

GND11

GND13

GND15

TRST#

GND17

+3V_PCH

2

Item2_X02

4

RC9 0_0402_5%~D

SHORT

RC9 0_0402_5%~D

SHORT

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

TD0

54
56

TDI

58

TMS

60

1 2

RC10 0_0402_5%~D

SHORT

RC10 0_0402_5%~D

SHORT

1 2

RC12 0_0402_5%~D

SHORT

RC12 0_0402_5%~D

SHORT

1 2

RC14 0_0402_5%~D

SHORT

RC14 0_0402_5%~D

SHORT

1 2

RC16 0_0402_5%~D

SHORT

RC16 0_0402_5%~D

SHORT

1 2

RC17 0_0402_5%~D

SHORT

RC17 0_0402_5%~D

SHORT

1 2

RC18 0_0402_5%~D

SHORT

RC18 0_0402_5%~D

SHORT

1 2

RC20 0_0402_5%~D

SHORT

RC20 0_0402_5%~D

SHORT

1 2

RC21 0_0402_5%~D

SHORT

RC21 0_0402_5%~D

SHORT

1 2

CLK_CPU_ITP
CLK_CPU_ITP#

XDP_RST#_RXDP_HOOK2
XDP_DBRESET#

XDP_TDO_C
XDP_TRST#_R
XDP_TDI_C
XDP_TMS_C

1 2

RC25 1K_0402_5%~D

RC25 1K_0402_5%~D

GPIO15

USB_OC0#
USB_OC1#

USB_OC2#

1.5VDDR_VID0

1.5VDDR_VID1
GPIO9

GPIO10
GPIO14

PLT_RST#

@

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

GPIO15 (18)

USB_OC0# (17,44)
USB_OC1# (17,44)

USB_OC2# (17,43)

1.5VDDR_VID0 (17,55)

1.5VDDR_VID1 (17,55)
GPIO9 (17)

GPIO10 (17)
GPIO14 (17)

CLK_CPU_ITP (15)
CLK_CPU_ITP# (15)

PLT_RST# (7,17,38,39,40,47)

XDP_DBRESET# (7,16)

XDP_TRST#_R (7)

Compal Secret Data

Compal Secret Data

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

XDP_TDO_C

XDP_TDI_C

XDP_TMS_C

Deciphered Date

Deciphered Date

Deciphered Date

2

+3VALW

12

RC27

RC27
1K_0402_5%~D

1K_0402_5%~D

SYS_PWROK_XDP

Item2_X02

RC28 0_0402_5%~D@RC28 0_0402_5%~D@

1 2

RC3 0_0402_5%~D@RC3 0_0402_5%~D@

1 2

RC31 0_0402_5%~D@RC31 0_0402_5%~D@

1 2

RC5 0_0402_5%~D@RC5 0_0402_5%~D@

1 2

RC29 0_0402_5%~D@RC29 0_0402_5%~D@

1 2

RC7 0_0402_5%~D@RC7 0_0402_5%~D@

1 2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+VCCP

1

1

@

@

@

@

Item2_X02

2

2

CC66

CC66

CC67

CC67

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

Place near JXDP1

PCH_JTAG_TDO (14)
XDP_TDO_R (7)

PCH_JTAG_TDI (14)
XDP_TDI_R (7)

PCH_JTAG_TMS (14)
XDP_TMS_R (7)

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

LA-8381P

LA-8381P

LA-8381P

1

6 63Thursday, January 12, 2012

6 63Thursday, January 12, 2012

6 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

4

PM, XDP, CLK, S3 Reduce, PLTRST

3

2

1

PU/PD for JTAG signals

JCPU1B

JCPU1B

D D

+VCCP

RC43

RC43

62_0402_5%

62_0402_5%

H_PROCHOT#(47)

H_PM_SYNC(16)

C C

Avoid stub in the PWRGD path
while placing resistors RC44 & RC53

B B

H_CPUPWRGD_R

12

RC4410K_0402_5%~D RC4410K_0402_5%~D

PLT_RST#(6,17,38,39,40,47)

H_CPUPWRGD(6,18)

+3VALW

1

2

CC68

CC68

0.1U_0402_16V7K~D

5

1

NC

2

A

3

0.1U_0402_16V7K~D

UC2

UC2

P

BUFO_CPU_RST# BUF_CPU_RST#

4

Y

G

SN74LVC1G07DCKR_SC70-5~D

SN74LVC1G07DCKR_SC70-5~D

RC130

RC130

@

@

1 2

0_0402_5%~D

0_0402_5%~D

1 2

+VCCP

12

RC32

RC32

H_SNB_IVB#(18)

H_PECI(18,47)

H_PROCHOT#

H_THERMTRIP#(18)

75_0402_5%

75_0402_5%

1 2

RC33 43_0402_1%RC33 43_0402_1%

T1PAD~D T1PAD~D

RC49 0_0402_5%~D

RC49 0_0402_5%~D

RC53 0_0402_5%~D

RC53 0_0402_5%~D

H_CATERR#

H_PROCHOT#_R

1 2

RC41 56_0402_5%RC41 56_0402_5%

H_THERMTRIP#

PM_SYNC_R

SHORT

SHORT

1 2

H_CPUPWRGD_R

SHORT

SHORT

1 2

VDDPWRGOOD_R

BUF_CPU_RST#

12

RC34

RC34
0_0402_5%~D@

0_0402_5%~D@

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

CONN@

CONN@

DPLL_REF_CLK

CLOCKS

CLOCKS

DDR3

DDR3

JTAG & BPM

JTAG & BPM

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]

SM_RCOMP[1]

SM_RCOMP[2]

MISC

MISC

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

BCLK

BCLK#

PRDY#

PREQ#

TRST#

DBR#

TCK
TMS

TDO

TDI

A28
A27

A16
A15

R8

SM_RCOMP0

AK1

SM_RCOMP1

A5

SM_RCOMP2

A4

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCK

AR26

XDP_TMS

AR27

XDP_TRST#

AP30

XDP_TDI

AR28

XDP_TDO

AP26

XDP_DBRESET#_R

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

CLK_CPU_DMI_R

CLK_CPU_DMI#_R

CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R

H_DRAMRST#

XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R

POWEROK

RC37 0_0402_5%~D

SHORT

RC37 0_0402_5%~D

SHORT

1 2

RC38 0_0402_5%~D

SHORT

RC38 0_0402_5%~D

SHORT

1 2

RC55 140_0402_1%RC55 140_0402_1%

1 2

RC58 25.5_0402_1%RC58 25.5_0402_1%

1 2

RC60 200_0402_1%~DRC60 200_0402_1%~D

1 2

RC121 0_0402_5%~D

SHORT

RC121 0_0402_5%~D

SHORT

1 2

RC122 0_0402_5%~D

SHORT

RC122 0_0402_5%~D

SHORT

1 2

RC123 0_0402_5%~D

SHORT

RC123 0_0402_5%~D

SHORT

1 2

RC124 0_0402_5%~D

SHORT

RC124 0_0402_5%~D

SHORT

1 2

RC125 0_0402_5%~D

SHORT

RC125 0_0402_5%~D

SHORT

1 2

RC50 0_0402_5%~D

SHORT

RC50 0_0402_5%~D

SHORT

1 2

RC51 0_0402_5%~D

SHORT

RC51 0_0402_5%~D

SHORT

1 2

RC56 0_0402_5%~D

SHORT

RC56 0_0402_5%~D

SHORT

1 2

RC59 0_0402_5%~D

SHORT

RC59 0_0402_5%~D

SHORT

1 2

RC61 0_0402_5%~D

SHORT

RC61 0_0402_5%~D

SHORT

1 2

RC62 0_0402_5%~D

SHORT

RC62 0_0402_5%~D

SHORT

1 2

RC63 0_0402_5%~D

SHORT

RC63 0_0402_5%~D

SHORT

1 2

RC64 0_0402_5%~D

SHORT

RC64 0_0402_5%~D

SHORT

1 2

RC65 0_0402_5%~D

SHORT

RC65 0_0402_5%~D

SHORT

1 2

RC66 0_0402_5%~D

SHORT

RC66 0_0402_5%~D

SHORT

1 2

RC67 0_0402_5%~D

SHORT

RC67 0_0402_5%~D

SHORT

1 2

Close to CPU

+3V_PCH +3V_PCH

Max 500mils

XDP_PRDY#_R

XDP_PREQ#_R

XDP_TCK_R
XDP_TMS_R

XDP_TRST#_R

XDP_TDI_R
XDP_TDO_R

XDP_DBRESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

CLK_CPU_DMI (15)
CLK_CPU_DMI# (15)

XDP_PRDY#_R (6)

XDP_PREQ#_R (6)

XDP_TCK_R (6)
XDP_TMS_R (6)
XDP_TRST#_R (6)

XDP_TDI_R (6)
XDP_TDO_R (6)

XDP_DBRESET# (6,16)

XDP_BPM#0 (6)
XDP_BPM#1 (6)
XDP_BPM#2 (6)
XDP_BPM#3 (6)
XDP_BPM#4 (6)
XDP_BPM#5 (6)
XDP_BPM#6 (6)
XDP_BPM#7 (6)

Item21_X01

CLK_CPU_DPLL#_R

CLK_CPU_DPLL_R

XDP_DBRESET#

XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

+1.5V_CPU_VDDQ

XDP_TMS_R

XDP_TDI_R

XDP_PREQ#

XDP_TDO

XDP_TCK_R

XDP_TRST#_R

RC42 1K_0402_5%~DRC42 1K_0402_5%~D

1 2

RC68 0_0402_5%~D@RC68 0_0402_5%~D@

1 2

RC69 0_0402_5%~D@RC69 0_0402_5%~D@

1 2

RC70 0_0402_5%~D@RC70 0_0402_5%~D@

1 2

RC71 0_0402_5%~D@RC71 0_0402_5%~D@

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

+3VS

RC4551_0402_5% RC4551_0402_5%

RC4651_0402_5% RC4651_0402_5%

RC4751_0402_5% @ RC4751_0402_5% @

RC4851_0402_5% RC4851_0402_5%

RC831K_0402_5%~D RC831K_0402_5%~D

RC821K_0402_5%~D RC821K_0402_5%~D

RC5251_0402_5% RC5251_0402_5%

RC5451_0402_5% RC5451_0402_5%

+VCCP

CFG12 (9)
CFG13 (9)
CFG14 (9)
CFG15 (9)

RC4

RC4
200_0402_1%~D

200_0402_1%~D

1 2

Item4_X03

SHORT

SHORT

For CPU S3 Power Reduce

DDR3_DRAMRST#_R

DDR3_DRAMRST#(12,13)

A A

DRAMRST_CNTRL_PCH(12,15)

DRAMRST_CNTRL_EC(47)

5

1 2

RC76 1K_0402_5%~DRC76 1K_0402_5%~D

Item4_X03

SHORT

SHORT

1 2

RC72 0_0402_5%~D

RC72 0_0402_5%~D

@

@

1 2

RC73 0_0402_5%~D

RC73 0_0402_5%~D

+1.5V

12

RC75

RC75
1K_0402_5%~D

1K_0402_5%~D

DRAMRST_CNTRL

RC74 0_0402_5%~D

RC74 0_0402_5%~D

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

4

@

@

1 2

QC2

QC2

D

D

1 3

G

G

2

1

2

S

S

4.99K_0402_1%

4.99K_0402_1%

CC69

CC69

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

H_DRAMRST# RUN_ON_CPU1.5VS3#

12

RC77

RC77

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

PM_DRAM_PWRGD(16)

PCH_PWROK(16,47)

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

1 2

RC11 0_0402_5%~D

RC11 0_0402_5%~D

RUN_ON_CPU1.5VS3#(32)

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D_PWG

2

UC1

UC1

1

5

B

VCC

2

A

4

GND3Y

74AHC1G09GW TSSOP 5P

74AHC1G09GW TSSOP 5P

12

1

RC8

RC8
200_0402_1%~D

200_0402_1%~D

2

CC65

CC65

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

VDDPWRGOOD

2

G

G

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1 2

RC57 130_0402_1%~DRC57 130_0402_1%~D

RC19

RC19
39_0402_1%

39_0402_1%

1 2

Item13_X02

13

D

D

QC1

QC1
2N7002K_SOT23-3

2N7002K_SOT23-3

S

S

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

LA-8381P

LA-8381P

LA-8381P

VDDPWRGOOD_R

1

1.0

1.0

7 63Thursday, January 12, 2012

7 63Thursday, January 12, 2012

7 63Thursday, January 12, 2012

1.0

5

smd.db-x7.ru

JCPU1C

D D

JCPU1C

4

3

JCPU1D

JCPU1D

2

1

DDR_A_D[0..63](12)

C C

B B

DDR_A_BS0(12)
DDR_A_BS1(12)
DDR_A_BS2(12)

DDR_A_CAS#(12)
DDR_A_RAS#(12)
DDR_A_WE#(12)

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AP11
AN11

AL12
AM12
AM11

AL11
AP12
AN12

AJ14
AH14

AL15
AK15

AL14
AK14

AJ15
AH15

AE10
AF10

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]

G10

SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]

M10

SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]

AG6

SA_DQ[32]

AG5

SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]

AH5

SA_DQ[36]

AH6

SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]

AH8

SA_DQ[44]

AH9

SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]

V6

SA_BS[2]

AE8

SA_CAS#

AD9

SA_RAS#

AF9

SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_CLK_DDR#0
DDR_CKE0_DIMMA

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0
M_ODT1

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 (12)
M_CLK_DDR#0 (12)
DDR_CKE0_DIMMA (12)

M_CLK_DDR1 (12)
M_CLK_DDR#1 (12)
DDR_CKE1_DIMMA (12)

DDR_CS0_DIMMA# (12)
DDR_CS1_DIMMA# (12)

M_ODT0 (12)
M_ODT1 (12)

DDR_A_DQS#[0..7] (12)

DDR_A_DQS[0..7] (12)

DDR_A_MA[0..15] (12)

DDR_B_D[0..63](13)

DDR_B_BS0(13)
DDR_B_BS1(13)
DDR_B_BS2(13)

DDR_B_CAS#(13)
DDR_B_RAS#(13)
DDR_B_WE#(13)

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AH11

AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA10

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]
SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

SB_CK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

M_CLK_DDR0

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_CLK_DDR2
M_CLK_DDR#2
DDR_CKE2_DIMMB

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT2
M_ODT3

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 (13)
M_CLK_DDR#2 (13)
DDR_CKE2_DIMMB (13)

M_CLK_DDR3 (13)
M_CLK_DDR#3 (13)
DDR_CKE3_DIMMB (13)

DDR_CS2_DIMMB# (13)
DDR_CS3_DIMMB# (13)

M_ODT2 (13)
M_ODT3 (13)

DDR_B_DQS#[0..7] (13)

DDR_B_DQS[0..7] (13)

DDR_B_MA[0..15] (13)

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

CONN@

CONN@

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

CONN@

CONN@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

PROCESSOR(3/6) DDRIII

PROCESSOR(3/6) DDRIII

LA-8381P

LA-8381P

LA-8381P

1

8 63Thursday, January 12, 2012

8 63Thursday, January 12, 2012

8 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

D D

C C

B B

CFG Straps for Processor

CFG2

12

RC781K_0402_1%~D RC781K_0402_1%~D

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation;
Lane # definition matches socket pin
map definition

CFG2

0:Lane Reversed

*

CFG4

@

12

RC811K_0402_1%~D@RC811K_0402_1%~D

Display Port Presence Strap

1 :Disabled; No Physical Display Port

*

attached to Embedded Display Port

CFG4

0 :Enabled; An external Display
Port device is connected to the
Embedded Display Port

CFG5

@

12

RC871K_0402_1%~D@RC871K_0402_1%~D

CFG6

@

12

RC861K_0402_1%~D@RC861K_0402_1%~D

PCIE Port Bifurcation Straps

11:(Default) x16 - Device 1 functions

*

1 and 2 disabled

10:x8, 8 - Device 1 function 1 enabled

CFG[6:5]

;function 2 disabled

01: Reserved - (Device 1 function 1
disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1
and 2 enabled

+VCC_GFXCORE_AXG

+VCC_CORE

RC79

@ RC79

@

RC80

@ RC80

@

1 2

RC79, RC80, RC90, RC91
Please place as close as JCPU1

RC90

RC90

50_0402_1% @

50_0402_1% @

1 2

50_0402_1%

50_0402_1%

VCC_VAL_SENSE

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

RC91

RC91

@

@

50_0402_1%

50_0402_1%

1 2

50_0402_1%

50_0402_1%

1 2

VCC_AXG_VAL_SENSE

CFG0(6)

CFG12(7)
CFG13(7)
CFG14(7)
CFG15(7)

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

JCPU1E

JCPU1E

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

KEY

CFG0
CFG1

T54PAD~D T54PAD~D

CFG2
CFG3

T59PAD~D T59PAD~D

CFG4
CFG5
CFG6
CFG7

T210PAD~D T210PAD~D

CFG8

T60PAD~D T60PAD~D

CFG9

T61PAD~D T61PAD~D

CFG10

T62PAD~D T62PAD~D

CFG11

T63PAD~D T63PAD~D

CFG12
CFG13
CFG14
CFG15
CFG16

T64PAD~D T64PAD~D

CFG17

T65PAD~D T65PAD~D

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

T19PAD~D T19PAD~D

T25PAD~D T25PAD~D
T26PAD~D T26PAD~D
T27PAD~D T27PAD~D
T28PAD~D T28PAD~D
T30PAD~D T30PAD~D
T32PAD~D T32PAD~D
T33PAD~D T33PAD~D
T34PAD~D T34PAD~D
T35PAD~D T35PAD~D
T37PAD~D T37PAD~D
T38PAD~D T38PAD~D
T39PAD~D T39PAD~D
T40PAD~D T40PAD~D
T41PAD~D T41PAD~D
T42PAD~D T42PAD~D
T43PAD~D T43PAD~D

T44PAD~D T44PAD~D
T45PAD~D T45PAD~D

T49PAD~D T49PAD~D

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

VCC_DIE_SENSE
VSS_DIE_SENSE

CFG

CFG

RESERVED

RESERVED

T36 PAD~DT36 PAD~D
T51 PAD~DT51 PAD~D

T2 PAD~DT2 PAD~D
T3 PAD~DT3 PAD~D
T4 PAD~DT4 PAD~D
T5 PAD~DT5 PAD~D

T6 PAD~DT6 PAD~D

T7 PAD~DT7 PAD~D
T8 PAD~DT8 PAD~D
T9 PAD~DT9 PAD~D

T10 PAD~DT10 PAD~D
T11 PAD~DT11 PAD~D
T12 PAD~DT12 PAD~D
T13 PAD~DT13 PAD~D

T14 PAD~DT14 PAD~D
T15 PAD~DT15 PAD~D
T16 PAD~DT16 PAD~D
T17 PAD~DT17 PAD~D
T18 PAD~DT18 PAD~D

T20 PAD~DT20 PAD~D
T21 PAD~DT21 PAD~D
T22 PAD~DT22 PAD~D
T23 PAD~DT23 PAD~D
T24 PAD~DT24 PAD~D

T29 PAD~DT29 PAD~D
T31 PAD~DT31 PAD~D

T46 PAD~DT46 PAD~D
T47 PAD~DT47 PAD~D
T48 PAD~DT48 PAD~D

T50 PAD~DT50 PAD~D

CLK_RES_ITP (15)
CLK_RES_ITP# (15)

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

CONN@

CONN@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

PROCESSOR(4/6) RSVD,CFG

PROCESSOR(4/6) RSVD,CFG

LA-8381P

LA-8381P

LA-8381P

1

9 63Thursday, January 12, 2012

9 63Thursday, January 12, 2012

9 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

POWER

QC=94A
DC=53A

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

POWER

CORE SUPPLY

CORE SUPPLY

PEG AND DDR

PEG AND DDR

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE

VSS_SENSE

+VCCP

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

H_CPU_SVIDDAT

AJ28

VIDSOUT:
Requires a pull-up to VCCIO through a pull-up resistor of 130 ±5% close to the processor, and a pull-up
to VCCIO through a pull-up resistor of 130 ±5% close to Intel MVP 7.
VIDSCLK:
Required pull-up to VCCIO through 55 ±5% close to Intel IMVP 7.

18-mil witdh,and shoulde use differential
routing with 7-milseparation.
Signals must have equal trace length
within 25 mils and are to be routed using external layer and
GND referencing (no split plane referencing). VSS_SENSE,
VCC_SENSE are to use 25-mils separation from any other
signal or rail.

+VCC_CORE

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

+VCCP

B10
A10

JCPU1F

JCPU1F

D D

C C

B B

A A

+VCC_CORE

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

CONN@

CONN@

4

8.5A

+VCCSA

Socket Cavity Socket Edge

1

2

CC167

CC167

10U_0805_25V6K~D

10U_0805_25V6K~D

+1.8VS

Item4_X03

RC109 0_0805_5%~D

SHORT

RC109 0_0805_5%~D

SHORT

1 2

VIDALERT#
Connect one end of series-resistor 43±5% close to
processor and pull-up to VCCIO through 75±5% on
the other end of the series-resistor towards Intel MVP 7.

Item3_X02

+VCCP

RC93 75_0402_5%RC93 75_0402_5%

1 2

RC94 43_0402_1%RC94 43_0402_1%

1 2

RC92 0_0402_5%~D

SHORT

RC92 0_0402_5%~D

SHORT

1 2

RC96 0_0402_5%~D

SHORT

RC96 0_0402_5%~D

SHORT

1 2

RC95 130_0402_1%~DRC95 130_0402_1%~D

1 2

RC95 close to CPU

RC97 100_0402_1%~DRC97 100_0402_1%~D

1 2

RC98 0_0402_5%~D

SHORT

RC98 0_0402_5%~D

SHORT

1 2

RC99 0_0402_5%~D

SHORT

RC99 0_0402_5%~D

SHORT

1 2

RC100 100_0402_1%~DRC100 100_0402_1%~D

1 2

RC126 10_0402_1%~DRC126 10_0402_1%~D

1 2

RC129 10_0402_1%~DRC129 10_0402_1%~D

1 2

1

2

CC172

CC172

VCC_SENSE & VSS_SENSE:
xxxxxx
100- ±1% pull-down to GND near processor

Item3_X02

1

2

CC168

CC168

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

1

1

2

2

CC170

CC170

CC169

CC169

10U_0805_25V6K~D

10U_0805_25V6K~D

Socket Edge

+1.8VS_VCCPLL

1

1

2

2

CC174

CC174

CC175

CC175

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

VR_SVID_ALRT# (59)
VR_SVID_CLK (59)
VR_SVID_DAT (59)

+VCCP

VCCSENSE (59)
VSSSENSE (59)

VCCIO_SENSE (56)
VSSIO_SENSE (56)

1

+

+

2

10U_0805_25V6K~D

10U_0805_25V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CC171

CC171
330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

1

+

+

2

CC176

CC176

330U_D2_2.5VM_R6M~D

330U_D2_2.5VM_R6M~D

3

@

@

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

J8 OPEN

+VCC_GFXCORE_AXG

1.2A

+1.8VS_VCCPLL

+1.5V_CPU_VDDQ+1.5V

J8

J8

33A

1

1

2

2

CC161

CC161

CC160

CC160

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

JCPU1G

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

TBD

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

CONN@

CONN@

2

Socket Edge

1

1

1

1

1

2

2

2

CC162

CC162

CC164

CC164

CC163

CC163

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

18-mil witdh,and shoulde use differential routing with 7-milseparation.
Signals must have equal trace length
within 25 mils and are to be routed using external layer and
GND referencing (no split plane referencing). VSS_SENSE,
VCC_SENSE are to use 25-mils separation from any other
signal or rail.

POWER

POWER

GRAPHICS

GRAPHICS

1.8V RAIL

1.8V RAIL

2

CC165

CC165

10U_0805_25V6K~D

10U_0805_25V6K~D

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

VREFMISC

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

+

+

CC166

CC166
330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

2

10U_0805_25V6K~D

10U_0805_25V6K~D

AK35

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

AK34

AL1

B4
D1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

A19

VSSAXG_SENSE

VCCSA_SENSE

Need PWR add new circuit on 1.05V(refer CRB)

VCC_AXG_SENSE
VSS_AXG_SENSE

+V_SM_VREF should
have 10 mil trace width

+V_SM_VREF

+V_DDR_REFA_R
+V_DDR_REFB_R

10mil .Spacing is 10mil

+1.5V_CPU_VDDQ

5A

+VCCSA

6A

VCCSA_VID0

RC111 0_0402_5%~D

SHORT

RC111 0_0402_5%~D

SHORT

VCCSA_VID1

H_VCCP_SEL

1 2

RC108 0_0402_5%~D

SHORT

RC108 0_0402_5%~D

SHORT

1 2

10mil .Spacing is 10mil

RC88 0_0402_5%~D

SHORT

RC88 0_0402_5%~D

SHORT

1 2

Item3_X02

+0.75VS

SHORT

SHORT

1 2

RC106 0_0402_5%~D

RC106 0_0402_5%~D

Item3_X02

1

CC250

CC250

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC_AXG_SENSE (59)
VSS_AXG_SENSE (59)

+V_SM_VREF

+V_DDR_REFA_R (12)
+V_DDR_REFB_R (12)

RC131 100_0402_5%~DRC131 100_0402_5%~D

1 2

RC132 100_0402_5%~DRC132 100_0402_5%~D

1 2

+1.5V_CPU_VDDQ +1.5V

CC182 0.1U_0402_10V7K~DCC182 0.1U_0402_10V7K~D

CC184 0.1U_0402_10V7K~DCC184 0.1U_0402_10V7K~D

CC181 0.1U_0402_10V7K~DCC181 0.1U_0402_10V7K~D

CC183 0.1U_0402_10V7K~DCC183 0.1U_0402_10V7K~D

VCCSA_SENSE (57)

H_VCCSA_VID0 (57)
H_VCCSA_VID1 (57)

VCCP_PWRCTRL (56)

1

+V_SM_VREF

12

12

12

12

+1.5V_CPU_VDDQ

12

1K_0402_5%~D

1K_0402_5%~D

@

@

RC112

RC112

12

1K_0402_5%~D

1K_0402_5%~D

@

@

RC116

RC116

+VCC_GFXCORE_AXG

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

LA-8381P

LA-8381P

LA-8381P

1

10 63Thursday, January 12, 2012

10 63Thursday, January 12, 2012

10 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

D D

JCPU1H

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

C C

B B

AP13
AP10

AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AM29
AM25
AM22
AM19
AM16
AM13
AM10

AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AJ25

VSS29
VSS30
VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AN7

VSS43

AN4

VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77

AK7

VSS78

AK4

VSS79
VSS80

4

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

3

JCPU1I

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

2

VSS

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

1

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

TYCO_2013620-3_IVYBRIDGE

CONN@

CONN@

TYCO_2013620-3_IVYBRIDGE

CONN@

CONN@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

LA-8381P

LA-8381P

LA-8381P

1

11 63Thursday, January 12, 2012

11 63Thursday, January 12, 2012

11 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

DDR_A_DQS#[0..7](8)

DDR_A_DQS[0..7](8)

DDR_A_D[0..63](8)

DDR_A_MA[0..15](8)

All VREF traces should

D D

C C

B B

have 10 mil trace width

All VREF traces should have 10 mil trace width

+V_DDR_REFA +1.5V

1

2

CD1

CD1

DDR_CKE0_DIMMA(8) DDR_CKE1_DIMMA (8)

DDR_A_BS2(8)

M_CLK_DDR0(8)
M_CLK_DDR#0(8)

DDR_A_BS0(8)

DDR_A_WE#(8)
DDR_A_CAS#(8)

DDR_CS1_DIMMA#(8)

+3VS

A A

4

+1.5V

JDIMM1

+V_DDR_REFA

DDR_A_D0
DDR_A_D1

1

DDR_A_D2

2

DDR_A_D3

CD2

0.1U_0402_16V7K~D

CD2

0.1U_0402_16V7K~D

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

1

2

CD21

CD21

1

2

CD22

CD22

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

1 2

RD6 10K_0402_5%~DRD6 10K_0402_5%~D

1 2

RD7 10K_0402_5%~DRD7 10K_0402_5%~D

+0.75VS

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

FOX_AS0A626-U2SN-7F

FOX_AS0A626-U2SN-7F

CONN@

CONN@

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

2

VSS

4

DQ4

6

DQ5

8

VSS

10
12
14

VSS

16

DQ6

18

DQ7

20

VSS

22
24
26

VSS

28

DM1

30
32

VSS

34
36
38

VSS

40
42
44

VSS

46

DM2

48

VSS

50
52
54

VSS

56
58
60

VSS

62
64
66

VSS

68
70
72

VSS

DDR_CKE1_DIMMA

74
76

VDD

78

A15

80

A14

82

VDD

84

A11

86

A7

88

VDD

90

A6

92

A4

94

VDD

96

A2

98

A0

100

VDD

102

CK1

104
106

VDD

108

BA1

110
112

VDD

114

S0#

116
118

VDD

120
122

NC

124

VDD

126
128

VSS

130
132
134

VSS

136

DM4

138

VSS

140
142
144

VSS

146
148
150

VSS

152
154
156

VSS

158
160
162

VSS

164
166
168

VSS

170

DM6

172

VSS

174
176
178

VSS

180
182
184

VSS

186
188
190

VSS

192
194
196

VSS

198
200

SDA

202

SCL

204

VTT

206
208

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#
M_ODT0

M_ODT1

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

3

M_CLK_DDR1 (8)
M_CLK_DDR#1 (8)

DDR_A_BS1 (8)
DDR_A_RAS# (8)

DDR_CS0_DIMMA# (8)
M_ODT0 (8)

M_ODT1 (8)

+VREF_CA

PCH_SMBDATA (6,13,15,38,45)

PCH_SMBCLK (6,13,15,38,45)

1

2

CD15

CD15

M1

1

2

CD16

CD16

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

+1.5V

12

RD1

RD1
1K_0402_1%~D

1K_0402_1%~D

RD10 0_0402_5%~D

RD10 0_0402_5%~D

12

RD3

RD3
1K_0402_1%~D

1K_0402_1%~D

DDR3_DRAMRST# (7,13)

+1.5V

12

RD4

RD4
1K_0402_1%~D

1K_0402_1%~D

12

RD5

RD5
1K_0402_1%~D

1K_0402_1%~D

SHORT

SHORT

1 2

Item3_X02

+V_DDR_REFA

2

+1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
vicinity of the CMD, Clock and Control signals
Those capacitors should be placed on the same side of the motherboard as the
SO-DIMM connector

Layout Note:
Place near JDIMM1

+1.5V

1

1

2

2

CD4

CD4

CD3

CD3

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.5V

1

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

RD8 0_0402_5%~D@RD8 0_0402_5%~D@

CD8

CD8

RD9 0_0402_5%~D@RD9 0_0402_5%~D@

2

CD9

CD9

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

CD18

CD18

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 2

D

D

1 3

1 2

D

D

1 3

M3

DRAMRST_CNTRL_PCH(7,15)

+V_DDR_REFA

+V_DDR_REFB

CD7

CD7

Layout Note:
Place near JDIMM1.203,204

+0.75VS

1

2

CD17

CD17

+V_DDR_REFA

DRAMRST_CNTRL_PCH

+V_DDR_REFB

DRAMRST_CNTRL_PCH

1

1

2

2

CD6

CD6

CD5

CD5

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD10

CD10

1

1

2

2

CD20

CD20

CD19

CD19

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

S

S

G

G

2

QD1

QD1

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

S

S

G

G

2

QD2

QD2

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

@

@

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD13

CD13

+V_DDR_REFA_R (10)

RD21

+V_DDR_REFB_R (10)

RD22

1

+

+

@

@

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

330U_SX_2VY~D

CD14

CD14

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD12

CD12

CD11

CD11

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

@RD21

@

1K_0402_1%~D

1K_0402_1%~D

12

@RD22

@

1K_0402_1%~D

1K_0402_1%~D

M3 Circuit (Processor Genera ted SO-DIMM VR EF_DQ)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

DDRIII DIMMA

DDRIII DIMMA

LA-8381P

LA-8381P

LA-8381P

1

12 63Thursday, January 12, 2012

12 63Thursday, January 12, 2012

12 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

+0.75VS

1

2

CD46

CD46

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

+1.5V+V_DDR_REFB

1

2

CD47

CD47

DDR_B_DQS#[0..7](8)

DDR_B_DQS[0..7](8)

DDR_B_D[0..63](8)

DDR_B_MA[0..15](8)

D D

All VREF traces should have 10 mil trace width

C C

B B

Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket

All VREF traces should
have 10 mil trace width

+3VS

1

2

CD27

CD27

DDR_CKE2_DIMMB(8)

DDR_CS3_DIMMB#(8)

12

RD19

RD19

10K_0402_5%~D

10K_0402_5%~D

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

DDR_B_BS2(8)

M_CLK_DDR2(8)
M_CLK_DDR#2(8)

DDR_B_BS0(8)

DDR_B_WE#(8)
DDR_B_CAS#(8)

+3VS

+V_DDR_REFB

1

2

CD26

CD26

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

12

10K_0402_5%~D

10K_0402_5%~D

RD20

RD20

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

JDIMM2

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

CONN@

CONN@

A A

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

+1.5V

2

DDR_B_D4

4

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

G2

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB#
M_ODT2

M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PCH_SMBDATA
PCH_SMBCLK

+0.75VS

DDR3_DRAMRST# (7,12)

DDR_CKE3_DIMMB (8)

M_CLK_DDR3 (8)
M_CLK_DDR#3 (8)

DDR_B_BS1 (8)
DDR_B_RAS# (8)

DDR_CS2_DIMMB# (8)
M_ODT2 (8)

M_ODT3 (8)

+VREF_CB

1

1

2

2

CD40

CD40

CD41

CD41

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

PCH_SMBDATA (6,12,15,38,45)

PCH_SMBCLK (6,12,15,38,45)

RD17

RD17
1K_0402_1%~D

1K_0402_1%~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

+1.5V

12

12

RD18

RD18
1K_0402_1%~D

1K_0402_1%~D

+1.5V_SUS decoupling caps be located at the VDD pins of each SO-DIMM connector in the
vicinity of the CMD, Clock and Control signals
Those capacitors should be placed on the same side of the motherboard as the
SO-DIMM connector

Layout Note:
Place near JDIMMB

+1.5V

1

1

1

1

2

2

2

2

CD29

CD29

CD28

CD28

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.5V

1

1

2

CD32

CD32

+0.75VS

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

Layout Note:
Place near JDIMMB.203,204

10U_0603_6.3V6M~D

CD33

CD33

CD34

CD34

1

1

2

2

CD43

CD43

CD42

CD42

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.5V

M1

CD31

CD31

CD30

CD30

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

1

2

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD35

CD35

CD36

CD36

CD37

CD37

1

1

2

2

CD45

CD45

CD44

CD44

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

12

RD15

RD15
1K_0402_1%~D

1K_0402_1%~D

RD11 0_0402_5%~D

SHORT

RD11 0_0402_5%~D

SHORT

1 2

12

Item3_X02

RD16

RD16
1K_0402_1%~D

1K_0402_1%~D

1

1

+

+

@

@

@

@

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD38

CD38

CD39

CD39

+V_DDR_REFB

330U_SX_2VY~D

330U_SX_2VY~D

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

DDRIII DIMMB

DDRIII DIMMB

LA-8381P

LA-8381P

LA-8381P

1

13 63Thursday, January 12, 2012

13 63Thursday, January 12, 2012

13 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

HDA_SPKR(41)

HDA_SDIN0(41)

HDA_SDO(47)

12

+RTCVCC

12

RH2

RH2
10M_0402_5%

10M_0402_5%

PCH_RTCX1

PCH_RTCX2

PCH_SPI_CLK_R

18P_0402_50V8J~D

18P_0402_50V8J~D

12

CH2

CH2

YH1

32.768KHZ_12.5PF_9H03200019

32.768KHZ_12.5PF_9H03200019

D D

+RTCVCC

+RTCVCC

C C

CH4

CH4

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 2

RH25 20K_0402_5%~DRH25 20K_0402_5%~D

1 2

RH23 20K_0402_5%~DRH23 20K_0402_5%~D

CH5

CH5

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

RH31 330K_0402_5%~DRH31 330K_0402_5%~D

RH34 330K_0402_5%~D

RH34 330K_0402_5%~D

H：Integrated VRM enable

*

L：Integrated VRM disable

+3V_PCH

12

12

@

@

@

@

@

@

200_0402_5%

200_0402_5%

200_0402_5%

200_0402_5%

RH40

RH40

RH38

RH38

RH39

RH39

12

12

RH44

RH44

RH45

RH45

RH46

RH46

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

1

2

1

2

1 2

@

@

1 2

INTVRMEN

12

200_0402_5%

200_0402_5%

12

1 2

RH53

RH53

100_0402_1%~D

100_0402_1%~D

51_0402_5%

51_0402_5%

CMOS

12

CLRP1

@CLRP1

@

SHORT PADS

SHORT PADS

PCH_RTCRST#

PCH_SRTCRST#

12

CLRP2

@CLRP2

@

SHORT PADS

SHORT PADS

ME CMOS

CLP1 & CLP2 place near DIMM

PCH_INTVRMEN

PCH_INTVRMEN

PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO

YH1

12

CH3 15P_0402_50V8J~DCH3 15P_0402_50V8J~D

far away hot spot

Item15_X03

HDA_BITCLK_AUDIO(41)

HDA_RST_AUDIO#(41)

HDA_SDOUT_AUDIO(41)

DP_PCH_HPD(35)

PCH_JTAG_TCK(6)

PCH_JTAG_TMS(6)

PCH_JTAG_TDI(6)

PCH_JTAG_TDO(6)

4

RH11

RH11

1 2

1M_0402_5%~D

1M_0402_5%~D

1 2

RH27 33_0402_5%~DRH27 33_0402_5%~D

HDA_SPKR

1 2

RH28 33_0402_5%~DRH28 33_0402_5%~D

HDA_SDIN0

Item10_X01

1 2

RH24 1K_0402_5%~DRH24 1K_0402_5%~D

1 2

RH30 33_0402_5%~DRH30 33_0402_5%~D

DP_PCH_HPD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

Item10_X01

1 2

RH255 33_0402_5%~DRH255 33_0402_5%~D

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_RST#

HDA_SDOUT

PCH_SPI_CLK

PCH_SPI_CS#

PCH_SPI_SI

PCH_SPI_SO

UH1A

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

JTAG

JTAG

RTCIHDA

RTCIHDA

SPI

SPI

3

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA

SATA

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36

E36
K36

SERIRQ

V5

AM3
AM1

SATA_PTX_DRX_N0

AP7

SATA_PTX_DRX_P0

AP5

AM10
AM8
AP11
AP10

AD7
AD5

SATA_PTX_DRX_N2

AH5

SATA_PTX_DRX_P2

AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

PCH_SATALED#

P3

PCH_GPIO21

V14

BBS_BIT0_R

P1

LPC_AD0 (47)
LPC_AD1 (47)
LPC_AD2 (47)
LPC_AD3 (47)

LPC_FRAME# (47)

SERIRQ (47)

CH91 0.01U_0402_16V7K~DCH91 0.01U_0402_16V7K~D

1 2

CH90 0.01U_0402_16V7K~DCH90 0.01U_0402_16V7K~D

1 2

CH92 0.01U_0402_16V7K~DCH92 0.01U_0402_16V7K~D

1 2

CH93 0.01U_0402_16V7K~DCH93 0.01U_0402_16V7K~D

1 2

SATA_COMP

1 2

RH41 37.4_0402_1%RH41 37.4_0402_1%

Width = 10 mil, Spacing = 20 mil
Close PCH within 500 mil

SATA3_COMP

1 2

RH43 49.9_0402_1%RH43 49.9_0402_1%

RBIAS_SATA3

1 2

RH48 750_0402_1%~DRH48 750_0402_1%~D

RH276 10K_0402_5%~DRH276 10K_0402_5%~D

+1.05VS_VCC_SATA

+1.05VS_SATA3

PCH_SATALED# (49)

+3VS

12

2

SATA_PRX_DTX_N0 (45)
SATA_PRX_DTX_P0 (45)
SATA_PTX_DRX_N0_C (45)
SATA_PTX_DRX_P0_C (45)

SATA_PRX_DTX_N1 (38)
SATA_PRX_DTX_P1 (38)
SATA_PTX_DRX_N1 (38)
SATA_PTX_DRX_P1 (38)

SATA_PRX_DTX_N2 (45)
SATA_PRX_DTX_P2 (45)
SATA_PTX_DRX_N2_RP (45)
SATA_PTX_DRX_P2_RP (45)

1

SERIRQ

PCH_GPIO21

PCH_SATALED#

HDA_SYNC

This signal has a weak internal pull-down
On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low
Needs to be pulled High for Huron River platfrom

RH29 10K_0402_5%~DRH29 10K_0402_5%~D

RH32 10K_0402_5%~DRH32 10K_0402_5%~D

RH35 10K_0402_5%~DRH35 10K_0402_5%~D

HDA_SYNC

RH52 1K_0402_5%~DRH52 1K_0402_5%~D

12

12

12

+3V_PCH

12

HDD1

mSATA

HDA_SPKR

ODD

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in effect (default)

RH37 1K_0402_5%~D@RH37 1K_0402_5%~D@

*

12

LOW=Default
HIGH=No Reboot

H=>Flash Descriptor Security will be overridden

+3V_PCH

HDA_SDOUT

RH42 1K_0402_5%~D@RH42 1K_0402_5%~D@

Low = Disabled

*

High = Enabled

12

+3VS

+3VS

+5VS

G

G

2

QH1

RH275

RH275
1M_0402_5%~D

1M_0402_5%~D

1 2

CH94

@ CH94

@

22P_0402_50V8J~D

22P_0402_50V8J~D

QH1

13

S

S

D

D

QH1 BSS138_NL_SOT23-3

QH1 BSS138_NL_SOT23-3

1 2

RH36 0_0402_5%~D@RH36 0_0402_5%~D@

RH256

@ RH256

@

12

1 2

33_0402_5%~D

33_0402_5%~D

1 2

RH54

RH54

SHORT

SHORT

1 2

RH58 0_0402_5%~D

PCH_SPI_SO PCH_SPI_SO_R

PCH_SPI_CLK_R

RH58 0_0402_5%~D

SHORT

SHORT

1 2

RH60 0_0402_5%~D

RH60 0_0402_5%~D

Item3_X02

4

PCH_SPI_WP#

+3V_PCH

3.3K_0402_5%

3.3K_0402_5%

1 2

RH57

RH57

PCH_SPI_CS#_RPCH_SPI_CS#

Item1_X03

3.3K_0402_5%

3.3K_0402_5%

SPI ROM FOR ME ( 8MByte )

SPI ROM FOR ME
( 8MByte )

U48

U48

1

/CS

2

DO

3

/WP

GND4DIO

W25Q64FVSSIG_SO8

W25Q64FVSSIG_SO8

SPI BIOS Pinout

(1)CS# (5)I/O_0
(2)I/O_1(6)CLK
(3)WP# (7)HOLD#
(4)GND (8)VCC

W25Q64

/HOLD

8

VCC

PCH_SPI_HOLD#

7

PCH_SPI_CLK_R

6

CLK

5

3

1 2

RH56 3.3K_0402_5%RH56 3.3K_0402_5%

SHORT

SHORT

1 2

RH63 0_0402_5%~D

RH63 0_0402_5%~D

Item3_X02

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

Item1_X03

+3V_PCH

1

CH6

CH6

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

PCH_SPI_SIPCH_SPI_SI_R

2

Compal Secret Data

Compal Secret Data

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

RTC Battery

+RTCBATT

+3VLP

RH259

RH259
1K_0402_5%~D

1K_0402_5%~D

1 2

W=20mils

W=20mils

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

W=20mils

2

3

DH4

DH4
BAT54CW_SOT323-3

BAT54CW_SOT323-3

1

1

CH95

CH95

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+RTCVCC

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

LA-8381P

LA-8381P

LA-8381P

1

1.0

1.0

14 63Thursday, January 12, 2012

14 63Thursday, January 12, 2012

14 63Thursday, January 12, 2012

1.0

B B

A A

HDA_SYNC_AUDIO(41)

@

@

PCH_SPI_CLK

12

CH98 10P_0402_50V8J~D

CH98 10P_0402_50V8J~D

Reserve for RF please close to UH1

@

@

HDA_SDOUT

12

CH103 10P_0402_50V8J~D

CH103 10P_0402_50V8J~D

@

@

HDA_BIT_CLK

12

CH97 10P_0402_50V8J~D

CH97 10P_0402_50V8J~D

RH33 33_0402_5%~DRH33 33_0402_5%~D

Reserve for RF please close to UH1

5

HDA_SYNC_R HDA_SYNC

1 2

Reserve for EMI please close to U48

5

smd.db-x7.ru

4

3

2

1

Place TX DC blocking caps close PCH.

PCIE_PRX_GLANTX_N3(39)

10/100/1G LAN --->

MiniDMC (Mini Card 2)--->

D D

MiniWLAN (Mini Card 1)--->

CARD_READER --->

PCIE_PRX_GLANTX_P3(39)
PCIE_PTX_GLANRX_N3(39)
PCIE_PTX_GLANRX_P3(39)

PCIE_PRX_WANTX_N2(38)
PCIE_PRX_WANTX_P2(38)
PCIE_PTX_WANRX_N2(38)
PCIE_PTX_WANRX_P2(38)

PCIE_PRX_WLANTX_N1(38)
PCIE_PRX_WLANTX_P1(38)
PCIE_PTX_WLANRX_N1(38)
PCIE_PTX_WLANRX_P1(38)

PCIE_PRX_CARDTX_N4(40)
PCIE_PRX_CARDTX_P4(40)
PCIE_PTX_CARDRX_N4(40)
PCIE_PTX_CARDRX_P4(40)

CH9 0.1U_0402_10V7K~DCH9 0.1U _0402_10V7K~D

1 2

CH14 0.1U_0402_10V7K~DCH14 0.1U_0402_10V7K~D

1 2

CH10 0.1U_0402_10V7K~DCH10 0.1U_0402_10V7K~D

1 2

CH15 0.1U_0402_10V7K~DCH15 0.1U_0402_10V7K~D

1 2

CH11 0.1U_0402_10V7K~DCH11 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~DCH16 0.1U_0402_10V7K~D

1 2

CH12 0.1U_0402_10V7K~DCH12 0.1U_0402_10V7K~D

1 2

CH13 0.1U_0402_10V7K~DCH13 0.1U_0402_10V7K~D

1 2

PCIE_PRX_GLANTX_N3
PCIE_PRX_GLANTX_P3
PCIE_PTX_GLANRX_N3_C
PCIE_PTX_GLANRX_P3_C

PCIE_PRX_WANTX_N2
PCIE_PRX_WANTX_P2
PCIE_PTX_WANRX_N2_C
PCIE_PTX_WANRX_P2_C

PCIE_PRX_WLANTX_N1
PCIE_PRX_WLANTX_P1
PCIE_PTX_WLANRX_N1_C
PCIE_PTX_WLANRX_P1_C

PCIE_PRX_CARDTX_N4
PCIE_PRX_CARDTX_P4
PCIE_PTX_CARDRX_N4_C
PCIE_PTX_CARDRX_P4_C

T81PAD~D T81PAD~D
T82PAD~D T82PAD~D

RH91 10K_0402_5%~DRH91 10K_0402_5%~D

+3V_PCH

C C

10/100/1G LAN --->

MiniDMC (Mini Card 2)--->

MiniWLAN (Mini Card 1)--->

Card Reader --->

CLK_PCIE_LAN#(39)
CLK_PCIE_LAN(39)

CLK_PCIE_MINI2#(38)
CLK_PCIE_MINI2(38)

CLK_PCIE_MINI1#(38)
CLK_PCIE_MINI1(38)

CLK_PCIE_CD#(40)
CLK_PCIE_CD(40)

+3VS

LANCLK_REQ#(39)

+3VS

MINI2CLK_REQ#(38)

+3V_PCH

MINI1CLK_REQ#(38)

+3V_PCH

CDCLK_REQ#(40)

1 2

RH93 0_0402_5%~D

SHORT

RH93 0_0402_5%~D

SHORT
SHORT

SHORT

SHORT

SHORT
SHORT

SHORT

SHORT

SHORT
SHORT

SHORT

SHORT

SHORT
SHORT

SHORT

12
12
12

12
12
12

12
12
12

12
12
12

RH94 0_0402_5%~D

RH94 0_0402_5%~D
RH95 10K_0402_5%~DRH95 10K_0402_5%~D

RH96 0_0402_5%~D

RH96 0_0402_5%~D
RH97 0_0402_5%~D

RH97 0_0402_5%~D
RH100 10K_0402_5%~DRH100 10K_0402_5%~D

RH101 0_0402_5%~D

RH101 0_0402_5%~D
RH102 0_0402_5%~D

RH102 0_0402_5%~D
RH103 10K_0402_5%~DRH103 10K_0402_5%~D

RH104 0_0402_5%~D

RH104 0_0402_5%~D
RH106 0_0402_5%~D

RH106 0_0402_5%~D
RH107 10K_0402_5%~DRH107 10K_0402_5%~D

Item3_X02

RH110 10K_0402_5%~DRH110 10K_0402_5%~D

+3V_PCH

+3V_PCH

B B

CLK_CPU_ITP#(6)
CLK_CPU_ITP(6)

CLK_RES_ITP#(9)
CLK_RES_ITP(9)

+3V_PCH

+3V_PCH

CLK_CPU_ITP#
CLK_CPU_ITP

1 2

RH112 10K_0402_5%~DRH112 10K_0402_5%~D

1 2

RH116 10K_0402_5%~DRH116 10K_0402_5%~D

1 2

RH118 10K_0402_5%~DRH118 10K_0402_5%~D

1 2

RH119 0_0402_5%~D

SHORT

RH119 0_0402_5%~D

SHORT
SHORT

SHORT

12
12

12
12

RH120 0_0402_5%~D

RH120 0_0402_5%~D

RH121 0_0402_5%~D@RH 121 0_0402_5%~D@
RH122 0_0402_5%~D@RH 122 0_0402_5%~D@

GPIO73

PCIE_LAN#
PCIE_LAN

LANCLK_REQ#

PCIE_MINI2#
PCIE_MINI2

MINI2CLK_REQ#

PCIE_MINI1#
PCIE_MINI1

MINI1CLK_REQ#

PCIE_CD#
PCIE_CD

CDCLK_REQ#

GPIO56

GPIO45

GPIO46

CLK_BCLK_ITP#
CLK_BCLK_ITP

UH1B

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

SMBUSController

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

PCI-E*

CLOCKS

CLOCKS

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

PCH_LID_SW_IN#

E12

SMBCLK

H14

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

GPIO74 PCH_LID_SW_IN#

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

No support iAMT

P10

PEG_A_CLKRQ#

M10

CLK_PEG_VGA#

AB37

CLK_PEG_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12
AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

Width = 10 mil, Spacing = 20 mil
C

GPIO64

K43

DMC_PCH_DET#

F47

BT_DET#

H47

CAM_DET#

K49

Item3_X02

Item3_X02

1 2

RH68 0_0402_5%~D

RH68 0_0402_5%~D

1 2

RH71 0_0402_5%~D

RH71 0_0402_5%~D

MEMORY

+3V_PCH

1 2

RH113 90.9_0402_1%RH113 90.9_0402_1%

lose PCH within 500 mil

Item6_X01

EC_LID_OUT#

SHORT

SHORT

LID_SW_IN#

@

@

DRAMRST_CNTRL_PCH (7,12)

RH141

RH141
10K_0402_5%~D

10K_0402_5%~D

1 2

CLK_PEG_VGA# (22)
CLK_PEG_VGA (22)

CLK_CPU_DMI# (7)
CLK_CPU_DMI (7)

T53 PAD~DT53 PAD~D
T52 PAD~DT52 PAD~D

CLK_PCI_LPBACK (17)

+1.05VS_VCCDIFFCLKN

DMC_PCH_DET# (38)

BT_DET# (38)

CAM_DET# (33)

PEG_A_CLKRQ# (22)

EC_LID_OUT# (47)

LID_SW_IN# (47,48,49)

+3VS

+3VS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

LID_SW_IN#

DRAMRST_CNTRL_PCH

GPIO74

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

If use extenal CLK gen, please
place close to CLK gen
else, please place close to PCH

CLK_PCH_14M

Reserve for EMI please close to UH1

CLK_PCI_LPBACK

Reserve for EMI please close to UH1

XTAL25_IN

XTAL25_OUT

CH24

CH24

15P_0402_50V8J~D

15P_0402_50V8J~D

RH76 10K_0402_5%~DRH76 10K_0402_5%~D
RH78 10K_0402_5%~DRH78 10K_0402_5%~D
RH77 10K_0402_5%~DRH77 10K_0402_5%~D
RH79 10K_0402_5%~DRH79 10K_0402_5%~D
RH80 10K_0402_5%~DRH80 10K_0402_5%~D
RH81 10K_0402_5%~DRH81 10K_0402_5%~D
RH82 10K_0402_5%~DRH82 10K_0402_5%~D
RH83 10K_0402_5%~DRH83 10K_0402_5%~D
RH84 10K_0402_5%~DRH84 10K_0402_5%~D

@

@

RH86 33_0402_5%~D

RH86 33_0402_5%~D

@

@

RH89 33_0402_5%~D

RH89 33_0402_5%~D

1 2

RH117 1M_0402_5%~DRH117 1M_0402_5%~D

YH2

YH2

1

IN

2

GND

1

25MHZ_12PF_X3G025000DC1H~D

25MHZ_12PF_X3G025000DC1H~D

2

Item27_X01

Item6_X01

GPIO64

DMC_PCH_DET#

BT_DET#

CAM_DET#

1 2

RH67 2.2K_0402_5%~DRH67 2.2K_0402_5%~D

1 2

RH69 2.2K_0402_5%~DRH69 2.2K_0402_5%~D

1 2

RH70 2.2K_0402_5%~DRH70 2.2K_0402_5%~D

1 2

RH72 2.2K_0402_5%~DRH72 2.2K_0402_5%~D

1 2

RH73 2.2K_0402_5%~DRH73 2.2K_0402_5%~D

1 2

RH74 2.2K_0402_5%~DRH74 2.2K_0402_5%~D

@

@

1 2

R1790 10K_0402_5%~D

R1790 10K_0402_5%~D

1 2

RH75 1K_0402_5%~DRH75 1K_0402_5%~D

1 2

R1793 10K_0402_5%~DR1793 10K_0402_5%~D

1 2

RH280 10K_0402_5%~DRH280 10K_0402_5%~D

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

@

@

CH21

CH21

1 2

12

@

@

CH22

CH22

1 2

12

3

OUT

4

GND

1 2

R1791 100K_0402_5%~DR1791 100K_0402_5%~D

1 2

RH109 10K_0402_5%~DRH109 10K_0402_5%~D

1 2

RH108 10K_0402_5%~DRH108 10K_0402_5%~D

1 2

RH166 10K_0402_5%~DRH166 10K_0402_5%~D

22P_0402_50V8J~D

22P_0402_50V8J~D

22P_0402_50V8J~D

22P_0402_50V8J~D

1

CH23

CH23
15P_0402_50V8J~D

15P_0402_50V8J~D

2

+3V_PCH

+3VS

+3VS

RH99

RH98

RH98

2.2K_0402_5%~D

2.2K_0402_5%~D

SML1CLK

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

A A

5

4

SML1DATA

2

6 1

QH4A

QH4A

5

3

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

QH4B

QH4B

4

3

EC_SMB_DA2 (22,23,41,43,46,47,53)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

SMBCLK

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

SMBDATA

Compal Secret Data

Compal Secret Data

Compal Secret Data

QH3A

QH3A

6 1

@

1 2

RH1050_0402_5%~D@RH1050_0402_5%~D

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

Deciphered Date

Deciphered Date

Deciphered Date

2

2

QH3B

QH3B

3

@

1 2

RH1110_0402_5%~D@RH1110_0402_5%~D

5

4

RH99

2.2K_0402_5%~D

2.2K_0402_5%~D

1 2

1 2

PCH_SMBCLK (6,12,13,38,45)EC_SMB_CK2 (22,23,41,43,46,47,53)

PCH_SMBDATA (6,12,13,38,45)

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

LA-8381P

LA-8381P

LA-8381P

1

15 63Thursday, January 12, 2012

15 63Thursday, January 12, 2012

15 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

UH1C

DMI_CTX_PRX_N0(6)
DMI_CTX_PRX_N1(6)
DMI_CTX_PRX_N2(6)
DMI_CTX_PRX_N3(6)

DMI_CTX_PRX_P0(6)
DMI_CTX_PRX_P1(6)
DMI_CTX_PRX_P2(6)
DMI_CTX_PRX_P3(6)

DMI_CRX_PTX_N0(6)

D D

Width = 4 mil, Spacing = 20 mil
Close PCH within 500 mil

XDP_DBRESET#(6,7)

PCH_PWROK(7,47)

PCH_APWROK(47)

C C

B B

PM_DRAM_PWRGD(7)

PCH_RSMRST#(47)

SUSPWRDNACK(47)

PBTN_OUT#(6,47)

AC_PRESENT(47)

SYS_PWROK
This signal should be used on the platform to indicate
that the processor VR power is good and therefore
it can be connected to the same source as PWROK on PCH.

GPIO72

RI#

WAKE#

AC_PRESENT

SUSPWRDNACK

Item20_X01

PCH_RSMRST#

SYS_PWROK

DMI_CRX_PTX_N1(6)
DMI_CRX_PTX_N2(6)
DMI_CRX_PTX_N3(6)

DMI_CRX_PTX_P0(6)
DMI_CRX_PTX_P1(6)
DMI_CRX_PTX_P2(6)
DMI_CRX_PTX_P3(6)

+1.05VS

XDP_DBRESET#

VGATE(6,59)

PCH_PWROK

PM_DRAM_PWRGD

RH143 10K_0402_5%~DRH143 10K_0402_5%~D

1 2

RH145 10K_0402_5%~DRH145 10K_0402_5%~D

1 2

RH146 10K_0402_5%~DRH146 10K_0402_5%~D

1 2

RH150 10K_0402_5%~D@RH 150 10K_0402_5%~D@

1 2

RH154 10K_0402_5%~D@RH 154 10K_0402_5%~D@

1 2

RH159 10K_0402_5%~DRH159 10K_0402_5%~D

1 2

RH272 10K_0402_5%~D@RH 272 10K_0402_5%~D@

1 2

RH124 49.9_0402_1%RH124 49.9_0402_1%

RH125 750_0402_1%~DRH125 750_0402_1%~D

4mil width and place
within 500mil of the PCH

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP

1 2

RBIAS_CPY

1 2

Deep Sleep not implemented
SUSACK# unconnected

SYS_PWROK

SHORT

SHORT

1 2

RH273 0_0402_5%~D

RH273 0_0402_5%~D

RH130 0_0402_5%~D

RH130 0_0402_5%~D

RH131 0_0402_5%~D

RH131 0_0402_5%~D

RH133 0_0402_5%~D

RH133 0_0402_5%~D

SUSPWRDNACK

RH135 0_0402_5%~D

RH135 0_0402_5%~D

RH137 0_0402_5%~D

RH137 0_0402_5%~D

Item3_X02

SHORT

SHORT

SHORT

SHORT

SHORT

SHORT

SHORT

SHORT

SHORT

SHORT

+3V_PCH

PM_PWROK_R

12

12

PCH_RSMRST#_R

12

PBTN_OUT#_R

12

AC_PRESENT_R

12

GPIO72

RI#

UH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

APWROK
This is a input signal to the PCH from power monitoring circuit to indicate that all Active
Sleep Well (ASW) rails, i.e. Intel ME sub-system and LAN power rails are stable on the
platform. Connect to ASW power rail monitoring circuit on motherboard. For platform
not supporting Intel AMT it can be connected to PWROK. The ASW power must be
stable for at least 1ms before platform logic asserts APWROK.

DPWROK
This is an input signal to the PCH from platform power monitoring logic to indicate that
all power rails associated with the PCH Deep Sx well (DSW) are valid and stable.
Connect to VccDSW3_3 power rail monitoring circuit on mother board for platforms
that support Deep Sx state. This signal can be tied to RSMRST# for platforms that do
not support the Deep Sx state. The DSW rails must be stable for at least 10ms before
DPWROK is asserted to PCH.

4

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

System Power Management

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

DSWODVREN

DSWODVREN

FDI_CTX_PRX_N1

AY14

FDI_CTX_PRX_N2

BE14

FDI_CTX_PRX_N3

BH13

FDI_CTX_PRX_N4

BC12

FDI_CTX_PRX_N5

BJ12

FDI_CTX_PRX_N6

BG10

FDI_CTX_PRX_N7

BG9

FDI_CTX_PRX_P0

BG14

FDI_CTX_PRX_P1

BB14

FDI_CTX_PRX_P2

BF14

FDI_CTX_PRX_P3

BG13

FDI_CTX_PRX_P4

BE12

FDI_CTX_PRX_P5

BG12

FDI_CTX_PRX_P6

BJ10

FDI_CTX_PRX_P7

BH9

FDI_INT

AW16

FDI_FSYNC0

AV12

FDI_FSYNC1

BC10

FDI_LSYNC0

AV14

FDI_LSYNC1

BB10

DSWODVREN

A18

E22

WAKE#

B9

PM_CLKRUN#

N3

SUS_STAT#

G8

SUSCLK

N14

PM_SLP_S5#

D10

PM_SLP_S4#

H4

PM_SLP_S3#

F4

G10

G16

H_PM_SYNC

AP14

K14

RH147 330K_0402_5%~DRH147 330K_0402_5%~D

RH151 330K_0402_5%~D@RH151 330K_0402_5%~D@

DSWODVREN - On Die DSW VR Enable

H：Enable

*

L：Disable

FDI_CTX_PRX_N0

BJ14

FDI_CTX_PRX_N0 (6)
FDI_CTX_PRX_N1 (6)
FDI_CTX_PRX_N2 (6)
FDI_CTX_PRX_N3 (6)
FDI_CTX_PRX_N4 (6)
FDI_CTX_PRX_N5 (6)
FDI_CTX_PRX_N6 (6)
FDI_CTX_PRX_N7 (6)

FDI_CTX_PRX_P0 (6)
FDI_CTX_PRX_P1 (6)
FDI_CTX_PRX_P2 (6)
FDI_CTX_PRX_P3 (6)
FDI_CTX_PRX_P4 (6)
FDI_CTX_PRX_P5 (6)
FDI_CTX_PRX_P6 (6)
FDI_CTX_PRX_P7 (6)

FDI_INT (6)

FDI_FSYNC0 (6)

FDI_FSYNC1 (6)

FDI_LSYNC0 (6)

FDI_LSYNC1 (6)

Item3_X02

PCH_RSMRST#_RPCH_DPWROK

SHORT

SHORT

1 2

RH126 0_0402_5%~D

RH126 0_0402_5%~D

SHORT

SHORT

12

RH128 0_0402_5%~D

RH128 0_0402_5%~D

T76 PAD~DT76 PAD~D

SHORT

SHORT

12

RH132 0_0402_5%~D

RH132 0_0402_5%~D

If not using integrated
LAN,signal may be left as NC.

12

12

PM_SLP_S5# (47,48)

PM_SLP_S4# (47)

PM_SLP_S3# (47,48)

H_PM_SYNC (7)

+RTCVCC

3

PCIE_WAKE# (38,39,47)

SUSCLK_R (47)

PCH_CRT_HSYNC(34)
PCH_CRT_VSYNC(34)

IGPU_BKLT_EN(47)

PCH_ENVDD(33,47)

PCH_INV_PWM(33)

PCH_LCD_CLK(33)

PCH_LCD_DATA(33)

RH144 2.37K_0402_1%~DRH144 2.37K_0402_1%~D

PCH_CRT_DDC_CLK(34)
PCH_CRT_DDC_DATA(34)

1 2

PCH_TXCLK-(33)
PCH_TXCLK+(33)

PCH_TXOUT0-(33)
PCH_TXOUT1-(33)
PCH_TXOUT2-(33)

PCH_TXOUT0+(33)
PCH_TXOUT1+(33)
PCH_TXOUT2+(33)

PCH_TZCLK-(33)
PCH_TZCLK+(33)

PCH_TZOUT0-(33)
PCH_TZOUT1-(33)
PCH_TZOUT2-(33)

PCH_TZOUT0+(33)
PCH_TZOUT1+(33)
PCH_TZOUT2+(33)

PCH_CRT_B(34)
PCH_CRT_G(34)
PCH_CRT_R(34)

T203PAD~D T203PAD~D

RH136 33_0402_5%~DRH136 33_0402_5%~D

1 2

RH138 33_0402_5%~DRH138 33_0402_5%~D

1 2

RH140

RH140

1K_0402_0.5%~D

1K_0402_0.5%~D

CRT_HSYNC and CRT_VSYNC resistor
33 ohm for Direct Connect
20 ohm for Dock Support
20 ohm for Switchable Graphics Device Down Topology
10 ohm for Switchable Graphics Dock Support

Put close PCH 500 mil

SUSCLK

Reserve for RF please close to UH1

IGPU_BKLT_EN

PCH_ENVDD

PCH_LCD_CLK
PCH_LCD_DATA

CTRL_CLK
CTRL_DATA

LVDS_IBG

PCH_TXCLK­PCH_TXCLK+

PCH_TXOUT0­PCH_TXOUT1­PCH_TXOUT2-

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

PCH_TZCLK­PCH_TZCLK+

PCH_TZOUT0­PCH_TZOUT1­PCH_TZOUT2-

PCH_TZOUT0+
PCH_TZOUT1+
PCH_TZOUT2+

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

PCH_CRT_DDC_CLK
PCH_CRT_DDC_DATA

HSYNC
VSYNC

CRT_IREF

12

PCH_CRT_R

RH156 150_0402_1%~DRH156 150_0402_1%~D
CH106 10P_0402_50V8J~D@ CH106 10P_0402_50V8J~D@

PCH_CRT_G

RH153 150_0402_1%~DRH153 150_0402_1%~D
CH107 10P_0402_50V8J~D@ CH107 10P_0402_50V8J~D@

PCH_CRT_B

RH149 150_0402_1%~DRH149 150_0402_1%~D
CH108 10P_0402_50V8J~D@ CH108 10P_0402_50V8J~D@

@

@

12

CH102 10P_0402_50V8J~D

CH102 10P_0402_50V8J~D

2

UH1D

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

12

12

12

12

12

12

1

SDVO_STALLN
SDVO_STALLP

SDVO_INTN

SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

PCH_HDMI_CLK
PCH_HDMI_DAT

PCH_HDMI_HPD

PCH_HDMI_TXD0­PCH_HDMI_TXD0+
PCH_HDMI_TXD1­PCH_HDMI_TXD1+
PCH_HDMI_TXD2­PCH_HDMI_TXD2+
PCH_HDMI_TXC­PCH_HDMI_TXC+

PCH_DPD_CLK
PCH_DPD_DAT

PCH_DPD_AUXN
PCH_DPD_AUXP
PCH_DMC_HPD

PCH_DPD_N0
PCH_DPD_P0
PCH_DPD_N1
PCH_DPD_P1
PCH_DPD_N2
PCH_DPD_P2
PCH_DPD_N3
PCH_DPD_P3

IGPU_BKLT_EN

PCH_ENVDD

PCH_DPD_CLK (37)
PCH_DPD_DAT (37)

PCH_LCD_CLK

PCH_LCD_DATA

CTRL_CLK

CTRL_DATA

PCH_CRT_DDC_CLK

PCH_CRT_DDC_DATA

PM_CLKRUN#

PCH_HDMI_CLK (36)

PCH_HDMI_DAT (36)

PCH_HDMI_HPD (36)

PCH_HDMI_TXD0- (36)
PCH_HDMI_TXD0+ (36)
PCH_HDMI_TXD1- (36)
PCH_HDMI_TXD1+ (36)
PCH_HDMI_TXD2- (36)
PCH_HDMI_TXD2+ (36)
PCH_HDMI_TXC- (36)
PCH_HDMI_TXC+ (36)

PCH_DPD_AUXN (37)
PCH_DPD_AUXP (37)

PCH_DMC_HPD (37)

PCH_DPD_N0 (37)
PCH_DPD_P0 (37)
PCH_DPD_N1 (37)
PCH_DPD_P1 (37)
PCH_DPD_N2 (37)
PCH_DPD_P2 (37)
PCH_DPD_N3 (37)
PCH_DPD_P3 (37)

DMC
(DP & HDMI)

+3VS

12

RH1482.2K_0402_5%~D RH1482.2K_0402_5%~D

12

RH1522.2K_0402_5%~D RH1522.2K_0402_5%~D

12

RH1552.2K_0402_5%~D RH1552.2K_0402_5%~D

12

RH1572.2K_0402_5%~D RH1572.2K_0402_5%~D

12

RH1842.2K_0402_5%~D RH1842.2K_0402_5%~D

12

RH1852.2K_0402_5%~D RH1852.2K_0402_5%~D

12

RH2488.2K_0402_5%~D RH2488.2K_0402_5%~D

12

RH123100K_0402_5%~D RH123100K_0402_5%~D

12

RH158100K_0402_5%~D RH158100K_0402_5%~D

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

mDP

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

CRT

DMC

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-8381P

LA-8381P

LA-8381P

1

16 63Thursday, January 12, 2012

16 63Thursday, January 12, 2012

16 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

D D

USB/USB3 Port Mapping

USB2[0]

USB2[1]

USB2[2]

USB2[3]

+3VS

C C

USB3[1]

USB3[2]

USB3[3]

USB3[4]

USB3RN0(44)
USB3RN1(44)

USB3RP0(44)
USB3RP1(44)

USB3TN0(44)
USB3TN1(44)

USB3TP0(44)
USB3TP1(44)

Item13_X01

CLK_PCI1

WL_OFF#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQC#

DMC_RADIO_OFF#
GPIO52
DGPU_PWR_EN#
FFS_INT1

PCI_PIRQA#
DGPU_HOLD_RST#
ODD_DA#

CLK_PCI_LPBACK(15)

CLK_PCI_LPC(47)

Item1_X01

CLK_PCI_LPBACK
CLK_PCI_LPC

DGPU_PWR_EN#(31)

DMC_RADIO_OFF#(38)

WL_OFF#(38)

FFS_INT1(45)

ODD_DA#(45)

DP_CBL_DET(35)

CH109 10P_0402_50V8J~D

CH109 10P_0402_50V8J~D

RH164 22_0402_5%~DRH164 22_0402_5%~D
RH165 22_0402_5%~DRH165 22_0402_5%~D

RH284 8.2K_0402_5%~DRH284 8.2K_0402_5%~D

1 2

RH285 8.2K_0402_5%~DRH285 8.2K_0402_5%~D

1 2

RH286 8.2K_0402_5%~DRH286 8.2K_0402_5%~D

1 2

RH287 8.2K_0402_5%~DRH287 8.2K_0402_5%~D

1 2

RH289 8.2K_0402_5%~DRH289 8.2K_0402_5%~D

1 2

RH291 8.2K_0402_5%~DRH291 8.2K_0402_5%~D

1 2

RH293 8.2K_0402_5%~DRH293 8.2K_0402_5%~D

1 2

RH295 8.2K_0402_5%~DRH295 8.2K_0402_5%~D

1 2

RH296 8.2K_0402_5%~DRH296 8.2K_0402_5%~D

1 2

RH297 8.2K_0402_5%~DRH297 8.2K_0402_5%~D

1 2

RH299 8.2K_0402_5%~DRH299 8.2K_0402_5%~D

1 2

B B

@

@

12

CH99 10P_0402_50V8J~D

CH99 10P_0402_50V8J~D

Reserve for RF please close to UH1

@

@

1 2

T123PAD~D T123PAD~D

12

12

4

DGPU_HOLD_RST#
GPIO52
DGPU_PWR_EN#

DMC_RADIO_OFF#

WL_OFF#

FFS_INT1
ODD_DA#
DP_CBL_DET

PCH_PLTRST#

T165PAD~D T165PAD~D
T166PAD~D T166PAD~D
T204PAD~D T204PAD~D

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4

UH1E

UH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3TP1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

USB

USB

RSVD23
RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

RSVD

RSVD

USB30

USB30

PCI

PCI

Intel Anti-Theft Techonlogy

AV1
BB1
BA3

NV_ALE

BB5
BB3
BB7
BE8
BD4
BF6

NV_ALE

AV5
AV10

AT8

AY5
BA2

AT12
BF3

USB20_N0

C24

USB20_P0

A24

USB20_N1

C25

USB20_P1

B25
C26
A26

USB20_N3

K28

USB20_P3

H28

USB20_N4

E28

USB20_P4

D28

USB20_N5

C28

USB20_P5

A28

USB20_N6

C29

USB20_P6

B29
N28
M28

USB20_N8

L30

USB20_P8

K30
G30
E30
C30
A30
L32
K32

USB20_N12

G32

USB20_P12

E32

USB20_N13

C32

USB20_P13

A32

USBRBIAS

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

Net USB_BIAS route impedacnes should be 50-ohm
and length less than 500-mil spacing is 15-mil.

USB_OC0#
USB_OC1#
USB_OC2#

1.5VDDR_VID0

1.5VDDR_VID1
GPIO9
GPIO10
GPIO14

High=Endabled

Low=Disable(floating)

RH160 1K_0402_5%~D@RH160 1K_0402_5%~D@

1 2

USB20_N0 (44)
USB20_P0 (44)
USB20_N1 (44)
USB20_P1 (44)

USB20_N3 (43)
USB20_P3 (43)
USB20_N4 (38)
USB20_P4 (38)
USB20_N5 (38)
USB20_P5 (38)
USB20_N6 (48)
USB20_P6 (48)

USB20_N8 (38)
USB20_P8 (38)

Item12_X01

USB20_N12 (33)
USB20_P12 (33)
USB20_N13 (46)
USB20_P13 (46)

Within 500 mils

1 2

RH163 22.6_0402_1%RH163 22.6_0402_1%

PLTRST_VGA#(22)

*

+1.8VS

USB3.0

USB3.0

Item12_X01

USB2.0

Mini Card(WLAN)

Mini Card(DMC/WWAN)

ELC LED

Bluetooth

Camera

VPK

USB_OC0# (6,44)
USB_OC1# (6,44)
USB_OC2# (6,43)

1.5VDDR_VID0 (6,55)

1.5VDDR_VID1 (6,55)
GPIO9 (6)

GPIO10 (6)
GPIO14 (6)

RH170 100_0402_5%~DRH170 100_0402_5%~D

Item12_X01

12

2

4

Y

12

RH172

RH172
100K_0402_5%~D

100K_0402_5%~D

1 2

RH254 0_0402_5%~D@ RH254 0_0402_5%~D@

+3VSDGPU

Item16_X01

5

UH6

UH6

2

P

B

DGPU_HOLD_RST#

1

A

G

SN74AHC1G08DCKR_SC70-5

SN74AHC1G08DCKR_SC70-5

3

@

@

1 2

USB_OC2#
USB_OC0#
GPIO10
GPIO9

USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1
GPIO14

1 2

RH265 0_0402_5%~D

RH265 0_0402_5%~D

1 2

RH266 0_0402_5%~D

RH266 0_0402_5%~D

Item3_X02

RH179

RH179
10K_0402_5%~D

10K_0402_5%~D

RH288 10K_0402_5%~DRH288 10K_0402_5%~D

1 2

RH290 10K_0402_5%~DRH290 10K_0402_5%~D

1 2

RH292 10K_0402_5%~DRH292 10K_0402_5%~D

1 2

RH294 10K_0402_5%~DRH294 10K_0402_5%~D

1 2

Item13_X01

RH298 10K_0402_5%~DRH298 10K_0402_5%~D

1 2

RH300 10K_0402_5%~DRH300 10K_0402_5%~D

1 2

RH301 10K_0402_5%~DRH301 10K_0402_5%~D

1 2

RH302 10K_0402_5%~DRH302 10K_0402_5%~D

1 2

DGPU_PWROK

@

@

PCH_PLTRST#

SHORT

SHORT

1

+3V_PCH

DGPU_PWROK (18,31,35,57)

+3VS

@

@

RH169

RH169

10K_0402_5%~D

10K_0402_5%~D

Check

1 2

12

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

PLT_RST#(6,7,38, 39,40,47)

A A

5

4

1 2

RH168 0_0402_5%~D

RH168 0_0402_5%~D

UH5

UH5

4

SN74AHC1G08DCKR_SC70-5

SN74AHC1G08DCKR_SC70-5

RH171

RH171
100K_0402_5%~D

100K_0402_5%~D

Issued Date

Issued Date

Issued Date

@

@

+3VS

5

IN1

O

IN2

3

PCH_PLTRST#

1

P

2

G

RH183

@ RH183

@

10K_0402_5%~D

10K_0402_5%~D

1 2

Compal Secret Data

Compal Secret Data

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM

LA-8381P

LA-8381P

LA-8381P

1

17 63Thursday, January 12, 2012

17 63Thursday, January 12, 2012

17 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

High: CRT Plugged

D D

CRT_DET#(34)

2N7002K_SOT23-3

2N7002K_SOT23-3

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H：On-Die voltage regulator enable

*

L：On-Die PLL Voltage Regulator disable

C C

B B

PCH_GPIO37

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated

*

to same voltage
(DC Coupling Mode)

+3VS

RH181 1K_0402_5%~D@RH181 1K_0402_5%~D@

RH182

RH182

RH198

RH198

10K_0402_5%~D

10K_0402_5%~D

CRT_DET

2

G

QH5

G

QH5

PCH_GPIO28

RH229 8.2K_0402_5%~DRH229 8.2K_0402_5%~D

RH177 1K_0402_5%~D

RH177 1K_0402_5%~D

1 2

+3VS

1 2

Item13_X02

13

D

D

S

S

1 2

@

@

1 2

12

10K_0402_5%~D

10K_0402_5%~D

+3V_PCH

PCH_GPIO28

PCH_GPIO37

PCH_GPIO37

4

CRT_DET

GPIO6

EC_SCI#(47)

EC_SMI#(47)

BT_RADIO_DIS#(38)

GPIO15(6)

DGPU_PWROK(17, 31,35,57)

BT_ON#(38)

ODD_DETECT#(45)

FFS_INT2(45)

HDD_DETECT#(45)

EC_SCI#

EC_SMI#

BT_RADIO_DIS#

GPIO15

GPIO16

DGPU_PWROK

PCH_GPIO22

PCH_GPIO28

BT_ON#

GPIO35

ODD_DETECT#

PCH_GPIO37

DGPU_PRSNT#

PCH_GPIO39

FFS_INT2

GPIO49

HDD_DETECT#

BD49

BE49

BF49

A42

H36

E38

C10

C4

G2

U2

D40

E16

M5

N2

M3

V13

D6

A44

A45

A46

B47

BD1

BE1

BF1

3

UH1F

UH1F

T7

BMBUSY# / GPIO0

TACH1 / GPIO1

TACH2 / GPIO6

TACH3 / GPIO7

GPIO8

LAN_PHY_PWR_CTRL / GPIO12

GPIO15

SATA4GP / GPIO16

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

SATA3GP / GPIO37

SLOAD / GPIO38

SDATAOUT0 / GPIO39

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

GPIO57

A4

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

2

ODD_EN#

A20GATE

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

PECI

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

GPIO69

GATEA20

PCH_PECI_R

KB_RST#

H_THERMTRIP#_C

INIT3_3V#

NV_CLE

T126 PAD~DT126 PAD~D

@

1 2

RH1750_0402_5%~D@RH1750_0402_5%~D

1 2

RH176390_0402_5% RH176390_0402_5%
T127 PAD~DT127 PAD~D

INIT3_3V

This signal has weak internal
PU, can't pull low

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

GPIO

GPIO

CPU/MISC

CPU/MISC

NCTF

NCTF

ODD_EN# (45)

GATEA20 (47)

H_PECI (7,47)

KB_RST# (47)

H_CPUPWRGD (6,7)

H_THERMTRIP# (7)

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

NV_CLE

CLOSE TO THE BRANCHING POINT

RH161 and RH162
Follow CRB FAB2 setting

HDD_DETECT#

EC_SMI#

BT_RADIO_DIS#

GPIO15

ODD_EN#

CRT_DET#

ODD_DETECT#

GPIO16

BT_ON#

KB_RST#

PCH_GPIO22

GPIO35

GPIO49

PCH_GPIO39

GPIO6

GATEA20

EC_SCI#

For BIOS setting dGPU present

LOW - dGPU exist

*

DGPU_PRSNT#

DGPU_PRSNT#

1 2

RH188 10K_0402_5%~DRH188 10K_0402_5%~D

1 2

RH190 10K_0402_5%~DRH190 10K_0402_5%~D

1 2

RH279 10K_0402_5%~DRH279 10K_0402_5%~D

1 2

RH281 1K_0402_5%~DRH281 1K_0402_5%~D

1 2

RH187 10K_0402_5%~DRH187 10K_0402_5%~D

@

@

1 2

RH192 10K_0402_5%~D

RH192 10K_0402_5%~D

1 2

RH193 200K_0402_5%RH193 200K_0402_5%

1 2

RH274 10K_0402_5%~DRH274 10K_0402_5%~D

1 2

RH195 8.2K_0402_5%~DRH195 8.2K_0402_5%~D

1 2

RH196 10K_0402_5%~DRH196 10K_0402_5%~D

1 2

RH197 10K_0402_5%~DRH197 10K_0402_5%~D

@

@

1 2

RH257 10K_0402_5%~D

RH257 10K_0402_5%~D

1 2

RH258 10K_0402_5%~DRH258 10K_0402_5%~D

1 2

RH263 10K_0402_5%~DRH263 10K_0402_5%~D

1 2

RH271 10K_0402_5%~DRH271 10K_0402_5%~D

1 2

RH174 10K_0402_5%~DRH174 10K_0402_5%~D

1 2

RH283 10K_0402_5%~DRH283 10K_0402_5%~D

@

@

1 2

RH262 10K_0402_5%~D

RH262 10K_0402_5%~D

1 2

RH282 10K_0402_5%~DRH282 10K_0402_5%~D

1

+1.8VS

12

RH161

RH161

2.2K_0402_5%~D

2.2K_0402_5%~D

12

RH1621K_0402_5%~D RH1621K_0402_5%~D

H_SNB_IVB# (7)

+3V_PCH

+3VS

+3VS

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC

LA-8381P

LA-8381P

LA-8381P

1

18 63Thursday, January 12, 2012

18 63Thursday, January 12, 2012

18 63Thursday, January 12, 2012

1.0

1.0

1.0

5

smd.db-x7.ru

4

3

2

1

check power resistor package

POWER

+1.05VS

D D

+1.05VS

RH201 0_0603_5%~D

RH201 0_0603_5%~D

+1.05VS

RH203 0_0805_5%~D

RH203 0_0805_5%~D

C C

+3VS

RH206 0_0805_5%~D

RH206 0_0805_5%~D

+1.05VS

RH208 0_0603_5%~D@RH 208 0_0603_5%~D@

@

@

J10

J10

PAD-OPEN 4x4m

PAD-OPEN 4x4m

+1.05VS

+VCCAPLLEXP_R

@

@

12

Place CH40 Near BJ22 pin

Item4_X03

SHORT

SHORT

1 2

Item4_X03

SHORT

SHORT

1 2

Place CH53 Near BG6 pin

12

VCCCORE=1.3A max

12

1

1

2

2

CH28

CH28

CH27

CH27

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

Item4_X03

SHORT

SHORT

12

RH200 0_0603_5%~D

RH200 0_0603_5%~D

LH3

@LH3

@

1 2

1UH_LB2012T1R0M_20%~D

1UH_LB2012T1R0M_20%~D

near AN21, AN16, AN33

+1.05VS_VCC_EXP

1

1

1

2

2

2

CH37

CH37

@ CH46

@

CH38

CH38

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CH44

CH44

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

+1.05VS

1

CH46
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

CH39

CH39

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

RH209 0_0805_5%~D

RH209 0_0805_5%~D

+1.05VS_VCCCORE

1

1

2

2

CH26

CH26

CH25

CH25

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+VCCAPLLEXP

close PCH

1

100mil

@

@

2

CH35

CH35

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

2

2

CH41

CH41

CH40

CH40

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+3VS_VCCA3GBG

+VCCAFDI_VRM

+1.05VS_VCCAPLL_FDI

Item4_X03

+1.05VS_VCCDPLL_FDI

SHORT

SHORT

1 2

+VCCP_VCCDMI

AT20, AU20 (Trace needs to be at least 20
mils width with full VSS/VCC reference plane)

UH1G

UH1G

AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29

AJ23
AJ26
AJ27
AJ29
AJ31

AN19

BJ22

AN16

AN17

AN21

AN26

AN27

AP21

AP23

AP24

AP26

AT24

AN33

AN34

BH29

AP16

BG6

AP17

AU20

BD82PPSM-QNHN-A0_BGA989~D

BD82PPSM-QNHN-A0_BGA989~D

1300mA

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

VCCIO[28]

VCCAPLLEXP

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]

VCCIO[21]

VCCIO[22]

VCCIO[23]

VCCIO[24]

VCCIO[25]

VCCIO[26]

VCC3_3[3]

VCCVRM[2]

VccAFDIPLL

VCCIO[27]

VCCDMI[2]

2925mA

POWER

VCC CORE

VCC CORE

VCCIO

VCCIO

FDI

FDI

CRTLVDS

CRTLVDS

60mA

DMI

DMI

190mA

DFT / SPI HVCMOS

DFT / SPI HVCMOS

20mA

1mA

VCCADAC

VSSADAC

1mA

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

20mA

VCCSPI

+VCCADAC

U48

U47

+VCCA_LVDS

AK36

AK37

+VCCTX_LVDS

AM37

AM38

AP36

AP37

+3VS_VCC3_3_6

V33

V34

+VCCAFDI_VRM

AT16

+VCCP_VCCDMI

AT20

+1.05VS_VCC_DMI_CCI

AB36

close PCH 100mil

AG16

AG17

AJ16

AJ17

+3V_VCCPSPI

V1

1

2

CH29

CH29

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

CH32

CH32

1

CH45

CH45

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 2

0_0805_5%~D

0_0805_5%~D

1

Item4_X03

CH47

CH47
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

Item4_X03

LH1

LH1

12

BLM18PG181SN1_0603~D

1

2

CH30

CH30

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

Near AP43

1

CH33

CH33

2

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

1

CH36

CH36

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

RH205 0_0805_5%~D

RH205 0_0805_5%~D

1

CH43

CH43
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+VCCPNAND

RH210

RH210

SHORT

SHORT

BLM18PG181SN1_0603~D

1

1

@

@

10U_0805_25V6K~D

10U_0805_25V6K~D

CH112

CH112

CH31

CH31

2

2

SHORT

SHORT

1 2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

RH199 0_0805_5%~D

RH199 0_0805_5%~D

Item4_X03

1

1

CH34

CH34

2

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

SHORT

SHORT

1 2

RH202 0_0805_5%~D

RH202 0_0805_5%~D

Item4_X03

AT20, AU20 (Trace needs to be at least 20
mils width with full VSS/VCC reference plane)

+VCCP_VCCDMI

RH204 0_0805_5%~D

RH204 0_0805_5%~D

1

+1.05VS

SHORT

SHORT

1 2

Item4_X03

SHORT

SHORT

1 2

RH207 0_0805_5%~D

RH207 0_0805_5%~D

Item4_X03

+3V_PCH

Item1_X03

CH42

CH42

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+1.8VS

+3VS

+3VS

LH2

LH2

12

0.1UH_MLF1608DR10KT_10%_1608

0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA

+3VS

+1.05VS

SHORT

SHORT

1 2

Item4_X03

+1.8VS

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1.05

1.05

1.05

1.05

S0 Iccmax
Current (A)

0.001

5

0.001

5

0.001

0.266

0.001

0.08

0.08

1.3

0.042

1.05VccIO 2.925

1.05VccASW 1.01

3.3VccSPI 0.02

3.3VccDSW 0.003

1.8 0.19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1.5 0.16

1.05VccCLKDMI

0.02

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.06

SUSP#

C432

C432

+3VALW

1

2

U47

U47

1

VIN

VOUT

2

GND

SHDN3BP

APE8805A-15Y5P_SOT23-5

APE8805A-15Y5P_SOT23-5

5

4

+VCCAFDI_VRM

Item9_X01

1

CH111

CH111

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

2

+VCCAFDI_VRM

1

CH110

CH110

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

B B

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

SUSP#(32,47,55,56)

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/06/02 2012/06/02

2011/06/02 2012/06/02

2011/06/02 2012/06/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (6/8) PWR

PCH (6/8) PWR

PCH (6/8) PWR

LA-8381P

LA-8381P

LA-8381P

1

19 63Thursday, January 12, 2012

19 63Thursday, January 12, 2012

19 63Thursday, January 12, 2012

1.0

1.0

1.0