Compal LA-8321P QBR10, Alienware M18x R2, LA-8321P Avenger MLK Schematic

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

1 1

LA-8321P

4619H531L01

QBR10

Compal Confidential

2 2

Avenger MLK

rPGA Ivy Bridge + FCBGA PCH Panther Point-M + MXM x2Ⅲ

3 3

Rev: 0.3 (X02)

2011.12.08

@ : Nopop component

CONN@ : ME connector

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

D

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal El ectronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-8321P

LA-8321P

LA-8321P

E

0.1

0.1

1 65Tuesday, January 17, 2012

1 65Tuesday, January 17, 2012

1 65Tuesday, January 17, 2012

0.1

A

B

C

D

E

Compal Confidential

Project Code : QBR10
File Name : LA-8321P

LVDS

1 1

Conn

2 2

3 3

DC/DC Interface

Power On/Off

BATTERY / OTP

DCIN / DECTOR

4 4

CHARGER

3V/5V ALW

LVDS MUX

P.25

CRT
Conn

HDMI 1.4
Conn

mini DP
Conn

Mini Card -2
Wireless Display
DMC (Full)

PCIE Port 2

Mini Card-2
DMC (Full)

P.42

+VCCP

+1.8V

P.44

+1.5V/+0.75V

P.45

VCCSA

P.46

CPU_CORE

P.47

A

P.36

HDMI to LVDS SW

STDP6038

LVDS MUX

P.25

CRT MUX

P.26

HDMI MUX

P.27

DP MUX

P.28

DP MUX

P.35

USB Port 5

LAN(GbE)

AR8151

Sub-board

IO Board

P.48P.43

LS-6571P

Media Board

P.49

LS-6572P

L-Speaker LED Board

P.50

LS-6575P

R-Speaker LED Board

P.51

LS-6574P

Power LED Board

P.52

LS-6579P

P.24

P.26

P.27

P.28

P.29

PCIE Port 1

P.31

RJ45

Conn

P.31

P.30

LVDS (DIS)

CRT (DIS)

DP Port C
DP Port B

DP Port B

DP Port C

DP Port A

DP Port D

(DIS)

(UMA)

(DIS)

(UMA)

(DIS)

(UMA)

Mini Card-1
WLAN (Half)

HDMI 1.3
input Conn

PCIE Port 3

Card Reader

P.35

USB Port 4

RTS5209

IO Board

NUM/CAP LED Board

LS-6573P

Alienware Logo Board

LS-6577P

Touch pad Board

LS-6608P

Power Button Board

LS-6578P

B

Master GPU

MXM III
Conn.

Slave GPU

MXM III
Conn.

PCIE Port 4 PCIE Port 5

PEG x8 (DIS)

P.14

PEG x8 (DIS)

P.15

LVDS

CRT

HDMI

DisplayPort

DMC

PCIE BUS

Express Card

( 54mm )

9 in 1

USB Port 11

Socket

SPI ROM

ENE 3810

Touch Pad

Intel

Ivy Bridge

Processor

(DDRIII)
Memory Bus

Dual Channel

1.5V DDRIII
1600/1333 MHz

4C 45W, 55W

rPGA 989 Socket

(UMA)

100MHz

2.7GT/s

P.4~9

DMI x4 gen 2FDI x8

100MHz

5GB/s

SATA

Intel

Panther Point

USB3.0

PCH

BGA 989 Balls

HM77

SPI

P.16

LPC Bus

ENE KB930

P.40

PS2 SPI

Int.KBD

P.38

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SE CRET AN D OTHER PROPRIE TARY INF ORMATION OF DEL L. THIS DOCUMEN T MAY NO T
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WI THOUT D ELL'S EX PRESS W RITTEN C ONSENT.

C

BIOS ROM

P.43 P.40

USB2.0

HD Audio

P16~23

Audio Codec
Malcolm
HDA015-B

P.40

Thermal sensor
/ Fan Control

EMC1412

204pin DDRIII SO-DIMM x4

SATA Port 0

SATA Port 1

SATA Port 3

SATA Port 2

SATA Port 4
USB Port 9

USB Port 0,1

USB Port 1,2

USB Port 12

USB Port 3,4

USB Port 2

USB Port 6

USB Port 8

USB Port 13

Amplifier x2
MAX9736

P.32

Media Board

Media / Mode
Buttons

D

PCH XDP

P.41

BANK 0, 1, 2, 3

Conn.

SATA HDD-1 Conn.

SATA HDD-2 Conn.

SATA HDD-3 Conn.

SATA ODD Conn.

USB / eSATA Conn.

USB Charger

USB 2.0 /3.0 Conn x 2
dual-stack

Digital Camera

USB 2.0/3.0 Conn x 2
dual-stack

AlienFX/ELC
C8051F347

BT 2.1 /BT 3.0

VPK

P.33

P.38

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

CPU XDP
Conn.

P.16

P.10,11,12,13

P.34

P.34

SATA Port 5

P.34

P.34

IO Board

thourgh LVDS cable

P.24

MAX7313D x3

P.37

P.35

P.35

Int. Speaker
4Ω 2.5Wx 2

P.33

Subwoofer
4Ω 5W

P.33

Head phone Jack x1
Mic phone Jack x1

MIC + Rear LF

S/PDIF Out

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

LA-8321P

LA-8321P

LA-8321P

E

P.5

mSATA Conn.

P.37~39

P.32

P.25

P.33

2 65Tuesday, January 17, 2012

2 65Tuesday, January 17, 2012

2 65Tuesday, January 17, 2012

of

of

of

P.34

0.1

0.1

0.1

A

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0
1
2
3
4
5
6
7

100K +/- 5%Ra

Rb V min

0 0 V

18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

AD_BID

0.168 V8.2K +/- 5% 0.250 V 0.362 V

0.436 V

0.712 V

1.036 V

1.453 V

1.935 V

2.500 V

V typ

AD_BID

0 V 0 V

0.503 V

0.819 V

1.185 V

1.650 V

2.200 V

3.300 V

V

AD_BID

0.538 V

0.875 V

1.264 V

1.759 V

2.341 V

3.300 VNC

max

POWER STATES

SLP
S4#

HIGHLOW

SLP

S4

S5#

STATE #

HIGH HIGH

HIGH

LOWLOWLOW ONLOW

SLP
M#

Signal

State

S0 (Full ON) / M0 HIGH

S3 (Suspend to RAM) / M-OFF ONLOWHIGH

S4 (Suspend to DISK) / M-OFF

S5 (SOFT OFF) / M-OFF

1 1

SLP
S3#

HIGH

LOW ONLOWLOWLOWLOW

ALWAYS
PLANE

ONHIGH

SUS
PLANE

ON OFF OFF

OFF OFF OFF

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

RUN

CLOCKS

PLANE

ONONON

OFFOFF OFF

PCB Revision

0.1

0.2

0.3

0.4

1.0

PM TABLE

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

power
plane

USB3.0

+5VALW

+3VALW

+3VLP

+3V_PCH

ON

ON

OFF

USB PORT#0DESTINATION

JUSB1

1

2

3

+1.5V

ON ON

ON

OFF

OFF

JUSB2

JUSB3

JUSB4

+5VS

+3VS

+1.8VS

+1.5VS

+0.75VS

+3VMXM

+5VMXM

+VCCP

+VCCSA

+VCC_CORE

+1.5V_CPU_VDDQ

OFFON

OFF

OFF

USB

USB PORT#0DESTINATION

JUSB1

1

2

3

4

5

6

7

8

JUSB2

JUSB3

JUSB4

Mini Card (WLAN)

Mini Card (DMC)

AlienFX/ELC

None

Bluetooth

9 USB / eSATA combo

10

11

12

13

None

EXPRESS CARD

CAMERA

VPK

CLK

DESTINATIONDIFFERENTIAL

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

CLKOUT_PCIE7

CLKOUT_PEG_A

None

10/100/1G LAN

MINI CARD-2 DMC

MINI CARD-1 WLAN

CARD READER

EXPRESS CARD

None

None

MXM I

CLKOUT_PEG_B MXM II

FLEX CLOCKS DESTINATION

CLKOUTFLEX0

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

None

None

None

None

Symbol Note :

Digital Ground

Analog Ground

+3VALW

+3VLP

+3V_PCH

+3VS

+3VMXM

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

VoltagePower plane

DESTINATION

3.3V

A

PCI EXPRESS

HDD1

HDD2

ODD

HDD3

E-SATA

mSATA

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

DESTINATION

10/100/1G LAN

MINI CARD-2 DMC

MINI CARD-1 WLAN

CARD READER

EXPRESS CARD

None

None

None

CLKOUT

PCI0

PCI1

PCI2

PCI3

PCI4

DESTINATION

PCH_LOOPBACK

EC

DEBUG

None

None

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Do cument Number Rev

Size Do cument Number Rev

Size Do cument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Index and Config.

Index and Config.

Index and Config.

LA-8321P

LA-8321P

LA-8321P

3 65Tuesday, J anuary 17, 2012

3 65Tuesday, J anuary 17, 2012

3 65Tuesday, J anuary 17, 2012

0.1

0.1

0.1

5

JCPUA

CONN@

JCPUA

D D

DMI_CRX_PTX_N0<18>
DMI_CRX_PTX_N1<18>
DMI_CRX_PTX_N2<18>
DMI_CRX_PTX_N3<18>

DMI_CRX_PTX_P0<18>
DMI_CRX_PTX_P1<18>
DMI_CRX_PTX_P2<18>
DMI_CRX_PTX_P3<18>

DMI_CTX_PRX_N0<18>
DMI_CTX_PRX_N1<18>
DMI_CTX_PRX_N2<18>
DMI_CTX_PRX_N3<18>

DMI_CTX_PRX_P0<18>
DMI_CTX_PRX_P1<18>
DMI_CTX_PRX_P2<18>
DMI_CTX_PRX_P3<18>

RC14

RC14

1 2

24.9_0402_1%

24.9_0402_1%

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

+EDP_COM

FDI_CTX_PRX_N0<18>
FDI_CTX_PRX_N1<18>
FDI_CTX_PRX_N2<18>
FDI_CTX_PRX_N3<18>
FDI_CTX_PRX_N4<18>
FDI_CTX_PRX_N5<18>

C C

B B

FDI_CTX_PRX_N6<18>
FDI_CTX_PRX_N7<18>

FDI_CTX_PRX_P0<18>
FDI_CTX_PRX_P1<18>
FDI_CTX_PRX_P2<18>
FDI_CTX_PRX_P3<18>
FDI_CTX_PRX_P4<18>
FDI_CTX_PRX_P5<18>
FDI_CTX_PRX_P6<18>
FDI_CTX_PRX_P7<18>

FDI_FSYNC0<18>
FDI_FSYNC1<18>

FDI_INT<18>

FDI_LSYNC0<18>
FDI_LSYNC1<18>

+VCCP

B27
B25
A25
B24

B28
B26
A24
B23

G21
E22

F21

D21

G22
D22

F20

C21

A21
H19
E19

F18
B21
C20
D18
E17

A22
G19
E20
G18
B20
C19
D19

F17

J18

J17

H20

J19
H17

A18
A17
B16

C15
D15

C17

F16
C16
G15

C18
E16
D16

F15

CONN@

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD#

eDP_AUX
eDP_AUX#

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

DMI

DMI

Intel(R) FDI

Intel(R) FDI

eDP

eDP

4

PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils

+VCCP

- typical impedance = 14.5 mohms

12

RC2

RC2

24.9_0402_1%

24.9_0402_1%

PEG_COMP

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

PEG_GTX_C_HRX_N0

K33

PEG_GTX_C_HRX_N1

M35

PEG_GTX_C_HRX_N2

L34

PEG_GTX_C_HRX_N3

J35

PEG_GTX_C_HRX_N4

J32

PEG_GTX_C_HRX_N5

H34

PEG_GTX_C_HRX_N6

H31

PEG_GTX_C_HRX_N7

G33

PEG_GTX_C_HRX_N8

G30

PEG_GTX_C_HRX_N9

F35

PEG_GTX_C_HRX_N10

E34

PEG_GTX_C_HRX_N11

E32

PEG_GTX_C_HRX_N12

D33

PEG_GTX_C_HRX_N13

D31

PEG_GTX_C_HRX_N14

B33

PEG_GTX_C_HRX_N15

C32

PEG_GTX_C_HRX_P0

J33

PEG_GTX_C_HRX_P1

L35

PEG_GTX_C_HRX_P2

K34

PEG_GTX_C_HRX_P3

H35

PEG_GTX_C_HRX_P4

H32

PEG_GTX_C_HRX_P5

G34

PEG_GTX_C_HRX_P6

G31

PEG_GTX_C_HRX_P7

F33

PEG_GTX_C_HRX_P8

F30

PEG_GTX_C_HRX_P9

E35

PEG_GTX_C_HRX_P10

E33

PEG_GTX_C_HRX_P11

F32

PEG_GTX_C_HRX_P12

D34

PEG_GTX_C_HRX_P13

E31

PEG_GTX_C_HRX_P14

C33

PEG_GTX_C_HRX_P15

B32

PEG_HTX_GRX_N0

M29

PEG_HTX_GRX_N1

M32

PEG_HTX_GRX_N2

M31

PEG_HTX_GRX_N3

L32

PEG_HTX_GRX_N4

L29

PEG_HTX_GRX_N5

K31

PEG_HTX_GRX_N6

K28

PEG_HTX_GRX_N7

J30

PEG_HTX_GRX_N8

J28

PEG_HTX_GRX_N9

H29

PEG_HTX_GRX_N10

G27

PEG_HTX_GRX_N11

E29

PEG_HTX_GRX_N12

F27

PEG_HTX_GRX_N13

D28

PEG_HTX_GRX_N14

F26

PEG_HTX_GRX_N15

E25

PEG_HTX_GRX_P0

M28

PEG_HTX_GRX_P1

M33

PEG_HTX_GRX_P2

M30

PEG_HTX_GRX_P3

L31

PEG_HTX_GRX_P4

L28

PEG_HTX_GRX_P5

K30

PEG_HTX_GRX_P6

K27

PEG_HTX_GRX_P7

J29

PEG_HTX_GRX_P8

J27

PEG_HTX_GRX_P9

H28

PEG_HTX_GRX_P10

G28

PEG_HTX_GRX_P11

E28

PEG_HTX_GRX_P12

F28

PEG_HTX_GRX_P13

D27

PEG_HTX_GRX_P14

E26

PEG_HTX_GRX_P15

D25

CC1 0.22U_0402_16V7K~DCC1 0.22U_0402_16V7K~D

1 2

CC2 0.22U_0402_16V7K~DCC2 0.22U_0402_16V7K~D

1 2

CC3 0.22U_0402_16V7K~DCC3 0.22U_0402_16V7K~D

1 2

CC4 0.22U_0402_16V7K~DCC4 0.22U_0402_16V7K~D

1 2

CC5 0.22U_0402_16V7K~DCC5 0.22U_0402_16V7K~D

1 2

CC6 0.22U_0402_16V7K~DCC6 0.22U_0402_16V7K~D

1 2

CC7 0.22U_0402_16V7K~DCC7 0.22U_0402_16V7K~D

1 2

CC8 0.22U_0402_16V7K~DCC8 0.22U_0402_16V7K~D

1 2

CC9 0.22U_0402_16V7K~DCC9 0.22U_0402_16V7K~D

1 2

CC10 0.22U_0402_16V7K~DCC10 0.22U_0402_16V7K~D

1 2

CC11 0.22U_0402_16V7K~DCC11 0.22U_0402_16V7K~D

1 2

CC12 0.22U_0402_16V7K~DCC12 0.22U_0402_16V7K~D

1 2

CC13 0.22U_0402_16V7K~DCC13 0.22U_0402_16V7K~D

1 2

CC14 0.22U_0402_16V7K~DCC14 0.22U_0402_16V7K~D

1 2

CC15 0.22U_0402_16V7K~DCC15 0.22U_0402_16V7K~D

1 2

CC16 0.22U_0402_16V7K~DCC16 0.22U_0402_16V7K~D

1 2

CC17 0.22U_0402_16V7K~DCC17 0.22U_0402_16V7K~D

1 2

CC18 0.22U_0402_16V7K~DCC18 0.22U_0402_16V7K~D

1 2

CC19 0.22U_0402_16V7K~DCC19 0.22U_0402_16V7K~D

1 2

CC20 0.22U_0402_16V7K~DCC20 0.22U_0402_16V7K~D

1 2

CC21 0.22U_0402_16V7K~DCC21 0.22U_0402_16V7K~D

1 2

CC22 0.22U_0402_16V7K~DCC22 0.22U_0402_16V7K~D

1 2

CC23 0.22U_0402_16V7K~DCC23 0.22U_0402_16V7K~D

1 2

CC24 0.22U_0402_16V7K~DCC24 0.22U_0402_16V7K~D

1 2

CC25 0.22U_0402_16V7K~DCC25 0.22U_0402_16V7K~D

1 2

CC26 0.22U_0402_16V7K~DCC26 0.22U_0402_16V7K~D

1 2

CC27 0.22U_0402_16V7K~DCC27 0.22U_0402_16V7K~D

1 2

CC28 0.22U_0402_16V7K~DCC28 0.22U_0402_16V7K~D

1 2

CC29 0.22U_0402_16V7K~DCC29 0.22U_0402_16V7K~D

1 2

CC30 0.22U_0402_16V7K~DCC30 0.22U_0402_16V7K~D

1 2

CC31 0.22U_0402_16V7K~DCC31 0.22U_0402_16V7K~D

1 2

CC32 0.22U_0402_16V7K~DCC32 0.22U_0402_16V7K~D

1 2

CC33 0.22U_0402_16V7K~DCC33 0.22U_0402_16V7K~D

1 2

CC34 0.22U_0402_16V7K~DCC34 0.22U_0402_16V7K~D

1 2

CC35 0.22U_0402_16V7K~DCC35 0.22U_0402_16V7K~D

1 2

CC36 0.22U_0402_16V7K~DCC36 0.22U_0402_16V7K~D

1 2

CC37 0.22U_0402_16V7K~DCC37 0.22U_0402_16V7K~D

1 2

CC38 0.22U_0402_16V7K~DCC38 0.22U_0402_16V7K~D

1 2

CC39 0.22U_0402_16V7K~DCC39 0.22U_0402_16V7K~D

1 2

CC40 0.22U_0402_16V7K~DCC40 0.22U_0402_16V7K~D

1 2

CC41 0.22U_0402_16V7K~DCC41 0.22U_0402_16V7K~D

1 2

CC42 0.22U_0402_16V7K~DCC42 0.22U_0402_16V7K~D

1 2

CC43 0.22U_0402_16V7K~DCC43 0.22U_0402_16V7K~D

1 2

CC44 0.22U_0402_16V7K~DCC44 0.22U_0402_16V7K~D

1 2

CC45 0.22U_0402_16V7K~DCC45 0.22U_0402_16V7K~D

1 2

CC46 0.22U_0402_16V7K~DCC46 0.22U_0402_16V7K~D

1 2

CC47 0.22U_0402_16V7K~DCC47 0.22U_0402_16V7K~D

1 2

CC48 0.22U_0402_16V7K~DCC48 0.22U_0402_16V7K~D

1 2

CC49 0.22U_0402_16V7K~DCC49 0.22U_0402_16V7K~D

1 2

CC50 0.22U_0402_16V7K~DCC50 0.22U_0402_16V7K~D

1 2

CC51 0.22U_0402_16V7K~DCC51 0.22U_0402_16V7K~D

1 2

CC52 0.22U_0402_16V7K~DCC52 0.22U_0402_16V7K~D

1 2

CC53 0.22U_0402_16V7K~DCC53 0.22U_0402_16V7K~D

1 2

CC54 0.22U_0402_16V7K~DCC54 0.22U_0402_16V7K~D

1 2

CC55 0.22U_0402_16V7K~DCC55 0.22U_0402_16V7K~D

1 2

CC56 0.22U_0402_16V7K~DCC56 0.22U_0402_16V7K~D

1 2

CC57 0.22U_0402_16V7K~DCC57 0.22U_0402_16V7K~D

1 2

CC58 0.22U_0402_16V7K~DCC58 0.22U_0402_16V7K~D

1 2

CC59 0.22U_0402_16V7K~DCC59 0.22U_0402_16V7K~D

1 2

CC60 0.22U_0402_16V7K~DCC60 0.22U_0402_16V7K~D

1 2

CC61 0.22U_0402_16V7K~DCC61 0.22U_0402_16V7K~D

1 2

CC62 0.22U_0402_16V7K~DCC62 0.22U_0402_16V7K~D

1 2

CC63 0.22U_0402_16V7K~DCC63 0.22U_0402_16V7K~D

1 2

CC64 0.22U_0402_16V7K~DCC64 0.22U_0402_16V7K~D

1 2

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

Near MXM Connector

3

PEG_GTX_HRX_N0
PEG_GTX_HRX_N1
PEG_GTX_HRX_N2
PEG_GTX_HRX_N3
PEG_GTX_HRX_N4
PEG_GTX_HRX_N5
PEG_GTX_HRX_N6
PEG_GTX_HRX_N7
PEG_GTX_HRX_N8
PEG_GTX_HRX_N9
PEG_GTX_HRX_N10
PEG_GTX_HRX_N11
PEG_GTX_HRX_N12
PEG_GTX_HRX_N13
PEG_GTX_HRX_N14
PEG_GTX_HRX_N15

PEG_GTX_HRX_P0
PEG_GTX_HRX_P1
PEG_GTX_HRX_P2
PEG_GTX_HRX_P3
PEG_GTX_HRX_P4
PEG_GTX_HRX_P5
PEG_GTX_HRX_P6
PEG_GTX_HRX_P7
PEG_GTX_HRX_P8
PEG_GTX_HRX_P9
PEG_GTX_HRX_P10
PEG_GTX_HRX_P11
PEG_GTX_HRX_P12
PEG_GTX_HRX_P13
PEG_GTX_HRX_P14
PEG_GTX_HRX_P15

PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N8

PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N15

PEG_HTX_C_GRX_P0

PEG_HTX_C_GRX_P1

PEG_HTX_C_GRX_P2

PEG_HTX_C_GRX_P3

PEG_HTX_C_GRX_P4

PEG_HTX_C_GRX_P5

PEG_HTX_C_GRX_P6

PEG_HTX_C_GRX_P7

PEG_HTX_C_GRX_P8

PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P15

PEG_GTX_HRX_N[0..15] <14,15>

PEG_GTX_HRX_P[0..15] <14,15>

PEG_HTX_C_GRX_N[0..15] <14,15>

PEG_HTX_C_GRX_P[0..15] <14,15>

2

JCPUI

CONN@

JCPUI

CONN@

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS

1

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

E15

VSS241

E13

VSS242

E10

VSS243

E9

VSS244

E8

VSS245

E7

VSS246

E6

VSS247

E5

VSS248

E4

VSS249

E3

VSS250

E2

VSS251

E1

VSS252

D35

VSS253

D32

VSS254

D29

VSS255

D26

VSS256

D20

VSS257

D17

VSS258

C34

VSS259

C31

VSS260

C28

VSS261

C27

VSS262

C25

VSS263

C23

VSS264

C10

VSS265

C1

VSS266

B22

VSS267

B19

VSS268

B17

VSS269

B15

VSS270

B13

VSS271

B11

VSS272

B9

VSS273

B8

VSS274

B7

VSS275

B5

VSS276

B3

VSS277

B2

VSS278

A35

VSS279

A32

VSS280

A29

VSS281

A26

VSS282

A23

VSS283

A20

VSS284

A3

VSS285

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal El ectronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

PROCESSOR(1/6) DMI,FDI,PEG

LA-8321P

LA-8321P

LA-8321P

1

4

4

4

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

5

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

1

@

@

CC65

CC65

2

D D

C C

CFG10<7>
CFG11<7>

H_CPUPWRGD

PBTN_OUT#

CFG0<7>

VGATE<16,18,53>

+3VALW

PCH_SMBDATA
PCH_SMBCLK

PCH_JTAG_TCK<16>

The resistor
for HOOK2 should be
placed such that the
stub is very small
on CFG0 net

1 2
1 2

1 2
1 2
1 2

1 2

2

@

@

CC66

CC66

RC1120_0402_5 % @ RC1120_0402 _5% @

12

RC1130_0402_5 % @ RC1130_0402 _5% @

12

XDP_PREQ#
XDP_PRDY#

XDP_BPM#0
XDP_BPM#1

XDP_BPM#2
XDP_BPM#3

CFG10_R
CFG11_R

XDP_BPM#4
XDP_BPM#5

XDP_BPM#6
XDP_BPM#7

H_CPUPWRGD_XDP

RC51K_0402_5% @ RC51K_0402_5% @

CFD_PWRBTN#_XDP

RC60_0402_5% @ RC60_04 02_5% @

XDP_HOOK2

RC71K_0402_5% @ RC71K_0402_5% @

SYS_PWROK_XDP

RC90_0402_5% @ RC90_04 02_5% @
RC31K_0402_5% @ RC31K_0402_5% @

XDP_TCK1

RC980 _0402_5% @ RC980 _0402_5% @

XDP_TCK

+VCCP +VCCP

JCPUXDP

JCPUXDP

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

SAMTE_BSH-030-01-L-D-A

CONN@

CONN@

JCPUB

CONN@

JCPUB

CONN@

4

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

TMS

GND17

3

2

CFG16_R

RC84 0_0402_5%@ RC84 0_0402_5%@

4

CFG17_R

6
8

CFG0_R

10

CFG1_R

12
14

CFG2_R

16

CFG3_R

18
20

CFG8_R

22

CFG9_R

24
26

CFG4_R

28

CFG5_R

30
32

CFG6_R

34

CFG7_R

36
38

CLK_CPU_ITP

40

CLK_CPU_ITP#

42
44

XDP_RST#_R

46

XDP_DBRESET#

48
50

XDP_TDO

52

TD0

TDI

XDP_TRST#

54

XDP_TDI

56

XDP_TMS

58
60

1 2

RC85 0_0402_5%@ RC85 0_0402_5%@

1 2

RC86 0_0402_5%@ RC86 0_0402_5%@

1 2

RC87 0_0402_5%@ RC87 0_0402_5%@

1 2

RC88 0_0402_5%@ RC88 0_0402_5%@

1 2

RC89 0_0402_5%@ RC89 0_0402_5%@

1 2

RC90 0_0402_5%@ RC90 0_0402_5%@

1 2

RC91 0_0402_5%@ RC91 0_0402_5%@

1 2

RC92 0_0402_5%@ RC92 0_0402_5%@

1 2

RC93 0_0402_5%@ RC93 0_0402_5%@

1 2

RC94 0_0402_5%@ RC94 0_0402_5%@

1 2

RC95 0_0402_5%@ RC95 0_0402_5%@

1 2

RC8 1K_0402_5%@RC8 1K_ 0402_5%@

RC99 0_0402_5%@ RC99 0_0402_5%@

1 2

RC100 0_0402_5%@ RC100 0_0402_5%@

1 2

RC101 0_0402_5%@ RC101 0_0402_5%@

1 2

CFG16 <7>
CFG17 <7>

CFG0 <7>
CFG1 <7>

CFG2 <7>
CFG3 <7>

CFG8 <7>
CFG9 <7>

CFG4 <7>
CFG5 <7>

CFG6 <7>
CFG7 <7>

CLK_CPU_ITP <17>
CLK_CPU_ITP# <17>

12

PLT_RST#

PCH_JTAG_TDO <16>

PCH_JTAG_TDI <16>
PCH_JTAG_TMS <16>

PM_DRAM_PWRGD<18>

R1905 0_0402_5%@ R1905 0_0402_5%@

12

R1910

R1910
100K_0402_5%

100K_0402_5%

1 2

VGATE<16,18,53>

2

RC58

RC58

10K_0402_5%~D

10K_0402_5%~D

RUN_ON_CPU1.5VS3#<9,42>

PLT_RST#<16,19,31,35,40,43>

+3VS

12

+3V_PCH

12

RC18

RC18
10K_0402_5%~D

10K_0402_5%~D

1

2

+3VALW

1

2

5

UC2

UC2

1

B

Y

VCC

2

A

G

MC74VHC1G09DFT2G_SC70-5

MC74VHC1G09DFT2G_SC70-5

3

RUN_ON_CPU1.5VS3#

+3VALW

1

CC140

CC140

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2

5

UC1

UC1

P

NC

4

Y

A

G

3

SN74LVC1G07DCKR_SC70-5

SN74LVC1G07DCKR_SC70-5

1

2

G

G

+VCCP

12

+1.5V_CPU_VDDQ

12

RC64

@ RC64

@

39_0402_1%

39_0402_1%

1 2

13

D

D

QC1

@

QC1

@

2N7002E-T1-E3_SOT23-3

2N7002E-T1-E3_SOT23-3

S

S

RC4

RC4
75_0402_1%

75_0402_1%

RC10

RC10

1 2

43_0402_1%

43_0402_1%

RC12

RC12
200_0402_1%

200_0402_1%

VDDPWRGOOD

CC156

CC156

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

4

BUFO_CPU_RST# BUF_CPU_RST#

CLK_CPU_DMI_R

A28

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

MISC

MISC

BCLK

BCLK#

PRDY#
PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

H_SNB_IVB#<20>

RC57

RC57

H_CATERR#

H_PROCHOT#_R

H_THRMTRIP#

H_PM_SYNC_R

H_CPUPWRGD_R

VDDPWRGOOD_R

BUF_CPU_RST#

T137PAD~D @T137PAD~D @

H_PECI<20,40>

B B

A A

H_PROCHOT#<40,45>

H_THRMTRIP#<20>

H_PM_SYNC<18>

H_CPUPWRGD<20>

VDDPWRGOOD

1 2

56_0402_5%

56_0402_5%

1 2

RC22 0_0402_5%~D@RC22 0_0 402_5%~D@

1 2

RC25 0_0402_5%~D@RC25 0_0 402_5%~D@

1 2

RC28 130_0402_1 %RC28 130_0402_ 1%

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWROK

AR33

RESET#

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

CLOCKS

CLOCKS

DDR3

DDR3

JTAG & BPM

JTAG & BPM

TCK
TMS

TDO

TDI

A27

A16
A15

R8

AK1
A5
A4

AP29
AP27

AR26
AR27
AP30

AR28
AP26

XDP_DBRESET#_R

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

CLK_CPU_DMI#_R

CLK_CPU_DPLL
CLK_CPU_DPLL#

H_DRAMRST#

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

XDP_PRDY#
XDP_PREQ#

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI_R
XDP_TDO_R

XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R

RC13 0_0402_5%~D@ RC13 0_0402_5%~D@

1 2

RC15 0_0402_5%~D@RC15 0_0402_5%~D@

1 2

H_DRAMRST# <6>

RC23 0_0402_5%@ RC23 0_0402_5%@

1 2

RC24 0_0402_5%@ RC24 0_0402_5%@

1 2

RC26 0_0402_5%~D@ RC26 0_0402_5%~D@

1 2

RC30 0_0402_5%@ RC30 0_0402_5%@

1 2

RC31 0_0402_5%@ RC31 0_0402_5%@

1 2

RC33 0_0402_5%@ RC33 0_0402_5%@

1 2

RC34 0_0402_5%@ RC34 0_0402_5%@

1 2

RC36 0_0402_5%@ RC36 0_0402_5%@

1 2

RC37 0_0402_5%@ RC37 0_0402_5%@

1 2

RC38 0_0402_5%@ RC38 0_0402_5%@

1 2

RC39 0_0402_5%@ RC39 0_0402_5%@

1 2

Processor Pullups

H_PROCHOT#

CLK_CPU_DMI <17>
CLK_CPU_DMI# <17>

1 2

XDP_TDI
XDP_TDO

XDP_DBRESET#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7

+VCCP

RC4462_0402_5%

RC4462_0402_5%

XDP_DBRESET# <16,18>

CLK_CPU_DPLL#

CLK_CPU_DPLL

RU25 1K_0402_5%RU25 1K_040 2_5%

RU24 1K_0402_5%RU24 1K_040 2_5%

XDP_DBRESET#

H_CPUPWRGD_R

1 2

1 2

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

1 2

1 2

1 2

1 2

1 2

+VCCP

RC191K_0402_5% RC191K_0402_5%

RC2110K_0402_5%~D RC2110K_0402_5%~D

+3VS

RC42140_0402_1% RC42140_0402_1%

RC4325.5_0402_1%~D RC4325.5_0402_1%~D

RC45200_0402_1% RC45200_0402_1%

PU/PD for JTAG signals

XDP_TMS

XDP_TDI_R

XDP_PREQ#

XDP_TDO_R

XDP_TCK

XDP_TRST#

1 2

1 2

1 2

1 2

1 2

1 2

+VCCP

RC2751_0402_5% RC2751_0402_5%

RC2951_0402_5% RC2951_0402_5%

RC3251_0402_5% @ RC3251_0402_5% @

RC3551_0402_5% RC3551_0402_5%

RC4051_0402_5% RC4051_0402_5%

RC4151_0402_5% RC4151_0402_5%

DELL CONFIDENTIAL/PROPRIETARY

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet

Date: Sheet

Compal El ectronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

PROCESSOR(2/6) PM,XDP,CLK

LA-8321P

LA-8321P

LA-8321P

1

5

5

5

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

of

of

5

JCPUC

CONN@

JCPUC

CONN@

DDR_A_D[0..63]<10,12>

D D

C C

B B

A A

DDR_A_BS0<10,12>
DDR_A_BS1<10,12>
DDR_A_BS2<10,12>

DDR_A_CAS#<10,12>
DDR_A_RAS#<10,12>
DDR_A_WE#<10,12>

DRAMRST_CNTRL_PCH<10,11,17>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

H_DRAMRST#<5> DDR3_DRAMRST# <10,11,12,13>

DRAMRST_CNTRL_EC<40>

5

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]

G10

SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]

N10

SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]

M10

SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]

AG6

SA_DQ[32]

AG5

SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]

AH5

SA_DQ[36]

AH6

SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]

AH8

SA_DQ[44]

AH9

SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]

AP11

SA_DQ[48]

AN11

SA_DQ[49]

AL12

SA_DQ[50]

AM12

SA_DQ[51]

AM11

SA_DQ[52]

AL11

SA_DQ[53]

AP12

SA_DQ[54]

AN12

SA_DQ[55]

AJ14

SA_DQ[56]

AH14

SA_DQ[57]

AL15

SA_DQ[58]

AK15

SA_DQ[59]

AL14

SA_DQ[60]

AK14

SA_DQ[61]

AJ15

SA_DQ[62]

AH15

SA_DQ[63]

AE10

SA_BS[0]

AF10

SA_BS[1]

V6

SA_BS[2]

AE8

SA_CAS#

AD9

SA_RAS#

AF9

SA_WE#

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

1 2

RC46 0_0402_5%~D@RC46 0_0402_5%~D@

1 2

RC47 0_0402_5%@RC47 0_0402_5%@

RC50

RC50

4.99K_0402_1%

4.99K_0402_1%

DRAMRST_CNTRL

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

S

S

12

QC2 BSS138_SOT23~D

QC2 BSS138_SOT23~D

SA_CK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]

SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

D

D

DDR3_DRAMRST#_RH_DRAMRST#

13

G

G

2

1

CC177

CC177

0.047U_0402_16V7K~D

0.047U_0402_16V7K~D

2

4

4

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA0

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA0

M_CLK_DDR4
M_CLK_DDR#4
DDR_CKE4_DIMMA1

M_CLK_DDR5
M_CLK_DDR#5
DDR_CKE5_DIMMA1

DDR_CS0_DIMMA0#
DDR_CS1_DIMMA0#
DDR_CS4_DIMMA1#
DDR_CS5_DIMMA1#

M_ODT0
M_ODT1
M_ODT4
M_ODT5

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

+1.5V

M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA0 <12>

M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA0 <12>

M_CLK_DDR4 <10>
M_CLK_DDR#4 <10>
DDR_CKE4_DIMMA1 <10>

M_CLK_DDR5 <10>
M_CLK_DDR#5 <10>
DDR_CKE5_DIMMA1 <10>

DDR_CS0_DIMMA0# <12>
DDR_CS1_DIMMA0# <12>
DDR_CS4_DIMMA1# <10>
DDR_CS5_DIMMA1# <10>

M_ODT0 <12>
M_ODT1 <12>
M_ODT4 <10>
M_ODT5 <10>

12

RC49

RC49
1K_0402_5%

1K_0402_5%

RC124 1K_0402_5%RC124 1K_0402_5%

DDR_A_DQS#[0..7] <10,12>

DDR_A_DQS[0..7] <10,12>

DDR_A_MA[0..15] <10,12>

1 2

3

JCPUD

JCPUD

DDR_B_D[0..63]<11,13>

DDR_B_BS0<11,13>
DDR_B_BS1<11,13>
DDR_B_BS2<11,13>

DDR_B_CAS#<11,13>
DDR_B_RAS#<11,13>
DDR_B_WE#<11,13>

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

CONN@

CONN@

2

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

2

SB_CK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

1

M_CLK_DDR2

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_CLK_DDR#2
DDR_CKE2_DIMMB0

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB0

M_CLK_DDR6
M_CLK_DDR#6
DDR_CKE6_DIMMB1

M_CLK_DDR7
M_CLK_DDR#7
DDR_CKE7_DIMMB1

DDR_CS2_DIMMB0#
DDR_CS3_DIMMB0#
DDR_CS6_DIMMB1#
DDR_CS7_DIMMB1#

M_ODT2
M_ODT3
M_ODT6
M_ODT7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB0 <13>

M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB0 <13>

M_CLK_DDR6 <11>
M_CLK_DDR#6 <11>
DDR_CKE6_DIMMB1 <11>

M_CLK_DDR7 <11>
M_CLK_DDR#7 <11>
DDR_CKE7_DIMMB1 <11>

DDR_CS2_DIMMB0# <13>
DDR_CS3_DIMMB0# <13>
DDR_CS6_DIMMB1# <11>
DDR_CS7_DIMMB1# <11>

M_ODT2 <13>
M_ODT3 <13>
M_ODT6 <11>
M_ODT7 <11>

DDR_B_DQS#[0..7] <11,13>

DDR_B_DQS[0..7] <11,13>

DDR_B_MA[0..15] <11,13>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(3/6) DDR III

PROCESSOR(3/6) DDR III

PROCESSOR(3/6) DDR III

LA-8321P

LA-8321P

LA-8321P

1

of

6

of

6

of

6

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

5

4

3

2

1

CFG Straps for Processor

D D

JCPUE

CONN@

JCPUE

CONN@

T7 PAD~D@ T7 PAD~D@
T8 PAD~D@ T8 PAD~D@

T1 PAD~D@ T1 PAD~D@
T2 PAD~D@ T2 PAD~D@
T9 PAD~D@ T9 PAD~D@
T10 PAD~D@ T10 PAD~D@

T11 PAD~D@ T11 PAD~D@

T12 PAD~D@ T12 PAD~D@
T14 PAD~D@ T14 PAD~D@
T16 PAD~D@ T16 PAD~D@

T4 PAD~D@ T4 PAD~D@
T18 PAD~D@ T18 PAD~D@
T19 PAD~D@ T19 PAD~D@
T21 PAD~D@ T21 PAD~D@

T23 PAD~D@ T23 PAD~D@
T25 PAD~D@ T25 PAD~D@
T27 PAD~D@ T27 PAD~D@
T29 PAD~D@ T29 PAD~D@
T31 PAD~D@ T31 PAD~D@

T33 PAD~D@ T33 PAD~D@
T34 PAD~D@ T34 PAD~D@
T35 PAD~D@ T35 PAD~D@
T40 PAD~D@ T40 PAD~D@
T42 PAD~D@ T42 PAD~D@

T47 PAD~D@ T47 PAD~D@
T59 PAD~D@ T59 PAD~D@

CLK_RES_ITP <17>
CLK_RES_ITP# <17>

T60 PAD~D@ T60 PAD~D@
T61 PAD~D@ T61 PAD~D@
T63 PAD~D@ T63 PAD~D@

T64 PAD~D@ T64 PAD~D@

PEG Static Lane Reversal - CFG2 is for the 16x

Display Port Presence Strap

PCIE Port Bifurcation Straps

CFG[6:5]

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

KEY

CFG

CFG

RESERVED

RESERVED

VCC_DIE_SENSE
VSS_DIE_SENSE

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

CFG0<5>
CFG1<5>
CFG2<5>
CFG3<5>
CFG4<5>
CFG5<5>
CFG6<5>
CFG7<5>
CFG8<5>
CFG9<5>
CFG10<5>
CFG11<5>

CFG16<5>
CFG17<5>

1 2

@

@

RC123

RC123

50_0402_1%

50_0402_1%

+VCC_GFXCORE_AXG

@

@

RC122

RC122

50_0402_1%

50_0402_1%

1 2

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

1 2

1 2

@

@

RC121
50_0402_1%

50_0402_1%

+VCC_CORE

@

@

RC120

RC120
50_0402_1%

50_0402_1%

C C

INTEL 12/28 reco mmand
to add RC120, RC 121, RC122, RC123
Please place as close as JCPU1

B B

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11

T5PAD~D @T5PAD~D @
T20PAD~D @T20PAD~D @
T24PAD~D @T24PAD~D @
T22PAD~D @T22PAD~D @

CFG16
CFG17

VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE

T28PAD~D @T28PAD~D @

T36PAD~D @T36PAD~D @RC121
T37PAD~D @T37PAD~D @
T38PAD~D @T38PAD~D @
T39PAD~D @T39PAD~D @
T41PAD~D @T41PAD~D @
T43PAD~D @T43PAD~D @
T44PAD~D @T44PAD~D @
T45PAD~D @T45PAD~D @
T46PAD~D @T46PAD~D @
T48PAD~D @T48PAD~D @
T49PAD~D @T49PAD~D @
T50PAD~D @T50PAD~D @
T51PAD~D @T51PAD~D @
T53PAD~D @T53PAD~D @
T55PAD~D @T55PAD~D @
T56PAD~D @T56PAD~D @

T57PAD~D @T57PAD~D @
T58PAD~D @T58PAD~D @

T62PAD~D @T62PAD~D @

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SE NSE

AH31

VSSAXG_VAL _SENSE

AJ33

VCC_VAL_ SENSE

AH33

VSS_VAL_S ENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

Need PWR add new circuit on 1.05V(refer CRB)

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

CFG2

12

RC51

@RC51

@

1K_0402_1%

1K_0402_1%

1:(Default) Norm al Operation; L ane #

CFG2

definition match es socket pin m ap definition
0:Lane Reversed

CFG4

12

RC52

@RC52

@

1K_0402_1%

1K_0402_1%

1 : Disabled; No Physical Displ ay Port

CFG4

attached to Embe dded Display Po rt

0 : Enabled; An external Displa y Port device is
connected to the Embedded Displ ay Port

CFG6

CFG5

12

12

RC54

1K_0402_1%

1K_0402_1%

RC54

RC53

@RC53

@

1K_0402_1%

1K_0402_1%

11: (Default) x1 6 - Device 1 fu nctions 1 and 2 disabled

10: x8, x8 - Dev ice 1 function 1 enabled ; func tion 2
disabled
01: Reserved - ( Device 1 functi on 1 disabled ; function
2 enabled)
00: x8,x4,x4 - D evice 1 functio ns 1 and 2 enabl ed

CFG7

12

RC56

@RC56

@

1K_0402_1%

1K_0402_1%

PEG DEFER TRAINING

1: (Default) PEG Train immediat ely

CFG7

following xxRESE TB de assertion

A A

0: PEG Wait for BIOS for traini ng

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD ,CFG

PROCESSOR(4/6) RSVD ,CFG

PROCESSOR(4/6) RSVD ,CFG

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

of

7

of

7

of

7

5

4

JCPUF

CONN@

JCPUF

CONN@

3

POWER

POWER

2

1

+VCC_CORE

AG35

D D

C C

B B

A A

5

4

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32

PEG AND DDR

PEG AND DDR

VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_ VCCIO

SENSE LINES SVID

SENSE LINES SVID

VIDSOUT

CORE SUPPLY

CORE SUPPLY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9

8.5A94A

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

H_CPU_SVIDDAT

AJ28

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

VCCIO_SENSE

B10

VSSIO_SENSE

A10

VCCIO_SENSE
VSSIO_SENSE

0902 RC1701 and RC1702 near close to CPU,
ask power to remove PR111 and PR104

+VCCP

PDDG 0.7@P12

RC61 43_0402_1%RC61 43_0402_1%

1 2

RC59 0_0402_5%~D@RC59 0_0402_5%~D@

1 2

RC65 0_0402_5%~D@RC65 0_0402_5%~D@

1 2

RC67 0_0402_5%~D@RC67 0_0402_5%~D@

1 2

RC68 0_0402_5%~D@RC68 0_0402_5%~D@

1 2

VCCIO_SENSE <49>

RC1701 10_0402_5%~DRC1701 10_0402_5%~D
RC1702 10_0402_5%~DRC1702 10_0402_5%~D

1 2
1 2

130_0402_1%

130_0402_1%

2

RC63

RC63

+VCCP

Place the PU

12

+VCCP

resistors close to CPU

12

RC60

RC60

75_0402_1%

75_0402_1%

VR_SVID_ALRT# <53,55>
VR_SVID_CLK <53,55>
VR_SVID_DAT <53,55>

+VCC_CORE

12

RC66

RC66
100_0402_1%

100_0402_1%

VCCSENSE <53>
VSSSENSE <53>

12

RC70

RC70

100_0402_1%

100_0402_1%

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

PROCESSOR(5/6) PWR,BYPASS

LA-8321P

LA-8321P

LA-8321P

8

8

8

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

of

of

of

5

4

3

2

1

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

QC3

QC3

AO4728L_SO8~D

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_V ID[0]
VCCSA_V ID[1]

VCCIO_SEL

AO4728L_SO8~D

8
7
6
5

4

12

1

RC75

RC75

2

330K_0402_5%~D

330K_0402_5%~D

AK35
AK34

+V_SM_VREF should
have 10 mil trace width

AL1

B4
D1

5A

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

6A

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

H_VCCP_SEL

A19

0.1U_0603_50V7K~D

0.1U_0603_50V7K~D

1
2
3

CC136

CC136

H_FC_C22

1

2

CC135

CC135

10U_0805_25V6K~D

10U_0805_25V6K~D

1

2

12

RC73

RC73

VCC_AXG_SENSE <55>
VSS_AXG_SENSE <55>

+V_SM_VREF_CNT

+V_DDR_REFA_R <10>
+V_DDR_REFB_R <11>

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

1

CC161

CC161

CC162

CC162

2

10U_0805_25V6K~D

10U_0805_25V6K~D

1

CC168

CC168

2

RC55

@RC55

@

1 2

0_0402_5%~D

0_0402_5%~D

20K_0402_5%

20K_0402_5%

1

2

1

2

+1.5V_CPU_VDDQ

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

1

CC163

CC163

2

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

1

CC169

CC169

2

VCCP_PWRCTRL <49>

CC164

CC164

CC170

CC170

12

1K_0402_1%~D

1K_0402_1%~D

12

1K_0402_1%~D

1K_0402_1%~D

10U_0805_25V6K~D

10U_0805_25V6K~D

1

CC165

CC165

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@

@

1

CC171

CC171

2

RC118

RC118

RC119

RC119

+1.5V_CPU_VDDQ

10U_0805_25V6K~D

10U_0805_25V6K~D

1

1

CC166

CC166

+

+

CC167

CC167

330U_D2_2.5VM_R6M~D

330U_D2_2.5VM_R6M~D

2

2

1

+

+

CC172

CC172
330U_D2_2.5VM_R6M~D

330U_D2_2.5VM_R6M~D

<BOM Structure>

<BOM Structure>

2

12

@ RC81

@

0_0402_5%

0_0402_5%

+V_SM_VREF_CNT

QC5
Follow E3
Macallan 13"

CC149 0.1U_0402_25V6K~DCC149 0.1U_0402_25V6K~D

CC150 0.1U_0402_25V6K~DCC150 0.1U_0402_25V6K~D

CC178 0.1U_0402_25V6K~DCC178 0.1U_0402_25V6K~D

CC182 0.1U_0402_25V6K~DCC182 0.1U_0402_25V6K~D

@PJP30

@

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

PJP30 OPEN

<BOM Structure>

<BOM Structure>

+VCCSA

VCCSA_SENSE <52>

H_FC_C22 <52>
VCCSA_SEL <52>

RC81

12

12

12

12

PJP30

+1.5V

JCPUH

CONN@

JCPUH

CONN@

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

B+_BIAS+3VALW

5

G

G

POWER

POWER

CONN@

CONN@

GRAPHICS

GRAPHICS

1.8V RAIL

1.8V RAIL

12

RC72

RC72
100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3

D

D

S

S

4 3

QC4B

QC4B
DMN66D0LDW-7

DMN66D0LDW-7

RUN_ON_CPU1.5VS3# <5,42>

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

VREFMISC

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_S ENSE

12

RC74

RC74
100K_0402_5%

100K_0402_5%

D D

RC77 0_0402_5%@RC77 0_0402_5%@

PJP31

PJP31
PAD-OPEN 4x4m

PAD-OPEN 4x4m

1 2

RC79 0_0402_5%~D@RC79 0_0402_5%~D@

1 2

1 2

330U_D2_2.5VM_R6M~D

330U_D2_2.5VM_R6M~D

1

+

+

2

PJP33

PJP33
PAD-OPEN 4x4m

PAD-OPEN 4x4m

1 2

CC176

CC176

+1.8VS_VCCPLL

10U_0805_25V6K~D

10U_0805_25V6K~D

1

1

CC173

CC173

2

2

SUSP#<21,40,42,43,49,50,51>

CPU1.5V_S3_GATE<40>

+VCC_GFXCORE_AXG_P

C C

B B

+VCC_GFXCORE_AXG +VCC_GFXCORE_AXG +VCC_GFXCORE_AXG

+1.8VS

RC80 0_0805_5%~D@RC80 0_0805_5%~D@

1 2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

G

G

CC174

CC174

RUN_ON_CPU1.5VS3#

D

D

S

S

1 6

PJP34

PJP34
PAD-OPEN 4x4m

PAD-OPEN 4x4m

1 2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CC175

CC175

2

QC4A

QC4A

DMN66D0LDW-7

DMN66D0LDW-7

33A

AT24
AT23
AT21
AT20
AT18

AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17

AM24
AM23
AM21
AM20
AM18
AM17

AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17

AJ24

AJ23

AJ21

AJ20

AJ18

AJ17
AH24
AH23
AH21
AH20
AH18
AH17

JCPUG

JCPUG

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

TBD

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

PROCESSOR(6/6) PWR,VSS

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

of

9

of

9

of

9

5

4

3

2

1

RD7

RD7

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

R1831

R1831

RD2

@ RD2

@

RD8

RD8

+3VS

1 2

1 2

+1.5V

12

12

@ R1832

@

10K_0402_5%~D

10K_0402_5%~D

1 2

RD3

RD3
10K_0402_5%~D

10K_0402_5%~D

1 2

R1832

DDR_A_DQS#[0..7]<6,12>

DDR_A_DQS[0..7]<6,12>

DDR_A_D[0..63]<6,12>

DDR_A_MA[0..15]<6,12>

M3 Circuit (Proce ssor Generated SO-DIMM VREF_DQ)

D D

+V_DDR_REFA

DRAMRST_CNTRL_PCH<6,11,17>

C C

B B

+0.75VS

A A

RD15 0_0402_5%~D@RD15 0_0402_5%~D@

1 2

QD1

QD1
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

D

S

D

S

1 3

G

G

2

Layout Note:
Place near JDIMM A

+1.5V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD3

CD3

1

1

2

2

+1.5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD7

CD7

CD8

CD8

1

1

2

2

Layout Note:
Place near JDIMM A.203,204

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD17

CD17

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD4

CD4

CD5

CD5

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD9

CD9

CD10

CD10

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD19

CD19

CD18

CD18

2

+V_DDR_REFA_R <9>

12

RD16

RD16
1K_0402_5%~D

1K_0402_5%~D

@

@

CD6

CD6

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD11

CD11

CD12

CD12

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD20

CD20

330U_SX_2VY~D

330U_SX_2VY~D

@

@

1

CD13

CD13

CD14

CD14

1

+

+

2

2

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

+3VS

1

2

DDR_CKE4_DIMMA1<6>

DDR_CS5_DIMMA1#<6>

+V_DDR_REFA

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD1

CD1

DDR_A_BS2<6,12>

M_CLK_DDR4<6>
M_CLK_DDR#4<6>

DDR_A_BS0<6,12>

DDR_A_WE#<6,12>
DDR_A_CAS#<6,12>

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

12

RD1

RD1
0_0402_5%~D

0_0402_5%~D

@

@

+DIMM0_VREF

DDR_A_D4
DDR_A_D5

1

CD2

CD2

DDR_A_D2

2

DDR_A_D7

DDR_A_D8

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D15

DDR_A_D21
DDR_A_D20

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D19
DDR_A_D18

DDR_A_D28 DDR_A_D31
DDR_A_D29

DDR_A_D26
DDR_A_D27

DDR_CKE4_DIMMA1 DDR_CKE5_DIMMA1

DDR_A_BS2

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR4
M_CLK_DDR#4

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS5_DIMMA1#

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D39

DDR_A_D41
DDR_A_D40

DDR_A_D42
DDR_A_D43

DDR_A_D48 DDR_A_D53
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55
DDR_A_D54

DDR_A_D61

DDR_A_D63
DDR_A_D62

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

+0.75VS

CD21

CD21

CD22

CD22

1

1

2

2

JDIMMA0

JDIMMA0

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18
DQ1953VSS19

55

VSS20

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013311-1

TYCO_2-2013311-1

CONN@

CONN@

DQ4
DQ5

VSS3

DQS0

VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

VTT2

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

SCL

G2

CIS link OK

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

+1.5V+1.5V

DDR_A_D1
DDR_A_D0

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D3
DDR_A_D6

DDR_A_D12
DDR_A_D13DDR_A_D9

DDR3_DRAMRST#

DDR_A_D14
DDR_A_D11

DDR_A_D17
DDR_A_D16

DDR_A_D22
DDR_A_D23

DDR_A_D24

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D25

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9

DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR5
M_CLK_DDR#5

DDR_A_BS1
DDR_A_RAS#

DDR_CS4_DIMMA1#
M_ODT4

M_ODT5

DDR_A_D32
DDR_A_D33

DDR_A_D35
DDR_A_D38

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52

DDR_A_D51
DDR_A_D50

DDR_A_D56
DDR_A_D57DDR_A_D60

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D59
DDR_A_D58

M_THERMAL#
PCH_SMBDATA
PCH_SMBCLK

+0.75VS

DIMM A0
REV TYPE (H9.2)

DDR3_DRAMRST# <6,11,12,13>

CPU

DDR_CKE5_DIMMA1 <6>

M_CLK_DDR5 <6>
M_CLK_DDR#5 <6>

DDR_A_BS1 <6,12>
DDR_A_RAS# <6,12>

DDR_CS4_DIMMA1# <6>
M_ODT4 <6>

M_ODT5 <6>

+VREF_CA

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

1

CD15

CD15

2

M_THERMAL# <11,12,13,40>

PCH_SMBDATA <5,11,12,13,16,17,34,35,43>
PCH_SMBCLK <5,11,12,13,16,17,34,35,43>

CH A1

TOP

BOT

CH B0

CH A0 (Std)

+1.5V

12

RD9

RD9

1K_0402_1%

1K_0402_1%

12

RD10

1

2

RD10
1K_0402_1%

1K_0402_1%

CD16

CD16

(H9.2)

(H5.2)CH B1

(H5.2)

(H9.2)

(Rev)

(Rev)

(Std)

DIMM A0

DIMM B0

DIMM B1

DIMM A1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMA0

DDRIII DIMMA0

DDRIII DIMMA0

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

of

10

of

10

of

10

5

DDR_B_DQS#[0..7]<6,13>

DDR_B_DQS[0..7]<6,13>

DDR_B_D[0..63]<6,13>

DDR_B_MA[0..15]<6,13>

D D

M3 Circuit (Proce ssor Generated SO-DIMM VREF_DQ)

RD17 0_0402_5%~D@RD17 0_0402_5%~D@

1 2

QD2

QD2
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

D

S

D

S

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD26

CD26

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD31

CD31

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD40

CD40

2

5

1 3

G

G

2

Layout Note:
Place near JDIMM B

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD27

CD27

CD28

CD28

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD33

CD33

CD32

CD32

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

CD34

CD34

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD42

CD42

CD41

CD41

2

+V_DDR_REFB_R <9>

12

RD18

RD18
1K_0402_5%~D

1K_0402_5%~D

@

@

330U_SX_2VY~D

330U_SX_2VY~D

@

@

1

CD35

CD35

CD36

CD36

1

+

+

2

2

+V_DDR_REFB

DRAMRST_CNTRL_PCH<6,10,17>

C C

B B

A A

+1.5V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD25

CD25

1

2

+1.5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD30

CD30

CD29

CD29

1

1

2

2

Layout Note:
Place near JDIMM B.203,204

+0.75VS

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD39

CD39

2

4

RD11

RD11

1K_0402_1%~D

1K_0402_1%~D

RD12

RD12

1K_0402_1%~D

1K_0402_1%~D

10K_0402_5%~D

10K_0402_5%~D

@ RD6

@

10K_0402_5%~D

10K_0402_5%~D

4

3

+1.5V

12

12

+3VS

RD5

RD5

R1833

R1833

10K_0402_5%~D

10K_0402_5%~D

1 2

1 2

12

RD6

10K_0402_5%~D

10K_0402_5%~D

1 2

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

@R1834

@

R1834

1

2

CD23

CD23

DDR_CKE6_DIMMB1<6>

DDR_CS7_DIMMB1#<6>

+3VS

+V_DDR_REFB

12

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

2

DDR_B_BS2<6,13>

M_CLK_DDR6<6>
M_CLK_DDR#6<6>

DDR_B_BS0<6,13>

DDR_B_WE#<6,13>
DDR_B_CAS#<6,13>

RD4

RD4

0_0402_5%~D

0_0402_5%~D

@

@

CD24

CD24

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

+1.5V

JDIMMB0

+DIMM1_VREF

DDR_B_D5 DDR_B_D0
DDR_B_D4

DDR_B_D7
DDR_B_D3

DDR_B_D13
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D14
DDR_B_D15

DDR_B_D21
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D23
DDR_B_D22

DDR_B_D28
DDR_B_D24

DDR_B_D30
DDR_B_D31

DDR_CKE6_DIMMB1

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR6
M_CLK_DDR#6

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS7_DIMMB1#

DDR_B_D37
DDR_B_D36

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D47

DDR_B_D43
DDR_B_D44

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55
DDR_B_D51

DDR_B_D61
DDR_B_D57

DDR_B_D63

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

+0.75VS

CD43

CD43

CD44

CD44

1

1

2

2

JDIMMB0

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013290-1

TYCO_2-2013290-1

CONN@

CONN@

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1
CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

A15
A14

A7

A6
A4

A2
A0

BA1

S0#

G2

CIS link OK

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

+1.5V

DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D6

DDR_B_D8
DDR_B_D12

DDR3_DRAMRST#

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D16

DDR_B_D19
DDR_B_D18

DDR_B_D29
DDR_B_D25

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D26
DDR_B_D27

DDR_CKE7_DIMMB1

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR7
M_CLK_DDR#7

DDR_B_BS1
DDR_B_RAS#

DDR_CS6_DIMMB1#
M_ODT6

M_ODT7

DDR_B_D32
DDR_B_D33

DDR_B_D38
DDR_B_D39

DDR_B_D41
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D42

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D50

DDR_B_D60
DDR_B_D56

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D58DDR_B_D59

M_THERMAL#
PCH_SMBDATA
PCH_SMBCLK

+0.75VS

DDR3_DRAMRST# <6,10,12,13>

DDR_CKE7_DIMMB1 <6>

M_CLK_DDR7 <6>
M_CLK_DDR#7 <6>

DDR_B_BS1 <6,13>
DDR_B_RAS# <6,13>

DDR_CS6_DIMMB1# <6>
M_ODT6 <6>

M_ODT7 <6>

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

M_THERMAL# <10,12,13,40>

PCH_SMBDATA <5,10,12,13,16,17,34,35,43>
PCH_SMBCLK <5,10,12,13,16,17,34,35,43>

2

DIMM B0
REV TYPE (H5.2)

TOP

BOT

CH B0

CH A0 (Std)

+1.5V

12

RD13

RD13

1K_0402_1%

1K_0402_1%

12

RD14

RD14
1K_0402_1%

1K_0402_1%

CD38

CD38

+VREF_CB

1

CD37

CD37

2

CPU

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

2

2

1

(H9.2)CH A1

(H5.2)CH B1

(H5.2)

(H9.2)

(Rev)

(Rev)

(Std)

DIMM A0

DIMM B0

DIMM B1

DIMM A1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMB0

DDRIII DIMMB0

DDRIII DIMMB0

LA-8321P

LA-8321P

LA-8321P

1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

of

11

of

11

of

11

0.1

0.1

0.1

5

DDR_A_DQS#[0..7]<6,10>

DDR_A_DQS[0..7]<6,10>

DDR_A_D[0..63]<6,10>

DDR_A_MA[0..15]<6,10>

D D

Layout Note:
Place near JDIMM C

+1.5V

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD53

CD53

CD54

CD54

1

1

2

2

C C

+1.5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

B B

A A

+0.75VS

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD57

CD57

CD58

CD58

1

1

2

2

Layout Note:
Place near JDIMM C.203,204

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD67

CD67

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

CD68

CD68

CD56

CD56

CD55

CD55

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD60

CD60

CD59

CD59

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD69

CD69

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD62

CD62

CD61

CD61

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD70

CD70

@ CD63

@

CD63

1

2

330U_SX_2VY~D

330U_SX_2VY~D

1

+

+

2

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

CD64

CD64

RD32

@RD32

@

RD53

RD53

RD28

RD28

RD29

RD29

4

12

12

+1.5V

+3VS

1 2

1 2

12

12

R1835

@R1835

@

10K_0402_5%~D

10K_0402_5%~D

+3VS

RD33

RD33
10K_0402_5%~D

10K_0402_5%~D

3

+V_DDR_REFA

12

RD27

RD27
0_0402_5%~D

0_0402_5%~D

@

@

+DIMM3_VREF

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

1

CD51

CD51

2

DDR_CKE0_DIMMA0<6>

DDR_A_BS2<6,10>

M_CLK_DDR0<6>
M_CLK_DDR#0<6>

DDR_A_BS0<6,10>

DDR_A_WE#<6,10>
DDR_A_CAS#<6,10>

DDR_CS1_DIMMA0#<6>

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

DDR_A_D4
DDR_A_D5

1

CD52

CD52

DDR_A_D2

2

DDR_A_D7

DDR_A_D8
DDR_A_D9 DDR_A_D13

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D15

DDR_A_D21
DDR_A_D20

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D19
DDR_A_D18

DDR_A_D28
DDR_A_D29

DDR_A_D26 DDR_A_D30
DDR_A_D27 DDR_A_D25

DDR_CKE0_DIMMA0 DDR_CKE1_DIMMA0

DDR_A_BS2

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA0#

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D39

DDR_A_D41
DDR_A_D40

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55
DDR_A_D54

DDR_A_D60
DDR_A_D61

DDR_A_D63
DDR_A_D62

+0.75VS

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

CD72

CD72

CD71

CD71

1

1

2

2

JDIMMA1

JDIMMA1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2
VSS1849DQ22

51

DQ18

53

DQ19
VSS2055DQ28

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

G1

TYCO_2-2013310-1

TYCO_2-2013310-1

CONN@

CONN@

VREF_CA

127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

205

CIS link OK

VSS3

DQS0
VSS6

VSS8
DQ12
DQ13

VSS10

DQ14
DQ15

DQ20
DQ21

VSS17

DQ23

VSS19

DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

+1.5V+1.5V

2

DDR_A_D1

4

DDR_A_D0

6

8

DDR_A_DQS#0

10

DDR_A_DQS0

12

14

DDR_A_D3

16

DDR_A_D6

18

20

DDR_A_D12

22

24

26

28

DDR3_DRAMRST#

30

32

DDR_A_D14

34

DDR_A_D11

36

38

DDR_A_D17

40

DDR_A_D16

42

44

46

48

DDR_A_D22

50

DDR_A_D23

52

54

DDR_A_D24

56

DDR_A_D31

58

60

DDR_A_DQS#3

62

DDR_A_DQS3

64

66

68

70

72

74

76

DDR_A_MA15

78

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

80

82

84

86

88

90

92

94

96

98

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

202

204

206

DDR_A_MA14

DDR_A_MA11DDR_A_MA12
DDR_A_MA7DDR_A_MA9

DDR_A_MA6DDR_A_MA8
DDR_A_MA4DDR_A_MA5

DDR_A_MA2
DDR_A_MA0

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA0#
M_ODT0

M_ODT1

DDR_A_D32
DDR_A_D33

DDR_A_D35
DDR_A_D38

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D53
DDR_A_D52

DDR_A_D51
DDR_A_D50

DDR_A_D56
DDR_A_D57

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D59
DDR_A_D58

M_THERMAL#
PCH_SMBDATA
PCH_SMBCLK

+0.75VS

DDR_CKE1_DIMMA0 <6>

M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>

DDR_A_BS1 <6,10>
DDR_A_RAS# <6,10>

DDR_CS0_DIMMA0# <6>
M_ODT0 <6>

M_ODT1 <6>

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

M_THERMAL# <10,11,13,40>

PCH_SMBDATA <5,10,11,13,16,17,34,35,43>
PCH_SMBCLK <5,10,11,13,16,17,34,35,43>

2

DIMM A1
STD TYPE (H9.2)

DDR3_DRAMRST# <6,10,11,13>

CPU

+VREF_CC

1

2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD65

CD65

TOP

BOT

CH B0

CH A0 (Std)

+1.5V

12

RD30

RD30

1K_0402_1%

1K_0402_1%

12

RD31

1

CD66

CD66

2

RD31

1K_0402_1%

1K_0402_1%

(H9.2)CH A1

(H5.2)CH B1

(H5.2)

(H9.2)

(Rev)

(Rev)

(Std)

1

DIMM A0

DIMM B0

DIMM B1

DIMM A1

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMA1

DDRIII DIMMA1

DDRIII DIMMA1

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

of

12

of

12

of

12

5

DDR_B_DQS#[0..7]<6,11>

D D

DDR_B_DQS[0..7]<6,11>

DDR_B_D[0..63]<6,11>

DDR_B_MA[0..15]<6,11>

Layout Note:
Place near JDIMM D

+1.5V

C C

B B

A A

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD78

CD78

CD79

CD79

1

1

2

2

+1.5V

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD82

CD82

1

2

Layout Note:
Place near JDIMM D.203,204

+0.75VS

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD83

CD83

CD84

CD84

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD92

CD92

CD93

CD93

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CD81

CD81

CD80

CD80

1

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD85

CD85

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

10U_0603_6.3V6M~D

330U_SX_2VY~D

330U_SX_2VY~D

@ CD88

@

1

CD87

CD87

CD88

CD89

CD86

CD86

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD95

CD95

CD94

CD94

2

CD89

1

+

+

2

2

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

RD41

RD41

1K_0402_1%~D

1K_0402_1%~D

RD42

RD42

1K_0402_1%~D

1K_0402_1%~D

RD54

@RD54

@

RD46

RD46

4

+1.5V

12

12

12

12

+3VS

1 2

12

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

1

2

R1836

R1836
10K_0402_5%~D

10K_0402_5%~D

+3VS

RD45

@RD45

@

10K_0402_5%~D

10K_0402_5%~D

CD76

CD76

DDR_CKE2_DIMMB0<6>

DDR_B_BS2<6,11>

M_CLK_DDR2<6>
M_CLK_DDR#2<6>

DDR_B_BS0<6,11>

DDR_B_WE#<6,11>
DDR_B_CAS#<6,11>

DDR_CS3_DIMMB0#<6>

+V_DDR_REFB

12

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

2

3

RD40

RD40
0_0402_5%~D

0_0402_5%~D

@

@

CD77

CD77

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

2

+1.5V

JDIMMB1

+DIMM4_VREF

DDR_B_D4

DDR_B_D7

DDR_B_D13
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D14

DDR_B_D21
DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D23
DDR_B_D22

DDR_B_D28
DDR_B_D24

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB0

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS3_DIMMB0#

DDR_B_D37
DDR_B_D36

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D47

DDR_B_D43
DDR_B_D44

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55
DDR_B_D51

DDR_B_D61
DDR_B_D57

DDR_B_D63
DDR_B_D59 DDR_B_D58

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

+0.75VS

CD96

CD96

CD97

CD97

1

2

JDIMMB1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013289-1

TYCO_2-2013289-1

CONN@

CONN@

DQ4
DQ5

VSS3

DQS#0

DQS0
VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1

CK1#

VDD12

BA1
RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35
DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47
DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL

VTT2

A15
A14

A11

A7

A6
A4

A2
A0

S0#

G2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

+1.5V

DDR_B_D1
DDR_B_D0DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D6DDR_B_D3

DDR_B_D8
DDR_B_D12

DDR3_DRAMRST#

DDR_B_D10
DDR_B_D11DDR_B_D15

DDR_B_D17
DDR_B_D16

DDR_B_D19
DDR_B_D18

DDR_B_D29
DDR_B_D25

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D26
DDR_B_D27

DDR_CKE3_DIMMB0

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS2_DIMMB0#
M_ODT2

M_ODT3

DDR_B_D32
DDR_B_D33

DDR_B_D38
DDR_B_D39

DDR_B_D41
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D42

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D50

DDR_B_D60
DDR_B_D56

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62

M_THERMAL#
PCH_SMBDATA
PCH_SMBCLK

+0.75VS

2

DIMM B1
STD TYPE (H5.2)

DDR3_DRAMRST# <6,10,11,12>

CPU

DDR_CKE3_DIMMB0 <6>

M_CLK_DDR3 <6>
M_CLK_DDR#3 <6>

DDR_B_BS1 <6,11>
DDR_B_RAS# <6,11>

DDR_CS2_DIMMB0# <6>
M_ODT2 <6>

M_ODT3 <6>

+VREF_CD

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2.2U_0603_10V7K~D

2.2U_0603_10V7K~D

1

2

M_THERMAL# <10,11,12,40>

PCH_SMBDATA <5,10,11,12,16,17,34,35,43>
PCH_SMBCLK <5,10,11,12,16,17,34,35,43>

1

CD90

CD90

2

1

(H9.2)CH A1

TOP

BOT

CH B0

CH A0 (Std)

+1.5V

12

RD43

RD43

1K_0402_1%

1K_0402_1%

12

RD44

RD44

1K_0402_1%

1K_0402_1%

CD91

CD91

(H5.2)CH B1

(H5.2)

(H9.2)

(Rev)

(Rev)

(Std)

DIMM A0

DIMM B0

DIMM B1

DIMM A1

CIS link OK

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

DDRIII DIMMB1

DDRIII DIMMB1

DDRIII DIMMB1

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

of

13

of

13

of

13

5

+3V_MXM

1

2

D D

C C

B B

A A

R98

@ R98

@

1 2

0_0805_5%~D

0_0805_5%~D

C226

C226

4.7U_0603_10V6K~D

4.7U_0603_10V6K~D

+3VMXM

10U_0805_25V6K~D

10U_0805_25V6K~D

C223

C223

1

2

+5V_MXM

PJP9

PJP9

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

C227

C227

1

2

160mil(4A)

68P_0402_50V8 J~D

68P_0402_50V8 J~D

1

2

2

C228

C228

C225

C225

+5V_MXM

JUMP_43X118

JUMP_43X118

B+_MXM

0.1U_0603_50V7K~D

0.1U_0603_50V7K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

680P_0402_50V 7K~D

680P_0402_50V 7K~D

C224

C224

1

2

100mil(2.5A, 5VIA)

Add R90 increase NV MXM PEG Swing

+3V_MXM

R94

R94

10K_0402_5%~D

10K_0402_5%~D

VGA_TH_OVERT#<15> TH_OVERT# <40>

R90 0_0402_5%~D@ R90 0_040 2_5%~D@

1 2

+3VALW+3V_MX M1

12

R105

R105

10K_0402_5%~D

10K_0402_5%~D

VGA_DISABLE#

VGA_HDMI_CEC

VGA_LCD_DAT
VGA_LCD_CLK

DGPU_ENVDD<24>
DGPU_BKL_EN<24>
VGA_PNL_PWM<24>

VGA_LCD_DAT<24>
VGA_LCD_CLK<24>

LVDS DDC Module have 4.7K Pull-UP

R92 10K_0402_5%~D@R92 10K_0402_5%~D@

1 2

R93 36K_0402_1%@R93 36K_0402_1%@

1 2

12

G

G

2

13

D

S

D

S

Q7

Q7
2N7002E-T1-E3_SOT23-3

2N7002E-T1-E3_SOT23-3

PEG_GTX_HRX_N7<4>
PEG_GTX_HRX_P7<4>

PEG_GTX_HRX_N6<4>
PEG_GTX_HRX_P6<4>

PEG_GTX_HRX_N5<4>
PEG_GTX_HRX_P5<4>

PEG_GTX_HRX_N4<4>
PEG_GTX_HRX_P4<4>

PEG_GTX_HRX_N3<4>
PEG_GTX_HRX_P3<4>

5

+5VMXM

112

JMXM1A

JMXM1A

1

PWR_SRC

3

PWR_SRC

5

PWR_SRC

7

PWR_SRC

9

E1 E2

E1 E2

PWR_SRC

11

PWR_SRC

13

PWR_SRC

15

PWR_SRC

17

PWR_SRC

19

C222

C222

2

1

GND

21

GND

23

GND

25

GND

27

GND

29

E3 E4

E3 E4

GND

31

GND

33

GND

35

GND

37

5V

39

5V

41

5V

43

5V

45

5V

47

GND

49

GND

51

GND

53

GND

55

PEX_STD_SW#

57

VGA_DISABLE#

59

PNL_PWR_EN

61

PNL_BL_EN

63

PNL_BL_PWM

65

HDMI_CEC

67

DVI_HPD

69

LVDS_DDC_DAT

71

LVDS_DDC_CLK

73

GND

75

OEM

77

OEM

79

OEM

81

OEM

83

GND

85

PEX_RX15#

87

PEX_RX15

89

GND

91

PEX_RX14#

93

PEX_RX14

95

GND

97

PEX_RX13#

99

PEX_RX13

101

GND

103

PEX_RX12#

105

PEX_RX12

107

GND

109

PEX_RX11#

111

PEX_RX11

113

GND

115

PEX_RX10#

117

PEX_RX10

119

GND

121

PEX_RX9#

123

PEX_RX9

125

GND

127

PEX_RX8#

129

PEX_RX8

131

GND

133

PEX_RX7#

135

PEX_RX7

137

GND

139

PEX_RX6#

141

PEX_RX6

143

GND

145

PEX_RX5#

147

PEX_RX5

149

GND

151

PEX_RX4#

153

PEX_RX4

155

GND

157

PEX_RX3#

159

PEX_RX3

161

GND

JAE_MM70-314-310B1-1-R300

JAE_MM70-314-310B1-1-R300

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC

GND
GND
GND
GND
GND
GND
GND
GND
GND

PRSNT_R#

WAKE#

PWR_GOOD

PWR_EN

RSVD
RSVD
RSVD
RSVD

PWR_LEVEL

TH_OVERT#
TH_ALERT#

TH_PWM

GPIO0
GPIO1

GPIO2
SMB_DAT
SMB_CLK

GND
OEM
OEM
OEM
OEM
GND

PEX_TX15#

PEX_TX15

GND

PEX_TX14#

PEX_TX14

GND

PEX_TX13#

PEX_TX13

GND

PEX_TX12#

PEX_TX12

GND

PEX_TX11#

PEX_TX11

GND

PEX_TX10#

PEX_TX10

GND

PEX_TX9#

PEX_TX9

GND

PEX_TX8#

PEX_TX8

GND

PEX_TX7#

PEX_TX7

GND

PEX_TX6#

PEX_TX6

GND

PEX_TX5#

PEX_TX5

GND

PEX_TX4#

PEX_TX4

GND

PEX_TX3#

PEX_TX3

GND

VGA_DDC_CLK
VGA_DDC_DATA

VGA_HDMI_CEC
VGA_DISABLE#
VGA_WAKE#

VGA_LCD_CLK
VGA_LCD_DAT
DGPU_PWROK

4

B+_MXM

2
4
6
8
10
12
14
16
18

20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160

R1826 2.2K_0402_5%~D

R1826 2.2K_0402_5%~D
R1827 2.2K_0402_5%~D

R1827 2.2K_0402_5%~D

R100 10K_0402_ 5%~D R100 10K_0402 _5%~D
R101 10K_0402_ 5%~D@R101 10K_0402_5%~D@
R102 10K_0402_ 5%~D@R102 10K_0402_5%~D@

R95 4.3K_0402_5% R95 4.3K_0402_5%
R96 4.3K_0402_5% R96 4.3K_0402_5%
R97 10K_0402_5%~D R97 10K_0402_5%~D

4

MXM_PS_0
MXM_PS_1
MXM_PS_2

(Pull-UP 10K at PCH)

VGA_PRSNT_R#
VGA_WAKE#
DGPU_PWROK
VGA_ON

AC_BATT#
VGA_TH_OVERT#

1 2

R91 10K_0402_5%~DR91 1 0K_0402_5%~D

VGA_SMB_DA1
VGA_SMB_CK1

MXM_PS_0
MXM_PS_1
MXM_PS_2

1 2
1 2

1 2
1 2
1 2

1 2
1 2

12

ACIN<18,37,40,43,47>

EC_AC_BAT#<40>

C2029 0.01U_0402_16V7K~D@ C2029 0.01U_0402 _16V7K~D@

1 2

C2031 0.01U_0402_16V7K~D@ C2031 0.01U_0402 _16V7K~D@

1 2

C2030 0.01U_0402_16V7K~D@ C2030 0.01U_0402 _16V7K~D@

1 2

VGA_PRSNT_R# <20>

DGPU_PWROK <20>
VGA_ON <15,17>

+3V_MXM

TO EC

+3VMXM

12

R2588

R2588

R2587

R2587

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

@

@

@

@

12

R2590

R2590

R2591

R2591

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

@

@

@

@

PEG_HTX_C_GRX_N7 <4>
PEG_HTX_C_GRX_P7 <4>

PEG_HTX_C_GRX_N6 <4>
PEG_HTX_C_GRX_P6 <4>

PEG_HTX_C_GRX_N5 <4>
PEG_HTX_C_GRX_P5 <4>

PEG_HTX_C_GRX_N4 <4>
PEG_HTX_C_GRX_P4 <4>

PEG_HTX_C_GRX_N3 <4>
PEG_HTX_C_GRX_P3 <4>

+3V_MXM

+3VALW

5

1

B

2

A

3

VGA_TH_OVERT# <15>

12

12

R2589

R2589

0_0402_5%~D

0_0402_5%~D

@

@

12

12

R2592

R2592

0_0402_5%~D

0_0402_5%~D

@

@

3

1

C1823

C1823

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2

U618

U618

4

Y

VCC
G

MC74VHC1G09DFT2G_SC70-5

MC74VHC1G09DFT2G_SC70-5

CLK_PEG_PCH#<17>
CLK_PEG_PCH<17>

MXM_PS_0
MXM_PS_1
MXM_PS_2

AC_BATT#

+3V_MXM

1 2

R103 0_0402_5%~D@ R103 0_0402_5%~D@
R104 0_0402_5%~D@ R104 0_0402_5%~D@

LVDS

HDMI

DMC

R88

R88
10K_0402_5%~D

10K_0402_5%~D

1 2
1 2

AC_BATT# <15>

PEG_GTX_HRX_N2<4>
PEG_GTX_HRX_P2<4>

PEG_GTX_HRX_N1<4>
PEG_GTX_HRX_P1<4>

PEG_GTX_HRX_N0<4>
PEG_GTX_HRX_P0<4>

VGA_TZCLK-<24>
VGA_TZCLK+<24>

VGA_TZOUT2-<24>
VGA_TZOUT2+<24>

VGA_TZOUT1-<24>
VGA_TZOUT1+<24>

VGA_TZOUT0-<24>
VGA_TZOUT0+<24>

GPU_HDMI_TXD2-<27>
GPU_HDMI_TXD2+<27>

GPU_HDMI_TXD1-<27>
GPU_HDMI_TXD1+<27>

GPU_HDMI_TXD0-<27>
GPU_HDMI_TXD0+<27>

GPU_HDMI_TXC-<27>
GPU_HDMI_TXC+<27>

GPU_HDMI_SDATA<27>
GPU_HDMI_SCLK<27>

VGA_DPC_N0<29>
VGA_DPC_P0<29>

VGA_DPC_N1<29>

VGA_DPC_P1<29>

VGA_DPC_N2<29>
VGA_DPC_P2<29>

VGA_DPC_N3<29>
VGA_DPC_P3<29>

VGA_DPC_AUXN/DDC<29>
VGA_DPC_AUXP/DDC<29>

VGA_PRSNT_L#<20>

(Pull-UP 10K at PCH)

CLK_PEG_PCH#_R
CLK_PEG_PCH_R

2N7002E-T1-E3_SOT23-3

2N7002E-T1-E3_SOT23-3

EC_SMB_DA1<40,44,45>

EC_SMB_CK1<40,44,45>

JMXM1B

JMXM1B

163

GND

165

PEX_RX2#

167

PEX_RX2

169

GND

171

PEX_RX1#

173

PEX_RX1

175

GND

177

PEX_RX0#

179

PEX_RX0

181

GND

183

PEX_REFCLK#

185

PEX_REFCLK

187

GND

189

RSVD

191

RSVD

193

RSVD

195

RSVD

197

RSVD

199

LVDS_UCLK#

201

LVDS_UCLK

203

GND

205

LVDS_UTX3#

207

LVDS_UTX3

209

GND

211

LVDS_UTX2#

213

LVDS_UTX2

215

GND

217

LVDS_UTX1#

219

LVDS_UTX1

221

GND

223

LVDS_UTX0#

225

LVDS_UTX0

227

GND

229

DP_C_L0#

231

DP_C_L0

233

GND

235

DP_C_L1#

237

DP_C_L1

239

GND

241

DP_C_L2#

243

DP_C_L2

245

GND

247

DP_C_L3#

249

DP_C_L3

251

GND

253

DP_C_AUX#

255

DP_C_AUX

257

RSVD

259

RSVD

261

RSVD

263

RSVD

265

RSVD

267

RSVD

269

RSVD

271

RSVD

273

RSVD

275

RSVD

277

RSVD

279

RSVD

281

GND

283

DP_A_L0#

285

DP_A_L0

287

GND

289

DP_A_L1#

291

DP_A_L1

293

GND

295

DP_A_L2#

297

DP_A_L2

299

GND

301

DP_A_L3#

303

DP_A_L3

305

GND

307

DP_A_AUX#

309

DP_A_AUX

310

PRSNT_L#

311

GND

JAE_MM70-314-310B1-1-R300

JAE_MM70-314-310B1-1-R300

MXM PCH

Port A

DMC(HDMI)

DP

Port B

HDMI

Port C

eDP

Port D

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

HDMI

DP

DMC(HDMI)

2

2

+3V_MXM

Q5

Q5

1 3

D

D

GND

PEX_TX2#

PEX_TX2

GND

PEX_TX1#

PEX_TX1

GND

PEX_TX0#

PEX_TX0

GND

PEX_CLK_REQ#

PEX_RST#
VGA_DDC_DAT
VGA_DDC_CLK

VGA_VSYNC
VGA_HSYNC

GND

VGA_RED

VGA_GREEN

VGA_BLUE

GND

LVDS_LCLK#

LVDS_LCLK

GND

LVDS_LTX3#

LVDS_LTX3

GND

LVDS_LTX2#

LVDS_LTX2

GND

LVDS_LTX1#

LVDS_LTX1

GND

LVDS_LTX0#

LVDS_LTX0

GND

DP_D_L0#

DP_D_L0

GND

DP_D_L1#

DP_D_L1

GND

DP_D_L2#

DP_D_L2

GND

DP_D_L3#

DP_D_L3

GND

DP_D_AUX#

DP_D_AUX
DP_C_HPD
DP_D_HPD

RSVD
RSVD
RSVD

GND

DP_B_L0#

DP_B_L0

GND

DP_B_L1#

DP_B_L1

GND

DP_B_L2#

DP_B_L2

GND

DP_B_L3#

DP_B_L3

GND

DP_B_AUX#

DP_B_AUX
DP_B_HPD
DP_A_HPD

GND

1

+3V_MXM +3V_MXM

12

R86

1 3

D

D

162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
262
264
266
268
270
272
274
276
278
280
282
284
286
288
290
292
294
296
298
300
302
304
306
308

312

2

R86

4.7K_0402_5%~D

4.7K_0402_5%~D

G

G

Q6

Q6

S

S

2N7002E-T1-E3_SOT23-3

2N7002E-T1-E3_SOT23-3

VGA_DDC_DATA
VGA_DDC_CLK

2

G

G

S

S

3V3
3V3

12

R87

R87

4.7K_0402_5%~D

4.7K_0402_5%~D

VGA_SMB_DA1

VGA_SMB_CK1

PEG_HTX_C_GRX_N2 <4>
PEG_HTX_C_GRX_P2 <4>

PEG_HTX_C_GRX_N1 <4>
PEG_HTX_C_GRX_P1 <4>

PEG_HTX_C_GRX_N0 <4>
PEG_HTX_C_GRX_P0 <4>

PEG_CLKREQ# <17>
PLTRST_VGA# <15,19>

VGA_DDC_DATA <26>

VGA_DDC_CLK <26>
VGA_CRT_VSYNC <26>
VGA_CRT_HSYNC <26>

VGA_CRT_R <26>
VGA_CRT_G <26>
VGA_CRT_B <26>

VGA_TXCLK- <24>
VGA_TXCLK+ <24>

VGA_TXOUT2- <24>
VGA_TXOUT2+ <24>

VGA_TXOUT1- <24>
VGA_TXOUT1+ <24>

VGA_TXOUT0- <24>
VGA_TXOUT0+ <24>

Reserve for eDP

+3V_MXM

40mil(1A)

VGA_SMB_DA1 <15>

VGA_SMB_CK1 <15>

VGA_HDMI_DET <27>

VGA_DPD_N0 <28>
VGA_DPD_P0 <28>

VGA_DPD_N1 <28>
VGA_DPD_P1 <28>

VGA_DPD_N2 <28>
VGA_DPD_P2 <28>

VGA_DPD_N3 <28>
VGA_DPD_P3 <28>

VGA_DPD_AUXN/DDC <28>
VGA_DPD_AUXP/DDC <28>

VGA_DPD_HPD <28>

VGA_DMC_HPD <29>

LVDS

mini DP

DELL CONFIDENTIAL/PROPRIETARY

Compal El ectronics, Inc.

Compal El ectronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal El ectronics, Inc.

MXMIII Connector (Master)

MXMIII Connector (Master)

MXMIII Connector (Master)

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

14

14

14

65Tuesday, January 17, 2012

5

R1633

@R1633

@

1 2

0_0805_5%~D

0_0805_5%~D

D D

C C

B B

A A

1

2

+3V_MXM

R1718 10K_0 402_5%~D@ R1718 10K_0402_5%~D@

R1722 10K_0 402_5%~D@ R1722 10K_0402_5%~D@

+3V_MXM1

R1716 3.3K_04 02_5%~DR1716 3.3K_0402_5%~D

R1720 3.3K_04 02_5%~DR1720 3.3K_0402_5%~D

MXM_CUR_DAT
MXM_CUR_CLK

MXM_CUR_VIN+<46>

MXM_CUR_VIN-<46>

MXM1_CUR_VIN+<46>

MXM1_CUR_VIN-<46>

+3V_MXM1

R1830 10K_0402_5%~D R1830 10K_04 02_5%~D

R112 10K_0402_5%~D@ R112 10K_0402_5%~D@

R111 10K_0402_5%~D@ R111 10K_0402_5%~D@

C1742

C1742

4.7U_0603_10V6K~D

4.7U_0603_10V6K~D

1 2

1 2

+3VMXM +5VMXM

B+_MXM_A1

12

B+_MXM_A0

12

B+_MXM1_A1

12

B+_MXM1_A0

12

R1714 0_0402_ 5%~D@ R1714 0_0402_5%~D@

1 2

R1715 0_0402_ 5%~D@ R1715 0_0402_5%~D@

1 2

R1725

@R1725

@
1 2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

0_0402_5%~D

0_0402_5%~D

@ C1802

@

1

C1802

R1726

@R1726

@

2

0_0402_5%~D

0_0402_5%~D

1 2

R1728

@R1728

@
1 2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

0_0402_5%~D

0_0402_5%~D

@C1804

@

1

C1804

R1729

@R1729

@

2

0_0402_5%~D

0_0402_5%~D

1 2

+3V_MXM1

12

5

+5V_MXM1+3V_MXM1

PJP10

PJP10

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

C1741

C1741

1

2

R1719 10K_0402_5%~DR1719 10K_0 402_5%~D

R1723 10K_0402_5%~DR1723 10K_0 402_5%~D

R1717 0_0402_ 5%@R1717 0_0402_5%@

R1721 0_0402_ 5%@R1721 0_0402_5%@

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

@ C1803

@

1

C1803

2

+3V_MXM

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

@C1805

@

1

C1805

2

MXM2_PCH_PWROK

VGA2_WAKE#

VGA2_DISABLE#

2

JUMP_43X118

JUMP_43X118

C1743

C1743

VGA_SMB_DA1 <14>
VGA_SMB_CK1 <14>

112

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

2

12

12

12

12

MXM1 Current Monitor

U612

U612

1

VIN+

2

VIN-

3
4

SDA

GND
VS

INA219AIDCNRG4_SOT23-8

INA219AIDCNRG4_SOT23-8

MXM2 Current Monitor

U613

U613

1

VIN+

2

VIN-

3
4

SDA

GND
VS

INA219AIDCNRG4_SOT23-8

INA219AIDCNRG4_SOT23-8

680P_0402_50V7 K~D

680P_0402_50V7 K~D

10U_0805_25V6K~D

10U_0805_25V6K~D

C1738

C1738

1

2

R110 0_0402_5%~D@ R110 0_0402_5%~D@

B+_MXM_A1

8

A1

B+_MXM_A0

7

A0

MXM_CUR_DAT

6

MXM_CUR_CLK

5

SCL

B+_MXM1_A1

8

A1

B+_MXM1_A0

7

A0

MXM_CUR_DAT

6

MXM_CUR_CLK

5

SCL

PEG_GTX_HRX_N15<4>
PEG_GTX_HRX_P15<4>

PEG_GTX_HRX_N14<4>
PEG_GTX_HRX_P14<4>

PEG_GTX_HRX_N13<4>
PEG_GTX_HRX_P13<4>

PEG_GTX_HRX_N12<4>
PEG_GTX_HRX_P12<4>

PEG_GTX_HRX_N11<4>
PEG_GTX_HRX_P11<4>

4

160mil(4A)

0.1U_0603_50V7K~D

0.1U_0603_50V7K~D

68P_0402_50V8J ~D

68P_0402_50V8J ~D

C1739

C1739

C1740

C1740

1

1

2

2

+5V_MXM1

100mil(2.5A, 5VIA)

1 2

VGA2_DISABLE#

PEG_GTX_HRX_N15
PEG_GTX_HRX_P15

PEG_GTX_HRX_N14
PEG_GTX_HRX_P14

PEG_GTX_HRX_N13
PEG_GTX_HRX_P13

PEG_GTX_HRX_N12
PEG_GTX_HRX_P12

PEG_GTX_HRX_N11
PEG_GTX_HRX_P11

4

3

EC_SMB_DA 2<17,30,40,41,44>

EC_SMB_CK 2<17,30,40,41,44>

GND
GND
GND
GND
GND
GND
GND
GND
GND

WAKE#

RSVD
RSVD
RSVD
RSVD

GPIO0
GPIO1
GPIO2

GND
OEM
OEM
OEM
OEM

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

2
4
6
8
10
12
14
16
18

20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160

B+_MXM1B+_MXM1

MXM2_PEG_PCH#<17>
MXM2_PEG_PCH<17 >

MXM2_PRSNT_R#
VGA2_WAKE#
MXM2_PCH_PWROK
MXM2_PWR_ON

AC_BATT#
VGA_TH_OVERT#

R109 10K_0402_5%~D

R109 10K_0402_5%~D

VGA_SMB_DA2
VGA_SMB_CK2

MXM_PS_3
MXM_PS_4
MXM_PS_5

PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_P15

PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P14

PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P13

PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_P12

PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P11

PEG_GTX_HRX_N10<4>
PEG_GTX_HRX_P10<4>

PEG_GTX_HRX_N9<4>
PEG_GTX_HRX_P9<4>

PEG_GTX_HRX_N8<4>
PEG_GTX_HRX_P8<4>

1 2

R107 0_0402_5%~D@R107 0_0402_5%~D@

1 2

R106 0_0402_5%~D@R106 0_0402_5%~D@

MXM_PS_3

C2032 0.01U_0402_16V7K~D@ C2032 0.01U_040 2_16V7K~D@

MXM_PS_4
MXM_PS_5

1 2

3

1 2

C2034 0.01U_0402_16V7K~D@ C2034 0.01U_040 2_16V7K~D@

1 2

C2033 0.01U_0402_16V7K~D@ C2033 0.01U_040 2_16V7K~D@

1 2

MXM2_PRSNT_R# <16,20>

MXM2_PCH_PWROK <20>

AC_BATT# <14>

VGA_TH_OVERT# <14>

+3VMXM

12

12

R2594

R2594

R2593

R2593

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

@

@

@

@

12

12

R2597

R2597

R2596

R2596

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

0_0402_5%~D

@

@

@

@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SE CRET AN D OTHER PROPRIE TARY INF ORMATION OF DEL L. THIS DOCUMEN T MAY NO T
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WI THOUT D ELL'S EX PRESS W RITTEN C ONSENT.

PEG_GTX_HRX_N10
PEG_GTX_HRX_P10

PEG_GTX_HRX_N9
PEG_GTX_HRX_P9

PEG_GTX_HRX_N8
PEG_GTX_HRX_P8

MXM2_PEG_PCH#_R
MXM2_PEG_PCH_R

+3V_MXM1

12

R2595

R2595

0_0402_5%~D

0_0402_5%~D

MXM_PS_3

@

@

MXM_PS_4
MXM_PS_5

12

R2598

R2598

0_0402_5%~D

0_0402_5%~D

@

@

PEG_HTX_C_GRX_N15 <4>
PEG_HTX_C_GRX_P15 <4>

PEG_HTX_C_GRX_N14 <4>
PEG_HTX_C_GRX_P14 <4>

PEG_HTX_C_GRX_N13 <4>
PEG_HTX_C_GRX_P13 <4>

PEG_HTX_C_GRX_N12 <4>
PEG_HTX_C_GRX_P12 <4>

PEG_HTX_C_GRX_N11 <4>
PEG_HTX_C_GRX_P11 <4>

JMXM2A

JMXM2A

1

PWR_SRC

3

PWR_SRC

5

PWR_SRC

7

C1737

C1737

2

1

PWR_SRC

9

PWR_SRC

11

PWR_SRC

13

PWR_SRC

15

PWR_SRC

17

PWR_SRC

19

GND

21

GND

23

GND

25

GND

27

GND

29

GND

31

GND

33

GND

35

GND

37

5V

39

5V

41

5V

43

5V

45

5V

47

GND

49

GND

51

GND

53

GND

55

PEX_STD_SW#

57

VGA_DISABLE#

59

PNL_PWR_EN

61

PNL_BL_EN

63

PNL_BL_PWM

65

HDMI_CEC

67

DVI_HPD

69

LVDS_DD C_DAT

71

LVDS_DD C_CLK

73

GND

75

OEM

77

OEM

79

OEM

81

OEM

83

GND

85

PEX_RX15#

87

PEX_RX15

89

GND

91

PEX_RX14#

93

PEX_RX14

95

GND

97

PEX_RX13#

99

PEX_RX13

101

GND

103

PEX_RX12#

105

PEX_RX12

107

GND

109

PEX_RX11#

111

PEX_RX11

113

GND

115

PEX_RX10#

117

PEX_RX10

119

GND

121

PEX_RX9#

123

PEX_RX9

125

GND

127

PEX_RX8#

129

PEX_RX8

131

GND

133

PEX_RX7#

135

PEX_RX7

137

GND

139

PEX_RX6#

141

PEX_RX6

143

GND

145

PEX_RX5#

147

PEX_RX5

149

GND

151

PEX_RX4#

153

PEX_RX4

155

GND

157

PEX_RX3#

159

PEX_RX3

161

GND

JAE_MM70-314-310B1-1-R300

JAE_MM70-314-310B1-1-R300

E1 E2

E1 E2

E3 E4

E3 E4

PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC

PRSNT_R#

PWR_GOOD

PWR_EN

PWR_LEVEL

TH_OVERT#

TH_ALERT#

TH_PWM

SMB_DAT
SMB_CLK

PEX_TX15#

PEX_TX15

PEX_TX14#

PEX_TX14

PEX_TX13#

PEX_TX13

PEX_TX12#

PEX_TX12

PEX_TX11#

PEX_TX11

PEX_TX10#

PEX_TX10

PEX_TX9#

PEX_TX9

PEX_TX8#

PEX_TX8

PEX_TX7#

PEX_TX7

PEX_TX6#

PEX_TX6

PEX_TX5#

PEX_TX5

PEX_TX4#

PEX_TX4

PEX_TX3#

PEX_TX3

2

+3V_MXM1 +3V_MX M1 +3V_MX M1

1 3

JMXM2B

JMXM2B

163

GND

165

PEX_RX2#

167

PEX_RX2

169

GND

171

PEX_RX1#

173

PEX_RX1

175

GND

177

PEX_RX0#

179

PEX_RX0

181

GND

183

PEX_REFCLK #

185

PEX_REFCLK

187

GND

189

RSVD

191

RSVD

193

RSVD

195

RSVD

197

RSVD

199

LVDS_UCLK#

201

LVDS_UCLK

203

GND

205

LVDS_UTX3#

207

LVDS_UTX3

209

GND

211

LVDS_UTX2#

213

LVDS_UTX2

215

GND

217

LVDS_UTX1#

219

LVDS_UTX1

221

GND

223

LVDS_UTX0#

225

LVDS_UTX0

227

GND

229

DP_C_L0#

231

DP_C_L0

233

GND

235

DP_C_L1#

237

DP_C_L1

239

GND

241

DP_C_L2#

243

DP_C_L2

245

GND

247

DP_C_L3#

249

DP_C_L3

251

GND

253

DP_C_AUX#

255

DP_C_AUX

257

RSVD

259

RSVD

261

RSVD

263

RSVD

265

RSVD

267

RSVD

269

RSVD

271

RSVD

273

RSVD

275

RSVD

277

RSVD

279

RSVD

281

GND

283

DP_A_L0#

285

DP_A_L0

287

GND

289

DP_A_L1#

291

DP_A_L1

293

GND

295

DP_A_L2#

297

DP_A_L2

299

GND

301

DP_A_L3#

303

DP_A_L3

305

GND

307

DP_A_AUX#

309

DP_A_AUX

310

PRSNT_L#

311

GND

JAE_MM70-314-310B1-1-R300

JAE_MM70-314-310B1-1-R300

2

2

G

G

D

S

D

S

PEX_TX2#

PEX_TX1#

PEX_TX0#

PEX_CLK_REQ#

PEX_RST#
VGA_DDC_D AT
VGA_DDC_C LK

VGA_VSYNC
VGA_HSYNC

VGA_RED

VGA_GREEN

VGA_BLUE

LVDS_LCLK #

LVDS_LCLK

LVDS_LTX3#

LVDS_LTX3

LVDS_LTX2#

LVDS_LTX2

LVDS_LTX1#

LVDS_LTX1

LVDS_LTX0#

LVDS_LTX0

DP_D_L0#

DP_D_L1#

DP_D_L2#

DP_D_L3#

DP_D_AUX#

DP_D_AUX

DP_C_HPD
DP_D_HPD

DP_B_L0#

DP_B_L1#

DP_B_L2#

DP_B_L3#

DP_B_AUX#

DP_B_AUX
DP_B_HPD
DP_A_HPD

R1886

R1886

4.7K_0402_5%~D

4.7K_0402_5%~D

Q277

Q277
2N7002E-T1-E3_SOT23-3

2N7002E-T1-E3_SOT23-3

2

G

G

Q278

Q278
2N7002E-T1-E3_SOT23-3

2N7002E-T1-E3_SOT23-3

1 3

D

S

D

S

162

GND

164
166

PEX_TX2

168

GND

170
172

PEX_TX1

174

GND

176
178

PEX_TX0

180

GND

182
184
186
188
190
192
194

GND

196
198
200
202

GND

204
206
208

GND

210
212
214

GND

216
218
220

GND

222
224
226

GND

228
230
232

GND

234
236

DP_D_L0

238

GND

240
242

DP_D_L1

244

GND

246
248

DP_D_L2

250

GND

252
254

DP_D_L3

256

GND

258
260
262
264
266

RSVD

268

RSVD

270

RSVD

272

GND

274
276

DP_B_L0

278

GND

280
282

DP_B_L1

284

GND

286
288

DP_B_L2

290

GND

292
294

DP_B_L3

296

GND

298
300
302
304
306

3V3

308

3V3

312

GND

1

12

12

R1887

R1887

4.7K_0402_5%~D

4.7K_0402_5%~D

VGA_SMB_DA2

VGA_SMB_CK2

PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P10

PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P9

PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_P8

MXM2_CLKREQ#
MXM2_RST#

MXM2_RST#

RH264

RH264

100K_0402_5%

100K_0402_5%

MXM2_PWR_ON

+3V_MXM1

40mil(1A)

4

O

12

4

PEG_HTX_C_GRX_N10 <4>
PEG_HTX_C_GRX_P10 <4>

PEG_HTX_C_GRX_N9 <4>
PEG_HTX_C_GRX_P9 <4>

PEG_HTX_C_GRX_N8 <4>
PEG_HTX_C_GRX_P8 <4>

MXM2_CLKREQ# <17>

+3VALW

C1849

C1849

1 2

5

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

P

IN1

2

IN2

G

3

UH7

UH7
SN74AHC1G08DCKR_SC 70-5

SN74AHC1G08DCKR_SC 70-5

+3VALW

C1850

C1850

1 2

5

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

P

IN1

O

2

IN2

G

3

UH8

UH8
SN74AHC1G08DCKR_SC 70-5

SN74AHC1G08DCKR_SC 70-5

MXM2_EC_RST# <20>

PLTRST_VGA# <14 ,19>

MXM2_PCH_PWR_ON <16,20>

VGA_ON <14,17>

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

MXMIII Connector (Slave)

MXMIII Connector (Slave)

MXMIII Connector (Slave)

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

15

15

15

5

D D

+RTCVCC

1 2

RH22 20 K_0402_5%RH22 20K_0402_5%

1 2

RH23 20 K_0402_5%RH23 20K_0402_5%

1 2

RH11 1M_0 402_5%~DRH11 1M_0 402_5%~D

HDA_BITCLK_AUDIO<32>

C C

HDA_RST_AUDIO#<32>

HDA_SYNC_AUDIO<32>

+3V_PCH +3V_PCH+3V_ PCH

12

RH43

@ RH43

@

200_04 02_5%

200_04 02_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

RH47

RH47

100_04 02_1%

100_04 02_1%

B B

1 2

RH25 33_0402 _5%~D

RH25 33_0402 _5%~D

1 2

RH27 33_0402 _5%~D

RH27 33_0402 _5%~D

1 2

RH26 33_0402 _5%~D

RH26 33_0402 _5%~D

12

RH44

@ RH44

@

200_04 02_5%

200_04 02_5%

12

RH48

RH48
100_04 02_1%

100_04 02_1%

1M_0402_ 5%~D

1M_0402_ 5%~D

12

RH45

@ RH45

@

200_04 02_5%

200_04 02_5%

12

RH49

RH49

100_04 02_1%

100_04 02_1%

HDA_BIT_CLK

HDA_RST#

HDA_SYNC_R

12

R1906

R1906

12

CH97

@ CH97

@

22P_040 2_50V8J~D

22P_040 2_50V8J~D

1U_0603 _25V6-K~D

1U_0603 _25V6-K~D

PCH_JTAG_TCK

RH59

RH59
51_040 2_5%

51_040 2_5%

12

1

CH4

CH4

2

+5VS

S

S

QH7

QH7
BSS138_SOT23~ D

BSS138_SOT23~ D

1 2

RH263 0_0402_5%@ RH263 0_0402_5%@

HDA_SDOUT_AUDIO<32>

PCH_SPI_CLK_R

@ CLRCMOS

@

CLRCMOS

SHORT PADS

SHORT PADS

12

G

G

2

13

D

D

HDA_SDO<40>

@ CLRME

@

CLRME

SHORT PADS

SHORT PADS

1U_0603 _25V6-K~D

1U_0603 _25V6-K~D

1

12

CH5

CH5

2

HDA_SPKR<32>

HDA_SDIN0<32>

RH52

@ RH52

@

0_0402 _5%~D

0_0402 _5%~D

1 2

1 2

RH29 33_0402 _5%~D

RH29 33_0402 _5%~D

RH240

RH240

1 2

33_040 2_5%~D

33_040 2_5%~D

RH240 & CH97 as close as
UH4

PCH_RTCX1

1 2

RH2 10M_0 402_5%RH2 10M_04 02_5%

YH1

YH1

1 2

32.768KHZ_ 12.5PF_9H0320 0019

32.768KHZ_ 12.5PF_9H0320 0019

15P_040 2_50V8J~D

15P_040 2_50V8J~D

CH2

CH2

1

2

A A

PCH_RTCX2

+3V_PCH

12

RH57

@ RH57

@

3.3K_040 2_5%~D

1

CH3

CH3
18P_040 2_50V8J~D

18P_040 2_50V8J~D

2

PCH_SPI_SO PCH_SPI_SO_R PCH_SPI_HOLD#

5

3.3K_040 2_5%~D

1 2

RH60 0_0402_5%~D@R H60 0_0 402_5%~D@

1 2

RH58 0_0402_5%~D@R H58 0_0 402_5%~D@

1 2

RH53

RH53

3.3K_040 2_5%~D

3.3K_040 2_5%~D

PCH_SPI_CS#_RPCH_SPI_CS#

PCH_SPI_WP#

4

USB_OC0#<19 ,43>
USB_OC1#<19 ,43>

1.5VDDR_VID0<19,51>

1.5VDDR_VID1< 19,51>
USB_OC4#<19 ,43>
USB_OC2#<19 ,36>
USB_OC3#<19 ,36>

ESATA_DETECT#<19 ,43>
PCH_GPIO16<20>

MXM2_PCH_PWR_ON< 15,20>

ODD_DETECT#<20 ,34>
PCH_GPIO37<20>
PCH_GPIO16<20>
MXM2_PRSNT_R#<15,2 0>
PCH_GPIO15<20>
CRT_DET<20>

UH4A

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS#

PCH_SPI_SI

PCH_SPI_SO

UH4A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

BD82HM77 QPRG -C1 BGA989~D

BD82HM77 QPRG -C1 BGA989~D

SPI ROM FOR ME
( 8MByte )

U1

U1

1

/CS

2

DO

3

/WP

GND4DIO

W25Q64CVSSI G_SO8~D

W25Q64CVSSI G_SO8~D

8

VCC

7

/HOLD

6

CLK

5

4

USB_OC0#
USB_OC1#

1.5VDDR_VID0

1.5VDDR_VID1
USB_OC4#
USB_OC2#
USB3_SMI#
ESATA_DETECT#
PCH_GPIO16
MXM2_PCH_PWR_ON
PCH_GPIO21
BBS_BIT0_R
ODD_DETECT#
PCH_GPIO37
PCH_GPIO16
MXM2_PRSNT_R#
PCH_GPIO15
CRT_DET

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SATA

SATA

SATA0GP / GPIO21

SATA1GP / GPIO19

12

RH55

RH55

3.3K_040 2_5%~D

3.3K_040 2_5%~D

SERIRQ

SATA0RXN
SATA0RXP

SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP

SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP

SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP

SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP

SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

RTCIHDA

RTCIHDA

JTAG

JTAG

SPI

SPI

+3V_PCH

PCH_SPI_CLK_R

PCH_SPI_SI_R PCH_SPI_SI

RH168 0_0402 _5%~D@ RH168 0_040 2_5%~D@

1 2

3

RH1 33_0402 _5%~D@ RH1 33_040 2_5%~D@

1 2

RH3 33_0402 _5%~D@ RH3 33_040 2_5%~D@

1 2

RH4 33_0402 _5%~D@ RH4 33_040 2_5%~D@

1 2

RH5 33_0402 _5%~D@ RH5 33_040 2_5%~D@

1 2

RH6 33_0402 _5%~D@ RH6 33_040 2_5%~D@

1 2

RH7 33_0402 _5%~D@ RH7 33_040 2_5%~D@

1 2

RH8 33_0402 _5%~D@ RH8 33_040 2_5%~D@

1 2

RH9 33_0402 _5%~D@ RH9 33_040 2_5%~D@

1 2

RH10 3 3_0402_5 %~D@ RH10 33 _0402_5%~D@

1 2

RH12 3 3_0402_5 %~D@ RH12 33 _0402_5%~D@

1 2

RH13 3 3_0402_5 %~D@ RH13 33 _0402_5%~D@

1 2

RH14 3 3_0402_5 %~D@ RH14 33 _0402_5%~D@

1 2

RH15 3 3_0402_5 %~D@ RH15 33 _0402_5%~D@

1 2

RH16 3 3_0402_5 %~D@ RH16 33 _0402_5%~D@

1 2

RH17 3 3_0402_5 %~D@ RH17 33 _0402_5%~D@

1 2

RH18 3 3_0402_5 %~D@ RH18 33 _0402_5%~D@

1 2

RH19 3 3_0402_5 %~D@ RH19 33 _0402_5%~D@

1 2

RH20 3 3_0402_5 %~D@ RH20 33 _0402_5%~D@

1 2

XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17

Please close to JXDP2

LPC_AD0

C38
A38
B37
C37

D36

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

LPC_LDRQ0 #
LPC_LDRQ1 #

SERIRQ

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED#

PCH_GPIO21

BBS_BIT0_R

LPC_AD0 <35,40>
LPC_AD1 <35,40>
LPC_AD2 <35,40>
LPC_AD3 <35,40>

LPC_FRAME# <35,40>

T79 PAD~D@ T79 PAD~D@
T77 PAD~D@ T77 PAD~D@

SERIRQ <40>

SATA_PRX_DTX_N0 <34>

SATA_PRX_DTX_P0 <34>
SATA_PTX_DRX_N0 <34>
SATA_PTX_DRX_P0 <34>

SATA_PRX_DTX_N1 <34>

SATA_PRX_DTX_P1 <34>
SATA_PTX_DRX_N1 <34>
SATA_PTX_DRX_P1 <34>

SATA_PRX_DTX_N2 <34>

SATA_PRX_DTX_P2 <34>
SATA_PTX_DRX_N2 <34>
SATA_PTX_DRX_P2 <34>

SATA_PRX_DTX_N3 <34>

SATA_PRX_DTX_P3 <34>
SATA_PTX_DRX_N3 <34>
SATA_PTX_DRX_P3 <34>

SATA_PRX_DTX_N4 <43>

SATA_PRX_DTX_P4 <43>
SATA_PTX_DRX_N4 <43>
SATA_PTX_DRX_P4 <43>

SATA_PRX_DTX_N5 <34>

SATA_PRX_DTX_P5 <34>
SATA_PTX_DRX_N5 <34>
SATA_PTX_DRX_P5 <34>

1 2

RH40 37.4_0402_ 1%RH40 37.4_0402_ 1%

1 2

RH42 49.9_0402_ 1%

RH42 49.9_0402_ 1%

1 2

RH46 750_0402_ 1%

RH46 750_0402_ 1%

PCH_SATALED# <38>

1 2

RH266 10K_04 02_5%~DRH266 10K_0402_5 %~D

BBS_BIT0 - BIOS BOOT STRAP BIT 0

GPIO19:
If not used, requires 8.2-kΩ to 10-kΩ
pull-up to +Vcc_3.3 (+3.3VS)
check list Rev 1.0

+3V_PCH

1

CH6

CH6

0.1U_04 02_25V6K~D

0.1U_04 02_25V6K~D

2

3

2

+3V_PCH

RH51

@ RH51

CH1

@ CH1

@

0.1U_04 02_25V6K~D

0.1U_04 02_25V6K~D

VGATE<5,1 8,53>
PBTN_OUT#<5,18 ,40>

1

2

PCH_JTAG_TCK<5>

@

1 2

0_0402 _5%

0_0402 _5%

1 2

RH21 0 _0402_5%@ RH2 1 0_040 2_5%@

PCH_SMBDATA<5,10,11 ,12,13,17,3 4,35,43>
PCH_SMBCLK<5,10,11,12 ,13,17,34,3 5,43>

+3V_PCH_XDP

XDP_FN0
XDP_FN1

XDP_FN2
XDP_FN3

XDP_FN4
XDP_FN5

XDP_FN6
XDP_FN7

VGATE

PCH_PWRBTN#_XDP

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

SAMTE_BSH-030-01 -L-D-A

SAMTE_BSH-030-01 -L-D-A

CONN@

CONN@

JPCHXDP

JPCHXDP

HDD1

HDD2

ODD

HDD3

PCH_INTVRMEN

PCH_INTVRMEN

RH38 3 30K_0402_5 %~DRH38 330K_0402_5%~D

RH39 3 30K_0402_5 %~D@RH39 330K_0402_5 %~D@

INTVRMEN

H：Integrated VRM enable

*

L

：

Integrated VRM disable

+RTCVCC

12

12

E-SATA

mSATA

+1.05VS_VCC_ SATA

+1.05VS_SATA3

+3VS

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

2

1

2

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

GND17

SERIRQ

PCH_GPIO21

PCH_SATALED#

TMS

XDP_FN16

4

XDP_FN17

6
8

XDP_FN8

10

XDP_FN9

12
14

XDP_FN10

16

XDP_FN11

18
20
22
24
26

XDP_FN12

28

XDP_FN13

30
32

XDP_FN14

34

XDP_FN15

36
38
40
42

+3V_PCH_XDP

44

PLTRST1#_XDP

46

XDP_DBRESET#

48
50

PCH_JTAG_TDO

52

TD0

54

PCH_JTAG_TDI

56

TDI

PCH_JTAG_TMSPCH_JTAG_TCK

58
60

RH28 1 0K_0402_5%~DRH28 10K_0402_5%~D

RH30 1 0K_0402_5%~DRH30 10K_0402_5%~D

RH31 1 0K_0402_5%~DRH31 10K_0402_5%~D

HDA_SPKR

RH35 1 K_0402_5%@RH35 1 K_0402_5%@

LOW=Default
HIGH=No Reboot

*

HDA_SDOUT

RH41 1 K_0402_5%@RH41 1 K_0402_5%@

Low = Disabled

*

High = Enabled

RH24

@ RH24

@

1K_0402 _5%

1K_0402 _5%

1 2

XDP_DBRESET# <5,18>

PCH_JTAG_TDO <5>

PCH_JTAG_TDI <5>
PCH_JTAG_TMS <5>

+3VS

12

12

12

+3VS

12

+3V_PCH

12

PLT_RST# <5,19,31,3 5,40,43>

HDA_SYNC

This signal has a weak intern al pull-down
On Die PLL VR i s supplied by

1.5V when smapl ed high

1.8V when sampl ed low
Needs to be pul led High for H uron River plat from

HDA_SYNC

RH66 1 K_0402_5%

RH66 1 K_0402_5%

+3V_PCH

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

16

16

16

5

PCIE_PRX_DTX_N1<31>

10/100/1G LAN --->

DMC --->

D D

MiniWLAN (Mini Card 1)--->

CARD_READER --->

EXPRESS_CARD --->

@

@

CH98

@ CH9 8

@

RH250

CLK_PCH_14 M

Reserve for EMI please close to UH4

C C

CLK_PCI_LPBACK

Reserve for EMI please close to UH4

RH250

33_040 2_5%~D

33_040 2_5%~D

@

@

RH251

RH251

33_040 2_5%~D

33_040 2_5%~D

1 2

12

22P_040 2_50V8J~D

22P_040 2_50V8J~D

CH99

@ CH9 9

@

1 2

12

22P_040 2_50V8J~D

22P_040 2_50V8J~D

10/100/1G LAN --->

MiniDMC (Mini Card 2)--->

MiniWLAN (Mini Card 1)--->

Card Reader --->

EXPRESS_CARD --->

B B

12

RH991M_0402 _5%~D RH991M_0402 _5%~D

YH2

YH2

25MHZ_12PF_7V2 5000012

25MHZ_12PF_7V2 5000012

1

1

15P_040 2_50V8J~D

15P_040 2_50V8J~D

GND

CH19

CH19

1

2

2

A A

GND

3

3

4

5

PCIE_PRX_DTX_P1<31>
PCIE_PTX_DRX_N1<31>
PCIE_PTX_DRX_P1<3 1>

PCIE_PRX_DTX_N2<35>
PCIE_PRX_DTX_P2<3 5>

PCIE_PTX_DRX_N2<35>

PCIE_PTX_DRX_P2<3 5>

PCIE_PRX_DTX_N3<35>

PCIE_PRX_DTX_P3<35>
PCIE_PTX_DRX_N3<35>
PCIE_PTX_DRX_P3<3 5>

PCIE_PRX_DTX_N4<43>

PCIE_PRX_DTX_P4<43>
PCIE_PTX_DRX_N4<43>
PCIE_PTX_DRX_P4<4 3>

PCIE_PRX_DTX_N5<43>

PCIE_PRX_DTX_P5<4 3>
PCIE_PTX_DRX_N5<43>
PCIE_PTX_DRX_P5<4 3>

CLK_PCIE_LAN#<3 1>
CLK_PCIE_LAN<31>

LANCLK_REQ#<31>

CLK_PCIE_MINI2#<35>
CLK_PCIE_MINI2<35>

CLK_PCIE_MINI3#<35>
CLK_PCIE_MINI3<35>

MINI1CLK_REQ#<35>

CLK_PCIE_CD#<43 >
CLK_PCIE_CD<43>

CDCLK_REQ#<43>

CLK_PCIE_EXP#<43>
CLK_PCIE_EXP<43 >

EXPCLK_REQ#< 43>

MXM2 --->

XTAL25_IN

XTAL25_OUT IO_DET#

15P_040 2_50V8J~D

15P_040 2_50V8J~D

CH18

CH18

1

MXM2_PEG_PCH#<15>
MXM2_PEG_PCH<1 5>

CLK_CPU_ITP#<5>
CLK_CPU_ITP<5>

CLK_RES_ITP#<7>
CLK_RES_ITP<7>

2

+3V_PCH

+3VS

+3VS

MINI2CLK_REQ#<35>

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

mSATA_DET#<34 >

+3V_PCH

VGA_ON<14,15>

CH12 0.1U_0402 _25V6K~DCH12 0.1U_040 2_25V6K~D

1 2

CH13 0.1U_0402 _25V6K~DCH13 0.1U_040 2_25V6K~D

1 2

CH10 0.1U_0402 _25V6K~DCH10 0.1U_040 2_25V6K~D

1 2

CH20 0.1U_0402 _25V6K~DCH20 0.1U_040 2_25V6K~D

1 2

CH8 0.1U_04 02_25V6K~DCH8 0.1 U_0402_25 V6K~D

1 2

CH9 0.1U_04 02_25V6K~DCH9 0.1 U_0402_25 V6K~D

1 2

CH14 0.1U_0402 _25V6K~DCH14 0.1U_040 2_25V6K~D

1 2

CH15 0.1U_0402 _25V6K~DCH15 0.1U_040 2_25V6K~D

1 2

CH16 0.1U_0402 _25V6K~DCH16 0.1U_040 2_25V6K~D

1 2

CH17 0.1U_0402 _25V6K~DCH17 0.1U_040 2_25V6K~D

1 2

RH81 10K_04 02_5%~DRH81 10K_04 02_5%~D

1 2

RH88 0_040 2_5%~D@ RH88 0_040 2_5%~D@

1 2

RH90 0_040 2_5%~D@ RH90 0_040 2_5%~D@

1 2

RH152 10K_04 02_5%~DRH152 10K_0 402_5%~D

RH98 0_040 2_5%~D@ RH98 0_040 2_5%~D@

1 2

RH191 0_040 2_5%~D@ RH191 0_0402 _5%~D@

1 2

RH103 10K_04 02_5%~DRH103 10K_0 402_5%~D

RH82 0_040 2_5%~D@ RH82 0_040 2_5%~D@

1 2

RH83 0_040 2_5%~D@ RH83 0_040 2_5%~D@

1 2

RH84 10K_04 02_5%~DRH84 10K_04 02_5%~D

RH92 0_040 2_5%~D@ RH92 0_040 2_5%~D@

1 2

RH93 0_040 2_5%~D@ RH93 0_040 2_5%~D@

1 2

RH94 10K_04 02_5%~DRH94 10K_04 02_5%~D

RH105 0_040 2_5%~D@ RH105 0_0402 _5%~D@

1 2

RH125 0_040 2_5%~D@ RH125 0_0402 _5%~D@

1 2

RH97 10K_04 02_5%~DRH97 10K_04 02_5%~D

1 2

RH101 10K_04 02_5%~DRH101 10K_0 402_5%~D

1 2

RH104 10K_04 02_5%~D@ RH104 1 0K_0402_5%~D@

1 2

RH106 0_040 2_5%~D@ RH106 0_0402 _5%~D@

1 2

RH107 0_040 2_5%~D@ RH107 0_0402 _5%~D@

1 2

RH108 0_040 2_5%@ RH10 8 0_04 02_5%@
RH109 0_040 2_5%@ RH10 9 0_04 02_5%@

MXM2_CLKREQ#<15>

10K_040 2_5%~D

10K_040 2_5%~D

RH257

RH257

12

12

12

12

12
12

@

@

4

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1_ C
PCIE_PTX_DRX_P1_C

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2_ C
PCIE_PTX_DRX_P2_C

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3_ C
PCIE_PTX_DRX_P3_C

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4_ C
PCIE_PTX_DRX_P4_C

PCIE_PRX_DTX_N5
PCIE_PRX_DTX_P5
PCIE_PTX_DRX_N5_ C
PCIE_PTX_DRX_P5_C

12

4

T95PAD~D @T95PAD~D @
T96PAD~D @T96PAD~D @

PCIECLKREQ0#

PCIE_LAN#
PCIE_LAN

LANCLK_REQ#

PCIE_MINI2#
PCIE_MINI2

MINI2CLK_REQ#

PCIE_MINI3#
PCIE_MINI3

MINI1CLK_REQ#

PCIE_CD#
PCIE_CD

CDCLK_REQ#

PCIE_EXP#
PCIE_EXP

EXPCLK_REQ#

MXM2_PEG_PCH#
MXM2_PEG_PCH

MXM2_CLKREQ#_R

T107PAD~D @T107PAD~D @
T108PAD~D @T108PAD~D @

VGA_ON

CLK_BCLK_ITP#
CLK_BCLK_ITP

1K_0402 _5%

1K_0402 _5%

DMN66D0LDW- 7

DMN66D0LDW- 7

RH258 0_0402 _5%@ RH258 0_0 402_5%@

+3V_MXM

RH256

RH256

4 3

S

S

12

BG34

BJ34
AV32
AU32

BE34
BF34
BB32

AY32

BG36

BJ36
AV34
AU34

BF36
BE36

AY34
BB34

BG37
BH37

AY36
BB36

BJ38
BG38
AU36
AV36

BG40

BJ40

AY40
BB40

BE38
BC38

AW38

AY38

Y40
Y39

J2

AB49
AB47

M1

AA48
AA47

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

AB42
AB40

E6

V40
V42

T13

V38
V37

K12

AK14
AK13

12

G

G

5

10K_040 2_5%~D

10K_040 2_5%~D

D

D

QH9B

QH9B

UH4B

UH4B

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

PERN7
PERP7
PETN7
PETP7

PERN8
PERP8
PETN8
PETP8

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N
CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N
CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N
CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N
CLKOUT_PCIE6P

PCIECLKRQ6# / GPIO45

CLKOUT_PCIE7N
CLKOUT_PCIE7P

PCIECLKRQ7# / GPIO46

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

BD82HM77 QPRG -C1 BGA989~D

BD82HM77 QPRG -C1 BGA989~D

+3V_MXM

12

R1565

R1565

+3V_PCH

12

2

G

G

1 6

D

D

S

S

QH9A

QH9A
DMN66D0LDW- 7

DMN66D0LDW- 7

SMBUSController

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

PCI-E*

CLOCKS

CLOCKS

RH154

RH154
10K_040 2_5%~D

10K_040 2_5%~D

MXM2_CLKREQ#_R

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_DATA1

Link

Link

CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

3

2

EC_LID_OUT#

1 2

RH162 0_0402_5%~D@ RH162 0_0402_5%~D@

SMBCLK

SMBDATA

SML0CLK

CL_CLK1

PCH_LID_SW_ IN#

E12

SMBCLK

H14

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

PCH_GPIO74

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

No support iAMT

1 2

RH172 0_0402_5%@RH17 2 0_040 2_5%@

MEMORY

DRAMRST_CNTRL_PCH <6,10,11>

EC

20090512
add dual mosfet prevent
ATI M92 electric leakage

P10

PEG_CLKREQ#_ R

M10

CLK_PEG_PCH#

AB37

CLK_PEG_PCH

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12
AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96 #

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14 M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

K43

DMC_PCH_DET#

F47

BT_DET#

H47

CAM_DET#

K49

12/08-74 01/03-92

IO_DET#

CAM_DET#

BT_DET#

DMC_PCH_DET#

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

CLK_PEG_PCH# <14>
CLK_PEG_PCH <1 4>

CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>

CLK_PCI_LPBACK <19>

1 2

RH100 90.9_ 0402_1%RH10 0 90.9_0402_ 1%

IO_DET# <4 3>

DMC_PCH_DET# <3 5>

BT_DET# <35>

CAM_DET# <25>

1 2

R1737 10K_04 02_5%~DR 1737 10 K_0402_5%~D

1 2

R1732 10K_04 02_5%~DR 1732 10 K_0402_5%~D

1 2

R1734 10K_04 02_5%~DR 1734 10 K_0402_5%~D

1 2

R1735 10K_04 02_5%~DR 1735 10 K_0402_5%~D

+3VS

+3V_PCH

12

RH80

RH80
10K_040 2_5%~D

10K_040 2_5%~D

+1.05VS_VCCDI FFCLKN

EC_LID_OUT# <40 >

LID_SW_IN# <37,38,4 0>

10K_040 2_5%~D

10K_040 2_5%~D

SMBCLK

RH239 0_ 0402_5%@ RH239 0_0402 _5%@

SMBDATA

2

+3V_MXM

R1528

R1528

2

D

D

1 2

12

2

D

D

G

G

1K_0402 _5%

1K_0402 _5%

G

G

16

S

S

QH3A

QH3A
DMN66D0LDW- 7

DMN66D0LDW- 7

RH237 0_0402 _5%@ RH237 0_0 402_5%@

16

S

S

QH1A

QH1A
DMN66D0LDW- 7

DMN66D0LDW- 7

D

D

1 2

RH252 0_0402 _5%@ RH252 0_0 402_5%@

1

+3V_MXM

RH235

RH235

D

D

1 2

2.2K_040 2_5%~D

2.2K_040 2_5%~D

5

G

G

DMN66D0LDW- 7

DMN66D0LDW- 7

DMN66D0LDW- 7

DMN66D0LDW- 7

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

DRAMRST_CNTRL_PCH

PCH_GPIO74

LID_SW_IN#

12

5

G

G

QH3B

QH3B
DMN66D0LDW- 7

DMN66D0LDW- 7

RH146

RH146

43

S

S

QH1B

QH1B
DMN66D0LDW- 7

DMN66D0LDW- 7

SML1CLK

SML1DATA

12

RH236

RH236

@

@

10K_040 2_5%~D

10K_040 2_5%~D

43

S

S

+3VS+3VS

1 2

1 2

+3VS

2

G

G

16

D

D

S

S

QH6A

QH6A

QH6B

QH6B

D

D

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96 #
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14 M

If use extenal CLK gen, please place close to
CLK gen . else, please place close to PCH

1 2

RH61 2. 2K_0402_5%~DRH61 2 .2K_0402_5 %~D

1 2

RH62 2. 2K_0402_5%~DRH62 2 .2K_0402_5 %~D

1 2

RH63 2. 2K_0402_5%~D

RH63 2. 2K_0402_5%~D

1 2

RH64 2. 2K_0402_5%~D

RH64 2. 2K_0402_5%~D

1 2

RH65 2. 2K_0402_5%~DRH65 2 .2K_0402_5 %~D

1 2

RH70 2. 2K_0402_5%~DRH70 2 .2K_0402_5 %~D

1 2

RH67 1K_ 0402_5%

RH67 1K_ 0402_5%

1 2

R1907 10K_04 02_5%~D

R1907 10K_04 02_5%~D

R1730 10K_0402 _5%~D

R1730 10K_0402 _5%~D

PEG_CLKREQ# <14 >

RH147

RH147

2.2K_040 2_5%~D

2.2K_040 2_5%~D

PCH_SMBCLK <5,10 ,11,12,13,1 6,34,35,43 >

PCH_SMBDATA <5,10 ,11,12,13, 16,34,35,4 3>

5

G

G

43

S

S

RH91 10K_0402_ 5%~D RH9 1 10 K_0402_5%~D

1 2

RH89 10K_0402_ 5%~D RH8 9 10 K_0402_5%~D

1 2

RH74 10K_0402_ 5%~D RH7 4 10 K_0402_5%~D

1 2

RH75 10K_0402_ 5%~D RH7 5 10 K_0402_5%~D

1 2

RH76 10K_0402_ 5%~D RH7 6 10 K_0402_5%~D

1 2

RH77 10K_0402_ 5%~D RH7 7 10 K_0402_5%~D

1 2

RH78 10K_0402_ 5%~D RH7 8 10 K_0402_5%~D

1 2

RH79 10K_0402_ 5%~D RH7 9 10 K_0402_5%~D

1 2

RH183 10K_040 2_5%~D R H183 10K_0402_5 %~D

1 2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

LA-8321P

LA-8321P

LA-8321P

1

+3V_PCH

+3VALW

12

EC_SMB_CK2 <15,30,40 ,41,44>

EC_SMB_DA2 <15,30,40 ,41,44>

17

17

17

0.1

0.1

0.1

65Tue sday, Janua ry 17, 2012

65Tue sday, Janua ry 17, 2012

65Tue sday, Janua ry 17, 2012

5

UH4C

UH4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82HM77 QPRG-C1 BGA989~D

BD82HM77 QPRG-C1 BGA989~D

DSWODVREN

DSWODVREN - On Die DSW VR Enable

*

H：Enable

：

Disable

L

1 2

1 2

+3V_PCH

5

G

G

QH11A

QH11A
DMN66D0LDW-7

DMN66D0LDW-7

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_IRCOMP

RBIAS_CPY

SUSACK#_R

XDP_DBRES ET#

PCH_SYS_PWROK

PM_PWROK_R

PM_DRAM_PWRGD

PCH_RSMRST#_R

SUSPWRDNACK_R

PBTN_OUT#_R

ACIN_PCH

BATLOW#

RI#

12

R1900

R1900
10K_0402_5%~D

10K_0402_5%~D

ACIN_PCH

D

D

S

S

4 3

QH11B

QH11B
DMN66D0LDW-7

DMN66D0LDW-7

DMI_CTX_PRX_N0<4>
DMI_CTX_PRX_N1<4>
DMI_CTX_PRX_N2<4>
DMI_CTX_PRX_N3<4>

DMI_CTX_PRX_P0<4>
DMI_CTX_PRX_P1<4>
DMI_CTX_PRX_P2<4>

D D

XDP_DBRES ET#<5,16>

C C

B B

VGATE<5,16,53>

PCH_PWROK<40>

PCH_APWROK<40>

PM_DRAM_PWRGD<5>

PCH_RSMRST#<40>

SUSPWRDNACK<40>

PBTN_OUT#<5,16,40>

ACIN<14,37,40,43,47>

DMI_CTX_PRX_P3<4>

DMI_CRX_PTX_N0<4>
DMI_CRX_PTX_N1<4>
DMI_CRX_PTX_N2<4>
DMI_CRX_PTX_N3<4>

DMI_CRX_PTX_P0<4>
DMI_CRX_PTX_P1<4>
DMI_CRX_PTX_P2<4>
DMI_CRX_PTX_P3<4>

+VCCP

RH111 49 .9_0402_1%RH111 49.9_0402_1%

RH112 75 0_0402_1%RH112 750_0402_1%

4mil width and p lace
within 500mil of the PCH

1 2

R1911 0_0402_5%~D@ R1911 0_0402_5%~D@

1 2

RH117 0_0402_5%~D@ RH117 0_0402_ 5%~D@

1 2

RH118 0_0402_5%~D@ RH118 0_0402_ 5%~D@

1 2

RH120 0_0402_5%~D@ RH120 0_0402_ 5%~D@

1 2

RH121 0_0402_5%~D@ RH121 0_0402_ 5%~D@

1 2

RH122 0_0402_5%~D@ RH122 0_0402_ 5%~D@

+3V_PCH

12

R1899

R1899

10K_0402_5%~D

10K_0402_5%~D

D

D

2

G

G

S

S

1 6

follow C RB Rev 0 .7

SUSPWRDNACK SUSACK#_R

A A

BATLOW#

RI#

WAKE#

1 2

RH135 0_ 0402_5%@ RH135 0_0402_5%@

RH139 1 0K_0402_5%~DRH139 10K_0402_5%~D

1 2

RH140 1 0K_0402_5%~DRH140 10K_0402_5%~D

1 2

RH142 1 K_0402_5% RH142 1K_0402 _5%

1 2

+3V_PCH

4

FDI_CTX_PRX_N0

BJ14

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6

DMI

DMI

System Power Management

System Power Management

RH127 3 30K_0402_5%~DRH127 3 30K_0402_5%~D

RH129 3 30K_0402_5%~D@RH129 330K_0 402_5%~D@

FDI_RXP7

FDI

FDI

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

12

12

FDI_CTX_PRX_N1

AY14

FDI_CTX_PRX_N2

BE14

FDI_CTX_PRX_N3

BH13

FDI_CTX_PRX_N4

BC12

FDI_CTX_PRX_N5

BJ12

FDI_CTX_PRX_N6

BG10

FDI_CTX_PRX_N7

BG9

FDI_CTX_PRX_P0

BG14

FDI_CTX_PRX_P1

BB14

FDI_CTX_PRX_P2

BF14

FDI_CTX_PRX_P3

BG13

FDI_CTX_PRX_P4

BE12

FDI_CTX_PRX_P5

BG12

FDI_CTX_PRX_P6

BJ10

FDI_CTX_PRX_P7

BH9

FDI_INT

AW16

FDI_FSYNC0

AV12

FDI_FSYNC1

BC10

FDI_LSYNC0

AV14

FDI_LSYNC1

BB10

DSWODVREN

A18

PCH_DPWROK_R

E22

WAKE#

B9

PM_CLKRUN#

N3

SUS_STAT#

G8

SUSCLK

N14

PM_SLP_S5#

D10

PM_SLP_S4#

H4

PM_SLP_S3#

F4

Can be left NC when IAMT is

G10

not support on the platfrom

PM_SLP_SUS#

G16

H_PM_SYNC

AP14

K14

+RTCVCC

FDI_CTX_PRX_N0 <4>
FDI_CTX_PRX_N1 <4>
FDI_CTX_PRX_N2 <4>
FDI_CTX_PRX_N3 <4>
FDI_CTX_PRX_N4 <4>
FDI_CTX_PRX_N5 <4>
FDI_CTX_PRX_N6 <4>
FDI_CTX_PRX_N7 <4>

FDI_CTX_PRX_P0 <4>
FDI_CTX_PRX_P1 <4>
FDI_CTX_PRX_P2 <4>
FDI_CTX_PRX_P3 <4>
FDI_CTX_PRX_P4 <4>
FDI_CTX_PRX_P5 <4>
FDI_CTX_PRX_P6 <4>
FDI_CTX_PRX_P7 <4>

FDI_INT <4>

FDI_FSYNC0 <4>

FDI_FSYNC1 <4>

FDI_LSYNC0 <4>

FDI_LSYNC1 <4>

0_0402_5%~D

0_0402_5%~D

1 2

RH113

@ RH113

@

RH115 0 _0402_5%~D@RH115 0_ 0402_5%~D@

1 2

T110 PAD~D

T110 PAD~D

@

RH119 0 _0402_5%~D@RH119 0_ 0402_5%~D@

If not using integrated
LAN,signal may be left as NC.

@

1 2

T112 PAD~D

T112 PAD~D

@

@

T113 PAD~D

T113 PAD~D

@

@

T114 PAD~D

T114 PAD~D

@

@

T115 PAD~D

T115 PAD~D

T116 PAD~D

T116 PAD~D

@

@

@

@

T165 PAD~D

T165 PAD~D

@

@

+3VS

1 2

RH128 2.2K_0402_5 %~DRH128 2.2K_0402_5 %~D

1 2

RH130 2.2K_0402_5 %~DRH130 2.2K_0402_5 %~D

1 2

RH153 2.2K_0402_5 %~DRH153 2.2K_0402_5 %~D

1 2

RH166 2.2K_0402_5 %~D

RH166 2.2K_0402_5 %~D

1 2

RV59 2.2K_0 402_5%~DRV59 2.2K_0402_5%~D

1 2

RV61 2.2K_0 402_5%~DRV61 2 .2K_0402_5%~D

1 2

R1901 10K_0402_ 5%~D@ R1901 10K_0402_5%~D@

1 2

R1736 10K_0402_ 5%~DR1736 10K_0402_5%~D

1 2

RH110 10 0K_0402_5%RH110 100K_0402_5%

1 2

RH243 10 0K_0402_5%~DRH243 100K_0402 _5%~D

RH244 2.37K _0402_1%RH244 2.37K_0402_1%

RH131 15 0_0402_1%RH131 150_0402_1%

RH132 15 0_0402_1%RH132 150_0402_1%

RH133 15 0_0402_1%RH133 150_0402_1%

RH134 10 0K_0402_5%RH134 100K_0402_5%

12

1 2

1 2

1 2

1 2

3

PCH_RSMRST#_R

PCIE_WAKE# <31,35,40,43>

SUSCLK_R <40>

PM_SLP_S5# <37,40>

PM_SLP_S4# <40>

PM_SLP_S3# <37,40>

H_PM_SYNC <5>

PCH_CRT_DDC_CL K

PCH_CRT_DDC_DA T

CTRL_CLK

CTRL_DATA

PCH_LCD_CL K

PCH_LCD_DA TA

PM_CLKRUN#

IGPU_BKLT_EN

TMDS_B_HPD

LVDS_IBG

PCH_CRT_BLU

PCH_CRT_GRN

PCH_CRT_RED

PCH_ENVDD

2

UH4D

IGPU_BKLT_EN<24>
PCH_ENVDD<24,40>

PCH_INV_PWM<24>

PCH_LCD_CL K<24>

PCH_LCD_DA TA<24>

PCH_CRT_BLU<26>
PCH_CRT_GRN<26>
PCH_CRT_RED<26>

PCH_CRT_DDC_CL K<26>
PCH_CRT_DDC_DA T<26>

PCH_CRT_HSYNC<26>
PCH_CRT_VSYNC<26>

IGPU_BKLT_EN
PCH_ENVDD

PCH_LCD_CL K
PCH_LCD_DA TA

CTRL_CLK
CTRL_DATA

LVDS_IBG

T203PAD~D@T203PAD~D

@

PCH_TXCLK-<24>
PCH_TXCLK+<24>

PCH_TXOUT0-<24>
PCH_TXOUT1-<24>
PCH_TXOUT2-<24>

PCH_TXOUT0+<24>
PCH_TXOUT1+<24>
PCH_TXOUT2+<24>

PCH_TZCLK-<24>
PCH_TZCLK+<24>

PCH_TZOUT0-<24>
PCH_TZOUT1-<24>
PCH_TZOUT2-<24>

PCH_TZOUT0+<24>
PCH_TZOUT1+<24>
PCH_TZOUT2+<24>

PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED

PCH_CRT_DDC_CL K
PCH_CRT_DDC_DA T

RH123 33_0 402_5%~DRH123 33_0 402_5%~D

RH124 33_0 402_5%~DRH124 33_0 402_5%~D

1K_0402_0.5%

1K_0402_0.5%

1 2
1 2

RH126

RH126

12

HSYNC
VSYNC

CRT_IREF

UH4D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CL K

K47

L_DDC_DA TA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CL K#

AK40

LVDSA_CL K

AN48

LVDSA_DA TA#0

AM47

LVDSA_DA TA#1

AK47

LVDSA_DA TA#2

AJ48

LVDSA_DA TA#3

AN47

LVDSA_DA TA0

AM49

LVDSA_DA TA1

AK49

LVDSA_DA TA2

AJ47

LVDSA_DA TA3

AF40

LVDSB_CL K#

AF39

LVDSB_CL K

AH45

LVDSB_DA TA#0

AH47

LVDSB_DA TA#1

AF49

LVDSB_DA TA#2

AF45

LVDSB_DA TA#3

AH43

LVDSB_DA TA0

AH49

LVDSB_DA TA1

AF47

LVDSB_DA TA2

AF43

LVDSB_DA TA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82HM77 QPRG-C1 BGA989~D

BD82HM77 QPRG-C1 BGA989~D

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

CRT

HDMICLK_NB <27>
HDMIDAT_NB <27>

TMDS_B_HPD <27>

TMDS_B_DATA2# <27>
TMDS_B_DATA2 <27>
TMDS_B_DATA1# <27>
TMDS_B_DATA1 <27>
TMDS_B_DATA0# <27>
TMDS_B_DATA0 <27>
TMDS_B_CLK# <27>
TMDS_B_CLK <27>

PCH_DPC_C LK <28>
PCH_DPC_D AT <28>

PCH_DPC_A UXN <28>
PCH_DPC_A UXP <28>

PCH_DPC_HPD <28>

PCH_DPC_N0 <28>
PCH_DPC_P 0 <28>
PCH_DPC_N1 <28>
PCH_DPC_P 1 <28>
PCH_DPC_N2 <28>
PCH_DPC_P 2 <28>
PCH_DPC_N3 <28>
PCH_DPC_P 3 <28>

PCH_DPD_C LK <29>
PCH_DPD_D AT <29>

PCH_DPD_A UXP <29>

PCH_DPD_A UXN <29>

PCH_DMC_HPD <29>

PCH_DPD_N0 <29>
PCH_DPD_P 0 <29>
PCH_DPD_N1 <29>
PCH_DPD_P 1 <29>
PCH_DPD_N2 <29>
PCH_DPD_P 2 <29>
PCH_DPD_N3 <29>
PCH_DPD_P 3 <29>

1

HDMI

mini DP

DMC
( HDMI )

DELL CONFIDENTIAL/PROPRIETARY

SUSPWRDNACK

PCH_RSMRST#

RH144 1 0K_0402_5%~D@ RH144 10K_0402 _5%~D@

1 2

RH145 1 0K_0402_5%~DRH145 10K_0402_5%~D

1 2

5

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SE CRET AN D OTHER PROPRIE TARY INF ORMATION OF DEL L. THIS DOCUMEN T MAY NO T
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WI THOUT D ELL'S EX PRESS W RITTEN C ONSENT.

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

65Tuesday, January 17, 2012

18

18

18

5

T118PAD~D @T118PAD~D @
T119PAD~D @T119PAD~D @
T130PAD~D @T130PAD~D @
T120PAD~D @T120PAD~D @
T131PAD~D @T131PAD~D @
T132PAD~D @T132PAD~D @
T121PAD~D @T121PAD~D @
T122PAD~D @T122PAD~D @
T139PAD~D @T139PAD~D @
T123PAD~D @T123PAD~D @
T124PAD~D @T124PAD~D @

D D

USB3RN1<43>
USB3RN2<43>
USB3RN3<36>
USB3RN4<36>
USB3RP1<4 3>
USB3RP2<4 3>
USB3RP3<3 6>
USB3RP4<3 6>
USB3TN1<43>
USB3TN2<43>
USB3TN3<36>
USB3TN4<36>
USB3TP1<43 >

C C

B B

CLK_PCI_LPBACK<17 >
CLK_PCI_LPC<40>
CLK_DEBUG<35>

WL_OFF#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQC#
DMC_RADIO_OFF#
BT_ON#
DGPU_SELECT#
FFS_INT1 DGPU_HOLD_ RST#
HDMI_IN_PWMSEL#
PCI_PIRQA#
ODD_DA#
DGPU_HOLD_ RST#

CLK_PCI_LPBACK
CLK_PCI_LPC
CLK_DEBUG CLK_PCI2

RH275 8.2K_0 402_5%~DRH275 8.2K_ 0402_5%~D

1 2

RH276 8.2K_0 402_5%~DRH276 8.2K_ 0402_5%~D

1 2

RH277 8.2K_0 402_5%~DRH277 8.2K_ 0402_5%~D

1 2

RH278 8.2K_0 402_5%~DRH278 8.2K_ 0402_5%~D

1 2

RH279 8.2K_0 402_5%~DRH279 8.2K_ 0402_5%~D

1 2

RH280 8.2K_0 402_5%~DRH280 8.2K_ 0402_5%~D

1 2

RH281 8.2K_0 402_5%~DRH281 8.2K_ 0402_5%~D

1 2

RH282 8.2K_0 402_5%~DRH282 8.2K_ 0402_5%~D

1 2

RH283 8.2K_0 402_5%~DRH283 8.2K_ 0402_5%~D

1 2

RH284 8.2K_0 402_5%~DRH284 8.2K_ 0402_5%~D

1 2

RH285 8.2K_0 402_5%~DRH285 8.2K_ 0402_5%~D

1 2

RH165 10K_04 02_5%~D@ RH165 1 0K_0402_5%~D@

1 2

USB3TP2<43 >
USB3TP3<36 >
USB3TP4<36 >

DGPU_SELECT#<24,26,2 7,28,29>
DGPU_PWR_EN<42>

DMC_RADIO_OFF#<35>
HDMI_IN_PWMSEL#<24>

FFS_INT1<3 4>
ODD_DA#<34>
DP_CBL_DET<28>

BT_ON#<35>

RH160 22_04 02_5%RH1 60 22_ 0402_5%
RH102 22_04 02_5%RH1 02 22_ 0402_5%

1 2

RH169 22_04 02_5%RH1 69 22_ 0402_5%

T134PAD~D @T134PAD~D @
T140PAD~D @T140PAD~D @
T125PAD~D @T125PAD~D @
T126PAD~D @T126PAD~D @
T135PAD~D @T135PAD~D @
T136PAD~D @T136PAD~D @
T127PAD~D @T127PAD~D @
T128PAD~D @T128PAD~D @
T129PAD~D @T129PAD~D @

T142PAD~D @T142PAD~D @
T143PAD~D @T143PAD~D @
T144PAD~D @T144PAD~D @
T145PAD~D @T145PAD~D @

USB3RN1
USB3RN2
USB3RN3
USB3RN4
USB3RP1
USB3RP2
USB3RP3
USB3RP4
USB3TN1
USB3TN2
USB3TN3
USB3TN4
USB3TP1
USB3TP2
USB3TP3
USB3TP4

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_ RST#

DGPU_SELECT#

DMC_RADIO_OFF#
HDMI_IN_PWMSEL#
WL_OFF#

WL_OFF#<35>

FFS_INT1
ODD_DA#

BT_ON#

T206PAD~D @T206PAD~D @

PCH_PLTRST#

T200PAD~D @T200PAD~D @
T199PAD~D @T199PAD~D @

+3VS

CLK_PCI0
CLK_PCI1

CLK_PCI3
CLK_PCI4

12

12

4

UH4E

UH4E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3TP1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82HM77 QPRG -C1 BGA989~D

BD82HM77 QPRG -C1 BGA989~D

10K_040 2_5%~D

10K_040 2_5%~D

PLT_RST#<5,16,31,3 5,40,43>

RH262

@ RH262

@

RSVD

RSVD

USB30

USB30

PCI

PCI

+3VS

1 2

12

EHCIⅠ

USB

USB

EHCIⅡ

RH157

RH157
100K_04 02_5%

100K_04 02_5%

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

+3VS

5

UH3

UH3

P

IN1

4

O

IN2

G

SN74AHC1G0 8DCKR_SC70-5

SN74AHC1G0 8DCKR_SC70-5

3

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8

AY5
BA2

AT12
BF3

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

C1847

C1847

1 2

0.1U_04 02_25V6K~D

0.1U_04 02_25V6K~D

1

2

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6

USB20_N8
USB20_P8
USB20_N9
USB20_P9

USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB20_N13
USB20_P13

USBRBIAS

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#

1.5VDDR_VID0

1.5VDDR_VID1
ESATA_DETECT#

PCH_PLTRST#

3

USB20_N0 <43 >
USB20_P0 <43>
USB20_N1 <43 >
USB20_P1 <43>
USB20_N2 <36 >
USB20_P2 <36>
USB20_N3 <36 >
USB20_P3 <36>
USB20_N4 <35 >
USB20_P4 <35>
USB20_N5 <35 >
USB20_P5 <35>
USB20_N6 <37 >
USB20_P6 <37>

USB20_N8 <35 >
USB20_P8 <35>
USB20_N9 <43 >
USB20_P9 <43>

USB20_N11 <43>
USB20_P11 <43 >
USB20_N12 <25>
USB20_P12 <25 >
USB20_N13 <44>
USB20_P13 <44 >

Within 500 mils

1 2

RH151 22 .6_0402_1 %RH151 2 2.6_0402_ 1%

USB_OC0# <16,43>
USB_OC1# <16,43>
USB_OC2# <16,36>
USB_OC3# <16,36>
USB_OC4# <16,43>

1.5VDDR_VID0 < 16,51>

1.5VDDR_VID1 < 16,51>
ESATA_DETECT# <16,4 3>

USB/B

USB/B

USB/B

USB/B

Mini Card(WLAN)

DMC

ELC

Bluetooth

USB / eSATA combo Conn.

EXPRESS CARD

Camera

VPK

(For USB Port 0)
(For USB Port 1)
(For USB Port 2)
(For USB Port 3)
(For USB Port 9)

PLTRST_VGA#<14,15 >

RH230

RH230
0_0402 _5%~D

0_0402 _5%~D

@ R1908

@

10K_040 2_5%~D

10K_040 2_5%~D

12

100K_04 02_5%

100K_04 02_5%

R1908

RH231

RH231

+3V_MXM

2

USB_OC0#

1.5VDDR_VID1
USB_OC3#
USB_OC2#
USB_OC1#
USB_OC4#
ESATA_DETECT#

1.5VDDR_VID0

1 2

RH254 0_04 02_5%@ RH254 0_04 02_5%@

12

12

+3VS

UH5

UH5

4

O

C1848

C1848

1 2

0.1U_04 02_25V6K~D

0.1U_04 02_25V6K~D

5

PCH_PLTRST#

1

P

IN1

2

IN2

G

SN74AHC1G0 8DCKR_SC70-5

SN74AHC1G0 8DCKR_SC70-5

3

RH267 10K_0 402_5%~DRH267 10K_0402 _5%~D

1 2

RH268 10K_0 402_5%~DRH268 10K_0402 _5%~D

1 2

RH269 10K_0 402_5%~DRH269 10K_0402 _5%~D

1 2

RH270 10K_0 402_5%~DRH270 10K_0402 _5%~D

1 2

RH271 10K_0 402_5%~DRH271 10K_0402 _5%~D

1 2

RH272 10K_0 402_5%~DRH272 10K_0402 _5%~D

1 2

RH273 10K_0 402_5%~DRH273 10K_0402 _5%~D

1 2

RH274 10K_0 402_5%~DRH274 10K_0402 _5%~D

1 2

1

+3V_PCH

12/19-86

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesda y, January 17, 2012

65Tuesda y, January 17, 2012

65Tuesda y, January 17, 2012

19

19

19

5

+3VS

RH232

2

G

G

RH232
10K_040 2_5%~D

10K_040 2_5%~D

1 2

13

D

D

QH2

QH2
2N7002E- T1-E3_SOT23-3

2N7002E- T1-E3_SOT23-3

S

S

High: CRT Plugged

CRT_DET

D D

GPIO28

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H：On-Die voltage regulator enable

*

L

：

On-Die PLL Voltage Regulator disable

+3V_PCH

RH286 10K_04 02_5%~DRH286 10K_0 402_5%~D

1 2

1 2

RH238 1K_04 02_5%@ RH238 1K_040 2_5%@

PCH_GPIO37

C C

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated

*

to same voltage
(DC Coupling Mode)

+3VS

RH173 1K_040 2_5%@RH173 1K_0402 _5%@

RH174 10K_04 02_5%~DRH174 10K_0 402_5%~D

1 2

CRT_DET#<26>

PCH_GPIO28

12

PCH_GPIO37

GPIO27

PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable

*

Low: VCCVRM VR Disable

RH241 1 0K_0402_5%~D@ RH241 10K_0402_5%~D@

B B

1 2

PCH_GPIO27

Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.

4

UH4F

CRT_DET<16>

DGPU_EDIDSEL#<24,27,2 8,29>

DGPU_HPD_INT#<27>

EC_SCI#<40>

EC_SMI#<40>

BT_RADIO_DIS#<35>

PCH_GPIO15<16 >

PCH_GPIO16<16 >

DGPU_PWROK<14>

ODD_EN#<34>

MXM2_PCH_PWR_ON<15,16 >

ODD_DETECT#<16,34>

PCH_GPIO37<16>

VGA_PRSNT_R#<1 4>

VGA_PRSNT_L#<14>

MXM2_PRSNT_R#<15,16>

HDD2_DETECT#<34>

CRT_DET

DGPU_EDIDSEL#

DGPU_HPD_INT#

EC_SMI#

PCH_GPIO15

PCH_GPIO16

PCH_GPIO22

ODD_EN#

PCH_GPIO27

PCH_GPIO28

STP_PCI#

MXM2_PCH_PWR_ON

ODD_DETECT#

PCH_GPIO37

VGA_PRSNT_R#

VGA_PRSNT_L#

FFS_INT2<34>

MXM2_PRSNT_R# MXM2_PRSNT_R#

HDD2_DETECT#

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

UH4F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82HM77 QPRG -C1 BGA989~D

BD82HM77 QPRG -C1 BGA989~D

GPIO

GPIO

NCTF

NCTF

3

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

CPU/MISC

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

LVDS_CAB_DET#

PCH_PECI_R

KB_RST#

H_THERMTRIP#_C

INIT3_3V#

NV_CLE

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

DGPU_BKL_PWM_SEL# <24>

MXM2_PCH_PWROK <1 5>

LVDS_CAB_DET# <25>

MXM2_EC_RST# <15>

@

1 2

RH1590_04 02_5%@RH1590_04 02_5%

KB_RST# <40>

H_CPUPWRGD < 5>

1 2

T141 PAD~D@ T141 PAD~D@

H_THRMTRIP#

RH161390_0 402_5% RH161390 _0402_5%

12

@

@

RH261

RH261
10K_040 2_5%~D

10K_040 2_5%~D

Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.

2

+3VS

RH158

RH158
10K_040 2_5%~D

10K_040 2_5%~D

1 2

H_PECI <5,40>

INIT3_3V

This signal has weak internal
PU, can't pull low

GATEA20 <40>

H_THRMTRIP# <5>

DGPU_HPD_INT#

DGPU_EDIDSEL#

VGA_PRSNT_L#

VGA_PRSNT_R#

PCH_GPIO16

ODD_EN#

HDD2_DETECT#

PCH_GPIO15

EC_SMI#

CRT_DET#

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Weak internal
PU,Do not pull low

NV_CLE

1 2

RH150 1K_0402 _5%RH1 50 1K_04 02_5%

CLOSE TO THE BRANCHING POINT

RH265 10K_0 402_5%~DRH265 10K_0 402_5%~D

1 2

RH163 10K_0 402_5%~DRH163 10K_0 402_5%~D

1 2

RH164 10K_0 402_5%~DRH164 10K_0 402_5%~D

1 2

RH182 10K_0 402_5%~DRH182 10K_0 402_5%~D

1 2

RH167 10K_0 402_5%~DRH167 10K_0 402_5%~D

1 2

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH181

RH181

+3V_PCH

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH176

RH176

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH170

RH170

1K_0402 _5%

1K_0402 _5%

1 2

RH177

RH177

10K_040 2_5%~D

10K_040 2_5%~D

1 2

RH71

RH71

10K_040 2_5%~D@

10K_040 2_5%~D@

1 2

RH178

RH178

+3VS

+3VS

+1.8VS

12

1

RH149

RH149

2.2K_040 2_5%~D

2.2K_040 2_5%~D

H_SNB_IVB# <5>

PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16

Please refer to Huron River Debug Board DG 0.5

A A

SATA2GP/GPIO36

When Used as SATA2GP/SATA3GP for Mechanical Presence detect

- Use a weak external pull-up (150K-200K ohms) to Vcc3_3

check list Rev 1.0

*

RH171

RH171
200K_04 02_5%

ODD_DETECT#

200K_04 02_5%

1 2

+3VS

STP_PCI#

KB_RST#

PCH_GPIO22

LVDS_CAB_DET#

1 2

RH180

RH180

1 2

RH203

RH203

1 2

RH179

RH179

1 2

R1740

R1740

10K_040 2_5%~D

10K_040 2_5%~D

10K_040 2_5%~D

10K_040 2_5%~D

10K_040 2_5%~D

10K_040 2_5%~D

10K_040 2_5%~D

10K_040 2_5%~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL. THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC

LA-8321P

LA-8321P

LA-8321P

1

0.1

0.1

0.1

65Tuesda y, January 17, 2012

65Tuesda y, January 17, 2012

65Tuesda y, January 17, 2012

20

20

20