Compal LA-8127P VALEA, ThinkPad Edge E455, ThinkPad Edge E545, LA-8127P VALEB Schematic

A

1 1

B

C

D

E

Compal Confidential

2 2

VALEA/VALEB Schematics Document

AMD APU Richland FS1r2 + FCH Bolton-M3 + GPU Sun Pro M2

2012-11-22

3 3

4 4

A

B

REV:1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Compal Electronics, Inc.

Cover Page

LA-8127P

1 51Tuesday, March 12, 2013

E

1.0

A

ompal confidential

C

ile Name : VALEA/VALEB

F

S

n Pro M2

u

B

C

D

E

V

AM

1 1

R 128M16/256M16 DDR3 x 4

Page 17

～～～～

24

LVDS translator

RTD2132S

Page 25

HDMI Conn.

Page 27

4 * x1 PCI-E 2.0

LVDS Conn.

Page 26

GPP1GPP3

CardReader

2 2

4 in 1 Conn.

PCI Express Mini card Slot 1

WLAN

Page 33

IC

RTS5229

USB(BT)

PCI-E(WLAN)

CRT CONN

Page 28

GPP0

LAN

RTL 8111F

FCH CRT (VGA DAC)

SPI ROM 4MB

3 3

Sub board

Power Board

LAN

Page 35

15" only

ODD board

G Sensor

ST LIS34ALTR

Audio Jack+ USB2.0

G

DP Port0

DP Port2

DP Port1

Page 13

Page 30

Tr

n2PCIE x 8

e

AMD FS1r2 APU

ack Point

Page 33

Click Pad

Richland uPGA 722 pin 35mm x 35mm

Page 5

x4 UMI Gen. 1

2.5GT/s per lane

Bolton M3

uFCBGA-656

24.5mm x 24.5mm

Page 12

LPC BUS

EC

ENE KB9012

Page 33

Page 31

M

emory BUS(DDRIII)

～～～～

9

AZALIA

14*USB2.0/ 4*USB3.0,10*USB2.0

6*SATA serial

～～～～

16

Int.KBD

Page 33

Dual Channel

1.5V DDRIII 1600 (1866)

SATA0

SATA1

04pin DDRIII-SO-DIMM X2

2

BANK 0, 1, 2

Page 10

～～～～

11

2Channel Speaker

Audio Codec

CX20671-21Z

Page 29

CMOS Camera

BlueTooth CONN

USB PORT 3.0 x3

Internal MIC

Audio Jacks

Combo jack

Page 26

Page 32

Page 34

USB PORT 2.0 x1 +Charger

WLAN

Page 33

Finger Printer

UPEK TCS5DA6C0

SATA3.0 HDD CONN

SATA ODD CONN

Page 30

4 4

FingerPrint

Card reader

A

B

Thermal Sensor

Fintek 5303

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

Page 32

Compal Secret Data

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Compal Electronics, Inc.

Block Diagrams

LA-8127P

2 51Tuesday, March 12, 2013

E

1.0

A

Voltage Rails

Power Plane Description

V

N

I

B+

+APU_CORE

+APU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU

1 1

+1.5V ON

+0.75VS OFFON OFF0.75V switched power rail for DDR terminator

+1.2VS ON OFF OFF

+2.5VS

+1.1VALW 1.1V switched power rail for FCH ON ON*ON

+1.1VS

+1.5VS OFF1.5V switched power rail ON OFF

+VGA_CORE OFFOFFON

+1.5VGS

+1.8VGS OFFON OFF1.8V switched power rail

+0.95VGS ON OFF OFF0.95V switched power rail for VGA

+3VALW

+3VS_WLAN ON OFF

+3VS

2 2

+5VALW

+5VS

+VSB ON ON*

+RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device Address Address

Smart Battery

3 3

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for APU

1.5V power rail for APU VDDIO and DDR

1.2V (VDDR, VDDP) switched power rail for APU

2.5V for APU VDDA

0.95-1.2V switched power rail

1.5V switched power rail

3.3V always on power rail

3.3V power rail for WLAN

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

RTC power

EC SM Bus2 address

0001-011xb

HEX

15H

Device

F75303 (DDR,VRAM,CPUCORE)1001-101xb

SB-TSI

Sun Pro M2

LVDS translator

B

S0 S3 S5

N/A N/A N/A

ON OFF

ON

ON OFF OFF1.1V switched power rail for FCH

ON OFF

ON

1001-100xb

1000-0010b

N/AN/AN/A

OFF

ON

OFF

ON ON*

OFF

ON

ON*

OFF

OFFON

ONON

HEX

9AH

98H

82H

C

H Hudson-M2/3

F SATA Port List

ATA0

S

SATA1

SATA2

SATA3

SATA4

SATA5

HDD

ODD

NC

BOM Structure

UMA@ : UMA only DIS@ : DIS muxless

CMOS@ : USB camera

CONN@ : ME components

C

Comal

PCIE Port List

AN

L

WLAN

NC

Card Reader

NC

APUFCH

CIE0

P

PCIE1

PCIE2

PCIE3

PCIE0

PCIE1

PCIE2

PCIE3

D

C

H Hudson-M2/3

F USB Port List

U

SB1.1

Port0

Port1

USB2.0

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Port8

Port9

Port10

Port11

Port12

Port13

USB2.0 Port

WLAN

CMOS

USB 3.0

E

NC

FP

BT

NC

X76@, H1G@, S1G@ : VRAM

BOM option and stencil

SDV:

FCH SMB0

Device Address

DDR DIMM1 (FCH_SMB0)

DDR DIMM2 (FCH_SMB0)

4 4

WLAN (FCH_SMB0)

Security ROM

1001-000xb

1001-001xb

(FCH_SMB0)

HEX

90

92

Stencil Memo

A

B

CMOS@/DIS@ + X76@

PJ201,PJ401,PJ502,PJ503,PJ504,PJ601,PJ603,PJ604, PJ701,PJ702,PJ703,PJ704,J1,J2301,J2401,J2402,J2403 PJ402,PJ403,PJ501,PJ602,PJ801,PJ802,PJ803,PJ805

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-8127P

E

3 51Tuesday, March 12, 2013

1.0

5

4

3

2

1

Power-Up/Down Sequence

‧

All the ASIC supplies, except for VDDR3, must fully reach their respective

ominal voltages within 20 ms of the start of the ramp-up sequence, though a

n shorter ramp-up duration is preferred. There is no timing requirement on the ramp up of VDDR3 relative to other power rails.

The external pull-up resistors on the DDC/AUX signals (if applicable) should

‧

r

amp up before or after both VDDC and VDD_CT have ramped up.

D D

‧

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC

hould reach 90% before VDD_CT starts to ramp up (or vice versa).

s

For power down, reversing the ramp-up sequence is recommended.

‧

APU

FCH

GPIO191

A

U_PCIE_RST#

P

S_RST#

X

AND GATE

G

P

U_RST#

PERSTB

GPU

VDDR3(3.3VGS)

PCIE_VDDC(0.95VGS)

GPIO192

GPIO51

PXS_PWREN

VGA_PWRGD

VDDR1(1.5VGS)

VDDC/VDDCI(1.12V)

PXS_PWREN

VDD_CT(1.8VGS)

C C

PERSTb

+3VS

+3VALW

MOS

Regulator

+3VGS

1

+0.95VGS

2

+1.8VS

MOS

+1.8VGS

5

REFCLK

Straps Reset

B+

PWM

4

+VGA_CORE

+1.5VS

MOS

+1.5VGS

3

Straps Valid

Global ASIC Reset

PS_3[ 0 ]PS_3[ 1 ]

0

10

00 1

0

10

01

T4+16clock

R_pu R_pd

R1430 R1436

NC 4.75K

R1430

8.45K

R1430

4.53K 2K

R1430

6.98K

R1430

4.53k 4.99K

R1430

3.24k 5.62k

R1430

3.4k

R1430

4.75K

R1436

2K

R1436

4.99K

R1436

10k

R1436

NC

ZZZ2

ZZZ1

S1G

S1G@

X7635939L09

ZZZ4

S2G

S2G@

X7635939L11

4

ZZZ2

H1G

H1G@

X7635939L10

ZZZ5

M2G

M2G@

X7635939L12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

dGPU Block Diagram

Custom

dGPU Block Diagram

LA-8127P

4 51Tuesday, March 12, 2013

1

4 51Tuesday, March 12, 2013

1.0

SUN PRO VRAM STRAP

B B

1G

2G

1G

A A

Vendor

H5TQ2G63DFR-11C SA00003YO70

K4W2G1646E-BC11 SA00005SH00

MT41J128M16JT-093G SA000067510 FBGA Code:D9PTD

K4W4G1646B-HC11 SA000068R00

MT41K256M16HA-107G SA000065D00 FBGA Code:D9PZD

MT41J128M16JT-107G SA00005SM30 FBGA Code:D9PRS

K4W2G1646E-BC1A SA000068U10

5

PS_3[ 2 ]

0 0

0

1

0 1

1

0

1

1 1

A

B

C

D

E

P

IE_CRX_GTX_P[0..7][17]

C

P

IE_CRX_GTX_N[0..7][17]

C

J

PU1A

C

P

I EXPRESS

C

GFX_RXP0 GFX_RXN0 GFX_RXP1 GFX_RXN1 GFX_RXP2 GFX_RXN2

C

GPP GRAPHICS

UMI

P

GFX_TXP0

_ _

GFX_TXN0

P P

GFX_TXP1

_

P

GFX_TXN1

_ _

GFX_TXP2

P P

GFX_TXN2

_ P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9 P_GFX_TXN9

P_GFX_TXP10 P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11 P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13 P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14 P_GFX_TXP15 P_GFX_TXN15

P_GPP_TXP0 P_GPP_TXN0 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3

P_ZVSS

AB2

P

IE_CTX_C_GRX_P0

C

AB1

C

IE_CTX_C_GRX_N0

P

AA3

P

IE_CTX_C_GRX_P1

C

AA2

P

IE_CTX_C_GRX_N1

C

Y5

C

IE_CTX_C_GRX_P2

P

Y4

P

IE_CTX_C_GRX_N2

C

Y2

PCIE_CTX_C_GRX_P3

Y1

PCIE_CTX_C_GRX_N3

W3

PCIE_CTX_C_GRX_P4

W2

PCIE_CTX_C_GRX_N4

V5

PCIE_CTX_C_GRX_P5

V4

PCIE_CTX_C_GRX_N5

V2

PCIE_CTX_C_GRX_P6

V1

PCIE_CTX_C_GRX_N6

U3

PCIE_CTX_C_GRX_P7

U2

PCIE_CTX_C_GRX_N7

T5 T4 T2 T1 R3 R2 P5 P4 P2 P1 N3 N2 M5 M4 M2 M1

AD5

PCIE_CTX_C_DRX_P0

AD4

PCIE_CTX_C_DRX_N0

AD2

PCIE_CTX_C_DRX_P1

AD1

PCIE_CTX_C_DRX_N1

AC3 AC2 AB5

PCIE_CTX_C_DRX_P3

AB4

PCIE_CTX_C_DRX_N3

AG2

UMI_TXP0_C

AG3

UMI_TXN0_C

AF4

UMI_TXP1_C

AF5

UMI_TXN1_C

AF1

UMI_TXP2_C

AF2

UMI_TXN2_C

AE2

UMI_TXP3_C

AE3

UMI_TXN3_C

AH11

P_ZVSS

C

C C

C C7 .1U_0402_16V7KDIS@C7 .1U_0402_16V7KDIS@ C8 .1U_0402_16V7KDIS@C8 .1U_0402_16V7KDIS@ C9 .1U_0402_16V7KDIS@C9 .1U_0402_16V7KDIS@ C10 .1U_0402_16V7KDIS@C10 .1U_0402_16V7KDIS@ C11 .1U_0402_16V7KDIS@C11 .1U_0402_16V7KDIS@ C12 .1U_0402_16V7KDIS@C12 .1U_0402_16V7KDIS@ C13 .1U_0402_16V7KDIS@C13 .1U_0402_16V7KDIS@ C14 .1U_0402_16V7KDIS@C14 .1U_0402_16V7KDIS@ C15 .1U_0402_16V7KDIS@C15 .1U_0402_16V7KDIS@ C16 .1U_0402_16V7KDIS@C16 .1U_0402_16V7KDIS@

1 2

R2 196_0402_1%R2 196_0402_1%

Power Sequence of APU

P

IE_CRX_GTX_P0

C C

IE_CRX_GTX_N0

P P

IE_CRX_GTX_P1

1 1

2 2

PCIE_CRX_DTX_P0[35]

LAN WLAN

Card Reader

3 3

PCIE_CRX_DTX_N0[35] PCIE_CRX_DTX_P1[33] PCIE_CRX_DTX_N1[33]

PCIE_CRX_DTX_P3[35] PCIE_CRX_DTX_N3[35]

UMI_RXP0[12] UMI_RXN0[12] UMI_RXP1[12] UMI_RXN1[12] UMI_RXP2[12] UMI_RXN2[12] UMI_RXP3[12] UMI_RXN3[12]

+1.2VS

C

P

IE_CRX_GTX_N1

C C

IE_CRX_GTX_P2

P P

IE_CRX_GTX_N2

C PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

1 2

R1 196_0402_1%R1 196_0402_1%

P_ZVDDP

AB8

P

_

AB7

_

P

AA9

P

_

AA8

P

_

AA5

_

P

AA6

P

_

Y8

P_GFX_RXP3

Y7

P_GFX_RXN3

W9

P_GFX_RXP4

W8

P_GFX_RXN4

W5

P_GFX_RXP5

W6

P_GFX_RXN5

V8

P_GFX_RXP6

V7

P_GFX_RXN6

U9

P_GFX_RXP7

U8

P_GFX_RXN7

U5

P_GFX_RXP8

U6

P_GFX_RXN8

T8

P_GFX_RXP9

T7

P_GFX_RXN9

R9

P_GFX_RXP10

R8

P_GFX_RXN10

R5

P_GFX_RXP11

R6

P_GFX_RXN11

P8

P_GFX_RXP12

P7

P_GFX_RXN12

N9

P_GFX_RXP13

N8

P_GFX_RXN13

N5

P_GFX_RXP14

N6

P_GFX_RXN14

M8

P_GFX_RXP15

M7

P_GFX_RXN15

AE5

P_GPP_RXP0

AE6

P_GPP_RXN0

AD8

P_GPP_RXP1

AD7

P_GPP_RXN1

AC9

P_GPP_RXP2

AC8

P_GPP_RXN2

AC5

P_GPP_RXP3

AC6

P_GPP_RXN3

AG8

P_UMI_RXP0

AG9

P_UMI_RXN0

AG6

P_UMI_RXP1

AG5

P_UMI_RXN1

AF7

P_UMI_RXP2

AF8

P_UMI_RXN2

AE8

P_UMI_RXP3

AE9

P_UMI_RXN3

AG11

P_ZVDDP

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

1 2

1U_0402_16V7KDIS@

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1U_0402_16V7KDIS@ 1U_0402_16V7KDIS@

1U_0402_16V7KDIS@

1 .

1 . 2 .

2 . 3 .

3 . 4 .

4 . 5 .

5 . 6 .

6 .

C33 .1U_0402_16V7KC33 .1U_0402_16V7K C34 .1U_0402_16V7KC34 .1U_0402_16V7K C123 .1U_0402_16V7KC123 .1U_0402_16V7K C124 .1U_0402_16V7KC124 .1U_0402_16V7K

C35 .1U_0402_16V7KC35 .1U_0402_16V7K C36 .1U_0402_16V7KC36 .1U_0402_16V7K

C37 .1U_0402_16V7KC37 .1U_0402_16V7K C38 .1U_0402_16V7KC38 .1U_0402_16V7K C39 .1U_0402_16V7KC39 .1U_0402_16V7K C40 .1U_0402_16V7KC40 .1U_0402_16V7K C41 .1U_0402_16V7KC41 .1U_0402_16V7K C42 .1U_0402_16V7KC42 .1U_0402_16V7K C43 .1U_0402_16V7KC43 .1U_0402_16V7K C44 .1U_0402_16V7KC44 .1U_0402_16V7K

P

IE_CTX_GRX_P0

C C

IE_CTX_GRX_N0

P P

IE_CTX_GRX_P1

C

P

IE_CTX_GRX_N1

C C

IE_CTX_GRX_P2

P P

IE_CTX_GRX_N2

C PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

P

IE_CTX_GRX_P[0..7] [17]

C

P

IE_CTX_GRX_N[0..7] [17]

C

SDV/FVT, NO.1SDV/FVT, NO.1

PCIE_CTX_DRX_P0 [35] PCIE_CTX_DRX_N0 [35] PCIE_CTX_DRX_P1 [33] PCIE_CTX_DRX_N1 [33]

PCIE_CTX_DRX_P3 [35] PCIE_CTX_DRX_N3 [35]

UMI_TXP0 [12] UMI_TXN0 [12] UMI_TXP1 [12] UMI_TXN1 [12] UMI_TXP2 [12] UMI_TXN2 [12] UMI_TXP3 [12] UMI_TXN3 [12]

+1.5V

+2.5VS

Group A

+1.5VS

+APU_CORE

+APU_CORE_NB

Group B

+1.2VS

4 4

Security Classification

2012/11/22 2015/11/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

FS1r2 PCIE/UMI

LA-8127P

5 51Tuesday, March 12, 2013

E

1.0

A

1 1

J

PU1B

C

M

MORY CHANNEL A

E

DDRA_SMA[15..0][10]

DDRA_SBS0#[10] DDRA_SBS1#[10] DDRA_SBS2#[10] DDRA_SDM[7..0][10]

2 2

DDRA_SDQS0[10] DDRA_SDQS0#[10] DDRA_SDQS1[10] DDRA_SDQS1#[10] DDRA_SDQS2[10] DDRA_SDQS2#[10] DDRA_SDQS3[10] DDRA_SDQS3#[10] DDRA_SDQS4[10] DDRA_SDQS4#[10] DDRA_SDQS5[10] DDRA_SDQS5#[10] DDRA_SDQS6[10] DDRA_SDQS6#[10] DDRA_SDQS7[10] DDRA_SDQS7#[10]

DDRA_CLK0[10] DDRA_CLK0#[10] DDRA_CLK1[10] DDRA_CLK1#[10]

DDRA_CKE0[10] DDRA_CKE1[10]

DDRA_ODT0[10] DDRA_ODT1[10]

3 3

DDRA_SCS0#[10] DDRA_SCS1#[10]

DDRA_SRAS#[10] DDRA_SCAS#[10] DDRA_SWE#[10]

MEM_MA_RST#[10] MEM_MA_EVENT#[10]

+MEM_VREF

+1.5V

15mil

Place them close to APU within 1"

DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15

DDRA_SBS0# DDRA_SBS1# DDRA_SBS2#

DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7#

DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1#

DDRA_CKE0 DDRA_CKE1

DDRA_ODT0 DDRA_ODT1

DDRA_SCS0# DDRA_SCS1#

DDRA_SRAS# DDRA_SCAS# DDRA_SWE#

MEM_MA_RST#

MEM_MA_EVENT#

1 2

R3 39.2_0402_1%R3 39.2_0402_1%

M_ZVDDIO

M21

M22

AA25

AD27 AC23 AD19 AC15

AE26 AD26

AB22 AA22 AB18 AA18 AA14 AA15

AA27

AA26

W24 W23

W20

W21

U20 R20 R21 P22 P21 N24 N23 N20 N21

U23

L24

L21 L20

U24 U21

L23

E14

J17 E21 F25

G14 H14 G18 H18

J21 H21 E27 E26

T21 T22 R23 R24

H28 H27

Y25

V22

V21

H25 T24

E

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1

MA_CKE0 MA_CKE1

MA_ODT0 MA_ODT1

MA_CS_L0 MA_CS_L1

MA_RAS_L MA_CAS_L MA_WE_L

MA_RESET_L MA_EVENT_L

M_VREF

M_ZVDDIO

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

B

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7

MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15

MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23

MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31

MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39

MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47

MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55

MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

E13 J13 H15 J15 H13 F13 F15 E15

H17 F17 E19 J19 G16 H16 H19 F19

H20 F21 J23 H23 G20 E20 G22 H22

G24 E25 G27 G26 F23 H24 E28 F27

AB28 AC27 AD25 AA24 AE28 AD28 AB26 AC25

Y23 AA23 Y21 AA20 AB24 AD24 AA21 AC21

AA19 AC19 AC17 AA17 AB20 Y19 AD18 AD17

AA16 Y15 AA13 AC13 Y17 AB16 AB14 Y13

DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7

DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15

DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23

DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31

DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39

DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47

DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55

DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

DDRA_SDQ[63..0] [10]

C

DDRB_SMA[15..0][11]

DDRB_SBS0#[11] DDRB_SBS1#[11] DDRB_SBS2#[11] DDRB_SDM[7..0][11]

DDRB_SDQS0[11] DDRB_SDQS0#[11] DDRB_SDQS1[11] DDRB_SDQS1#[11] DDRB_SDQS2[11] DDRB_SDQS2#[11] DDRB_SDQS3[11] DDRB_SDQS3#[11] DDRB_SDQS4[11] DDRB_SDQS4#[11] DDRB_SDQS5[11] DDRB_SDQS5#[11] DDRB_SDQS6[11] DDRB_SDQS6#[11] DDRB_SDQS7[11] DDRB_SDQS7#[11]

DDRB_CLK0[11] DDRB_CLK0#[11] DDRB_CLK1[11] DDRB_CLK1#[11]

DDRB_CKE0[11] DDRB_CKE1[11]

DDRB_ODT0[11] DDRB_ODT1[11]

DDRB_SCS0#[11] DDRB_SCS1#[11]

DDRB_SRAS#[11] DDRB_SCAS#[11] DDRB_SWE#[11]

MEM_MB_RST#[11] MEM_MB_EVENT#[11]

DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15

DDRB_SBS0# DDRB_SBS1# DDRB_SBS2#

DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7

DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7#

DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1#

DDRB_CKE0 DDRB_CKE1

DDRB_ODT0 DDRB_ODT1

DDRB_SCS0# DDRB_SCS1#

DDRB_SRAS# DDRB_SCAS# DDRB_SWE#

MEM_MB_RST# MEM_MB_EVENT#

D

J

PU1C

C

M

MORY CHANNEL B

E

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1

MB_CKE0 MB_CKE1

MB_ODT0 MB_ODT1

MB_CS_L0 MB_CS_L1

MB_RAS_L MB_CAS_L MB_WE_L

MB_RESET_L MB_EVENT_L

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

M28 M27 M24 M25

W26

AF25 AG22 AH18 AD14

AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14

W27

T27 P24 P25 N27 N26

L26 U26 L27 K27

K25 K24

U27 T28 K28

D14 A18 A22 C25

C15 B15 E18 D18 E22 D22 B26 A26

R26 R27 P27 P28

J26 J27

Y28

V25 Y27

V24 V27 V28

J25 T25

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7

MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15

MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23

MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31

MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39

MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47

MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55

MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

A14 B14 D16 E16 B13 C13 B16 A16

C17 B18 B20 A20 E17 B17 B19 C19

C21 B22 C23 A24 D20 B21 E23 B23

E24 B25 B27 D28 B24 D24 D26 C27

AG26 AH26 AF23 AG23 AG27 AF27 AH24 AE24

AE22 AH22 AE20 AH20 AD23 AD22 AD21 AD20

AF19 AE18 AE16 AH16 AG20 AG19 AF17 AD16

AG15 AD15 AG13 AD13 AG16 AF15 AE14 AF13

DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7

DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15

DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23

DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31

DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39

DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47

DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55

DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63

E

DDRB_SDQ[63..0] [11]

EVENT# pull high 0.75V reference voltage

+1.5V

4 4

1 2

R5 1K_0402_5%R5 1K_0402_5%

1 2

R6 1K_0402_5%R6 1K_0402_5%

MEM_MA_EVENT#

MEM_MB_EVENT# +MEM_VREF

A

R4

1K_0402_1%

R7

1K_0402_1%

+1.5V

1 2

B

1

C45

C45 1000P_0402_50V7K

1000P_0402_50V7K

2

15mil

2

C46

C46 .1U_0402_16V7K

.1U_0402_16V7K

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

FS1r2 DDRIII Memory I/F

LA-8127P

6 51Tuesday, March 12, 2013

E

1.0

A

Place near APU

1 2

5

2 .1U_0402_16V7K

C

P

0_TXP0_C[25]

D

P

0_TXN0_C[25]

D

L

_VGA_TXP0[13]

1 1

2 2

+1.5V

3 3

4 4

1 2

R49 1K_0402_5%R49 1K_0402_5%

1 2

R52 1K_0402_5%R52 1K_0402_5%

1 2

R32 1K_0402_5%R32 1K_0402_5%

1 2

R37 1K_0402_5%R37 1K_0402_5%

1 2

R39 1K_0402_5%R39 1K_0402_5%

R36 1K_0402_5%R36 1K_0402_5%

1 2

R33 1K_0402_5%@R33 1K_0402_5%@

1 2

R38 1K_0402_5%@R38 1K_0402_5%@

1 2

R40 1K_0402_5%@R40 1K_0402_5%@

1 2

R41 1K_0402_5%R41 1K_0402_5%

1 2

R43 1K_0402_5%R43 1K_0402_5%

1 2

R46 1K_0402_5%R46 1K_0402_5%

+1.5VS

1 2

R54 300_0402_5%R54 300_0402_5%

1 2

R57 300_0402_5%R57 300_0402_5%

+3VS

1 2

R60 10K_0402_5%R60 10K_0402_5%

1 2

R61 10K_0402_5%R61 10K_0402_5%

Aux signal are re-configured as I2C signals for DDC. APU AUX pin are 3.3V tolerant Default follow PAWGX setting for pull-high resistor value

M M

_VGA_TXN0[13]

L

M

_VGA_TXP1[13]

L

M

_VGA_TXN1[13]

L

ML_VGA_TXP2[13] ML_VGA_TXN2[13]

ML_VGA_TXP3[13] ML_VGA_TXN3[13]

HDMI_TX2P[27] HDMI_TX2N[27]

HDMI_TX1P[27] HDMI_TX1N[27]

HDMI_TX0P[27] HDMI_TX0N[27]

HDMI_CLKP[27] HDMI_CLKN[27]

Route as differential with VSS_SENSE

ALLOW_STOP

APU_DBREQ#

12

APU_TRST#

APU_RST#

APU_PWRGD

A

APU_TCK

APU_TMS

APU_TDI

APU_SVT

APU_SVC

APU_SVD

APU_SIC

APU_SID

ALERT_L

HDMI_CLK

HDMI_DATA

C

1 2

4

7 .1U_0402_16V7K

C

1 2

6

1 .1U_0402_16V7K

C

1 2

C

2 .1U_0402_16V7K

6

1 2

C

3 .1U_0402_16V7K

6

1 2

C

4 .1U_0402_16V7K

6

1 2

C65 .1U_0402_16V7KC65 .1U_0402_16V7K

1 2

C66 .1U_0402_16V7KC66 .1U_0402_16V7K

1 2

C67 .1U_0402_16V7KC67 .1U_0402_16V7K

1 2

C68 .1U_0402_16V7KC68 .1U_0402_16V7K

1 2

C50 .1U_0402_16V7KC50 .1U_0402_16V7K

1 2

C51 .1U_0402_16V7KC51 .1U_0402_16V7K

1 2

C55 .1U_0402_16V7KC55 .1U_0402_16V7K

1 2

C56 .1U_0402_16V7KC56 .1U_0402_16V7K

1 2

C57 .1U_0402_16V7KC57 .1U_0402_16V7K

1 2

C58 .1U_0402_16V7KC58 .1U_0402_16V7K

1 2

C59 .1U_0402_16V7KC59 .1U_0402_16V7K

1 2

C60 .1U_0402_16V7KC60 .1U_0402_16V7K

APU_CLK[12] APU_CLK#[12]

APU_DISP_CLK[12] APU_DISP_CLK#[12]

APU_SVC[45] APU_SVD[45]

APU_SVT[45]

T32T32

APU_RST#[12] APU_PWRGD[12,45]

APU_PROCHOT#[12]

APU_VDD_SEN_L[45]

APU_VDDNB_SEN[45]

APU_VDD_SEN_H[45]

T33T33

T23T23 T24T24 T25T25 T26T26 T27T27 T28T28 T29T29

APU_CLK APU_CLK#

APU_DISP_CLK APU_DISP_CLK#

APU_SIC APU_SID

APU_RST# APU_PWRGD

APU_PROCHOT# APU_THERMTRIP# ALERT_L

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

APU_VDD_SEN_L

APU_VDDNB_SEN

T20T20

APU_VDD_SEN_H

T21T21

P

0_TXP0

D

P

0_TXN0

D

1_TXP0

P

D

1_TXN0

P

D

1_TXP1

P

D

1_TXN1

P

DP1_TXP2 DP1_TXN2

DP1_TXP3 DP1_TXN3

DP2_TXP0 DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

B

N

ALOG/DISPLAY/MISC

A

P

0_TXP0

D D

0_TXN0

P

L

D

0_TXP1

P P

0_TXN1

D

0_TXP2

P

D

0_TXN2

P

D

0_TXP3

P

D

0_TXN3

P

1_TXP0

D D

1_TXN0

P

D

1_TXP1

P

D

1_TXN1

P

To FCH

DP1_TXP2 DP1_TXN2

DP1_TXP3 DP1_TXN3

DP2_TXP0 DP2_TXN0

DP2_TXP1

HDMI

DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

CLKIN_H CLKIN_L

DISP_CLKIN_H DISP_CLKIN_L

SVC SVD

SVT

SIC SID

RESET_L PWROK

PROCHOT_L THERMTRIP_L ALERT_L

TDI TDO TCK TMS TRST_L DBRDY DBREQ_L

VSS_SENSE VDDP_SENSE VDDNB_SENSE VDDIO_SENSE VDD_SENSE VDDR_SENSE

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

+3VS

APU_SIC

AE11 AD11

AB11 AA11

AG12 AH12

AF10 AB12

AC10 AE12 AF12

H10

F10 G10

L3 L2

K5 K4

K2 K1

J3 J2

H5 H4

H2 H1

G3 G2

F2 F1

L9 L8

L5 L6

K8 K7

J6 J5

B3 A3

C3

J10

F9 G9 H9

B4 C5

A4

A5 C4

B5

B

J

C

V

DS

DISPLAY PORT 0

DISPLAY PORT 2 DISPLAY PORT 1

CTRL SE R. CLK

JTAG

SENSE

31.6K_0402_1%

PU1D

P

0_AUXP

D D

0_AUXN

P

D

1_AUXP

P P

1_AUXN

D

2_AUXP

P

D

2_AUXN

P

D

3_AUXP

P

D

3_AUXN

P

4_AUXP

D D

4_AUXN

P

D

5_AUXP

P

D

5_AUXN

P

DP0_HPD DP1_HPD

DISPLAY PORT MISC.

DP2_HPD DP3_HPD DP4_HPD DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24

TEST

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

DMAACTIVE_L

RSVD1 RSVD2 RSVD3

RSVD

RSVD4

C69 0.1U_0402_16V4ZC69 0.1U_0402_16V4Z

1 2

R34

3 1

SGD

BSH111_SOT23-3

3 1

BSH111_SOT23-3

C

D1

P

0_AUXP

D

D2

P

0_AUXN

D

E1

M

_VGA_AUXP

L

E2

M

_VGA_AUXN

L

D5

H

MI_CLK

D

D6

H

MI_DATA

D

E5 E6

F5 F6

G5 G6

D3

LVDS_HPD

E3

ML_VGA_HPD

D7

HDMI_DET

E7 F7 G7

C6 B6 A6

DP_INT_PWM

C1

DP_AUX_ZVSS

AD12

TEST6

M18

TEST9

N18 F11 G11 H11 J11 F12

APU_TEST18

G12

APU_TEST19

J12

APU_TEST20

H12

APU_TEST24

AE10

TEST25_H

AD10

TEST25_L

L10

TEST28_H

M10

TEST28_L

P19

TEST30_H

R19

TEST30_L

K22

APU_TEST31

T19 N19 AA12

APU_TEST35

W10

FS1R2

AC12

ALLOW_STOP

P18

TEST4

R18

TEST5

Y10 AA10 Y12 K21

1 2

R35

30K_0402_1%

2

Q4

2

Q5

SGD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

1 2

5

3 .1U_0402_16V7K

C

1 2

4

8 .1U_0402_16V7K

C

1 2

C

4 .1U_0402_16V7K

5

1 2

C

9 .1U_0402_16V7K

4

1 2

R13 150_0402_1%R13 150_0402_1%

T1T1 T2T2 T3T3 T4T4 T5T5 T6T6

R14 1K_0402_5%R14 1K_0402_5% R15 1K_0402_5%R15 1K_0402_5% R16 1K_0402_5%R16 1K_0402_5% R17 1K_0402_5%R17 1K_0402_5% R20 510_0402_1%R20 510_0402_1% R23 510_0402_1%R23 510_0402_1%

T14T14 T15T15 T7T7 T8T8

R25 39.2_0402_1%R 25 39.2_0402_1%

R26 300_0402_5%R26 300_0402_5% R27 300_0402_5%@R27 300_0402_5%@ R28 10K_0402_5%R28 10K_0402_5%

T9T9 T10T10

EC_SMB_DAAPU_SID

1 2

0_0402_5%

EC_SMB_CK

1 2

R50

@R50

@

R59

@R59

@

0_0402_5%

R44 0_0402_5%@R44 0_0402_5%@

R47

@R47

@

R55 0_0402_5%@R55 0_0402_5%@

R58

@R58

@

C

P

0_AUXP_C [25]

D

P

0_AUXN_C [25]

D

M

_VGA_AUXP_C [13]

L

M

_VGA_AUXN_C [13]

L

H

MI_CLK [27]

D D

MI_DATA [27]

H

LVDS_HPD [25] ML_VGA_HPD [13] HDMI_DET [27]

DP_INT_PWM [9]

T30T30 T31T31

1 2 1 2 1 2 1 2 1 2 1 2

1 2

1 2 1 2 1 2

ALLOW_STOP [12]

SIT, NO.3

1 2

0_0402_5%

1 2

0_0402_5%

2012/11/22 2015/11/22

+1.2VS

+1.5V

+3VALW

CPU TSI interface level shift

BSH111, the Vgs is: min = 0.4V Max = 1.3V

EC_SMB_DA2 [18,25,31,32]

FCH_SID [14]

EC_SMB_CK2 [18,25,31,32]

FCH_SIC [14]

Compal Secret Data

To LVDS Translater

To FCH MainLink

To HDMI

Asserted as an input to force the processor into the HTC-active state

Deciphered Date

D

1K_0402_5%

APU_PROCHOT#

THERMTRIP shutdown Temperature: 125 degree

ALERT_L

To EC

To FCH

To EC

To FCH

D

To FCH

+

.5V

1

R12

1 2

R78 0_0402_5%@R78 0_0402_5%@

1K_0402_5%

APU_THERMTRIP#

+1.5V

12

B

2

E

3 1

MMBT3904_NL_SOT23-3

E

f

not used, pins are left unconnected (DG ref.)

I 20101111

M

_VGA_AUXP

L

R

9 1

_VGA_AUXN

L

0_AUXP

P

0_AUXN

P

R18

R18 10K_0402_5%

10K_0402_5%

Q2

C

9 1

R

8 1

R

9 1.8K_0402_5%

7

R

1 1.8K_0402_5%

8

LA-8127P

M

D

H

PROCHOT#_EC: default low/active high

_ APU_PROCHOT# : default high/ active low H_PROCHOT#: default high/ active low

Q7

13

2N7002K_SOT23-3

D

2

G

S

Indicates to the FCH that a thermal trip has occurred. Its assertion will cause the

+1.5V

FCH to transition the system to S5 immediately

R21

R29

R29 10K_0402_5%@

10K_0402_5%@

Q3

@

Q3

@

C

Title

Size Document Number Rev

Custom

Date: Sheet of

12

1 2

B

2

E

3 1

MMBT3904_NL_SOT23-3

1 2

R30 0_0402_5%@R30 0_0402_5%@

1 2

R31 0_0402_5%@R31 0_0402_5%@

Compal Electronics, Inc.

FS1r2 Display/MISC/HDT

E

12

.8K_0402_5%

12

.8K_0402_5%

12

H_PROCHOT#_EC [31,38]

H_PROCHOT# [38,45]

H_THERMTRIP# [14]

APU_ALERT#_FCH [13]

APU_ALERT#_EC [31]

7 51Tuesday, March 12, 2013

1.0

A

Power Name

VDD +APU_CORE

VDDNB +APU_CORE_NB

VDDIO +1.5V

VDDP / VDDR +1.2VS

VDDA

1 1

+2.5VS 0.5A

2 2

3 3

Consumption

5A / 3.5A

VDDR decoupling

180P_0402_50V8J

C1

03

04

1

2

60A

44A

3.2A

180P_0402_50V8J

C1

C1 05

05

1

2

+1.2VS

0.22U_0402_6.3V6K

C1

C1 06

06

+APU_CORE_NB

0.22U_0402_6.3V6K

1

2

+1.5V

+

PU_CORE

A

F8

D

D_1

V

H6

V

D_2

D

J1

D

D_3

V

J14

V

D_4

D

P6

V

D_5

D

P10

VDD_6

J16

VDD_7

J18

VDD_8

J9

VDD_9

K19

VDD_10

K3

VDD_11

K17

VDD_12

M3

VDD_13

K6

VDD_14

V10

VDD_15

V18

VDD_16

V3

VDD_17

F3

VDD_18

L18

VDD_19

V6

VDD_20

W1

VDD_21

T18

VDD_22

Y14

VDD_23

AA1

VDD_24

AB6

VDD_25

AC1

VDD_26

R1

VDD_27

P3

VDD_28

K10

VDD_29

H3

VDD_30

M19

VDD_31

C8

VDDNB_1

D10

VDDNB_2

B8

VDDNB_3

B12

VDDNB_4

C9

VDDNB_5

A9

VDDNB_6

A10

VDDNB_7

A8

VDDNB_8

A11

VDDNB_9

E10

VDDNB_10

E11

VDDNB_11

C10

VDDNB_12

H26

VDDIO_1

K20

VDDIO_2

J28

VDDIO_3

K23

VDDIO_4

K26

VDDIO_5

L22

VDDIO_6

L25

VDDIO_7

L28

VDDIO_8

M20

VDDIO_9

M23

VDDIO_10

M26

VDDIO_11

N22

VDDIO_12

N25

VDDIO_13

N28

VDDIO_14

P20

VDDIO_15

P23

VDDIO_16

P26

VDDIO_17

AA28

VDDIO_18

AH6

VDDP_1

AH5

VDDP_2

AH4

VDDP_3

AH3

VDDP_4

AH7

VDDP_5

AB10

VDDA

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

J

PU1E

C

V V V V V VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62

VDDNB_13 VDDNB_14 VDDNB_15 VDDNB_16 VDDNB_17 VDDNB_18 VDDNB_19 VDDNB_20 VDDNB_21 VDDNB_22 VDDNB_23

VDDNB_CAP_1 VDDNB_CAP_2

VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36

VDDR_1 VDDR_2 VDDR_3 VDDR_4

B

+

PU_CORE

A

0.01U_0402_16V7K

0.22U_0402_6.3V6K

C73

+APU_CORE_NB

180P_0402_50V8J

C109

1

2

1

2

0.22U_0402_6.3V6K

C77

1

2

+1.5V

22U_0603_6.3V6M

C82

1

@

2

+1.5V

0.22U_0402_6.3V6K

C99

1

2

1000P_0402_50V7K

C110

1

2

@

+

PU_CORE

A

R11

D

D_32

T10

D_33

D

H8

D

D_34

G1

D_35

D

U11

D_36

D

W11 W13 W15 W17 W19 AB3 AD3 AD6 AE1 L1 Y6 M6 N11 N1 T3 T6 U19 U1 Y16 Y18 Y3 D4 F4 AF6 AF3 L11

C11

+APU_CORE_NB

C12 D9 D8 D12 D11 B11 A12 B10 E12 B9

K13

+APU_CORE_NB_CAP

K12

T23

+1.5V

T26 U22 U25 U28 Y26 T20 R28 R25 R22 V20 V23 V26 W22 W25 W28 Y24 G28

AG10 AH8 AH9 AH10

180P_0402_50V8J

C108

C107

1

2

0.01U_0402_16V7K

0.22U_0402_6.3V6K

C70

C74

1

2

0.22U_0402_6.3V6K

180P_0402_50V8J

C78

C79

1

2

22U_0603_6.3V6M

C84

C83

1

2

Across VDDIO and VSS split

0.22U_0402_6.3V6K

180P_0402_50V8J

C100

C101

1

2

1000P_0402_50V7K

C111

C112

1

2

@

C

0.01U_0402_16V7K

C75

C71

1

2

180P_0402_50V8J

C81

C80

1

2

22U_0603_6.3V6M

C86

C85

1

2

180P_0402_50V8J

C102

1

2

VDDR decoupling

1000P_0402_50V7K

0.22U_0402_6.3V6K

C113

1

2

D

180P_0402_50V8J

0.01U_0402_16V7K

180P_0402_50V8J

22U_0603_6.3V6M

C114

1

2

180P_0402_50V8J

C72

C76

1

2

0.22U_0402_6.3V6K

4.7U_0603_6.3V6K

C88

+1.2VS

4.7U_0603_6.3V6K

C89

C90

1

2

C90

1

2

4.7U_0603_6.3V6K

C87

1

2

0.22U_0402_6.3V6K

C91

1

2

0.22U_0402_6.3V6K

C92

1

2

+APU_CORE_NB_CAP

22U_0603_6.3V6M

C216

1

@

2

0.22U_0402_6.3V6K

C93

C94

1

2

22U_0603_6.3V6M

C215

C214

1

2

0.22U_0402_6.3V6K

C96

C95

1

2

180P_0402_50V8J

C217

1

2

180P_0402_50V8J

330U_D2_2.5VY_R9M

180P_0402_50V8J

C136

C97

1

2

330U_D2_2.5VY_R9M

C98

1

+

2

Demo Board Capacitor

APU_CORE 22uF x 10

0.22uF x 2

0.01uF x 3 180pF x 2

CORE_NB 22uF x 2 10uF x 1

0.22uF x 2 180pF x 3

CORE_NB_CAP 22uF x 2 180pF x 1

E

C

PU1F

J

J20

V

S_1

S

L4

S

S_2

V

R7

V

S_3

S

W18

V

S_4

S

A15

V

S_5

S

AB17

V

S_6

S

AC22

V

S_7

S

AE21

V

S_8

S

AF24

S

S_9

V

AH23

S

S_10

V

AH25

V

S_11

S

B7

S

S_12

V

C14

V

S_13

S

C16

V

S_14

S

C2

VSS_15

C20

VSS_16

C22

VSS_17

C24

VSS_18

C26

VSS_19

C28

VSS_20

D13

VSS_21

D15

VSS_22

D17

VSS_23

D19

VSS_24

D23

VSS_25

D25

VSS_26

D27

VSS_27

E4

VSS_28

E9

VSS_29

F14

VSS_30

F16

VSS_31

F18

VSS_32

F20

VSS_33

F22

VSS_34

F26

VSS_35

F28

VSS_36

G13

VSS_37

G15

VSS_38

G17

VSS_39

G19

VSS_40

G21

VSS_41

G23

VSS_42

G25

VSS_43

G4

VSS_44

J22

VSS_45

J24

VSS_46

J4

VSS_47

J7

VSS_48

K11

VSS_49

K14

VSS_50

K9

VSS_51

AC11

VSS_52

L19

VSS_53

L7

VSS_54

M11

VSS_55

AF11

VSS_56

V19

VSS_57

V9

VSS_58

W16

VSS_59

W4

VSS_60

W7

VSS_61

Y11

VSS_62

Y20

VSS_63

Y22

VSS_64

Y9

VSS_65

A17

VSS_66

A13

VSS_67

K16

VSS_68

F24

VSS_69

G8

VSS_70

H7

VSS_71

J8

VSS_72

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

VDDIO_SUS (CPU side) 22uF x 4

4.7uF x 4

0.22uF x 6 +2(split) 180pF x 1 + 2(split)

V

S_73

S S

S_74

V V

S_75

S

V

S_76

S

V

S_77

S

V

S_78

S

V

S_79

S

V

S_80

S S

S_81

V

S

S_82

V V

S_83

S S

S_84

V V

S_85

S

V

S_86

S VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143

A19 A21 A23 A25 A7 AA4 AA7 AB13 AB15 AB19 AB21 AB23 AB25 AB27 AB9 AC14 AC16 AC18 AC20 AC24 AC26 AC28 AC4 AC7 AD9 AE13 AE15 AE17 M9 N10 N4 N7 R10 R4 T11 T9 U10 U18 U4 U7 V11 AE19 AE23 AE25 AE27 AE4 AE7 AF14 AF16 AF18 AF20 AF22 AF26 AF28 AF9 AG4 AG7 AH13 AH15 AH17 AH19 AH21 P9 C18 D21 W14 P11 C7 E8 K18 W12

4 4

+2.5VS

L1

L1 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

12

3300P_0402_50V7-K

0.22U_0402_6.3V6K

C1

15

16

1

2

A

40mil

+VDDA

4.7U_0402_6.3V6M

C117

1

2

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

VDDP

0.22uF x 2 180pF x 2

D

VDDR

0.22uF x 2 1nF x 4 180pF x 2

Title

Size Document Number Rev

Custom

Date: Sheet of

VDDA

4.7uF x 1

0.22uF x 1

3.3nF x 1

Compal Electronics, Inc.

FS1r2 PWR/GND

VDDIO_SUS (DIMM x2) 100uF x 2

0.1uF x 12

LA-8127P

E

1.0

8 51Tuesday, March 12, 2013

1.0

5

4

3

2

1

D D

+

S

3V

Panel PWM

12

R62

R62 47K_0402_5%

47K_0402_5%

C C

C

Q8

DP_INT_PWM[7]

12

B B

1 2

R66 2.2K_0402_5%R66 2.2K_0402_5%

R67

4.7K_0402_5%

Q8

C

2

B

E

3 1

2

MMBT3904_NL_SOT23-3

12

R63

4.7K_0402_5%

13

D

Q6

G

2N7002K_SOT23-3

S

APU_INVT_PWM [25]

A A

Security Classification

2012/11/22 2015/11/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

4

Compal Electronics, Inc.

Title

FS1r2 Signal Level Shifter

Size Document Number Rev

Custom

Date: Sheet of

3

Date: Sheet of

Compal Electronics, Inc.

LA-8127P

2

9 51Tuesday, March 12, 2013

1

1.0

A

B

C

D

E

V

REF_DQ

+

D D

D

D D

D

C2011

0.1U_0402_16V4Z

D

D D

D DDRA_SDQ11

DDRA_SDQ16 DDRA_SDQ17

DDRA_SDQS2# DDRA_SDQS2

DDRA_SDQ18 DDRA_SDQ19

DDRA_SDQ24 DDRA_SDQ25

DDRA_SDM3

DDRA_SDQ26 DDRA_SDQ27

DDRA_CKE0

DDRA_SBS2#

DDRA_SMA12 DDRA_SMA9

DDRA_SMA8 DDRA_SMA5

DDRA_SMA3 DDRA_SMA1

DDRA_CLK0 DDRA_CLK0#

DDRA_SMA10 DDRA_SBS0#

DDRA_SWE# DDRA_SCAS#

DDRA_SMA13 DDRA_SCS1#

DDRA_SDQ32 DDRA_SDQ33

DDRA_SDQS4# DDRA_SDQS4

DDRA_SDQ34 DDRA_SDQ35

DDRA_SDQ40 DDRA_SDQ41

DDRA_SDM5

DDRA_SDQ42 DDRA_SDQ43

DDRA_SDQ48 DDRA_SDQ49

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ56 DDRA_SDQ57

DDRA_SDM7

DDRA_SDQ58 DDRA_SDQ59

R2005 10K_0402_5%

1 1

2 2

3 3

2.2U_0603_6.3V6K

+3VS

C2010

D

RA_SDQS1#[6]

D D

RA_SDQS1[6]

D

DDRA_SDQS2#[6] DDRA_SDQS2[6]

DDRA_SBS2#[6]

DDRA_CLK0[6] DDRA_CLK0#[6]

DDRA_SBS0#[6]

DDRA_SWE#[6]

DDRA_SCAS#[ 6]

DDRA_SCS1#[6]

DDRA_SDQS4#[6] DDRA_SDQS4[6]

DDRA_SDQS6#[6] DDRA_SDQS6[6]

1

2

RA_SDQ0

D

RA_SDQ1

D

RA_SDM0

D

RA_SDQ2

D

RA_SDQ3

D

RA_SDQ8 RA_SDQ9

D

RA_SDQS1# RA_SDQS1

D

RA_SDQ10

D

1 2

12

1

+

R2000

R2000 10K_0402_5%

10K_0402_5%

.5V

D

IMM2

J

1

V

EF_DQ

R

3

V

S2

S

5

D

0

Q

7

D

1

Q

9

V

S4

S

11

M

0

D

13

V

S5

S

15

D

2

Q

17

D

3

Q

19

V

S7

S

21

D

8

Q

23

Q

9

D

25

V

S9

S

27

D

S#1

Q

29

Q

S1

D

31

V

S11

S

33

Q

10

D

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17 VSS1849DQ22

51

DQ18 DQ1953VSS19 VSS2055DQ28

57

DQ24 DQ2559VSS21 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

FOX_AS0A626-U2RN-7F

CONN@

D

E

R

VDD12

VDD14

VDD16

VDD18

VREF_CA

DQS#5

DQS#7

EVENT#

V

V Q D V

V D D

V

S

SET#

V

S D DQ15

DQ20 DQ21

DQ23

DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS7

VSS50

DQ62 DQ63

VSS52

VTT2

1

.5V

+

2

S1

S

4

D

RA_SDQ4

D

4

Q

D

5

Q S3

S

S#0

Q

S0 S6

S D

6

Q

D

7

Q S8

S

12

Q Q

13

S10

D

1

M

S12

Q

14

DM2

A15 A14

A7

A6 A4

A2 A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

G2

D

6

D

RA_SDQ5

D

8 10

D

RA_SDQS0#

D

12

D

RA_SDQS0

D

14 16

D

RA_SDQ6

D

18

D

RA_SDQ7

D

20 22

D

RA_SDQ12

D

24

D

RA_SDQ13

D

26 28

D

RA_SDM1

D

30

M

M_MA_RST#

E

32 34

D

RA_SDQ14

D

36

DDRA_SDQ15

38 40

DDRA_SDQ20

42

DDRA_SDQ21

44 46

DDRA_SDM2

48 50

DDRA_SDQ22

52

DDRA_SDQ23

54 56

DDRA_SDQ28

58

DDRA_SDQ29

60 62

DDRA_SDQS3#

64

DDRA_SDQS3

66 68

DDRA_SDQ30

70

DDRA_SDQ31

72

74

DDRA_CKE1

76 78

DDRA_SMA15

80

DDRA_SMA14

82 84

DDRA_SMA11

86

DDRA_SMA7

88 90

DDRA_SMA6

92

DDRA_SMA4

94 96

DDRA_SMA2

98

DDRA_SMA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDRA_SBS1#

110

DDRA_SRAS#

112 114

DDRA_SCS0#

116

DDRA_ODT0

118 120

DDRA_ODT1

122 124 126 128 130

DDRA_SDQ36

132

DDRA_SDQ37

134 136

DDRA_SDM4

138 140

DDRA_SDQ38

142

DDRA_SDQ39

144 146

DDRA_SDQ44

148

DDRA_SDQ45

150 152

DDRA_SDQS5#

154

DDRA_SDQS5

156 158

DDRA_SDQ46

160

DDRA_SDQ47

162 164

DDRA_SDQ52

166

DDRA_SDQ53

168 170

DDRA_SDM6

172 174

DDRA_SDQ54

176

DDRA_SDQ55

178 180

DDRA_SDQ60

182

DDRA_SDQ61

184 186

DDRA_SDQS7#

188

DDRA_SDQS7

190 192

DDRA_SDQ62

194

DDRA_SDQ63

196 198

MEM_MA_EVENT#

200 202 204

206

+0.75VS

D

RA_SDQS0# [6]

D D

RA_SDQS0 [6]

D

E

M_MA_RST# [6]

M

DDRA_SDQS3# [6] DDRA_SDQS3 [6]

DDRA_CKE1 [ 6]DDRA_CKE0[6]

DDRA_CLK1 [ 6] DDRA_CLK1# [6]

DDRA_SBS1# [6] DDRA_SRAS# [6]

DDRA_SCS0# [6] DDRA_ODT0 [6]

DDRA_ODT1 [6]

+VREF_CA

DDRA_SDQS5# [6] DDRA_SDQS5 [6]

DDRA_SDQS7# [6] DDRA_SDQS7 [6]

MEM_MA_EVENT# [ 6]

FCH_SDATA0 [11,14,31,33] FCH_SCLK0 [11,14,31,33]

D

RA_SDQ[0..63]

D

RA_SDM[0..7]

D

RA_SMA[0..15]

D

+1.5V

2

1

0.1U_0402_16V4Z

+VREF_DQ

15mil

0.1U_0402_16V4Z

C2001

0.1U_0402_16V4Z

2

1

C2007

2

D

RA_SDQ[0..63] [6]

D

RA_SDM[0..7] [6]

D

RA_SMA[0..15] [6]

D

C2002

0.1U_0402_16V4Z

+VREF_DQ

1000P_0402_50V7K

2

1

C2008

2

0.1U_0402_16V4Z

C2003

+1.5V

R2001

R2001 1K_0402_1%

1K_0402_1%

1 2

R2003

R2003 1K_0402_1%

1K_0402_1%

1 2

2

C2004

1

0.1U_0402_16V4Z

Place near DIMM1

0.1U_0402_16V4Z

2

C2006

C2005

1

+VREF_CA

+1.5V

1

+

C2025

C2025 330U_D2_2V_Y

330U_D2_2V_Y

2

15mil

+1.5V

R2002

R2002 1K_0402_1%

1K_0402_1%

+VREF_CA

1

C2000

2

0.1U_0402_16V4Z

1 2

1

C2009

R2004

R2004 1K_0402_1%

1K_0402_1%

2

1 2

1000P_0402_50V7K

Reverse H:5.2mm

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

DDRIII SO-DIMM 1

LA-8127P

E

10 51Tuesday, March 12, 2013

1.0

A

+

.5V

RB_SDQ0

D D

RB_SDQ1

D

RB_SDM0

RB_SDQ2

D D

RB_SDQ3

1 2

12

1

R2007

10K_0402_5%

J

IMM1

D

1

V

EF_DQ

R

3

V

S2

S

5

D

0

Q

7

D

1

Q

9

S

S4

V

11

D

0

M

13

V

S5

S

15

Q

2

D

17

D

3

Q

19

S

S7

V

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17 VSS1849DQ22

51

DQ18 DQ1953VSS19 VSS2055DQ28

57

DQ24 DQ2559VSS21 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3 A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

9

5

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

05

2

G1

FOX_AS0A626-UARN-7F

FOX_AS0A626-UARN-7F CONN@

CONN@

V

D

D V Q

D

V

D

D V

DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ23

DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

S

S S#0 Q S

S

A15 A14

CK1

BA1

S0#

NC2

SDA SCL

+

REF_DQ

V

D

+3VS

D

D D

DDRB_SDQ8 DDRB_SDQ9

DDRB_SDQS1# DDRB_SDQS1

DDRB_SDQ10 DDRB_SDQ11

DDRB_SDQ16 DDRB_SDQ17

DDRB_SDQS2# DDRB_SDQS2

DDRB_SDQ18 DDRB_SDQ19

DDRB_SDQ24 DDRB_SDQ25

DDRB_SDM3

DDRB_SDQ26 DDRB_SDQ27

DDRB_CKE0

DDRB_SBS2#

DDRB_SMA12 DDRB_SMA9

DDRB_SMA8 DDRB_SMA5

DDRB_SMA3 DDRB_SMA1

DDRB_CLK0 DDRB_CLK0#

DDRB_SMA10 DDRB_SBS0#

DDRB_SWE# DDRB_SCAS#

DDRB_SMA13 DDRB_SCS1#

DDRB_SDQ32 DDRB_SDQ33

DDRB_SDQS4# DDRB_SDQS4

DDRB_SDQ34 DDRB_SDQ35

DDRB_SDQ40 DDRB_SDQ41

DDRB_SDM5

DDRB_SDQ42 DDRB_SDQ43

DDRB_SDQ48 DDRB_SDQ49

DDRB_SDQS6# DDRB_SDQS6

DDRB_SDQ50 DDRB_SDQ51

DDRB_SDQ56 DDRB_SDQ57

DDRB_SDM7

DDRB_SDQ58 DDRB_SDQ59

R2006 10K_0402_5%R2006 10K_0402_5%

1 1

DDRB_SDQS1#[6] DDRB_SDQS1[6] MEM_MB_RST# [6]

DDRB_SDQS2#[6] DDRB_SDQS2[6]

2 2

3 3

DDRB_CKE0[6]

DDRB_SBS2#[6]

DDRB_CLK0[6] DDRB_CLK0#[6]

DDRB_SBS0#[6]

DDRB_SWE#[6]

DDRB_SCAS#[ 6]

DDRB_SCS1#[6]

DDRB_SDQS4#[6] DDRB_SDQS4[6]

DDRB_SDQS6#[6] DDRB_SDQS6[6]

B

+

.5V

1

2

S1

4

D

RB_SDQ4

D

4

Q

6

D

RB_SDQ5

D

5

Q

8

S3

10

D

RB_SDQS0#

D

12

D

RB_SDQS0

S0 S6 Q Q S8

A7

A6 A4

A2 A0

G2

D

14 16

D

RB_SDQ6

D

6

18

D

RB_SDQ7

D

7

20 22

DDRB_SDQ12

24

DDRB_SDQ13

26 28

DDRB_SDM1

30

MEM_MB_RST#

32 34

DDRB_SDQ14

36

DDRB_SDQ15

38 40

DDRB_SDQ20

42

DDRB_SDQ21

44 46

DDRB_SDM2

48 50

DDRB_SDQ22

52

DDRB_SDQ23

54 56

DDRB_SDQ28

58

DDRB_SDQ29

60 62

DDRB_SDQS3#

64

DDRB_SDQS3

66 68

DDRB_SDQ30

70

DDRB_SDQ31

72

74

DDRB_CKE1

76 78

DDRB_SMA15

80

DDRB_SMA14

82 84

DDRB_SMA11

86

DDRB_SMA7

88 90

DDRB_SMA6

92

DDRB_SMA4

94 9

6

DDRB_SMA2

98

DDRB_SMA0

100 102

DDRB_CLK1

104

DDRB_CLK1#

106 108

DDRB_SBS1#

110

DDRB_SRAS#

112 114

DDRB_SCS0#

116

DDRB_ODT0

118 120

DDRB_ODT1

122 124 126 128 130

DDRB_SDQ36

132

DDRB_SDQ37

134 136

DDRB_SDM4

138 140

DDRB_SDQ38

142

DDRB_SDQ39

144 146

DDRB_SDQ44

148

DDRB_SDQ45

150 152

DDRB_SDQS5#

154

DDRB_SDQS5

156 158

DDRB_SDQ46

160

DDRB_SDQ47

162 164

DDRB_SDQ52

166

DDRB_SDQ53

168 170

DDRB_SDM6

172 174

DDRB_SDQ54

176

DDRB_SDQ55

178 180

DDRB_SDQ60

182

DDRB_SDQ61

184 186

DDRB_SDQS7#

188

DDRB_SDQS7

190 192

DDRB_SDQ62

194

DDRB_SDQ63

196 198

MEM_MB_EVENT#

200 202 204

06

2

+0.75VS

D

RB_SDQS0# [6]

D

RB_SDQS0 [6]

D

DDRB_SDQS3# [6] DDRB_SDQS3 [6]

DDRB_CKE1 [ 6]

DDRB_CLK1 [6] DDRB_CLK1# [ 6]

DDRB_SBS1# [6] DDRB_SRAS# [6]

DDRB_SCS0# [6] DDRB_ODT0 [6]

DDRB_ODT1 [6]

+VREF_CA

DDRB_SDQS5# [6] DDRB_SDQS5 [6]

DDRB_SDQS7# [6] DDRB_SDQS7 [6]

MEM_MB_EVENT# [ 6]

FCH_SDATA0 [10,14,31,33] FCH_SCLK0 [10,14,31,33]

D

RB_SDQ[0..63]

D

RB_SDM[0..7]

D

RB_SMA[0..15]

D

C

D

RB_SDQ[0..63] [6]

D

RB_SDM[0..7] [6]

D

RB_SMA[0..15] [ 6]

D

V

REF_DQ

+

15mil

V

REF_DQ

+

1000P_0402_50V7K

0.1U_0402_16V4Z

C2022

0.1U_0402_16V4Z

+1.5V

2

1

C2012

1

2

0.1U_0402_16V4Z

C2016

+0.75VS

2

1

C2013

1

2

C2017

1

2

C2018

1

0.1U_0402_16V4Z

C2023

4.7U_0603_6.3V6K

D

V

+

0.1U_0402_16V4Z

2

C2019

1

REF_CA

15mil

V

REF_CA

+

0.1U_0402_16V4Z

C2014

1

2

Place near DIMM2

2

1

0.1U_0402_16V4Z

8/25

1000P_0402_50V7K

1

C2015

2

0.1U_0402_16V4Z

C2020

+1.5V

2

1

+

C2024

C2024 330U_D2_2V_Y

330U_D2_2V_Y

@

2

C2021

E

4 4

A

Reverse H:9.2mm

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

DDRIII SO-DIMM 2

LA-8127P

E

11 51Tuesday, March 12, 2013

1.0

A

150P_0402_50V8J

R90/ C146 close to FCH

1 1

1 2

C129

22P_0402_50V8J

20M_0402_5%

C130

22P_0402_50V8J

2 2

R75

1 2

10P_0402_50V8J

1 2

C131

1M_0402_5%

C134

1 2

10P_0402_50V8J

12

Close to HUDSON-M2/3

X1

X1 2

2

5MHZ_10PF_X3G025000DA1H-X

1

R88

1

GND

2

150P_0402_50V8J

32K_X1

Y1

32.768KHZ_12.5PF_CM31532768DZFT

32K_X2

25M_X1

3

GND

4

25M_X2

WLAN

3 3

LAN

Card Reader

For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)

APU_PCIE_RST #: Reset PCIE device on APU

M

C74VHC1G08DFT2G_SC70-5

4 4

APU_PCIE_RST#_C

R89/ C135 close to FCH

R89

1 2

33_0402_5%

C74VHC1G08DFT2G_SC70-5

1

35

R90

C1

@

2

1 2

150P_0402_50V8J

A

+3V_FCH

5

2

P

B

1

A

G

3

8.2K_0402_5%

R92

@R92

@

1 2

0_0402_5%

C

1

1 2

U

M

U

M M

U U

M M

U U

M M

U

M

U

M

U

M

U

M UMI_TXN1[5] UMI_TXP2[5] UMI_TXN2[5] UMI_TXP3[5] UMI_TXN3[5]

+VDDAN_11_PCIE

CLK_PCIE_VGA[17] CLK_PCIE_VGA#[17]

CLK_PCIE_WLAN#[33]

CLK_PCIE_LAN[35] CLK_PCIE_LAN#[35]

CLK_PCIE_CARD[35] CLK_PCIE_CARD#[35]

CLK_LAN_25M[35]

C133

1 2

0.1U_0402_16V4Z

4

Y

U3

25

I_RXP0[5] I_RXN0[5] I_RXP1[5] I_RXN1[5] I_RXP2[5] I_RXN2[5] I_RXP3[5] I_RXN3[5]

I_TXP0[5] I_TXN0[5] I_TXP1[5]

12

B

P

T_RST#

L

1 2

C

26 .1U_0402_16V7K

1

1 2

C

18 .1U_0402_16V7K

1

1 2

C

19 .1U_0402_16V7K

1

1 2

C

20 .1U_0402_16V7K

1

1 2

C

27 .1U_0402_16V7K

1

1 2

C

21 .1U_0402_16V7K

1

1 2

1

28 .1U_0402_16V7K

C

1 2

1

22 .1U_0402_16V7K

C

+1.1VS_CKVDD

1 2

R76 0_0402_5%@R76 0_0402_5%@

1 2

R77 0_0402_5%@R77 0_0402_5%@

R150 0_0402_5%@R 150 0_0402_5%@ R142 0_0402_5%@R 142 0_0402_5%@

R80 33_0402_5%R80 33_0402_5% R82 33_0402_5%R82 33_0402_5%

R83 33_0402_5%R83 33_0402_5% R84 33_0402_5%R84 33_0402_5%

R86 22_0402_5%@R86 22_0402_5%@

APU_PCIE_RST# [17,33,35]

R91

R91 0_0402_5%

0_0402_5%

@

PLT_RST# [31,35]

B

P

U_PCIE_RST#_C

1 2

R

7

1 2

R71 590_0402_1%R71 590_0402_1%

1 2

R73 2K_0402_1%R73 2K_0402_1%

1 2 1 2

1 2

A

2 33_0402_5%

R74

1 2

2K_0402_1%

APU_DISP_CLK[7] APU_DISP_CLK#[7]

APU_CLK[7] APU_CLK#[7]

CLK_PCIE_VGA_R CLK_PCIE_VGA#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

CLK_PCIE_CARD_R CLK_PCIE_CARD#_R

A

RST#

_

U

I_RXP0_C

M

U

I_RXN0_C

M

U

I_RXP1_C

M

U

I_RXN1_C

M

U

I_RXP2_C

M M

I_RXN2_C

U U

I_RXP3_C

M

U

I_RXN3_C

M

PCIE_CALRP PCIE_CALRN

CLK_CALRN

CLK_LAN_25M_R

25M_X1

25M_X2

S

U

AE2 AD5

AE30 AE32 AD33 AD31 AD28 AD29 AC30 AC32

AB33 AB31 AB28 AB29

Y33 Y31 Y28 Y29

AF29 AF31

V33

V31 W30 W32

AB26 AB27 AA24 AA23

AA27 AA26

W27

V27

V26 W26 W24 W23

F27

G30

G28

R26

T26

H33

H31

T24 T23

J30

K29

H27

H28

J27

K26

F33 F31

E33

E31

M23 M24

M27 M26

N25

N26

R23

R24

N27

R27

J26

C31

C33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

V/FVT, NO.12

D

2

A

C

IE_RST#

P A

RST#

_

U

I_TX0P

M

U

I_TX0N

M

U

I_TX1P

M

U

I_TX1N

M

U

I_TX2P

M

U

I_TX2N

M M

I_TX3P

U

M

I_TX3N

U

M

I_RX0P

U U

I_RX0N

M

U

I_RX1P

M UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N

PCIE_CALRP PCIE_CALRN

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N

GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N

CLK_CALRN

PCIE_RCLKP PCIE_RCLKN

DISP_CLKP DISP_CLKN

DISP2_CLKP DISP2_CLKN

APU_CLKP APU_CLKN

SLT_GFX_CLKP SLT_GFX_CLKN

GPP_CLK0P GPP_CLK0N

GPP_CLK1P GPP_CLK1N

GPP_CLK2P GPP_CLK2N

GPP_CLK3P GPP_CLK3N

GPP_CLK4P GPP_CLK4N

GPP_CLK5P GPP_CLK5N

GPP_CLK6P GPP_CLK6N

GPP_CLK7P GPP_CLK7N

GPP_CLK8P GPP_CLK8N

14M_25M_48M_OSC

25M_X1

25M_X2

218-0844000 A0 BOLTON-M3

PCI EXPRESS INTERFACES

CLOCK GENERATOR

C

UDSON-2

H

P

ICLK1/GPO36

C C

ICLK2/GPO37

P P

ICLK3/GPO38

PCI CLKS

PCI INTERFACE

LPCAPUS5 PLUS

2012/11/22 2015/11/22

C

P

ICLK4/14M_OSC/GPO39

C

AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

REQ1#/GPIO40 REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT1#/GPO44

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

INTE#/GPIO32

INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LDRQ1#/CLK_REQ6#/GPIO49

SERIRQ/GPIO48

DMA_ACTIVE#

S5_CORE_EN

INTRUDER_ALERT#

VDDBT_RTC_G

Compal Secret Data

C

ICLK0

P

IRST#

C

D

0/GPIO0

A

D

1/GPIO1

A A

2/GPIO2

D D

3/GPIO3

A A

4/GPIO4

D

A

5/GPIO5

D AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP# PERR# SERR#

REQ0#

GNT0#

CLKRUN#

LOCK#

LPCCLK0

LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

RTCCLK

32K_X1

32K_X2

Deciphered Date

AF3 AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

B25

D25 D27 C28 A26 A29 A31 B27 AE27 AE19

G25 E28 E26 G26 F26

H7 F1 F3 E6

G2

G4

D

1 2

R209 0_0402_5%@R 209 0_0402_5%@

1 2

R208 0_0402_5%@R 208 0_0402_5%@

LPCCLK0

APU_PROCHOT#_R

32K_X1

32K_X2

D

P

I_CLK1 [16]

C

P

I_CLK3 [16]

C

P

I_CLK4 [16]

C

PCI_AD23 [16] PCI_AD24 [16] PCI_AD25 [16] PCI_AD26 [16] PCI_AD27 [16]

T11T11

T22T22

1 2

R110 0_0402_5%@R 110 0_0402_5%@

1 2

R215 33_0402_5%R215 33_0402_5%

LPC_CLK1 [16] LPC_AD0 [31,33,35] LPC_AD1 [31,33,35] LPC_AD2 [31,33,35] LPC_AD3 [31,33,35] LPC_FRAME# [31,33,35]

SERIRQ [31]

1 2

R85 0_0402_5%@R85 0_0402_5%@

APU_PWRGD [45,7]

APU_RST# [7]

RTC_CLK [16,31]

1U_0402_6.3V6K

PXS_RST# [14,17] PXS_PWREN [14,19,43,44]

W=20mils

1

C132

2

Date: Sheet of

E

CLK_PCI_DB [33,35]CLK_PCIE_WLAN[33]

CLK_PCI_EC [16,31]

ALLOW_STOP [7] APU_PROCHOT# [7]

1 2

R87 510_0402_5%R87 510_0402_5%

+RTCBATT

12

JCMOS1

@JCMOS1

@

SHORT PADS

for Clear CMOS

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RTC

LA-8127P

12 51Tuesday, March 12, 2013

E

1.0

A

B

C

D

E

4MB SPI ROM

P

I_CLK_FCH

@

S

R

9

33_0402_5%

@

22P_0402_50V8J

@

SPI_CLK_FCH_R

+3V_FCH

12

3

1

38

C

& Non-share ROM.

+

VALW

2

B

U

1 1

HDD

ODD

2 2

3 3

4 4

S

TA_FTX_DRX_P0[30]

A

S

TA_FTX_DRX_N0[30]

A

SATA_FRX_C_DTX_N0[30] SATA_FRX_C_DTX_P0[30]

SATA_FTX_DRX_P1[30] SATA_FTX_DRX_N1[30]

SATA_FRX_C_DTX_N1[30] SATA_FRX_C_DTX_P1[30]

+AVDD_SATA

1 2

C

39 0.01U_0402_16V7K

1

1 2

C

40 0.01U_0402_16V7K

1

1 2

C143 0.01U_0402_16V7KC143 0.01U_0402_16V7K

1 2

C142 0.01U_0402_16V7KC142 0.01U_0402_16V7K

+3VS

BT_ON#[32]

WLBT_OFF#[33]

WL_OFF#[33]

ODD_EN[30]

S

TA_FTX_C_DRX_P0

A

S

TA_FTX_C_DRX_N0

A

SATA_FTX_C_DRX_P1 SATA_FTX_C_DRX_N1

12

SATA_CALRP

R1071K_0402_1% R1 071K_0402_1%

12

SATA_CALRN

R108931_0402_1% R108931_0402_1%

12

R21410K_0402_5% R21410K _0402_5%

BT_ON#

WLBT_OFF# WL_OFF#

ODD_EN

1 2

R119 10K_0402_5%R119 10K_0402_5%

1 2

R122 10K_0402_5%R122 10K_0402_5%

1 2

R123 10K_0402_5%R123 10K_0402_5%

U

AK19

A

TA_TX0P

S

AM19

S

TA_TX0N

A

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

K6

TEMPIN0/GPIO171

K5

TEMPIN1/GPIO172

K3

TEMPIN2/GPIO173

M6

TEMPIN3/TALERT#/GPIO174

SERIAL ATA

UDSON-2

H

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

ROM_RST#/SPI_WP#/GPIO161

HW MONITOR

D

_CLK/SCLK_2/GPIO73

S

_CMD/SLOAD_2/GPIO74

D

S

_CD/GPIO75

D

SD_WP/GPIO76

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_COL

GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_RXCTL/RXDV

GBE_RXERR

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

VGA_RED

VGA_GREEN

VGA_BLUE

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70 VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

AUXCAL

ML_VGA_L0P

ML_VGA_L0N

ML_VGA_L1P

ML_VGA_L1N

ML_VGA_L2P

ML_VGA_L2N

ML_VGA_L3P

ML_VGA_L3N

ML_VGA_HPD/GPIO229

VIN0/GPIO175

VIN1/GPIO176

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

NC1 NC2 NC3 NC4 NC5

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10

FCH SCLv1.20 19:

AB8

GBE_COL/GBE_CRS/GBE_RXERR NC

AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9

GBE_PHY_INTR

V6

SPI_SO

V5

SPI_SI

V3

SPI_CLK_FCH_R

T6

SPI_SB_CS0#

V1

SPI_WP#

L30

L32

M29

M28 N30

M33 N32

K31

V28 V29

U28

T31 T33 T29 T28 R32 R30 P29 P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG16 AH10 A28 G27 L4

1 2

R104 150_0402_1%R104 150_0402_1%

1 2

R105 150_0402_1%R105 150_0402_1%

1 2

R106 150_0402_1%R106 150_0402_1%

1 2

R109 715_0402_1%R109 715_0402_1%

AUXCAL

R111 100_0402_1%R111 100_0402_1%

1 2

R113 10K_0402_5%R113 10K_040 2_5%

1 2

R114 10K_0402_5%R114 10K_040 2_5%

1 2

R115 10K_0402_5%R115 10K_040 2_5%

1 2

R116 10K_0402_5%R116 10K_040 2_5%

1 2

R117 10K_0402_5%R117 10K_040 2_5%

1 2

R118 10K_0402_5%R118 10K_040 2_5%

1 2

R120 10K_0402_5%R120 10K_040 2_5%

1 2

R121 10K_0402_5%R121 10K_040 2_5%

3

VALW

+

CRT_HSYNC [28] CRT_VSYNC [28]

CRT_DDC_DATA [28] CRT_DDC_CLK [28]

ML_VGA_AUXP_C [7] ML_VGA_AUXN_C [7]

1 2

ML_VGA_TXP0 [7] ML_VGA_TXN0 [7] ML_VGA_TXP1 [7] ML_VGA_TXN1 [7] ML_VGA_TXP2 [7] ML_VGA_TXN2 [7] ML_VGA_TXP3 [7] ML_VGA_TXN3 [7]

ML_VGA_HPD [7]

Follow Comal OR B Rework Memo

R94 10K_0402_5%R94 10K_0402_5%

3

+

VALW

8 7 6 5

DI

3

0.1U_0402_16V4Z

SPI_HOLD# SPI_CLK_FCH SPI_SI

GBE_PHY_INTR

C

41

1

1 2

R100 10K_0402_5%R100 10K_0402_5%

1 2

S

I_HOLD#

9

5

R

01

1

10K_0402_5%

1 2

SPI_SB_CS0# SPI_SO

1 2

SPI_WP#

DAC_RED [28]

DAC_GRN [28]

DAC_BLU [28]

+VDDAN_11_ML

+FCH_VDDAN_33_DAC

12

R11210K_0402_5% R11210K_0402_5%

Used as GPIO181 or configure as one of the f ollowing:

-> 10-KΩ 5% pul l-down resistor .

-> 10-KΩ 5% pul l-up resistor t o +3.3V_S5.

-> Enabled inte grated pull-dow n/up and left unconnected.

P

10K_0402_5%

U

4

1

CS#

2

DO

3

WP#

4

GND

25Q32BVSSIG_SO8

W

VCC

HOLD#

CLK

1 2

R99

R99 0_0402_5%

0_0402_5%

1 2

218-0844000 A0 BOLTON-M3

APU_ALERT#_FCH[7]

A

B

218-0844000 A0 BOLTON-M3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Date: Sheet

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

LA-8127P

E

of

13 51Tuesday, March 12, 2013

1.0

A

B

C

D

E

1

R

1

R

C

H_PWRGD[45]

F

1 1

For ODD Power Leakage issue

ODD_DA#_FCH[30]

2 2

+3V_FCH

For FCH internal debug use

1 2

R128 2.2K_0402_5%@R128 2.2K_0402_5%@

1 2

R129 2.2K_0402_5%@R129 2.2K_0402_5%@

1 2

R130 2.2K_0402_5%@R130 2.2K_0402_5%@

+3V_FCH

1 2

R154 10K_0402_5%R154 10K_0402_5%

1 2

R137 10K_0402_5%R137 10K_0402_5%

1 2

R139 10K_0402_5%R139 10K_0402_5%

1 2

R205 10K_0402_5%@R205 10K_0402_5%@

1 2

R143 10K_0402_5%@R143 10K_0402_5%@

1 2

R145 100K_0402_5%@R145 100K_0402_5%@

1 2

R149 10K_0402_5%R149 10K_0402_5%

3 3

4 4

1 2

R155 10K_0402_5%@R155 10K_0402_5%@

+3VS

1 2

R174 10K_0402_5%R174 10K_0402_5%

1 2

R156 10K_0402_5%R156 10K_0402_5%

1 2

R151 2.2K_0402_5%R151 2.2K_0402_5%

1 2

R152 2.2K_0402_5%R152 2.2K_0402_5%

1 2

R153 10K_0402_5%R153 10K_0402_5%

1 2

R159 8.2K_0402_5%R159 8.2K_0402_5%

1 2

R160 10K_0402_5%@R160 10K_0402_5%@

1 2

R161 10K_0402_5%@R161 10K_0402_5%@

1 2

R162 10K_0402_5%R162 10K_0402_5%

1 2

R163 10K_0402_5%@R163 10K_0402_5%@

1 2

R166 10K_0402_5%@R166 10K_0402_5%@

1 2

R167 10K_0402_5%@R167 10K_0402_5%@

CLKREQG Not Implemented: Used as GPIO65, IDLEEXIT#, or left unconnected.

4

2

@

C

45

1

.1U_0402_16V7K

1

+3VS +3VS

1 2

THERMTRIP 8/16 AMD confirmed: The FCH already have internal PU resistor and don't need external PU resistor. Note: need BIOS check: Ensure FCH internal pull-up resistor to +3.3V S5 is disabled to prevent leakage when APU is powered down.

A

12

24 0_0402_5%@

12

25 0_0402_5%

+

VS

3

@

C

44 .1U_0402_16V7K

1

1 2

5

2

P

B

Y

1

A

G

C74VHC1G08DFT2G_SC70-5

M

3

@

U

5

R213

R213 10K_0402_5%

10K_0402_5%

PEG_CLKREQ#_R

G

S

Q43

Q43 2N7002K_SOT23-3

2N7002K_SOT23-3

TEST0

TEST1

TEST2

USB_OC3#

USB_OC1#

USB_OC0#

ODD_DETECT#

H_THERMTRIP#

EC_LID_OUT#

FCH_PCIE_WAKE#

ODD_DA#_FCH_R

WLAN_CLKREQ#

CARD_CLKREQ#

FCH_SCLK0

FCH_SDATA0

WD_PWRGD

LAN_CLKREQ#

FCH_SCLK1

FCH_SDATA1

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

2

D

SCL1/SDA1: ASF-Capable LAN Devices Not Implemented: Used as GPIO227 or configured for one of the following options: 10-KΩ 5% pull-up resistor to +3.3V_S5; 10-KΩ 5% pull-down resistor.

13

ODD_DA#_FCH_R

+3V_FCH

12

UMA@

12

DIS@

2

D

U

IE_RST2 : Reset PCIE device on Hudson2/3

PC

T

3

1

F

H_PWRGD

C

T

ST0

E

T

ST1

E

T

ST2

E

SYS_RESET#

WD_PWRGD

FCH_SCLK0 FCH_SDATA0 FCH_SCLK1 FCH_SDATA1

PEG_CLKREQ#_R

ODD_DA#_FCH_R

ODD_DETECT# USB_OC3#

USB_OC1# USB_OC0#

10

01

1

T19T19

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

GPIO188

GPIO189 GPIO190

T34T34 T35T35 T36T36 T37T37 T38T38 T39T39 T43T43 T44T44 T45T45 T40T40 T41T41 T42T42 T49T49 T50T50 T51T51 T46T46 T47T47 T48T48

FunctionGPIO188 GPIO189 GPIO190

PX

Reserved

DISCRET

UMA

E

_LID_OUT#[31]

C

P

_SLP_S3#[31]

M M

_SLP_S5#[31]

P P

TN_OUT#[31]

F

H_POK [31]

C

G

ATE [31,45]

V

+3V_FCH

PEG_CLKREQ#[18]

HDA_BITCLK_AUDIO[29] HDA_SDOUT_AUDIO[29]

HDA_SDIN0[29]

HDA_SYNC_AUDIO[29]

HDA_RST_AUDIO#[29]

PXS_RST#[12,17] PXS_PWREN[12,19,43,44]

DMN66D0LDW-7_SOT363-6

+3V_FCH

1 2

R211 10K_0402_5%DIS@R211 10K_0402_5%DIS@

EC_PXCONTROL[31]

8/26

12

@

UMA@

R157

10K_0402_5%

12

DIS@

R164

10K_0402_5%

R206

R158

10K_0402_5%

GPIO188

GPIO189

GPIO190

12

R210

R165

10K_0402_5%

B

G

TEA20[31]

A

KB_RST#[31] EC_SCI#[31] EC_SMI#[31]

1 2

R126 10K_0402_5%@R126 10K_0402_5%@

FCH_PCIE_WAKE#[35]

H_THERMTRIP#[7]

EC_RSMRST#[31]

LAN_CLKREQ#[35]

CARD_CLKREQ#[35]

FCH_SPKR[29] FCH_SCLK0[10,11,31,33] FCH_SDATA0[10,11,31,33] FCH_SCLK1[33] FCH_SDATA1[33]

WLAN_CLKREQ#[33]

VGA_PWRGD[44]

R131 0_0402_5%@R 131 0_0402_5%@

ODD_DETECT#[30]

USB_OC3#[35]

USB_OC1#[34] USB_OC0#[34]

1 2

R134 33_0402_5%R134 33_0402_5%

1 2

R135 33_0402_5%R135 33_0402_5%

1 2

R138 33_0402_5%R138 33_0402_5%

1 2

R140 33_0402_5%R140 33_0402_5%

DIS@

Q44A

DMN66D0LDW-7_SOT363-6

2

3 4

EC_PXCONTROL

0

0 0

0

1 1

B

61

12 12

DIS@

Q44B

12

R1460_0402_5% @ R1460_0402_5% @ R1480_0402_5% @ R1480_0402_5% @

5

U

AB6

P

IE_RST2#/PCI_PME#/GEVENT4#

C

R2

I

#/GEVENT22#

R

W7

S

I_CS3#/GBE_STAT1/GEVENT21#

P

T3

S

P_S3#

L

W2

S

P_S5#

L

J4

P

R_BTN#

W

N7

P

R_GOOD

W

T9

E

ST0

T

T10

E

ST1/TMS

T

V9

T

ST2

E

AE22

G

20IN/GEVENT0#

A

AG19

KBRST#/GEVENT1#

R9

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

LPC_PD#/GEVENT5#

U4

SYS_RESET#/GEVENT19#

K1

WAKE#/GEVENT8#

V7

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVEN T2#

AF19

WD_PWRGD

U2

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

T7

SCL1/GPIO227

R7

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

J2

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN #/GPIO51

V8

DDR3_RST#/GEVENT7#/VGA_PD

W8

GBE_LED0/GPIO183

Y6

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BLINK/USB_OC7#/GEVENT18#

R8

USB_OC6#/IR_TX1/GEVENT6#

T1

USB_OC5#/IR_TX0/GEVENT17#

P6

USB_OC4#/IR_RX0/GEVENT16#

F5

USB_OC3#/AC_PRES/TDO/GEVENT15#

P5

USB_OC2#/TCK/GEVENT14#

J7

USB_OC1#/TDI/GEVENT13#

T8

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12 #

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

Y5

AZ_SDIN1/GPIO168

Y3

AZ_SDIN2/GPIO169

Y1

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

218-0844000 A0 BOLTON-M3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

HUDSON-2

EMBEDDED CTRL

2012/11/22 2015/11/22

U

BCLK/14M_25M_48M_OSC

S

USB MISCUSB 1.1USB 2.0USB 3.0

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

Deciphered Date

U

B_FSD1P/GPIO186

S

U

B_FSD0P/GPIO185

S

U

U USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9N

USB_HSD8N

USB_HSD7N

USB_HSD6N

USB_HSD5N

USB_HSD4N

USB_HSD3N

USB_HSD2N

USB_HSD1N

USB_HSD0N

USBSS_CALRP

USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

B_RCOMP

S

U

B_FSD1N

S

B_FSD0N

U

B_HSD13P

S S

B_HSD13N

B_HSD12P

S

USB_HSD9P

USB_HSD8P

USB_HSD7P

USB_HSD6P

USB_HSD5P

USB_HSD4P

USB_HSD3P

USB_HSD2P

USB_HSD1P

USB_HSD0P

G8

B9

U

B_RCOMP

S

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

K12 K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

F8 E8

C6 A6

C5 A5

C1 C3

E1 E3

C16

USBSS_CALRP

A16

USBSS_CALRN

A14 C14

C12 A12

D15

USB30_FTX_DRX_P2_C

B15

USB30_FTX_DRX_N2_C

E14

USB30_FRX_DTX_P2

F14

USB30_FRX_DTX_N2

F15

USB30_FTX_DRX_P1_C

G15

USB30_FTX_DRX_N1_C

H13

USB30_FRX_DTX_P1

G13

USB30_FRX_DTX_N1

J16

USB30_FTX_DRX_P0_C

H16

USB30_FTX_DRX_N0_C

J15

USB30_FRX_DTX_P0

K15

USB30_FRX_DTX_N0

H19

R144 10K_0402_5%R144 10K_0402_5%

G19

R147 10K_0402_5%R147 10K_0402_5%

G22

FCH_SIC

G21

FCH_SID

E22 H22 J22

EC_PWM2

H21

K21 K22 F22 F24 E24 B23 C24 F18

D

USB30_N12 USB30_N11 USB30_N10 USB20_N6 USB20_N0

1 2 1 2

1 2

R

27 11.8K_0402_1%

1

U

B30_P12 [34]

S

USB30_N12 [34]

USB30_P11 [34] USB30_N11 [34]

USB30_P10 [34] USB30_N10 [34]

LP3

LP2

LP1

BT

USB20_P7 [35] USB20_N7 [35]

USB20_P6 [26] USB20_N6 [26]

USB20_P5 [33] USB20_N5 [33]

R230 300_0402_5%@R230 300_0402_5%@ R231 300_0402_5%@R231 300_0402_5%@ R232 300_0402_5%@R232 300_0402_5%@ R233 300_0402_5%@R233 300_0402_5%@ R234 300_0402_5%@R234 300_0402_5%@

R132 1K_0402_1%R132 1K_0402 _1% R133 1K_0402_1%R133 1K_0402 _1%

FP

CMOS

WLAN

Near Device

1 2 1 2 1 2 1 2 1 2

USB20_P0 [35] USB20_N0 [35]

1 2 1 2

1 2

C212 .1U_0402_16V7KC212 .1U_0402_16V7K

1 2

C213 .1U_0402_16V7KC213 .1U_0402_16V7K

1 2

C218 .1U_0402_16V7KC218 .1U_0402_16V7K

1 2

C219 .1U_0402_16V7KC219 .1U_0402_16V7K

1 2

C220 .1U_0402_16V7KC220 .1U_0402_16V7K

1 2

C221 .1U_0402_16V7KC221 .1U_0402_16V7K

Title

Size Document Number Rev

Custom

Date: Sheet of

RP1

FCH_SIC [7] FCH_SID [7]

EC_PWM2 [16]

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

1 2

C222 10P_0402_50V8J@C222 10P_0402_50V8J@

1 2

C223 10P_0402_50V8J@C223 10P_0402_50V8J@

1 2

C224 10P_0402_50V8J@C224 10P_0402_50V8J@

1 2

C225 10P_0402_50V8J@C225 10P_0402_50V8J@

1 2

C226 10P_0402_50V8J@C226 10P_0402_50V8J@

+FCH_VDD_11_SSUSB_S

USB30_FTX_DRX_P2 [34] USB30_FTX_DRX_N2 [34]

USB30_FRX_DTX_P2 [34] USB30_FRX_DTX_N2 [34]

USB30_FTX_DRX_P1 [34] USB30_FTX_DRX_N1 [34]

USB30_FRX_DTX_P1 [34] USB30_FRX_DTX_N1 [34]

USB30_FTX_DRX_P0 [34] USB30_FTX_DRX_N0 [34]

USB30_FRX_DTX_P0 [34] USB30_FRX_DTX_N0 [34]

strap pin

LA-8127P

E

LP3

LP2

LP1

1.0

14 51Tuesday, March 12, 2013

1.0

A

B

C

D

E

3

VS

+

CH_VDDAN_33_DAC

F

1 1

3

VS

+

+3VS +FCH_VDDAN_33_DAC

F

BMA-L11-201209-221LMA30T_0805

2 2

+3V

3 3

+3VS

4 4

1 2

M

BK1608221YZF_2P

220 ohm

1 2

R

68 0_0402_5%@

1

L3

1 2

MBK1608221YZF_2P

@

L5

1 2

220 ohm

1 2

MBK1608221YZF_2P

1 2

MBK1608221YZF_2P

220 ohm

1 2

MBK1608221YZF_2P

220 ohm

1 2

MBK1608221YZF_2P

220 ohm

2

L

L7

220 ohm

L11

L14

L15

V

DDPL_33_SYS

+

C154

1

2

+

DDPL_33_MLDAC

V

C153

1

2

30mil

2.2U_0603_6.3V6K

C175

1

2

+VDDPL_33_SSUSB_S

2.2U_0402_6.3V6M

C1

C1 85

85

1

2

+VDDPL_33_USB_S

C193

1

2

+VDDPL_33_PCIE

+VDDPL_33_SATA

A

2.2U_0402_6.3V6M

.1U_0402_16V7K

C147

1

2

.1U_0402_16V7K

C158

1

2

LDO_CAP: Internally generated 1.8V supply for the RGB outputs

+1.1VS

0.1U_0402_16V4Z

C176

1

2

.1U_0402_16V7K

C186

1

2

2.2U_0402_6.3V6M

.1U_0402_16V7K

C194

1

2

2.2U_0402_6.3V6M

C200

1

2

2.2U_0402_6.3V6M

C207

1

+1.1V

2

+

VS

3

+VDDPL_33_MLDAC

L4

1 2

MBK1608221YZF_2P

220 ohm/2A

+3V

FBMA-L11-201209-221LMA30T_0805

+1.1V

MBK1608221YZF_2P

+1.1V

MBK1608221YZF_2P

L16

FBMA-L11-201209-221LMA30T_0805

42 ohm/4A

1 2

R

71 0_0603_5%@

1

R

73 0_0402_5%@

1

R169 0_0402_5%@R 169 0_0402_5%@

+VDDPL_33_SSUSB_S

+VDDPL_33_USB_S

+VDDPL_33_PCIE

+VDDPL_33_SATA

R176 0_0402_5%@R 176 0_0402_5%@

R177 0_0603_5%@R 177 0_0603_5%@

L6

1 2

220 ohm/2A

L10

1 2

220 ohm

L12

1 2

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

12

1 2

R183 0_0603_5%@R 183 0_0603_5%@

1 2

R185 0_0603_5%@R 185 0_0603_5%@

B

C146

1

2

+

DDPL_33_SYS

V

1 2

10U_0603_6.3V6M

C180

1

2

2.2U_0402_6.3V6M

C188

1

2

10U_0603_6.3V6M

C195

1

2

+

DDIO_33_PCIGP

V

22U_0603_6.3V6M

.1U_0402_16V7K

C152

C151

1

2

+FCH_VDDAN_33_DAC

@

1 2

C164 2.2U_0603_6.3V6K

4.7U_0402_6.3V6M

.1U_0402_16V7K

C168

C169

1

2

1 2

R180 0_0402_5%@R 180 0_0402_5%@

+VDDAN_33_USB

10U_0603_6.3V6M

1U_0402_6.3V6K

C181

C182

1

2

+VDDAN_11_USB_S

.1U_0402_16V7K

C190

C189

1

@

2

+VDDCR_11V_USB

.1U_0402_16V7K

C196

C197

1

2

+VDDAN_11_SSUSB

1U_0402_6.3V6K

C201

C202

1

2

+VDDCR_11_SSUSB

10U_0603_6.3V6M

C208

C209

1

2

.1U_0402_16V7K

C157

1

2

V

DDPL_33_DAC

+

+VDDPL_33_ML

+VDDPL_11_DAC

+VDDAN_11_ML

.1U_0402_16V7K

C170

1

2

1U_0402_6.3V6K

C184

C183

1

2

.1U_0402_16V7K

C203

1

2

1U_0402_6.3V6K

C210

1

2

.1U_0402_16V7K

2

C

U

102mA

AB17

D

DIO_33_PCIGP_1

V

AB18

V

DIO_33_PCIGP_2

D

AE9

V

DIO_33_PCIGP_3

D

AD10

V

DIO_33_PCIGP_4

D

AG7

V

DIO_33_PCIGP_5

D

AC13

V

DIO_33_PCIGP_6

D

AB12

V

DIO_33_PCIGP_7

D

AB13

D

DIO_33_PCIGP_8

V

AB14

D

DIO_33_PCIGP_9

V

AB16

V

DIO_33_PCIGP_10

D

4

mA

7

H24

V

DPL_33_SYS

D

20mA

V22

VDDPL_33_DAC

12mA

U22

VDDPL_33_ML

30mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

D7

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

G7

VDDAN_33_USB_S_1

H8

.1U_0402_16V7K

VDDAN_33_USB_S_2

J8

VDDAN_33_USB_S_3

K8

VDDAN_33_USB_S_4

K9

VDDAN_33_USB_S_5

M9

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

N9

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

218-0844000 A0 BOLTON-M3

.1U_0402_16V7K

C211

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

H

UDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

C

D

V V

D

V

D

V

D

V

D

V

D

V

D D

V

CORE S0

D

V

DAN_11_CLK_1

D

V

DAN_11_CLK_2

D VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM_ S

VDDIO_AZ_S

2012/11/22 2015/11/22

1007mA

T14

DCR_11_1

T17

DCR_11_2

T20

DCR_11_3

U16

DCR_11_4

U18

DCR_11_5

V14

DCR_11_6

V17

DCR_11_7

V20

DCR_11_8

Y17

DCR_11_9

340mA

H26 J25 K24 L22 M22 N21 N22 P22

1088mA

AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27

1337mA

AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19

59mA

N18 L19 M18 V12 V13 Y12 Y13 W11

5mA

G24

187mA

N20 M20

70mA

J24

12mA

M8

26mA

AA4

Compal Secret Data

.1U_0402_16V7K

C155

1

2

.1U_0402_16V7K

C159

1

2

.1U_0402_16V7K

C165

1

2

.1U_0402_16V7K

C171

1

2

1U_0402_6.3V6K

C177

1

2

2.2U_0402_6.3V6M

C187

1

2

1U_0402_6.3V6K

C191

1

2

2.2U_0402_6.3V6M

C198

1

2

2.2U_0402_6.3V6M

C204

1

2

Deciphered Date

V

CC_VDDCR_11

+

.1U_0402_16V7K

1U_0402_6.3V6K

C148

C149

1

2

+

.1VS_CKVDD

1

.1U_0402_16V7K

1U_0402_6.3V6K

C160

C161

1

2

+VDDAN_11_PCIE

+VDDIO_33_S

22U_0603_6.3V6M

1U_0402_6.3V6K

C167

C166

1

2

1U_0402_6.3V6K

C172

C173

1

2

2.2U_0402_6.3V6M

1U_0402_6.3V6K

C179

C178

1

2

+VDDXL_3.3V

+VDDCR_1.1V

1U_0402_6.3V6K

C192

1

2

+VDDPL_11_SYS_S

.1U_0402_16V7K

C199

1

2

+VDDAN_33_HWM

.1U_0402_16V7K

C205

1

2

+VDDIO_AZ

1 2

C206 2.2U_0402_6.3V6MC206 2.2U_0402_6.3V6M

D

C150

C162

+VDDAN_11_PCIE

C174

1U_0402_6.3V6K

C156

1

2

+

.1VS_CKVDD

1

1U_0402_6.3V6K

C163

1

2

+AVDD_SATA

22U_0603_6.3V6M

1

2

R179 0_0402_5%@R 179 0_0402_5%@

R182 0_0402_5%@R 182 0_0402_5%@

R184 0_0402_5%@R 184 0_0402_5%@

1 2

10U_0603_6.3V6M

1

2

1 2

R

72 0_0603_5%@

1

22U_0603_6.3V6M

1

2

1 2

L8

1 2

MBK1608221YZF_2P

220 ohm

1 2

R181 0_0603_5%@R 181 0_0603_5%@

L13

1 2

MBK1608221YZF_2P

220 ohm

1 2

1

.1VS

+

1

700_08 05_5% @

R

+

.1VS

1

+1.1VS

R1750_0805_5% @ R1750_0805_5% @

+1.1VS

R1780_0805_5% @ R1780_0805_5% @

+3V_FCH

+3V

+VDDXL_3.3V Tie to +3.3V_S5 rail if USB3 Wake is supported; otherwise, tie to +3.3V_S0 rail. Hudson-2 designs: Tie to +3.3V_S0 rail.

+1.1VALW

VDDPL_11_SYS_S should be

+1.1V

tied to +1.1V_S5 rail if USB 3.0 Wake is supported; otherwise, it can be tied to +1.1V_S0 rail.

+3V_FCH

AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.

VDDIO_AZ_S

+3VS

Wake on Ring supported: Tie to +3.3/

1.5V_S5 rail, and treat like a 3.3/1.1V_S5 rail. Wake on Ring not supported: Tie to +3.3/

1.5V_S0 rail, and treat like a 3.3/1.1V S0 rail.

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

FCH PWR

FCH PWR LA-8127P

LA-8127P

E

of

15 51Tuesday, March 12, 2013

1.0

5

2

E

U

UDSON-2

H

A3

A33

B7

B13

D D

C C

B B

D13

E12 E16 E29

F11 F13 F16 F17 F19 F23 F25 F29

G16 G32 H12 H15 H29

K16 K27 K28

L12 L13 L15 L16

L21 M13 M16 M21 M25

N11

N13

N23

N24

P12

P18

P20

P21

P31

P33

R11

R25

R28

T11

T16

T18

K25

H25

J10 J13 J28 J32

D9

E5

F7 F9

G6

J6 J9

K7

L6

N6

R4

N8

H

V

S

V

S

V

S

V

S

S S

S

V V

S

S S

S

V

S

V V

S

S VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GROUND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSPL_DAC

VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

T25

S

T27

S

U6

S

U14

S

U17

S

U20

S

U21

S

U30

S

U32

S

V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

T21 L28 K33 N28

R6

S

RAP PINS

T

PULL HIGH

PULL LOW

PCI_CLK1[12 ]

PCI_CLK3[12 ]

PCI_CLK4[12 ]

CLK_PCI_EC[12,31]

LPC_CLK1[12]

EC_PWM2[14]

RTC_CLK[12,31]

C

I_CLK1

P

L

LOW

A PCIE GEN2

D

FAULT

E

FORCE PCIE GEN1

4

C

I_CLK3

P

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

@

R186 10K_0402_5%R186 10K_0 402_5%

12

R198 10K_0402_5%@R198 10K_0402_5%

12

C

I_CLK4 CLK_PCI_EC

P

O

N_FUSION

N CLOCK MODE

FUSION CLOCK MODE

DEFAULT

R188 10K_0402_5%@R188 10K_0402_5%

R187 10K_0402_5%@R187 10K_0402_5%

12

@

R200 10K_0402_5%R200 10K_0 402_5%

R199 10K_0402_5%R199 10K_0 402_5%

12

C

E E

NABLED

EC DISABLED

DEFAULT

R189 10K_0402_5%@R189 10K_0402_5%

12

@

R201 10K_0402_5%R201 10K_0 402_5%

12

@

3

L

KGEN

C ENABLED

D

FAULT

E

CLKGEN DISABLE

R190 10K_0402_5%R190 10K_0 402_5%

@

R202 10K_0402_5%@R202 10K_0402_5%

2

E

BUG STRAPS

D

F

H HAS 15K INTERNAL PU FOR PCI_AD[27:23]

C

_PWM2

E

P

C ROM

L

SPI ROM

DEFAULT

+3V_FCH+3 V_FCH+3V_FC H+3V_FCH+3VS+3VS+3VS

R192 10K_0402_5%R192 10K_0 402_5%

R191 10K_0402_5%@R191 10K_0402_5%

12

R204 2.2K_0402_5%@R204 2.2K_0402_5%

R203 2.2K_0402_5%R203 2.2K_0402_5%

12

@

T

C_CLKLPC_CLK1

R

5

PLUS

S MODE DISABLED

D

FAULT

E

S5 PLUS MODE ENABLED

C

I_AD27 PCI_AD26

P

P HIGH

PULL LOW

PCI_AD27[12]

PCI_AD26[12]

PCI_AD25[12]

PCI_AD24[12]

PCI_AD23[12]

USE PCI

LL

U

PLL

D

FAULT

E

BYPASS PCI PLL

DISABLE ILA AUTORUN

D

FAULT

E

ENABLE ILA AUTORUN

R193 2.2K_0402_5%@R193 2.2K_0402_5%

12

@

C

I_AD25 PCI_AD24

P

S

E FC

U PLL

BYPASS FC PLL

R194 2.2K_0402_5%@R194 2.2K_0402_5%

12

R195 2.2K_0402_5%@R195 2.2K_0402_5%

12

@

1

USE DEFAULT PCIE STRAPS

D

FAULT

E

USE EEPROM PCIE STRAPS

12

@

R196 2.2K_0402_5%@R196 2.2K_0402_5%

PCI_AD23

DISABLE PCI MEM BOOT

D

FAULTDEFAULT

E

ENABLE PCI MEM BOOT

12

@

R197 2.2K_0402_5%@R197 2.2K_0402_5%

218-0844000 A0 BOLTON-M3

A A

218-0844000 A0 BOLTON-M3

5

Security Classification

2012/11/22 2015/11/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

FCH-VSS/Strap

LA-8127P

1

16 5

1.0

1Tuesday, March 12, 2013

A

B

C

D

E

A

W36

W38

M37

M35

G36

G38

AB35 AA36

AH16

AA30

A

38

Y

7

3

Y35

V37

V35 U36

U38 T37

T35 R36

R38 P37

P35 N36

N38

L36

L38 K37

K35

J36

J38

H37

H35

F37

F35 E37

SDV/FVT, NO.3

U

401A

1

P

ART 1 0F 9

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC NC

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

TEST_PG

PERSTB

S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39DIS@

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCI EXPRESS INTERFACE

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

P

IE_CRX_GTX_P[7..0]

C

P

IE_CRX_GTX_N[7..0]

C

3

Y

P

IE_CRX_C_GTX_P0

C

Y

2

3

P

IE_CRX_C_GTX_N0

C

W33

PCIE_CRX_C_GTX_P1

W32

PCIE_CRX_C_GTX_N1 PCIE_CRX_GTX_N1

U33

PCIE_CRX_C_GTX_P2

U32

PCIE_CRX_C_GTX_N2

U30

PCIE_CRX_C_GTX_P3

U29

PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_N3

T33

PCIE_CRX_C_GTX_P4 PCIE_CRX_GTX_P4

T32

PCIE_CRX_C_GTX_N4

T30

PCIE_CRX_C_GTX_P5 PCIE_CRX_GTX_P5PCIE_CTX_GRX_P5

T29

P33

PCIE_CRX_C_GTX_P6

P32

PCIE_CRX_C_GTX_N6

P30

PCIE_CRX_C_GTX_P7 PCIE_CRX_GTX_P7

P29

SDV/FVT, NO.2SDV/FVT, NO.1

N33

NC

N32

NC

N30

NC

N29

NC

L33

NC

L32

NC

L30

NC

L29

NC

K33

NC

K32

NC

J33

NC

J32

NC

K30

NC

K29

NC

H33

NC

H32

NC

Y30

1 2

R1403 1.69K_0402_1%DIS@R1403 1.69K_0402_1%DIS@

1 2

Y29

R1405 1K_0402_1%DIS@R1405 1K_0402_1%DIS@

C

IE_CRX_GTX_P[7..0] [5]

P

C

IE_CRX_GTX_N[7..0] [5]

P

+0.95VGS

12

C

1

12

C

1

12

C1404.1U_0402_16V7K

12

C1405.1U_0402_16V7K DIS@C1405.1U_0402_16V7K DIS@

12

C1406.1U_0402_16V7K

12

C1407.1U_0402_16V7K DIS@C1407.1U_0402_16V7K DIS@

12

C1408.1U_0402_16V7K

12

C1403.1U_0402_16V7K DIS@C1403.1U_0402_16V7K DIS@

12

C1409.1U_0402_16V7K

12

C1410.1U_0402_16V7K DIS@C1410.1U_0402_16V7K DIS@

12

C1411.1U_0402_16V7K

12

C1412.1U_0402_16V7K DIS@C1412.1U_0402_16V7K DIS@

12

C1413.1U_0402_16V7K

12

C1414.1U_0402_16V7K DIS@C1414.1U_0402_16V7K DIS@

12

C1415.1U_0402_16V7K

12

C1416.1U_0402_16V7K DIS@C1416.1U_0402_16V7K DIS@

401.1U_0402_16V7K DIS@

402.1U_0402_16V7K DIS@

DIS@

P

IE_CRX_GTX_P0

C

P

IE_CRX_GTX_N0

C

PCIE_CRX_GTX_P1

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P3

PCIE_CRX_GTX_N4

PCIE_CRX_GTX_N5PCIE_CRX_C_GTX_N5

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_N7PCIE_CRX_C_GTX_N7

L

DS Interface

V

U

401D

1

ART 7 0F 9

P

RSVD/VARY_BL

LVDS CONTROL

LVTMDP

DIS@

PXS_RST#[12,14]

APU_PCIE_RST#[12,33,35]

RSVD/DIGON

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

NC#AF35

NC#AG36

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39

+3VGS

5

2

B

1

A

3

A

27

K

A

7

J2

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36

NC

AP37

NC

U1400

P

4

GPU_RST#

Y

G

DIS@

MC74VHC1G08DFT2G SC70 5P

SUN NC

P

IE_CTX_GRX_P[7..0]

P

IE_CTX_GRX_P[7..0][5]

C

P

IE_CTX_GRX_N[7..0][5]

C

1 1

2 2

3 3

CLK_PCIE_VGA[12] CLK_PCIE_VGA#[12]

C

P

IE_CTX_GRX_N[7..0]

C

P

IE_CTX_GRX_P0

C

P

IE_CTX_GRX_N0

C

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

CLK_PCIE_VGA CLK_PCIE_VGA#

12

DIS@

R1404 1K_0402_5%

GPU_RST#

12

DIS@

R2486

R2486 100K_0402_5%

100K_0402_5%

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

ATI_Sun Pro_M2_PCIE/LVDS

LA-8127P

17 51Tuesday, March 12, 2013

E

1.0

A

U

401B

1

SDV/FVT, NO.11

1 1

2 2

SDV/FVT, NO.6

VGA_AC_DET[31,44]

GPU_VID1[44] GPU_VID5[44]

GPU_VID2[44]

PEG_CLKREQ#[14]

GPU_VID3[44] GPU_VID4[44]

3 3

4 4

+1.8VGS

R1424

R1424 499_0402_1%

499_0402_1%

DIS@

1 2

12

DIS@

R1429

R1429 249_0402_1%

249_0402_1%

H

L

MLPS

Disable

Enable

+1.8VGS

BLM15BD121SN1D_2P~D

GPIO_28_FDO

TSVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

DIS@

1

C1438

C1438 .1U_0402_16V7K

.1U_0402_16V7K

2

DIS@

L1404

1 2

A

D1401

RB751V_SOD323 @

R1423 10K_0402_5%@R1423 10K_0402_5%@

0.60 V level, Please VREFG Divider ans cap close to ASIC

R1434 1K_0402_5%

R1435 10K_0402_5%

(1.8V@13mA TSVDD)

C1447

DIS@ C1447

DIS@

10U_0603_6.3V6M

1

401

T

T T

T

402

1

1 2

DIS@

T1400T1400

1 2

1

2

1U_0402_6.3V6K

DIS@

21

C1448

DIS@ C1448

DIS@

T1408T1408

1

2

E

NLK_CLK

G G

NLK_VSYNC

E

VGA_SMB_CK2 VGA_SMB_DA2

GPU_GPIO5

GPU_VID1 GPU_VID5 THM_ALERT#

GPU_VID2

PEG_CLKREQ#

GPU_VID3 GPU_VID4

+VREFG_GPU

GPIO24_TRSTB GPIO25_TDI GPIO26_TCK GPIO27_TMS GPIO28_TDO

+TSVDD

1

C1449

2

0.1U_0402_16V4Z

DIS@ C1449

DIS@

PX_EN

A A

A

AW5

AW6

AR10

AW10

AU10 AP10 AV11 AT11 AR12

AW12

AU12 AP12

AJ23

AH23

AK26

AJ26

AH20 AH18 AN16

AH17

AJ17

AK17

AJ13

AH15

AJ16

AK16

AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17

AL13

AJ14 AK13 AN13

AG32 AG33

AJ19 AK19

AJ20 AK20

AJ24 AH26 AH24

AC30

AK24

AH13

AL21

AD28

AM23 AN23 AK23

AL24 AM24

AF29 AG29

AK32

AL31

AJ32

AJ33

D

29 29

C

J

21

K

21

R

8

A A

8

U

A

8

P

8

W

A

3

R

A

1

R

A

1

U

A

3

U

W

3

AP6

AU5 AR6

AU6 AT7 AV7 AN7 AV9 AT9

MUTI GFX

E

NLK_CLK

G G

NLK_VSYNC

E

S

APLOCKA

W W

APLOCKB

S

N

C C

N D

G_CNTL0

B

N

C

N

C

N

C

D

G_DATA0

B

D

G_DATA1

B

D

G_DATA2

B DBG_DATA3 DBG_DATA4 DBG_DATA5 DBG_DATA6 DBG_DATA7 DBG_DATA8 DBG_DATA9 DBG_DATA10 DBG_DATA11 DBG_DATA12 DBG_DATA13 DBG_DATA14 DBG_DATA15 DBG_DATA16 DBG_DATA17 DBG_DATA18 DBG_DATA19 DBG_DATA20 DBG_DATA21 DBG_DATA22 DBG_DATA23

SMBCLK

SMBus

SMBDATA

SCL

I2C

SDA

GENERAL PURPOSE I/O

GPIO_0 GPIO_1 GPIO_2

GPIO_5_AC_BATT GPIO_6_TACH GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21 GPIO_22_ROMCSB CLKREQB

GPIO_29 GPIO_30

GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF_HPD5 GENERICG_HPD6

CEC_1

HPD1

DBG_VREFG

BACO

PX_EN

DEBUG

TESTEN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

THERMAL

DPLUS DMINUS

GPIO_28_FDO

TS_A

TSVDD TSVSS

PART 2 0F 9

DPA

DPB

DPC

DPD

B

DAC1

MLPS

DDC/AUX

S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39DIS@

B

AVSSN

HSYNC VSYNC

AVDD

AVSSQ

VDD1DI

VSS1DI

NC_SVI2 NC_SVI2 NC_SVI2

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

DDCVGACLK

DDCVGADATA

RSET

PS_0

PS_1

PS_2

PS_3

C

U

24

A

N

C

A

23

V

N

C

A

25

T

C

N

R

24

A

N

C

A

26

U

C

N

A

25

V

N

C

T

27

A

G

R

R T

V U

26

30 29

31 30

GPIO24_TRSTB GPIO25_TDI GPIO27_TMS

GPIO26_TCK

R1422 499_0402_1%MARS@R1422 499_0402_1%MARS@

+AVDD

+VDD1DI

PS_0

PS_1

PS_2

PS_3

P

T

H

1 2

N

C

A

N

C

A

N

C

A

N

C

A

C

N

A

N

C

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

R

AD37

AE36

G

AD35

AF37

B

AE38

AC36 AC38

AB34

AD34 AE34

AC33 AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31 AD30 AD32

AM34

AD31

AG31

AD33

AM26 AN26

AM27 AL27

AM19 AL19

AN20 AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30 AJ31

TRAPS

S

U_GPIO5

R

425 100K_0402_5%@

1

R

M_ALERT#

426 2.2K_0402_5%@

1

1 2

R1418 10K_0402_5%@R1418 10K_0402_5%@

1 2

R1419 10K_0402_5%@R1419 10K_0402_5%@

1 2

R1420 10K_0402_5%@R1420 10K_0402_5%@

1 2

R1421 10K_0402_5%@R1421 10K_0402_5%@

(1.8V@70mA AVDD)

(1.8V@117mA VDD1DI)

10K_0402_5%

VGA_SMB_CK2

VGA_SMB_DA2

Resistor Divider Lookup Lable

R_pu (ohm)

+

VGS

3

12

+3VGS

R1430

0402 1% resistors are equired

Capacitor Divider Lookup Lable

Cap (nF) C1439

MARS@

1 2

L1401 BLM15BD121SN1D_2P~D

1

C1432

2

.1U_0402_16V7K

MARS@ C1432

MARS@

1

C1435

C1436

2

.1U_0402_16V7K

1U_0402_6.3V6K

MARS@ C1435

MARS@

MARS@ C1436

MARS@

+3VGS

12

DIS@

R1427

R1428

R1428 10K_0402_5%

10K_0402_5%

1

C1433

C1434

2

1U_0402_6.3V6K

10U_0603_6.3V6M

MARS@ C1434

MARS@

MARS@ C1433

MARS@

+1.8VGS

1 2

L1402

MARS@L1402

MARS@

BLM15BD121SN1D_2P~D

1

C1437

2

10U_0603_6.3V6M

MARS@ C1437

MARS@

VDD1DI MarsCR B Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

Internal VGA Thermal Sensor

+3VGS

5

34

2

Q1400B

DIS@ Q1400B

DIS@

2N7002KDWH_SOT363-6

Q1400A

DIS@ Q1400A

DIS@

2N7002KDWH_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

R_pd (ohm) R1436

NC

8.45k

4.53k

6.98k

4.53k

3.24k

3.4k

4.75k

Bitd [5:4]

680nF

00

82nF

01

10nF 10

NC

11

AVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

61

Bitd [3:1]

4.75k

2k

4.99k

5.62k

10k

NC

000

001

010

011

100

101

110

111

Compal PN

SE00000YJ80

SE076823K80

SE074103KN0

+1.8VGS

EC_SMB_CK2 [25,31,32,7]

EC_SMB_DA2 [25,31,32,7]

2012/11/22 2015/11/22

Compal Secret Data

D

C

NFIGURATION STRAPS

O

A

LOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE

L

GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

S

RAPS

T

TX_PWRS_ENB

TX_DEEMPH_EN

B

F_GEN3_EN_A

I

BIF_VGA DIS

ROMIDCFG[2:0]

BIOS_ROM_EN PS_2[3]

AUD[1]

AUD[0]

CEC_DIS PS_0[4]

RESERVED PS_1[3]

RESERVED PS_1[2]

RESERVED NA

AUD_PORT_CONN_PINSTRAP[2] PS_3[5]

AUD_PORT_CONN_PINSTRAP[1] PS_3[4]

AUD_PORT_CONN_PINSTRAP[0] PS_0[5]

PS_1[4] 0:50% Tx output swing

PS_1[5] 0:T x de-emphasis disabled

PS_1[1]

PS_2[4]

PS_0[3..1]

NA

DESCRIPTION OF DEFAULT SETTINGSMLPS

T

ansmitter Power Savings Enable

r

1:Full Tx output swing

PCIE Transmitter De-emphasis Enable

1:Tx de-emphasis enabled

PCIE Gen3 Enable (NOTE:RESERVED for Thames/Seymour and should be strapped to 0)

0:GEN3 not support at power-on 1:GEN3 supported at power-on

VGA control

0:VGA controller capacity enabled 1:VGA controller capacity disabled (for multi-GPU)

Serial ROM type or Memory Aperture Size Select

If PS_2[3]=0, defines memory aperture s ize If PS_2[3]=1, defines ROM type 100 - 512Kbit M25P05A (ST) 101 - 1Mbit M25P10A (ST ) 101 - 2Mbit M25P20 (ST) 101 - 4Mbit M25P40 (ST) 101 - 8Mbit M25P80 (ST) 100 - 512Kbit Pm25LV010 (Chingis) 101 - 1Mbit Pm25LV010 (Chingis)

Enable external BIOS ROM device

0:Disabled 1:Enabled

00 - No audio function 01 - Audio for DP only 10 - Audio for DP and HDMI if dongle is detected 11 - Audio for both DP and HDMI

HDMI must only be enabled on systems that are legally entitled. It isthe responsibility of the system designer to ensure that the system is entitled to support this feature.

Reserved for future ASIC

NOTE:ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET

Reserved

Reserved (for Thames/Whistl er/Seymour only)

STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS

111 = 0 usable endpoints 110 = 1 usable endpoints 101 = 2 usable endpoints 100 = 3 usable endpoints 011 = 4 usable endpoints 010 = 5 usable endpoints 001 = 6 usable endpoints 000 = all endpoints are usable

MLPS Strap

CapacitorBits[5:4]

Deciphered Date

D

PS_0[5:1]

PS_1[5:1]

PS_2[5:1]

PS_3[5:1]

PS_0 PS_1 PS_2 PS_3

@

C1439

0.01U_0402_16V7K

DIS@

1

C1440

2

Bits[3:1]

1 1

0 0

1 1

DIS@

1

C1441

2

0.01U_0402_16V7K

SDV/FVT, NO.14

0 0 1

0 0 0

X X X

@

1

C1442

2

0.01U_0402_16V7K

R_pu R_pd

8.45K 2K

NC

C

680 nF

N

X

NC

12

R1431

8.45K_0402_1%

12

4.75K_0402_1%

R1431

R1438

DIS@

R1430

X76@

8.45K_0402_1%

R1436

X76@

4.75K_0402_1%

Place CLOSE VGA CHIP

Title

ATI_Sun Pro_M2_Main_MSIC

Size Document Number Rev

C

Date: Sheet of

E

R

COMMENDED SETTINGS

E 0= DO NOT INSTALL RESISTOR 1 = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

4.75K

Mapping to VRAM type please refer to page 04

X

12

@

12

Compal Electronics, Inc.

R1432

@

8.45K_0402_1%

R1439

DIS@

4.75K_0402_1%

LA-8127P

E

12

8.45K_0402_1%

12

R1433

DIS@

R1440

DIS@

2K_0402_1%

+1.8VGS

18 51Tuesday, March 12, 2013

D

fault Setting

e

X

1

0

X

XX

0

XXX

12

1.0

A

M

LL_PVDD MarsCRB Design

P

220ohm 1 1

0.1u 1 1

1 1

1u 1 1 10u 1 1

SPLL_PVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

SPLL_VDDC MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

2 2

+1.8VGS

+0.95VGS

B

SDV/FVT, NO.9

+

.8VGS

1

L

1 2

MBK1608221YZF_2P

DIS@

L1406

BLM15BD121SN1D_2P~D

DIS@

L1407

BLM15BD121SN1D_2P~D

405

DIS@

405

DIS@

1

12

10U_0603_6.3V6M

(SPLL_VDDC:0.95V@100mA )

12

M

PLL_PVDD:1.8V@130mA )

(

1

C1450

2

DIS@ C14 50

DIS@

10U_0603_6.3V6M

C1452

C1451

2

.1U_0402_16V7K

1U_0402_6.3V6K

DIS@ C14 52

DIS@

DIS@ C14 51

DIS@

(SPLL_PVDD:1.8V@75mA )

1

C1453

2

DIS@ C14 53

DIS@

C1456

DIS@ C14 56

DIS@

10U_0603_6.3V6M

1

C1454

C1455

2

1U_0402_6.3V6K

.1U_0402_16V7K

DIS@ C14 54

DIS@

DIS@ C14 55

DIS@

1

2

1

C1458

C1457

2

.1U_0402_16V7K

1U_0402_6.3V6K

DIS@ C14 58

DIS@

DIS@ C14 57

DIS@

+MPLL_PVDD

+SPLL_PVDD

+SPLL_VDDC

T1406T1406 T1407T1407

SDV/FVT, NO.5

AM10

AN10

AF30 AF31

H7 H8

AN9

C

U

401C

1

MPLL_PVDD MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD NC_XTAL_PVSS

DIS@

P

RT 9 0F 9

A

33

V

X

ALIN

T

U

34

A

T

ALOUT

X

AW34

XO_IN

PLLS/XTAL

S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39

XO_IN2

CLKTESTA CLKTESTB

AW35

AK10 AL10

T

ALIN

X

ALOUT

T

GPUTESTA GPUTESTB

12

@

C1443

0.1U_0402_16V7K

12

@

R1441

51.1_0402_1%

D

X

T

20P_0402_50V8

12

@

C1444

0.1U_0402_16V7K

12

@

R1442

51.1_0402_1%

R

437 1M_0402_5%DIS@

1

ALOUT

1

DIS@

C1445

GND

2

27MHZ 16PF 5YEA27000163IF50Q5

DIS@

Y

E

X

ALIN

T

1

400

3

GND

DIS@

C1446

4

20P_0402_50V8

+3VALW

12

@

R1443

100K_0402_5%

PXS_PWREN#

1

@

Q1409

OUT

DDTC124EKA-7-F_SC59-3

IN

DDTC124EKA-7-F_SC59-3

GND

3

3 3

PXS_PWREN[12,14,43,44]

PXS_PWREN

2

SDV/FVT, NO.15

4 4

A

PXS_PWREN

SDV/FVT, NO.7

+5VALW

DIS@

R1445

1 2

470K_0402_1%

+3.3VS TO +3.3VGS

short Jumper J2

+3VS +3VGS

DIS@

R1446

1 2

10K_0402_5%

13

D

2

DIS@

G

Q1410

G

Q1410 2N7002K_SOT23-3

2N7002K_SOT23-3

S

J1

@J1

@

2 1

2MM

3 1

Q1407

AP2301GN-HF_SOT23-3

2

DIS@

1

C1466

C1466 .1U_0603_25V7K

.1U_0603_25V7K

2

B

DIS@Q1407

DIS@

10U_0603_6.3V6M

1

C1464

DIS@

2

PXS_PWREN#

1U_0603_10V6K

1

C1465

DIS@

2

1 2

12

13

D

S

R1447

R1444

R1444 470_0603_5%

470_0603_5%

@

Q1408

2

G

2N7002K_SOT23-3

0_0402_5%@

+1.5VS TO +1.5VGS

+1.5V

8

1

2

+VSB

DIS@

R1449

R1449 330K_0402_5%

330K_0402_5%

R1450

1 2

20K_0402_5%

61

DIS@

Q1412A

Q1412A 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

7 6 5

DIS@

C1467

10U_0603_6.3V6M

+3VALW

12

DIS@

R1451

100K_0402_5%

PXS_PWREN

DIS@ R1454

DIS@

100K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

5

12

R1454

2012/11/22 2015/11/22

PXS_PWREN2#

34

DIS@

Q1412B

Q1412B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

Compal Secret Data

Deciphered Date

2

D

J2

2 1

MM

2

DIS@

U1404

U1404 AO4430L_SO8

AO4430L_SO8

R1452

R1452 0_0402_5%

0_0402_5%

@

1 2

@

4

+1.5VGS

1 2

DIS@

1

3

C1468

C1468 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

DIS@

C1470

C1470 .1U_0603_25V7K

.1U_0603_25V7K

2

Title

ATI_Sun Pro_M2_BACO POWER

Size Document Number Rev

Custom

Date: Sheet of

DIS@

1

2

PXS_PWREN2#

Compal Electronics, Inc.

C1469

C1469 1U_0603_10V6K

1U_0603_10V6K

@

1 2

R1453 0_0402_5%

LA-8127P

E

12

13

D

S

R1448

@R1448

@

470_0603_5%

@

Q1411

Q1411 2N7002K_SOT23-3

2N7002K_SOT23-3

2

G

19 51Tuesday, March 12, 2013

1.0

A

U

401G

1

P

ART 6 0F 9

B

39

A

GND

E

9

3

GND

3

4

F

GND

F

9

3

GND

G

3

GND

G

4

3

GND

H

1

3

GND

H

4

3

GND

H

9

3

GND

3

1

J

GND

3

4

J

W31 W34

K K K

M34 M39 N31 N34 P31 P34 P39 R34

U31 U34 V34 V39

K14

M17 M22 M24 N16 N18

N21 N23 N26

R15 R17

R20 R22 R24 R27

U15 U17

U20 U22 U24 U27

V11 V16 V18 V21 V23 V26

GND

1

3

GND

3

4

GND

9

3

GND

L

1

3

GND

L

4

3

GND GND GND GND GND GND GND GND GND

T31

GND

T34

GND

T39

GND GND GND GND GND GND GND

Y34

GND

Y39

GND

F15

GND

F17

GND

F19

GND

F21

GND

F23

GND

F25

GND

F27

GND

F29

GND

F31

GND

F33

GND

F7

GND

F9

GND

G2

GND

G6

G

H9

G

J2

G

J27

GND

J6

G

J8

G GND

K7

G

L11

GND

L17

GND

L2

GND

L22

GND

L24

GND

L6

GND GND GND GND GND GND

N2

GND GND GND GND

N6

G GND GND

R2

G GND GND GND GND

R6

GND

T11

GND

T13

GND

T16

GND

T18

GND

T21

GND

T23

GND

T26

GND GND GND

U2

G GND GND GND GND

U6

G GND GND GND GND GND GND

W2

GND

W6

GND

Y15

GND

Y17

GND

Y20

GND

Y22

GND

Y24

GND

Y27

GND

DIS@

GND

ND ND ND

ND ND

ND

VSS_MECH VSS_MECH VSS_MECH

S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39

A

1 1

2 2

3 3

4 4

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND G GND GND

G GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

NC

3

A

ND

A

7

3 A

16

A A

18

A

2

A

21

A

23

A

26

A

28

A A

6

A

B

12

A A

15

B B

17

A A

20

B

A

22

B

A

24

B AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20

AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20

AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11

ND

F13

AG22

A39

MECH#1

AW1

MECH#2

AW39

MECH#3

P_VDDR MarsCRB Design

D

0.1u 1 1 1u 1 1 10u 1 1

A

MD: no display from GPU, can uninstall t he capacitors

+1.8VGS

1 2

R1456 0_0402_5%@R 1456 0_0402_5%@

T1403 PADT1403 PAD T1404 PADT1404 PAD T1405 PADT1405 PAD

B

(DP_VDDR:1.8V@237mA/link )

.1U_0402_16V7K

SDV/FVT, NO.8

@C1476

@

1

2

C1476

1U_0402_6.3V6K

@C1471

@

1

2

C1471

B

SDV/FVT, NO.10

R1459 150_0402_1%DIS@R1459 150_0402_1%DIS@

C

1

401F

U

A

24

N

NC

P

24

A

NC

P

25

A

NC

A

26

P

NC

U

28

A

NC

A

29

V

NC

AP20

NC

AP21

NC

AP22

NC

AP23

NC

AU18

NC

AV19

NC

DP_VDDR

12

AH34

DP_VDDR

AJ34

DP_VDDR

AF34

DP_VDDR

AG34

DP_VDDR

AM37

DP_VDDR

AL38

DP_VDDR

AM32

DP_VDDR

AW28

NC

AW18

NC

AM39

DP_CALR

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

P

ART 8 0F 9

DP_VDDR DP_VDDC

DP GND

CALIBRATION

S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39DIS@

Compal Secret Data

2012/11/22 2015/11/22

Compal Secret Data

DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC DP_VDDC

NC NC NC NC

DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR

Deciphered Date

A

P

A

P

A

N

A

P

A

L M

A

K

A A

K N

A

AP13 AT13 AP14 AP15

AN27 AP27 AP28 AW24 AW26 AN29 AP29 AP30 AW30 AW32 AN17 AP16 AP17 AW14 AW16 AN19 AP18 AP19 AW20 AW22 AN34 AP39 AR39 AU37 AF39 AH39 AK39 AL34 AV27 AR28 AV17 AR18 AN38 AM35 AN32

31 32

33 33 33

33 33 34

31

D

_VDDC

P

SDV/FVT, NO.8

D

DP_VDDC:0.95V@280mA/link )

(

D

E

0

.95VGS

+

1 2

R

4550_0402_5% @

1

@C1486

@

@C1485

@

1

2

C1486

C1485

.1U_0402_16V7K

1U_0402_6.3V6K

DP_VDDC MarsCRB Design

0.1u 1 1 1u 1 1 10u 1 1

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ATI_Sun Pro_M2_PWR_GND

LA-8127P

20 51Tuesday, March 12, 2013

E

1.0

A

1

.5VGS

+

1

495

1

+

C1

@

1 1

VDDR1 MarsCRB Design

0.01u 5 0

0.1u 5 5 1u 0 5

2.2u 5 0 10u 3 5 220u 0 1

VDD_CT MarsCR B Design 120ohm 1 1

0.1u 1 1 1u 1 3 10u 1 1

2 2

VDDR3 MarsCRB Design 120ohm 1 0

0.1u 1 0 1u 2 3 10u 0 1

VDDR4 MarsCRB Design 220ohm 1 1

0.1u 1 1 1u 1 1 10u 1 0

220U_B2_2.5VM_R35

C1496

2

DIS@ C1496

DIS@

10U_0603_6.3V6M

1

C1503

2

DIS@ C1503

DIS@

10U_0603_6.3V6M

1

C1498

C1497

2

DIS@ C1498

DIS@

DIS@ C1497

DIS@

10U_0603_6.3V6M

+3VGS

+1.8VGS

C1499

C1504

2

1U_0402_6.3V6K

DIS@ C1499

DIS@

DIS@ C1504

DIS@

DIS@ L1409

DIS@

1 2

BLM15BD121SN1D_2P~D

L1410

1 2

MBK1608221YZF_2P

1

C1505

2

DIS@ C1505

DIS@

L1409

MARS@L1410

MARS@

1U_0402_6.3V6K

10U_0603_6.3V6M

for Sun Pro Ball name AD12,AF11,AF12,AF13,AF15,AG11,AG13,AG15 is NC

3 3

B

o

r GDDR5, MVDDQ = 1.5V

F

(VDDR1:1.5V@3A,GDDR5:1125MHz )

1

C1500

2

1U_0402_6.3V6K

DIS@ C1500

DIS@

1

C1506

C1507

2

1U_0402_6.3V6K

DIS@ C1506

DIS@

DIS@ C1507

DIS@

1

C1501

C1509

C1508

C1510

2

.1U_0402_16V7K

DIS@ C1501

DIS@

.1U_0402_16V7K

DIS@ C1509

DIS@

DIS@ C1508

DIS@

DIS@ C1510

DIS@

+VDDC_CT+1.8VGS

(VDD_CT:1.8V@13mA )

1

C1532

C1533

2

1U_0402_6.3V6K

DIS@ C1533

DIS@

DIS@ C1532

DIS@

10U_0603_6.3V6M

1

C1536

C1534

C1535

2

.1U_0402_16V7K

1U_0402_6.3V6K

DIS@ C1536

DIS@

DIS@ C1534

DIS@

DIS@ C1535

DIS@

(VDDR3:3.3V@25mA)

1

C1537

2

DIS@ C1537

DIS@

1

C1540

C1538

C1539

2

1U_0402_6.3V6K

DIS@ C1540

DIS@

DIS@ C1538

DIS@

DIS@ C1539

DIS@

( VDDR4:1.8V@300mA)

1

C1553

C1554

2

1U_0402_6.3V6K

.1U_0402_16V7K

MARS@ C1553

MARS@

MARS@ C1554

MARS@

Route as differential pair

VCCSENSE_VGA[44]

VSSSENSE_VGA[44]

1

2

.1U_0402_16V7K

+VDDR3

+VDDR4

C

U

401E

1

P

ART 5 0F 9

MEM I/O

C

7

A

V

DR1

D

11

A

D

DR1

V

A

F7

V

DR1

D

A

10

G

1

C1502

2

DIS@ C1502

DIS@

AG26 AG27

AG23 AG24

AD12

AG11 AG13 AG15

AG28

AH29

AF26 AF27

AF23 AF24

AF11 AF12 AF13

AF15

AF28

A

G G G G G G G H10

M11 N11

R11 U11

A

7

J K

8

A

9

L

1

4

1

7

1

0

2

3

2

6

2 2

9

J7

J9 K11 K13

K8 L12 L16 L21 L23 L26

L7

P7

U7

Y11

Y7

V

DR1

D

V

DR1

D

V

DR1

D D

DR1

V V

DR1

D

V

DR1

D

V

DR1

D

V

DR1

D

V

DR1

D

V

DR1

D

V

DR1

D VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL

LEVEL TRANSLATION

TRANSLATION

VDD_CT VDD_CT VDD_CT VDD_CT

I/O

VDDR3 VDDR3 VDDR3 VDDR3

DVP

VDDR4 VDDR4 VDDR4 VDDR4

VOLTAGE

SENESE

FB_VDDC

FB_VDDCI

FB_GND

S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39DIS@

PCIE

BACO

CORE

N

_BIF_VDDC

C

N

_BIF_VDDC

C

P

C

P P P P PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

CORE I/O

ISOLATED

IE_PVDD

IE_VDDC

C C

IE_VDDC IE_VDDC

C

IE_VDDC

C

BIF_VDDC BIF_VDDC

N

C

N

C C

N N

C

N

C

N

C

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

(PCIE_VDDR:1.8V@100mA )

+

CIE_VDDR

P

A

31

A

32

A A

33

A

34

A

W

0

3

1

Y V

8

2

W

9

2

A

37

B

G

0

3

P

CIE_VDDC

+

G

1

3

H

9

2 3

0

H J29 J30 L28 M28 N28 R28 T28 U28

N27

+0.95VGS

T27

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18

AH22 AH27 AH28 M26 N24 R18 R21 R23 R26 T17 T20 T22 T24 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

1

C1489

C1490

2

.1U_0402_16V7K

DIS@ C1489

DIS@

DIS@ C1490

DIS@

1

C1492

C1491

C1493

2

1U_0402_6.3V6K

DIS@ C1492

DIS@

DIS@ C1491

DIS@

DIS@ C1493

DIS@

1

(PCIE_VDDC:0.95V@2.5A_GEN3.0 )

1

C1512

C1514

C1513

C1511

2

1U_0402_6.3V6K

DIS@ C1512

DIS@

DIS@ C1514

DIS@

DIS@ C1513

DIS@

DIS@ C1511

DIS@

(BIF_VDDC:0.95V@1.4A)

1

C1518

C1517

2

1U_0402_6.3V6K

DIS@ C1518

DIS@

DIS@ C1517

DIS@

1

C1524

2

1U_0402_6.3V6K

DIS@ C1524

DIS@

1

C1541

2

1U_0402_6.3V6K

DIS@ C1541

DIS@

+VGA_CORE

1

C1555

2

DIS@ C1555

DIS@

22U_0603_6.3V6M

1

C1526

C1525

C1519

2

1U_0402_6.3V6K

DIS@ C1526

DIS@

DIS@ C1525

DIS@

DIS@ C1519

DIS@

1

C1544

C1542

C1543

2

1U_0402_6.3V6K

DIS@ C1544

DIS@

DIS@ C1542

DIS@

DIS@ C1543

DIS@

1

C1556

2

DIS@ C1556

DIS@

1

C1523

2

1U_0402_6.3V6K

DIS@ C1523

DIS@

1U_0402_6.3V6K

10U_0603_6.3V6M

(VDDCI:0.9~1.15V@8.8A)

1

C1558

C1557

2

1U_0402_6.3V6K

DIS@ C1558

DIS@

DIS@ C1557

DIS@

1

C1561

C1560

C1559

2

1U_0402_6.3V6K

DIS@ C1561

DIS@

DIS@ C1560

DIS@

DIS@ C1559

DIS@

1

C1494

2

DIS@ C1494

DIS@

10U_0603_6.3V6M

1

C1515

2

@ C1515

@

1U_0402_6.3V6K

1

C1545

2

1U_0402_6.3V6K

DIS@ C1545

DIS@

1U_0402_6.3V6K

DIS@

MBK1608121YZF_0603

+

.95VGS

0

1

C1516

2

DIS@ C1516

DIS@

10U_0603_6.3V6M

1

C1528

C1527

2

1U_0402_6.3V6K

DIS@ C1528

DIS@

DIS@ C1527

DIS@

1

C1547

C1546

2

1U_0402_6.3V6K

DIS@ C1547

DIS@

DIS@ C1546

DIS@

1

C1562

C1563

2

1U_0402_6.3V6K

DIS@ C1562

DIS@

DIS@ C1563

DIS@

D

1

.8VGS

+

1

408

L

12

+0.95VGS

+VGA_CORE

1

C1520

2

DIS@ C1520

DIS@

1U_0402_6.3V6K

1

C1564

2

DIS@ C1564

DIS@

1

C1521

1U_0402_6.3V6K

DIS@ C1521

DIS@

1

C1550

2

DIS@ C1550

DIS@

C1567

DIS@ C1567

DIS@

10U_0603_6.3V6M

C1522

2

1U_0402_6.3V6K

DIS@ C1522

DIS@

+VGA_CORE

1

C1551

2

1U_0402_6.3V6K

DIS@ C1551

DIS@

+VGA_CORE

1

C1568

2

DIS@ C1568

DIS@

22U_0603_6.3V6M

1

C1531

2

1U_0402_6.3V6K

DIS@ C1531

DIS@

1

C1552

2

1U_0402_6.3V6K

DIS@ C1552

DIS@

C1529

C1530

2

1U_0402_6.3V6K

DIS@ C1529

DIS@

DIS@ C1530

DIS@

1

C1548

C1549

2

1U_0402_6.3V6K

DIS@ C1548

DIS@

DIS@ C1549

DIS@

1

C1565

C1566

2

1U_0402_6.3V6K

DIS@ C1565

DIS@

DIS@ C1566

DIS@

P

IE_VDDR MarsC RB Design

C

0.1u 0 2 1u 2 3 10u 1 1

PCIE_VDDC Mar sCRB Design 1u 7 5 10u 2 1

E

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

ATI_Sun Pro_M2_Power

LA-8127P

E

21 51Tuesday, March 12, 2013

1.0

A

U

401H

1

P

ART 3 0F 9

GDDR5/DDR3

Q

A0_0

D

Q

A0_1

D D

A0_2

Q Q

A0_3

D

Q

A0_4

D D

A0_5

Q Q

A0_6

D D

A0_7

Q

D

A0_8

Q

D

A0_9

Q

D

A0_10

Q Q

A0_11

D D

A0_12

Q

D

A0_13

Q

D

A0_14

Q

D

A0_15

Q

D

A0_16

Q

D

A0_17

Q

D

A0_18

Q DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MVREFDA MVREFSA

NC NC NC

MEM_CALRP0

NC NC

GDDR5/DDR3

MEMORY INTERFACE A

M M M M M M M M M

M M M M

M

A

M

A

M

A

W

KA0_0/DQMA_0

C

W

KA0B_0/DQMA_1

C

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

EDCA0_0/QSA_0 EDCA0_1/QSA_1 EDCA0_2/QSA_2 EDCA0_3/QSA_3 EDCA1_0/QSA_4 EDCA1_1/QSA_5 EDCA1_2/QSA_6 EDCA1_3/QSA_7

DDBIA0_0/QSA_0B DDBIA0_1/QSA_1B DDBIA0_2/QSA_2B DDBIA0_3/QSA_3B DDBIA1_0/QSA_4B DDBIA1_1/QSA_5B DDBIA1_2/QSA_6B DDBIA1_3/QSA_7B

ADBIA0/ODTA0

ADBIA1/ODTA1

MAA0_8/MAA_13 MAA1_8/MAA_14 MAA0_9/MAA_15

MAA1_9/RSVD

S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39DIS@

A

A0_0/MAA_0

A

A0_1/MAA_1 A0_2/MAA_2

A A

A0_3/MAA_3

A

A0_4/MAA_4 A0_5/MAA_5

A A

A0_6/MAA_6 A0_7/MAA_7

A

A1_0/MAA_8

A

A1_1/MAA_9

A

A1_2/MAA_10

A A

A1_3/MAA_11 A1_4/MAA_12

A

A1_5/MAA_BA2 A1_6/MAA_BA0 A1_7/MAA_BA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B RASA1B

CASA0B CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

2

4

G

2

3

J H

4

2

4

J H

6

2

6

J

2

1

H G

1

2

H

9

1

H

0

2 1

3

L G

6

1

J

6

1

H

6

1

J

7

1

H

7

1

A

2

3 3

2

C D23 E22 C14 A14 E10 D9

C34 D29 D25 E20 E16 E12 J10 D7

A34 E30 E26 C20 C16 C12 J11 F8

J21 G19

H27 G27

J14 H14

K23 K19

K20 K17

K24 K27

M13 K16

K21 J20

K26 L15

H23 J19 M21 M20

3

7

C

3

5

C A

5

3 3

4

E G

2

3 3

3

D

3

2

F E

2

3

D

1

3

F

0

3 3

0

C A

0

3

F

8

2

C

8

AG12

AH12

2

A

8

2

E

8

2

D

7

2

F

6

2 2

6

C A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13

J13 H11 G10

G8 K9

K10

G9 A8 C8 E8 A6 C6 E6 A5

L18

L20

L27 N12

M27

M12

1 1

2 2

SDV/FVT, NO.11

1 2

R1470 120_0402_1%DIS@R1470 120_0402_1%DIS@

SDV/FVT, NO.11

S

DV/FVT, NO.4

B

M

A[0..63]

D

M

A[0..14]

A

BA[0..2]

_

DQMA#[0..7]

QSA[0..7]

QSA#[0..7]

C

M

A[0..63] [23]

D

M

A[0..14] [23]

A

A_BA[0..2] [23]

DQMA#[0..7] [23]

QSA[0..7] [23]

QSA#[0..7] [23]

D

M M

D

M

D

M

D

M

D

M

D

M

D

M

D

M

D

M

D

M

D D

M M

D D

M

D

M M

D D

M M

D MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

+VDD_MEM15_REFDA +VDD_MEM15_REFSA

D

U

401I

1

P

ART 4 0F 9

GDDR5/DDR3

D

B0_0

Q

D

B0_1

Q

D

B0_2

Q Q

B0_3

D D

B0_4

Q

D

B0_5

Q Q

B0_6

D D

B0_7

Q

D

B0_8

Q

D

B0_9

Q

D

B0_10

Q

D

B0_11

Q

D

B0_12

Q

D

B0_13

Q

D

B0_14

Q Q

B0_15

D D

B0_16

Q

D

B0_17

Q DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 DQB0_25 DQB0_26 DQB0_27 DQB0_28 DQB0_29 DQB0_30 DQB0_31 DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8 DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31

MVREFDB MVREFSB

GDDR5/DDR3

MEMORY INTERFACE B

M M M

W

KB0_0/DQMB_0

C

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

EDCB0_0/QSB_0 EDCB0_1/QSB_1 EDCB0_2/QSB_2 EDCB0_3/QSB_3 EDCB1_0/QSB_4 EDCB1_1/QSB_5 EDCB1_2/QSB_6 EDCB1_3/QSB_7

DDBIB0_0/QSB_0B DDBIB0_1/QSB_1B DDBIB0_2/QSB_2B DDBIB0_3/QSB_3B DDBIB1_0/QSB_4B DDBIB1_1/QSB_5B DDBIB1_2/QSB_6B DDBIB1_3/QSB_7B

MAB0_8/MAB_13 MAB1_8/MAB_14 MAB0_9/MAB_15

S IC 216-0841000 A0 SUN PRO M2 FCBGA 962P A39DIS@

A

B0_0/MAB_0

M M

B0_1/MAB_1

A A

B0_2/MAB_2

M

A

B0_3/MAB_3

M M

B0_4/MAB_4

A A

B0_5/MAB_5

M M

B0_6/MAB_6

A

M

B0_7/MAB_7

A

M

B1_0/MAB_8

A

M

B1_1/MAB_9

A

B1_2/MAB_10 B1_3/MAB_11

A

B1_4/MAB_12

A

M

B1_5/BA2

A

M

B1_6/BA0

A

M

B1_7/BA1

A

ADBIB0/ODTB0 ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B RASB1B

CASB0B CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

CKEB0 CKEB1

WEB0B WEB1B

MAB1_9/RSVD

DRAM_RST

P T P N N N U U Y W A A A A Y A

H H1 T3 T5 AE4 AF5 AK6 AK5

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

T7 W7

L9 L8

AD8 AD7

T10 Y10

W10 AA10

P10 L10

AD10 AC10

U10 AA11

N10 AB11

T8 W8 U12 V12

AH11

8 9 9

7 8 9 9 8

9

8

C

9

C

7

A

8

A 8

9

A

3

A

M M

A

M

A

M

A

M

A

M

A

M

A

M

A

M

A

M

A

M

A A

M M

A _

A

_

A

BA1

_

ODTA0 ODTA1

CLKA0 CLKA0#

CLKA1 CLKA1#

RASA0# RASA1#

CASA0# CASA1#

CSA0#_0

CSA1#_0

CKEA0 CKEA1

WEA0# WEA1#

MAA13 MAA14

DRAM_RST#_R

5

C

A0

C

3

A1

3

E

A2

E

1

A3

1

F

A4

3

F

A5

F

5

A6

G

4

A7

H

5

A8

6

H

A9

J

4

A10

K

6

A11

K

5

A12

L

4

A13

M

6

A14

M

1

A15

M

3

A16

5

M

A17

N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3

Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6

AG4

AH5 AH6 AJ4 AK3 AF8 AF9

AG8 AG7

AK9 AL7

AM8 AM7

AK1 AL4

AM6 AM1

AN4 AP3 AP1 AP5

Y12

AA12

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 BA2 BA0

D

MA#0

Q DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7

QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7

QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7

E

ODTA0 [23] ODTA1 [23]

CLKA0 [23] CLKA0# [23]

CLKA1 [23] CLKA1# [23]

RASA0# [23] RASA1# [23]

CASA0# [23] CASA1# [23]

CSA0#_0 [23]

CSA1#_0 [23]

CKEA0 [23] CKEA1 [23]

WEA0# [23] WEA1# [23]

3 3

+1.5VGS

+1.5VGS +1.5VGS

12

R1473

40.2_0402_1%

DIS@

1

12

DIS@

R1477

100_0402_1%

4 4

DIS@

C1571

C1571 1U_0402_6.3V6K

1U_0402_6.3V6K

2

A

R1474

40.2_0402_1%

DIS@

R1478

100_0402_1%

DIS@

12

+VDD_MEM15_REFSA+VDD_MEM15_REFDA

1

12

DIS@

C1572

C1572 1U_0402_6.3V6K

1U_0402_6.3V6K

2

DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board to pass Reset Signal Spec. Place all these components very close to GPU (Within 25mm) and keep all component close to each Other (within 5mm) except Rser2

B

DRAM_RST#[23]

1 2

51.1_0402_1%

12

R1472

4.7K_0402_5%

@

DIS@

R1475

DIS@

1 2

10_0402_5%

1

DIS@

C1573

C1573 120P_0402_50V8

120P_0402_50V8

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

R1476

DRAM_RST#_R

DIS@

R1479

4.99K_0402_1%

1 2

Compal Secret Data

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

ATI_Sun Pro_M2_MEM IF

LA-8127P

E

22 51Tuesday, March 12, 2013

1.0

5

he Seymour M2 only support channel B (64 bit),

T this page unmount all parts

V V

D D

M

A[0..63][22]

D

MAA[14..0][22]

DQMA#[7..0][22]

QSA[7..0][22]

QSA#[7..0][22]

C C

CLKA0

R1484 40.2_0402_1%

CLKA0#

R1485 40.2_0402_1%

B B

CLKA1

R1494 40.2_0402_1%

CLKA1#

R1495 40.2_0402_1%

1 2

DIS@

1 2

DIS@

1 2

DIS@

1 2

DIS@

M

A[0..63]

D

MAA[14..0]

DQMA#[7..0]

QSA[7..0]

QSA#[7..0]

12

C1574

0.01U_0402_16V7K

DIS@

12

C1575

0.01U_0402_16V7K

DIS@

A_BA0[22] A_BA1[22] A_BA2[22]

CLKA0[22] CLKA0#[22] CKEA0[22]

ODTA0[22] CSA0#_0[22] RASA0#[22] CASA0#[22] WEA0#[22]

DRAM_RST#[22]

DIS@

R1480

243_0402_1%

QSA2 QSA0

DQMA#2 DQMA#0

QSA#2 QSA#0

U

405

1

M8

EFC_A1

R

V

EFCA

R

H1

EFD_Q1

R

V

EFDQ

R

N

3

M

A0

A

0

A

7

P

M

A1

A

1

3

P

M

A2

A

2

N

M

A3

A

3

8

P

M

A4

A

4

2

P

A

A5

M

A

5

R

8

M

A6

A

6

A

2

R

A

A7

M

A

7

8

T

A

A8

M

A

8

R

3

M

A9

A

9

A

L7

A

A10

M

A

0/AP

1

R7

M

A11

A

1

A

N7

MAA12

A12

T3

MAA13

A13

T7

MAA14

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J

7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

12

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

+1.5VGS +1.5VGS

12

DIS@

R1486

4.99K_0402_1%

12

DIS@

R1496

4.99K_0402_1%

DIS@

12

C1576

4

U

406

1

E3

M

A19

D

L0

Q

F7

M

A20

D

L1

Q

F2

M

A21

D

L2

Q

F8

M

A16

D

Q

L3

D

H3

M

A23

D

L4

Q

H8

M

A17

D

L5

Q

G2

M

A22

D

L6

Q

H7

M

A18

D

L7

Q

D7

D

A0

M

D

U0

Q

C3

D

A4

M

D

U1

Q

C8

M

A1

D

Q

U2

D

C2

D

A7

M

D

U3

Q

A7

M

A3

D

Q

U4

D

A2

DQU5

B8

MDA2

DQU6

A3

MDA5

DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VREFD_Q1 VREFD_Q2

.1U_0402_16V7K

+1.5VGS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VGS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9

VSS

B3

VSS

E1

VSS

G8

VSS

J2

VSS

J8

VSS

M1

VSS

M9

VSS

P1

VSS

P9

VSS

T1

VSS

T9

VSS

B1 B9 D1 D8 E2 E8 F9 G1 G9

4.99K_0402_1%

DIS@

R1487

DIS@

R1497

DIS@

R1481

243_0402_1%

+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS

12

VREFC_A1 VREFC_A2

12

.1U_0402_16V7K

12

C1577

DIS@

M8

V

EFC_A2

R

H1

V

EFD_Q2

R

N

3

M

A0

A

7

P

M

A1

A

3

P

M

A2

A

2

N

M

A3

A

8

P

M

A4

A

2

P

A

A5

M

R

8

M

A6

A

2

R

A

A7

M

8

T

A

A8

M

R

3

M

A9

A

L7

A

A10

M

R7

M

A11

A

N7

MAA12 MAA12 MAA12

T3

MAA13 MAA13 MAA13

T7

MAA14 MAA14 MAA14

M7

M2

A_BA0 A_BA0 A_BA0

N8

A_BA1 A_BA1 A_BA1

M3

A_BA2 A_BA2 A_BA2

J

7

CLKA0

K7

CLKA0#

K9

CKEA0 CKEA1

K1

ODTA0 ODTA1

L2

CSA0#_0 CSA1#_0

J3

RASA0# RASA1#

K3

CASA0# CASA1#

L3

WEA0# WEA1#

F3

QSA3 QSA4

C7

QSA1

E7

DQMA#3 DQMA#4

D3

DQMA#1

G3

QSA#3 QSA#4

B7

QSA#1

T2

DRAM_RST# DRAM_RST# DRAM_RST#

L8

12

J1 L1 J9 L9

K4W1G1646E-HC12_FBGA96

X76@

R1488

4.99K_0402_1%

DIS@

R1498

4.99K_0402_1%

DIS@

V

EFCA

R

V

EFDQ

R

0

A A

1

A

2

A

3

A

4

A

5 6

A A

7

A

8 9

A A

0/AP

1 1

1

A A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET

ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

12

DIS@

D

L0

Q

D

L1

Q

D

L2

Q Q

L3

D D

L4

Q

D

L5

Q

D

L6

Q

D

L7

Q

D

U0

Q

D

U1

Q Q

U2

D D

U3

Q Q

U4

D DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

.1U_0402_16V7K

12

C1578

E3

M

F7

M

F2

M

F8

M

H3

M

H8

M

G2

M

H7

M

D7

M

C3

M

C8

M

C2

M

A7

M

A2

MDA9MDA6

B8

MDA14

A3

MDA8

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

4.99K_0402_1%

DIS@

D D D D D D D D

D D D D D

R1489

DIS@

R1499

A27 A31 A25 A29 A26 A30 A24 A28

A15 A11 A12 A10 A13

3

+1.5VGS

12

243_0402_1%

C1579

DIS@

CLKA1[22] CLKA1#[22] CKEA1[22]

ODTA1[22] CSA1#_0[22] RASA1#[22] CASA1#[22] WEA1#[22]

12

DIS@

R1482

.1U_0402_16V7K

12

V

R

V

R

EFC_A3 EFD_Q3

QSA5

DQMA#5

QSA#5

M

A0

A

M

A1

A

M

A2

A

M

A3

A

M

A4

A A

A5

M M

A6

A A

A7

M

A

A8

M M

A9

A A

A10

M M

A11

A

4.99K_0402_1%

U

407

1

M8

V

EFCA

R

H1

V

EFDQ

R

N

3

0

A

7

P

A

1

3

P

A

2

N

A

3

8

P

A

4

2

P

A

5

R

8

6

A

2

R

A

7

8

T

A

8

R

3

9

A

L7

A

0/AP

1

R7

1

A

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J

7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

12

R1490

DIS@

12

R1500

DIS@

C1580

12

D

L0

Q

D

L1

Q

D

L2

Q Q

L3

D D

L4

Q

D

L5

Q

D

L6

Q

D

L7

Q

D

U0

Q

D

U1

Q Q

U2

D D

U3

Q Q

U4

D DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VREFC_A3

.1U_0402_16V7K

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

R1491

4.99K_0402_1%

DIS@

R1501

4.99K_0402_1%

DIS@

M

D

M

D

M

D

M

D

M

D

M

D

M

D

M

D

M

D

M M

D D

M M

D MDA42 MDA46 MDA43

12

A35 A37 A32 A39 A34 A36 A33 A38

A45 A41 A47 A40 A44

+1.5VGS

2

243_0402_1%

C1581

DIS@

12

DIS@

R1483

VREFD_Q3

.1U_0402_16V7K

12

V V

EFC_A4

R

EFD_Q4

R

CLKA1 CLKA1#

QSA6 QSA7

DQMA#6 DQMA#7

QSA#6 QSA#7

M

A0

A

M

A1

A

M

A2

A

M

A3

A

M

A4

A A

A5

M M

A6

A A

A7

M

A

A8

M M

A9

A A

A10

M M

A11

A

4.99K_0402_1%

U

408

1

M8

V

EFCA

R

H1

V

EFDQ

R

N

3

0

A

7

P

A

1

3

P

A

2

N

A

3

8

P

A

4

2

P

A

5

R

8

6

A

2

R

A

7

8

T

A

8

R

3

9

A

L7

A

0/AP

1

R7

1

A

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J

7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4W1G1646E-HC12_FBGA96

X76@

12

R1492

DIS@

12

R1502

DIS@

C1582

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

12

D

L0

Q

D

L1

Q

D

L2

Q Q

L3

D D

L4

Q

D

L5

Q

D

L6

Q

D

L7

Q

D

U0

Q

D

U1

Q Q

U2

D D

U3

Q Q

U4

D DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VREFC_A4

.1U_0402_16V7K

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

R1493

4.99K_0402_1%

DIS@

R1503

4.99K_0402_1%

DIS@

M

D

M

D

M

D

M

D

M

D

M

D

M

D

M

D

M

D

M M

D D

M M

D MDA62 MDA58 MDA60

A53 A50 A52 A51 A55 A49 A54 A48

A56 A59 A63 A61 A57

12

+1.5VGS

DIS@

C1583

12

1

VREFD_Q4

.1U_0402_16V7K

+1.5VGS

585

584

584 C1

C1

.1U_0402_16V7K

DIS@

A A

DIS@

586

1

C1

2

.1U_0402_16V7K

DIS@

1

C1

2

.1U_0402_16V7K

DIS@

5

1

C1587

C1588

2

.1U_0402_16V7K

DIS@ C1587

DIS@

DIS@ C1588

DIS@

1

C1590

C1589

2

.1U_0402_16V7K

DIS@ C1590

DIS@

DIS@ C1589

DIS@

1

C1592

C1591

2

.1U_0402_16V7K

DIS@ C1592

DIS@

DIS@ C1591

DIS@

1

C1593

C1594

2

.1U_0402_16V7K

DIS@ C1593

DIS@

DIS@ C1594

DIS@

1

C1596

C1595

2

.1U_0402_16V7K

DIS@ C1596

DIS@

DIS@ C1595

DIS@

4

+1.5VGS

10U_0603_6.3V6M

+1.5VGS +1.5VGS

1

C1597

C1598

2

DIS@ C1597

DIS@

DIS@ C1598

DIS@

10U_0603_6.3V6M

1

C1600

C1599

2

DIS@ C1600

DIS@

DIS@ C1599

DIS@

10U_0603_6.3V6M

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

1

C1601

2

1U_0402_6.3V6K

DIS@ C1601

DIS@

Issued Date

1

C1602

C1603

2

1U_0402_6.3V6K

DIS@ C1602

DIS@

DIS@ C1603

DIS@

1

C1605

C1604

2

1U_0402_6.3V6K

DIS@ C1605

DIS@

DIS@ C1604

DIS@

2012/11/22 2015/11/22

1

C1607

C1606

2

1U_0402_6.3V6K

DIS@ C1607

DIS@

DIS@ C1606

DIS@

Compal Secret Data

1

C1608

C1609

2

1U_0402_6.3V6K

DIS@ C1608

DIS@

DIS@ C1609

DIS@

Deciphered Date

2

1

C1610

2

1U_0402_6.3V6K

DIS@ C1610

DIS@

1

C1611

2

1U_0402_6.3V6K

DIS@ C1611

DIS@

1

C1613

C1612

2

1U_0402_6.3V6K

DIS@ C1613

DIS@

DIS@ C1612

DIS@

1

C1614

C1615

2

1U_0402_6.3V6K

DIS@ C1614

DIS@

DIS@ C1615

DIS@

Title

ATI_Sun Pro_M2_VRAM_A

Size Document Number Rev

C

Date: Sheet of

1

C1618

C1619

2

1U_0402_6.3V6K

DIS@ C1618

DIS@

DIS@ C1619

DIS@

LA-8127P

1

C1620

2

1U_0402_6.3V6K

DIS@ C1620

DIS@

23 51Tuesday, March 12, 2013

1

C1617

C1616

2

1U_0402_6.3V6K

DIS@ C1617

DIS@

DIS@ C1616

DIS@

Compal Electronics, Inc.

1.0

5

he Mars Pro M2 only support channel B (64 bit)

T

DV/FVT, NO.4

S

D D

C C

4

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

ATI_Sun Pro_M2_VRAM_B

Size Document Number Rev

C

Date: Sheet of

LA-8127P

1

24 51Tuesday, March 12, 2013

1.0

5

4

3

2

1

C2

C2 101

101

2

C2

C2 111

111

3

mil30mil

0

+

0.1U_0402_16V4Z

1

C2107

2

0.1U_0402_16V4Z

Close to Pin7

+

3

D

1

2

VS_PS

P_V33

C2100

Close to Pin18

+SWR_VDD

0.1U_0402_16V4Z

1

C2108

2

+SWR_V12

1 2

L2103 0_0805_5%L2103 0_0805_5%

+

VS_PS

3

L

101

2

FBMA-L11-201209-221LMA30T_0805

L

102

2

FBMA-L11-201209-221LMA30T_0805

+

WR_V12

S

Reserved for EC programming ROM Need EC confirm

LVDS_HPD[7]

+1.2VS

100K_0402_5%

R2106

12

1 2

L

100

2

4.7UH_PG031B-4R7MS_1.1A_20%

1 2

R2171 1K_0402_1%R2171 1K_0402_1%

12

D

P_V33

+

12

+

WR_VDD

S

+

WR_LX

S

@

DP0_AUXP_C[7] DP0_AUXN_C[7]

DP0_TXP0_C[7] DP0_TXN0_C[7]

CSCL CSDA

R2107

12K_0402_1%

Change to 12Kohm 1% (DG ref.) 20101114

LVDS_HPD_C

1 2

P

art number: SA00004EU10

U2101

3

40mil

D

_V33

P

60mil

6

0

60mil60mil

13

W

S

18

P

V

12

mil

S

W

11

S

W

27

VCCK

7

DP_V12

2

AUX_P

1

AUX_N

5

LANE0P

6

LANE0N

9

CIICSCL1

10

CIICSDA1

32

HPD

8

DP_REXT

4

DP_GND

R_VDD

CC

R_LX R_VCCK

RTD2132S

Power

DP-IN

GPIO

LVDS

Other

EDID

ROM

RTD2132S-GR_QFN32_5X5

T

EC+

X

T

X

T

X

T

X

LVDS

T

X

TXE0+

TXE0-

GPIO(PWM OUT)

GPIO(Panel_VCC)

GPIO(PWM IN)

GPIO(BL_EN)

MIICSCL1

MIICDA1

MIICSCL0

MIICSDA0

GND

EEROM

EEROMEEROM

+

WR_VDD

S

R

169 10K _0402_5%

2

19 20

EC-

21

E2+

22

E2-

23

E1+

24

E1-

25 26

14 15 16 17

TL_BKOFF#_R

29 28

31

MIIC_SCL

30

MIIC_SDA

33

L

DS_ACLK [26]

V

L

DS_ACLK# [26]

V

L

DS_A2 [26]

V V

DS_A2# [26]

L

DS_A1 [26]

V V

DS_A1# [26]

L

LVDS_A0 [26] LVDS_A0# [26]

TL_INVT_PWM [26]

TL_ENVDD [26]

APU_INVT_PWM [9]

EDID_CLK [26] EDID_DATA [26]

M M

IC_SCL

I

IC_SDA

I

2

R

2

R

0_0402_5%

1 2

102

1 2

103

0_0402_5%

M

IC_SCL_R

I

M

IC_SDA_R

I

MIIC_SCL

21 Internal RAM support, pin31 PD to GND EEROM EEROM EEROM EEROM

A0

R2167 10K_0402_5%R2167 10K_0402_5%

A1

R2168 10K_0402_5%R2168 10K_0402_5%

WP

R2170 10K_0402_5%R2170 10K_0402_5%

EDID_DATA

EDID_CLK

8 7

P

W

6 5

32S-Ver E: External ROM, pin31 PU +3VS

1 2

R2108 4.7K_0402_5%R2108 4.7K_0402_5%

1 2

R2109 4.7K_0402_5%R2109 4.7K_0402_5%

12

U

100

2

A

V

C

0

C

A

W

1

P

C

2

L

S

A

D

N

A

D

S

G

CAT24C64WI-GT3_SO8

+3VS_PS

R2104

4.7K_0402_5%

1 2

@

R2105

4.7K_0402_5%

1 2

12

1 2 3 4

+3VS_PS

A

0 1

A A

2

3

VS

+

1 2

R

101 0_06 03_5%@

2

l

ose to Pin3

C

0.1U_0402_16V4Z

10U_0603_6.3V6M

D D

1

C2

C2 102

102

2

0.1U_0402_16V4Z

1

C2

C2 103

103

2

Close to L27

0.1U_0402_16V4Z

10U_0603_6.3V6M

1

C2

C2 104

104

2

106

1

C2

C2 105

105

2

22U_0603_6.3V6M

Close to Pin13

Close to L29

C C

0.1U_0402_16V4Z

22U_0603_6.3V6M

1

C2

C2 109

109

2

0.1U_0402_16V4Z

1

2

1

C2

C2 110

110

2

Close to Pin27

Vendor advise reserve it

1 2

R2100 0_0402_5%@R 2100 0_0402_5%@

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

TL_BKOFF#_R

+3VS_PS

BKOFF#[26,31]

+3VS_PS

2

Q2107A

@Q2107A

@

DMN66D0LDW-7_SOT363-6

2012/11/22 2015/11/22

1 2

R2160 0_0402_5%@R2160 0_0402_5%@

C2112

C2112 .1U_0402_16V7K

.1U_0402_16V7K

1 2

5

2

P

B

4

Y

1

A

G

U2104

3

MC74VHC1G08DFT2G_SC70-5

61

5

Q2107B

@Q2107B

@

DMN66D0LDW-7_SOT363-6

34

Compal Secret Data

Deciphered Date

SIT, NO.7

EC_SMB_DA2CSDA

EC_SMB_CK2CSCL

ENBKL [31]

TL_BKOFF# [26]

EC_SMB_DA2 [18,31,32,7]

EC_SMB_CK2 [18,31,32,7]

2

MIIC_SDA

CSCL

CSDA

TL_INVT_PWM

TL_ENVDD

TL_BKOFF#_R

Vendor Suggest 2011.08.15

+3VS

CSDA

CSCL

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

LVDS Translator - RTD2132S

1 2

R2110 4.7K_0402_5%R2110 4.7K_0402_5%

1 2

R2158 4.7K_0402_5%R2158 4.7K_0402_5%

1 2

R2159 4.7K_0402_5%R2159 4.7K_0402_5%

1 2

R2163 100K_0402_5%R2163 100K_0402_5%

1 2

R2164 100K_0402_5%R2164 100K_0402_5%

1 2

R2165 100K_0402_5%R2165 100K_0402_5%

R2177 10K_0402_5%@R2177 10K_0402_5%@

R2178 10K_0402_5%@R2178 10K_0402_5%@

12

@

R2117 0_0402_5%

@

R2116 0_0402_5%

LA-8127P

1

25 51Tuesday, March 12, 2013

SIT, NO.7

TL_DATA [31]

TL_CLK [31]

of

1.0

1

LCD POWER CIRCUIT

2

3

4

5

+

LCD/LED PANEL Conn.

VS

D2101

3

W=60mils

1

C

114

2

4.7U_0805_10V4Z

2

31

2

AP2301GN-HF_SOT23-3

AP2301GN-HF_SOT23-3 Q2101

+LCDVDD

+3VS

12

Q2101

W=60mils

1 2

FBMA-L11-201209-221LMA30T_0805

L2104

R2118

@ R2118

@

4.7K_0402_5%

DISPOFF#

R2121

10K_0402_5%

+LCDVDD_CONN

C2120

0.1U_0402_16V4Z

1

2

C2119

4.7U_0805_25V6-K

1

2

+3VS_CMOS DMIC_CLK[29] DMIC_1_2[29]

LOGO RED LIGHT

+3VS Logo_LED#[31,35] +3VALW USB20_N6[14] USB20_P6[14] LVDS_ACLK[25] LVDS_ACLK#[25]

LVDS_A2[25] LVDS_A2#[25] LVDS_A1[25] LVDS_A1#[25] LVDS_A0[25] LVDS_A0#[25]

EDID_DATA[25] EDID_CLK[25] +3VS +LCDVDD_CONN

1

2

Place closed to JLVDS1

+

VS

3

1

2

+3VS

1 2

R2123 10K_0402_5%@R2123 10K_0402_5%@

1 2

C2121 220P_0402_50V7KC2121 220P_0402_50V7K

1 2

C2124 220P_0402_50V7KC2124 220P_0402_50V7K

1 2

C2122 10P_0402_50V8J@C2122 10P_0402_50V8J@

1 2

C2123 10P_0402_50V8J@C2123 10P_0402_50V8J@

C2115

0.1U_0402_16V4Z

1 2

R2122 0_0402_5%@R2122 0_0402_5%@

1 2

R2166 1.6K_0402_1%R2166 1.6K_0402_1%

+

EDVDD

L

DISPOFF# INVPWM

DMIC_CLK DMIC_1_2

Logo_LED#

USB20_N6 USB20_P6

EDID_DATA EDID_CLK

INVPWM

DISPOFF#

EDID_CLK

EDID_DATA

C2116

4.7U_0805_25V6-K

(20 MIL)

40 39 38 37 36 35 34 33 32 3 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 10

STARC_107K40-000001-G2

CONN@

1

2

JLCD1

40 39 38 37 36 35 34 33 32

1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12

1

11 10

9

8

7

6

5

4

3

2

1

3

1

1 2

1

C2117

@C2117

@

680P_0402_50V7K

2

SIT, NO.4

4

6

G6

45

G5

4

G4

43

G3

42

G2

4

1

G1

DISPOFF#INVPWM

2

D2100

@ D2100

@

PJSOT24C 3P C/A SOT-23

PN:SCA00001G00

B

+

2

1130_0805_5% @

R

L

5

CDVDD

VALW

+

12

13

D

S

2

G

12

1 2

R2161 0_0402_5%@R2161 0_0402_5%@

1 2

R2162 0_0402_5%@R2162 0_0402_5%@

12

100K_0402_5%

Q

100

2

G

2N7002K_SOT23-3

13

D

S

R

112

2

1 2

Q2102

2N7002K_SOT23-3

R2114

R2114 220K_0402_1%

220K_0402_1%

C2118

0.1U_0402_16V4Z

@ D2101

@

RB751V-40_SOD323-2

1 2

R2119 0_0402_5%R2119 0_0402_5%

12

R2120

@R2120

@

10K_0402_5%

R

111

2

150_0603_1%

A A

TL_ENVDD[25]

B B

C C

150_0603_1%

TL_ENVDD

R2115

@R2115

@

100K_0402_5%

BKOFF#[25,31]

TL_BKOFF#[25]

+3VS

12

R2175

4.7K_0402_5%

@

12

@

R2172

R2172 10K_0402_5%

10K_0402_5%

@

INVPWM

12

2

D2110

@ D2110

@

RB751V-40_SOD323-2

1 2

TL_INVT_PWM[25]

D D

1

R2173 0_0402_5%R2173 0_0402_5%

12

@

R2174

R2174 10K_0402_5%

10K_0402_5%

1 2

C2145 22P_0402_50V8JC2145 22P_0402_50V8J

1 2

C2144 22P_0402_50V8JC2144 22P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DMIC_CLK

DMIC_1_2

CMOS_ON#[31]

CMOS Camera Conn

CMOS@

Q2103

(20 MIL)

+3VALW

1

C2127

0.1U_0402_16V4Z

CMOS@

1 2

R2125

150K_0402_5%

2012/11/22 2015/11/22

2

1

C2128

0.1U_0402_16V4Z

CMOS@

2

Compal Secret Data

Deciphered Date

4

Q2103

3 1

AP2301GN-HF_SOT23-3

2

4.7V

(20 MIL)

CMOS SUSPEND 2. 4mA

CMOS@

C2125

0.1U_0402_16V4Z

1

2

Title

Size Document Number Rev

Custom

Date: Sheet of

+3VS_CMOS+3VS

CMOS@

1

C2126

10U_0603_6.3V6M

2

Compal Electronics, Inc.

LVDS CONN/CAMERA

LA-8127P

5

1.0

26 51Tuesday, March 12, 2013

1.0

5

4

3

2

1

R

H

MI_CLKP[7]

D

H

MI_CLKN[7]

D

H

MI_TX0P[7]

D

H

MI_TX0N[7]

D

H

MI_TX1P[7]

D

H

MI_TX1N[7]

D

H

MI_TX2P[7]

D

H

MI_TX2N[7]

D

D D

HDMI_CLKP

HDMI_CLKN

HDMI_TX0P

HDMI_TX0N

HDMI_TX1P

C C

HDMI_TX1N

HDMI_TX2P

HDMI_TX2N

R R

R

L2105

1

4

WCM-2012HS-900T_4P

L2106

1

4

WCM-2012HS-900T_4P

L2107

1

4

WCM-2012HS-900T_4P

L2108

1

4

WCM-2012HS-900T_4P

1 2

126 0_0402_5%@

2

1 2

127 0_0402_5%@

2

1 2

128 0_0402_5%@

2

1 2

129 0_0402_5%@

2

1 2

130 0_0402_5%@

2

1 2

131 0_0402_5%@

2

1 2

132 0_0402_5%@

2

1 2

133 0_0402_5%@

2

3

2

3

2

3

2

3

2

HDMI_CLK+_CONN

3

HDMI_CLK-_CONN

2

HDMI_TX0+_CONN

3

HDMI_TX0-_CONN

2

HDMI_TX1+_CONN

3

HDMI_TX1-_CONN

2

HDMI_TX2+_CONN

3

HDMI_TX2-_CONN

ESD Request

D2105

HDMI_CLK-_CONN

HDMI_CLK+_CONN

HDMI_TX1-_CONN

HDMI_TX1+_CONN HDM I_TX1+_CONN

B B

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_TX2-_CONN

HDMI_TX2+_CONN

HDMI_HPD HDMI_HPD

HDMICLK_R HDMICLK_R

A A

+5VS_HDMI +5VS_H DMI

1

2

4

5

3

8

YSCLAMP0524P_SLP2510P8-10-9

D2102

1

2

4

5

3

8

YSCLAMP0524P_SLP2510P8-10-9

D2103

1

2

4

5

3

8

YSCLAMP0524P_SLP2510P8-10-9

5

10

9

7

65

10

9

7

65

10

9

7

65

9

8

7

6

9

8

7

6

9

8

7

6

H

MI_CLK+_CONN

D

H

MI_CLK-_CONN

D

H

MI_TX0+_CONN

D

H

MI_TX0-_CONN

D

H

MI_TX1+_CONN

D

H

MI_TX1-_CONN

D

H

MI_TX2+_CONN

D

MI_TX2-_CONN

H

HDMI_CLK-_CONN

HDMI_CLK+_CONN

HDMI_TX1-_CONN

HDMI_TX0-_CONN

HDMI_TX0+_CONN

HDMI_TX2-_CONN

HDMI_TX2+_CONN

HDMIDAT_RHDMIDAT_R

HDMI_CLK+_CONN

HDMI_CLK-_CONN

HDMI_TX0+_CONN

HDMI_TX0-_CONN

HDMI_TX1+_CONN

HDMI_TX1-_CONN

HDMI_TX2+_CONN

HDMI_TX2-_CONN

R2134 604_0402_1%R2134 604_0402_1%

R2135 604_0402_1%R2135 604_0402_1%

R2136 604_0402_1%R2136 604_0402_1%

R2137 604_0402_1%R2137 604_0402_1%

R2138 604_0402_1%R2138 604_0402_1%

R2139 604_0402_1%R2139 604_0402_1%

R2140 604_0402_1%R2140 604_0402_1%

R2141 604_0402_1%R2141 604_0402_1%

NEAR CONNECTOR

4

1 2

+5VS

HDMI_DET[7]

HDMI_CLK[7]

13

D

Q2105

2

G

12

@

R2143

R2143 100K_0402_5%

100K_0402_5%

2N7002K_SOT23-3

S

+3VS

C

Q2106

3

Q2106

E

3 1

12

R2150

R2150 100K_0402_5%

100K_0402_5%

MMBT3904_NL_SOT23-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

R2148

2

1 2

B

150K_0402_5%

200K_0402_5%

2012/11/22 2015/11/22

HDMI_DATA[7]

HDMI_HPD

@

R2149

1 2

Compal Secret Data

Deciphered Date

1.1A_6V_SMD1812P110TF

R2146

2K_0402_5%

1 2

2

+3VS

2

61

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6 Q2104A

Q2104A

5

2N7002KDWH_SOT363-6

1 2

0_0402_5%

@

R2142

0_0402_5%@

R2144

+5VS_HDMI_F

21

F2100

+5VS_HDMI

R2147

R2147 2K_0402_5%

2K_0402_5%

HDMI_CLK-_CONN

HDMI_CLK+_CONN HDMI_TX0-_CONN

HDMI_TX0+_CONN HDMI_TX1-_CONN

HDMI_TX1+_CONN HDMI_TX2-_CONN

HDMI_TX2+_CONN

Q2104B

HDMI_HPD

HDMIDAT_R HDMICLK_R

HDMICLK_R

34

R2145

@R2145

@

0_0805_5%

1

2

Title

Size Document Number Rev

Custom

Date: Sheet of

3

2

RB491D-YS_SOT23-3

RB491D-YS_SOT23-3 D2104

D2104

C2129

0.1U_0402_16V4Z

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUYIN_100042GR019M23DZL

CONN@

Compal Electronics, Inc.

HDMI Connector

HDMIDAT_R

+5VS

20

GND

21

GND

22

GND

23

GND

LA-8127P

1

27 51Tuesday, March 12, 2013

1.0

A

D

C_RED

1 1

D

C_RED[1 3]

A

D

C_GRN[13]

A

DAC_BLU[13]

A

C_GRN

D

DAC_BLU

12

R2151

R2151 150_040 2_1%

150_040 2_1%

12

R2152

R2152 150_040 2_1%

150_040 2_1%

12

R2153

R2153 150_040 2_1%

150_040 2_1%

CLOSE TO CONN

+CRT_VC C

1

C2136

0.1U_040 2_16V4Z

2 2

CRT_HSYNC[13]

CRT_VSYNC[13]

3 3

CRT_DDC _DATA[13]

CRT_DDC _CLK[13]

4 4

0.1U_040 2_16V4Z

C2138

2

+CRT_VC C

1

2

R2154

1 2

1K_0402 _5%

5

1

U2102

P

4

OE#

A2Y

G

74AHCT1 G125GW_SO T353-5

3

R2155

1 2

1K_0402 _5%

5

1

U2103

P

4

OE#

A2Y

G

74AHCT1 G125GW_SO T353-5

3

1

2

10P_040 2_50V8J

CRT_HSYNC _1

CRT_VSYNC _1

R2156

4.7K_040 2_5%

100P_04 02_50V8J

B

1

C2130

2

+R_CRT_ VCC

12

@

C2141

FCM1608 CF-121T03_2P

1 2

L

FCM1608 CF-121T03_2P

1 2

L

FCM1608 CF-121T03_2P

1 2

L2111

1

C2131

C2132

C2132 10P_040 2_50V8J

10P_040 2_50V8J

2

10P_040 2_50V8J

1 2

L2112

FCM1608 CF-121T03_2P

1 2

L2113

FCM1608 CF-121T03_2P

12

R2157

4.7K_040 2_5%

CRT_DDC _DATA

CRT_DDC _CLK

1

@

C2142

C2142 68P_040 2_50V8J

68P_040 2_50V8J

2

109

110

2

1

C2133

2

10P_040 2_50V8J

1

2

1

2

1

C2134

2

10P_040 2_50V8J

JVGA_HS

@

C2137

C2137 10P_040 2_50V8J

10P_040 2_50V8J

JVGA_VS

@

C2139

C2139 10P_040 2_50V8J

10P_040 2_50V8J

C

R

D

E

R

EEN

G

BLUE

C2135

C2135 10P_040 2_50V8J

10P_040 2_50V8J

1 2

R2179 0_04 02_5%R2179 0_04 02_5%

1 2

R2180 0_04 02_5%R2180 0_04 02_5%

1 2

R2181 0_04 02_5%R2181 0_04 02_5%

1 2

R2182 0_04 02_5%R2182 0_04 02_5%

D

ESD Request

BLUE

+R_CRT_ VCC

CRT_DDC _DATA

+R_CRT_ VCC

CRT_DDC _CLK

D2107

6

I/O4

5

VDD

4

I/O3

AZC099-0 4S.R7G_SOT23-6

D2108

6

I/O4

5

VDD

4

I/O3

AZC099-0 4S.R7G_SOT23-6

+5VS

D2106

2

3

RB491D-YS_ SOT23-3

RED

CRT_DDC _DATA GREEN

JVGA_HS BLUE

JVGA_VS

CRT_DDC _CLK

E

3

I/O2

GND

I/O1

I/O2

GND

I/O1

RED

2

1

GREEN

3

JVGA_HS

2

1

JVGA_VS

CRT Connector

+R_CRT_ VCC

F2101

1

F2101

21

1.1A_6V_ SMD1812P110T F

W=40mils

1

C2143

100P_04 02_50V8J

2

1

C2140

0.1U_040 2_16V4Z

2

JCRT1

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

C-H_13-12 201558CP

CONN@

16 17

+CRT_VC C

Security Class ification

AMD check list update 20101110

A

B

Security Class ification

2012/11/ 22 2015/11/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/ 22 2015/11/22

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

CRT Connector

LA-8127P

28 51Tuesday, March 12, 201 3

E

1.0

1

C

X20671 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO).

A

n integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).

A A

PC Beep

B

EC Beep

ICH Beep

B B

PLUG_IN[35]

HDA_SYNC_AUDIO[14]

C C

EP#[31]

E

FCH_SPKR[14]

Combo Jack detect (normal close)

MIC_JD

13

D

S

PLUG_IN

CX_GPIO0

R1136 0_0402_5%R1136 0_0402_5%

D

102

1

RB751V-40_SOD323-2

1 2

1

111 0.1U_0402_16V4Z

C

@

C

@

1 2

C1141 0.1U_0402_16V4Z

@

C1141 0.1U_0402_16V4Z

@

D1101

RB751V-40_SOD323-2

Q1103

Q1103 LBSS138LT1G_SOT-23-3

LBSS138LT1G_SOT-23-3

2

G

+5VS

@

G

2

Q1104

Q1104 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

HDA_SYNC_AUDIO

D

S

D

S

1 2

12

R1120 33_0402_5%R1120 33_0402_5%

12

R1121

10K_0402_5%

1 2

R1130 33K_0402_5%R1130 33K_0402_5%

1

C1146

C1146 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1 2

R1129 33K_0402_5%

@

R1129 33K_0402_5%

@

1

C1147

C1147 1U_0402_6.3V6K

1U_0402_6.3V6K

@

2

1 2

EXT_MIC

potential leakage concern

Decoupling CAP

+CLASSD_5V

1 2

C1115 0.1U_0402_16V4ZC1115 0.1U_0402_16V4Z

1 2

C1117 10U_0603_6.3V6MC1117 10U_0603_6.3V6M

1 2

C1118 0.1U_0402_16V4ZC1118 0.1U_0402_16V4Z

1 2

C1120 10U_0603_6.3V6M

@

Near Pin 12

Near Pin 15

2

L

ayout Note:Path from +5VS to Pin12, Pin15 must be very low resistance (<0.01 ohms)

T

support Wake-on-Jack or Wake-on-Ring, the CODEC

o VAUX_3.3 & VDD_IO pins must be powerd by a rail that is not removed unless AC power is removed. *DSH page42 has more detail.

1 2

PC_BEEP_C PC_BEEP

0.1U_0402_16V4Z

0.1U_0402_16V4Z C1142

C1142

HDA_RST_AUDIO#[14]

HDA_BITCLK_AUDIO[14]

HDA_SDIN0[14] HDA_SDOUT_AUDIO[14]

EAPD[31] EC_MUTE#[31]

Internal DMIC

DMIC_CLK[26]

DMIC_1_2[26]

Internal SPEAKER

10K only needed if supply to VAUX_3.3 is removed during system re-start.

1 2

R1112 @ 4.7K_0402_5%R1112 @ 4.7K_0402_5%

1 2

R1115 33_0402_5%R1115 33_0402_5%

EAPD active low 0=power down ex AMP 1=power up ex AMP

1 2

R1111 0_0402_5%R1111 0_0402_5%

1 2

R1131 0_0402_5%@R1131 0_0402_5%@

1 2

R1138

FBMA-10-100505-301T_2P

1 2

R1139 0_0402_5%R1139 0_0402_5%

+

VS

3

0.1U_0402_16V4Z

C

0.1U_0402_16V4Z

1

C

C1132

3

12

121

1

12

116

12

HDA_RST#_AUDIO

HDA_BITCLK_AUDIO HDA_SYNC_AUDIO

HDA_SDOUT_AUDIO

PC_BEEP

CX_GPIO0

DMIC_CLK_R

DMIC_1_2_R

SPK_L2+ SPK_L1-

SPK_R2+ SPK_R1-

12

C

@

C

@

119

1

4.7U_0603_6.3V6K

N

ear Pin 2

12

1

114

@

114

@

C

1U_0402_6.3V6K

Near Pin 7

12

C1130

4.7U_0603_6.3V6K

Near Pin 3

FILT_1.8_R

U1101

9

RESET#

5

BIT_CLK

8

SYNC

6

SDATA_IN

4

SDATA_OUT

10

PC_BEEP

38

GPIO0/EAPD#

37

GPIO1/SPK_MUTE#

40

DMIC_CLK

1

DMIC_1/2

11

LEFT+

13

LEFT-

16

RIGHT+

14

RIGHT-

SPK_RT_Detect#[31]

3

7

FILT_1.8

GND

41

4

1 2

1

135 1U_0402_6.3V6K

C

1 2

C

136 0.1U_0402_16V4Z

1

1 2

1

133 4.7U_0603_6.3V6K

C

1 2

C

134 0.1U_0402_16V4Z

1

12

C1113

12

C1124

SENSE_A

PORTC_R PORTC_L

EXT_MIC

HP_OUTR_R HP_OUTL_R

AVEE FLY_P FLY_N

Rdc < 0.05 ohms Rated Current > 2A

29

18

2

VDD_IO

FILT_1.65

VAUX_3.3

DVDD_3.3

CX20671-21Z_QFN40_6X6

27

28

AVDD_3.3

I

LT_1.65_R

F

+

DO_OUT_3.3V

L

26

LPWR_5.0 RPWR_5.0

AVDD_5V

AVDD_HP CLASS-D_REF

SENSE_A

PORTB_R

PORTB_L

PORTC_R

PORTC_L

PORTA_R

PORTA_L

B_BIAS

C_BIAS

AVEE

FLY_P

FLY_N

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

12 15 17

36

35 34 33

32 31 30

23 22

24

NC

2

5

NC

39

NC

21 19 20

Width 20 mil

SPK_R1SPK_R2+ SPK_L1- SPK_L1-_CONN SPK_L2+ SPK_L2+_CONN

1 2

L1102 0_0603_5%L1102 0_0603_5%

1 2

L1103 0_0603_5%L1103 0_0603_5%

1 2

L1104 0_0603_5%L1104 0_0603_5%

1 2

L1105 0_0603_5%L1105 0_0603_5%

1 2

R1140 0_0402_5%R1140 0_0402_5%

Near Pin 29

Near Pin 27

+

VS

5

12

C1112

@

C1112

@

4.7U_0603_6.3V6K

Near Pin 28

+3VS

12

C1129

@

C1129

@

0.1U_0402_16V4Z

Near Pin 26

Near Pin 17

1 2

C1107 0.1U_0402_16V4ZC1107 0.1U_0402_16V4Z

1 2

R1113 5.11K_0402_1%R1113 5.11K_0402_1%

1 2

R1114 20K_0402_1%R1114 20K_0402_1%

1 2

R1116 39.2K_0402_1%R1116 39.2K_0402_1%

1 2

C1108 2.2U_0603_6.3V6KC1108 2.2U_0603_6.3V6K

1 2

R1132 2K_0402_5%R1132 2K_0402_5%

1 2

R1117 39_0402_5%R1117 39_0402_5%

1 2

R1118 39_0402_5%R1118 39_0402_5%

Changed from 5.1ohm to 15ohm for "zi zi"noise.

1 2

C1110 1U_0603_10V4ZC1110 1U_0603_10V4Z

+MICBIASB

Internal Speaker

SPK_R1-_CONN SPK_R2+_CONN

SPK_RT_Detect#_RSPK_RT_Detect#

EMI

GND GNDA

+CLASSD_5V

MIC_JD PLUG_IN

1 2

R1133 100_0402_1%R1133 100_0402_1%

1 2

R1128 4.7K_0402_5%R1128 4.7K_0402_5%

HP_OUTR HP_OUTL

@

C1137

1

2

1 2

R1137 0_0805_5%R1137 0_0805_5%

+3VS

+MICBIASB

HP_OUTR [35] HP_OUTL [35]

1 2

C1122 0.1U_0402_16V4ZC1122 0.1U_0402_16V4Z

1 2

C1125 4.7U_0603_6.3V6KC1125 4.7U_0603_6.3V6K

@

C1138

C1139

1000P_0402_50V7K

1

2

5

EMI

1 2

1

102 0.1U_0402_16V4Z@

C

1 2

C

103 0.1U_0402_16V4Z@

1

1 2

C

104 0.1U_0402_16V4Z@

1

1 2

R

@

R

@

102 0_0402_5%

1

1 2

R

104 0_0402_5%@

1

1 2

R

105 0_0402_5%@

1

GND

Sense resistors must be connected same power that is used for VAUX_3.3

Port B Port A

External MIC

EXT_MIC

Headphone

@

C1140

1000P_0402_50V7K

1

2

+5VS+3VS

EXT_MIC [35]

Near Pin 21

1 2 3 4 5 6

7 8

E-T_4070K-G06N-00L

JSPK1

1 2 3 4 5 6

GND GND

CONN@

Note.

D D

HDA_RST#_AUDIO

HDA_SYNC_AUDIO

HDA_SDOUT_AUDIO

HDA_BITCLK_AUDIO HDA_BITCLK_AUDIO_R

1 2

R1123 33_0402_5%@R1123 33_0402_5%@

1

EMI

C1123 22P_0402_50V8J@C1123 22P_0402_50V8J@

C1126 22P_0402_50V8J@C1126 22P_0402_50V8J@

C1128 22P_0402_50V8J@C1128 22P_0402_50V8J@

C1131 22P_0402_50V8J@C1131 22P_0402_50V8J@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

4

Title

Size Document Number Rev

Custom

Date: Sheet of

QALEA 14" => JSPK1 => 4Pin QALEB 15" => JSPK1 => 6Pin

Compal Electronics, Inc.

HD Audio Codec CX20671

LA-8127P

5

29 51Tuesday, March 12, 2013

1.0

A

B

C

D

E

F

G

H

SATA HDD Conn.

J

DD1

H

1

G

D

N

S

TA_FTX_DRX_P0

S

TA_FTX_DRX_P0[13]

A

S

TA_FTX_DRX_N0[13]

A

TA_FRX_C_DTX_N0[13]

S

A

TA_FRX_C_DTX_P0[13]

1 1

S

HDD_DETECT#[31]

+5VS_HDD

@

1000P_0402_50V7K

C2405

1

2

1 2

C

401 0.01U_0402_16V7K

2

1 2

C

402 0.01U_0402_16V7K

2

@

10U_0603_6.3V6M

1U_0603_10V4Z

C2406

C2471

1

2

A

S

TA_FTX_DRX_N0

A

S

TA_FRX_DTX_N0

A A

TA_FRX_DTX_P0

S

+

VS

3

+5VS_HDD

2

A

+

3

A

-

4

G

D

N

5

B

-

6

B

+

7

N

D

G

8

3

V

9

V

3

10

V

3

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

SANTA_198202-1

CONN@

GND GND

+

VS

5

23 24

J

401@

2

112

JUMP_43X79

2

+

VS_HDD

5

2 2

SATA ODD Conn.

JODD2

SATA_FTX_DRX_P1[13] SATA_FTX_DRX_N1[13]

SATA_FRX_C_DTX_N1[13] SATA_FRX_C_DTX_P1[13]

ODD_DETECT#[14]

+5VS_ODD

ODD_DA#_FCH[14]

3 3

SATA_FRX_C_DTX_N1 SATA_FRX_C_DTX_P1 SATA_FRX_DTX_P1

+5VS_ODD

R2437 0_0402_5%@R 2437 0_0402_5%@

1 2

C2408 0.01U_0402_16V7KC2408 0.01U_0402_16V7K

1 2

C2409 0.01U_0402_16V7KC2409 0.01U_0402_16V7K

1 2

R2406 0_0402_5%@R 2406 0_0402_5%@

1 2

R2401 0_ 0402_5%

@

R2401 0_ 0402_5%

@

1 2

SATA_FTX_DRX_P1 SATA_FTX_DRX_N1

SATA_FRX_DTX_N1

ODD_DETECT#_R

ODD_DA#_R

SATA_FTX_DRX_P1 SATA_FTX_DRX_N1

SATA_FRX_DTX_N1 SATA_FRX_DTX_P1

ODD_DETECT#_R +5VS_ODD

ODD_DA#_R

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_88514-104N

CONN@

Note. QALEA 14" => JO DD1 QALEB 15" => JO DD2

10K_0402_5%

ODD_EN[13]

2

APS G-Sensor

12

R2402

R2402 100K_0402_5%

100K_0402_5%

U2406

.1U_0402_16V7K

C2410

1

2

B

2

ST

14

Vs

15

Vs

3

COM

5

COM

6

COM

7

COM

LIS34ALTR LGA 16P G-SENSOR

@ J2402

@

2MM

GS_SELFTEST[31] GS_VOUTX [31]

+3VS +3VS_GS

1 2

R2405 0_0 603_5%

@

R2405 0_0 603_5%

@

4 4

te.

No Main Source => C2417 use 10U ( SE000005T80) 2nd Source => C 2417 use 10K (S D013100280)

A

10U_0603_6.3V6M

C2417

1

2

APS_GND

J2402

Xout Yout Zout

21

12

VOUTX

10

VOUTY

8

C2411

1

NC

4

NC

9

NC

11

NC

13

NC

16

NC

APS_GND

1

2

APS_GND

C

1 2

R2403 56K_0402_5%R2403 56K_0402_5%

1 2

R2404 56K_0402_5%R2404 56K_0402_5%

.1U_0402_16V7K

C2418

1

2

150K_0402_5%

GS_VOUTY [31]

.1U_0402_16V7K

C2412

C2416

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

D

GS_ON#[31]

2012/11/22 2015/11/22

E

GS_ON#

Compal Secret Data

150K_0402_5%

R2410

1 2

150K_0402_5%

Deciphered Date

ODD Power Control

R2438

IN

@

R2411

+5VS

+3VS

F

12

R2440

1 2

1

100K_0402_5%

OUT

Q2410

Q2410 DDTC124EKA-7-F_SC59-3

DDTC124EKA-7-F_SC59-3

GND

3

12

1

@

C2421

0.01U_0402_16V7K

2

AP2301GN-HF_SOT23-3

3 1

J4

@

2

112

JU

MP_43X79

Q2411

2

C2413 0.01U_0402_16V7KC2413 0.01U_0402_16V7K

3 1

2

1

C2420

0.01U_0402_16V7K

2

C2486

0.01U_0402_16V7K

1 2

Q2402

Q2402 AP2301GN-HF_SOT23-3

AP2301GN-HF_SOT23-3

1

C2419

0.1U_0402_16V4Z

2

Title

Size Document Number Rev

B

Date: Sheet of

+5VS_ODD

1

2

Compal Electronics, Inc.

G

1

C2501

C2501 10U_0805_10V4Z

10U_0805_10V4Z

2

12

R2409

@

0_0603_5%

1

C2487

10U_0603_6.3V6M

@

2

HDD/ODD/G-Sensor

LA-8127P

+3VS_GS

1.0

30 51Tuesday, March 12, 2013

H

1.0

1

1 2

00 0_0603_5%@

L22

+3V

A A

+3VALW_EC

B B

+3VALW

1 2

R2212 47K_0402_5%@R2212 47K_0402_5%@

1 2

R2213 47K_0402_5%@R2213 47K_0402_5%@

1 2

R2214 2.2K_0402_5%R2214 2.2K_0402_5%

1 2

R2215 2.2K_0402_5%R2215 2.2K_0402_5%

+3VS

1 2

R2236 100K_0402_5%@R2236 100K_0402_5%@

1 2

R2235 10K_0402_5%@R2235 10K_0402_5%@

C C

+3VALW

1 2

R2217 2.2K_0402_5%R2217 2.2K_0402_5%

1 2

R2218 2.2K_0402_5%R2218 2.2K_0402_5%

1 2

C2220 100P_0402_50V8J@C2220 100P_0402_50V8J@

1 2

C2219 100P_0402_50V8J@C2219 100P_0402_50V8J@

+3VS

1 2

R2227 2.2K_0402_5%@R2227 2.2K_0402_5%@

1 2

R2226 2.2K_0402_5%@R2226 2.2K_0402_5%@

D D

L22

ALW_EC

1 2

01 0_0603_5%@

L22

1 2

C2209 @ 22P_0402_50V8JC2209 @ 22P_0402_50V8J

1 2

R2203 330K_0402_5%R2203 330K_0402_5%

KSO1

KSO2

EC_SMB_CK1

EC_SMB_DA1

SPK_RT_Detect#

H_PROCHOT#_EC

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2

EC_SMB_DA2

EC_SMB_CK2

EC_SMB_DA2

@

C2217

C2217 18P_0402_50V8J

18P_0402_50V8J

1

0.1U_0402_16V4Z

FCH_POK[14]

+3VS

C22

01

R2204 @ 10_0402_5%R2204 @ 10_0402_5%

C2210

0.1U_0402_16V4Z

KSO[0..17][33]

KSI[0..7][33]

12

R2220

10K_0402_5%

@

R2231 10M_0402_5%@R2231 10M_0402_5%@

1

2

1

2

ECA

1 2

@

Y2200

1 2

32.768KHZ_12.5PF_CM31532768DZFT

+EC

1

C22

02

1000P_0402_50V7K

2

GND

1 2

1

2

@

D2200

RB751V-40_SOD323-2

2 1

12

R2221

0_0402_5%

RTC_CLK[12,16]

_AVCC

CLK_PCI_EC[12,16]

KSO[0..17]

KSI[0..7]

R2200 0_0402_5%@R2200 0_0402_5%@

@

1

C2218

C2218 18P_0402_50V8J

18P_0402_50V8J

2

GATE KB_RST#[14] SERIRQ[12] LPC_FRAME#[12,33,35] LPC_AD3[12,33,35] LPC_AD2[12,33,35] LPC_AD1[12,33,35] LPC_AD0[12,33,35]

PLT_RST#[12,31,35]

EC_SCI#[14] ADP_PROTECT[38]

EC_SMB_CK1[38,39] EC_SMB_DA1[38,39] EC_SMB_CK2[18,25,32,7] EC_SMB_DA2[18,25,32,7]

PM_SLP_S3#[14] PM_SLP_S5#[14] EC_SMI#[14] CMOS_ON#[26] TP_RESET[33] GS_ON#[30] WL_OFF_EC#[33]

EC_TACH[32]

EC_TX_P80_DATA[33,35] EC_RX_P80_CLK[33,35]

EC_FAN_PWM[32]

GS_SELFTEST[30]

XCLKI

XCLKO

A20[14]

1 2

2

C2203

0.1U_0402_16V4Z

1

2

GATE

RST#

KB_ SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

EC_RST# EC_SCI# ADP_PROTECT

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

PM_SLP_S3# PM_SLP_S5# EC_SMI# CMOS_ON# TP_RESET GS_ON# WL_OFF_EC#

EC_TACH EC_PME# EC_TX_P80_DATA EC_RX_P80_CLK FCH_PWROK EC_FAN_PWM GS_SELFTEST

100K_0402_5%

2

C2204

A20

1

2

XCLKI XCLKO

R2225

C2205

0.1U_0402_16V4Z

1

2

1 2

C2208

C2207

0.1U_0402_16V4Z

1000P_0402_50V7K

1

2

U22

00

EA20/GPIO00

GAT KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1

LPC & MISC

LPC_AD0

CLK_PCI_EC PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A

XCLKI/GPIO5D XCLKO/GPIO5E

C2208

1

2

Int. K/B

Int. K/B Matrix

Matrix

C2206

1 2 3 4 5 7 8

10

12 13 37 20 38

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

12

C2215

20P_0402_50V8

POP for susclk implemented 20100810

+3V

1000P_0402_50V7K

SM Bus

ALW_EC

9

EC_VDD/VCC

PS2 Interface

+EC

+3V

LP

22

33

96

125

111

EC_VDD0

EC_VDD/VCC

PWM Output

AD Input

DA Output

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

GPIO

BATT_LOW_LED#/GPIO55

H_PROCHOT#_EC/GPXIOA06

GPO

GPIO

PCH_APWROK/GPXIOA10

GPI

GND/GND

GND0

11

24

35

94

113

_AVCC

67

EC_VDD/AVCC

BATT_CHG_LED#/GPIO52

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04 PROCHOT_IN/GPXIOA05

VCOUT0_PH/GPXIOA07

PECI_KB9012/GPXIOD07

AGND/AGND

69

ECAGND

LP

+3V

ALW

O0F

GPI

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

BATT_TEMP/GPIO38

GPIO39

ADP_I/GPIO3A

GPIO3B GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH/GPXIOD00

SPIDI/GPIO5B

SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/GPIO40

PECI_KB930/GPIO41

FSTCHG/GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56

VR_ON/GPIO57

PM_SLP_S4#/GPIO59

BKOFF#/GPXIOA08

PBTN_OUT#/GPXIOA09

SA_PGOOD/GPXIOA11

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

V18R

KB9012QF-A4_LQFP128_14X14

3

J22

00

112

JUMP_43X39@

J22

112

JUMP_43X39@

00

2

ALW_EC

+3V

01

2

+3V

ALW_EC

2

G

Log

13

D

Q22

Q22 2N7002K_SOT23-3

2N7002K_SOT23-3

S

o_LED#

01

Log

o_LED# [26,35]

4

V

cc 2207

R

oard ID

B

0 1 2 3 4 5

_DETECT#

21 23

P#

BEE

26

WLAN_WAKE#

27

ACOFF

63

BATT_TEMP

64

GS_VOUTX

65

ADP_I

66

GS_VOUTY

75

BRDID

76

APU_IMON

68

AOU_CTL2

70

FCH_PWR_EN

71

AOU_CTL3

72

SPK_RT_Detect#

83

EC_MUTE#

84

USB_ON#

85

TL_CLK

86

TL_DATA

87

TP_CLK

88

TP_DATA

97

VGATE

98 99

APU_ALERT#_EC

109

9012_PH1

119

EAPD_R

120 126 128

BM#

73

ENBKL

74

ADP_ID

89 90

AOU_EN

91

AOAC_WLAN

92

HDD_DETECT#

93

CP_RESET#

95

SYSON

121

VR_ON

127

VSB_ON

100

EC_RSMRST#

101

EC_LID_OUT#

102

Turbo_V

103

H_PROCHOT#_EC

104

MAINPWON_R

105

BKOFF#

106

PBTN_OUT#

107 108

EC_PXCONTROL

110

ACIN

112

EC_ON

114

ON/OFF

115

LID_SW#

116

SUSP#

117 118

124

+V18R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

BEEP# [29] WLAN_WAKE# [33] ACOFF [39]

BATT_TEMP [38] GS_VOUTX [30] ADP_I [38,39] GS_VOUTY [30]

APU_IMON [45]

AOU_CTL2 [35] FCH_PWR_EN [36] AOU_CTL3 [35] SPK_RT_Detect# [29]

EC_MUTE# [29] USB_ON# [34] TL_CLK [25] TL_DATA [25] TP_CLK [33] TP_DATA [33]

VGATE [14,45]

VGA_AC_DET [18,44]

APU_ALERT#_EC [7] 9012_PH1 [38]

SDV/FVT, NO.13

BM# [40]

SDV/FVT, NO.13

ENBKL [25] ADP_ID [37]

AOU_EN [35] AOAC_WLAN [33] HDD_DETECT# [30] CP_RESET# [33] SYSON [41,43] VR_ON [42,45] VSB_ON [38]

EC_RSMRST# [14] EC_LID_OUT# [14] Turbo_V [38] H_PROCHOT#_EC [38,7]

BKOFF# [25,26] PBTN_OUT# [14]

EC_PXCONTROL [14]

ACIN [35,39] EC_ON [35,40] ON/OFF [35] LID_SW# [35] SUSP# [36,42,44]

1

C2216

2.2U_0805_10V6K

2

PLT_RST#[12,31,35]

2012/11/22 2015/11/22

ENBKL

VR_ON

+3VS

12

R2222

R2222 10K_0402_5%

10K_0402_5%

@

PLT_RST#

Compal Secret Data

Deciphered Date

4

R2233 100K_0402_5%@R2233 100K_0402_5%@

R2234 100K_0402_5%@R2234 100K_0402_5%@

HDD

BM#

EC_MUTE#

BEEP#

LID_SW#

EAPD_R TL_CLK

USB_ON#

TP_CLK

TP_DATA

BATT_TEMP

ACIN

1 2

LAN_WAKE#[35]

MAINPWON_R

Security ROM

U2201

1

NC

VCC

2

NC

WP

3

SCL

PROT#

4

SDA

GND

PCA24S08D_SO8

EEPROM SA00004MK00

3.3V +/- 5%

00K +/- 5%

1

2209

K +/- 5%

0

8

.2K +/- 5%

18K +/- 5%

3

3K +/- 5%

6K +/- 5%

1 2

32 100K_0402_5%

R22

1 2

R22

30 100K_0402_5%@

1 2

R2202 100K_0402_5%R2202 100K_0402_5%

1 2

R2205 10K_0402_5%@R2205 10K_0402_5%@

1 2

R2206 100K_0402_5%R2206 100K_0402_5%

1 2

R2223 0_0402_5%@R2223 0_0402_5%@

1 2

R2224 0_0402_5%@R2224 0_0402_5%@

1 2

R2208 10K_0402_5%@R2208 10K_0402_5%@

1 2

R2210 4.7K_0402_5%R2210 4.7K_0402_5%

1 2

R2211 4.7K_0402_5%R2211 4.7K_0402_5%

1 2

C2211 100P_0402_50V8JC2211 100P_0402_50V8J

1 2

C2212 100P_0402_50V8JC2212 100P_0402_50V8J

R2219 0_0402_5%@R2219 0_0402_5%@

R2228 0_0402_5%@R2228 0_0402_5%@

8 7

ROM_WP

6 5

5

m

in

VR

D_BID

A

0 V

t

yp

V

D_BID

A

m

V

ax

D_BID

A

0

V0 V

0.289 V0.250 V0.216 V

0.436 V

0.712 V

1.036 V

1 2

FCH_SCLK0 [10,11,14,33]

FCH_SDATA0 [10,11,14,33]

Title

Size Document Number Rev

Custom

Date: Sheet of

0.503 V

0.819 V

1.185 V 1.264 V

+3V

ALW

+3VALW_EC

EAPD [29]

+5VALW

+5VS

+3VALW

R2216

R2216 10K_0402_5%

10K_0402_5%

1 2

Compal Electronics, Inc.

EC ENE-KB9012

0.538 V 0

EC_PME#

MAINPWON [38,40]

+3VS

1

C2200

0.1U_0402_16V4Z

2

LA-8127P

5

.875 V

100K_0402_1%

BRDID

0_0402_5%

31 51Tuesday, March 12, 2013

R2207

R2209

+3VALW

SVT S FVT SIT SDV

12

DV2

1.0

5

4

3

2

1

Fintek Thermal sensor

Close U2402

C

2

2200P_0 402_50V7K

D D

C2441

2200P_0 402_50V7K

R

MOTE1+

E

1

439

2

R

MOTE1-

E

MOTE2+

R

1

@

2

REMOTE2 -

C2443

0.1U_040 2_16V4Z

Placed near by APU_CORE

+

VS

3

U

402

2

1

C

V

REMOTE1 +

2

REMOTE1 -

REMOTE2 +

1

REMOTE2 -

2

DP1

3

DN1

4

DP2

5

DN2

F75303M _MSOP10

Address 1001_101xb

S

SDA

ALERT#

THERM#

GND

+

VS

3

12

R

434

2

10K_040 2_5%

@

10

C

L

9

8

7

6

E

_SMB_CK 2 [18,2 5,31,7]

C

EC_SMB_ DA2 [18 ,25,31,7]

R

MOTE1+

E

C

440

2

100P_04 02_50V8J

R

MOTE1-

E

REMOTE2 +

C2442

100P_04 02_50V8J

REMOTE2 -

@

REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8"

C C

1

2

B

2

1

2

B

2

Close to DDR

C

Q

406

2

MMST390 4-7-F_SOT323-3

E

3 1

Under VRAM

C

Q2407

DIS@

Q2407

DIS@

MMST390 4-7-F_SOT323-3

E

3 1

BT Connector

B B

A A

5

+3VS

BT_ON#[13]

SIT, NO.6

R475

1 2

220K_04 02_5%

Q30

Q30 AP2301G N-HF_SOT23-3

AP2301G N-HF_SOT23-3

3 1

2

SDV2, NO.78

4

FAN1 Conn

+3VS

12

R2467

10K_040 2_5%

+3VAUX_ BT

C469 10U_0805_10V4ZC469 10U_0805_10V4Z

C468 0.1U_0402_16V4ZC468 0.1U_0402_16V4Z

12

@

R500

R500 470_040 2_5%

470_040 2_5%

13

@

D

Q42

G

Q42

2N7002K _SOT23-3

S

2

1

2

Security Class ification

2012/11/ 22 2015/11/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/ 22 2015/11/22

3

Compal Secret Data

10K_040 2_5%

EC_TACH[31] EC_FAN_ PWM[31]

Deciphered Date

R2468@

10K_040 2_5%

2

+5VS

1 2

C2499 1U_0603_10 V4ZC 2499 1U_06 03_10V4Z

40mil

1 2 3 4 5 6

ACES_50 273-00401-001

CONN@

Title

Size Docu ment Number Rev

B

Date: Sheet of

JFAN1

1 2 3 4 G5 G6

Compal Electronics, Inc.

Thermal/FAN/BT

LA-8127P

1.0

32 51Tuesday, March 12, 201 3

1

WLAN Conn

W

AN_WAKE#[31]

L

W

BT_OFF#[13,33]

L L

AN_CLKREQ#[14]

W

C

K_PCIE_WLAN#[12]

L L

K_PCIE_WLAN[12]

C

PCIE_CRX_DTX_N1[5] PCIE_CRX_DTX_P1[5]

PCIE_CTX_DRX_N1[5] PCIE_CTX_DRX_P1[5]

+3VS_WLAN

EC_TX_P80_DATA[31,35] EC_RX_P80_CLK[31,35]

WLBT_OFF#[13,33]

W

AN_WAKE#

L

W

AN_CLKREQ#

L

C

K_PCIE_WLAN#

L

C

K_PCIE_WLAN

L

1 2

R2489 0_0402_5%@R2489 0_0402_5%@

1 2

R2490 0_0402_5%@R2490 0_0402_5%@

PCIE_CTX_DRX_N1 PCIE_CTX_DRX_P1

EC_TX_P80_DATA EC_RX_P80_CLK

1 2

R

484 0_0402_5%

2

PCIE_CRX_C_DTX_N1 PCIE_CRX_C_DTX_P1

R2432

1 2 1 2

R2433

R24611K_0402_5% R24611K_0402_5%

For EC to detect debug card insert.

100K_0402_5%

R2441

PCI_RST#_R CLK_PCI_DB

100_0402_1%

100_0402_1% 100_0402_1%

100_0402_1%

12

M

INI1

J

1

3

5

7

9

1

3

1

5

1

15

17

9

1

19

21

3

2

23

5

2

25

7

2

27

29

3

1

31

33

35

3

7

37

39

41

4

3

43

45

4

7

47

49

51

53

GND1

BELLW_80003-7021

CONN@

GND2

2 4 6 8 0

1 1

2 4

1 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

J

403@

2

JUMP_43X79

2 4 6 8 1

0 2

1 1

4 6

1

18

0

2 22

4

2

6

2

8

2 30 3

2 34 36 3

8 40 42 4

4 46 4

8 50 52

54

+

VS

3

1

2

L

P

L

P

L

P

L

P

LPC_AD0_R

RF_OFF# APU_PCIE_RST#

FCH_SCLK0 FCH_SDATA0

USB20_N5 USB20_P5

3

C_FRAME#_R C_AD3_R C_AD2_R C_AD1_R

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB

+3VS

+3V

+1.5VS

R

_OFF#

F

APU_PCIE_RST# [12,17,35]

FCH_SCLK0 [10,11,14,31] FCH_SDATA0 [10,11, 14,31]

USB20_N5 [14] USB20_P5 [14]

1 2

R2477 0_0402_5%R2477 0_0402_5%

1 2

R2478 0_0402_5%R2478 0_0402_5%

1 2

R2474 0_0402_5%R2474 0_0402_5%

1 2

R2475 0_0402_5%R2475 0_0402_5%

1 2

R2476 0_0402_5%R2476 0_0402_5%

1 2

R2479 0_0402_5%R2479 0_0402_5%

+

Power

.5VS

VS_WLAN

1

Mini Card Power Rating

Primary Power (mA)

NormalPeak

1000

330

500

2

495 0_0402_5%

R

R R

R

496 0_0402_5%

2

1 2

@

1 2

750

250

375

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 APU_PCIE_RST#

Auxiliary Power (mA)

Normal

250 (wake enable)

5

(Not wake enable)

L

_OFF# [13]

W W

_OFF_EC# [31]

L

LPC_FRAME# [12,31,35] LPC_AD3 [12,31,35] LPC_AD2 [12,31,35] LPC_AD1 [12,31,35] LPC_AD0 [12,31,35]

CLK_PCI_DB [ 12,35]

A

AC function

O

S

45

Q

400

2

SI3456DDV-T1-GE3_TSOP6

G

@

3

1

C2493

C2493 .1U_0603_25V7K

.1U_0603_25V7K

2

@

+

VS_WLAN

3

+

VALW

C

494

2

1U_0402_6.3V6K

@

R2492

1.5M_0402_5%

3

1

2

12

@

1 2

R

494 @ 0_0805_5%

2

D

6

2 1

R

491

2

1 2

0_0402_5%

@

+

SB

V

12

2

493

R

470K_0402_5%

@

WLAN_EN

13

D

AOAC_WLAN[31]

Q2403

2N7002K_SOT23-3

@

2

G

S

For AOAC assessment

+3VS_WLAN path:

1. +3VS (default)

2. +3VALW

3. +3VALW + Switch

INT_KBD Conn.

KSI[0..7]

KSO[0..17]

KSO2

KSO15

KSO6

KSO8

KSO13

KSO12

KSO11

KSO10

KSO3

KSO4

KSI0

KSO0

CONN PIN define need double check

1 2

C2445 100P_0402_50V8J@C2445 100P_0402_50V8J@

1 2

C2448 100P_0402_50V8J@C2448 100P_0402_50V8J@

1 2

C2449 100P_0402_50V8J@C2449 100P_0402_50V8J@

1 2

C2451 100P_0402_50V8J@C2451 100P_0402_50V8J@

1 2

C2453 100P_0402_50V8J@C2453 100P_0402_50V8J@

1 2

C2455 100P_0402_50V8J@C2455 100P_0402_50V8J@

1 2

C2457 100P_0402_50V8J@C2457 100P_0402_50V8J@

1 2

C2459 100P_0402_50V8J@C2459 100P_0402_50V8J@

1 2

C2461 100P_0402_50V8J@C2461 100P_0402_50V8J@

1 2

C2463 100P_0402_50V8J@C2463 100P_0402_50V8J@

1 2

C2465 100P_0402_50V8J@C2465 100P_0402_50V8J@

1 2

C2467 100P_0402_50V8J@C2467 100P_0402_50V8J@

KSI[0..7] [31]

KSO[0..17] [31]

Screw Holes

H2

H_4P0

@

1

FVT, NO.33

H22

H_3P3

@

1

H_4P0

H_2P3

H4

H3

H_4P0

@

1

H19

H10

H_5P2X5P7N

@

1

H_4P0

H5

H_2P3

@

1

H23

H_5P2X5P7N

@

1

Track Point Conn

+5VS

1

C2470

2

JTP1

1

TP_DATA2 TP_RESET MIDDLE RIGHT LEFT TP_CLK2

1

2

3

4

5

6

7

8

9

0

1

10

11

GND

12

GND

ACES_50524-0100N-001

CONN@

TP_CLK

TP_DATA

2

3

@

D2402

PJDLC05_SOT23-3

1

Compal Secret Data

2012/11/22 2015/11/22

Compal Secret Data

H_2P3

1

H7

@

C2490 100P_0402_50V8J@C2490 100P_0402_50V8J@

C2491 100P_0402_50V8J@C2491 100P_0402_50V8J@

C2492 100P_0402_50V8J@C2492 100P_0402_50V8J@

C2483 100P_0402_50V8J@C2483 100P_0402_50V8J@

C2482 100P_0402_50V8J@C2482 100P_0402_50V8J@

C2446 100P_0402_50V8J@C2446 100P_0402_50V8J@

C2447 100P_0402_50V8J@C2447 100P_0402_50V8J@

C2450 100P_0402_50V8J@C2450 100P_0402_50V8J@

C2452 100P_0402_50V8J@C2452 100P_0402_50V8J@

C2454 100P_0402_50V8J@C2454 100P_0402_50V8J@

C2456 100P_0402_50V8J@C2456 100P_0402_50V8J@

C2458 100P_0402_50V8J@C2458 100P_0402_50V8J@

C2460 100P_0402_50V8J@C2460 100P_0402_50V8J@

C2462 100P_0402_50V8J@C2462 100P_0402_50V8J@

C2464 100P_0402_50V8J@C2464 100P_0402_50V8J@

C2466 100P_0402_50V8J@C2466 100P_0402_50V8J@

C2468 100P_0402_50V8J@C2468 100P_0402_50V8J@

H_2P3

@

1

H17

H_3P5X4P5N

1

H9

@

1 2

@

1

H8

H_2P3

1

H24

H_3P5X4P5N

@

1

KSI1 KSI7 KSI6 KSO9 KSI4 KSI5 KSO0 KSI2 KSI3 KSO5 KSO1 KSI0 KSO2 KSO4 KSO7 KSO8 KSO6 KSO3 KSO12 KSO13 KSO14 KSO11 KSO10 KSO15

LEFT MIDDLE RIGHT KSO16 KSO17

H12

H13

H_2P3

@

H25

H_4P0N

@

1

H11

H_4P0N

@

1

@

FD1FD1

H15

H_2P3

H21

H_4P0N

H16

H_2P3

@

1

@

1

FD2FD2

FD3FD3

1

10 11 1 13 14 15 16 1 1 19 20 21 2 2 2 25 26 2 2 2 30

31 32

H14

H_2P3

FD4FD4

1

2

3

4

5

6

7

8

9

9 10 11

2

12 13 14 15 16

7

17

8

18 19 20 21

2

22

3

23

4

24 25 26

7

27

8

28

9

29 30

GND1 GND2

JAE_FL4S030HA3R3000A-DT

CONN@

H18

H_2P3

@

1

ZZZ3

LA-8127_PCB

DA8000XR010

0.1U_0402_16V4Z

TP_RESET[31]

ESD Request

TP_CLK2

TP_DATA2

2

3

@

D2403

PJDLC05_SOT23-3

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

JKB1

1

LEFT

MIDDLE

RIGHT

KSO16

KSO17

KSO1

KSO7

KSI2

KSO5

KSI3

KSO14

KSI7

KSI6

KSI5

KSI4

KSO9

KSI1

H6

@

1

H20

H_2P1N

Click pad 10PIN

Deciphered Date

+5VS

JCP1

R2483

FCH_SCLK1[14]

FCH_SDATA1[14]

CP_RESET#[ 31] TP_CLK[31] TP_DATA[31]

1 2

0_0402_5%

1 2

0_0402_5%

C2489

@ C2489

@

100P_0402_50V8J

+5VS

R2473 4.7K_0402_5%@R2473 4. 7K_0402_5%@

R2464 @ 4.7K_0402_5%R2464 @ 4.7K_0402_5%

R2470 4.7K_0402_5%R2470 4.7K_0402_5%

R2472 0_0402_5%@R2472 0_0402_5%@

R2471 100K_0402_1%R2471 100K_0402_1%

+3VS

R2497 2.2K_0402_5%R2497 2.2K_0402_5%

R2498 2.2K_0402_5%R2498 2.2K_0402_5%

FCH_SCLK1_R TP_DETECT TP_DATA2 TP_CLK2

R2485

FCH_SDATA1_R

CP_RESET# TP_CLK TP_DATA

1

C2488

@ C2488

@

100P_0402_50V8J

2

1 2

Title

TP/KBD/Screw Hole/Debug

Size Document Number Rev

C

Date: Sheet of

1

2

3

4

5

6

7

8

9

11

9

GND

10

12

10

GND

ACES_51522-01001-001

CONN@

TP_CLK2

TP_DATA2

TP_RESET

TP_DETECT

CP_RESET#

FCH_SCLK1_R

FCH_SDATA1_R

Compal Electronics, Inc.

SIT, NO.2

LA-8127P

33 51Tuesday, March 12, 2013

1.0

5

S

B3.0 Conn *3

U

S

B30_FTX_DRX_N0

U

B30_FTX_DRX_N0[14]

S

D D

U

B30_FTX_DRX_P0[14]

S

B30_FRX_DTX_N0[14]

U

B30_FRX_DTX_P0[14]

S

USB30_P10[14]

USB30_N10[14]

C C

USB30_FTX_DRX_N1[14]

USB30_FTX_DRX_P1[14]

USB30_FRX_DTX_N1[14]

USB30_FRX_DTX_P1[14]

USB30_P11[14]

USB30_N11[14]

U

S

B30_FTX_DRX_P0

U

B30_FRX_DTX_N0

S

U

B30_FRX_DTX_P0

S

USB30_P10

USB30_N10

USB30_FTX_DRX_N1

USB30_FTX_DRX_P1

USB30_FRX_DTX_N1

USB30_P11

USB30_N11

1 2

R

443

@

443

@

2

1 2

R

442

@

442

@

2

1 2

R

444

@

444

@

2

1 2

R

445

@

445

@

2

1 2

R2446

@R2446

@

1 2

R2447

@R2447

@

1 2

R2448

@ R2448

@

1 2

R2449

@ R2449

@

1 2

R2450

@ R2450

@

1 2

R2452

@ R2452

@

1 2

R2451

@ R2451

@

1 2

R2453

@ R2453

@

S

B30_FTX_DRX_N0_L

U

0_0402_5%

S

B30_FTX_DRX_P0_L

U

0_0402_5%

U

B30_FRX_DTX_N0_L

S

0_0402_5%

U

B30_FRX_DTX_P0_L

S

0_0402_5%

USB30_P10_L

0_0402_5%

USB30_N10_L

0_0402_5%

USB30_FTX_DRX_N1_L

0_0402_5%

USB30_FTX_DRX_P1_L

0_0402_5%

USB30_FRX_DTX_N1_L

0_0402_5%

USB30_FRX_DTX_P1_LUSB30_FRX_DTX_P1

0_0402_5%

USB30_P11_L

0_0402_5%

USB30_N11_L

0_0402_5%

4

F

r EMI request

o

L

400

2

U

B30_FTX_DRX_P0

S

U

B30_FTX_DRX_N0

S

B30_FRX_DTX_P0

U

S

B30_FRX_DTX_N0

U

USB30_P10

USB30_N10

USB30_FTX_DRX_N1

USB30_FTX_DRX_P1

USB30_FRX_DTX_P1 USB30_FRX_DTX_P1_L

USB30_P11

USB30_N11

1

4

WCM-2012HS-900T_4P

L

401

2

1

4

WCM-2012HS-900T_4P

L2402

1

4

WCM-2012-670T_4P

For EMI request

L2403

1

4

WCM-2012HS-900T_4P

L2404

1

4

WCM-2012HS-900T_4P

L2405

1

4

WCM-2012-670T_4P

2

U

B30_FTX_DRX_P0_L

S

2

3

U

B30_FTX_DRX_N0_L

S

3

2

S

B30_FRX_DTX_P0_L

U

2

3

S

B30_FRX_DTX_N0_L

U

3

2

3

2

USB30_FTX_DRX_N1_L

2

3

USB30_FTX_DRX_P1_L

3

2

USB30_FRX_DTX_N1_LUSB30_FRX_DTX_N1

2

3

2

3

USB30_P10_L

USB30_N10_L

USB30_P11_L

USB30_N11_L

S

B30_FRX_DTX_N0_L

U

S

B30_FRX_DTX_P0_L

U

B30_FTX_DRX_N0_L

S

U

B30_FTX_DRX_P0_L

S

USB30_FRX_DTX_N1_L

USB30_FRX_DTX_P1_L

USB30_FTX_DRX_P1_L

3

2

404

D

9

8

7

6

TVWDF1004AD0_DFN9

D2406

9

8

7

6

TVWDF1004AD0_DFN9

1

S

B30_FRX_DTX_N0_L

U

2

S

B30_FRX_DTX_P0_L

U

4

U

B30_FTX_DRX_N0_L

S

5

U

B30_FTX_DRX_P0_L

S

3

C2475

0.1U_0402_16V4Z

1 2

USB_ON#[31]

1

USB30_FRX_DTX_N1_L

2

USB30_FRX_DTX_P1_L

4

USB30_FTX_DRX_N1_LUSB30_FTX_DRX_N1_L

5

USB30_FTX_DRX_P1_L

3

U

B30_P10_L

S

USB_ON#

USB30_P11_L

2

405

D

3

I

O2

/

2

N

D

G

1

I

O1

/

AZC099-04S.R7G_SOT23-6

U2404

1

GND

VOUT

2

VOUT7VIN

VIN3VOUT

4

FLG

EN

G547I2P81U_MSOP8

Low Active

D2407

3

I/O2

2

GND

1

I/O1

AZC099-04S.R7G_SOT23-6

I

O4

/

D

V

I

O3

/

+USB3_VCCA+5VALW

8

6 5

R2487 0_0402_5%@R2487 0_0402_5%@

I/O4

VDD

I/O3

2

6

5

4

U

W=80mils

1 2

6

5

4

USB30_N11_L

S

B30_N10_L

+

VALW

5

+5VALW

+

U

2

C2476

@C2476

@

0.1U_0402_16V4Z

1

SB3_VCCA

1

C2473

+

2

150U_B2_6.3VM_R35M

USB_OC0# [ 14]

1

L

1

P

+

SB3_VCCA

U

W

80mils

=

J

SB3

U

B30_FTX_DRX_P0_L

S

U

B30_FTX_DRX_N0_L

S S

B30_P10_L

C2474

1

2

470P_0402_50V7K

U

S

B30_N10_L

U

S

B30_FRX_DTX_P0_L

U

S

B30_FRX_DTX_N0_L

U

9

S

TX+

S

1

V

US

B

8

S

TX-

S

3

D

+

7

N

D

G

2

D

-

6

S

RX+

S

4

N

D

G

5

S

RX-

S

ACON_TARA4-9K1311

CONN@

10

G

D

N

11

G

D

N

12

N

D

G

13

G

D

N

LP2

USB30_FTX_DRX_P1_L

USB30_FTX_DRX_N1_L USB30_P11_L

USB30_N11_L USB30_FRX_DTX_P1_L

USB30_FRX_DTX_N1_L

+USB3_VCCA

W=80mils

JUSB2

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

D-

6

SSRX+

4

GND

5

SSRX-

ACON_TARA4-9K1311

CONN@

10

GND

11

GND

12

GND

13

GND

USB_OC1# [14]

+USB3_VCCB

1

C2478

C2479

1

+

2

470P_0402_50V7K

150U_B2_6.3VM_R35M

LP3

+USB3_VCCB

USB30_FTX_DRX_P2_L

USB30_FTX_DRX_N2_L USB30_P12_L

USB30_N12_L USB30_FRX_DTX_P2_L

USB30_FRX_DTX_N2_L

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

W=80mils

JUSB1

9

SSTX+

1

VBUS

8

SSTX-

3

D+

7

GND

2

GND

D-

6

GND

SSRX+

4

GND

5

SSRX-

GND

ACON_TARA4-9K1311

CONN@

USB 3.0 Conn

LA-8127P

1

10 11 12 13

34 51Tuesday, March 12, 2013

1.0

+USB3_VCCB+5VALW

U2405

C2477

0.1U_0402_16V4Z

For EMI request

L2406

1 2

USB30_FTX_DRX_N2[14]

B B

USB30_FTX_DRX_P2[14]

USB30_FRX_DTX_N2[14]

USB30_FRX_DTX_P2[14]

USB30_P12[14]

USB30_N12[14]

A A

USB30_FTX_DRX_N2

USB30_FRX_DTX_N2

USB30_FRX_DTX_P2 USB30_FRX_DTX_P2_L

USB30_P12

USB30_N12

5

R2454

@R2454

@

1 2

R2455

@R2455

@

1 2

R2457

@R2457

@

1 2

R2456

@R2456

@

1 2

R2458

@R2458

@

1 2

R2459

@R2459

@

USB30_FTX_DRX_N2_L

0_0402_5%

USB30_FRX_DTX_N2_L

0_0402_5%

USB30_P12_L

0_0402_5%

USB30_FTX_DRX_N2

USB30_FTX_DRX_P2

USB30_FRX_DTX_N2 USB30_FR X_DTX_N2_L

USB30_P12

USB30_N12

1

4

WCM-2012HS-900T_4P

L2407

1

4

WCM-2012HS-900T_4P

L2408

1

4

WCM-2012-670T_4P

4

2

USB30_FTX_DRX_N2_L

2

3

USB30_FTX_DRX_P2_LUSB30_FTX_DRX_P2 USB30_FTX_DRX_P2_L

3

2

3

USB30_FRX_DTX_P2_LUSB30_FRX_DTX_P2USB30_N12_L

3

2

3

USB30_P12_L

USB30_N12_L

USB30_FRX_DTX_N2_L

USB30_FRX_DTX_P2_L

USB30_FTX_DRX_N2_L

USB30_FTX_DRX_P2_L

D2408

9

8

7

6

TVWDF1004AD0_DFN9

3

1 2

1

USB30_FRX_DTX_N2_L

2

USB30_FRX_DTX_P2_L

4

USB30_FTX_DRX_N2_L

5

USB30_FTX_DRX_P2_L

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

1

GND

VOUT

2

VOUT7VIN

VIN3VOUT

4

USB_ON#

EN

G547I2P81U_MSOP8

Low Active

3

USB30_P12_L

2

1

2012/11/22 2015/11/22

W=80mils

8

6 5

1 2

R2488 0_0402_5%@R2488 0_0402_5%@

FLG

D2409

I/O4

I/O2

VDD

GND

I/O3

I/O1

AZC099-04S.R7G_SOT23-6

Compal Secret Data

Deciphered Date

2

C2480

@C2480

@

0.1U_0402_16V4Z

1

6

5

+5VALW

4

USB30_N12_L

2

5

4

3

2

1

ON/OFF switch

+

VLP

3

R

460

2

100K_0402_5%

D2410

2

3

BAV70W_SOT323-3

1 2

ON/OFF

51_ON#

ON/OFF [31]

51_ON#

D D

J2405

1 2

SHORT PADS

ON/OFFBTN#

1

SIT, NO.1

13

D

Q2408

EC_ON

EC_ON[31,40 ]

R2463

R2463 100K_0402_5%

100K_0402_5%

@

1 2

C C

Lan Conn

PCIE_CRX_DTX_N0[5] PCIE_CRX_DTX_P0[5]

PCIE_CTX_DRX_N0[5] PCIE_CTX_DRX_P0[5]

CLK_PCIE_LAN#[12] CLK_PCIE_LAN[12]

LAN_CLKREQ#[14]

APU_PCIE_RST#[12,17,33,35] LAN_WAKE#[31] FCH_PCIE_WAKE#[14] CLK_LAN_25M[12]

ACIN[31,39]

+3VS

+3VALW

+RTCBATT

ESD Request

CLK_LAN_25M

B B

1 2

R2480 33_0402_5%R2480 33_0402_5%

2

C2500

C2500 22P_0402_50V8J

22P_0402_50V8J

1

2

G

PCIE_CRX_DTX_N0 PCIE_CRX_DTX_P0

PCIE_CTX_DRX_N0 PCIE_CTX_DRX_P0

CLK_PCIE_LAN# CLK_PCIE_LAN LAN_CLKREQ# APU_PCIE_RST# LAN_WAKE# FCH_PCIE_WAKE# CLK_LAN_25MCLK_LAN_25M ACIN

2N7002K_SOT23-3

@

S

JRJ45

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

GND

20

GND

ACES_50506-01841-P01

CONN@

Power Button Board Conn

+

VALW

VLP

3

2

481

482

0_0402_5%

LID_SW#[31]

ESD Request

R

482

R

R 0_0402_5%

0_0402_5%

@

1 2

O

OFFBTN#

N/

L

D_SW#

I

LID_SW#ON/OFFBTN#

2

3

@

1

D2416

D2416 PJSOT24CH_SOT23-3

PJSOT24CH_SOT23-3

Finger Printer

+3VS

1

C2481

0.1U_0402_16V4Z

2

USB20_N7[14] USB20_P7[1 4]

AZC199-02SPR7G_SOT23-3

For ESD

J

WR1

P

1

2

3

5

G

3

1

6

4

G2

4

ACES_50504-0040N-001

CONN@

@

D2413

223

1

+3VS_FP

2

USB20_N7

3

USB20_P7

4

FP_GND

ACES_50504-0040N-001

CONN@

3

1

CONN@

USB2.0/Audio Jack SB CONN

+

VALW

5

H

_OUTL[29]

P

H

_OUTR[29]

P

X

T_MIC[29]

E PLUG_IN[29]

USB20_N0[14] USB20_P0[14]

USB_OC3#[14] AOU_EN[31]

AOU_CTL2[31] AOU_CTL3[31]

JFPB1

1 2

5

G1

3

6

G2

4

J

UD1

A

1

2

3

4

5

6

7

8

9

10

11

12

1

3

13

14

15

1

6

16

17

1

8

18

9

1

19

0

2

20

21

GND1

22

GND2

ACES_88194-2041

CONN@

Card Reader

+3VS

JCARD1

1

2

3

4

5

6

7

8

9

0

1

10

11

12

13

14

GND GND

ACES_50224-0140N-001

CONN@

15 16

4

+3VALW

PCIE_CRX_DTX_P3 PCIE_CRX_DTX_N3

CLK_PCIE_CARD CLK_PCIE_CARD#

PCIE_CTX_DRX_P3 PCIE_CTX_DRX_N3 CARD_CLKREQ# APU_PCIE_RST#

PCIE_CRX_DTX_P3[5] PCIE_CRX_DTX_N3[5]

CLK_PCIE_CARD[12] CLK_PCIE_CARD#[12]

PCIE_CTX_DRX_P3[5] PCIE_CTX_DRX_N3[5]

CARD_CLKREQ#[14]

APU_PCIE_RST#[12,17,33,35]

Logo_LED#[26,31]

A A

5

Debug Conn.

+3VS +3VALW

LPC_FRAME#[12,31,33] LPC_AD3[12,31,33] LPC_AD2[12,31,33] LPC_AD1[12,31,33] LPC_AD0[12,31,33]

PLT_RST#[12,31]

CLK_PCI_DB[12,33]

EC_TX_P80_DATA[31, 33] EC_RX_P80_CLK[31,33]

PLT_RST#

CLK_PCI_DB

12P_0402_50V8J

3

JDB3

1

2

3

4

5

6

7

8

9

10

11

13

11

GND

12

14

12

GND

ACES_85201-1205N

CONN@

C2502

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Sub Board

LA-8127P

1

35 51Tuesday, March 12, 2013

1.0

A

+3VALW TO +3VS

+

VALW

3

U

8

1

7 6

C

307

2

5

10U_0603_6.3V6M

2

V

SB

+

AP4800BGM-HF_SO-8

1 1

SUSP

12

R

304

2

470K_0402_5%

R2308

10K_0402_5%

Q2305

Q2305 2N7002K_SOT23-3

2N7002K_SOT23-3

R2308

13

D

2

G

S

+

VS

3

302

2

1

2 3

C

308

2

10U_0603_6.3V6M

2

4

12

3VS_GATE_R3VS_GATE

1

C2311

C2311 .1U_0603_25V7K

.1U_0603_25V7K

2

SIT, NO.8 SIT, NO.8

12

2

303

R

R 470_0603_5%

470_0603_5%

13

D

2

G

S

Q

302

2

2N7002K_SOT23-3

B

+5VALW TO +5VS

+

VALW

5

U

301

2

8

V

SB

R

2

150K_0402_5%

5VS_GATE

13

D

Q2304

Q2304 2N7002K_SOT23-3

2N7002K_SOT23-3

S

305

7 6 5

R2307

10K_0402_5%

AP4800BGM-HF_SO-8

4

12

5VS_GATE_R

1

C

304

2

10U_0603_6.3V6M

2

+

U

SP

S

2

SUSP

G

+

VS

5

1 2 3

1

C2310

C2310 .1U_0603_25V7K

.1U_0603_25V7K

2

1

C

305

2

10U_0603_6.3V6M

2

C

+1.5V to +1.5VS

12

2

302

R

R 470_0603_5%

470_0603_5%

13

D

2

U

SP

S

G

S

Q

300

2

2N7002K_SOT23-3

SUSP#

D

1

C

301

2

10U_0603_6.3V6M

2

5

VALW

+

12

100K_0402_5%

100K_0402_5% R

R

306

2

1.5VS_GATE 1. 5VS_GATE_R

13

D

2

Q2306

G

2N7002K_SOT23-3

G

2N7002K_SOT23-3

S

+

.5V

1

AP2301GN-HF_SOT23-3

1 2

R2309

150K_0402_5%

2

301

Q

3 1

2

+

.5VS

1

@

C

302

2

10U_0603_6.3V6M

2

1

C2300

C2300 .1U_0603_25V7K

.1U_0603_25V7K

2

1

C

303

2

1U_0603_10V6K

2

12

13

D

S

E

R

301

2

470_0603_5%

@

2

G

@

Q

303

2

2N7002K_SOT23-3

U

SP

S

+1.1VALW to +1.1VS

+1.1VALW +1.1VS

U2300

8

1

7 6

C2313

5

10U_0603_6.3V6M

SUSP

10U_0603_6.3V6M

2

+VSB

12

1.1VS_GATE 1.1VS_GATE_R

13

D

2

G

S

R2315

R2315 220K_0402_5%

220K_0402_5%

47K_0402_5%

Q2310

Q2310 2N7002K_SOT23-3

2N7002K_SOT23-3

AP4800BGM-HF_SO-8

R2316

2 2

3 3

1

2 3

C2314

C2314 10U_0603_6.3V6M

10U_0603_6.3V6M

2

4

12

1

2

C2316

C2316 1U_0603_25V6K

1U_0603_25V6K

1

C2315

C2315 1U_0603_10V6K

1U_0603_10V6K

2

@

Q2307

2N7002K_SOT23-3

12

13

D

S

R2311

R2311 470_0603_5%

470_0603_5%

@

2

SUSP

G

+3VALW TO +3V +1.1VALW to +1.1V

@

S

SI2305CDS-T1-GE3_SOT23-3

@

R2310

0_0402_5%

@

Q2313

Q2313 2N7002K_SOT23-3

2N7002K_SOT23-3

@

Q2318

G

D

13

1

@

C2321

2

C2321 10U_0603_6.3V6M

10U_0603_6.3V6M

2

12

3V_FCH_GATE_R3V_FCH_GATE

SUSP[43]

SUSP#[31,42,44]

1

@

C2312

C2312 .1U_0603_25V7K

.1U_0603_25V7K

2

SUSP

12

R2312

R2312 100K_0402_5%

100K_0402_5%

J2303 @

JUMP_43X79

+5VALW+RTCBATT

12

@

R2313

R2313 100K_0402_5%

100K_0402_5%

1

OUT

2

IN

GND

3

FCH_PWR_EN_R

+0.75VS

12

R2319

R2319 470_0603_5%

470_0603_5%

@

13

D

S

+3VALW +3V

1

@

C2309

C2309 10U_0603_6.3V6M

10U_0603_6.3V6M

2

+5VALW

12

@

R2323

R2323 100K_0402_5%

100K_0402_5%

13

D

2

G

S

@

Q2312

2

SUSP

G

2N7002K_SOT23-3

SIT, NO.5

2

112

Q2308

Q2308 DDTC124EKA-7-F_SC59-3

DDTC124EKA-7-F_SC59-3

SIT, NO.5

@

+1.1VALW +1.1V

1

C2317

C2317 10U_0603_6.3V6M

10U_0603_6.3V6M

2

@

+5VALW

12

@

R2322

R2322 150K_0402_5%

150K_0402_5%

1.1V_FCH_GATE 1. 1V_FCH_GATE_R

13

D

@

FCH_PWR_EN_R

+3V+3VALW

2

G

@

Q2316

Q2316 2N7002K_SOT23-3

2N7002K_SOT23-3

S

@

Q2317

S

D

13

G

2

SI2305CDS-T1-GE3_SOT23-3

@

12

R2317

0_0402_5%

1

@

C2320

C2320 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

2

1

@

C2318

C2318 1U_0603_10V6K

1U_0603_10V6K

2

@

C2319

C2319 1U_0603_10V6K

1U_0603_10V6K

+1.1VALW +1.1V

J2302 @

112

JUMP_43X79

2

+3VALW TO +3V_FCH

Sh

ort J2301 for PCH VCCSUS3.3

+3VALW +3V_FCH

J2301 @

2

112

JUMP_43X79

12

FCH_PWR_EN[31]

4 4

A

B

R2325 0_0402_5%@R2325 0_0402_5%@

FCH_PWR_EN_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

DC V TO VS INTERFACE

Size Document Number Rev

C

Date: Sheet of

LA-8127P

E

36 51Tuesday, March 12, 2013

1.0

5

R

101

P

P 10K_0402_1%

10K_0402_1%

+

VALW

3

D

CIN1

J

D D

J

1

2

A

DIN

P

2

3

4

5

ACES_50312-00541-001

@

P

F

7A_24VDC_429007.WRML

1 2

12

PC102

PC103

680P_0603_50VK

0.1U_0402_16V7K

PC101

1000P_0402_50V7K

12

PC104

0.1U_0402_16V7K

1 2

P

101

L

SMB3025500YA_2P

100P_0402_50V8J

R

102

P

P 270_0402_1%

270_0402_1%

1 2

21

A

DIN1

P

101

12

4

3

2

1

ADP_ID

C

Adapter 135W 90W 65W

A

P_ID [31]

D

A

/D

A

R(K ohm) 0 open 10 ADP_ID(V) 0 3.3 1.65

Detection voltage <0.33 >2.64 1.32~1.98

I

N

V

12

100P_0402_50V8J

PC105

PC106

1000P_0402_50V7K

VIN

PD104

LL4148_LL34-2

PR123

LL4148_LL34-2

1 2

51ON-1

12

@

12

@

PR124

PR124 68_1206_5%

68_1206_5%

PD105

LL4148_LL34-2

@

PR125

200_0603_5%

1 2

@

12

68_1206_5%

C C

BATT+

CHGRTCP

+3VLP

@

PR133

+CHGRTC

PR132

PD106

B B

A A

5

+RTCBATT

4

PD106

1 2

RB751V-40_SOD323-2

PR132

1K_0603_5%

1 2

PR133

PU102

0_0603_5%

BIT3021A-ST9 SOT89 3P

1 2

3

12

PC116

PC116 10U_0603_6.3V6M

10U_0603_6.3V6M

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

@

VOUT

VIN

GND

1

3

12

PR131

PR131 200_0603_5%

200_0603_5%

2

CHGRTCIN

12

PC117

PC117 1U_0805_25V6K

1U_0805_25V6K

@

Compal Secret Data

2011/04/18 2015/07/08

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PWR DCIN / Vin Detector /Pre-charge

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

1

37 51Tuesday, March 12, 2013

1.0

5

M

B2

V

J

ATT1

B

1

2

3

4

5

D D

5

6

7

8

G

D

N

9

G

D

N

SUYIN_200082GR007M211ZR

@

E E

C

_SMCA _SMDA

C

12

201

100_0402_1%

PR

PR202

P

201

F

12A_65V_451012MRL

21

V

B

M

SMB3025500YA_2P

12

P

201

C

1000P_0402_50V7K

4

P

201

L

1 2

B

12

P

202

C

0.01U_0402_25V7K

3

TT+

A

PH1 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

2

1

For KB930 --> Keep PU201 circuit (Vth = 1.25V)

For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206 PH201

EC_SMB_CK1 [31,39]

EC_SMB_DA1 [31,39]

1 2

PR203

6.49K_0402_1%

1 2

PR204

PR204 10K_0402_5%

10K_0402_5%

C C

+3VALW

BATT_TEMP [31]

A/D

PC203

0.1U_0603_25V7K

VL

12

+3VS

H_PROCHOT#[45,7]

H_PROCHOT#_EC[31,7]

B B

100K_0402_1%

SPOK[40,41]

A A

5

4

VSB_ON[31]

PR227

1 2

PQ206

13

D

SSM3K7002FU_SC70-3

S

VL

PR213

100K_0402_1%

2

ADP_OCP_1

G

PR226

PR226 0_0402_5%

0_0402_5%

1 2

@

PR212

1 2

1K_0402_5%

1 2

PR233

PR233 0_0402_5%

0_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

12

@

3

ADP_I[31,39]

PR225

2.1K_0402_1%

1 2

13

D

PR224

4.42K_0402_1%

PU201

1

VCC

2

GND

3

OT1

4

OT2

G718TM1U_SOT23-8

13

2

G

PC206

1U_0402_6.3V6K

2011/04/18 2015/07/08

8

TMSNS1

7

RHYST1

6

TMSNS2

5

RHYST2

PR209

10K_0402_1%

B+

PR215

22K_0402_1%

1 2

D

PQ201

2N7002W-T/R7_SOT323-3

S

12

Compal Secret Data

1 2

PR214

100K_0402_1%

PQ205

1 2

PR208

1 2

27.4K_0402_1%

12

PC204

0.22U_0603_25V7K

Deciphered Date

2

G

S

ADP_PROTECT[31]

2N7002W-T/R7_SOT323-3

12

PH201

100K_0402_1%_TSM0B104F4251RZ

12

PR230

PR230 0_0402_5%

0_0402_5%

PQ202

TP0610K-T1-E3_SOT23-3

2

+3VLP

12

@

PR205

21.5K_0402_1%

12

PR228

PR228 0_0402_5%

0_0402_5%

@

Turbo_V[31]

13

12

PC205

0.1U_0603_25V7K

+VSBP

2

+3VLP

PR229

1 2

+VSBP

PR206

12.7K_0402_1%

PR211

@PR211

@

0_0402_5%

1 2

PR207

10K_0402_1%

1 2

PR232

PR232 0_0402_5%

0_0402_5%

1 2

@

100K_0402_1%

PJ201

PJ201 JUMP_43X39@

JUMP_43X39@

2

112

Compal Electronics, Inc.

Title

PWR-BATTERY CONN/OTP

Size Document Number Rev

Custom

Date: Sheet of

+3VLP

1 2

47K_0402_1%

+3VALW

PR231

47K_0402_1%

@

+VSB

PR234

1 2

MAINPWON [31,40]

1

9012_PH1 [31]

38 51Tuesday, March 12, 2013

1.0

5

2

PQ3

01

AO4407A_SO8

DTA144EUA_SC70-3

47K_0402_5%

PQ307

13

2

PQ310A

PACIN_2

PACIN

PR321

1 2

10K_0402_5%

8 7

5

PQ3

2

PR317

47K_0402_1%

1 2

4

05

1 3

015EUBFS8TL_UMT3F

LTC

PQ313

2

VIN

D D

C C

B B

12

01

PR3

V1

61

2

2N7002KDW -2N_SOT363-6

ACOFF[31]

P

1 2 36

12

PC301

PR306

200K_0402_1%

0.1U_0603_25V7K

P2-1

12

PR309

150K_0402_1%

P2-2

34

PQ310B

5

13

2N7002KDW-2N_SOT363-6

EC_SMB_DA1[31,38]

EC_SMB_CK1[31,38]

LTC015EUBFS8TL_UMT3F

04

PQ3

AO4423_SO8

1 2 3 6

4

5600P_0402_25V7K

PR314

PR319

1 2

64.9K_0603_1%

1 2

PC324

0.1U_0603_25V7K

CHGVADJ=(Vcell-4)/0.10627

Vcell

4V

4.2V

4.35V

CHGVADJ

0V

1.882V

3.2935V

CC=0.25A~3A

IREF=1.016*Icharge

IREF=0.254V~3.048V

VCHLIM need over 95mV

1 2

PC3

VIN

12

432K_0603_1%

8 7

5

02

PR333

PR333 0_0402_5%

0_0402_5%

1 2

PR334

PR334 0_0402_5%

0_0402_5%

1 2

+3VALW

4

3

P

S

H00000AA00

1 2

PL3

02

PC303

10U_0805_25V6K

ADP_I[31,38]

100p_0603_50V8

PR322

1 2

316K_0402_1%

PR325

100K_0402_1%

02

PC313

1 2

12

1UH_PCMB061H-1R0M S_7A_20%

1 2

PR3

02

0.01_1206_1%

1

2

1 2

PC304

10U_0805_25V6K@

ACPRN

5

6

7

8

9

10

ACOK

ACDET

IOUT

SDA

BQ24737RGRR_VQFN20_ 3P5X3P5

SA000051W00

SCL

ILIM

11

0.1U_0603_25V7K

ACP

6.8_0603_5%

B

4

3

4

PU301

12

PC320

12

CMPIN

SRN12BM

PR326

3

+

Need EC write ChargeOption() bit[8]=1

1

+

PC323

2

100U_25V_M

@

ACN

PC309

1 2

PC312

0.1U_0603_25V7K

3

2

CMPOUT

SRP

13

14

12

PR327

10_0603_5%

12

PC321

0.1U_0603_25V7K

100U_25V_M

0.1U_0603_25V7K

12

ACP

GND

PC310

12

0.1U_0603_25V7K

1

ACN

TP

VCC

PHASE

HIDRV

BTST

REGN

LODRV

15

DL_CHG

12

1 2

PC305

4.7U_0805_25V6-K

21

20

BQ24727VCC-1

19

LX_CHG

18

DH_CHG

17

BST_CHG

PD303 RB751V- 40_SOD323-2P D303 RB751V-40_SOD323-2

16

12

PC318

PC318 1U_0603_25V6

1U_0603_25V6

@

PC322

0.1U_0603_25V7K

PC306

1 2

4.7U_0805_25V6-K

PR318

10_1206_5%

12

1 2

PC307

4.7U_0805_25V6-K

P2

1 2

PC314

1 2

1U_0603_25V6

PR324

2.2_0603_5%

1 2

0.047U_0603_25V7M

ACPRN

47K_0402_1%

PC308

2200P_0402_50V7K

PC315

BQ24727VDD

PR336

2

PQ3

02

AO4407A_SO8

1 2 3 6

B

+

1 2

PR307

47K_0402_1%

DISCHG_G-1

13

LTC015EUBFS8TL_UMT3F

LTC015EUBFS8TL_UMT3F PQ308

PQ308

6

578

PQ312

123

6

578

123

BQ24727VDD

12

PR338

PR338 10K_0402_1%

10K_0402_1%

13

D

PQ319

S

2N7002W- T/R7_SOT323-3

PQ312

AO4466L_SO8

PQ314

AO4466L_SO8

4

12

4

12

2

G

8 7

5

4

VIN

05

PR3

200K_0402_1%

1 2

1

V

PR308

PR308 220K_0402_1%

220K_0402_1%

1 2

2

13

12

D

PC311

S

0.039U_0603_25V7K

PQ311

2N7002W- T/R7_SOT323-3

PL301

@

PR323

@

PC319

PR337

PR339

1 2

4.7_1206_5%

680P_0603_50V7K

PL301

10UH_+-20%_PCMB104T -100MS_6A

12

24727_SN

12

10K_0402_1%

1 2

PACIN

12

12K_0402_1%

2

G

CHGCH G

ACIN [31,35]

PACIN_2

PR320

0.01_1206_1%

1

2

SRP

SRN

1

T+

BAT

4

3

12

PC317

PC316

10U_0805_25V6K

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELEC TRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

T

tle

i

Title

2015/07/082011/04/18

2

Title

Size D ocument Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

CHARGER

1

1.0

39 51Tuesday, March 12, 2013

1.0

of

5

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

D D

RT8205_B+

PJ401

B+

401

401 PC

PC

C C

B B

PJ401

2

112

JUMP_43 X118@

12

421

421 PC

0.1U_0603_25V7K

PC

PC403

0.1U_0603_25V7K

4.7U_0805_25V6-K

+3VALWP

EC_ON[31,35]

MAINPWON[31,38]

2.2K_040 2_5%

PR414

PR414 0_0402_ 5%

0_0402_ 5%

PR418

12

PC404

PC405

4.7U_0805_25V6-K

4.7U_0805_25V6-K 2200P_0402_50V7K

2200P_0402_50V7K

4.7UH +-20 % PCMC063T-4R7M N 5.5A

12

PC423

1U_0603_10V6K

2N7002K DW-2N_SOT3 63-6

12

1 2

1

+

PC413

PC413 150U_B2 _6.3VM_R45M

150U_B2 _6.3VM_R45M

2

PQ405A

VL

AO4466L _SO8

PL401

61

PQ401

12

PR409

4.7_1206_5%

12

PC415

680P_0603_50V7K

2

100K_04 02_1%

123

PR413

241

12

PQ406

6

3 6

4

578

4

578

PQ403

PQ403 AO4712L _SO8

AO4712L _SO8

13

34

5

Typ: 175mA

+3VLP

12

PC410

4.7U_0805_10V6K

2.2_0603 _5%

1 2

PC411

0.1U_060 3_25V7K

PR417

499K_04 02_1%@

1 2

VS

PR411

499K_04 02_1%

1 2

B+

ENTRIP2ENTRIP1

PQ405B

PQ405B 2N7002K DW-2N_SOT3 63-6

2N7002K DW-2N_SOT3 63-6

PR412

PR407

100K_0402_1%

BST_3V

UG_3V

LX_3V

LG_3V

12

2VREF_8205

2

REF_8205

V

PR401

13K_040 2_1%

1 2

PR403

20K_040 2_1%

1 2

PR405

130K_04 02_1%

1 2

PU401

25

7

8

9

10

11

12

PC417

1U_0603_10V6K

3

P PAD

VO2

VREG3

BOOT2

UGATE2

PHASE2

LGATE2

12

PC402

1U_0603_10V6K

ENTRIP2

6

5

FB2

ENTRIP2

VFB=2.0V

SKIPSEL

EN

3 1

14

RT8205_ B+

2

P

J

+

VALW P

3

+5VALW P +5VALW

PR402

30K_040 2_1%

1 2

PR404

20K_040 2_1%

1 2

PR406

66.5K_04 02_1%

1 2

ENTRIP1

1

2

3

4

FB1

REF

TONSEL

15

ENTRIP1

24

VO1

23

PGOOD

22

BOOT1

UGATE1

PHASE1

LGATE1

NC

VREG5

VIN16GND

8

17

1

12

PC418

12

4.7U_0805_10V6K

PC419

0.1U_0603_25V7K

BST_5V

21

UG_5V

20

LX_5V

19

LG_5V

RT8205L ZQW(2) W QFN24_4X4

VL

Typ: 175mA

PC406

4.7U_0805_25V6-K

PR408

2.2_0603 _5%

1 2

RT8205_ B+

12

PC407

4.7U_0805_25V6-K

SPOK [38,41]

PC412

0.1U_060 3_25V7K

1 2

12

PC409

PC408

0.1U_0603_25V7K

2200P_0402_50V7K

PQ402

5

PQ404TPC8A03-H_SO8 PQ404TPC8A03-H_SO8

4

+3.3VALWP OCP(min)=5.81A +5VALWP OCP(min)=8.44A

2

JUMP_43 X118@

J

P

2

JUMP_43 X118

@

678

TPC8037-H_SO8

35241

4.7UH_20 %_VMPI1004AR-4R7 M-Z01_10A

12

786

PR410

12

123

PC416

402

112

403

112

PL402

1 2

4.7_1206_5%

680P_0603_50V7K

1

+

VALW

3

+5VALWP

1

+

PC414

12

150U_B2 _6.3VM_R45M

2

PC422

1U_0603_10V6K

+3VLP

1 2

PR420

PR420 100K_04 02_1%

12

100K_04 02_1%

@

1 2

@

5

12

PC424

A A

PR419

BM#[31]

0_0402_ 5%

VS

PR415

100K_04 02_1%

13

D

2

G

PQ407

S

@

0.1U_0603_10V7K

12

@

2N7002KW 1N SOT323-3

2

12

LTC015EUBFS8TL_UMT3F

PC420

PR416

40.2K_0402_1%

4.7U_0603_10V6K

@

4

LTC015EUBFS8TL_UMT3F

Security Class ification

2011/04/ 18 2015/07 /08

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/04/ 18 2015/07 /08

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

3VALWP/5VALWP

Size Docu ment Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

40 51Tuesday, March 12, 201 3

1

1.0

5

4

3

+

.1VALWP_B+

1

2

P

01

@

01

@

J5

2

112

JUMP_43X118

B

+

1

12

D D

PR502

2.2_0603_5%

PU501

1

PR501

1 2

12

0.1U_0402_16V7K

1 2

PR510

1 2

12

@

0.1U_0402_16V7K

1 2

TRIP_+1.1VALWP

EN_+1.1VALWP

FB_+1.1VALWP

RF_+1.1VALWP

12

470K_0402_1%

PR508

PR508 10K_0402_1%

10K_0402_1%

TRIP_+1.5VP

EN_+1.5VP

FB_+1.5VP

RF_+1.5VP

12

470K_0402_1%

PR516

PR516 10K_0402_1%

10K_0402_1%

PR506

PR514

34K_0402_1%

PR503

PR503 0_0402_5%

0_0402_5%

SPOK[38,40]

C C

B B

SYSON[31,43]

A A

1 2

PR511

PR511 0_0402_5%

0_0402_5%

1 2

@

34K_0402_1%

@

504

504 PR

PR

PC501

1 2

47K_0402_1%

140K_0402_1%

512

512 PR

PR

PC515

1 2

47K_0402_1%

@

2

3

4

5

TPS51212DSCR_SON10_3X3

PR507

5.76K_0402_1%

PU502

1

2

3

4

5

TPS51212DSCR_SON10_3X3

PR515

11.5K_0402_1%

PGOOD

TRIP

EN

VFB

RF

12

PGOOD

TRIP

EN

VFB

RF

12

VBST

DRVH

V5IN

DRVL

VBST

DRVH

V5IN

DRVL

10

BST_+1.1VALWP

9

UG_+1.1VALWP

8

7

6

11

10

9

8

7

6

11

SW_+1.1VALWP

+1.1VALWP_5V

LG_+1.1VALWP

BST_+1.5VP

UG_+1.5VP

SW_+1.5VP

+1.5VP_5V

LG_+1.5VP

SW

TP

SW

TP

1 2

PR509

2.2_0603_5%

1 2

0.1U_0603_25V7K

12

PC507

PC507 1U_0603_6.3V6M

1U_0603_6.3V6M

0.1U_0603_25V7K

12

PC516

PC516 1U_0603_6.3V6M

1U_0603_6.3V6M

PC506

1 2

+5VALW

PC514

1 2

+5VALW

786

5

PQ501

5

123

786

123

786

123

786

123

PQ501 TPC8037-H 1N SO8

TPC8037-H 1N SO8

PQ502

PQ502 TPC8A03_SO8

TPC8A03_SO8

+1.5VP_B+

PQ503

PQ503 TPC8037-H 1N SO8

TPC8037-H 1N SO8

PQ504

PQ504 TPC8A03_SO8

TPC8A03_SO8

4

PC502

0.1U_0402_25V6

PL501

1UH +-20%_VMPI0703AR-1R0M-Z01_11A

1 2

12

@

PR505

4.7_1206_5%

12

PC509

@PC509

@

680P_0603_50V7K

12

PC510

0.1U_0402_25V6

PL502

PR513

PC518

PL502

1 2

1.0UH_PCMC104T-1R0MN_20A_ 20%

12

@

4.7_1206_5%

12

@PC518

@

680P_0603_50V7K

12

PC503

2200P_0402_50V7K

12

PC504

PC505

4.7U_0805_25V6-K

PJ502

2

112

JUMP_43X118@

+1.1VALW+1.1VALWP

+1.1VALWP

B+

+1.1VALWP Iocp=5.85A

1

12

+

PC519

PC508

2

1U_0603_10V6K

220U_D2_4VY_R15M

PJ503

@ PJ503

@

2

112

JUMP_43X118

12

PC511

2200P_0402_50V7K

12

PC513

PC512

4.7U_0805_25V6-K

+1.5VP

1

12

+

PC517

PC520

2

220U_6.3V_M

1U_0603_10V6K

+1.5VP

PJ504

2

112

JUMP_43X118@

+1.5VP Iocp=15.6A

+1.5V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/04/18

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

+1.1VALWP/+1.5VP

41 51Tuesday, March 12, 2013

1

1.0

5

4

3

1

.2VSP_B+

+

2

J

601

@

601

@

P

2

112

JUMP_43 X118

1

+

B

12

PC603

786

D D

R

602

P

2.2_0603 _5%

VR_ON[31,45]

PR610 0 _0402_5%

12

@

PR603

SUSP#[31,36,44]

243K_04 02_1%

1 2

604

604 PR

PR

1 2

47K_0402_1%

@

C C

PR601

1 2

75K_040 2_1%

12

PC601

1U_0402_16V7K

1 2

TRIP_+1.2V SP

EN_+1.2V SP

FB_+1.2V SP

RF_+1.2V SP

12

470K_04 02_1%

PR608

PR608 10K_040 2_1%

10K_040 2_1%

PR606

PU601

1

2

3

4

5

TPS5121 2DSCR_SON10_ 3X3

PR607

7.15K_04 02_1%

PGOOD

TRIP

EN

VFB

RF

12

VBST

DRVH

V5IN

DRVL

10

BST_+1.2 VSP

9

UG_+1.2V SP

8

SW

TP

SW_+ 1.2VSP

7

+1.2VSP_ 5V

6

LG_+1.2V SP

11

1 2

0.1U_060 3_25V7K

12

PC607

PC607 1U_0603 _6.3V6M

1U_0603 _6.3V6M

P

606

C

1 2

+5VALW

5

Q

601

P

5

P TPC8037 -H 1N SO8

TPC8037 -H 1N SO8

123

786

PQ602

PQ602 TPC8A03 _SO8

TPC8A03 _SO8

123

1UH +-20% _VMPI0703AR-1R0M -Z01_11A

12

PR605

4.7_1206 _5%

12

PC609

680P_06 03_50V7K

4

PC603

PC602

0.1U_0402_25V6

PL601

1 2

2200P_0402_50V7K

12

PC605

PC604

4.7U_0805_25V6-K

+1.2VSP

1

12

+

PC608

PC612

2

1U_0603_10V6K

220U_D2_4VY_R15M

+1.2VSP

PJ602

2

JUMP_43 X118@

+1.2VSP Iocp=13A

112

+1.2VS

B B

PU602

APL5508 -25DC-TRL_SOT8 9-3

PJ603

+3VS

A A

Security Class ification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

112

JUMP_43 X39@

Issued Date

2

PC610

1U_0603 _10V6K

APL5508 -25DC-TRL_SOT8 9-3

2

12

2011/04/ 18

3

IN

GND

1

3

OUT

12

PC611

4.7U_0805_6.3V6K

Compal Secret Data

Deciphered Date

12

PR609

PR609 10K_120 6_5%

10K_120 6_5%

@

+2.5VSP

2

PJ604

2

112

JUMP_43 X39@

(0.38A,20mils ,Via NO.=1)

Title

Size Docu ment Number Rev

Date: Sheet of

JUMP_43 X39@

Compal Electronics, Inc.

+1.2VSP/+2.5VSP

+2.5VS+2.5VSP

42 51Tuesday, March 12, 201 3

1

1.0

5

D D

PR701

@PR701

@

0_0402_5%

SYSON[31,41]

SUSP[36]

C C

1 2

PR703

PR703 0_0402_5%

0_0402_5%

1 2

PC701

@PC701

@

1U_0402_6.3V6K

PQ701

PQ701 2N7002KW 1N SOT323-3

2N7002KW 1N SOT323-3

2

G

12

13

D

S

4

1

.5V

+

2

1

1 2

P

01

J7

2

JUMP_43X79

@

1

PC702

4.7U_0805_6.3V6K

PR702

1K_0402_1%

PR704

3

PU701

VIN1VCNTL

2

12

PC704

1K_0402_1%

0.1U_0402_16V7K

GND

3

VREF

4

VOUT

APL5336KAI-TRL_SOP8P8

12

PC706

PC705

10U_0603_6.3V6M

6

5

NC

7

NC

8

NC

9

TP

+0.75VSP

12

+3VALW

PC703

1U_0603_10V6K

2

PJ702

2

112

JUMP_43X79

@

1

+0.75VS+0.75VSP

PL701

PU702

PJ703

+5VALW

B B

2,14,19,44]

A A

2

112

JUMP_43X118@

PXS_PWREN

5

PR707

12

PC707

PC707 22U_0805_6.3VAM

22U_0805_6.3VAM

1 2

200K_0402_1%

EN_1.8V

1M_0402_5%

PR708

1 2

PC712

1 2

4

10

PVIN

9

PVIN

8

SVIN

5

EN

0.1U_0402_10V7-K

2

LX

PG

3

LX

6

FB

TP

NC

7

1

11

SY8033BDBC_DFN10_3X3

4

LX_1.8V

FB=0.6Volt

PL701

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

PR706

30K_0402_1%

PR705

4.7_1206_5%

12

PC709

680P_0603_50V7K

FB_1.8V

PR709

14.7K_0402_1%

12

PC708

68P_0402_50V8J

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

12

PC710

22U_0805_6.3VAM

2011/04/18

+1.8VSP

PC711

22U_0805_6.3VAM

Compal Secret Data

Deciphered Date

2

+1.8VSP +1.8VGS

Date: Sheet of

PJ704

2

112

JUMP_43X118@

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

+0.75VP/+1.8VP

43 51Tuesday, March 12, 2013

1

1.0

A

GPIO29 GPIO30 GPIO20 GPIO15

GPIO21

VID4 VID3 VID2 VID1 VDDC

VID5

0 1 1 1 1

0 0 0 0

1

0 0 0

1

0

1

0 0

1

1 1

2 2

4.02K_0402_1%

3 3

4 4

VSSSENSE_VGA[21]

0 00

1

0 0

1

0 0

1

0

1

1 1

1

+3VGS

PR832

VGA_PWRGD[14]

1 2

@

38

PR8

1 2

PR837

470K_0402_5%_TSM0B474J4702RE

1 2

@

12

39

PR8

8.06K_0402_1%

1 2

249K_0402_1%

PC865

33P_0402_50V8J

1 2

FB2_VGA

PC867

150P_0402_50V8J

VCCSENSE_VGA[21]

0_0402_5%

VGA_AC_DET[18,31]

PH801

@

12

1 2

169K_0402_1%

+3VGS

16

PC8

PR844

+VGA_COREP

1

0 0

1 1

1

1 1

1 1 1

0 0 0

0 0

1

0

1

0 0

PXS_PWREN[12,14,19,43,44]

SUSP#[31,36,42]

PR865

1 2

10K_0402_1%

12

31

PR8

1.91K_0402_1%

1.91K_0402_1% 100K_0402_5%

100K_0402_5%

1 2

+3VGS

PR834

147K_0402_1%

PR835

100K_0402_5%@

1 2

PR836

@PR836

@

0_0402_5%

VW_VGA

PR840

499_0402_1%

1 2

FB1_VGA

1000P_0402_50V7K

+5VS

A

PR842

1.3K_0402_1%

1 2

12

PR847

PR847 56K_0402_1%

56K_0402_1%

PR848

1 2

0_0402_5%

PR858

1 2

0_0402_5%

PR875

1 2

0_0402_5%

PR859

1 2

0_0402_5%

390P_0402_50V7K

PR827

1 2

0_0402_5%

1

PR861

PR861 91K_0402_1%

91K_0402_1%

1 2

0_0402_5%

1 2

PC801 .1U_0402_16V7KPC801 .1U_0402_16V7K

DPRSLPVR_VGA-1

PR833

12

RBIAS_VGA

COMP_VGA

FB_VGA

PC817

1 2

PR828

0_0402_5%

330P_0402_50V7K

1000P_0402_50V7K

1.125V

1.100V

1.075V

1.050V

1.025V

1.000V

0.975V

0.950V

0.925V

0.900V

0.875V

0.850V

0.825V

0.800V

0.775V1 1 0 1

PR862

1 2

PSI#_VGA

PC833

PC838

10

41

@PR862

@

1 2 3 4 5 6 7 8 9

PU801

PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2

AGND

VSEN_VGA

12

Default

40

39

CLK_EN#

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

@PC839

@

12

PC839

330P_0402_50V7K

VRON_VGA

38

DPRSLPVR

RTN_VGA

12

PR820

PR820 0_0402_5%

0_0402_5%

GPU_VID6

37

VR_ON

ISUM-_VGA

12

VSUM_VGA_N001

12

35

VID4

16

VDD_VGA

12

PR863

0_0402_5%

1 2

GPU_VID5

12

PR821

PR821 0_0402_5%

0_0402_5%

VID031VID132VID233VID334VID536VID6

BOOT2 UGATE2 PHASE2

VSSP2

LGATE2

VCCP

PWM3

LGATE1

VSSP1

PHASE1

VIN

IMON18BOOT119UGATE1

ISL62883CHRTZ-T_TQFN40_5X5

17

20

PR843 0_0402_5%PR843 0_0402_5%

1 2

VIN_VGA

1_0402_5%

1 2

12

PC826

PC827

1U_0603_10V6K

0.22U_0603_25V7K

@PR849

@

PR849

82.5_0402_5%

@PC840

@

PC840

0.01U_0402_25V7K

PR860

PR860 866_0402_1%

866_0402_1%

1 2

B

PR813

1 2

10K_0402_5%

@

GPU_VID4

12

PR822

PR822 0_0402_5%

0_0402_5%

30 29 28 27 26 25 24 23 22 21

PR846

12

PC834

2200P_0603_25V7K

B

2

[18]

12

P

+

VALW

3

61

PQ802A

2N7002KDWH_SOT363-6

@

[18]

GPU_VID3

12

PR823

PR823 0_0402_5%

0_0402_5%

+VGA_B+

+5VS

12

PC835

0.22U_0603_25V7K

12

PC842

.1U_0402_16V7K

S SCH DIO RB751V40 SC76

X

S_PWREN[12,14,19,43,44]

P

801

J

2

JUMP_43X79

@

+3VGS+3 VALW

PR814

1 2

10K_0402_5%

@

[18]

GPU_VID1

GPU_VID2

12

PR824

PR825

0_0402_5%

12

PC815

PC815 1U_0603_10V6K

1U_0603_10V6K

PR841 0_0402_5%@PR841 0_0402_5%@

12

PR845

PC866

1 2

7.87K_0402_1%

.047U_0402_16V7K

12

PR851

2.61K_0402_1%~N

NTC_VGA

12

PR857

11K_0402_1%

P

01

D8

12

R8

66

P

P 130K_0402_1%

130K_0402_1%

1 2

P

0.1U_0402_10V7K

112

12

PC869

@

0.1U_0402_10V7K

34

PQ802B

5

2N7002KDWH_SOT363-6

@

[18]

GPU_VID0

12

PR826

PR826 0_0402_5%

0_0402_5%

+5VS

1 2

PH802

PH802 10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

PR829

1 2

0_0402_5%

VSUM+_VGA

VSUM-_VGA

+5VS

P

R8

82K_0402_1%

1 2

68

C8

12

PR801 10K _0402_1%PR801 10K_0402_1%

C

74

N_

0.95V

E

@

10U_0805_6.3V6M

BOOT1_VGA

12

1 2

PR802 10K _0402_1%PR802 10K_0402_1%

GPU_VID4

UGATE1_VGA

PHASE1_VGA

LGATE1_VGA

+3VGS

1 2

PC871

10U_0805_6.3V6M

1 2

PR803 10K _0402_1%@PR803 10K _0402_1%

GPU_VID3

@

P

67

R8

100K_0402_1%

16

VIN

1

I

N

V

2

V

N

I

U8

02

P

3

TPS54618RTER_QFN16_3X3

G

D

N

4

G

D

N

17

PWRPD

AGND5VSENSE6COMP7RT/CLK

PR869

18K_0402_1%

1 2

PR805 10K _0402_1%@PR805 10K _0402_1%

PR804 10K _0402_1%@PR804 10K _0402_1%

GPU_VID2

GPU_VID1

@

VGA_IMVP_IMON

PR850

2.2_0603_5%

12

BOOT1_1_VGA

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1 2

PR807 10K _0402_1%@PR807 10K _0402_1%

PR806 10K _0402_1%@PR806 10K _0402_1%

GPU_VID0

GPU_VID5

@

0.22U_0603_10V7K

1 2

Layout Note: Place near Phase1 Choke

Issued Date

P

68

R8

0_0402_5%

1 2

14

13

15

EN

PC832

1 2

PR808 10K _0402_1%@PR808 10K _0402_1%

GPU_VID4

@

1

2

BOOT

H

P

PWRGD

1

P

H

0

1

P

H

9

S

/TR

S

12

8

12

PR870

1 2 12

182K_0402_1%

PC872

3300P_0402_50V7K

1 2

PR809 10K _0402_1%PR809 10K_0402_1%

GPU_VID3

1 2

PR811 10K _0402_1%PR811 10K_0402_1%

PR812 10K _0402_1%PR812 10K_0402_1%

PR810 10K _0402_1%PR810 10K_0402_1%

GPU_VID2

GPU_VID1

GPU_VID0

PR864

1 2

0_0603_5%

2012/07/03 2013/07/03

12

PC870

1 2

GPU_VID5

D

P

76

C8

0.22U_0603_10V7K

1 2

P

803

L

1UH_PCMB063T-1R0MS_12A_20%

L

_0.95V

X

PC873

2200P_0402_50V7K

+VGA_COREP +VGA_CORE

5

4

123

4

123 5

Compal Secret Data

Deciphered Date

1 2

12

PR871

SNUB_0.95V

4.7_0402_1%

@

12

PC874

@

12

PQ804

PC844

68P_0402_50V8J

@

TPCA8065-H_SOP-ADV8-5

PQ805

TPCA8057-H 1N PPAK56-8

D

680P_0402_50V7K

100K_0402_1%

PJ802

2

JUMP_43X118@

PJ803

2

JUMP_43X118@

12

PC828

0.1U_0402_25V6

@

12

@PR853

@

PR853

4.7_1206_5%

SNUB1_VGA

12

PR872

1 2

19.1K_0402_1%

0.8V

PR873

1 2

112

12

PC829

PC830

2200P_0402_50V7K@

10U_0805_25V6K

0.36UH_PCMC104T-R36MN1R17_30A_20%

12

PR854

3.65K_0402_1%

VSUM+_VGA

PC841

@

680P_0603_50V7K

E

J

805

P

V

GA_PCIEP

+

12

PC875

22P_0402_50V8J

+VGA_B+

FBMA-L11-453215800LMA90T_2P

12

PC831

10U_0805_25V6K

PL801

1

2

Title

Size Document Number Rev

Date: Sheet of

2

112

JUMP_43X79

@

12

PC878

PC877

PC879

22U_0805_6.3VAM

PL802

1 2

4

3

12

1

+

PR856

1_0402_1%

PC881

2

330U_D2_2V_Y

VSUM-_VGA

Compal Electronics, Inc.

VGA_COREP

E

PC880

22U_0805_6.3VAM

1

+

PC882

2

0

.95VGS

+

GA_PCIEP

V

B+

+VGA_COREP

1

+

PC836

PC837

2

330U_D2_2V_Y

44 51Tuesday, March 12, 2013

1.0

5

C

902

P

330P_04 02_50V7K

R

907

P

P 0_0402_ 5%

0_0402_ 5%

12

P

C

1000P_0 402_50V7 K

@

PR912

590_040 2_1%

12

PC915

@

220P_04 02_50V7K

12

330P_04 02_50V7K

1000P_0 402_50V7 K

910

12

A

U_VDDNB_S EN[7]

P

R

906

P

10_0402 _5%

2.61K_0402_1%

PC914

10_0402 _5%

12

911

912

912 PR

PR

1 2

PC913

PC

1 2

11K_0402_1%

0.1U_0402_25V6

0.047U_0402_16V7-K

PR914

@PR 914

@

100_040 2_1%

D D

V

S

UMP_NB

A

PU_CORE_NB

+

12

902

902 PH

PH

10K_0402_5%_ERTJ0ER103J

12

909

909 PR

PR

0.1U_060 3_50V7K

P

12

C

904

P

2K_0402 _1%

P

903

R

3.4K_04 02_1%

301_040 2_1%

12

902

R

12

R

908

P

12

PR969

10K_040 2_1%

P

904

R

137K_04 02_1%

100P_04 02_50V8J

12

After rev1.1 mu st change to 13 3k

48

PU901

12

PWROK

12

PC929

PR950

1 2

SVC

SVD

VDDIO

SVT

ENABLE

0.22U_0402_10V6K

11K_0402_1%

12

PC930

0.22U_0402_10V6K

1 2

PU901

1

ISEN2_NB

2

NTC_NB

3

IMON_NB

4

SVC

5

VR_HOT_L

6

SVD

7

VDDIO

8

SVT

9

ENABLE

10

PWROK

11

IMON

12

NTC

ISEN3

ISEN2

ISEN1

1 2

PC935

0.082U_0402_16V7K

PR957

100_040 2_1%

@

ISEN1_NB

ISEN3

13

PR970

PR970 10K_040 2_1%

10K_040 2_1%

@

PC936

PR955

0.22U_0402_10V6K

0.22U_0402_10V6K 604_040 2_1%

604_040 2_1%

820P_04 02_50V7K

12

PR920

133K_04 02_1%

PR921 27.4K_040 2_1%P R921 27.4 K_0402_1 %

12

PH901

470K_04 02_5%_TSM0B 474J4702R E

C C

After rev1.1 mu st change to 13 3k

B B

12

PR926

10.5K_0 402_1%

PR934

133K_04 02_1%

1 2

PC927

1000P_0 402_25V6 K

1 2

PR936 2 7.4K_0402 _1%PR936 27.4K_ 0402_1%

PH903

470K_04 02_5%_TSM0B 474J4702R E

12

PR945

10.5K_0 402_1%

PC919

1000P_0 402_25V6 K

1 2

PR971

PR971 0_0402_ 5%

0_0402_ 5%

1 2

APU_SVC[7]

APU_SVD[7]

+1.5VS

APU_SVT[7]

VR_ON[3 1,42]

APU_PW RGD[1 2,7]

FCH_PWR GD[14]

+5VS

10_0402 _5%

VSUM-

VSUM+

VSUM-

H_PROCHOT#[38,7]

12

APU_IMON[31]

+5VS

PR938

PR938 0_0402_ 5%

0_0402_ 5%

PR942

@

PR923

10_0402 _5%

PR901 0_0402_ 5%PR901 0_04 02_5%

PR925 0_0402_ 5%PR925 0_04 02_5%

PR927 0_0402_ 5%PR927 0_04 02_5%

PR929 0_0402_ 5%PR929 0_04 02_5%

PR930 0_0402_ 5%PR930 0_04 02_5%

PR933 0_0402_ 5%PR933 0_04 02_5%

PR932 0_0402_ 5%PR932 0_04 02_5%

PR968 0_0402_ 5%

@

12

PR947

2.61K_0402_1%

12

PH904

10K_0402_5%_ERTJ0ER103J

12

PC946

0.1U_060 3_50V7K

P

903

C

390P_04 02_50V7K

12

C

905

P

12

44

45

47

46

FB_NB

VSEN_NB

ISUMP_NB

ISUMN_NB

ISL6277 HRTZ-T_TQFN48_6X6

ISUMN17ISEN1

ISUMP16ISEN2

15

14

12

PC944

12

@

4

43

42

COMP_NB

9

18

1

1 2

PC937

1 2

P

905

@

905

@

R

32.4K_0 402_1%

40

41

FCCM_NB

PGOOD_NB

RTN

FB220VSEN

1000P_0 402_50V7 K

330P_0402_50V7K

PC948

0.01U_0402_25V7K

12

39

LGATEX

PWM2_NB

COMP

FB21PGOOD

22

PC933

FCCM_NBVSUMN_NB

37

38

PHASEX

23

24

12

2.94K_0 402_1%

PR962

PR962 0_0402_ 5%

0_0402_ 5%

PR964

PR964 0_0402_ 5%

0_0402_ 5%

LGATE_NB1

PHASE_NB 1

UGATE_NB1

UGATEX

BOOTX

BOOT2

UGATE2

PHASE2

LGATE2

VDDP

PWM_Y

LGATE1

PHASE1

UGATE1

BOOT1

PR948

301_040 2_1%

PR951

12

VIN

VDD

TP

49

12

PR956

10_0402 _5%

PR966

10_0402 _5%

36

35

34

33

32

31

30

29

28

27

26

25

12

PR913

0_0603_5%

@

BOOT_NB1

BOOT2

UGATE2

PHASE2

LGATE2

LGATE1

PHASE1

UGATE1

PR939

100K_04 02_5%

10P_040 2_25V8K

100P_04 02_50V8J

PR952

137K_04 02_1%

PR954

2K_0402 _1%

12

PR924

0_0603_ 5%

12

PC920

0.22U_06 03_25V7K

1_0603_ 5%

12

+3VS

12

PC932

12

PC934

12

PC942

390P_04 02_50V7K

12

PC943

680P_04 02_50V7K

12

+APU_CORE

APU_VDD_ SEN_H [7 ]

APU_VDD_ SEN_L [7]

PR931

PC925

12

1U_0603_16V6K

CPU_B+

12

VGATE [14,31]

PR949

32.4K_0 402_1%

@

PR972

0_0603_ 5%

PR973

0_0603_ 5%

PC926

1U_0603_16V6K

12

3

5

PQ901

UGATE_NB1

PHASE_NB 1

BOOT_NB1

12

+5VALW

12

+5VS

@

PR915

2.2_060 3_5%

1 2

LGATE_NB1

TPCA8057-H_ PPAK56-8-5

UGATE1

PHASE1

2.2_060 3_5%

1 2

BOOT1

LGATE1

4

PC916

0.22U_06 03_25V7K

12

4

PQ902

PC928

PR941

0.22U_06 03_25V7K

12

PQ904

TPCA8057-H_ PPAK56-8-5

PQ904

5

4

123

TPCA8065-H_SOP-ADV8-5

4

PQ907

123

TPCA8057-H_PPAK56-8-5

5

123

5

123

PQ903

TPCA8065-H_SOP-ADV8-5

5

PQ905

PC945

0.22U_06 03_25V7K

12

LGATE2

PQ906

4

123

TPCA8065-H_SOP-ADV8-5

12

5

4

123

12

UGATE2

PHASE2

BOOT2

PR960

2.2_060 3_5%

1 2

TPCA8057-H_ PPAK56-8-5

PC907

5

123

12

PR943

<BOM Struct ure>PR94 3

4.7_120 6_5%

PC931

<BOM Struct ure>PC93 1

12

680P_06 03_50V7K

PR961

<BOM Struct ure>PR9 61

4.7_120 6_5%

PC947

<BOM Struct ure>PC9 47

680P_06 03_50V7K

2

C

12

PC908

10U_0805_25V6K

12

PR916

<BOM Struct ure>PR9 16

4.7_120 6_5%

12

PC917

<BOM Struct ure>PC9 17

680P_06 03_50V7K

ISEN1

VSUM+

VSUM-

ISEN2

VSUM+

VSUM-

U_B+

P

12

PC909

PC911

10U_0805_25V6K

0.01U_0402_25V7K

2200P_0402_50V7K

VSUMP_NB

VSUMN_NB

CPU_B+

12

PC921

PC923

10U_0805_25V6K

PR937

10K_040 2_1%

PR944

3.65K_0 402_1%

PR946

1_0402_ 1%

CPU_B+

12

PC938

PC939

10U_0805_25V6K

0.36UH_V MPI1004AR-R3 6M-Z03_30A_ 20%

12

PR958

10K_040 2_1%

PR963

3.65K_0 402_1%

12

PR965

1_0402_ 1%

12

P

L

FBMA-L18-4 53215-900 LMA90T_1812

12

PL901

0.36UH_V MPI1004AR-R3 6M-Z03_30A_ 20%

1

4

3

2

PR919

3.65K_0 402_1%

12

PR922

1_0402_ 1%

12

PC924

PC922

0.01U_0402_25V7K

2200P_0402_50V7K

PL903

0.36UH_V MPI1004AR-R3 6M-Z03_30A_ 20%

1

4

1 2

3

2

12

PR940

PR940 10K_040 2_1%

10K_040 2_1%

12

PC940

PC941

0.01U_0402_25V7K

2200P_0402_50V7K

PL904

1

4

1 2

3

2

PR959

PR959 10K_040 2_1%

10K_040 2_1%

1

902

12

1

+

PC906

2

100U_25V_M

+

B

1

+

PC949

2

68U_25V_M

+APU_CORE_NB

+APU_CORE_NB Iocp=39A

ISEN2

ISEN1

+APU_CORE

+APU_CORE Iocp=60A

+APU_CORE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2011/04/18 2015/07/08

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size D ocument Numb er Rev

Custom

Date: Sheet of

CPU_COREP

45 51Tuesday, March 12, 2013

1

45 51Tuesday, March 12, 2013

1.0

5

4

3

2

1

+CPU_CORE_NB

+

PU_CORE

A

12

D D

C C

1001

1001 PC

PC

22U_0603_6.3V6K

12

1012

1012 PC

PC

22U_0603_6.3V6K

+APU_CORE

12

PC1002

22U_0603_6.3V6K

12

PC1013

22U_0603_6.3V6K

12

PC1017

@

22U_0603_6.3V6K

12

PC1003

22U_0603_6.3V6K

12

PC1014

22U_0603_6.3V6K

12

PC1018

@

22U_0603_6.3V6K

12

PC1005

PC1004

22U_0603_6.3V6K

12

PC1015

22U_0603_6.3V6K

12

PC1019

@

22U_0603_6.3V6K

PC1005

PC1016

+

PU_CORE

C

12

22U_0603_6.3V6K

12

22U_0603_6.3V6K

+

PU_CORE_NB

A

12

PC1006

PC1007

22U_0603_6.3V6K

1

+

PC1020

2

330U_D2_2VM_R7M

12

PC1008

22U_0603_6.3V6K

1

+

PC1021

2

PC1010

PC1009

22U_0603_6.3V6K

@

330U_D2_2VM_R7M

12

PC1011

22U_0603_6.3V6K

10U_0603_6.3V6K

1

+

1022

1022 PC

PC

2

330U_D2_2VM_R9M

1

+

1026

@

PC

2

330U_D2_2VM_R7M

B B

1

+

PC1023

2

330U_D2_2VM_R9M

1

+

PC1024

2

330U_D2_2VM_R9M

1

+

PC1025

2

330U_D2_2VM_R9M

PC1027

22U_0603_6.3V6K

+1.2VS

12

PC1029

PC1030

PC1028

10U_0603_6.3V6K

PC1030

10U_0603_6.3V6K

12

PC1031

PC1032

10U_0603_6.3V6K

12

PC1033

10U_0603_6.3V6K

+1.2VS

A A

Security Class ification

2011/04/ 18

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/04/ 18

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu ment Number Rev

A3

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

46 51Tuesday, March 12, 201 3

1

1.0

5

4

3

2

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date

1

PhaseItem

ase on EE's request for fine tune power sequence. Change PR866 from 2.49k to 130k.P44 2013.1.11

B

1

D D

2

3

4

Base on must meet EUP spec, change power design.

5

6

Base on must meet EUP spec, change power design. P39 Add PR336, PR338, PR337, PR339, PQ319.

Base on must meet EUP spec, change power design. From 0.2 to 0.32013.1.11

7

Change PR860 from 604ohm to 866ohm.For fine tune OCP set up point of VGA core. From 0.1 to 0.22013.1.11P44

Change PR861 from 47k to 91k.Base on EE's request for fine tune power sequence. From 0.1 to 0.22013.1.11P44

Remove PR110, PC108, PR114, PC109, PR109, PC107,PU101, PR111, PD101, PR138, PR116, PR112, PD105, PR125, PR128, PC114, PR129, PQ101, PD104, PR123, PR124, PC115, PR131, PC117, PR103, PR104, PR105, PD102, PQ102, PR106, PR107, PQ103, PQ104, PR108, PR118, PR121, PC113, PR127, PQ106, PQ105, PR120, PR115, PC110, PC112, PR126, PR119, PR122, PD103.

RemovePQ315, PR328, PR329, PQ316, PD304, PD301, PD302, PQ303, PR303, PR304, PQ306, PQ309.P39Base on must meet EUP spec, change power design.

Remove PR417, PC420, PQ407, PR420, PC424.

P40

Add PR411. Change PR418 from 47K to 2.2K.

2013.1.11 From 0.2 to 0.3

From 0.1 to 0.2

From 0.2 to 0.3P37 2013.1.11

8

C C

9

10

11

12

13

14

15

16

B B

17

18

19

20

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2011/04/18 2015/07/08

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PIR (PWR)

C38-G series Chief River Schematic

47 51Tuesday, March 12, 2013

1

1.0

5

S

h LayoutPhase DescriptionNo. BOMDate

c

D

V/FVT V V

S

SDV/FVT V V V

D D

SDV/FVT V V V

0

12/11/22

2

2012/11/22

2012/11/22 VV

SDV/FVT V V

2012/11/22

2012/11/22 VVSDV/FVT V

2012/11/22 V V VSDV/FVT

SDV/FVT V

2012/11/22 V V VSDV/FVT

SDV/FVT

2013/1/10 X V VSDV/FVT

SDV/FVT

C C

SDV/FVT

2013/1/10 V V

2013/1/11

SDV/FVT

No.1 Page 5, Delete for Sun Pro M2

No.2 Page 17, Delete for Sun Pro M2

V

C17,C18,C19,C20 ,C21,C22,C23,C2 4,C25,C26,C27, C28,C29,C30,C31 ,C32 Delete PCIE_CRX _GTX_P8~15 P CIE_CTX_C_GRX_ P8~15 PCIE_C TX_GRX_P8~15 PCIE_CRX _GTX_N8~15 P CIE_CTX_C_GRX_ N8~15 PCIE_C TX_GRX_N8~15

C1400,C1417,C14 18,C1419,C1420, C1421,C1422,C1 423,C1424,C1425 ,C1426,C1427,C1 428,C1429,C1430 ,C1431 Delet PCIE_CRX_ C_GTX_P8~15 PCIE_CRX_ C_GTX_N8~15

No.3 Page 17 ,U1401 change Part Num ber from SA000 047H50 to SA000 06BA30 for Sun Pro M2

No.4

VSDV/FVT

No.5 Page 19, Reserv ed T1406,T1407 for Sun Pro M2

No.6

No.7

No.8

No.9 Page 20, L1405 change Part Num ber from SM010 009U00 to SM010 00AX00 for Sun Pro M2 Spec Sug getion 120 to 220 ohm

VV2012/11/22

No.10

No.11 Page 2 0, Delete Thame s&Seymour reser ved

VVV2012/11/22

Page 24, Delete for Sun Pro M2 no Channel B C1621, C1622,C1623,C16 24,C1625,C1626 ,C1627,C1628,C1 629,C1630,C1631 ,C1632,C1633,C1 634,C1635,R146 2,R1463 C1636, C1637,C1638,C16 39,C1640,C1641 ,C1642,C1643,C1 644,C1645,C1646 ,C1647,C1648,C1 649,C1650,R146 4,R1465 C1651, C1652,C1653,C16 54,C1655,C1656 ,C1657,C1658,C1 659,C1660,C1661 ,C1662,C1663,C1 664,C1665,C156 9 C1666, C1667,R1504,R15 04,R1505,R1505 ,R1506,R1507,R1 508,R1509,R1510 ,R1510,R1511,R1 511,R1512,C157 0 R1513, R1514,R1515,R15 16,R1517,R1518 ,R1519,R1520,R1 521,R1522,R1523 ,R1524,R1525,R1 526,R1527,U140 9,U1410,U1411,U 1412

Page 18, Reserv ed D1401 for Su n Pro M2 PX5.5

Page 19, Delete PX4.0 and PX5. 0 schematic C1459, C1460,C1461,C14 62,C1463,D1400 ,Q1401,Q1402,Q1 403A,Q1403B,Q14 04,Q1405,Q1406, R1401,R1438,R1 439,,R1440, R1442, R1460,R1461,U14 02,U1403

Page 20, Delete DGPU Display P ower not need reserved C1472, C1473,C1474,C14 75,C1477,C1478 ,C1479,C1480,C1 481,C1482,C1483 ,C1484,C1487,C1 488

Page 20, Delete R1457,R1458 ,B ecause the Sun Pro M2 AW28,AW 18 are NC.

R1407, R1408,R1409,R14 10,R1411,R1412 ,R1413,R1414,R1 415,R1416,R1417 ,R1466,R1467,R1 468,R1469,R147 1

Page 12 U2 chan ge Part Number from SA000066K 10 to SA000066K 60No.12

No.13

No.14

No.15

VVX

X2013 /1/11

VV

Page 31, for Po wer Eulot 6 mod fiy Delete net FSTCHG,BAT T_LEN#

Page 18, for fi ne tune VGA Pow er saving Stuff C1441

Page 19, for fi ne tune VGA Pow er Sequence R1445 change value fr om 20K to 470K R1446 change value fr om 20K to 10K

4

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

EE modify list

LA-8126P

Tuesday, March 12, 2013

1.0

48 51

1

1.0

5

S

h LayoutPhase DescriptionNo. BOMDate

c

2013/1/10SIT

2013/1/10

I

T 2013/2/1

S

D D

2013/2/1SIT VV

2013/2/20

2013/3/05

2013/3/12

C C

No.1

No.2

No.3

No.4

No.5

No.6

No.7

No.8

V VSIT

V V

V

VVV

V

VSIT

V

VSIT

V

VSIT

VSIT 20 13/3/12

V

Page 35, for Po wer Eulot 6 mod fiy Un-Stu ff @ Q2408,R246 3

Page 33, for To uch Pad Module requirment Stuff R2470

Page 07, for AP U_SID and APU_S IC voltage smo thly Stuff C69

Page 26, for Lo go LED brightne ss change Resi stor Valve from 4.99K to 1.6K

Page 36, for de lete Discharge circuit ,remov e R2324,Q2314,R 2321,Q2309

Page 33, for Fa ctory issue ,re move JBT1

Page 25, for co st down ,not ne ed reserved fo r EC ,non-stuff Q2107,R2177,R2 178

Page 36, for cu stomer request , Stuff R2302, R2303,Q2300,Q23 02

4

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

EE modify list

LA-8126P

Tuesday, March 12, 2013

1.0

49 51

1

1.0

5

S

h LayoutPhase DescriptionNo. BOMDate

c

D D

C C

4

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

EE modify list

LA-8126P

Tuesday, March 12, 2013

1.0

50 51

1

1.0

5

S

h LayoutPhase DescriptionNo. BOMDate

c

D D

C C

4

3

2

1

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

EE modify list

LA-8126P

Tuesday, March 12, 2013

1.0

51 51

1

1.0