Compal LA-8127P VALEA, ThinkPad Edge E455, ThinkPad Edge E545, LA-8127P VALEB Schematic

1 1

Compal Confidential

2 2

VALEA/VALEB Schematics Document

AMD APU Richland FS1r2 + FCH Bolton-M3 + GPU Sun Pro M2

2012-11-22

3 3

4 4

REV:1.0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

Cover Page

LA-8127P

1 51Tuesday, March 12, 2013

1.0

ompal confidential

ile Name : VALEA/VALEB

n Pro M2

1 1

R 128M16/256M16 DDR3 x 4

Page 17

～～～～

LVDS translator

RTD2132S

Page 25

HDMI Conn.

Page 27

4 * x1 PCI-E 2.0

LVDS Conn.

Page 26

GPP1GPP3

CardReader

2 2

4 in 1 Conn.

PCI Express Mini card Slot 1

WLAN

Page 33

RTS5229

USB(BT)

PCI-E(WLAN)

CRT CONN

Page 28

GPP0

LAN

RTL 8111F

FCH CRT (VGA DAC)

SPI ROM 4MB

3 3

Sub board

Power Board

LAN

Page 35

15" only

ODD board

G Sensor

ST LIS34ALTR

Audio Jack+ USB2.0

DP Port0

DP Port2

DP Port1

Page 13

Page 30

n2PCIE x 8

AMD FS1r2 APU

ack Point

Page 33

Click Pad

Richland uPGA 722 pin 35mm x 35mm

Page 5

x4 UMI Gen. 1

2.5GT/s per lane

Bolton M3

uFCBGA-656

24.5mm x 24.5mm

Page 12

LPC BUS

ENE KB9012

Page 33

Page 31

emory BUS(DDRIII)

～～～～

AZALIA

14*USB2.0/ 4*USB3.0,10*USB2.0

6*SATA serial

～～～～

Int.KBD

Page 33

Dual Channel

1.5V DDRIII 1600 (1866)

SATA0

SATA1

04pin DDRIII-SO-DIMM X2

BANK 0, 1, 2

Page 10

～～～～

2Channel Speaker

Audio Codec

CX20671-21Z

Page 29

CMOS Camera

BlueTooth CONN

USB PORT 3.0 x3

Internal MIC

Audio Jacks

Combo jack

Page 26

Page 32

Page 34

USB PORT 2.0 x1 +Charger

WLAN

Page 33

Finger Printer

UPEK TCS5DA6C0

SATA3.0 HDD CONN

SATA ODD CONN

Page 30

4 4

FingerPrint

Card reader

Thermal Sensor

Fintek 5303

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

Page 32

Compal Secret Data

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

Block Diagrams

LA-8127P

2 51Tuesday, March 12, 2013

1.0

Voltage Rails

Power Plane Description

B+

+APU_CORE

+APU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU

1 1

+1.5V ON

+0.75VS OFFON OFF0.75V switched power rail for DDR terminator

+1.2VS ON OFF OFF

+2.5VS

+1.1VALW 1.1V switched power rail for FCH ON ON*ON

+1.1VS

+1.5VS OFF1.5V switched power rail ON OFF

+VGA_CORE OFFOFFON

+1.5VGS

+1.8VGS OFFON OFF1.8V switched power rail

+0.95VGS ON OFF OFF0.95V switched power rail for VGA

+3VALW

+3VS_WLAN ON OFF

+3VS

2 2

+5VALW

+5VS

+VSB ON ON*

+RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

Device Address Address

Smart Battery

3 3

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for APU

1.5V power rail for APU VDDIO and DDR

1.2V (VDDR, VDDP) switched power rail for APU

2.5V for APU VDDA

0.95-1.2V switched power rail

1.5V switched power rail

3.3V always on power rail

3.3V power rail for WLAN

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

RTC power

EC SM Bus2 address

0001-011xb

HEX

15H

Device

F75303 (DDR,VRAM,CPUCORE)1001-101xb

SB-TSI

Sun Pro M2

LVDS translator

S0 S3 S5

N/A N/A N/A

ON OFF

ON OFF OFF1.1V switched power rail for FCH

ON OFF

1001-100xb

1000-0010b

N/AN/AN/A

OFF

ON ON*

OFF

ON*

OFF

OFFON

ONON

HEX

9AH

98H

82H

H Hudson-M2/3

F SATA Port List

ATA0

SATA1

SATA2

SATA3

SATA4

SATA5

HDD

ODD

BOM Structure

UMA@ : UMA only DIS@ : DIS muxless

CMOS@ : USB camera

CONN@ : ME components

Comal

PCIE Port List

WLAN

Card Reader

APUFCH

CIE0

PCIE1

PCIE2

PCIE3

PCIE0

PCIE1

PCIE2

PCIE3

H Hudson-M2/3

F USB Port List

SB1.1

Port0

Port1

USB2.0

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Port8

Port9

Port10

Port11

Port12

Port13

USB2.0 Port

WLAN

CMOS

USB 3.0

X76@, H1G@, S1G@ : VRAM

BOM option and stencil

SDV:

FCH SMB0

Device Address

DDR DIMM1 (FCH_SMB0)

DDR DIMM2 (FCH_SMB0)

4 4

WLAN (FCH_SMB0)

Security ROM

1001-000xb

1001-001xb

(FCH_SMB0)

HEX

Stencil Memo

CMOS@/DIS@ + X76@

PJ201,PJ401,PJ502,PJ503,PJ504,PJ601,PJ603,PJ604, PJ701,PJ702,PJ703,PJ704,J1,J2301,J2401,J2402,J2403 PJ402,PJ403,PJ501,PJ602,PJ801,PJ802,PJ803,PJ805

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-8127P

3 51Tuesday, March 12, 2013

1.0

Power-Up/Down Sequence

‧

All the ASIC supplies, except for VDDR3, must fully reach their respective

ominal voltages within 20 ms of the start of the ramp-up sequence, though a

n shorter ramp-up duration is preferred. There is no timing requirement on the ramp up of VDDR3 relative to other power rails.

The external pull-up resistors on the DDC/AUX signals (if applicable) should

‧

amp up before or after both VDDC and VDD_CT have ramped up.

D D

‧

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC

hould reach 90% before VDD_CT starts to ramp up (or vice versa).

For power down, reversing the ramp-up sequence is recommended.

‧

APU

FCH

GPIO191

U_PCIE_RST#

S_RST#

AND GATE

U_RST#

PERSTB

GPU

VDDR3(3.3VGS)

PCIE_VDDC(0.95VGS)

GPIO192

GPIO51

PXS_PWREN

VGA_PWRGD

VDDR1(1.5VGS)

VDDC/VDDCI(1.12V)

PXS_PWREN

VDD_CT(1.8VGS)

C C

PERSTb

+3VS

+3VALW

MOS

Regulator

+3VGS

+0.95VGS

+1.8VS

MOS

+1.8VGS

REFCLK

Straps Reset

B+

PWM

+VGA_CORE

+1.5VS

MOS

+1.5VGS

Straps Valid

Global ASIC Reset

PS_3[ 0 ]PS_3[ 1 ]

00 1

T4+16clock

R_pu R_pd

R1430 R1436

NC 4.75K

R1430

8.45K

R1430

4.53K 2K

R1430

6.98K

R1430

4.53k 4.99K

R1430

3.24k 5.62k

R1430

3.4k

R1430

4.75K

R1436

4.99K

R1436

10k

R1436

ZZZ2

ZZZ1

S1G

S1G@

X7635939L09

ZZZ4

S2G

S2G@

X7635939L11

ZZZ2

H1G

H1G@

X7635939L10

ZZZ5

M2G

M2G@

X7635939L12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

dGPU Block Diagram

Custom

dGPU Block Diagram

LA-8127P

4 51Tuesday, March 12, 2013

1.0

SUN PRO VRAM STRAP

B B

A A

Vendor

H5TQ2G63DFR-11C SA00003YO70

K4W2G1646E-BC11 SA00005SH00

MT41J128M16JT-093G SA000067510 FBGA Code:D9PTD

K4W4G1646B-HC11 SA000068R00

MT41K256M16HA-107G SA000065D00 FBGA Code:D9PZD

MT41J128M16JT-107G SA00005SM30 FBGA Code:D9PRS

K4W2G1646E-BC1A SA000068U10

PS_3[ 2 ]

0 0

0 1

1 1

IE_CRX_GTX_P[0..7][17]

IE_CRX_GTX_N[0..7][17]

PU1A

I EXPRESS

GFX_RXP0 GFX_RXN0 GFX_RXP1 GFX_RXN1 GFX_RXP2 GFX_RXN2

GPP GRAPHICS

UMI

GFX_TXP0

_ _

GFX_TXN0

P P

GFX_TXP1

GFX_TXN1

_ _

GFX_TXP2

P P

GFX_TXN2

_ P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9 P_GFX_TXN9

P_GFX_TXP10 P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11 P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13 P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14 P_GFX_TXP15 P_GFX_TXN15

P_GPP_TXP0 P_GPP_TXN0 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3

P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3

P_ZVSS

AB2

IE_CTX_C_GRX_P0

AB1

IE_CTX_C_GRX_N0

AA3

IE_CTX_C_GRX_P1

AA2

IE_CTX_C_GRX_N1

IE_CTX_C_GRX_P2

IE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P3

PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P4

PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P5

PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P6

PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P7

PCIE_CTX_C_GRX_N7

T5 T4 T2 T1 R3 R2 P5 P4 P2 P1 N3 N2 M5 M4 M2 M1

AD5

PCIE_CTX_C_DRX_P0

AD4

PCIE_CTX_C_DRX_N0

AD2

PCIE_CTX_C_DRX_P1

AD1

PCIE_CTX_C_DRX_N1

AC3 AC2 AB5

PCIE_CTX_C_DRX_P3

AB4

PCIE_CTX_C_DRX_N3

AG2

UMI_TXP0_C

AG3

UMI_TXN0_C

AF4

UMI_TXP1_C

AF5

UMI_TXN1_C

AF1

UMI_TXP2_C

AF2

UMI_TXN2_C

AE2

UMI_TXP3_C

AE3

UMI_TXN3_C

AH11

P_ZVSS

C C

C C7 .1U_0402_16V7KDIS@C7 .1U_0402_16V7KDIS@ C8 .1U_0402_16V7KDIS@C8 .1U_0402_16V7KDIS@ C9 .1U_0402_16V7KDIS@C9 .1U_0402_16V7KDIS@ C10 .1U_0402_16V7KDIS@C10 .1U_0402_16V7KDIS@ C11 .1U_0402_16V7KDIS@C11 .1U_0402_16V7KDIS@ C12 .1U_0402_16V7KDIS@C12 .1U_0402_16V7KDIS@ C13 .1U_0402_16V7KDIS@C13 .1U_0402_16V7KDIS@ C14 .1U_0402_16V7KDIS@C14 .1U_0402_16V7KDIS@ C15 .1U_0402_16V7KDIS@C15 .1U_0402_16V7KDIS@ C16 .1U_0402_16V7KDIS@C16 .1U_0402_16V7KDIS@

1 2

R2 196_0402_1%R2 196_0402_1%

Power Sequence of APU

IE_CRX_GTX_P0

C C

IE_CRX_GTX_N0

P P

IE_CRX_GTX_P1

1 1

2 2

PCIE_CRX_DTX_P0[35]

LAN WLAN

Card Reader

3 3

PCIE_CRX_DTX_N0[35] PCIE_CRX_DTX_P1[33] PCIE_CRX_DTX_N1[33]

PCIE_CRX_DTX_P3[35] PCIE_CRX_DTX_N3[35]

UMI_RXP0[12] UMI_RXN0[12] UMI_RXP1[12] UMI_RXN1[12] UMI_RXP2[12] UMI_RXN2[12] UMI_RXP3[12] UMI_RXN3[12]

+1.2VS

IE_CRX_GTX_N1

C C

IE_CRX_GTX_P2

P P

IE_CRX_GTX_N2

C PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

1 2

R1 196_0402_1%R1 196_0402_1%

P_ZVDDP

AB8

AB7

AA9

AA8

AA5

AA6

P_GFX_RXP3

P_GFX_RXN3

P_GFX_RXP4

P_GFX_RXN4

P_GFX_RXP5

P_GFX_RXN5

P_GFX_RXP6

P_GFX_RXN6

P_GFX_RXP7

P_GFX_RXN7

P_GFX_RXP8

P_GFX_RXN8

P_GFX_RXP9

P_GFX_RXN9

P_GFX_RXP10

P_GFX_RXN10

P_GFX_RXP11

P_GFX_RXN11

P_GFX_RXP12

P_GFX_RXN12

P_GFX_RXP13

P_GFX_RXN13

P_GFX_RXP14

P_GFX_RXN14

P_GFX_RXP15

P_GFX_RXN15

AE5

P_GPP_RXP0

AE6

P_GPP_RXN0

AD8

P_GPP_RXP1

AD7

P_GPP_RXN1

AC9

P_GPP_RXP2

AC8

P_GPP_RXN2

AC5

P_GPP_RXP3

AC6

P_GPP_RXN3

AG8

P_UMI_RXP0

AG9

P_UMI_RXN0

AG6

P_UMI_RXP1

AG5

P_UMI_RXN1

AF7

P_UMI_RXP2

AF8

P_UMI_RXN2

AE8

P_UMI_RXP3

AE9

P_UMI_RXN3

AG11

P_ZVDDP

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

1 2

1U_0402_16V7KDIS@

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1U_0402_16V7KDIS@ 1U_0402_16V7KDIS@

1U_0402_16V7KDIS@

1 .

1 . 2 .

2 . 3 .

3 . 4 .

4 . 5 .

5 . 6 .

6 .

C33 .1U_0402_16V7KC33 .1U_0402_16V7K C34 .1U_0402_16V7KC34 .1U_0402_16V7K C123 .1U_0402_16V7KC123 .1U_0402_16V7K C124 .1U_0402_16V7KC124 .1U_0402_16V7K

C35 .1U_0402_16V7KC35 .1U_0402_16V7K C36 .1U_0402_16V7KC36 .1U_0402_16V7K

C37 .1U_0402_16V7KC37 .1U_0402_16V7K C38 .1U_0402_16V7KC38 .1U_0402_16V7K C39 .1U_0402_16V7KC39 .1U_0402_16V7K C40 .1U_0402_16V7KC40 .1U_0402_16V7K C41 .1U_0402_16V7KC41 .1U_0402_16V7K C42 .1U_0402_16V7KC42 .1U_0402_16V7K C43 .1U_0402_16V7KC43 .1U_0402_16V7K C44 .1U_0402_16V7KC44 .1U_0402_16V7K

IE_CTX_GRX_P0

C C

IE_CTX_GRX_N0

P P

IE_CTX_GRX_P1

IE_CTX_GRX_N1

C C

IE_CTX_GRX_P2

P P

IE_CTX_GRX_N2

C PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

IE_CTX_GRX_P[0..7] [17]

IE_CTX_GRX_N[0..7] [17]

SDV/FVT, NO.1SDV/FVT, NO.1

PCIE_CTX_DRX_P0 [35] PCIE_CTX_DRX_N0 [35] PCIE_CTX_DRX_P1 [33] PCIE_CTX_DRX_N1 [33]

PCIE_CTX_DRX_P3 [35] PCIE_CTX_DRX_N3 [35]

UMI_TXP0 [12] UMI_TXN0 [12] UMI_TXP1 [12] UMI_TXN1 [12] UMI_TXP2 [12] UMI_TXN2 [12] UMI_TXP3 [12] UMI_TXN3 [12]

+1.5V

+2.5VS

Group A

+1.5VS

+APU_CORE

+APU_CORE_NB

Group B

+1.2VS

4 4

Security Classification

2012/11/22 2015/11/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

FS1r2 PCIE/UMI

LA-8127P

5 51Tuesday, March 12, 2013

1.0

1 1

PU1B

MORY CHANNEL A

DDRA_SMA[15..0][10]

DDRA_SBS0#[10] DDRA_SBS1#[10] DDRA_SBS2#[10] DDRA_SDM[7..0][10]

2 2

DDRA_SDQS0[10] DDRA_SDQS0#[10] DDRA_SDQS1[10] DDRA_SDQS1#[10] DDRA_SDQS2[10] DDRA_SDQS2#[10] DDRA_SDQS3[10] DDRA_SDQS3#[10] DDRA_SDQS4[10] DDRA_SDQS4#[10] DDRA_SDQS5[10] DDRA_SDQS5#[10] DDRA_SDQS6[10] DDRA_SDQS6#[10] DDRA_SDQS7[10] DDRA_SDQS7#[10]

DDRA_CLK0[10] DDRA_CLK0#[10] DDRA_CLK1[10] DDRA_CLK1#[10]

DDRA_CKE0[10] DDRA_CKE1[10]

DDRA_ODT0[10] DDRA_ODT1[10]

3 3

DDRA_SCS0#[10] DDRA_SCS1#[10]

DDRA_SRAS#[10] DDRA_SCAS#[10] DDRA_SWE#[10]

MEM_MA_RST#[10] MEM_MA_EVENT#[10]

+MEM_VREF

+1.5V

15mil

Place them close to APU within 1"

DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15

DDRA_SBS0# DDRA_SBS1# DDRA_SBS2#

DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7

DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7#

DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1#

DDRA_CKE0 DDRA_CKE1

DDRA_ODT0 DDRA_ODT1

DDRA_SCS0# DDRA_SCS1#

DDRA_SRAS# DDRA_SCAS# DDRA_SWE#

MEM_MA_RST#

MEM_MA_EVENT#

1 2

R3 39.2_0402_1%R3 39.2_0402_1%

M_ZVDDIO

M21

M22

AA25

AD27 AC23 AD19 AC15

AE26 AD26

AB22 AA22 AB18 AA18 AA14 AA15

AA27

AA26

W24 W23

W20

W21

U20 R20 R21 P22 P21 N24 N23 N20 N21

U23

L24

L21 L20

U24 U21

L23

E14

J17 E21 F25

G14 H14 G18 H18

J21 H21 E27 E26

T21 T22 R23 R24

H28 H27

Y25

V22

V21

H25 T24

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7

MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1

MA_CKE0 MA_CKE1

MA_ODT0 MA_ODT1

MA_CS_L0 MA_CS_L1

MA_RAS_L MA_CAS_L MA_WE_L

MA_RESET_L MA_EVENT_L

M_VREF

M_ZVDDIO

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7

MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15

MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23

MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31

MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39

MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47

MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55

MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

E13 J13 H15 J15 H13 F13 F15 E15

H17 F17 E19 J19 G16 H16 H19 F19

H20 F21 J23 H23 G20 E20 G22 H22

G24 E25 G27 G26 F23 H24 E28 F27

AB28 AC27 AD25 AA24 AE28 AD28 AB26 AC25

Y23 AA23 Y21 AA20 AB24 AD24 AA21 AC21

AA19 AC19 AC17 AA17 AB20 Y19 AD18 AD17

AA16 Y15 AA13 AC13 Y17 AB16 AB14 Y13

DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7

DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15

DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23

DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31

DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39

DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47

DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55

DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

DDRA_SDQ[63..0] [10]

DDRB_SMA[15..0][11]

DDRB_SBS0#[11] DDRB_SBS1#[11] DDRB_SBS2#[11] DDRB_SDM[7..0][11]

DDRB_SDQS0[11] DDRB_SDQS0#[11] DDRB_SDQS1[11] DDRB_SDQS1#[11] DDRB_SDQS2[11] DDRB_SDQS2#[11] DDRB_SDQS3[11] DDRB_SDQS3#[11] DDRB_SDQS4[11] DDRB_SDQS4#[11] DDRB_SDQS5[11] DDRB_SDQS5#[11] DDRB_SDQS6[11] DDRB_SDQS6#[11] DDRB_SDQS7[11] DDRB_SDQS7#[11]

DDRB_CLK0[11] DDRB_CLK0#[11] DDRB_CLK1[11] DDRB_CLK1#[11]

DDRB_CKE0[11] DDRB_CKE1[11]

DDRB_ODT0[11] DDRB_ODT1[11]

DDRB_SCS0#[11] DDRB_SCS1#[11]

DDRB_SRAS#[11] DDRB_SCAS#[11] DDRB_SWE#[11]

MEM_MB_RST#[11] MEM_MB_EVENT#[11]

DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15

DDRB_SBS0# DDRB_SBS1# DDRB_SBS2#

DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7

DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7#

DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1#

DDRB_CKE0 DDRB_CKE1

DDRB_ODT0 DDRB_ODT1

DDRB_SCS0# DDRB_SCS1#

DDRB_SRAS# DDRB_SCAS# DDRB_SWE#

MEM_MB_RST# MEM_MB_EVENT#

PU1C

MORY CHANNEL B

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1

MB_CKE0 MB_CKE1

MB_ODT0 MB_ODT1

MB_CS_L0 MB_CS_L1

MB_RAS_L MB_CAS_L MB_WE_L

MB_RESET_L MB_EVENT_L

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

M28 M27 M24 M25

W26

AF25 AG22 AH18 AD14

AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14

W27

T27 P24 P25 N27 N26

L26 U26 L27 K27

K25 K24

U27 T28 K28

D14 A18 A22 C25

C15 B15 E18 D18 E22 D22 B26 A26

R26 R27 P27 P28

J26 J27

Y28

V25 Y27

V24 V27 V28

J25 T25

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7

MB_DATA8

MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15

MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23

MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31

MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39

MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47

MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55

MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

A14 B14 D16 E16 B13 C13 B16 A16

C17 B18 B20 A20 E17 B17 B19 C19

C21 B22 C23 A24 D20 B21 E23 B23

E24 B25 B27 D28 B24 D24 D26 C27

AG26 AH26 AF23 AG23 AG27 AF27 AH24 AE24

AE22 AH22 AE20 AH20 AD23 AD22 AD21 AD20

AF19 AE18 AE16 AH16 AG20 AG19 AF17 AD16

AG15 AD15 AG13 AD13 AG16 AF15 AE14 AF13

DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7

DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15

DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23

DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31

DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39

DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47

DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55

DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63

DDRB_SDQ[63..0] [11]

EVENT# pull high 0.75V reference voltage

+1.5V

4 4

1 2

R5 1K_0402_5%R5 1K_0402_5%

1 2

R6 1K_0402_5%R6 1K_0402_5%

MEM_MA_EVENT#

MEM_MB_EVENT# +MEM_VREF

1K_0402_1%

+1.5V

1 2

C45

C45 1000P_0402_50V7K

1000P_0402_50V7K

15mil

C46

C46 .1U_0402_16V7K

.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

FS1r2 DDRIII Memory I/F

LA-8127P

6 51Tuesday, March 12, 2013

1.0

Place near APU

1 2

2 .1U_0402_16V7K

0_TXP0_C[25]

0_TXN0_C[25]

_VGA_TXP0[13]

1 1

2 2

+1.5V

3 3

4 4

1 2

R49 1K_0402_5%R49 1K_0402_5%

1 2

R52 1K_0402_5%R52 1K_0402_5%

1 2

R32 1K_0402_5%R32 1K_0402_5%

1 2

R37 1K_0402_5%R37 1K_0402_5%

1 2

R39 1K_0402_5%R39 1K_0402_5%

R36 1K_0402_5%R36 1K_0402_5%

1 2

R33 1K_0402_5%@R33 1K_0402_5%@

1 2

R38 1K_0402_5%@R38 1K_0402_5%@

1 2

R40 1K_0402_5%@R40 1K_0402_5%@

1 2

R41 1K_0402_5%R41 1K_0402_5%

1 2

R43 1K_0402_5%R43 1K_0402_5%

1 2

R46 1K_0402_5%R46 1K_0402_5%

+1.5VS

1 2

R54 300_0402_5%R54 300_0402_5%

1 2

R57 300_0402_5%R57 300_0402_5%

+3VS

1 2

R60 10K_0402_5%R60 10K_0402_5%

1 2

R61 10K_0402_5%R61 10K_0402_5%

Aux signal are re-configured as I2C signals for DDC. APU AUX pin are 3.3V tolerant Default follow PAWGX setting for pull-high resistor value

M M

_VGA_TXN0[13]

_VGA_TXP1[13]

_VGA_TXN1[13]

ML_VGA_TXP2[13] ML_VGA_TXN2[13]

ML_VGA_TXP3[13] ML_VGA_TXN3[13]

HDMI_TX2P[27] HDMI_TX2N[27]

HDMI_TX1P[27] HDMI_TX1N[27]

HDMI_TX0P[27] HDMI_TX0N[27]

HDMI_CLKP[27] HDMI_CLKN[27]

Route as differential with VSS_SENSE

ALLOW_STOP

APU_DBREQ#

APU_TRST#

APU_RST#

APU_PWRGD

APU_TCK

APU_TMS

APU_TDI

APU_SVT

APU_SVC

APU_SVD

APU_SIC

APU_SID

ALERT_L

HDMI_CLK

HDMI_DATA

1 2

7 .1U_0402_16V7K

1 2

1 .1U_0402_16V7K

1 2

2 .1U_0402_16V7K

1 2

3 .1U_0402_16V7K

1 2

4 .1U_0402_16V7K

1 2

C65 .1U_0402_16V7KC65 .1U_0402_16V7K

1 2

C66 .1U_0402_16V7KC66 .1U_0402_16V7K

1 2

C67 .1U_0402_16V7KC67 .1U_0402_16V7K

1 2

C68 .1U_0402_16V7KC68 .1U_0402_16V7K

1 2

C50 .1U_0402_16V7KC50 .1U_0402_16V7K

1 2

C51 .1U_0402_16V7KC51 .1U_0402_16V7K

1 2

C55 .1U_0402_16V7KC55 .1U_0402_16V7K

1 2

C56 .1U_0402_16V7KC56 .1U_0402_16V7K

1 2

C57 .1U_0402_16V7KC57 .1U_0402_16V7K

1 2

C58 .1U_0402_16V7KC58 .1U_0402_16V7K

1 2

C59 .1U_0402_16V7KC59 .1U_0402_16V7K

1 2

C60 .1U_0402_16V7KC60 .1U_0402_16V7K

APU_CLK[12] APU_CLK#[12]

APU_DISP_CLK[12] APU_DISP_CLK#[12]

APU_SVC[45] APU_SVD[45]

APU_SVT[45]

T32T32

APU_RST#[12] APU_PWRGD[12,45]

APU_PROCHOT#[12]

APU_VDD_SEN_L[45]

APU_VDDNB_SEN[45]

APU_VDD_SEN_H[45]

T33T33

T23T23 T24T24 T25T25 T26T26 T27T27 T28T28 T29T29

APU_CLK APU_CLK#

APU_DISP_CLK APU_DISP_CLK#

APU_SIC APU_SID

APU_RST# APU_PWRGD

APU_PROCHOT# APU_THERMTRIP# ALERT_L

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

APU_VDD_SEN_L

APU_VDDNB_SEN

T20T20

APU_VDD_SEN_H

T21T21

0_TXP0

0_TXN0

1_TXP0

1_TXN0

1_TXP1

1_TXN1

DP1_TXP2 DP1_TXN2

DP1_TXP3 DP1_TXN3

DP2_TXP0 DP2_TXN0

DP2_TXP1 DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

ALOG/DISPLAY/MISC

0_TXP0

D D

0_TXN0

0_TXP1

P P

0_TXN1

0_TXP2

0_TXN2

0_TXP3

0_TXN3

1_TXP0

D D

1_TXN0

1_TXP1

1_TXN1

To FCH

DP1_TXP2 DP1_TXN2

DP1_TXP3 DP1_TXN3

DP2_TXP0 DP2_TXN0

DP2_TXP1

HDMI

DP2_TXN1

DP2_TXP2 DP2_TXN2

DP2_TXP3 DP2_TXN3

CLKIN_H CLKIN_L

DISP_CLKIN_H DISP_CLKIN_L

SVC SVD

SVT

SIC SID

RESET_L PWROK

PROCHOT_L THERMTRIP_L ALERT_L

TDI TDO TCK TMS TRST_L DBRDY DBREQ_L

VSS_SENSE VDDP_SENSE VDDNB_SENSE VDDIO_SENSE VDD_SENSE VDDR_SENSE

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

+3VS

APU_SIC

AE11 AD11

AB11 AA11

AG12 AH12

AF10 AB12

AC10 AE12 AF12

H10

F10 G10

L3 L2

K5 K4

K2 K1

J3 J2

H5 H4

H2 H1

G3 G2

F2 F1

L9 L8

L5 L6

K8 K7

J6 J5

B3 A3

J10

F9 G9 H9

B4 C5

A5 C4

DISPLAY PORT 0

DISPLAY PORT 2 DISPLAY PORT 1

CTRL SE R. CLK

JTAG

SENSE

31.6K_0402_1%

PU1D

0_AUXP

D D

0_AUXN

1_AUXP

P P

1_AUXN

2_AUXP

2_AUXN

3_AUXP

3_AUXN

4_AUXP

D D

4_AUXN

5_AUXP

5_AUXN

DP0_HPD DP1_HPD

DISPLAY PORT MISC.

DP2_HPD DP3_HPD DP4_HPD DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24

TEST

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

DMAACTIVE_L

RSVD1 RSVD2 RSVD3

RSVD

RSVD4

C69 0.1U_0402_16V4ZC69 0.1U_0402_16V4Z

1 2

R34

3 1

SGD

BSH111_SOT23-3

3 1

BSH111_SOT23-3

0_AUXP

0_AUXN

_VGA_AUXP

_VGA_AUXN

MI_CLK

MI_DATA

E5 E6

F5 F6

G5 G6

LVDS_HPD

ML_VGA_HPD

HDMI_DET

E7 F7 G7

C6 B6 A6

DP_INT_PWM

DP_AUX_ZVSS

AD12

TEST6

M18

TEST9

N18 F11 G11 H11 J11 F12

APU_TEST18

G12

APU_TEST19

J12

APU_TEST20

H12

APU_TEST24

AE10

TEST25_H

AD10

TEST25_L

L10

TEST28_H

M10

TEST28_L

P19

TEST30_H

R19

TEST30_L

K22

APU_TEST31

T19 N19 AA12

APU_TEST35

W10

FS1R2

AC12

ALLOW_STOP

P18

TEST4

R18

TEST5

Y10 AA10 Y12 K21

1 2

R35

30K_0402_1%

SGD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

1 2

3 .1U_0402_16V7K

1 2

8 .1U_0402_16V7K

1 2

4 .1U_0402_16V7K

1 2

9 .1U_0402_16V7K

1 2

R13 150_0402_1%R13 150_0402_1%

T1T1 T2T2 T3T3 T4T4 T5T5 T6T6

R14 1K_0402_5%R14 1K_0402_5% R15 1K_0402_5%R15 1K_0402_5% R16 1K_0402_5%R16 1K_0402_5% R17 1K_0402_5%R17 1K_0402_5% R20 510_0402_1%R20 510_0402_1% R23 510_0402_1%R23 510_0402_1%

T14T14 T15T15 T7T7 T8T8

R25 39.2_0402_1%R 25 39.2_0402_1%

R26 300_0402_5%R26 300_0402_5% R27 300_0402_5%@R27 300_0402_5%@ R28 10K_0402_5%R28 10K_0402_5%

T9T9 T10T10

EC_SMB_DAAPU_SID

1 2

0_0402_5%

EC_SMB_CK

1 2

R50

@R50

R59

@R59

0_0402_5%

R44 0_0402_5%@R44 0_0402_5%@

R47

@R47

R55 0_0402_5%@R55 0_0402_5%@

R58

@R58

0_AUXP_C [25]

0_AUXN_C [25]

_VGA_AUXP_C [13]

_VGA_AUXN_C [13]

MI_CLK [27]

D D

MI_DATA [27]

LVDS_HPD [25] ML_VGA_HPD [13] HDMI_DET [27]

DP_INT_PWM [9]

T30T30 T31T31

1 2 1 2 1 2 1 2 1 2 1 2

1 2

1 2 1 2 1 2

ALLOW_STOP [12]

SIT, NO.3

1 2

0_0402_5%

1 2

0_0402_5%

2012/11/22 2015/11/22

+1.2VS

+1.5V

+3VALW

CPU TSI interface level shift

BSH111, the Vgs is: min = 0.4V Max = 1.3V

EC_SMB_DA2 [18,25,31,32]

FCH_SID [14]

EC_SMB_CK2 [18,25,31,32]

FCH_SIC [14]

Compal Secret Data

To LVDS Translater

To FCH MainLink

To HDMI

Asserted as an input to force the processor into the HTC-active state

Deciphered Date

1K_0402_5%

APU_PROCHOT#

THERMTRIP shutdown Temperature: 125 degree

ALERT_L

To EC

To FCH

To EC

To FCH

.5V

R12

1 2

R78 0_0402_5%@R78 0_0402_5%@

1K_0402_5%

APU_THERMTRIP#

+1.5V

3 1

MMBT3904_NL_SOT23-3

not used, pins are left unconnected (DG ref.)

I 20101111

_VGA_AUXP

9 1

_VGA_AUXN

0_AUXP

0_AUXN

R18

R18 10K_0402_5%

10K_0402_5%

9 1

8 1

9 1.8K_0402_5%

1 1.8K_0402_5%

LA-8127P

PROCHOT#_EC: default low/active high

_ APU_PROCHOT# : default high/ active low H_PROCHOT#: default high/ active low

2N7002K_SOT23-3

Indicates to the FCH that a thermal trip has occurred. Its assertion will cause the

+1.5V

FCH to transition the system to S5 immediately

R21

R29

R29 10K_0402_5%@

10K_0402_5%@

Title

Size Document Number Rev

Custom

Date: Sheet of

1 2

3 1

MMBT3904_NL_SOT23-3

1 2

R30 0_0402_5%@R30 0_0402_5%@

1 2

R31 0_0402_5%@R31 0_0402_5%@

Compal Electronics, Inc.

FS1r2 Display/MISC/HDT

.8K_0402_5%

H_PROCHOT#_EC [31,38]

H_PROCHOT# [38,45]

H_THERMTRIP# [14]

APU_ALERT#_FCH [13]

APU_ALERT#_EC [31]

7 51Tuesday, March 12, 2013

1.0

Power Name

VDD +APU_CORE

VDDNB +APU_CORE_NB

VDDIO +1.5V

VDDP / VDDR +1.2VS

VDDA

1 1

+2.5VS 0.5A

2 2

3 3

Consumption

5A / 3.5A

VDDR decoupling

180P_0402_50V8J

60A

44A

3.2A

180P_0402_50V8J

C1 05

+1.2VS

0.22U_0402_6.3V6K

C1 06

+APU_CORE_NB

0.22U_0402_6.3V6K

+1.5V

PU_CORE

D_1

D_2

D_3

J14

D_4

D_5

P10

VDD_6

J16

VDD_7

J18

VDD_8

VDD_9

K19

VDD_10

VDD_11

K17

VDD_12

VDD_13

VDD_14

V10

VDD_15

V18

VDD_16

VDD_17

VDD_18

L18

VDD_19

VDD_20

VDD_21

T18

VDD_22

Y14

VDD_23

AA1

VDD_24

AB6

VDD_25

AC1

VDD_26

VDD_27

VDD_28

K10

VDD_29

VDD_30

M19

VDD_31

VDDNB_1

D10

VDDNB_2

VDDNB_3

B12

VDDNB_4

VDDNB_5

VDDNB_6

A10

VDDNB_7

VDDNB_8

A11

VDDNB_9

E10

VDDNB_10

E11

VDDNB_11

C10

VDDNB_12

H26

VDDIO_1

K20

VDDIO_2

J28

VDDIO_3

K23

VDDIO_4

K26

VDDIO_5

L22

VDDIO_6

L25

VDDIO_7

L28

VDDIO_8

M20

VDDIO_9

M23

VDDIO_10

M26

VDDIO_11

N22

VDDIO_12

N25

VDDIO_13

N28

VDDIO_14

P20

VDDIO_15

P23

VDDIO_16

P26

VDDIO_17

AA28

VDDIO_18

AH6

VDDP_1

AH5

VDDP_2

AH4

VDDP_3

AH3

VDDP_4

AH7

VDDP_5

AB10

VDDA

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

PU1E

V V V V V VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62

VDDNB_13 VDDNB_14 VDDNB_15 VDDNB_16 VDDNB_17 VDDNB_18 VDDNB_19 VDDNB_20 VDDNB_21 VDDNB_22 VDDNB_23

VDDNB_CAP_1 VDDNB_CAP_2

VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36

VDDR_1 VDDR_2 VDDR_3 VDDR_4

PU_CORE

0.01U_0402_16V7K

0.22U_0402_6.3V6K

C73

+APU_CORE_NB

180P_0402_50V8J

C109

0.22U_0402_6.3V6K

C77

+1.5V

22U_0603_6.3V6M

C82

+1.5V

0.22U_0402_6.3V6K

C99

1000P_0402_50V7K

C110

PU_CORE

R11

D_32

T10

D_33

D_34

D_35

U11

D_36

W11 W13 W15 W17 W19 AB3 AD3 AD6 AE1 L1 Y6 M6 N11 N1 T3 T6 U19 U1 Y16 Y18 Y3 D4 F4 AF6 AF3 L11

C11

+APU_CORE_NB

C12 D9 D8 D12 D11 B11 A12 B10 E12 B9

K13

+APU_CORE_NB_CAP

K12

T23

+1.5V

T26 U22 U25 U28 Y26 T20 R28 R25 R22 V20 V23 V26 W22 W25 W28 Y24 G28

AG10 AH8 AH9 AH10

180P_0402_50V8J

C108

C107

0.01U_0402_16V7K

0.22U_0402_6.3V6K

C70

C74

0.22U_0402_6.3V6K

180P_0402_50V8J

C78

C79

22U_0603_6.3V6M

C84

C83

Across VDDIO and VSS split

0.22U_0402_6.3V6K

180P_0402_50V8J

C100

C101

1000P_0402_50V7K

C111

C112

0.01U_0402_16V7K

C75

C71

180P_0402_50V8J

C81

C80

22U_0603_6.3V6M

C86

C85

180P_0402_50V8J

C102

VDDR decoupling

1000P_0402_50V7K

0.22U_0402_6.3V6K

C113

180P_0402_50V8J

0.01U_0402_16V7K

180P_0402_50V8J

22U_0603_6.3V6M

C114

180P_0402_50V8J

C72

C76

0.22U_0402_6.3V6K

4.7U_0603_6.3V6K

C88

+1.2VS

4.7U_0603_6.3V6K

C89

C90

4.7U_0603_6.3V6K

C87

0.22U_0402_6.3V6K

C91

0.22U_0402_6.3V6K

C92

+APU_CORE_NB_CAP

22U_0603_6.3V6M

C216

0.22U_0402_6.3V6K

C93

C94

22U_0603_6.3V6M

C215

C214

0.22U_0402_6.3V6K

C96

C95

180P_0402_50V8J

C217

180P_0402_50V8J

330U_D2_2.5VY_R9M

180P_0402_50V8J

C136

C97

330U_D2_2.5VY_R9M

C98

Demo Board Capacitor

APU_CORE 22uF x 10

0.22uF x 2

0.01uF x 3 180pF x 2

CORE_NB 22uF x 2 10uF x 1

0.22uF x 2 180pF x 3

CORE_NB_CAP 22uF x 2 180pF x 1

PU1F

J20

S_1

S_2

S_3

W18

S_4

A15

S_5

AB17

S_6

AC22

S_7

AE21

S_8

AF24

S_9

AH23

S_10

AH25

S_11

S_12

C14

S_13

C16

S_14

VSS_15

C20

VSS_16

C22

VSS_17

C24

VSS_18

C26

VSS_19

C28

VSS_20

D13

VSS_21

D15

VSS_22

D17

VSS_23

D19

VSS_24

D23

VSS_25

D25

VSS_26

D27

VSS_27

VSS_28

VSS_29

F14

VSS_30

F16

VSS_31

F18

VSS_32

F20

VSS_33

F22

VSS_34

F26

VSS_35

F28

VSS_36

G13

VSS_37

G15

VSS_38

G17

VSS_39

G19

VSS_40

G21

VSS_41

G23

VSS_42

G25

VSS_43

VSS_44

J22

VSS_45

J24

VSS_46

VSS_47

VSS_48

K11

VSS_49

K14

VSS_50

VSS_51

AC11

VSS_52

L19

VSS_53

VSS_54

M11

VSS_55

AF11

VSS_56

V19

VSS_57

VSS_58

W16

VSS_59

VSS_60

VSS_61

Y11

VSS_62

Y20

VSS_63

Y22

VSS_64

VSS_65

A17

VSS_66

A13

VSS_67

K16

VSS_68

F24

VSS_69

VSS_70

VSS_71

VSS_72

LOTES_ACA-ZIF-109-P12-A_FS1R2

CONN@

VDDIO_SUS (CPU side) 22uF x 4

4.7uF x 4

0.22uF x 6 +2(split) 180pF x 1 + 2(split)

S_73

S S

S_74

V V

S_75

S_76

S_77

S_78

S_79

S_80

S S

S_81

S_82

V V

S_83

S S

S_84

V V

S_85

S_86

S VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143

A19 A21 A23 A25 A7 AA4 AA7 AB13 AB15 AB19 AB21 AB23 AB25 AB27 AB9 AC14 AC16 AC18 AC20 AC24 AC26 AC28 AC4 AC7 AD9 AE13 AE15 AE17 M9 N10 N4 N7 R10 R4 T11 T9 U10 U18 U4 U7 V11 AE19 AE23 AE25 AE27 AE4 AE7 AF14 AF16 AF18 AF20 AF22 AF26 AF28 AF9 AG4 AG7 AH13 AH15 AH17 AH19 AH21 P9 C18 D21 W14 P11 C7 E8 K18 W12

4 4

+2.5VS

L1 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

3300P_0402_50V7-K

0.22U_0402_6.3V6K

40mil

+VDDA

4.7U_0402_6.3V6M

C117

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

VDDP

0.22uF x 2 180pF x 2

VDDR

0.22uF x 2 1nF x 4 180pF x 2

Title

Size Document Number Rev

Custom

Date: Sheet of

VDDA

4.7uF x 1

0.22uF x 1

3.3nF x 1

Compal Electronics, Inc.

FS1r2 PWR/GND

VDDIO_SUS (DIMM x2) 100uF x 2

0.1uF x 12

LA-8127P

1.0

8 51Tuesday, March 12, 2013

1.0

D D

Panel PWM

R62

R62 47K_0402_5%

47K_0402_5%

C C

DP_INT_PWM[7]

B B

1 2

R66 2.2K_0402_5%R66 2.2K_0402_5%

R67

4.7K_0402_5%

3 1

MMBT3904_NL_SOT23-3

R63

4.7K_0402_5%

2N7002K_SOT23-3

APU_INVT_PWM [25]

A A

Security Classification

2012/11/22 2015/11/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

FS1r2 Signal Level Shifter

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

LA-8127P

9 51Tuesday, March 12, 2013

1.0

REF_DQ

D D

C2011

0.1U_0402_16V4Z

D D

D DDRA_SDQ11

DDRA_SDQ16 DDRA_SDQ17

DDRA_SDQS2# DDRA_SDQS2

DDRA_SDQ18 DDRA_SDQ19

DDRA_SDQ24 DDRA_SDQ25

DDRA_SDM3

DDRA_SDQ26 DDRA_SDQ27

DDRA_CKE0

DDRA_SBS2#

DDRA_SMA12 DDRA_SMA9

DDRA_SMA8 DDRA_SMA5

DDRA_SMA3 DDRA_SMA1

DDRA_CLK0 DDRA_CLK0#

DDRA_SMA10 DDRA_SBS0#

DDRA_SWE# DDRA_SCAS#

DDRA_SMA13 DDRA_SCS1#

DDRA_SDQ32 DDRA_SDQ33

DDRA_SDQS4# DDRA_SDQS4

DDRA_SDQ34 DDRA_SDQ35

DDRA_SDQ40 DDRA_SDQ41

DDRA_SDM5

DDRA_SDQ42 DDRA_SDQ43

DDRA_SDQ48 DDRA_SDQ49

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ56 DDRA_SDQ57

DDRA_SDM7

DDRA_SDQ58 DDRA_SDQ59

R2005 10K_0402_5%

1 1

2 2

3 3

2.2U_0603_6.3V6K

+3VS

C2010

RA_SDQS1#[6]

D D

RA_SDQS1[6]

DDRA_SDQS2#[6] DDRA_SDQS2[6]

DDRA_SBS2#[6]

DDRA_CLK0[6] DDRA_CLK0#[6]

DDRA_SBS0#[6]

DDRA_SWE#[6]

DDRA_SCAS#[ 6]

DDRA_SCS1#[6]

DDRA_SDQS4#[6] DDRA_SDQS4[6]

DDRA_SDQS6#[6] DDRA_SDQS6[6]

RA_SDQ0

RA_SDQ1

RA_SDM0

RA_SDQ2

RA_SDQ3

RA_SDQ8 RA_SDQ9

RA_SDQS1# RA_SDQS1

RA_SDQ10

1 2

R2000

R2000 10K_0402_5%

10K_0402_5%

.5V

IMM2

EF_DQ

S#1

S11

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2 DQS247VSS17 VSS1849DQ22

DQ18 DQ1953VSS19 VSS2055DQ28

DQ24 DQ2559VSS21 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3 A12/BC#83A11

VDD5

VDD7

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

FOX_AS0A626-U2RN-7F

CONN@

VDD12

VDD14

VDD16

VDD18

VREF_CA

DQS#5

DQS#7

EVENT#

V Q D V

V D D

SET#

S D DQ15

DQ20 DQ21

DQ23

DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS7

VSS50

DQ62 DQ63

VSS52

VTT2

.5V

RA_SDQ4

Q S3

S#0

S0 S6

S D

Q S8

Q Q

S10

S12

DM2

A15 A14

A6 A4

A2 A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

RA_SDQ5

8 10

RA_SDQS0#

RA_SDQS0

14 16

RA_SDQ6

RA_SDQ7

20 22

RA_SDQ12

RA_SDQ13

26 28

RA_SDM1

M_MA_RST#

32 34

RA_SDQ14

DDRA_SDQ15

38 40

DDRA_SDQ20

DDRA_SDQ21

44 46

DDRA_SDM2

48 50

DDRA_SDQ22

DDRA_SDQ23

54 56

DDRA_SDQ28

DDRA_SDQ29

60 62

DDRA_SDQS3#

DDRA_SDQS3

66 68

DDRA_SDQ30

DDRA_SDQ31

DDRA_CKE1

76 78

DDRA_SMA15

DDRA_SMA14

82 84

DDRA_SMA11

DDRA_SMA7

88 90

DDRA_SMA6

DDRA_SMA4

94 96

DDRA_SMA2

DDRA_SMA0

100 102

DDRA_CLK1

104

DDRA_CLK1#

106 108

DDRA_SBS1#

110

DDRA_SRAS#

112 114

DDRA_SCS0#

116

DDRA_ODT0

118 120

DDRA_ODT1

122 124 126 128 130

DDRA_SDQ36

132

DDRA_SDQ37

134 136

DDRA_SDM4

138 140

DDRA_SDQ38

142

DDRA_SDQ39

144 146

DDRA_SDQ44

148

DDRA_SDQ45

150 152

DDRA_SDQS5#

154

DDRA_SDQS5

156 158

DDRA_SDQ46

160

DDRA_SDQ47

162 164

DDRA_SDQ52

166

DDRA_SDQ53

168 170

DDRA_SDM6

172 174

DDRA_SDQ54

176

DDRA_SDQ55

178 180

DDRA_SDQ60

182

DDRA_SDQ61

184 186

DDRA_SDQS7#

188

DDRA_SDQS7

190 192

DDRA_SDQ62

194

DDRA_SDQ63

196 198

MEM_MA_EVENT#

200 202 204

206

+0.75VS

RA_SDQS0# [6]

D D

RA_SDQS0 [6]

M_MA_RST# [6]

DDRA_SDQS3# [6] DDRA_SDQS3 [6]

DDRA_CKE1 [ 6]DDRA_CKE0[6]

DDRA_CLK1 [ 6] DDRA_CLK1# [6]

DDRA_SBS1# [6] DDRA_SRAS# [6]

DDRA_SCS0# [6] DDRA_ODT0 [6]

DDRA_ODT1 [6]

+VREF_CA

DDRA_SDQS5# [6] DDRA_SDQS5 [6]

DDRA_SDQS7# [6] DDRA_SDQS7 [6]

MEM_MA_EVENT# [ 6]

FCH_SDATA0 [11,14,31,33] FCH_SCLK0 [11,14,31,33]

RA_SDQ[0..63]

RA_SDM[0..7]

RA_SMA[0..15]

+1.5V

0.1U_0402_16V4Z

+VREF_DQ

15mil

0.1U_0402_16V4Z

C2001

0.1U_0402_16V4Z

C2007

RA_SDQ[0..63] [6]

RA_SDM[0..7] [6]

RA_SMA[0..15] [6]

C2002

0.1U_0402_16V4Z

+VREF_DQ

1000P_0402_50V7K

C2008

0.1U_0402_16V4Z

C2003

+1.5V

R2001

R2001 1K_0402_1%

1K_0402_1%

1 2

R2003

R2003 1K_0402_1%

1K_0402_1%

1 2

C2004

0.1U_0402_16V4Z

Place near DIMM1

0.1U_0402_16V4Z

C2006

C2005

+VREF_CA

+1.5V

C2025

C2025 330U_D2_2V_Y

330U_D2_2V_Y

15mil

+1.5V

R2002

R2002 1K_0402_1%

1K_0402_1%

+VREF_CA

C2000

0.1U_0402_16V4Z

1 2

C2009

R2004

R2004 1K_0402_1%

1K_0402_1%

1 2

1000P_0402_50V7K

Reverse H:5.2mm

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

DDRIII SO-DIMM 1

LA-8127P

10 51Tuesday, March 12, 2013

1.0

.5V

RB_SDQ0

D D

RB_SDQ1

RB_SDM0

RB_SDQ2

D D

RB_SDQ3

1 2

R2007

10K_0402_5%

IMM1

EF_DQ

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2 DQS247VSS17 VSS1849DQ22

DQ18 DQ1953VSS19 VSS2055DQ28

DQ24 DQ2559VSS21 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3 A12/BC#83A11

VDD5

VDD7

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

FOX_AS0A626-UARN-7F

FOX_AS0A626-UARN-7F CONN@

CONN@

D V Q

D V

DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ23

DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

S S#0 Q S

A15 A14

CK1

BA1

S0#

NC2

SDA SCL

REF_DQ

+3VS

D D

DDRB_SDQ8 DDRB_SDQ9

DDRB_SDQS1# DDRB_SDQS1

DDRB_SDQ10 DDRB_SDQ11

DDRB_SDQ16 DDRB_SDQ17

DDRB_SDQS2# DDRB_SDQS2

DDRB_SDQ18 DDRB_SDQ19

DDRB_SDQ24 DDRB_SDQ25

DDRB_SDM3

DDRB_SDQ26 DDRB_SDQ27

DDRB_CKE0

DDRB_SBS2#

DDRB_SMA12 DDRB_SMA9

DDRB_SMA8 DDRB_SMA5

DDRB_SMA3 DDRB_SMA1

DDRB_CLK0 DDRB_CLK0#

DDRB_SMA10 DDRB_SBS0#

DDRB_SWE# DDRB_SCAS#

DDRB_SMA13 DDRB_SCS1#

DDRB_SDQ32 DDRB_SDQ33

DDRB_SDQS4# DDRB_SDQS4

DDRB_SDQ34 DDRB_SDQ35

DDRB_SDQ40 DDRB_SDQ41

DDRB_SDM5

DDRB_SDQ42 DDRB_SDQ43

DDRB_SDQ48 DDRB_SDQ49

DDRB_SDQS6# DDRB_SDQS6

DDRB_SDQ50 DDRB_SDQ51

DDRB_SDQ56 DDRB_SDQ57

DDRB_SDM7

DDRB_SDQ58 DDRB_SDQ59

R2006 10K_0402_5%R2006 10K_0402_5%

1 1

DDRB_SDQS1#[6] DDRB_SDQS1[6] MEM_MB_RST# [6]

DDRB_SDQS2#[6] DDRB_SDQS2[6]

2 2

3 3

DDRB_CKE0[6]

DDRB_SBS2#[6]

DDRB_CLK0[6] DDRB_CLK0#[6]

DDRB_SBS0#[6]

DDRB_SWE#[6]

DDRB_SCAS#[ 6]

DDRB_SCS1#[6]

DDRB_SDQS4#[6] DDRB_SDQS4[6]

DDRB_SDQS6#[6] DDRB_SDQS6[6]

.5V

RB_SDQ4

RB_SDQ5

RB_SDQS0#

RB_SDQS0

S0 S6 Q Q S8

A6 A4

A2 A0

14 16

RB_SDQ6

RB_SDQ7

20 22

DDRB_SDQ12

DDRB_SDQ13

26 28

DDRB_SDM1

MEM_MB_RST#

32 34

DDRB_SDQ14

DDRB_SDQ15

38 40

DDRB_SDQ20

DDRB_SDQ21

44 46

DDRB_SDM2

48 50

DDRB_SDQ22

DDRB_SDQ23

54 56

DDRB_SDQ28

DDRB_SDQ29

60 62

DDRB_SDQS3#

DDRB_SDQS3

66 68

DDRB_SDQ30

DDRB_SDQ31

DDRB_CKE1

76 78

DDRB_SMA15

DDRB_SMA14

82 84

DDRB_SMA11

DDRB_SMA7

88 90

DDRB_SMA6

DDRB_SMA4

94 9

DDRB_SMA2

DDRB_SMA0

100 102

DDRB_CLK1

104

DDRB_CLK1#

106 108

DDRB_SBS1#

110

DDRB_SRAS#

112 114

DDRB_SCS0#

116

DDRB_ODT0

118 120

DDRB_ODT1

122 124 126 128 130

DDRB_SDQ36

132

DDRB_SDQ37

134 136

DDRB_SDM4

138 140

DDRB_SDQ38

142

DDRB_SDQ39

144 146

DDRB_SDQ44

148

DDRB_SDQ45

150 152

DDRB_SDQS5#

154

DDRB_SDQS5

156 158

DDRB_SDQ46

160

DDRB_SDQ47

162 164

DDRB_SDQ52

166

DDRB_SDQ53

168 170

DDRB_SDM6

172 174

DDRB_SDQ54

176

DDRB_SDQ55

178 180

DDRB_SDQ60

182

DDRB_SDQ61

184 186

DDRB_SDQS7#

188

DDRB_SDQS7

190 192

DDRB_SDQ62

194

DDRB_SDQ63

196 198

MEM_MB_EVENT#

200 202 204

+0.75VS

RB_SDQS0# [6]

RB_SDQS0 [6]

DDRB_SDQS3# [6] DDRB_SDQS3 [6]

DDRB_CKE1 [ 6]

DDRB_CLK1 [6] DDRB_CLK1# [ 6]

DDRB_SBS1# [6] DDRB_SRAS# [6]

DDRB_SCS0# [6] DDRB_ODT0 [6]

DDRB_ODT1 [6]

+VREF_CA

DDRB_SDQS5# [6] DDRB_SDQS5 [6]

DDRB_SDQS7# [6] DDRB_SDQS7 [6]

MEM_MB_EVENT# [ 6]

FCH_SDATA0 [10,14,31,33] FCH_SCLK0 [10,14,31,33]

RB_SDQ[0..63]

RB_SDM[0..7]

RB_SMA[0..15]

RB_SDQ[0..63] [6]

RB_SDM[0..7] [6]

RB_SMA[0..15] [ 6]

REF_DQ

15mil

REF_DQ

1000P_0402_50V7K

0.1U_0402_16V4Z

C2022

0.1U_0402_16V4Z

+1.5V

C2012

0.1U_0402_16V4Z

C2016

+0.75VS

C2013

C2017

C2018

0.1U_0402_16V4Z

C2023

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

C2019

REF_CA

15mil

REF_CA

0.1U_0402_16V4Z

C2014

Place near DIMM2

0.1U_0402_16V4Z

8/25

1000P_0402_50V7K

C2015

0.1U_0402_16V4Z

C2020

+1.5V

C2024

C2024 330U_D2_2V_Y

330U_D2_2V_Y

C2021

4 4

Reverse H:9.2mm

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

DDRIII SO-DIMM 2

LA-8127P

11 51Tuesday, March 12, 2013

1.0

150P_0402_50V8J

R90/ C146 close to FCH

1 1

1 2

C129

22P_0402_50V8J

20M_0402_5%

C130

22P_0402_50V8J

2 2

R75

1 2

10P_0402_50V8J

1 2

C131

1M_0402_5%

C134

1 2

10P_0402_50V8J

Close to HUDSON-M2/3

X1 2

5MHZ_10PF_X3G025000DA1H-X

R88

GND

150P_0402_50V8J

32K_X1

32.768KHZ_12.5PF_CM31532768DZFT

32K_X2

25M_X1

GND

25M_X2

WLAN

3 3

LAN

Card Reader

For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)

APU_PCIE_RST #: Reset PCIE device on APU

C74VHC1G08DFT2G_SC70-5

4 4

APU_PCIE_RST#_C

R89/ C135 close to FCH

R89

1 2

33_0402_5%

C74VHC1G08DFT2G_SC70-5

R90

1 2

150P_0402_50V8J

+3V_FCH

8.2K_0402_5%

R92

@R92

1 2

0_0402_5%

1 2

M M

U U

M M

U U

M M

M UMI_TXN1[5] UMI_TXP2[5] UMI_TXN2[5] UMI_TXP3[5] UMI_TXN3[5]

+VDDAN_11_PCIE

CLK_PCIE_VGA[17] CLK_PCIE_VGA#[17]

CLK_PCIE_WLAN#[33]

CLK_PCIE_LAN[35] CLK_PCIE_LAN#[35]

CLK_PCIE_CARD[35] CLK_PCIE_CARD#[35]

CLK_LAN_25M[35]

C133

1 2

0.1U_0402_16V4Z

I_RXP0[5] I_RXN0[5] I_RXP1[5] I_RXN1[5] I_RXP2[5] I_RXN2[5] I_RXP3[5] I_RXN3[5]

I_TXP0[5] I_TXN0[5] I_TXP1[5]

T_RST#

1 2

26 .1U_0402_16V7K

1 2

18 .1U_0402_16V7K

1 2

19 .1U_0402_16V7K

1 2

20 .1U_0402_16V7K

1 2

27 .1U_0402_16V7K

1 2

21 .1U_0402_16V7K

1 2

28 .1U_0402_16V7K

1 2

22 .1U_0402_16V7K

+1.1VS_CKVDD

1 2

R76 0_0402_5%@R76 0_0402_5%@

1 2

R77 0_0402_5%@R77 0_0402_5%@

R150 0_0402_5%@R 150 0_0402_5%@ R142 0_0402_5%@R 142 0_0402_5%@

R80 33_0402_5%R80 33_0402_5% R82 33_0402_5%R82 33_0402_5%

R83 33_0402_5%R83 33_0402_5% R84 33_0402_5%R84 33_0402_5%

R86 22_0402_5%@R86 22_0402_5%@

APU_PCIE_RST# [17,33,35]

R91

R91 0_0402_5%

0_0402_5%

PLT_RST# [31,35]

U_PCIE_RST#_C

1 2

R71 590_0402_1%R71 590_0402_1%

1 2

R73 2K_0402_1%R73 2K_0402_1%

1 2 1 2

1 2

2 33_0402_5%

R74

1 2

2K_0402_1%

APU_DISP_CLK[7] APU_DISP_CLK#[7]

APU_CLK[7] APU_CLK#[7]

CLK_PCIE_VGA_R CLK_PCIE_VGA#_R

CLK_PCIE_WLAN_R CLK_PCIE_WLAN#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

CLK_PCIE_CARD_R CLK_PCIE_CARD#_R

RST#

I_RXP0_C

I_RXN0_C

I_RXP1_C

I_RXN1_C

I_RXP2_C

M M

I_RXN2_C

U U

I_RXP3_C

I_RXN3_C

PCIE_CALRP PCIE_CALRN

CLK_CALRN

CLK_LAN_25M_R

25M_X1

25M_X2

AE2 AD5

AE30 AE32 AD33 AD31 AD28 AD29 AC30 AC32

AB33 AB31 AB28 AB29

Y33 Y31 Y28 Y29

AF29 AF31

V33

V31 W30 W32

AB26 AB27 AA24 AA23

AA27 AA26

W27

V27

V26 W26 W24 W23

F27

G30

G28

R26

T26

H33

H31

T24 T23

J30

K29

H27

H28

J27

K26

F33 F31

E33

E31

M23 M24

M27 M26

N25

N26

R23

R24

N27

R27

J26

C31

C33

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

V/FVT, NO.12

IE_RST#

P A

RST#

I_TX0P

I_TX0N

I_TX1P

I_TX1N

I_TX2P

I_TX2N

M M

I_TX3P

I_TX3N

I_RX0P

U U

I_RX0N

I_RX1P

M UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N

PCIE_CALRP PCIE_CALRN

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N

GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N

CLK_CALRN

PCIE_RCLKP PCIE_RCLKN

DISP_CLKP DISP_CLKN

DISP2_CLKP DISP2_CLKN

APU_CLKP APU_CLKN

SLT_GFX_CLKP SLT_GFX_CLKN

GPP_CLK0P GPP_CLK0N

GPP_CLK1P GPP_CLK1N

GPP_CLK2P GPP_CLK2N

GPP_CLK3P GPP_CLK3N

GPP_CLK4P GPP_CLK4N

GPP_CLK5P GPP_CLK5N

GPP_CLK6P GPP_CLK6N

GPP_CLK7P GPP_CLK7N

GPP_CLK8P GPP_CLK8N

14M_25M_48M_OSC

25M_X1

25M_X2

218-0844000 A0 BOLTON-M3

PCI EXPRESS INTERFACES

CLOCK GENERATOR

UDSON-2

ICLK1/GPO36

C C

ICLK2/GPO37

P P

ICLK3/GPO38

PCI CLKS

PCI INTERFACE

LPCAPUS5 PLUS

2012/11/22 2015/11/22

ICLK4/14M_OSC/GPO39

AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

REQ1#/GPIO40 REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42

GNT1#/GPO44

GNT2#/SD_LED/GPO45

GNT3#/CLK_REQ7#/GPIO46

INTE#/GPIO32

INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35

LDRQ1#/CLK_REQ6#/GPIO49

SERIRQ/GPIO48

DMA_ACTIVE#

S5_CORE_EN

INTRUDER_ALERT#

VDDBT_RTC_G

Compal Secret Data

ICLK0

IRST#

0/GPIO0

1/GPIO1

A A

2/GPIO2

D D

3/GPIO3

A A

4/GPIO4

5/GPIO5

D AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9

CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP# PERR# SERR#

REQ0#

GNT0#

CLKRUN#

LOCK#

LPCCLK0

LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

RTCCLK

32K_X1

32K_X2

Deciphered Date

AF3 AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

B25

D25 D27 C28 A26 A29 A31 B27 AE27 AE19

G25 E28 E26 G26 F26

H7 F1 F3 E6

1 2

R209 0_0402_5%@R 209 0_0402_5%@

1 2

R208 0_0402_5%@R 208 0_0402_5%@

LPCCLK0

APU_PROCHOT#_R

32K_X1

32K_X2

I_CLK1 [16]

I_CLK3 [16]

I_CLK4 [16]

PCI_AD23 [16] PCI_AD24 [16] PCI_AD25 [16] PCI_AD26 [16] PCI_AD27 [16]

T11T11

T22T22

1 2

R110 0_0402_5%@R 110 0_0402_5%@

1 2

R215 33_0402_5%R215 33_0402_5%

LPC_CLK1 [16] LPC_AD0 [31,33,35] LPC_AD1 [31,33,35] LPC_AD2 [31,33,35] LPC_AD3 [31,33,35] LPC_FRAME# [31,33,35]

SERIRQ [31]

1 2

R85 0_0402_5%@R85 0_0402_5%@

APU_PWRGD [45,7]

APU_RST# [7]

RTC_CLK [16,31]

1U_0402_6.3V6K

PXS_RST# [14,17] PXS_PWREN [14,19,43,44]

W=20mils

C132

Date: Sheet of

CLK_PCI_DB [33,35]CLK_PCIE_WLAN[33]

CLK_PCI_EC [16,31]

ALLOW_STOP [7] APU_PROCHOT# [7]

1 2

R87 510_0402_5%R87 510_0402_5%

+RTCBATT

JCMOS1

@JCMOS1

SHORT PADS

for Clear CMOS

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

FCH PCIE/CLK/PCI/LPC/RTC

LA-8127P

12 51Tuesday, March 12, 2013

1.0

4MB SPI ROM

I_CLK_FCH

33_0402_5%

22P_0402_50V8J

SPI_CLK_FCH_R

+3V_FCH

& Non-share ROM.

VALW

1 1

HDD

ODD

2 2

3 3

4 4

TA_FTX_DRX_P0[30]

TA_FTX_DRX_N0[30]

SATA_FRX_C_DTX_N0[30] SATA_FRX_C_DTX_P0[30]

SATA_FTX_DRX_P1[30] SATA_FTX_DRX_N1[30]

SATA_FRX_C_DTX_N1[30] SATA_FRX_C_DTX_P1[30]

+AVDD_SATA

1 2

39 0.01U_0402_16V7K

1 2

40 0.01U_0402_16V7K

1 2

C143 0.01U_0402_16V7KC143 0.01U_0402_16V7K

1 2

C142 0.01U_0402_16V7KC142 0.01U_0402_16V7K

+3VS

BT_ON#[32]

WLBT_OFF#[33]

WL_OFF#[33]

ODD_EN[30]

TA_FTX_C_DRX_P0

TA_FTX_C_DRX_N0

SATA_FTX_C_DRX_P1 SATA_FTX_C_DRX_N1

SATA_CALRP

R1071K_0402_1% R1 071K_0402_1%

SATA_CALRN

R108931_0402_1% R108931_0402_1%

R21410K_0402_5% R21410K _0402_5%

BT_ON#

WLBT_OFF# WL_OFF#

ODD_EN

1 2

R119 10K_0402_5%R119 10K_0402_5%

1 2

R122 10K_0402_5%R122 10K_0402_5%

1 2

R123 10K_0402_5%R123 10K_0402_5%

AK19

TA_TX0P

AM19

TA_TX0N

AL20

SATA_RX0N

AN20

SATA_RX0P

AN22

SATA_TX1P

AL22

SATA_TX1N

AH20

SATA_RX1N

AJ20

SATA_RX1P

AJ22

SATA_TX2P

AH22

SATA_TX2N

AM23

SATA_RX2N

AK23

SATA_RX2P

AH24

SATA_TX3P

AJ24

SATA_TX3N

AN24

SATA_RX3N

AL24

SATA_RX3P

AL26

SATA_TX4P

AN26

SATA_TX4N

AJ26

SATA_RX4N

AH26

SATA_RX4P

AN29

SATA_TX5P

AL28

SATA_TX5N

AK27

SATA_RX5N

AM27

SATA_RX5P

AL29

NC6

AN31

NC7

AL31

NC8

AL33

NC9

AH33

NC10

AH31

NC11

AJ33

NC12

AJ31

NC13

AF28

SATA_CALRP

AF27

SATA_CALRN

AD22

SATA_ACT#/GPIO67

AF21

SATA_X1

AG21

SATA_X2

AH16

FANOUT0/GPIO52

AM15

FANOUT1/GPIO53

AJ16

FANOUT2/GPIO54

AK15

FANIN0/GPIO56

AN16

FANIN1/GPIO57

AL16

FANIN2/GPIO58

TEMPIN0/GPIO171

TEMPIN1/GPIO172

TEMPIN2/GPIO173

TEMPIN3/TALERT#/GPIO174

SERIAL ATA

UDSON-2

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

ROM_RST#/SPI_WP#/GPIO161

HW MONITOR

_CLK/SCLK_2/GPIO73

_CMD/SLOAD_2/GPIO74

_CD/GPIO75

SD_WP/GPIO76

SD_DATA0/SDATI_2/GPIO77

SD_DATA1/SDATO_2/GPIO78

SD_DATA2/GPIO79 SD_DATA3/GPIO80

GBE_COL

GBE_CRS

GBE_MDCK

GBE_MDIO

GBE_RXCLK

GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0

GBE_RXCTL/RXDV

GBE_RXERR

GBE_TXCLK

GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0

GBE_TXCTL/TXEN

GBE_PHY_PD

GBE_PHY_RST#

GBE_PHY_INTR

SPI_DI/GPIO164

SPI_DO/GPIO163

SPI_CLK/GPIO162

SPI_CS1#/GPIO165

VGA_RED

VGA_GREEN

VGA_BLUE

VGA_HSYNC/GPO68 VGA_VSYNC/GPO69

VGA_DDC_SDA/GPO70 VGA_DDC_SCL/GPO71

VGA_DAC_RSET

AUX_VGA_CH_P AUX_VGA_CH_N

AUXCAL

ML_VGA_L0P

ML_VGA_L0N

ML_VGA_L1P

ML_VGA_L1N

ML_VGA_L2P

ML_VGA_L2N

ML_VGA_L3P

ML_VGA_L3N

ML_VGA_HPD/GPIO229

VIN0/GPIO175

VIN1/GPIO176

VIN2/SDATI_1/GPIO177

VIN3/SDATO_1/GPIO178

VIN4/SLOAD_1/GPIO179

VIN5/SCLK_1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

NC1 NC2 NC3 NC4 NC5

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10

FCH SCLv1.20 19:

AB8

GBE_COL/GBE_CRS/GBE_RXERR NC

AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9

GBE_PHY_INTR

SPI_SO

SPI_SI

SPI_CLK_FCH_R

SPI_SB_CS0#

SPI_WP#

L30

L32

M29

M28 N30

M33 N32

K31

V28 V29

U28

T31 T33 T29 T28 R32 R30 P29 P28

C29

AG16 AH10 A28 G27 L4

1 2

R104 150_0402_1%R104 150_0402_1%

1 2

R105 150_0402_1%R105 150_0402_1%

1 2

R106 150_0402_1%R106 150_0402_1%

1 2

R109 715_0402_1%R109 715_0402_1%

AUXCAL

R111 100_0402_1%R111 100_0402_1%

1 2

R113 10K_0402_5%R113 10K_040 2_5%

1 2

R114 10K_0402_5%R114 10K_040 2_5%

1 2

R115 10K_0402_5%R115 10K_040 2_5%

1 2

R116 10K_0402_5%R116 10K_040 2_5%

1 2

R117 10K_0402_5%R117 10K_040 2_5%

1 2

R118 10K_0402_5%R118 10K_040 2_5%

1 2

R120 10K_0402_5%R120 10K_040 2_5%

1 2

R121 10K_0402_5%R121 10K_040 2_5%

VALW

CRT_HSYNC [28] CRT_VSYNC [28]

CRT_DDC_DATA [28] CRT_DDC_CLK [28]

ML_VGA_AUXP_C [7] ML_VGA_AUXN_C [7]

1 2

ML_VGA_TXP0 [7] ML_VGA_TXN0 [7] ML_VGA_TXP1 [7] ML_VGA_TXN1 [7] ML_VGA_TXP2 [7] ML_VGA_TXN2 [7] ML_VGA_TXP3 [7] ML_VGA_TXN3 [7]

ML_VGA_HPD [7]

Follow Comal OR B Rework Memo

R94 10K_0402_5%R94 10K_0402_5%

VALW

8 7 6 5

0.1U_0402_16V4Z

SPI_HOLD# SPI_CLK_FCH SPI_SI

GBE_PHY_INTR

1 2

R100 10K_0402_5%R100 10K_0402_5%

1 2

I_HOLD#

10K_0402_5%

1 2

SPI_SB_CS0# SPI_SO

1 2

SPI_WP#

DAC_RED [28]

DAC_GRN [28]

DAC_BLU [28]

+VDDAN_11_ML

+FCH_VDDAN_33_DAC

R11210K_0402_5% R11210K_0402_5%

Used as GPIO181 or configure as one of the f ollowing:

-> 10-KΩ 5% pul l-down resistor .

-> 10-KΩ 5% pul l-up resistor t o +3.3V_S5.

-> Enabled inte grated pull-dow n/up and left unconnected.

10K_0402_5%

CS#

WP#

GND

25Q32BVSSIG_SO8

VCC

HOLD#

CLK

1 2

R99

R99 0_0402_5%

0_0402_5%

1 2

218-0844000 A0 BOLTON-M3

APU_ALERT#_FCH[7]

218-0844000 A0 BOLTON-M3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

LA-8127P

13 51Tuesday, March 12, 2013

1.0

H_PWRGD[45]

1 1

For ODD Power Leakage issue

ODD_DA#_FCH[30]

2 2

+3V_FCH

For FCH internal debug use

1 2

R128 2.2K_0402_5%@R128 2.2K_0402_5%@

1 2

R129 2.2K_0402_5%@R129 2.2K_0402_5%@

1 2

R130 2.2K_0402_5%@R130 2.2K_0402_5%@

+3V_FCH

1 2

R154 10K_0402_5%R154 10K_0402_5%

1 2

R137 10K_0402_5%R137 10K_0402_5%

1 2

R139 10K_0402_5%R139 10K_0402_5%

1 2

R205 10K_0402_5%@R205 10K_0402_5%@

1 2

R143 10K_0402_5%@R143 10K_0402_5%@

1 2

R145 100K_0402_5%@R145 100K_0402_5%@

1 2

R149 10K_0402_5%R149 10K_0402_5%

3 3

4 4

1 2

R155 10K_0402_5%@R155 10K_0402_5%@

+3VS

1 2

R174 10K_0402_5%R174 10K_0402_5%

1 2

R156 10K_0402_5%R156 10K_0402_5%

1 2

R151 2.2K_0402_5%R151 2.2K_0402_5%

1 2

R152 2.2K_0402_5%R152 2.2K_0402_5%

1 2

R153 10K_0402_5%R153 10K_0402_5%

1 2

R159 8.2K_0402_5%R159 8.2K_0402_5%

1 2

R160 10K_0402_5%@R160 10K_0402_5%@

1 2

R161 10K_0402_5%@R161 10K_0402_5%@

1 2

R162 10K_0402_5%R162 10K_0402_5%

1 2

R163 10K_0402_5%@R163 10K_0402_5%@

1 2

R166 10K_0402_5%@R166 10K_0402_5%@

1 2

R167 10K_0402_5%@R167 10K_0402_5%@

CLKREQG Not Implemented: Used as GPIO65, IDLEEXIT#, or left unconnected.

.1U_0402_16V7K

+3VS +3VS

1 2

THERMTRIP 8/16 AMD confirmed: The FCH already have internal PU resistor and don't need external PU resistor. Note: need BIOS check: Ensure FCH internal pull-up resistor to +3.3V S5 is disabled to prevent leakage when APU is powered down.

24 0_0402_5%@

25 0_0402_5%

44 .1U_0402_16V7K

1 2

C74VHC1G08DFT2G_SC70-5

R213

R213 10K_0402_5%

10K_0402_5%

PEG_CLKREQ#_R

Q43

Q43 2N7002K_SOT23-3

2N7002K_SOT23-3

TEST0

TEST1

TEST2

USB_OC3#

USB_OC1#

USB_OC0#

ODD_DETECT#

H_THERMTRIP#

EC_LID_OUT#

FCH_PCIE_WAKE#

ODD_DA#_FCH_R

WLAN_CLKREQ#

CARD_CLKREQ#

FCH_SCLK0

FCH_SDATA0

WD_PWRGD

LAN_CLKREQ#

FCH_SCLK1

FCH_SDATA1

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

SCL1/SDA1: ASF-Capable LAN Devices Not Implemented: Used as GPIO227 or configured for one of the following options: 10-KΩ 5% pull-up resistor to +3.3V_S5; 10-KΩ 5% pull-down resistor.

ODD_DA#_FCH_R

+3V_FCH

UMA@

DIS@

IE_RST2 : Reset PCIE device on Hudson2/3

H_PWRGD

ST0

ST1

ST2

SYS_RESET#

WD_PWRGD

FCH_SCLK0 FCH_SDATA0 FCH_SCLK1 FCH_SDATA1

PEG_CLKREQ#_R

ODD_DA#_FCH_R

ODD_DETECT# USB_OC3#

USB_OC1# USB_OC0#

T19T19

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

GPIO188

GPIO189 GPIO190

T34T34 T35T35 T36T36 T37T37 T38T38 T39T39 T43T43 T44T44 T45T45 T40T40 T41T41 T42T42 T49T49 T50T50 T51T51 T46T46 T47T47 T48T48

FunctionGPIO188 GPIO189 GPIO190

Reserved

DISCRET

UMA

_LID_OUT#[31]

_SLP_S3#[31]

M M

_SLP_S5#[31]

P P

TN_OUT#[31]

H_POK [31]

ATE [31,45]

+3V_FCH

PEG_CLKREQ#[18]

HDA_BITCLK_AUDIO[29] HDA_SDOUT_AUDIO[29]

HDA_SDIN0[29]

HDA_SYNC_AUDIO[29]

HDA_RST_AUDIO#[29]

PXS_RST#[12,17] PXS_PWREN[12,19,43,44]

DMN66D0LDW-7_SOT363-6

+3V_FCH

1 2

R211 10K_0402_5%DIS@R211 10K_0402_5%DIS@

EC_PXCONTROL[31]

8/26

UMA@

R157

10K_0402_5%

DIS@

R164

10K_0402_5%

R206

R158

10K_0402_5%

GPIO188

GPIO189

GPIO190

R210

R165

10K_0402_5%

TEA20[31]

KB_RST#[31] EC_SCI#[31] EC_SMI#[31]

1 2

R126 10K_0402_5%@R126 10K_0402_5%@

FCH_PCIE_WAKE#[35]

H_THERMTRIP#[7]

EC_RSMRST#[31]

LAN_CLKREQ#[35]

CARD_CLKREQ#[35]

FCH_SPKR[29] FCH_SCLK0[10,11,31,33] FCH_SDATA0[10,11,31,33] FCH_SCLK1[33] FCH_SDATA1[33]

WLAN_CLKREQ#[33]

VGA_PWRGD[44]

R131 0_0402_5%@R 131 0_0402_5%@

ODD_DETECT#[30]

USB_OC3#[35]

USB_OC1#[34] USB_OC0#[34]

1 2

R134 33_0402_5%R134 33_0402_5%

1 2

R135 33_0402_5%R135 33_0402_5%

1 2

R138 33_0402_5%R138 33_0402_5%

1 2

R140 33_0402_5%R140 33_0402_5%

DIS@

Q44A

DMN66D0LDW-7_SOT363-6

3 4

EC_PXCONTROL

0 0

1 1

12 12

DIS@

Q44B

R1460_0402_5% @ R1460_0402_5% @ R1480_0402_5% @ R1480_0402_5% @

AB6

IE_RST2#/PCI_PME#/GEVENT4#

#/GEVENT22#

I_CS3#/GBE_STAT1/GEVENT21#

P_S3#

P_S5#

R_BTN#

R_GOOD

ST0

T10

ST1/TMS

ST2

AE22

20IN/GEVENT0#

AG19

KBRST#/GEVENT1#

LPC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

LPC_PD#/GEVENT5#

SYS_RESET#/GEVENT19#

WAKE#/GEVENT8#

IR_RX1/GEVENT20#

R10

THRMTRIP#/SMBALERT#/GEVEN T2#

AF19

WD_PWRGD

RSMRST#

AG24

CLK_REQ4#/SATA_IS0#/GPIO64

AE24

CLK_REQ3#/SATA_IS1#/GPIO63

AE26

SMARTVOLT1/SATA_IS2#/GPIO50

AF22

CLK_REQ0#/SATA_IS3#/GPIO60

AH17

SATA_IS4#/FANOUT3/GPIO55

AG18

SATA_IS5#/FANIN3/GPIO59

AF24

SPKR/GPIO66

AD26

SCL0/GPIO43

AD25

SDA0/GPIO47

SCL1/GPIO227

SDA1/GPIO228

AG25

CLK_REQ2#/FANIN4/GPIO62

AG22

CLK_REQ1#/FANOUT4/GPIO61

IR_LED#/LLB#/GPIO184

AG26

SMARTVOLT2/SHUTDOWN #/GPIO51

DDR3_RST#/GEVENT7#/VGA_PD

GBE_LED0/GPIO183

SPI_HOLD#/GBE_LED1/GEVENT9#

V10

GBE_LED2/GEVENT10#

AA8

GBE_STAT0/GEVENT11#

AF25

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

BLINK/USB_OC7#/GEVENT18#

USB_OC6#/IR_TX1/GEVENT6#

USB_OC5#/IR_TX0/GEVENT17#

USB_OC4#/IR_RX0/GEVENT16#

USB_OC3#/AC_PRES/TDO/GEVENT15#

USB_OC2#/TCK/GEVENT14#

USB_OC1#/TDI/GEVENT13#

USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12 #

AB3

AZ_BITCLK

AB1

AZ_SDOUT

AA2

AZ_SDIN0/GPIO167

AZ_SDIN1/GPIO168

AZ_SDIN2/GPIO169

AZ_SDIN3/GPIO170

AD6

AZ_SYNC

AE4

AZ_RST#

K19

PS2_DAT/SDA4/GPIO187

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI_CS2#/GBE_STAT2/GPIO166

D21

PS2KB_DAT/GPIO189

C20

PS2KB_CLK/GPIO190

D23

PS2M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

218-0844000 A0 BOLTON-M3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

HUDSON-2

EMBEDDED CTRL

2012/11/22 2015/11/22

BCLK/14M_25M_48M_OSC

USB MISCUSB 1.1USB 2.0USB 3.0

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

EC_PWM0/EC_TIMER 0/GPIO197 EC_PWM1/EC_TIMER 1/GPIO198

EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER 3/GPIO200

Compal Secret Data

Deciphered Date

B_FSD1P/GPIO186

B_FSD0P/GPIO185

U USB_HSD12N

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9N

USB_HSD8N

USB_HSD7N

USB_HSD6N

USB_HSD5N

USB_HSD4N

USB_HSD3N

USB_HSD2N

USB_HSD1N

USB_HSD0N

USBSS_CALRP

USBSS_CALRN

USB_SS_TX3P USB_SS_TX3N

USB_SS_RX3P USB_SS_RX3N

USB_SS_TX2P USB_SS_TX2N

USB_SS_RX2P USB_SS_RX2N

USB_SS_TX1P USB_SS_TX1N

USB_SS_RX1P USB_SS_RX1N

USB_SS_TX0P USB_SS_TX0N

USB_SS_RX0P USB_SS_RX0N

SCL2/GPIO193

SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

B_RCOMP

B_FSD1N

B_FSD0N

B_HSD13P

S S

B_HSD13N

B_HSD12P

USB_HSD9P

USB_HSD8P

USB_HSD7P

USB_HSD6P

USB_HSD5P

USB_HSD4P

USB_HSD3P

USB_HSD2P

USB_HSD1P

USB_HSD0P

B_RCOMP

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

K12 K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

F8 E8

C6 A6

C5 A5

C1 C3

E1 E3

C16

USBSS_CALRP

A16

USBSS_CALRN

A14 C14

C12 A12

D15

USB30_FTX_DRX_P2_C

B15

USB30_FTX_DRX_N2_C

E14

USB30_FRX_DTX_P2

F14

USB30_FRX_DTX_N2

F15

USB30_FTX_DRX_P1_C

G15

USB30_FTX_DRX_N1_C

H13

USB30_FRX_DTX_P1

G13

USB30_FRX_DTX_N1

J16

USB30_FTX_DRX_P0_C

H16

USB30_FTX_DRX_N0_C

J15

USB30_FRX_DTX_P0

K15

USB30_FRX_DTX_N0

H19

R144 10K_0402_5%R144 10K_0402_5%

G19

R147 10K_0402_5%R147 10K_0402_5%

G22

FCH_SIC

G21

FCH_SID

E22 H22 J22

EC_PWM2

H21

K21 K22 F22 F24 E24 B23 C24 F18

USB30_N12 USB30_N11 USB30_N10 USB20_N6 USB20_N0

1 2 1 2

1 2

27 11.8K_0402_1%

B30_P12 [34]

USB30_N12 [34]

USB30_P11 [34] USB30_N11 [34]

USB30_P10 [34] USB30_N10 [34]

LP3

LP2

LP1

USB20_P7 [35] USB20_N7 [35]

USB20_P6 [26] USB20_N6 [26]

USB20_P5 [33] USB20_N5 [33]

R230 300_0402_5%@R230 300_0402_5%@ R231 300_0402_5%@R231 300_0402_5%@ R232 300_0402_5%@R232 300_0402_5%@ R233 300_0402_5%@R233 300_0402_5%@ R234 300_0402_5%@R234 300_0402_5%@

R132 1K_0402_1%R132 1K_0402 _1% R133 1K_0402_1%R133 1K_0402 _1%

CMOS

WLAN

Near Device

1 2 1 2 1 2 1 2 1 2

USB20_P0 [35] USB20_N0 [35]

1 2 1 2

1 2

C212 .1U_0402_16V7KC212 .1U_0402_16V7K

1 2

C213 .1U_0402_16V7KC213 .1U_0402_16V7K

1 2

C218 .1U_0402_16V7KC218 .1U_0402_16V7K

1 2

C219 .1U_0402_16V7KC219 .1U_0402_16V7K

1 2

C220 .1U_0402_16V7KC220 .1U_0402_16V7K

1 2

C221 .1U_0402_16V7KC221 .1U_0402_16V7K

Title

Size Document Number Rev

Custom

Date: Sheet of

RP1

FCH_SIC [7] FCH_SID [7]

EC_PWM2 [16]

Compal Electronics, Inc.

FCH SATA/SPI/VGA/HWM/SD

1 2

C222 10P_0402_50V8J@C222 10P_0402_50V8J@

1 2

C223 10P_0402_50V8J@C223 10P_0402_50V8J@

1 2

C224 10P_0402_50V8J@C224 10P_0402_50V8J@

1 2

C225 10P_0402_50V8J@C225 10P_0402_50V8J@

1 2

C226 10P_0402_50V8J@C226 10P_0402_50V8J@

+FCH_VDD_11_SSUSB_S

USB30_FTX_DRX_P2 [34] USB30_FTX_DRX_N2 [34]

USB30_FRX_DTX_P2 [34] USB30_FRX_DTX_N2 [34]

USB30_FTX_DRX_P1 [34] USB30_FTX_DRX_N1 [34]

USB30_FRX_DTX_P1 [34] USB30_FRX_DTX_N1 [34]

USB30_FTX_DRX_P0 [34] USB30_FTX_DRX_N0 [34]

USB30_FRX_DTX_P0 [34] USB30_FRX_DTX_N0 [34]

strap pin

LA-8127P

LP3

LP2

LP1

1.0

14 51Tuesday, March 12, 2013

1.0

CH_VDDAN_33_DAC

1 1

+3VS +FCH_VDDAN_33_DAC

BMA-L11-201209-221LMA30T_0805

2 2

+3V

3 3

+3VS

4 4

1 2

BK1608221YZF_2P

220 ohm

1 2

68 0_0402_5%@

1 2

MBK1608221YZF_2P

1 2

220 ohm

1 2

MBK1608221YZF_2P

1 2

MBK1608221YZF_2P

220 ohm

1 2

MBK1608221YZF_2P

220 ohm

1 2

MBK1608221YZF_2P

220 ohm

L11

L14

L15

DDPL_33_SYS

C154

DDPL_33_MLDAC

C153

30mil

2.2U_0603_6.3V6K

C175

+VDDPL_33_SSUSB_S

2.2U_0402_6.3V6M

C1 85

+VDDPL_33_USB_S

C193

+VDDPL_33_PCIE

+VDDPL_33_SATA

2.2U_0402_6.3V6M

.1U_0402_16V7K

C147

.1U_0402_16V7K

C158

LDO_CAP: Internally generated 1.8V supply for the RGB outputs

+1.1VS

0.1U_0402_16V4Z

C176

.1U_0402_16V7K

C186

2.2U_0402_6.3V6M

.1U_0402_16V7K

C194

2.2U_0402_6.3V6M

C200

2.2U_0402_6.3V6M

C207

+1.1V

+VDDPL_33_MLDAC

1 2

MBK1608221YZF_2P

220 ohm/2A

+3V

FBMA-L11-201209-221LMA30T_0805

+1.1V

MBK1608221YZF_2P

+1.1V

MBK1608221YZF_2P

L16

FBMA-L11-201209-221LMA30T_0805

42 ohm/4A

1 2

71 0_0603_5%@

73 0_0402_5%@

R169 0_0402_5%@R 169 0_0402_5%@

+VDDPL_33_SSUSB_S

+VDDPL_33_USB_S

+VDDPL_33_PCIE

+VDDPL_33_SATA

R176 0_0402_5%@R 176 0_0402_5%@

R177 0_0603_5%@R 177 0_0603_5%@

1 2

220 ohm/2A

L10

1 2

220 ohm

L12

1 2

220 ohm

+FCH_VDD_11_SSUSB_S

40mils

1 2

R183 0_0603_5%@R 183 0_0603_5%@

1 2

R185 0_0603_5%@R 185 0_0603_5%@

C146

DDPL_33_SYS

1 2

10U_0603_6.3V6M

C180

2.2U_0402_6.3V6M

C188

10U_0603_6.3V6M

C195

DDIO_33_PCIGP

22U_0603_6.3V6M

.1U_0402_16V7K

C152

C151

+FCH_VDDAN_33_DAC

1 2

C164 2.2U_0603_6.3V6K

4.7U_0402_6.3V6M

.1U_0402_16V7K

C168

C169

1 2

R180 0_0402_5%@R 180 0_0402_5%@

+VDDAN_33_USB

10U_0603_6.3V6M

1U_0402_6.3V6K

C181

C182

+VDDAN_11_USB_S

.1U_0402_16V7K

C190

C189

+VDDCR_11V_USB

.1U_0402_16V7K

C196

C197

+VDDAN_11_SSUSB

1U_0402_6.3V6K

C201

C202

+VDDCR_11_SSUSB

10U_0603_6.3V6M

C208

C209

.1U_0402_16V7K

C157

DDPL_33_DAC

+VDDPL_33_ML

+VDDPL_11_DAC

+VDDAN_11_ML

.1U_0402_16V7K

C170

1U_0402_6.3V6K

C184

C183

.1U_0402_16V7K

C203

1U_0402_6.3V6K

C210

.1U_0402_16V7K

102mA

AB17

DIO_33_PCIGP_1

AB18

DIO_33_PCIGP_2

AE9

DIO_33_PCIGP_3

AD10

DIO_33_PCIGP_4

AG7

DIO_33_PCIGP_5

AC13

DIO_33_PCIGP_6

AB12

DIO_33_PCIGP_7

AB13

DIO_33_PCIGP_8

AB14

DIO_33_PCIGP_9

AB16

DIO_33_PCIGP_10

H24

DPL_33_SYS

20mA

V22

VDDPL_33_DAC

12mA

U22

VDDPL_33_ML

30mA

T22

VDDAN_33_DAC

11mA

L18

VDDPL_33_SSUSB_S

14mA

VDDPL_33_USB_S

11mA

AH29

VDDPL_33_PCIE

12mA

AG28

VDDPL_33_SATA

M31

LDO_CAP

7mA

V21

VDDPL_11_DAC

226mA

Y22

VDDAN_11_ML_1

V23

VDDAN_11_ML_2

V24

VDDAN_11_ML_3

V25

VDDAN_11_ML_4

AB10

VDDIO_33_GBE_S

AB11

VDDCR_11_GBE_S_1

AA11

VDDCR_11_GBE_S_2

AA9

VDDIO_GBE_S_1

AA10

VDDIO_GBE_S_2

470mA

VDDAN_33_USB_S_1

.1U_0402_16V7K

VDDAN_33_USB_S_2

VDDAN_33_USB_S_3

VDDAN_33_USB_S_4

VDDAN_33_USB_S_5

VDDAN_33_USB_S_6

M10

VDDAN_33_USB_S_7

VDDAN_33_USB_S_8

N10

VDDAN_33_USB_S_9

M12

VDDAN_33_USB_S_10

N12

VDDAN_33_USB_S_11

M11

VDDAN_33_USB_S_12

140mA

U12

VDDAN_11_USB_S_1

U13

VDDAN_11_USB_S_2

42mA

T12

VDDCR_11_USB_S_1

T13

VDDCR_11_USB_S_2

282mA

P16

VDDAN_11_SSUSB_S_1

M14

VDDAN_11_SSUSB_S_2

N14

VDDAN_11_SSUSB_S_3

P13

VDDAN_11_SSUSB_S_4

P14

VDDAN_11_SSUSB_S_5

424mA

N16

VDDCR_11_SSUSB_S_1

N17

VDDCR_11_SSUSB_S_2

P17

VDDCR_11_SSUSB_S_3

M17

VDDCR_11_SSUSB_S_4

218-0844000 A0 BOLTON-M3

.1U_0402_16V7K

C211

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

UDSON-2

PCI/GPIO I/O

USB SS USB MAIN LINKGBE LAN

POWER

V V

D D

CORE S0

DAN_11_CLK_1

DAN_11_CLK_2

D VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9

VDDAN_11_SATA_10

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDXL_33_S

VDDCR_11_S_1 VDDCR_11_S_2

VDDPL_11_SYS_S

VDDAN_33_HWM_ S

VDDIO_AZ_S

2012/11/22 2015/11/22

1007mA

T14

DCR_11_1

T17

DCR_11_2

T20

DCR_11_3

U16

DCR_11_4

U18

DCR_11_5

V14

DCR_11_6

V17

DCR_11_7

V20

DCR_11_8

Y17

DCR_11_9

340mA

H26 J25 K24 L22 M22 N21 N22 P22

1088mA

AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27

1337mA

AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19

59mA

N18 L19 M18 V12 V13 Y12 Y13 W11

5mA

G24

187mA

N20 M20

70mA

J24

12mA

26mA

AA4

Compal Secret Data

.1U_0402_16V7K

C155

.1U_0402_16V7K

C159

.1U_0402_16V7K

C165

.1U_0402_16V7K

C171

1U_0402_6.3V6K

C177

2.2U_0402_6.3V6M

C187

1U_0402_6.3V6K

C191

2.2U_0402_6.3V6M

C198

2.2U_0402_6.3V6M

C204

Deciphered Date

CC_VDDCR_11

.1U_0402_16V7K

1U_0402_6.3V6K

C148

C149

.1VS_CKVDD

.1U_0402_16V7K

1U_0402_6.3V6K

C160

C161

+VDDAN_11_PCIE

+VDDIO_33_S

22U_0603_6.3V6M

1U_0402_6.3V6K

C167

C166

1U_0402_6.3V6K

C172

C173

2.2U_0402_6.3V6M

1U_0402_6.3V6K

C179

C178

+VDDXL_3.3V

+VDDCR_1.1V

1U_0402_6.3V6K

C192

+VDDPL_11_SYS_S

.1U_0402_16V7K

C199

+VDDAN_33_HWM

.1U_0402_16V7K

C205

+VDDIO_AZ

1 2

C206 2.2U_0402_6.3V6MC206 2.2U_0402_6.3V6M

C150

C162

+VDDAN_11_PCIE

C174

1U_0402_6.3V6K

C156

.1VS_CKVDD

1U_0402_6.3V6K

C163

+AVDD_SATA

22U_0603_6.3V6M

R179 0_0402_5%@R 179 0_0402_5%@

R182 0_0402_5%@R 182 0_0402_5%@

R184 0_0402_5%@R 184 0_0402_5%@

1 2

10U_0603_6.3V6M

1 2

72 0_0603_5%@

22U_0603_6.3V6M

1 2

MBK1608221YZF_2P

220 ohm

1 2

R181 0_0603_5%@R 181 0_0603_5%@

L13

1 2

MBK1608221YZF_2P

220 ohm

1 2

.1VS

700_08 05_5% @

.1VS

+1.1VS

R1750_0805_5% @ R1750_0805_5% @

+1.1VS

R1780_0805_5% @ R1780_0805_5% @

+3V_FCH

+3V

+VDDXL_3.3V Tie to +3.3V_S5 rail if USB3 Wake is supported; otherwise, tie to +3.3V_S0 rail. Hudson-2 designs: Tie to +3.3V_S0 rail.

+1.1VALW

VDDPL_11_SYS_S should be

+1.1V

tied to +1.1V_S5 rail if USB 3.0 Wake is supported; otherwise, it can be tied to +1.1V_S0 rail.

+3V_FCH

AMD reply: VDDAN_33_HWM_S: Please connect it to +3.3V_S5 directly if HWM is not used.

VDDIO_AZ_S

+3VS

Wake on Ring supported: Tie to +3.3/

1.5V_S5 rail, and treat like a 3.3/1.1V_S5 rail. Wake on Ring not supported: Tie to +3.3/

1.5V_S0 rail, and treat like a 3.3/1.1V S0 rail.

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

FCH PWR

FCH PWR LA-8127P

LA-8127P

15 51Tuesday, March 12, 2013

1.0

UDSON-2

A33

B13

D D

C C

B B

D13

E12 E16 E29

F11 F13 F16 F17 F19 F23 F25 F29

G16 G32 H12 H15 H29

K16 K27 K28

L12 L13 L15 L16

L21 M13 M16 M21 M25

N11

N13

N23

N24

P12

P18

P20

P21

P31

P33

R11

R25

R28

T11

T16

T18

K25

H25

J10 J13 J28 J32

F7 F9

J6 J9

S S

V V

S S

V V

S VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSAN_HWM

VSSXL

VSSPL_SYS

V V V V V V V V V VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

GROUND

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSPL_DAC

VSSAN_DAC

VSSANQ_DAC

VSSIO_DAC

EFUSE

T25

T27

U14

U17

U20

U21

U30

U32

V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33

T21 L28 K33 N28

RAP PINS

PULL HIGH

PULL LOW

PCI_CLK1[12 ]

PCI_CLK3[12 ]

PCI_CLK4[12 ]

CLK_PCI_EC[12,31]

LPC_CLK1[12]

EC_PWM2[14]

RTC_CLK[12,31]

I_CLK1

LOW

A PCIE GEN2

FAULT

FORCE PCIE GEN1

I_CLK3

USE DEBUG STRAPS

IGNORE DEBUG STRAP

DEFAULT

R186 10K_0402_5%R186 10K_0 402_5%

R198 10K_0402_5%@R198 10K_0402_5%

I_CLK4 CLK_PCI_EC

N_FUSION

N CLOCK MODE

FUSION CLOCK MODE

DEFAULT

R188 10K_0402_5%@R188 10K_0402_5%

R187 10K_0402_5%@R187 10K_0402_5%

R200 10K_0402_5%R200 10K_0 402_5%

R199 10K_0402_5%R199 10K_0 402_5%

E E

NABLED

EC DISABLED

DEFAULT

R189 10K_0402_5%@R189 10K_0402_5%

R201 10K_0402_5%R201 10K_0 402_5%

KGEN

C ENABLED

FAULT

CLKGEN DISABLE

R190 10K_0402_5%R190 10K_0 402_5%

R202 10K_0402_5%@R202 10K_0402_5%

BUG STRAPS

H HAS 15K INTERNAL PU FOR PCI_AD[27:23]

_PWM2

C ROM

SPI ROM

DEFAULT

+3V_FCH+3 V_FCH+3V_FC H+3V_FCH+3VS+3VS+3VS

R192 10K_0402_5%R192 10K_0 402_5%

R191 10K_0402_5%@R191 10K_0402_5%

R204 2.2K_0402_5%@R204 2.2K_0402_5%

R203 2.2K_0402_5%R203 2.2K_0402_5%

C_CLKLPC_CLK1

PLUS

S MODE DISABLED

FAULT

S5 PLUS MODE ENABLED

I_AD27 PCI_AD26

P HIGH

PULL LOW

PCI_AD27[12]

PCI_AD26[12]

PCI_AD25[12]

PCI_AD24[12]

PCI_AD23[12]

USE PCI

PLL

FAULT

BYPASS PCI PLL

DISABLE ILA AUTORUN

FAULT

ENABLE ILA AUTORUN

R193 2.2K_0402_5%@R193 2.2K_0402_5%

I_AD25 PCI_AD24

E FC

U PLL

BYPASS FC PLL

R194 2.2K_0402_5%@R194 2.2K_0402_5%

R195 2.2K_0402_5%@R195 2.2K_0402_5%

USE DEFAULT PCIE STRAPS

FAULT

USE EEPROM PCIE STRAPS

R196 2.2K_0402_5%@R196 2.2K_0402_5%

PCI_AD23

DISABLE PCI MEM BOOT

FAULTDEFAULT

ENABLE PCI MEM BOOT

R197 2.2K_0402_5%@R197 2.2K_0402_5%

218-0844000 A0 BOLTON-M3

A A

218-0844000 A0 BOLTON-M3

Security Classification

2012/11/22 2015/11/22

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/11/22 2015/11/22

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docum ent Number Rev

Date: Sheet of

Compal Electronics, Inc.

FCH-VSS/Strap

LA-8127P

16 5

1.0

1Tuesday, March 12, 2013

+ 36 hidden pages