Compal LA-7901P QXW00 Korbel 14 UMA, Latitude E5430 Schematic

A

COMPAL CONFIDENTIAL

B

C

D

E

MODEL NAME :

1 1

PCB NO :

LA-7901P (DA60000PM00)

BOM P/N :

GPIO MAP:

E4_VC_GPIO_map_rev_1.1

QXW00

4619F631L01 / L02

Korbel 14 UMA--Non vPRO

2 2

Ivy/Sandy Bridge + Panther POINT(HM77w/DASH)

2012-03-03

REV : 1.0 (A00)

@ : Nopop Component

CONN@ : Connector Component

MB Type

BOM P/N

TPM

3 3

43*

1@

2@ 4@TCM

5@

5@

TPM DIS 2@3@3@

HM77 w/o Vpro

QM77 w/ Vpro

PXDP@PCH XDP

46@HDMI LOGO

4 4

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

MB PCB

MB PCB

Part Number Description

Part Number Description

A

PCB 0LH LA-7901P REV0 M/B UMA

PCB 0LH LA-7901P REV0 M/B UMA

DA60000PM00

DA60000PM00

B

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

C

D

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-7901P

LA-7901P

LA-7901P

1 61Saturday, March 03, 2012

1 61Saturday, March 03, 2012

1 61Saturday, March 03, 2012

E

1.0

1.0

1.0

A

B

C

D

E

Intel
Ivy/Sandy Bridge
Processorr

Memory BUS

1.5V DDRIII 1333 /1600 MHz

DDRIII-DIMM X4

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

P12-13

rPGA 989 Socket

1 1

FDI x8 DMI Gen 2x 4

LVDS CONN

P23

HDMI CONN

P25

On IO board

CRT CONN

P37

2 2

VGA

Docking VGA

For MB/DOCK
Video Switch
PI3V713-AZLEX

Docking DPC

Docking DPD

PCIE BUS

1/2 Mini Card
WLAN/WiFi

SMSC SIO
ECE5048

EMC4021PWM FAN

Port2Port5Port3Port6

P39

Port7

BROADCOM
BCM5761

Card Reader
OZ600FJ0

Smart card
Express card

1/2 Mini Card
PP

P30~31

USB port 6USB port 10

Docking LAN

LAN SWITCH
PI3L720

3 3

RJ45

on IO board

4 4

A

P31

P37

DC/DC Interface

SDXC/MMC

CPU XDP Port

PCH XDP Port

WiFi ON/OFF

LED

FFS LNG3DM

P33

P7

P14

P37

P42

P43

P27

B

LVDS

DPB

VGA

P23

Port1

Full Mini Card
WWAN

USB port 5USB port 4

China TCM1.2
SSX44B

P32

Discrete TPM
AT97SC3204

P32

Option

BC BUS

SMSC KBC
ECE5055

TP CONN KB CONN

P41 P41

INTEL
Panther POINT-M
BGA 989 Balls
HM77

LPC Bus

P34P34P34P35P33

P40P22P22

C

P14~21

SPI Bus

P6-11

USB port 11

USB port 12

USB port 13

USB

SATA 3.0

USB port 2

USB port 1

USB port 0.9

Port0

Port1

HD Audio I/F

MDC

W25Q32BVSSIG

P14

32M 4K sector

W25Q32BVSSIG

P14

32M 4K sector

Docking DPC

Docking DPD

DAI

USB2.0 [3,8]

SATA port 5

DOCK LAN

USB3.0 [4]

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

P37

RJ11

on IO board

DOCKING

P38

D

BT 4.0

Camera

Through LVDS Cable

Fingerprint
CONN

SATA port 4

USB3.0 port 3

USB3.0 port 2

HDD CONN

P27

ODD CONN

P28

HDA Codec
92HD90B2

P29

Dig. MIC

Through LVDS Cable

P41

P24

P41

E-SATA

USB 3.0 Port

USB 2.0 Port

P36

USB 3.0 Port

USB 2.0 Port

P36

USB2.0

P37

on IO board

INT.Speaker

P29

Combo Jack

DAI

P37

on Audio board

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

UMA Block Diagram

UMA Block Diagram

UMA Block Diagram

LA-7901P

LA-7901P

LA-7901P

E

2 61Friday, March 02, 2012

2 61Friday, March 02, 2012

2 61Friday, March 02, 2012

1.0

1.0

1.0

5

4

3

2

1

POWER STATES

RUN

State

S0 (Full ON) / M0

D D

S3 (Suspend to RAM) / M3

S4 (Suspend to DISK) / M3 ON ON OFF

S5 (SOFT OFF) / M3 ON ON OFFL

S3 (Suspend to RAM) / M-OFF

S4 (Suspend to DISK) / M-OFF HIGH

S5 (SOFT OFF) / M-OFF

Signal

SLP
S3#

HIGH

LOW HIGH HIGH ON ON ON OFF

LOW HIGH HIGH

OW HIGHLOW

LOW HIGH HIGH LOW ON ONOFF OFF OFF

LOW LOW LOW ON OFF OFF OFF OFF

LOW LOW LOW LOW ON OFF OFF OFF OFF

SLP

SLP

S5#

S4#

HIGH HIGH

LOW

LOW

SLP
A#

HIGH

HIGH

ALWAYS
PLANE

ON

M

LANE

P

ON

SUS

LANE

P

ON ON ON

OFF

OFF

PLANE

CLOCKS

OFF

OFF

OFF

USB 3.0 PORT#

1

2

3 JUSB2 (Left side)

4

Connetion

NA

JUSB1 (Left side)

DOCKING

PCH

USB PORT#

0

1

2

3

4

5

6

*1

7

*1

8

JUSB (Right side-IO/B)

JUSB (Left side)

JESA1 (Leftt side ESATA)

MLK DOCK

WLAN

WWAN

JMINI3(Flash)-for w/ Vpro

DOCKING

NA

DESTINATION

PM TABLE

C C

power
p

lane

State

S0

S3

S5 S4/AC

S5 S4/AC don't exist

B B

+15V_ALW

+5V_ALW

+3.3V_ALW_PCH

3.3V_RTC_LDO

+

ON

N

O

+3.3V_SUS

+1.5V_MEM

ON ON

ON

OFF

OFFOFF

+5V_RUN

+3.3V_RUN

+1.8V_RUN

+1.5V_RUN

+0.75V_DDR_VTT

+VCC_CORE

+1.05V_RUN_VTT

+1.05V_RUN

OFFON

OFF

O

FF

need to update Power Status and
PM Table

+3.3V_M +3.3V_M

+1.05V_M

ON

ON

ON

+1.05V_M

(M-OFF)

ON

OFF

OFF

OFFOFF

SATA

SATA 0

SATA 1

SATA 2

SATA 3

SATA 4

DESTINATION

HDD

ODD/ E3 Module Bay

NA

NA

ESATA

9

10 Express card/Smart Card

11

12

13 BIO

*1: HM76 don't support port 6,7

PCI EXPRESS

Lane 1

Lane 2

Lane 3

SATA 5

Dock

Lane 4

JUSB (Right side-Audio/B)

Bluetooth

Camera

DESTINATION

MINI CARD-1 WWAN

MINI CARD-2 WLAN

Express card

None

UMA DP/HDMI Port

Port B

Port C

A A

Port D

Connetion

MB HDMI Conn

Dock DP port 2

Dock DP port 1

Lane 5

Lane 6

Lane 7

Lane 8 None

1/2vMINI CARD-3 PCIE

MMI

10/100/1G LOM

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Index and Config.

Index and Config.

Index and Config.

LA-7901P

LA-7901P

LA-7901P

3 61Friday, March 02, 2012

3 61Friday, March 02, 2012

3 61Friday, March 02, 2012

1

1.0

1.0

1.0

5

4

3

2

1

D D

EN_INVPWR

ADAPTER

1.05V_0.8V_PWROK

BATTERY

C C

CHARGER

+PWR_SRC

FDC654P

(Q21)

ISL95836

(PU700)

+BL_PWR_SRC

+VCC_GFXCORE

+5V_RUN

+5V_HDD

Pop option

SIO_SLP_S3#

ALWON

RT8205
(PU100)

MODC_EN

SI3456BDVSI3456BDV

(Q30)(Q27)

+5V_MOD

+5V_ALW

+3.3V_ALW

RUN_ON

0.75V_DDR_VTT_ON

SIO_SLP_S3#

SYN470
(PU300)

+1.8V_RUN

AO4728
(QC3)

RT8207
(PU200)

DDR_ON

+1.5V_MEM

SIO_SLP_S3#

SIO_SLP_S4#

NTGS4141N

(Q59)

ISL95836

(PU700)

B B

1.05V_0.8V_PWROK

+VCC_CORE

TPS51212

(PU500)

CPU_VTT_ON

SIO_SLP_S3#

+1.05V_RUN_VTT +1.05V_M

SIO_SLP_S3#

SI4164

(Q63)

PJP8

TPS51212

(PU400)

SIO_SLP_A#

Pop option

SIO_SLP_S3#

CPU1.5V_S3_GATE

1.05V_VTTPWRGD

TPS51461

(PU7)

+VCC_SA

AUX_EN_WOWL

SI3456

(Q38)

+3.3V_WLAN

PCH_ALW_ON

SI3456

(Q49)

+3.3V_ALW_PCH

AUX_ON

SIO_SLP_S3#

SIO_SLP_S3#

TPS22966

S13456

(Q54)

SIO_SLP_S4#

SIO_SLP_LAN#

SI3456

(Q34) (U78)

SIO_SLP_S5#

SUS_ON

+3.3V_LAN+3.3V_SUS

Pop option

+3.3V_M

+3.3V_RUN

+5V_RUN

SIO_SLP_A#

SI3456

(Q58)

+3.3V_M

R206

+3.3V_SUS

MCARD_MISC_PWREN

SI3456

(Q42)

+3.3V_PCIE_FLASH

+3.3V_PCIE_WWAN

MCARD_WWAN_PWREN

SI3456

(Q40)

+0.75V_DDR_VTT+1.5V_RUN+1.5V_CPU_VDDQ

+1.05V_RUN

A A

+1.0V_LAN

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Power Rail

Power Rail

Power Rail

LA-7901P

LA-7901P

LA-7901P

1

4 61Friday, March 02, 2012

4 61Friday, March 02, 2012

4 61Friday, March 02, 2012

1.0

1.0

1.0

5

SMBUS Address [0x9a]

MEM_SMBCLK

H14

MEM_SMBDATA

C9

D D

C8

PCH

DMN66D0L

DMN66D0L

G12

E14M16

SML1_SMBDATA

SML1_SMBCLK

B6A5

3A

3A

A50

1E

B53

1E

C C

KBC

B4

1A

A31A

B5

1B

A4

1B

SIO_LAN_SMBCLK

SIO_LAN_SMBDAT

DOCK_SMB_CLK

DOCK_SMB_DAT

LCD_SMBCLK

LCD_SMDATA

4

DMN66D0L

DMN66D0L

2.2K

2.2K

2.2K

2.2K

LAN_APE_SMB_DATA0

LAN_APE_SMB_CLK0

+3.3V_ALW_PCH

+3.3V_ALW_PCH

2.2K

2.2K

2.2K

2.2K

2.2K

2.2K

+3.3V_ALW

+3.3V_ALW

+3.3V_ALW

DMN66D0L

DMN66D0L

L09

L10

2.2K

2.2K

127

129

3

BCM LOM

+3.3V_LAN

DOCKING

SMBUS Address [**]

SMBUS Address

APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13

202

200

202

200

2

DIMM1

DIMM2

53

51

53

51

XDP1

XDP2

SMBUS Address [A0]

SMBUS Address [A4]

SMBUS Address [TBD]

SMBUS Address [TBD]

1

10K

G Sensor

WWAN

+3.3V_RUN

SMBUS Address [3B]

SMBUS Address [TBD]

10K

4

6

30

32

2.2K

1C

1C

B B

B59

PBAT_SMBCLK

PBAT_SMBDAT

A56

2.2K

+3.3V_ALW

100 ohm

100 ohm

7

6

BATTERY
CONN

SMBUS Address [0x16]

2.2K

MEC 5055

A49

B52

CARD_SMBCLK

CARD_SMBDAT

2B

2B

2.2K

2.2K

B50

A47

CHARGER_SMBCLK

CHARGER_SMBDAT

1G

1G

2.2K

2.2K

2.2K

B7

A7

BAY_SMBDAT

BAY_SMBCLK

A A

2D

2D

+3.3V_SUS

+3.3V_ALW

+3.3V_ALW

10

9

7

8

Charger

Express card

SMBUS Address [TBD]

SMBUS Address [0x12]

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

SMBUS TOPOLOGY

SMBUS TOPOLOGY

SMBUS TOPOLOGY

LA-7901P

LA-7901P

LA-7901P

5 61Friday, March 02, 2012

5 61Friday, March 02, 2012

5 61Friday, March 02, 2012

1

1.0

1.0

1.0

5

D D

DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>

FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>

C C

B B

FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>

FDI_FSYNC0< 16>
FDI_FSYNC1< 16>

FDI_INT<16>

FDI_LSYNC0<16>
FDI_LSYNC1<16>

(1) EDP_COMPIO use 4mil trace to RC1
(2) EDP_ICOMPO use 12mil to RC1

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT

FDI_LSYNC0
FDI_LSYNC1

EDP_COMP

4

JCPU1A

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]

DMI

DMI

Intel(R) FDI

Intel(R) FDI

eDP

eDP

PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

Link CIS

3

PEG_COMP

J22
J21
H22

(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then
use 4mil connect to RC2.

K33
M35

(2)PEG_ICOMPO use 12mil connect to RC2

L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34

K35
K32
K29
K26

H33
H30
H27
H24
H21
H18
H15
H13
H10

G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

2

JCPU1I

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198
VSS199
VSS200
VSS201
VSS202

J34

VSS203

J31

VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

1

+1.05V_RUN_VTT +1.05V_RUN_VTT

1 2

RC1 24.9_0402_1%~DRC1 24.9_0402_1%~D

DP Compensation

eDP_COMPIO and ICOMPO signals should be shorted near

A A

balls and routed with typical impedance <25 mohms

EDP_COMP

1 2

RC2 24.9_0402_1%~DRC2 24.9_0402_1%~D

PEG Compensation

PEG_ICOMPI and RCOMPO signals should be shorted and routed
with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

PEG_COMP

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

Link CIS

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

ize Document Number Rev

S

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Ivy/Sandt Bridge (1/6)

Ivy/Sandt Bridge (1/6)

Ivy/Sandt Bridge (1/6)

LA-7901P

LA-7901P

LA-7901P

6 61Friday, March 02, 2012

6 61Friday, March 02, 2012

6 61Friday, March 02, 2012

1

1.0

1.0

1.0

of

5

4

3

2

1

Follow DG Rev0.71 SM_DRAMPWROK topology

+3.3V_ALW_PCH

D D

+1.05V_RUN_VTT

C C

B B

RUNPWROK<39,40>

PM_DRAM_PWRGD<16>

+3.3V_ALW_PCH

RC126 56_0402_5%~D@RC126 56_0402_5%~D@

RC128 49.9_0402_1%~D@RC128 49.9_0402_1%~D@

RC44 62_0402_5%~DRC44 62_0402_5%~D

1 2

RC18 200_0402_1%~DRC18 200_0402_1%~D

1 2

1 2

1 2

H_PROCHOT#<40,51,52>

H_THERMTRIP#<22>

H_CPUPWRGD<18>

H_THERMTRIP#

H_CATERR#

H_PROCHOT#

CPU_DETECT#<39>

PECI_EC<40>

VR1 TOPOLOGY

1 2

RC57 56_0402_5%~DRC57 56_0402_5%~D

1 2

RC129 0_0402_5%~DRC129 0_0402_5%~D

place RC129 near CPU

H_PM_SYNC<16>

1 2

RC25 1K_0402_5%~DRC25 1K_0402_5%~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

5

1

P

B

O

2

A

G

74AHC1G09GW_TSSOP5~D

74AHC1G09GW_TSSOP5~D

3

RUN_ON_CPU1.5VS3#<11,42>

Close to JCBU1

VCCPWRGOOD_0_R

PM_DRAM_PWRGD_CPU

PCH_PLTRST#_R

CC156

CC156

1 2

4

UC2

UC2

H_CATERR#

H_PROCHOT#_R

H_THERMTRIP#_R

+1.5V_CPU_VDDQ

200_0402_1%~D

200_0402_1%~D

12

RC12

RC12

RUNPWROK_AND PM_DRAM_PWRGD_CPU

2

G

G

JCPU1B

JCPU1B

C26

PROC_SELECT #

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPW RGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

1 2

RC28 130_0402_1%~DRC28 130_0402_1%~D

39_0402_5%~D

39_0402_5%~D

@RC64

@

RC64

1 2

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

@

@

13

D

D

QC1

QC1

S

S

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

Link CIS

CLOCKS

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

JTAG & BPM

BCLK

BCLK#

DPLL_REF_CL K

DPLL_REF_CL K#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#
PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

+3.3V_ALW_PCH

SYS_PWROK_XDP

1 2

RC124 1K_0402_1%~D@RC124 1K_0402_1%~D@

SIO_PWRBTN#_R<14,16>

DDR_XDP_WAN_SMBDAT<12,13,14,15,27,34>

DDR_XDP_WAN_SMBCLK<12,13,14,15,27,34>

CPU_DMI
CPU_DMI#

CPU_DPLL
CPU_DPLL#

DDR3_DRAMRST#_CPU

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

XDP_PRDY#
XDP_PREQ#

XDP_TCLK
XDP_TMS
XDP_TRST#

XDP_TDI_R
XDP_TDO_R

XDP_DBRESET#_R

XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R
XDP_OBS3_R
XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R

RC13 0_0402_5%~D@RC13 0_0402_5%~D@

1 2

RC15 0_0402_5%~D@RC15 0_0402_5%~D@

1 2

RC16 1K_0402_1%~DRC16 1K_0402_1%~D

1 2

RC17 1K_0402_1%~DRC17 1K_0402_1%~D

1 2

DDR_HVREF_RST_PCH<15>

DDR_HVREF_RST_GATE<40>

RC26 0_0402_5%~DRC26 0_0402_5%~D

RC30 0_0402_5%~DRC30 0_0402_5%~D
RC31 0_0402_5%~DRC31 0_0402_5%~D
RC33 0_0402_5%~DRC33 0_0402_5%~D
RC34 0_0402_5%~DRC34 0_0402_5%~D
RC36 0_0402_5%~DRC36 0_0402_5%~D
RC37 0_0402_5%~DRC37 0_0402_5%~D
RC38 0_0402_5%~DRC38 0_0402_5%~D
RC39 0_0402_5%~DRC39 0_0402_5%~D

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

A28
A27

A16
A15

R8

AK1
A5
A4

AP29
AP27

AR26

TCK

AR27

TMS

AP30

AR28

TDI

AP26

TDO

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

For ESD concern, please put near CPU

+1.05V_RUN_VTT

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

1

CC65

CC65

CC66

CC66

2

2

Place near JXDP1

The resistor for HOOK2 should beplaced
such that the stub is very small on CFG0 net

H_CPUPWRGD

SYS_PWROK<16,39>

CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>H_SNB_IVB#<18>

4.99K_0402_1%~D

4.99K_0402_1%~D

12

RC50

RC50

XDP_DBRESET# <14,16>

XDP_OBS0
XDP_OBS1 XDP_TDI
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

1 2

RC5 1K_0402_1%~DRC5 1K_0402_1%~D

1 2

RC6 0_0402_5%~DRC6 0_0402_5%~D

CFG0

1 2

RC7 1K_0402_1%~DRC7 1K_0402_1%~D

1 2

RC9 0_0402_5%~D@ RC9 0_0402_5%~D@

1 2

RC125 0_0402_5%~DRC125 0_0402_5%~D

1 2

RC127 0_0402_5%~DRC127 0_0402_5%~D

+1.05V_RUN_VTT

1 2

RC48 0_0402_5%~D@RC48 0_0402_5%~D@

D

S

D

S

13

G

G

BSS138W-7-F_SOT323-3~D

BSS138W-7-F_SOT323-3~D

2

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

CC177

CC177

1

2

1 2

RC46 0_0402_5%~D@RC46 0_0402_5%~D@

1 2

RC47 0_0402_5%~D@RC47 0_0402_5%~D@

QC2

QC2

DDR_HVREF_RST

XDP_TDI_R

XDP_TDO_R

XDP_PREQ#
XDP_PRDY#

XDP_OBS0
XDP_OBS1

XDP_OBS2
XDP_OBS3

CFG10<9>
CFG11<9>

XDP_OBS4
XDP_OBS5

XDP_OBS6
XDP_OBS7

H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP

SYS_PWROK_XDP

DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1

XDP_TCLK

DDR3_DRAMRST# <12>

1 2

RC23 0_0402_5%~DRC23 0_0402_5%~D

1 2

RC24 0_0402_5%~DRC24 0_0402_5%~D

+1.05V_RUN_VTT +1.05V_RUN_VTT

JXDP1

JXDP1

1

GND0

3

CFG10
CFG11

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

SAMTE_BSH-030-01-L-D-A

CLK_XDP_ITP<9>

CLK_XDP_ITP#<9>

DDR_HVREF_RST <12>

XDP_TDO

XDP_RST#_R

CLK_XDP

CLK_XDP#

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

CONN@

CONN@

RC8 1K_0402_1%~DRC8 1K_0402_1%~D

1 2

RH107 0_0402_5%~DRH107 0_0402_5%~D

1 2

RH106 0_0402_5%~DRH106 0_0402_5%~D

1 2

RH109 0_0402_5%~D@RH109 0_0402_5%~D@

1 2

RH108 0_0402_5%~D@RH108 0_0402_5%~D@

XDP_DBRESET#

XDP_TMS

XDP_TDI

XDP_PREQ#

XDP_TDO

XDP_TCLK

XDP_TRST#

2

GND1

4
6
8

GND3

10
12
14

GND5

16
18
20

GND7

22
24
26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

12

PU/PD for JTAG signals

RC19 1K_0402_1%~DRC19 1K_0402_1%~D

RC27 51_0402_1%~DRC27 51_0402_1%~D

RC29 51_0402_1%~DRC29 51_0402_1%~D

RC32 51_0402_1%~D@RC32 51_0402_1%~D@

RC35 51_0402_1%~DRC35 51_0402_1%~D

RC40 51_0402_1%~DRC40 51_0402_1%~D

RC41 51_0402_1%~DRC41 51_0402_1%~D

CFG16
CFG17

CFG0
CFG1

CFG2
CFG3

CFG8
CFG9

CFG4
CFG5

CFG6
CFG7

CLK_XDP
CLK_XDP#

XDP_RST#_RXDP_HOOK2
XDP_DBRESET#

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

12

12

12

12

12

12

12

CFG16 <9>
CFG17 <9>

CFG0 <9>
CFG1 <9>

CFG2 <9>
CFG3 <9>

CFG8 <9>
CFG9 <9>

CFG4 <9>
CFG5 <9>

CFG6 <9>
CFG7 <9>

PLTRST_XDP# <17>

CLK_CPU_ITP <15>

CLK_CPU_ITP# <15>

+3.3V_RUN

+1.05V_RUN_VTT

Buffered reset to CPU

+3.3V_RUN

UC1

UC1

1

5

NC

VCC

A A

PCH_PLTRST#<14,17>

2

A
GND3Y

SN74LVC1G07DCKR_SC70-5~D

SN74LVC1G07DCKR_SC70-5~D

Open drain buffer

5

4

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

1

CC140

CC140

2

PCH_PLTRST#_BUF

+1.05V_RUN_VTT

75_0402_1%~D

75_0402_1%~D

12

RC4

RC4

1 2

RC10 43_0402_5%~DRC10 43_0402_5%~D

PCH_PLTRST#_R

1

2

4

100P_0402_50V8J~D

100P_0402_50V8J~D

CC142

CC142

H_THERMTRIP#PECI_EC H_CPUPWRGD

100P_0402_50V8J~D

100P_0402_50V8J~D

1

CC143

CC143

2

1

2

ESD request

100P_0402_50V8J~D

100P_0402_50V8J~D

CC144

CC144

100P_0402_50V8J~D

100P_0402_50V8J~D

1

CC141

CC141

2

3

Place closed JCPU1

XDP_DBRESET#

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

1

2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

VCCPWRGOOD_0_R

@CE13

@

CE13

Avoid stub in the PWRGD path
while placing resistors RC25 & RC130

10K_0402_5%~D

10K_0402_5%~D

12

RC130

RC130

SM_RCOMP0

1 2

RC42 140_0402_1%~DRC42 140_0402_1%~D

SM_RCOMP1

1 2

RC43 25.5_0402_1%~DRC43 25.5_0402_1%~D

SM_RCOMP2

1 2

RC45 200_0402_1%~DRC45 200_0402_1%~D

SM_RCOMP2 --> 15mil
SM_RCOMP1/0 --> 20mil
Max length 500mils

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Ivy/Sandy Bridge (2/6)

Ivy/Sandy Bridge (2/6)

Ivy/Sandy Bridge (2/6)

LA-7901P

LA-7901P

LA-7901P

1

7 61Friday, March 02, 2012

7 61Friday, March 02, 2012

7 61Friday, March 02, 2012

1.0

1.0

1.0

5

JCPU1C

D D

JCPU1C

4

3

JCPU1D

JCPU1D

2

1

DDR_A_D[0..63]<12>

C C

B B

DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>

DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

AP11
AN11

AL12
AM12
AM11

AL11

AP12
AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10

AF10

G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8

AK9
AH8
AH9
AL9
AL8

AE8
AD9
AF9

F10

AJ5
AJ6
AJ8

AJ9

C5
D5
D3
D2
D6
C6
C2
C3

F8

G9

F9

F7
G8
G7

K4

K5

K1

J1

J5

J4

J2

K2
M8

N8
N7

M9
N9
M7

V6

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_CLK_DDR#0
DDR_CKE0_DIMMA

M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#

M_ODT0

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>

M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>

DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>

M_ODT0 <12>
M_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <12>

DDR_A_MA[0..15] <12>

DDR_B_D[0..63]<13>

DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>

DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#< 13>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9

AP6
AN8
AR6
AR5
AR9

AJ11

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7

AA10

AB8
AB9

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]

R6

SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

SB_CK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

SB_ODT[0]

SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

M_CLK_DDR0

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_CLK_DDR2
M_CLK_DDR#2

DDR_CKE2_DIMMB

M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB

DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

M_ODT2
M_ODT3M_ODT1

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 <13 >
M_CLK_DDR#2 <1 3>
DDR_CKE2_DIMMB <13>

M_CLK_DDR3 <13 >
M_CLK_DDR#3 <1 3>
DDR_CKE3_DIMMB <13>

DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>

M_ODT2 <13>
M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <13>

DDR_B_MA[0..15] <13>

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

A A

Link CIS Link CIS

TYCO_2134146-3_IVYBRIDGE~D

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Ivy/Sandy Bridge (3/6)

Ivy/Sandy Bridge (3/6)

Ivy/Sandy Bridge (3/6)

LA-7901P

LA-7901P

LA-7901P

8 61Friday, March 02, 2012

8 61Friday, March 02, 2012

8 61Friday, March 02, 2012

1

1.0

1.0

1.0

5

4

3

2

1

CFG Straps for Processor

CFG2

D D

PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #

JCPU1E

JCPU1E

T39 PAD~D@ T39 PAD~D@

T1 PAD~D@T1 PAD~D@
T2 PAD~D@T2 PAD~D@
T3 PAD~D@T3 PAD~D@
T4 PAD~D@T4 PAD~D@

T5 PAD~D@T5 PAD~D@

T6 PAD~D@T6 PAD~D@
T7 PAD~D@T7 PAD~D@
T8 PAD~D@T8 PAD~D@

T11 PAD~D@ T11 PAD~D@
T13 PAD~D@ T13 PAD~D@
T15 PAD~D@ T15 PAD~D@
T16 PAD~D@ T16 PAD~D@

T17 PAD~D@ T17 PAD~D@
T18 PAD~D@ T18 PAD~D@
T19 PAD~D@ T19 PAD~D@
T20 PAD~D@ T20 PAD~D@
T21 PAD~D@ T21 PAD~D@

T23 PAD~D@ T23 PAD~D@
T24 PAD~D@ T24 PAD~D@
T25 PAD~D@ T25 PAD~D@
T26 PAD~D@ T26 PAD~D@
T27 PAD~D@ T27 PAD~D@

T32 PAD~D@ T32 PAD~D@
T34 PAD~D@ T34 PAD~D@

CLK_XDP_ITP <7>
CLK_XDP_ITP# <7>

T49 PAD~D@ T49 PAD~D@
T50 PAD~D@ T50 PAD~D@
T51 PAD~D@ T51 PAD~D@

T53 PAD~D@ T53 PAD~D@

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

KEY

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

CFG0<7>
CFG1<7>
CFG2<7>
CFG3<7>
CFG4<7>
CFG5<7>
CFG6<7>
CFG7<7>
CFG8<7>
CFG9<7>
CFG10<7>

+VCC_GFXCORE

1 2

+VCC_CORE

RC122 49.9_0402_1%~D@RC122 49.9_0402_1%~D@

RC123 49.9_0402_1%~D@RC123 49.9_0402_1%~D@

RC120 49.9_0402_1%~D@RC120 49.9_0402_1%~D@

RC121 49.9_0402_1%~D@RC121 49.9_0402_1%~D@

1 2

1 2

1 2

C C

B B

VAXG_VAL_SENSE

100_0402_1%~D

100_0402_1%~D

12

@RC69

@

RC69

VSSAXG_VAL_SENSE

VCC_VAL_SNESE

100_0402_1%~D

100_0402_1%~D

12

@RC71

@

RC71

VSS_VAL_SNESE

CFG11<7>

CFG16<7>
CFG17<7>

T22PAD~D @T22PAD~D @

T28PAD~D @T28PAD~D @
T29PAD~D @T29PAD~D @
T30PAD~D @T30PAD~D @
T31PAD~D @T31PAD~D @
T33PAD~D @T33PAD~D @
T35PAD~D @T35PAD~D @
T36PAD~D @T36PAD~D @
T37PAD~D @T37PAD~D @
T38PAD~D @T38PAD~D @
T40PAD~D @T40PAD~D @
T41PAD~D @T41PAD~D @
T42PAD~D @T42PAD~D @
T43PAD~D @T43PAD~D @
T44PAD~D @T44PAD~D @
T45PAD~D @T45PAD~D @
T46PAD~D @T46PAD~D @

T47PAD~D @T47PAD~D @
T48PAD~D @T48PAD~D @

T52PAD~D @T52PAD~D @

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SNESE
VSS_VAL_SNESE

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

CFG

CFG

VCC_DIE_SENSE

VSS_DIE_SENSE

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8

RESERVED

RESERVED

RSVD_NCTF9

RSVD_NCTF10

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

CFG2

CFG4

CFG[6:5]

definition matches socket pin map definition
0:Lane Reversed

1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled

01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

1K_0402_1%~D

1K_0402_1%~D

@RC51

@

12

RC51

CFG4

1K_0402_1%~D

1K_0402_1%~D

12

@RC52

@

RC52

Display Port Presence Strap

CFG6

CFG5

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

1K_0402_1%~D

12

@RC54

@

12

@RC53

@

RC54

RC53

PCIE Port Bifurcation Straps

CFG7

1K_0402_1%~D

1K_0402_1%~D

12

@RC56

@

RC56

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

Link CIS

PEG DEFER TRAINING

1: (Default) PEG Train immediately

CFG7

following xxRESETB de assertion
0: PEG Wait for BIOS for training

A A

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

ize Document Number Rev

S

Date: Sheet of

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

Ivy/Sandy Bridge (4/6)

Ivy/Sandy Bridge (4/6)

Ivy/Sandy Bridge (4/6)

LA-7901P

LA-7901P

LA-7901P

9 61Friday, March 02, 2012

9 61Friday, March 02, 2012

9 61Friday, March 02, 2012

1

1.0

1.0

1.0

of

5

JCPU1F

JCPU1F

4

POWER

POWER

3

2

1

+VCC_CORE

53A

AG35

VCC1

AG34

VCC2

AG33

D D

C C

B B

A A

5

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

CORE SUPPLY

CORE SUPPLY

SENSE LINES SVID

SENSE LINES SVID

Link CIS

4

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32

PEG AND DDR

PEG AND DDR

VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

8.5A

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

AJ29
AJ30
AJ28

AJ35
AJ34

B10
A10

+1.05V_RUN_VTT

H_CPU_SVIDALRT#
VIDSCLK
VIDSOUT

VCCSENSE_R
VSSSENSE_R

VTT_SENSE
VSSIO_SENSE_R

+1.05V_RUN_VTT

75_0402_1%~D

75_0402_1%~D

12

RC60

RC60

Note: Place the PU resistors close to CPU
RC61 close to CPU 300 - 1500mils

H_CPU_SVIDALRT#

VIDSCLK < 51>

Place RC67, RC68 near CPU

RC67 0_0402_5%~D@ RC67 0_0402_5%~D@

1 2

RC68 0_0402_5%~D@ RC68 0_0402_5%~D@

1 2

RC98 10_0402_1%~DRC98 10_0402_1%~D

10_0402_1%~D

10_0402_1%~D

12

RC133

RC133

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

1 2

RC61 43_0402_5%~DRC61 43_0402_5%~D

+1.05V_RUN_VTT

130_0402_1%~D

130_0402_1%~D

12

RC63

RC63

H_CPU_SVIDALRT# must be routed between the
VIDSOUT and VIDSCLK lines to reduce cross talk.
18 mils spacing to others.

12

CAD Note: Place the PU
resistors close to CPU
RC63 close to CPU 300 - 1500mils

VIDSOUT <51>

RC75

@RC75

@

1 2

100_0402_1%~D

100_0402_1%~D

+1.05V_RUN_VTT

VTT_SENSE <49>
VSSIO_SENSE_R < 49>

+VCC_CORE

VIDALERT_N <5 1>

100_0402_1%~D

100_0402_1%~D

12

RC66

RC66

VCCSENSE <51>

VSSSENSE <51>

100_0402_1%~D

100_0402_1%~D

12

RC70

RC70

2

Iccmax current changed for PDDG Rev0.7

CPU Power Rail Table

Voltage Rail Voltage

VCC 530.65-1.3

VCCIO 1.05 8.5

5A to Mem controller(+1.5V_CPU_VDDQ)
5-6A to 2 DIMMs/channel
2-5A to +1.5V_RUN & +0.75V_DDR_VTT

S0 Iccmax
Current (A)

260.0-1.1VAXG

31.8VCCPLL

51.5VDDQ

60.65-0.9VCCSA

12-161.5+1.5V_MEM

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Ivy/Sandy Bridge (5/6)

Ivy/Sandy Bridge (5/6)

Ivy/Sandy Bridge (5/6)

LA-7903P

LA-7903P

LA-7903P

10 61Friday, March 02, 2012

10 61Friday, March 02, 2012

10 61Friday, March 02, 2012

1

1.0

1.0

1.0

5

4

3

2

1

+1.5V_CPU_VDDQ Source

+PWR_SRC_S

330K_0402_5%~D

+3.3V_ALW2

100K_0402_5%~D

100K_0402_5%~D

12

RC74

RC74

D D

RUN_ON_CPU1.5VS3#

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

61

QC4A

SIO_SLP_S3#<16,27,35,39,42,47,48,49>

CPU1.5V_S3_GATE<40>

RC82 0_0402_5%~D@ RC82 0_0402_5%~D@

RC79 0_0402_5%~D@ RC79 0_0402_5%~D@

1 2

1 2

QC4A

2

330K_0402_5%~D

5

+1.5V_MEM +1.5V_CPU_VDDQ

12

RC72

RC72

RUN_ON_CPU1.5VS3

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

3

QC4B

QC4B

4

8
7
6
5

QC3

QC3

AO4304L_SO8

AO4304L_SO8

1M_0402_5%~D

1M_0402_5%~D

12

RC143

RC143

4

0.022U_0402_25V7K~D

0.022U_0402_25V7K~D

1

2

1
2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

3

CC136

CC136

20K_0402_5%~D

20K_0402_5%~D

12

CC135

CC135

1

@

@

RC73

RC73

2

+1.5V_MEM

+V_DDR_SMREF

1K_0402_1%~D

1K_0402_1%~D

12

@RC80

@

RC80

1K_0402_1%~D

1K_0402_1%~D

12

@RC81

@

RC81

1 2

RC135 0_0402_5%~D@RC135 0_0402_5%~D@

1 2

RC134 0_0402_5%~D@RC134 0_0402_5%~D@

NTR4503NT1G_SOT23-3~D

NTR4503NT1G_SOT23-3~D

RUN_ON_CPU1.5VS3

@QC5

@

1

+V_DDR_REF

+1.5V_CPU_VDDQ

1K_0402_1%~D

1K_0402_1%~D

12

RC84

RC84

QC5

3

2

+V_SM_VREF_CNT

1K_0402_1%~D

1K_0402_1%~D

12

RC78

RC78

RUN_ON_CPU1.5VS3# <7,42>

+VCC_GFXCORE

100_0402_1%~D

100_0402_1%~D

12

RC99

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC161

CC161

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@CC168

@

CC168

1

2

VCCSA_SENSE <50>

VCCSA_VID_0 <50>
VCCSA_VID_1 <50>

RC99

100_0402_1%~D

100_0402_1%~D

12

RC100

RC100

+V_SM_VREF should
have 10 mil trace width

+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

CC163

CC163

CC162

CC162

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CC169

CC169

CC170

CC170

1

1

2

2

RC76

@RC76

@

1 2

100_0402_1%~D

100_0402_1%~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

1

CC164

CC164

CC165

CC165

2

2

+VCC_SA

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CC171

CC171

1

1

CC172

CC172

+

+

2

2

VCCP_PWRCTRL <49>

+1.5V_CPU_VDDQ

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

1

1

+

+

CC166

CC166

2

2

VCC_AXG_SENSE <51>
VSS_AXG_SENSE <51>

CC178 0.1U_0402_10V7K~DCC178 0.1U_0402_10V7K~D

CC179 0.1U_0402_10V7K~DCC179 0.1U_0402_10V7K~D

CC149 0.1U_0402_10V7K~DCC149 0.1U_0402_10V7K~D

CC150 0.1U_0402_10V7K~DCC150 0.1U_0402_10V7K~D

CC167

CC167

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

ESD Request

12

12

12

12

CC153

CC153

+1.5V_CPU_VDDQ

+1.5V_MEM

1

@

@

2

6A

1

CC151

CC151

@

@

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

1

CC152

CC152

@

@

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2

+1.5V_MEM

POWER

+VCC_GFXCORE

C C

B B

+DIMM0_1_VREF_CPU

1 2

RC96 1K_0402_1%~D@RC96 1K_0402_1%~D@

RC97 1K_0402_1%~D@RC97 1K_0402_1%~D@

A A

1 2

+DIMM0_1_CA_CPU

+1.8V_RUN

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CC173

CC173

2

1U_0402_6.3V6K~D

1

CC174

CC174

2

1

1

CC176

CC176

CC175

CC175

+

+

2

2

330U_D2_2.5VM_R6M~D

330U_D2_2.5VM_R6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

33A

1.2A

AM24
AM23
AM21
AM20
AM18
AM17

AK24
AK23
AK21
AK20
AK18
AK17

AH24
AH23
AH21
AH20
AH18
AH17

JCPU1G

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

POWER

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

VREFMISC

GRAPHICS

GRAPHICS

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

1.8V RAIL

1.8V RAIL

Link CIS

VAXG_SENSE

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

AK35
AK34

AL1

+V_SM_VREF_CNT

+DIMM0_1_VREF_CPU

B4

+DIMM0_1_CA_CPU

D1

5A

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

6A

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

1 2

A19

RC140 0_0402_5%~D@RC140 0_0402_5%~D@

Depop RC140 for ES2 CPU

JCPU1H

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

TYCO_2134146-3_IVYBRIDGE~D

TYCO_2134146-3_IVYBRIDGE~D

VSS

VSS

Link CIS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

ize Document Number Rev

S

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Ivy/Sandy Bridge (6/6)

Ivy/Sandy Bridge (6/6)

Ivy/Sandy Bridge (6/6)

LA-7901P

LA-7901P

LA-7901P

1

11 61Friday, March 02, 2012

11 61Friday, March 02, 2012

11 61Friday, March 02, 2012

1.0

1.0

1.0

of

5

4

3

2

1

All VREF traces should

DDR_A_DQS#[0..7]<8>

DDR_A_D[0..63]<8>

DDR_A_DQS[0..7]<8>

DDR_A_MA[0..15]<8>

D D

Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3

+V_DDR_REFA_M3

+V_DDR_REF

have 10 mil trace width

1 2

RD7 0_0402_5%~D@RD7 0_0402_5%~D@

1 2

RD1 0_0402_5%~D@RD1 0_0402_5%~D@

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

1

CD1

CD1

2

2

Layout Note:
Place near JDIMM1

+1.5V_MEM

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD3

CD3

2

C C

+1.5V_MEM

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD7

CD7

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD9

CD9

CD8

CD8

CD10

CD10

1

1

2

2

1U_0402_6.3V6K~D

1

1

CD4

CD4

CD5

CD5

CD6

CD6

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

330U_SX_2VY~D

CD11

CD11

1

1

2

2

1

CD14

CD51

CD51

CD14

CD13

CD13

1

+

+

2

2

DDR_CKE0_DIMMA<8>

DDR_A_BS2<8>

M_CLK_DDR0<8>
M_CLK_DDR#0<8>

DDR_A_BS0<8>

DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<8>

Layout Note:
Place near JDIMM1.203,204

B B

+0.75V_DDR_VTT

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

2

A A

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD19

CD19

CD18

CD18

2

2

RD2 10K_0402_5%~DRD2 10K_0402_5%~D

RD3 10K_0402_5%~DRD3 10K_0402_5%~D

1U_0402_6.3V6K~D

CD20

CD20

1 2

1 2

DIMM1_SA0

DIMM1_SA1

+3.3V_RUN

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

CD21

CD21

2

+0.75V_DDR_VTT

1

CD22

CD22

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD17

CD17

2

JDIMM1 Rev Type H=8mm

2-3A to 1 DIMMs/channel

+DIMM1_VREF_DQ

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD2

CD2

+1.5V_MEM

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

DIMM1_SA0

DIMM1_SA1

JDIMM1

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103

LCN_DAN06-K4806-0103
C

C

ONN@

ONN@

Link CIS

DQ4
DQ5

VSS3

DQS0

VSS6

DQ6
DQ7

VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

A15
A14

A7

A6
A4

A2
A0

CK1

BA1

S0#

NC2

SDA
SCL

G2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

+1.5V_MEM

DDR3_DRAMRST#_R

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_D36
DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

+0.75V_DDR_VTT

DDR_CKE1_DIMMA <8>

M_CLK_DDR1 <8>

M_CLK_DDR#1 <8>

DDR_A_BS1 <8>

DDR_A_RAS# <8>

DDR_CS0_DIMMA# <8>

M_ODT0 <8>

M_ODT1 <8>

DDR_XDP_WAN_SMBDAT <7,13,14,15,27,34>

DDR_XDP_WAN_SMBCLK <7,13,14,15,27,34>

+DIMM1_VREF_CA

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

CD15

CD15

1

1

2

2

RD11 0_0402_5%~D@RD11 0_0402_5%~D@

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD16

CD16

1 2

RD28 1K_0402_1%~DRD28 1K_0402_1%~D

RD29 0_0402_5%~D@RD29 0_0402_5%~D@

1 2

QD1

QD1

D

S

D

S

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

RD30 0_0402_5%~D@RD30 0_0402_5%~D@

G

G

2

1 2

S

S

G

G

2

13

QD2

QD2

D

D

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

+DIMM0_1_VREF_CPU

DDR_HVREF_RST<7>

+DIMM0_1_CA_CPU

DDR_HVREF_RST

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

12

+V_DDR_REF

+1.5V_MEM

12

1K_0402_1%~D

1K_0402_1%~D

RD27

RD27

DDR3_DRAMRST# <7>DDR3_DRAMRST#_R<13>

+V_DDR_REFA_M3

+V_DDR_REFB_M3

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

DDRIII-SODIMM SLOT1

LA-7901P

LA-7901P

LA-7901P

1

1.0

1.0

12 61Friday, March 02, 2012

12 61Friday, March 02, 2012

12 61Friday, March 02, 2012

1.0

5

4

3

2

1

+V_DDR_REF

All VREF traces should
have 10 mil trace width

1 2

RD4 0_0402_5%~D@RD4 0_0402_5%~D@

1 2

RD8 0_0402_5%~D@RD8 0_0402_5%~D@

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD23

CD23

CD24

1

2

CD24

1

2

DDR_B_DQS#[0..7]<8>

DDR_B_D[0..63]<8>

DDR_B_DQS[0..7]<8>

DDR_B_MA[0..15]<8>

D D

+V_DDR_REFB_M3

Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3

Layout Note:
Place near JDIMM2

+1.5V_MEM

1U_0402_6.3V6K~D

+1.5V_MEM

1

2

1U_0402_6.3V6K~D

1

CD25

CD25

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD30

CD30

CD29

CD29

1

2

C C

B B

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD26

CD26

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD31

CD31

1

1

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CD27

CD27

CD28

CD28

2

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

CD32

CD32

1

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

330U_SX_2VY~D

1

CD34

CD34

CD33

CD33

1

2

CD36

CD36

CD35

CD35

1

+

+

2

2

DDR_CKE2_DIMMB<8>

DDR_B_BS2<8>

M_CLK_DDR2<8>
M_CLK_DDR#2<8>

DDR_B_BS0<8>

DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<8>

Layout Note:
Place near JDIMM2.203,204

+0.75V_DDR_VTT

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD39

CD39

2

A A

5

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CD40

CD40

2

1U_0402_6.3V6K~D

1

1

CD41

CD41

CD42

CD42

2

2

+3.3V_RUN

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

CD43

CD43

CD44

CD44

1

2

+3.3V_RUN

RD5 10K_0402_5%~DRD5 10K_0402_5%~D

RD6 10K_0402_5%~DRD6 10K_0402_5%~D

4

12

12

DIMM2_SA1

DIMM2_SA0

1

2

JDIMM2 Rev Type H=4

2-3A to 1 DIMMs/channel

+1.5V_MEM+DIMM2_VREF_DQ

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

DIMM2_SA0

DIMM2_SA1

+0.75V_DDR_VTT +0.75V_DDR_VTT

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

JDIMM2

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

LCN_DAN06-K4406-0103

CONN@

CONN@

Link CIS

VREF_CA

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

CK1#

RAS#

ODT0

ODT1

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

+1.5V_MEM

2

VSS

4

DQ4

6

DQ5

8

VSS

10
12
14

VSS

16

DQ6

18

DQ7

20

VSS

22
24
26

VSS

28

DM1

30
32

VSS

34
36
38

VSS

40
42
44

VSS

46

DM2

48

VSS

50
52
54

VSS

56
58
60

VSS

62
64
66

VSS

68
70
72

VSS

74
76

VDD

78

A15

80

A14

82

VDD

84

A11

86

A7

88

VDD

90

A6

92

A4

94

VDD

96

A2

98

A0

100

VDD

102

CK1

104
106

VDD

108

BA1

110
112

VDD

114

S0#

116
118

VDD

120
122

NC

124

VDD

126
128

VSS

130
132
134

VSS

136

DM4

138

VSS

140
142
144

VSS

146
148
150

VSS

152
154
156

VSS

158
160
162

VSS

164
166
168

VSS

170

DM6

172

VSS

174
176
178

VSS

180
182
184

VSS

186
188
190

VSS

192
194
196

VSS

198
200

SDA

202

SCL

204

VTT

206
208

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

M_ODT2

M_ODT3

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

2

DDR3_DRAMRST#_R <12>

DDR_CKE3_DIMMB <8>

M_CLK_DDR3 <8>

M_CLK_DDR#3 <8>

DDR_B_BS1 <8>

DDR_B_RAS# <8>

DDR_CS2_DIMMB# <8>

M_ODT2 <8>

M_ODT3 <8>

+DIMM2_VREF_CA

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D

1

CD37

CD37

2

DDR_XDP_WAN_SMBDAT <7,12,14,15,27,34>

DDR_XDP_WAN_SMBCLK <7,12,14,15,27,34>

RD15 0_0402_5%~D@ RD15 0_0402_5%~D@

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

CD38

CD38

1

2

12

+V_DDR_REF

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ize Document Number Rev

S

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

DDRIII-SODIMM SLOT2

LA-7901P

LA-7901P

LA-7901P

1

13 61Friday, March 02, 2012

13 61Friday, March 02, 2012

13 61Friday, March 02, 2012

1.0

1.0

1.0

of

5

+RTC_CELL

330K_0402_1%~D

330K_0402_1%~D

12

RH38

RH38

PCH_INTVRMEN

330K_0402_1%~D

330K_0402_1%~D

12

@RH39

@

D D

C C

B B

RH39

INTVRMEN- Integrated SUS

1.1V VRM Enable
High - Enable Internal VRs
Low - Enable External VRs

1

PCH_AZ_CODEC_SDOUT<29>

PCH_AZ_CODEC_SYNC<29>

PCH_AZ_CODEC_RST#<29>

PCH_AZ_CODEC_BITCLK<29>

1

@

@

ME1 SHORT PADS~D

ME1 SHORT PADS~D

1 2

CH5 1U_0402_6.3V6K~DCH5 1U_0402_6.3V6K~D

CMOS_CLR1

Shunt

Open

ME_CLR1

Shunt Clear ME RTC Registers

Open

1

2

+3.3V_ALW_PCH

1K_0402_1%~D

1K_0402_1%~D

12

RH66

RH66

PCH_AZ_SYNC

100K_0402_5%~D

100K_0402_5%~D

12

@RH282

@

RH282

PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.

+RTC_CELL

2

2

CMOS setting

Clear CMOS

Keep CMOS

TPM setting

Keep ME RTC Registers

RH29 33_0402 _5%~DRH29 33_0402_5%~D

1 2

RH26 33_0402 _5%~DRH26 33_0402_5%~D

1 2

RH27 33_0402 _5%~DRH27 33_0402_5%~D

1 2

RH25 33_0402 _5%~DRH25 33_0402_5%~D

1 2

27P_0402_50V8J~D

27P_0402_50V8J~D

@CH101

@

CH101

RH31 1M_0402_5 %~DRH31 1M_0402_5%~D

RH22 20K_0 402_5%~DRH22 20K_0402_5%~D

1 2

RH23 20K_0 402_5%~DRH23 20K_0402_5%~D

1 2

RH11 1M_040 2_5%~DRH11 1M_0402_5%~D

1 2

1

@

@

CMOS1 SHORT PADS~D

CMOS1 SHORT PADS~D

CH4

CH4

CMOS place near DIMM

PCH_AZ_SDOUT

PCH_AZ_SYNC_Q

PCH_AZ_RST#

PCH_AZ_BITCLK

1 2

1

1 2

PCH_AZ_SYNC_Q

2

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

+3.3V_ALW_PCH

12

0_0603_5%~D

0_0603_5%~D

INTEL HDA_SYNC isolation circuit

3.3K_0402_5%~D

3.3K_0402_5%~D

12

R890

R890

200 MIL SO8
64Mb Flash ROM

U52

SPI_PCH_CS0# SP I_PCH_CS0#_R

1 2

R935 47_0402_5%~DR935 47_0402_5%~D

SPI_PCH_DIN S PI_DIN64

1 2

R894 33_0402_5%~DR894 33_0402_5%~D

SPI_WP#_SEL_R

5

R898 0_0402_5%~D@R898 0_0402_5%~D@

1 2

SPI_WP#_SEL<39>

A A

U52

1

/CS

2

DO

3

/WP

GND4DIO

W25Q64CVSSIG_SO8

W25Q64CVSSIG_SO8

/HOLD

8

VCC

7

6

CLK

5

SLP_ME_CSW_DEV #<18,39>
USB_MCARD1_DET#<18,34>

SIO_EXT_SCI#_R<18>

PCH_RSMRST#_Q<16,41>

@

@

RH288

RH288

+3.3V_ALW_PCH_J TAG

+5V_RUN

G

G

2

13

D

S

D

S

QH7

QH7

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

+3.3V_SPI

SPI_CLK64

R899 33_04 02_5%~DR899 33_0402_5 %~D

SPI_DO64

R901 33_04 02_5%~DR901 33_0402_5 %~D

4

USB_OC0#_R<17>
USB_OC1#_R<17>

USB_OC2#<17>
USB_OC3#<17>

USB_OC4#_R<17>

USB_OC5#<17>
USB_OC6#<17>

SIO_EXT_SMI#<17,40>

PCH_GPIO36<18>
PCH_GPIO37<18>
PCH_GPIO16<18>

TEMP_ALERT#<18,39>

PCH_GPIO15<18>

CH2

CH2

12

15P_0402_50V8J~D

15P_0402_50V8J~D

CH3

CH3

12

15P_0402_50V8J~D

15P_0402_50V8J~D

@CH100

@

27P_0402_50V8J~D

27P_0402_50V8J~D

PCH_AZ_MDC_BITCLK<37 >

PCH_AZ_MDC_SYNC<37>

SPKR<29>

PCH_AZ_MDC_RST#<37>

+3.3V_ALW_PCH

PCH_AZ_MDC_SDOUT<37 >

ME_FWP<39>

RH59 51_0402 _1%~DRH59 51_0402_1%~D

RH44 200_0402_1%~DRH44 200_0402_1%~D

RH45 200_0402_1%~DRH45 200_0402_1%~D

RH43 200_040 2_1%~DRH43 200_0402_1%~D

PCH_AZ_SYNC

C746

C746

1 2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

3.3K_0402_5%~D

3.3K_0402_5%~D

12

R891

R891

SPI_HOLD#

SPI_PCH_CLK

1 2

SPI_PCH_DO

1 2

4

3

USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#
SIO_EXT_SMI#
SLP_ME_CSW_DEV #
USB_MCARD1_DET#

HDD_DET#_R

BBS_BIT0_R
PCH_GPIO36
PCH_GPIO37
PCH_GPIO16
TEMP_ALERT#
PCH_GPIO15
SIO_EXT_SCI#_R
PCH_RSMRST#_Q RSMRST#_XDP

12

YH1

YH1

32.768KHZ_12.5PF_Q13FC1350000~D

32.768KHZ_12.5PF_Q13FC1350000~D

PCH_RTCX2_R

CH100

12

PCH_AZ_CODEC_SDIN0< 29>

PCH_AZ_MDC_SDIN1<37>

12

12

12

12

RH1 33_0402_5%~DPXDP@ RH1 33_0402_5%~DPXDP @

1 2

RH3 33_0402_5%~DPXDP@ RH3 33_0402_5%~DPXDP @

1 2

RH4 33_0402_5%~DPXDP@ RH4 33_0402_5%~DPXDP @

1 2

RH5 33_0402_5%~DPXDP@ RH5 33_0402_5%~DPXDP @

1 2

RH6 33_0402_5%~DPXDP@ RH6 33_0402_5%~DPXDP @

1 2

RH7 33_0402_5%~DPXDP@ RH7 33_0402_5%~DPXDP @

1 2

RH8 33_0402_5%~DPXDP@ RH8 33_0402_5%~DPXDP @

1 2

RH9 33_0402_5%~DPXDP@ RH9 33_0402_5%~DPXDP @

1 2

RH10 33_0402 _5%~DPXDP@ RH10 33_0402_5%~DPXDP@

1 2

RH12 33_0402 _5%~DPXDP@ RH12 33_0402_5%~DPXDP@

1 2

RH13 33_0402 _5%~DPXDP@ RH13 33_0402_5%~DPXDP@

1 2

RH14 33_0402 _5%~DPXDP@ RH14 33_0402_5%~DPXDP@

1 2

RH15 33_0402 _5%~DPXDP@ RH15 33_0402_5%~DPXDP@

1 2

RH16 33_0402 _5%~DPXDP@ RH16 33_0402_5%~DPXDP@

1 2

RH17 33_0402 _5%~DPXDP@ RH17 33_0402_5%~DPXDP@

1 2

RH18 33_0402 _5%~DPXDP@ RH18 33_0402_5%~DPXDP@

1 2

RH19 33_0402 _5%~DPXDP@ RH19 33_0402_5%~DPXDP@

1 2

RH20 33_0402 _5%~DPXDP@ RH20 33_0402_5%~DPXDP@

1 2

RH24 1K_04 02_1%~DPXDP@ RH24 1K_0402_1%~DPXDP@

1 2

PCH_RTCX1

1 2

RH286 0_0402_5%~D@ RH286 0_0402_5%~D@

1 2

RH32 33_0402_5%~DRH32 33_0402_5%~ D

1 2

RH33 33_0402_5%~DRH33 33_0402_5%~ D

1 2

RH34 33_0402_5%~DRH34 33_0402_5%~D

RH287 1K_0402_1%~D@RH287 1K_0402_1%~ D@

1 2

RH36 33_0402_5%~ DRH36 33_0402_5%~D

1 2

RH50 1K_0402_ 1%~DRH50 1K_0402_1%~D

1 2

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

12

12

12

@

@

@

@

RH48

RH48

RH49

RH49

PCH_SPI_CLK

10P_0402_50V8J~D

10P_0402_50V8J~D

@

@

1

CE15

CE15

2

10M_0402_5%~D

10M_0402_5%~D

12

RH2

RH2

PCH_RTCX2

PCH_RTCRST#

SRTCRST#

INTRUDER#

PCH_INTVRMEN

PCH_AZ_CODEC_SDIN0

PCH_AZ_MDC_SDIN1

100_0402_1%~D

100_0402_1%~D

@

@

RH47

RH47

PCH_AZ_BITCLK

PCH_AZ_SYNCPCH_AZ_SYNC_Q

PCH_AZ_RST#

PCH_AZ_SDOUT

PCH_GPIO33

PCH_GPIO13

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_CS1#

PCH_SPI_DO

PCH_SPI_DIN

XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
XDP_FN15
XDP_FN16
XDP_FN17

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

C36

N32

H7

K5

H1

Y14

U3

Close to UH4.T3

SPI_PCH_CS1#

R936 47_0402_5%~DR936 47_0402_5%~D

1 2

R895 33_0402_5%~DR895 33_0402_5%~D

1 2

SPI_CLK64

33_0402_5%~D

33_0402_5%~D

12

@RE1

@

RE1

27P_0402_50V8J~D

27P_0402_50V8J~D

@CE1

@

1

CE1

2

Close to U52

3

UH4A

UH4A

RTCX1

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

T3

SPI_CLK

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

SPI_MISO

BD82HM77 QPRG C1_BGA989~D

BD82HM77 QPRG C1_BGA989~D

SPI_PCH_CS1#_R
SPI_DIN32
SPI_WP#_SEL_R

DDR_XDP_WAN_SMBDAT<7,12,13,15,27,34>

DDR_XDP_WAN_SMBCLK<7,12,13,15,27,34>

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

RTCIHDA

RTCIHDA

SATA 6G

SATA 6G

SATA

SATA LPC

SATAICOMPO

SATAICOMPI

JTAG

JTAG

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP / GPIO21

SPI

SPI

SATA1GP / GPIO19

U53

U53

1

CS#

2

DO

HOLD#

3

WP#

4

GND

W25Q32BVSSIG_SO8~D

W25Q32BVSSIG_SO8~D

200 MIL SO8
32Mb Flash ROM

+3.3V_ALW_PCH

RH283 1K_0402_1%~DPXDP @RH283 1K_0402_1%~DPXDP @

1.05V_0.8V_PWROK<40,51>
SIO_PWRBTN#_R<7,16>

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATALED#

1 2
1 2

RH21 0_0402_5%~DPXDP@RH21 0_0402_5%~ DPXDP@

RH284 0_0402_5%~DPXDP@RH284 0_0402_5 %~DPXDP@

1 2
1 2

RH285 0_0402_5%~D

RH285 0_0402_5%~D

PXDP@

PXDP@

LPC_LAD0

C38

LPC_LAD1

A38

LPC_LAD2

B37

LPC_LAD3

C37

LPC_LFRAME#

D36

E36

LPC_LDRQ1#

K36

IRQ_SERIRQ

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

SATA_COMP

Y10

AB12

SATA3_COMP

AB13

RBIAS_SATA3

AH1

SATA_ACT#

P3

HDD_DET#_R

V14

BBS_BIT0_R

P1

PCH_PLTRST#<7,17>

BBS_BIT0 - BIOS BOOT STRAP BIT 0

+3.3V_SPI

1 2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

8

VCC

SPI_HOLD#SPI_PCH_DIN

7
6

CLK

5

DI

R897 33_0402_5%~DR897 33_0402_5%~D

SPI_DO32

R900 33_0402_5%~DR900 33_0402_5%~D

SPI_CLK32

Close to U53

2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

PXDP@ CH1

PXDP@

1

CH1

2

1.05V_0.8V_PWROK_R
PCH_PWRBTN#_XDP

DDR_XDP_WAN_SMBDAT_R2
DDR_XDP_WAN_SMBCLK _R2

LPC_LAD0 <32,34,39,40>
LPC_LAD1 <32,34,39,40>
LPC_LAD2 <32,34,39,40>
LPC_LAD3 <32,34,39,40>

LPC_LFRAME# <32,34,39,40 >

LPC_LDRQ1# <39>

IRQ_SERIRQ <32,39,40>

PSATA_PRX_DTX_N0_C <27>
PSATA_PRX_DTX_P0_C <27>
PSATA_PTX_DRX_N0_C <27>
PSATA_PTX_DRX_P0_C <27>

SATA_ODD_PRX_DTX_N1_C <28>
SATA_ODD_PRX_DTX_P1_C <28>
SATA_ODD_PTX_DRX_N1_C <28>
SATA_ODD_PTX_DRX_P1_C <28>

ESATA_PRX_DTX_N4_C <36>
ESATA_PRX_DTX_P4_C <36>
ESATA_PTX_DRX_N4_C <36>
ESATA_PTX_DRX_P4_C <36>

SATA_PRX_DKTX_N5_C <38>
SATA_PRX_DKTX_P5_C <38>
SATA_PTX_DKRX_N5_C <38>
SATA_PTX_DKRX_P5_C <38>

1 2

RH40 37.4_0402_1%~DRH40 37.4_0402_1%~D

1 2

RH42 49.9_0402_1%~DRH42 49.9_0402_1%~D

1 2

RH46 750_0402_1%~DRH46 750_0402_1%~D

SATA_ACT# <43>

RH290 0_0402_5%~D@RH290 0_0402_5%~D@

1 2

D

D

1 3

G

G

2

C745

C745

1 2
1 2

33_0402_5%~D

33_0402_5%~D

12

@RE2

@

RE2

27P_0402_50V8J~D

27P_0402_50V8J~D

@CE2

@

1

CE2

2

2

+3.3V_ALW_PCH

XDP_FN0
XDP_FN1

XDP_FN2
XDP_FN3

XDP_FN4
XDP_FN5

XDP_FN6
XDP_FN7

+1.05V_RUN

+1.05V_RUN

S

S

QH1

QH1

BSS138W-7-F_SOT323-3~D

BSS138W-7-F_SOT323-3~D

SPI_PCH_CLKSPI_CLK32

SPI_PCH_DO

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

SAMTE_BSH-030-01-L-D-A

HDD

ODD/ E Module Bay

E-SATA

DOCK

HDD_DET# <27>

PCH_SATA_MOD_EN# <40>

+3.3V_SPI

+3.3V_M_RUN

1

JXDP2

JXDP2

HM76(w/o vpro): depop RH350 and pop RH359
QM77(w/ vpro) : pop RH350 and depop RH359

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10

OBSDATA_C0

12

OBSDATA_C1

14

GND5

16

OBSDATA_C2

18

OBSDATA_C3

20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28

OBSDATA_D0

30

OBSDATA_D1

32

GND11

34

OBSDATA_D2

36

OBSDATA_D3

38

GND13

40

ITPCLK/HOOK4

42

ITPCLK#/HOOK5

44

VCC_OBS_CD

46

RESET#/HOOK6

48

DBR#/HOOK7

50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

CONN@

CONN@

PCH_GPIO33

IRQ_SERIRQ

BBS_BIT0_R

HDD_DET#

SPKR

PCH_GPIO13

+3.3V_M_RUN

RH360 0_0603_5%~DRH360 0_0603_5%~D

RH359 0_0603_5%~D@ RH359 0_0603_5%~D@

RH350 0_0603_5%~DRH35 0 0_06 03_5%~D

XDP_FN16
XDP_FN17

XDP_FN8
XDP_FN9

XDP_FN10
XDP_FN11

XDP_FN12
XDP_FN13

XDP_FN14
XDP_FN15

+3.3V_ALW_PCH

RSMRST#_XDP
XDP_DBRESET#

PCH_JTAG_TDO

PCH_JTAG_TDI
PCH_JTAG_TMSPCH_JTAG_TCK

RH355 100K_0402_5%~DRH355 100K_0402 _5%~D

12

RH28 8.2K_0402_5%~DRH28 8.2K_0402_5%~D

12

RH52 4.7K_0402_5%~DRH52 4.7K_0402_5%~D

12

RH30 10K_0402_5%~DRH30 10K_0402_5%~D

12

RH35 10K_0402_5%~D@ RH35 10K_0402_5%~D@

12

No Reboot Strap

Low = Default

SPKR

High = No Reboot

R712 100K_0402_5%~DR712 100K_0402_5%~D

12

SPI_PCH_CS1#

RH3450_0402_5%~D RH3450_0402_5%~D

12

PCH_SPI_CS1#
SPI_PCH_DO

RH3460_0402_5%~D RH3460_0402_5%~D

12

PCH_SPI_DO
SPI_PCH_DIN

RH3470_0402_5%~D RH3470_0402_5%~D

12

PCH_SPI_DIN
SPI_PCH_CLK

RH3480_0402_5%~D RH3480_0402_5%~D

12

PCH_SPI_CLK
SPI_PCH_CS0#

RH3490_0402_5%~D RH3490_0402_5%~D

12

PCH_SPI_CS0#

12

+3.3V_RUN

12

+3.3V_M

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

S

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8)

PCH (1/8)

ize Document Number Rev

PCH (1/8)

LA-7901P

LA-7901P

LA-7901P

1

XDP_DBRESET# <7,16>

+3.3V_RUN

+3.3V_ALW_PCH

JSPI1

JSPI1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

G1

18

G2

HRS_FH12-16S-0P5SH(55)~D

HRS_FH12-16S-0P5SH(55)~D

CONN@

CONN@

14 61Saturday, March 03, 2012

14 61Saturday, March 03, 2012

14 61Saturday, March 03, 2012

of

1.0

1.0

1.0

5

4

+3.3V_ALW_PCH

3

+3.3V_RUN

2

1

2

SIO_LAN_SMBCLK<30,40>

D D

WWAN (Mini Card 1)--->

WLAN (Mini Card 2)--->

EXPRESS Card--- >

1/2 MINI CARD-3 PCIE
(Mini Card 3)--->

C C

MMI --->

10/100/1G LAN - -->

WWAN (Mini Card 1)--->

10/100/1G LAN - -->

MMI--->

B B

PP (Mini Card 3 )--->

Express card--- >

WLAN (Mini Card 2)--->

A A

SIO_LAN_SMBDATA<30,40>

PCIE_PRX_WANTX_N1<34>
PCIE_PRX_WANTX_P1<34>
PCIE_PTX_WANRX_N1<34>
PCIE_PTX_WANRX_P1<34>

PCIE_PRX_WLANTX_N2<34>

PCIE_PRX_WLANTX_P2<34>
PCIE_PTX_WLANRX_N2<34>
PCIE_PTX_WLANRX_P2<34>

PCIE_PRX_EXPTX_N3<35>
PCIE_PRX_EXPTX_P3<35>
PCIE_PTX_EXPRX_N3<35>
PCIE_PTX_EXPRX_P3<35>

PCIE_PRX_WPANTX_N5<34>

PCIE_PRX_WPANTX_P5<34>
PCIE_PTX_WPANRX_N5<34>
PCIE_PTX_WPANRX_P5<34>

PCIE_PRX_MMITX_N6<33>
PCIE_PRX_MMITX_P6<33>
PCIE_PTX_MMIRX_N6<33>
PCIE_PTX_MMIRX_P6<33>

PCIE_PRX_GLANTX_N7<30>
PCIE_PRX_GLANTX_P7<30>
PCIE_PTX_GLANRX_N7<30>
PCIE_PTX_GLANRX_P7<30>

CLK_PCIE_MINI1#<34>
CLK_PCIE_MINI1<34>

+3.3V_ALW_PCH

LANCLK_REQ#<30>

MMICLK_REQ#<33>

CLK_PCIE_MINI3#<34>

CLK_PCIE_MINI3<34>

CLK_PCIE_MINI2#<34>

+3.3V_ALW_PCH

CLK_CPU_ITP#<7>

CLK_CPU_ITP<7>

MINI1CLK_REQ#<34>

CLK_PCIE_LAN#<30>
CLK_PCIE_LAN<30>

CLK_PCIE_MMI#<33>
CLK_PCIE_MMI<33>

+3.3V_RUN

+3.3V_ALW_PCH

MINI3CLK_REQ#<34>

CLK_PCIE_EXP#<35>

CLK_PCIE_EXP<35>

+3.3V_ALW_PCH

EXPCLK_REQ#<35>

CLK_PCIE_MINI2<34>

MINI2CLK_REQ#<34>

+3.3V_ALW_PCH

+3.3V_ALW_PCH

+3.3V_ALW_PCH

RH307 0_0402_5%~D@RH307 0_0402_5%~D@
RH308 0_0402_5%~D@RH308 0_0402_5%~D@
RH81 10K_0402_5%~DRH81 10K_0402_5%~D

RH82 0_0402_5%~D@ RH82 0_0402_5%~D@
RH83 0_0402_5%~D@ RH83 0_0402_5%~D@

RH85 0_0402_5%~D@ RH85 0_0402_5%~D@
RH86 0_0402_5%~D@ RH86 0_0402_5%~D@

RH87 10K_0402_5%~DRH87 10K_0402_5%~D

RH88 0_0402_5%~D@ RH88 0_0402_5%~D@
RH90 0_0402_5%~D@ RH90 0_0402_5%~D@

RH152 10K_0402_5%~DRH152 10K_0402_5%~D

RH92 0_0402_5%~D@ RH92 0_0402_5%~D@
RH93 0_0402_5%~D@ RH93 0_0402_5%~D@

RH94 10K_0402_5%~DRH94 10K_0402_5%~D

RH95 0_0402_5%~D@ RH95 0_0402_5%~D@
RH96 0_0402_5%~D@ RH96 0_0402_5%~D@

RH97 10K_0402_5%~DRH97 10K_0402_5%~D

RH98 10K_0402_5%~DRH98 10K_0402_5%~D

RH110 10K_0402_5%~DRH110 10K_0402_5%~D

RH104 10K_0402_5%~DRH104 10K_0402_5%~D

RH280 0_0402_5%~D@RH280 0_0402_5%~D@
RH281 0_0402_5%~D@RH281 0_0402_5%~D@

6 1

5

3

QH8B

QH8B

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

PCIE_PRX_WANTX_N1
PCIE_PRX_WANTX_P1
PCIE_PTX_WANRX_N1
PCIE_PTX_WANRX_P1

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3
PCIE_PTX_EXPRX_P3

PCIE_PRX_WPANTX_N5
PCIE_PRX_WPANTX_P5
PCIE_PTX_WPANRX_N5
PCIE_PTX_WPANRX_P5

PCIE_PRX_MMITX_N6
PCIE_PRX_MMITX_P6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6

PCIE_PRX_GLANTX_N7
PCIE_PRX_GLANTX_P7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7

12
12

12

12
12

12
12

1 2

12
12

12

12
12

12

12
12

12

1 2

12

12

12
12

PCIE REQ power rail:

MEM_SMBCLK

QH8A

QH8A

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

MEM_SMBDATA

4

PCIE_MINI1#
PCIE_MINI1

MINI1CLK_REQ#

PCIE_LAN#
PCIE_LAN

LANCLK_REQ#

PCIE_MMI#
PCIE_MMI

MMICLK_REQ#

PCIE_MINI3#
PCIE_MINI3

MINI3CLK_REQ#

PCIE_EXP#
PCIE_EXP

EXPCLK_REQ#

PCIE_MINI2#
PCIE_MINI2

MINI2CLK_REQ#

PEG_B_CLKRQ#

PCIECLKRQ6#

PCIECLKRQ7#

CLK_BCLK_ITP#
CLK_BCLK_ITP

UH4B

UH4B

BG34

BJ34
AV32
AU32

BE34
BF34
BB32
AY32

BG36

BJ36
AV34
AU34

BF36
BE36
AY34
BB34

BG37
BH37
AY36
BB36

BJ38
BG38
AU36
AV36

BG40

BJ40
AY40
BB40

BE38
BC38

AW38

AY38

Y40
Y39

J2

AB49
AB47

M1

AA48
AA47

V10

Y37
Y36

A8

Y43
Y45

L12

V45
V46

L14

AB42
AB40

E6

V40
V42

T13

V38
V37

K12

AK14
AK13

BD82HM77 QPRG C1_BGA989~D

BD82HM77 QPRG C1_BGA989~D

MEM_SMBCLK

MEM_SMBDATA

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

PERN7
PERP7
PETN7
PETP7

PERN8
PERP8
PETN8
PETP8

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N
CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N
CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N
CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N
CLKOUT_PCIE6P

PCIECLKRQ6# / GPIO45

CLKOUT_PCIE7N
CLKOUT_PCIE7P

PCIECLKRQ7# / GPIO46

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

SMBUSController

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

PCI-E*

CLOCKS

CLOCKS

3

QH5B

QH5B

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

suspend: 0 3 4 5 6 7
core: 1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

6 1

QH5A

QH5A

5

DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

4

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

2

E12

H14

C9

A12

C8

G12

C13

E14

M16

M7

T11

P10

M10

AB37
AB38

AV22
AU22

AM12
AM13

BF18
BE18

BJ30
BG30

G24
E24

AK7
AK5

K45

H45

V47
V49

Y47

K43

F47

H47

K49

DDR_XDP_WAN_SMBCLK <7,12,13,14,27,34>

DDR_XDP_WAN_SMBDAT <7,12,13,14,27,34>

PCH_SMB_ALERT#

MEM_SMBCLK

MEM_SMBDATA

DDR_HVREF_RST_PCH

SML0CLK

SML0DATA

PCH_GPIO74

SML1_SMBCLK

SML1_SMBDATA

PCH_CL_CLK1

PCH_CL_DATA1

PCH_CL_RST1#

PEG_A_CLKRQ#

CLK_CPU_DMI#
CLK_CPU_DMI

CLK_BUF_DMI#
CLK_BUF_DMI

CLK_BUF_BCLK
CLK_BUF_BCLK

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLK_PCH_14M

CLK_PCI_LOOPBACK

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

CLK_48M

SIO_14M

PCI_TPM_TCM

JETWAY_14M

RH100 90.9_0402_1%~DRH100 90.9_0402_1%~D

RH322 22_0402_5%~DRH322 22_0402_5%~D

RH313 22_0402_5%~DRH313 22_0402_5%~D

RH311 10_0402_1%~D5@ RH311 10_0402_1%~D5@
RH314 10_0402_1%~DRH314 10_0402_1%~D
RH315 22_0402_5%~D@ RH315 22_0402_5%~D@

DDR_HVREF_RST_PCH <7>

SML1_SMBCLK <30,40>

SML1_SMBDATA <30,40>

PCH_CL_CLK1 <34>

PCH_CL_DATA1 <34>

PCH_CL_RST1# <34>

CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>

CLK_PCI_LOOPBACK <17>

1 2

12

12

12
12
12

2

SML1_SMBCLK

SML1_SMBDATA

DDR_HVREF_RST_PCH

PCH_GPIO74

MEM_SMBCLK

MEM_SMBDATA

PCH_SMB_ALERT#

PEG_A_CLKRQ#

SML0CLK

SML0DATA

RH298 2.2K_0402_5%~DRH298 2.2K_0402_5%~D

1 2

RH299 2.2K_0402_5%~DRH299 2.2K_0402_5%~D

1 2

RH300 1K_0402_1%~DRH300 1K_0402_1%~D

RH301 10K_0402_5%~DRH301 10K_0402_5%~D

RH302 2.2K_0402_5%~DRH302 2.2K_0402_5%~D

RH303 2.2K_0402_5%~DRH303 2.2K_0402_5%~D

RH304 10K_0402_5%~DRH304 10K_0402_5%~D

RH80 10K_0402_5%~DRH80 10K_0402_5%~D

RH305 2.2K_0402_5%~DRH305 2.2K_0402_5%~D

RH306 2.2K_0402_5%~DRH306 2.2K_0402_5%~D

10P_0402_50V8J~D

10P_0402_50V8J~D

@CE17

@

1

CE17

2

RF review in 0629

CLK_BUF_DMI#
CLK_BUF_DMI

CLK_BUF_BCLK

CLK_BUF_DOT96#
CLK_BUF_DOT96

CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD

CLK_PCH_14M

RH74 10K_0402_5%~DRH74 10K_0402_5%~D

1 2

RH75 10K_0402_5%~DRH75 10K_0402_5%~D

1 2

RH91 10K_0402_5%~DRH91 10K_0402_5%~D

1 2

RH76 10K_0402_5%~DRH76 10K_0402_5%~D

1 2

RH77 10K_0402_5%~DRH77 10K_0402_5%~D

1 2

RH78 10K_0402_5%~DRH78 10K_0402_5%~D

1 2

RH79 10K_0402_5%~DRH79 10K_0402_5%~D

1 2

RH183 10K_0402_5%~DRH183 10K_0402_5%~D

1 2

CLOCK TERMINATION for FCIM and need close to PCH

1M_0402_5%~D

1M_0402_5%~D

RH309 0_0402_5%~D@RH309 0_0402_5%~D@

12

RH99

RH99

YH2

+1.05V_RUN

CLK_SMART_48M <35>

CLK_SIO_14M <39>

CLK_PCI_TPM_TCM <32>
PCLK_80H <34>

JETWAY_CLK14M <32>

10P_0402_50V8J~D

10P_0402_50V8J~D

2

CH18

CH18

1

YH2

25MHZ_10PF_Q22FA2380049900~D

25MHZ_10PF_Q22FA2380049900~D

3

OUT

4

GND

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

S

ize Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

12

12

12

12

12

12

12

12

PCH_CL_CLK1CLK_PCI_LOOPBACK

12

1

IN

2

GND

PCH (2/8)

PCH (2/8)

PCH (2/8)

LA-7901P

LA-7901P

LA-7901P

1

+3.3V_ALW_PCH

10P_0402_50V8J~D

10P_0402_50V8J~D

@

@

1

CE16

CE16

2

10P_0402_50V8J~D

10P_0402_50V8J~D

2

CH19

CH19

1

15 61Saturday, March 03, 2012

15 61Saturday, March 03, 2012

15 61Saturday, March 03, 2012

1.0

1.0

1.0

of

5

4

3

2

1

RH357 0_0402_5%~DRH357 0_0402_5%~D

1 2

RH113 0_0402_5%~D@RH113 0_0402_5%~D@

RH323 0_0402_5%~D@RH323 0_0402_5%~D@

RH321 0_0402_5%~D@RH321 0_0402_5%~D@

RH119 0_0402_5%~D@RH119 0_0402_5%~D@

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

+3.3V_RUN

1

B

2

A

1 2

1 2

1 2

DSWODVREN

PCH_DPWROK

PCH_PCIE_WAKE#

CLKRUN#

SUS_STAT#/LPCPD#

SUSCLK

SIO_SLP_S5#

SIO_SLP_S4#

SIO_SLP_S3#

SIO_SLP_A#

SIO_SLP_SUS#

H_PM_SYNC

SIO_SLP_LAN#

CH99

@CH99

@

1 2

5

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

P

4

O

G

UC3

@UC3

@

74AHC1G09GW_TSSOP5~D

74AHC1G09GW_TSSOP5~D

3

12

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

SYS_RESET#

FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>

FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>

FDI_INT <6>

FDI_FSYNC0 <6>

FDI_FSYNC1 <6>

FDI_LSYNC0 <6>

FDI_LSYNC1 <6>

PCH_PCIE_WAKE# <40>

CLKRUN# <32,39,40>

T56 PAD~D @T56 PAD~D @

T57 PAD~D @T57 PAD~D @

T58 PAD~D @T58 PAD~D @

SIO_SLP_S5# <40,42>

T59 PAD~D @T59 PAD~D @

SIO_SLP_S4# <39,42,46>

SIO_SLP_S3# <11,27,35,39,42,47,48,49>

SIO_SLP_A# <39,42,48>

T62 PAD~D @T62 PAD~D @

SIO_SLP_SUS# <39>

T63 PAD~D @T63 PAD~D @

H_PM_SYNC <7>

SIO_SLP_LAN# <30,39>

PCH_CRT_BLU

PCH_CRT_GRN

PCH_CRT_RED

ENVDD_PCH

3

RH131 150_0402_1%~DRH131 150_0402_1%~D

RH132 150_0402_1%~DRH132 150_0402_1%~D

RH133 150_0402_1%~DRH133 150_0402_1%~D

RH134 100K_0402_5%~DRH134 100K_0402_5%~D

+3.3V_ALW_PCH

D D

+3.3V_RUN

C C

+1.05V_RUN

SUSACK#<39> PCH_DPWROK <39>

SYS_PWROK<7,39>

B B

A A

RESET_OUT#<40>

PM_DRAM_PWRGD<7>

PCH_RSMRST#_Q<14,41>

ME_SUS_PWR_ACK<40>

SIO_PWRBTN#_R<7,14>

SIO_PWRBTN#<40>

+3.3V_ALW_PCH

SIO_SLP_A#

PM_APWROK<40>

RH118 0_0402_5%~D@RH118 0_0402_5%~D@

5

1 2

RH318 10K_0402_5%~D@ RH318 10K_0402_5%~D@

1 2

RH144 10K_0402_5%~DRH144 10K_0402_5%~D

1 2

RH142 10K_0402_5%~DRH142 10K_0402_5%~D

1 2

RH319 10K_0402_5%~D@ RH319 10K_0402_5%~D@

1 2

RH140 10K_0402_5%~DRH140 10K_0402_5%~D

1 2

RH137 8.2K_0402_5%~DRH137 8.2K_0402_5%~D

1 2

RH138 8.2K_0402_5%~D@RH138 8.2K_0402_5%~D@

DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>

DMI_CRX_PTX_N0<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N3<6>

DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>

1 2

RH111 49.9_0402_1%~DRH111 49.9_0402_1%~D

1 2

RH112 750_0402_1%~DRH112 750_0402_1%~D

1 2

RH114 0_0402_5%~D@ RH114 0_0402_5%~D@

1 2

RH116 0_0402_5%~D@ RH116 0_0402_5%~D@

1 2

RH117 0_0402_5%~D@ RH117 0_0402_5%~D@

1 2

RH320 0_0402_5%~D@ RH320 0_0402_5%~D@

1 2

RH120 0_0402_5%~D@ RH120 0_0402_5%~D@

1 2

RH121 0_0402_5%~D@ RH121 0_0402_5%~D@

1 2

RH122 0_0402_5%~D@ RH122 0_0402_5%~D@

AC_PRESENT<40>

1 2

RH139 8.2K_0402_5%~DRH139 8.2K_0402_5%~D

+3.3V_ALW2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

5

1

P

B

4

O

2

A

G

UH5

UH5

3

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

1 2

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

DMI_COMP_R

RBIAS_CPY

SUSACK#_R

SYS_RESET#

SYS_PWROK_R

PCH_PWROK

PM_APWROK_R

PM_DRAM_PWRGD_R

PCH_RSMRST#_R

ME_SUS_PWR_ACK_R

SIO_PWRBTN#_R

AC_PRESENT

PCH_BATLOW#

PCH_RI#

CH108

CH108

1 2

PM_APWROK_R

SUS_STAT#/LPCPD#

ME_SUS_PWR_ACK

PCH_PCIE_WAKE#

SIO_SLP_LAN#

PCH_RI#

CLKRUN#

ME_RESET#

XDP_DBRESET#<7,14>

UH4C

UH4C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SU SPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82HM77 QPRG C1_BGA989~D

BD82HM77 QPRG C1_BGA989~D

ME_RESET#

RH141 8.2K_0402_5%~D@ RH141 8.2K_0402_5%~D@

4

12

PCH_DPWROK PCH_RSMRST#_R

ME_SUS_PWR_ACK_R SUSACK#_R

SYS_PWROK_R RESET_OUT#

RESET_OUT# PM_APWROK_R

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

DMI

FDI

DMI

FDI

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

System Power Management

System Power Management

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

+RTC_CELL

330K_0402_1%~D

330K_0402_1%~D

RH127

RH127

1 2

DSWODVREN

PCH_CRT_HSYNC<23>
PCH_CRT_VSYNC<23>

330K_0402_1%~D

330K_0402_1%~D

DSWODVREN - On Die DSW VR Enable

@RH129

@

12

RH129

Enabled (DEFAULT)

HIGH: RH127 STUFFED,
RH129 UNSTUFFED

Disabled

LOW: RH129 STUFFED,
RH127 UNSTUFFED

UH4D

HSYNC
VSYNC

M45

AF37
AF36

AE48
AE47

AK39
AK40

AN48
AM47
AK47

AJ48

AN47
AM49
AK49

AJ47

AF40
AF39

AH45
AH47
AF49
AF45

AH43
AH49
AF47
AF43

M40

M47
M49

J47

P45

T40
K47

T45
P39

N48
P49
T49

T39

T43
T42

2

UH4D

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_CL K
L_DDC_DATA

L_CTRL_C LK
L_CTRL_D ATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_ CLK
CRT_DDC_ DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

BD82HM77 QPRG C1_BGA989~D

BD82HM77 QPRG C1_BGA989~D

1 2

1 2
1 2

PANEL_BKEN_PCH
ENVDD_PCH

BIA_PWM_PCH

LDDC_CLK_PCH
LDDC_DATA_PCH

LVD_IBG

LCD_ACLK-_PCH
LCD_ACLK+_PCH

LCD_A0-_PCH
LCD_A1-_PCH
LCD_A2-_PCH

LCD_A0+_PCH
LCD_A1+_PCH
LCD_A2+_PCH

LCD_BCLK-_PCH
LCD_BCLK+_PCH

LCD_B0-_PCH
LCD_B1-_PCH
LCD_B2-_PCH

LCD_B0+_PCH
LCD_B1+_PCH
LCD_B2+_PCH

PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED

PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT

CRT_IREF

1K_0402_0.5%~D

1K_0402_0.5%~D

12

RH126

RH126

PANEL_BKEN_PCH<24>

ENVDD_PCH<24,39>

BIA_PWM_PCH<24>

LDDC_CLK_PCH<24>
LDDC_DATA_PCH<24>

RH344 2.37K_0402_1%~DRH344 2.37K_0402_1%~D

Minimum speacing of 20mils for LVD_IBG

LCD_ACLK-_PCH<24>
LCD_ACLK+_PCH<24>

LCD_A0-_PCH<24>
LCD_A1-_PCH<24>
LCD_A2-_PCH<24>

LCD_A0+_PCH<24>
LCD_A1+_PCH<24>
LCD_A2+_PCH<24>

LCD_BCLK-_PCH<24>
LCD_BCLK+_PCH<24>

LCD_B0-_PCH<24>
LCD_B1-_PCH<24>
LCD_B2-_PCH<24>

LCD_B0+_PCH<24>
LCD_B1+_PCH<24>
LCD_B2+_PCH<24>

PCH_CRT_BLU<23>
PCH_CRT_GRN<23>
PCH_CRT_RED<23>

PCH_CRT_DDC_CLK<23>

PCH_CRT_DDC_DAT<23>

RH123 20_0402_1%~DRH123 20_0402_1%~D
RH124 20_0402_1%~DRH124 20_0402_1%~D

12

12

12

12

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PCH_CRT_DDC_CLK

PCH_CRT_DDC_DAT

PCH_SDVO_CTRLCLK

PCH_SDVO_CTRLDATA

LVDS

LVDS

Digital Display Interface

Digital Display Interface

CRT

CRT

RH317 2.2K_0402_5%~DRH317 2.2K_0402_5%~D

RH316 2.2K_0402_5%~DRH316 2.2K_0402_5%~D

RH351 2.2K_0402_5%~DRH351 2.2K_0402_5%~D

RH352 2.2K_0402_5%~DRH352 2.2K_0402_5%~D

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCL K

SDVO_CTRLDATA

DDPC_CTR LCLK

DDPC_CTR LDATA

DDPD_CTR LCLK

DDPD_CTR LDATA

DELL CONFIDENTIAL/PROPRIETARY

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3.3V_RUN

12

12

12

12

PCH_SDVO_CTRLCLK <25>

PCH_SDVO_CTRLDATA <25>

HDMIB_PCH_HPD <25>

TMDSB_PCH_N2 <25>
TMDSB_PCH_P2 <25>
TMDSB_PCH_N1 <25>
TMDSB_PCH_P1 <25>
TMDSB_PCH_N0 <25>
TMDSB_PCH_P0 <25>
TMDSB_PCH_CLK# <25>
TMDSB_PCH_CLK <25>

PCH_DDPC_CTRLCLK <26>

PCH_DDPC_CTRLDATA <26>

DPC_PCH_DOCK_AUX# <26>
DPC_PCH_DOCK_AUX <26>
DPC_PCH_DOCK_HPD <38>

DPC_PCH_LANE_N0 <38>
DPC_PCH_LANE_P0 <38>
DPC_PCH_LANE_N1 <38>
DPC_PCH_LANE_P1 <38>
DPC_PCH_LANE_N2 <38>
DPC_PCH_LANE_P2 <38>
DPC_PCH_LANE_N3 <38>
DPC_PCH_LANE_P3 <38>

PCH_DDPD_CTRLCLK <26>

PCH_DDPD_CTRLDATA <26>

DPD_PCH_DOCK_AUX# <26>
DPD_PCH_DOCK_AUX <26>
DPD_PCH_DOCK_HPD <38>

DPD_PCH_LANE_N0 <38>
DPD_PCH_LANE_P0 <38>
DPD_PCH_LANE_N1 <38>
DPD_PCH_LANE_P1 <38>
DPD_PCH_LANE_N2 <38>
DPD_PCH_LANE_P2 <38>
DPD_PCH_LANE_N3 <38>
DPD_PCH_LANE_P3 <38>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH (3/8)

PCH (3/8)

PCH (3/8)

LA-7901P

LA-7901P

LA-7901P

1

1.0

1.0

16 61Saturday, March 03, 2012

16 61Saturday, March 03, 2012

16 61Saturday, March 03, 2012

1.0

5

D D

C C

+3.3V_RUN

1 2

RH324 8.2K_0402_5%~DR H324 8.2K_0402_5%~D

1 2

RH325 8.2K_0402_5%~DR H325 8.2K_0402_5%~D

1 2

RH326 8.2K_0402_5%~DR H326 8.2K_0402_5%~D

1 2

RH329 8.2K_0402_5%~DR H329 8.2K_0402_5%~D

1 2

RH327 10K_0402_5%~DRH327 10K_0402_5%~D

1 2

RH330 10K_0402_5%~DRH330 10K_0402_5%~D

1 2

RH331 10K_0402_5%~DRH331 10K_0402_5%~D

1 2

RH328 10K_0402_5%~DRH328 10K_0402_5%~D

1 2

RH332 10K_0402_5%~DRH332 10K_0402_5%~D

1 2

RH361 10K_0402_5%~DRH361 10K_0402_5%~D

PCI_GNT3#

1K_0402_1%~D

1K_0402_1%~D

@RH333

@

12

RH333

PCI_PIRQA#

PCI_PIRQB#

PCI_PIRQC#

PCI_PIRQD#

PCI_REQ1#

LCD_CBL_DET#

CAM_MIC_CBL_DET#

BT_DET#

PCH_GPIO3

PCIE_MCARD2_DET#

A16 swap override Strap/Top-Block

Swap Override jumper

PCI_GNT#3

B B

Low = A16 swap

High = Default

HDD_FALL_INT< 27>

PLTRST_MMI#<33>
PLTRST_XDP#<7>
PLTRST_LAN#<30>

CLK_PCI_5048<39>

CLK_PCI_MEC<40>

CLK_PCI_DOCK<38>

CLK_PCI_LOOPBACK<15>

1 2

RH334 0_0402_5%~D@ RH334 0_0402_5%~D@

RH336 0_0402_5%~D@ RH336 0_0402_5%~D@

1 2

RH337 0_0402_5%~DRH337 0_0402_5%~D

1 2

RH338 0_0402_5%~D@ RH338 0_0402_5%~D@

1 2

RH160 22_0402_5%~DRH160 22_0402_5%~D
RH102 22_0402_5%~DRH102 22_0402_5%~D
RH103 22_0402_5%~DRH103 22_0402_5%~D

RH105 22_0402_5%~DRH105 22_0402_5%~D

4

UH4E

UH4E

T72PAD~D @T72PAD~D @
T64PAD~D @T64PAD~D @
T73PAD~D @T73PAD~D @
T65PAD~D @T65PAD~D @
T74PAD~D @T74PAD~D @
T66PAD~D @T66PAD~D @
T67PAD~D @T67PAD~D @
T75PAD~D @T75PAD~D @
T76PAD~D @T76PAD~D @
T77PAD~D @T77PAD~D @
T68PAD~D @T68PAD~D @
T69PAD~D @T69PAD~D @
T78PAD~D @T78PAD~D @
T79PAD~D @T79PAD~D @
T80PAD~D @T80PAD~D @
T70PAD~D @T70PAD~D @
T81PAD~D @T81PAD~D @
T71PAD~D @T71PAD~D @
T82PAD~D @T82PAD~D @
T83PAD~D @T83PAD~D @

T84PAD~D @T84PAD~D @
T85PAD~D @T85PAD~D @
T86PAD~D @T86PAD~D @
T87PAD~D @T87PAD~D @

USB3RN2<36>
USB3RN3<36>
USB3RN4<38>

USB3RP2<36>
USB3RP3<36>
USB3RP4<38>

USB3TN2<36>
USB3TN3<36>
USB3TN4<38>

USB3TP2<36>
USB3TP3<36>
USB3TP4<38>

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCIE_MCARD2_DET#<34>

BT_DET#<41>

LCD_CBL_DET#<24>

CAM_MIC_CBL_DET#<24>

12
12
12

12

PCI_REQ1#

BBS_BIT1

PCI_GNT3#

LCD_CBL_DET#
PCH_GPIO3
CAM_MIC_CBL_DET#
FFS_PCH_INT

T104PAD~D @T104PAD~D @

PCH_PLTRST#

PCI_5048
PCI_MEC
PCI_DOCK

PCI_LOOPBACKOUT

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3TP1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82HM77 QPRG C1_BGA989~D

BD82HM77 QPRG C1_BGA989~D

RSVD

RSVD

USB30

USB30

PCI

PCI

3

USB

USB

RSVD1
RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22

RSVD23
RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5
AV10

AT8

AY5
BA2

AT12
BF3

USBP0-

C24

USBP0+

A24

USBP1-

C25

USBP1+

B25

USBP2-

C26

USBP2+

A26

USBP3-

K28

USBP3+

H28

USBP4-

E28

USBP4+

D28

USBP5-

C28

USBP5+

A28

USBP6-

C29

USBP6+

B29

USBP7-

N28

USBP7+

M28

USBP8-

L30

USBP8+

K30

USBP9-

G30

USBP9+

E30

USBP10-

C30

USBP10+

A30

USBP11-

L32

USBP11+

K32

USBP12-

G32

USBP12+

E32

USBP13-

C32

USBP13+

A32

USBRBIAS

C33

B33

A14
K20
B17
C16
L16
A16
D14
C14

RH151 22.6_0402_1%~DRH151 22.6_0402_1%~D

Route single-end 50-ohms and max 500-mils length.
Minimum spacing to other signals: 15 mils

USB_OC0#_R
USB_OC1#_R
USB_OC2#
USB_OC3#
USB_OC4#_R
USB_OC5#
USB_OC6#

1 2

RH339 0_0402_5%~D@ RH339 0_0402_5%~D@
RH341 0_0402_5%~D@ RH341 0_0402_5%~D@

RH356 0_0402_5%~D@ RH356 0_0402_5%~D@

USBP0- <37>
USBP0+ <37>
USBP1- <36>
USBP1+ <36>
USBP2- <36>
USBP2+ <36>
USBP3- <38>
USBP3+ <38>
USBP4- <34>
USBP4+ <34>
USBP5- <34>
USBP5+ <34>
USBP6- <34>
USBP6+ <34>
USBP7- <38>
USBP7+ <38>

USBP9- <37>
USBP9+ <37>
USBP10- <35>
USBP10+ <35>
USBP11- <41>
USBP11+ <41>
USBP12- <24>
USBP12+ <24>
USBP13- <32>
USBP13+ <32>

1 2
1 2

1 2

2

----->Back Right--IO

----->Left Side

----->Left side E-SATA

----->MLK DOCK

----->WLAN/WIMAX

----->WWAN/UWB

----->Flash

----->DOCK

-

---->Non used

----->Right side--IO

----->Express Card

----->Blue Tooth

----->Camera

----->BIO

USB_OC0# <36,37>
USB_OC1# <36>
USB_OC2# <14>
USB_OC3# <14>
USB_OC4# <37>
USB_OC5# <14>
USB_OC6# <14>
SIO_EXT_SMI# <14,40>

USB_OC0#_R <14>
USB_OC1#_R <14>
USB_OC4#_R <14>

USB_OC0#_R
USB_OC1#_R
USB_OC3#
USB_OC4#_R

USB_OC2#
USB_OC5#
USB_OC6#
SIO_EXT_SMI#

1

+3.3V_ALW_PCH

RPH1

RPH1

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

10K_1206_8P4R_5%~D

RPH2

RPH2

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%~D

10K_1206_8P4R_5%~D

+3.3V_RUN

Reserve for ESD in 6/22

PCH_PLTRST#

A A

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

@CE10

@

CE10

1

2

5

PCH_PLTRST#<7,14>

1

2

CH102

CH102

1 2

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D

5

UH3

UH3

P

B

4

O

A

G

TC7SH08FU_SSOP5~D

TC7SH08FU_SSOP5~D

3

4

PCH_PLTRST#_EC <32,34,35,39,40>

Boot BIOS Strap

BBS_BIT1 Boot BIOS Location

SATA_SLPD
(BBS_BIT0)

00 LPC

0 1 Reserved (NAND)

1 0 PCI

*

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

11 SPI

BBS_BIT1

1K_0402_1%~D

1K_0402_1%~D

@RH342

@

12

RH342

2

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

ize Document Number Rev

S

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8)

PCH (4/8)

PCH (4/8)

LA-7901P

LA-7901P

LA-7901P

17 61Saturday, March 03, 2012

17 61Saturday, March 03, 2012

17 61Saturday, March 03, 2012

1

of

1.0

1.0

1.0

5

4

3

2

1

+3.3V_ALW_PCH

4.7K_0402_5%~D

4.7K_0402_5%~D

RH53

RH53

D D

+3.3V_ALW_PCH

C C

B B

A A

1 2

SLP_ME_CSW_DEV#

1K_0402_1%~D

1K_0402_1%~D

12

@RH353

@

RH353

Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)

SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE

ENABLED HIGH (DEFAULT)

DISABLED LOW

SIO_EXT_WAKE#

1 2

12

PCH_GPIO15

PM_LANPHY_ENABLE

12

PCH_GPIO27

12

KB_DET#

12

RH177 10K_0402_5%~DRH177 10K_0402_5%~D

RH354 1K_0402_1%~DRH354 1K_0402_1%~D

RH179 10K_0402_5%~DRH179 10K_0402_5%~D

RH180 10K_0402_5%~DRH180 10K_0402_5%~D

RH170 10K_0402_5%~DRH170 10K_0402_5%~D

SIO_EXT_SCI#_R<14>

SIO_EXT_SCI#<40>

SIO_EXT_WAKE#<39>

vPro only---

PCH_GPIO15<14>

PCH_GPIO16<14>

MEDIA_DET#<43>

PCIE_MCARD1_DET#<34>

SLP_ME_CSW_DEV#<14,39>

USB_MCARD1_DET#<14,34>

PCH_GPIO36<14>

PCH_GPIO37<14>

FFS_INT2<27>

TEMP_ALERT#<14,39>

KB_DET#<41>

Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.

+3.3V_RUN +3.3V_RUN

TPM_ID0

1 2

RH259 0_0402_5%~D@RH259 0_0402_5%~D@

PCH_GPIO1

IO_LOOP#

PCH_GPIO7

SIO_EXT_WAKE#

PM_LANPHY_ENABLE

PCH_GPIO15

PCH_GPIO16

PCH_GPIO17

MEDIA_DET#

PCIE_MCARD1_DET#

PCH_GPIO27

SLP_ME_CSW_DEV#

PCH_GPIO34

USB_MCARD1_DET#

PCH_GPIO36

PCH_GPIO37

TPM_ID0

TPM_ID1

FFS_INT2

TEMP_ALERT#

KB_DET#

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

10K_0402_5%~D

10K_0402_5%~D

1@ RH267

1@

RH267

1 2

10K_0402_5%~D

2@ RH270

10K_0402_5%~D

2@

RH270

1 2

TPM_ID1

UH4F

UH4F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82HM77 QPRG C1_BGA989~D

BD82HM77 QPRG C1_BGA989~D

20K_0402_5%~D

20K_0402_5%~D

3@ RH268

3@

12

RH268

No TPM, No China TPM

2.2K_0402_5%~D

4@ RH271

2.2K_0402_5%~D

4@

12

RH271

China TPM

TBD

TPM

GPIO

GPIO

NCTF

NCTF

A20GATE

PECI

RCIN#

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

PROCPWRGD

CPU/MISC

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

TPM_ID0 TPM_ID1

0 0

0 1

CONTACTLESS_DET#

PCH_GPIO69

PCIE_MCARD3_DET#

USB_MCARD2_DET#

SIO_A20GATE

SIO_RCIN#

H_CPUPWRGD

PCH_THRMTRIP#_R

INIT3_3V#

DF_TVS

NC_1

11

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

PCIE_MCARD3_DET# <34>

USB_MCARD2_DET# <34>

SIO_A20GATE <40>

SIO_RCIN# <40>

H_CPUPWRGD <7>

T106PAD~D @T106PAD~D @

T108PAD~D @T108PAD~D @

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D
RH262 56_0402_5%~DRH262 56_0402_5%~D

CH97

CH97

1

2

Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.

DF_TVS DF_TVS_R

PLACE RH150 CLOSE TO THE BRANCHING POINT
( TO CPU and NVRAM CONNECTOR)

12

12

RH3581K_0402_1%~D RH3581K_0402_1%~D

+1.05V_RUN_VTT

+VCCDFTERM

SIO_A20GATE

SIO_RCIN#

SIO_EXT_SCI#

PCH_GPIO1

PCH_GPIO36

PCH_GPIO37

PCH_GPIO16

TEMP_ALERT#

MEDIA_DET#

PCH_GPIO7

PCH_GPIO17

IO_LOOP#

PCH_GPIO34

CONTACTLESS_DET#

PCH_GPIO36

PCH_GPIO37

PCH_GPIO17

PCH_GPIO16

PCH_GPIO69

DMI & FDI Termination Voltage

DF_TVS

2.2K_0402_5%~D

2.2K_0402_5%~D

12

RH149

RH149

RH149 need to close to CPU

RH158 10K_0402_5%~DRH158 10K_0402_5%~D

RH203 10K_0402_5%~DRH203 10K_0402_5%~D

1 2

RH263 10K_0402_5%~DRH263 10K_0402_5%~D

1 2

RH164 100K_0402_5%~DRH164 100K_0402_5%~D

1 2

RH171 10K_0402_5%~D@RH171 10K_0402_5%~D@

1 2

RH173 1K_0402_1%~D@RH173 1K_0402_1%~D@

RH272 10K_0402_5%~DRH272 10K_0402_5%~D

1 2

RH266 10K_0402_5%~DRH266 10K_0402_5%~D

1 2

RH181 10K_0402_5%~DRH181 10K_0402_5%~D

1 2

RH178 10K_0402_5%~DRH178 10K_0402_5%~D

RH269 8.2K_0402_5%~DRH269 8.2K_0402_5%~D

RH163 10K_0402_5%~DRH163 10K_0402_5%~D

1 2

RH182 10K_0402_5%~DRH182 10K_0402_5%~D

RH256 10K_0402_5%~DRH256 10K_0402_5%~D

1 2

RH174 10K_0402_5%~DRH174 10K_0402_5%~D

1 2

RH172 10K_0402_5%~DRH172 10K_0402_5%~D

1 2

RH273 1K_0402_1%~D@RH273 1K_0402_1%~D@

1 2

RH265 10K_0402_5%~D@RH265 10K_0402_5%~D@

1 2

RH260 1.5K_0402_1%~DRH260 1.5K_0402_1%~D

Set to Vss when LOW

Set to Vcc when HIGH

12

H_SNB_IVB# <7>

RH1500_0402_5%~D @ RH1500_0402_5%~D @

+3.3V_RUN

12

12

12

12

12

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

ize Document Number Rev

S

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8)

PCH (5/8)

PCH (5/8)

LA-7901P

LA-7901P

LA-7901P

18 61Saturday, March 03, 2012

18 61Saturday, March 03, 2012

18 61Saturday, March 03, 2012

1

1.0

1.0

1.0

of

5

D D

C C

B B

+1.05V_RUN

1 2

RH195 0.022_0805_1%@RH195 0.022_0805_1%@

+1.05V_RUN

1

2

+1.05V_RUN

1 2

1UH_LB2012T1R0M_20%~D

1UH_LB2012T1R0M_20%~D

+1.05V_RUN

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CH44

CH44

2

+3.3V_RUN

+VCCAPLL_FDI

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1

CH30

CH30

2

RH247

@RH247

@

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

1

CH45

CH45

2

2

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

CH51

CH51

+1.05V_+1.5V_1.8V_RUN

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH32

CH32

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH46

CH46

2

+1.05V_RUN_VTT

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CH33

CH33

+1.05V_RUN

1

2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH47

CH47

2

+1.05V_RUN

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH31

CH31

2

+VCCAPLLEXP

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@

@

CH40

CH40

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CH48

CH48

+VCCAPLL_FDI

4

UH4G

UH4G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

BD82HM77 QPRG C1_BGA989~D

BD82HM77 QPRG C1_BGA989~D

POWER

POWER

VCC CORE

VCC CORE

VCCIO

VCCIO

FDI

FDI

CRTLVDS

CRTLVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

DMI

DMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI HVCMOS

DFT / SPI HVCMOS

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

+1.05V_RUN_VCCCLKDMI

AB36

AG16

AG17

AJ16

AJ17

V1

3

+VCCADAC

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

1

CH34

CH34

CH35

CH35

2

2

+3.3V_RUN

+1.8V_RUN_LVDS

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

CH103

CH103

1

1

2

2

+3.3V_RUN

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

CH43

CH43

1

2

+1.05V_+1.5V_1.8V_RUN

CH49 1U_0402_6.3V6 K~DCH49 1U_0402_6.3V6K~D

1 2

+VCCDFTERM

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1

CH52

CH52

2

+VCCSPI

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

CH54

CH54

1

2

22U_0603_6.3V6M~D

22U_0603_6.3V6M~D

1UH_GLFR1608T1R0M-LR_20%~D

1UH_GLFR1608T1R0M-LR_20%~D

1

CH36

CH36

2

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D
100NH_HK1608R10J-T_5%_0603~D

100NH_HK1608R10J-T_5%_0603~D

CH105

CH105

CH104

CH104

1

2

+1.05V_RUN_VTT

RH276 0_0805_5%~D@RH276 0_0805_5%~D@

PJP66

@PJP66

@

1 2

PAD-OPEN1x1m

PAD-OPEN1x1m

RH202 0_0603_5%~D@RH202 0_0603_5%~D@

RH204 0_0603_5%~D@RH204 0_0603_5%~D@

+3.3V_RUN

LH1

LH1

12

LH8

LH8

0.1uH inductor, 200mA
CPN : SHI0110BJ0L

12

12

12

+1.8V_RUN

12

+1.05V_RUN_VCCCLKDMI

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

CH50

CH50

2

+3.3V_RUN

+1.8V_RUN

+3.3V_M

+3.3V_RUN

2

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

RH205 0_0603_5%~DRH 205 0_0603_5%~D

@CH106

@

1

CH106

2

1

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC3

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1.05

1.05

1.05

1.05

S0 Iccmax
Current (A)

0.001

5

5

0.001

0.001

0.288

0.063

0.08

0.08

1.7

0.047

1.05VccIO 3.711

VccASW

VccSPI

+1.05V_RUN

12

VccDSW3_3 0.001

1.05

3.3

3.3

1.8 0.002VCCDFTERM

0.903

0.01

3.3VccRTC 6uA

3.3VccSus3_3

3.3VccSusHDA

0.126

0.01

VccVRM 1.8 / 1 .5 0.16 7

1.05VccClkDMI 0.07

1.05VccSSC

VccDIFFCLKN 0.055

1.05

VccALVDS 3.3

0.095

0.001

1.8VccTX_LVDS 0.04

HM76(w/o vpro): depop RH202 and pop RH204
QM77(w/ vpro) : pop RH202 and depop RH204

+1.5V_RUN +1.05V_+1.5V_1.8V_RUN

RH197 0_0603_5%~D@ RH197 0_0603_5%~D@

A A

12

DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

2

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (6/8)

PCH (6/8)

PCH (6/8)

LA-7901P

LA-7901P

LA-7901P

19 61Saturday, March 03, 2012

19 61Saturday, March 03, 2012

19 61Saturday, March 03, 2012

1

1.0

1.0

1.0