Compal LA-7871P QAL51, G580 Schematic
A
1 1
B
C
D
E
Compal Confidential
2 2
QAL51 MB Schematic Document
LA-7871P
Intel Ivy Bridge / Panther Point
Discrete : N13P-GS / N13P-GT
3 3
Rev: 1.0
2012.02.29
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/12/01 2012/12/31
2009/12/01 2012/12/31
2009/12/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Cover Sheet
Cover Sheet
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
E
1.0
1.0
1 60Wednesday, March 07, 2012
1 60Wednesday, March 07, 2012
1 60Wednesday, March 07, 2012
1.0
Compal Confidential
Model Name : QAL51
File Name : LA-7871P
A
B
C
D
E
PEG(DIS)
1 1
N13P GS/GT
64*16 1G
128*16 2GB
2 2
PCIeMini Card
WLAN & BT 2.0
3 3
PCI-Express (PCIE 2.5GT/s)
port 2 port 1
USB port 13
PCIe port 2
page 32
Express Card
page 20~28
PCIe port 3
USB port 4
Page 32
PCI-E 2.0x16 5GT/s PER LANE100MHz
CRT
LVDS Conn.
HDMI Conn.
100MHz
RTL8105E 10/100M
RTL8111E 1G
PCIe port 1
page 33
RJ45
page 33
PCIe 1x
1.5V 2.5GHz(250MB/s)
page 30
page 29
page 31
Mobile Ivy Bridge
CPU Dual / Quad Core
Socket-rPGA989
37.5mm*37.5mm
page 4,5,6,7,8,9
Intel Panther Point
PCBGA989
25mm*25mm
page 12,13,14,15,
16,17,18,19
ENE KB930
(Co-Lay KB9012)
Touch Pad
page 35
DMI X4
LPC BUS
33MHz
page 38
Int.KBD
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 1333/1600
USB
5V 480Mbps
SATA port 0
5V (6Gb/s)
SATA port 2
5V 1.5GHz(150MB/s)
HD Audio
page 42
USB/B Right
USB port 8,9
3.3V 24.576MHz/48Mhz
Int. Camera RTS5129 3IN1
page 40
SATA HDD
SATA ODD
BIOS ROM
USB port 10
page 36
page 36
page 39
204pin DDRIII-SO-DIMM X2
page 10,11
Smart Card
USB port 5
page 29
BANK 0, 1, 2, 3
USB port 11
page 35
HDA Codec
ALC259
Int.
MIC CONN
page 34
MIC CONN
page 40
page 32
page 34
HP CONN
page 40
SPK CONN
page 34
EC ROM
Function /B
page 40
4 4
USB&Audio/B
page 40
Power/B
page 41
Touch Pad/B
page 35
Fan Control
page 41
RTC CKT.
page 12
DC/DC Interface CKT.
page 44
Power Circuit DC/DC
page 45~56
A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
page 39
C
Compal Secret Data
Compal Secret Data
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Chief River-Block Diagram
Chief River-Block Diagram
Chief River-Block Diagram
LA-7871P
E
CPU XDP
page 5
PCH XDP
page 12
2 60Wednesday, March 07, 2012
2 60Wednesday, March 07, 2012
2 60Wednesday, March 07, 2012
1.0
1.0
1.0
Board ID Table for AD channel
Vcc 3.3V +/- 5%
Board ID
0
1
2
3
4
5
6
7
100K +/- 5%Ra
Rb V min
0 0 V
8.2K +/- 5% 0.168V 0.250 V 0.362 V
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
AD_BID
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
V typ
AD_BID
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
V
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
max
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
QAL30
QAL31 / LP
QAL31 / GT
QAL50
QAL51 / GS
QAL51 / GT
A
USB PORT#
0
1
2
3
4
USB2/3 (Left Hand side front)
USB2/3 (Left Hand side back)
None
None
USB2 (Right Hand side front)
DESTINATION
5
6
SMBUS Control Table
X
X
V
X
VGA Int.
Thermal
X X
V
X
V
JXDP1
JXDP2
X
V
X
CLKOUT
PCI0
PCI1
PCI2
PCI3
PCI4
DESTINATION
PCH_LOOPBACK
EC
TPM
None
None
SOURCE
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
PCH_SMBCLK
PCH_SMBDATA PCH
PCH_SMLCLK
PCH_SMLDATA
1 1
KB930
KB9012
KB930
KB9012
PCH
MIINI1 BATT SODIMM
0001 011x b 1001 000x b 1001 010x b 0x9A
X
V
X
V
X
X
X
SODIMM
X
XX
V
X
PCH
7
8
9
10
11
12
13
Smart CARD
None
None
EXPRESS CARD
USB2 (Right Hand side back)
CAMERA
Card Reader
Finger Print
BT Comb
OPTIMUS: XDP@/D@
DESTINATION
HDD
None
ODD
None
None
PCI EXPRESS
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
DESTINATION
LAN
WLAN
Express Card
None
CLK
CLKOUT_PCIE0
CLKOUT_PCIE1
CLKOUT_PCIE2
CLKOUT_PCIE3
CLKOUT_PCIE4
DESTINATIONDIFFERENTIAL
LAN
WLAN
Express Card
None
None
FLEX CLOCKS DESTINATION
CLKOUTFLEX0
CLKOUTFLEX1
CLKOUTFLEX2
CLKOUTFLEX3
None
None
None
None None
SATA
SATA0
SATA1
SATA2
SATA3
SATA4
CLKOUT_PCIE5
None
NoneCLKOUT_PCIE6
CLKOUT_PCIE7 None
CLKOUT_PEG_A
VGA
CLKOUT_PEG_B None
Symbol Note :
: means Digital Ground
: means Analog Ground
SATA5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
None
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Lane 6
Lane 7
Lane 8
None
None
None
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
3 60Wednesday, March 07, 2012
3 60Wednesday, March 07, 2012
3 60Wednesday, March 07, 2012
1.0
1.0
1.0
5
JCPU1A
D D
DMI_CRX_PTX_N014
DMI_CRX_PTX_N114
DMI_CRX_PTX_N214
DMI_CRX_PTX_N314
DMI_CRX_PTX_P014
DMI_CRX_PTX_P114
DMI_CRX_PTX_P214
DMI_CRX_PTX_P314
14
DMI_CTX_PRX_N0
14
DMI_CTX_PRX_N1
14
DMI_CTX_PRX_N2
14
DMI_CTX_PRX_N3
14
DMI_CTX_PRX_P0
14
DMI_CTX_PRX_P1
14
DMI_CTX_PRX_P2
14
DMI_CTX_PRX_P3
14
FDI_CTX_PRX_N0
14
FDI_CTX_PRX_N1
14
FDI_CTX_PRX_N2
14
FDI_CTX_PRX_N3
14
FDI_CTX_PRX_N4
14
FDI_CTX_PRX_N5
14
C C
+V1.05S_VCCP
+V1.05S_VCCP
B B
FDI_CTX_PRX_N6
14
FDI_CTX_PRX_N7
14
FDI_CTX_PRX_P0
14
FDI_CTX_PRX_P1
14
FDI_CTX_PRX_P2
14
FDI_CTX_PRX_P3
14
FDI_CTX_PRX_P4
14
FDI_CTX_PRX_P5
14
FDI_CTX_PRX_P6
14
FDI_CTX_PRX_P7
FDI_FSYNC014
FDI_FSYNC114
FDI_INT14
FDI_LSYNC014
FDI_LSYNC114
RC2 24.9_0402_1%RC2 24.9_0402_1%
10K_0402_5%
10K_0402_5%
RC8
@RC8
@
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
EDP_COMP
EDP_HPD#
JCPU1A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD#
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
4
RC1
RC1
24.9_0402_1%
24.9_0402_1%
PEG_COMP
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
J21
H22
PCIE_GTX_C_CRX_N15
K33
PCIE_GTX_C_CRX_N14
M35
PCIE_GTX_C_CRX_N13
L34
PCIE_GTX_C_CRX_N12
J35
PCIE_GTX_C_CRX_N11
J32
PCIE_GTX_C_CRX_N10
H34
PCIE_GTX_C_CRX_N9
H31
PCIE_GTX_C_CRX_N8
G33
PCIE_GTX_C_CRX_N7
G30
PCIE_GTX_C_CRX_N6
F35
PCIE_GTX_C_CRX_N5
E34
PCIE_GTX_C_CRX_N4
E32
PCIE_GTX_C_CRX_N3
D33
PCIE_GTX_C_CRX_N2
D31
PCIE_GTX_C_CRX_N1
B33
PCIE_GTX_C_CRX_N0
C32
PCIE_GTX_C_CRX_P15
J33
PCIE_GTX_C_CRX_P14
L35
PCIE_GTX_C_CRX_P13
K34
PCIE_GTX_C_CRX_P12
H35
PCIE_GTX_C_CRX_P11
H32
PCIE_GTX_C_CRX_P10
G34
PCIE_GTX_C_CRX_P9
G31
PCIE_GTX_C_CRX_P8
F33
PCIE_GTX_C_CRX_P7
F30
PCIE_GTX_C_CRX_P6
E35
PCIE_GTX_C_CRX_P5
E33
PCIE_GTX_C_CRX_P4
F32
PCIE_GTX_C_CRX_P3
D34
PCIE_GTX_C_CRX_P2
E31
PCIE_GTX_C_CRX_P1
C33
PCIE_GTX_C_CRX_P0
B32
PCIE_CTX_GRX_N15
M29
PCIE_CTX_GRX_N14
M32
PCIE_CTX_GRX_N13
M31
PCIE_CTX_GRX_N12
L32
PCIE_CTX_GRX_N11
L29
PCIE_CTX_GRX_N10
K31
PCIE_CTX_GRX_N9
K28
PCIE_CTX_GRX_N8
J30
PCIE_CTX_GRX_N7
J28
PCIE_CTX_GRX_N6
H29
PCIE_CTX_GRX_N5
G27
PCIE_CTX_GRX_N4
E29
PCIE_CTX_GRX_N3
F27
PCIE_CTX_GRX_N2
D28
PCIE_CTX_GRX_N1
F26
PCIE_CTX_GRX_N0
E25
PCIE_CTX_GRX_P15
M28
PCIE_CTX_GRX_P14
M33
PCIE_CTX_GRX_P13
M30
PCIE_CTX_GRX_P12
L31
PCIE_CTX_GRX_P11
L28
PCIE_CTX_GRX_P10
K30
PCIE_CTX_GRX_P9
K27
PCIE_CTX_GRX_P8
J29
PCIE_CTX_GRX_P7
J27
PCIE_CTX_GRX_P6
H28
PCIE_CTX_GRX_P5
G28
PCIE_CTX_GRX_P4
E28
PCIE_CTX_GRX_P3
F28
PCIE_CTX_GRX_P2
D27
PCIE_CTX_GRX_P1
E26
PCIE_CTX_GRX_P0
D25
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI
DMI
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
Intel(R) FDI
Intel(R) FDI
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
eDP
eDP
3
+V1.05S_VCCP
PEG_ICOMPI and RCOMPO signals should be short ed and routed
with - max leng th = 500 mils - typical impeda nce = 43 mohms
PEG_ICOMPO sign als should be r outed with - ma x length = 500 mils
- typical imped ance = 14.5 moh ms
PCIE_GTX_C_CRX_N[0..15]
PCIE_GTX_C_CRX_P[0..15]
20
20
PAY ATTENTION ON PCIE SWAP WHEN REVIEW
CV1 0.22U_0402_10V6KDIS@CV1 0.22U_0402_10V6KDIS@
CV2 0.22U_0402_10V6KDIS@CV2 0.22U_0402_10V6KDIS@
CV3 0.22U_0402_10V6KDIS@CV3 0.22U_0402_10V6KDIS@
CV4 0.22U_0402_10V6KDIS@CV4 0.22U_0402_10V6KDIS@
CV5 0.22U_0402_10V6KDIS@CV5 0.22U_0402_10V6KDIS@
CV6 0.22U_0402_10V6KDIS@CV6 0.22U_0402_10V6KDIS@
CV7 0.22U_0402_10V6KDIS@CV7 0.22U_0402_10V6KDIS@
CV8 0.22U_0402_10V6K
CV8 0.22U_0402_10V6K
DIS@
DIS@
CV9 0.22U_0402_10V6K
CV9 0.22U_0402_10V6K
DIS@
DIS@
CV10 0.22U_0402_10V6K
CV10 0.22U_0402_10V6K
DIS@
DIS@
CV11 0.22U_0402_10V6K
CV11 0.22U_0402_10V6K
DIS@
DIS@
CV12 0.22U_0402_10V6K
CV12 0.22U_0402_10V6K
DIS@
DIS@
CV13 0.22U_0402_10V6K
CV13 0.22U_0402_10V6K
DIS@
DIS@
CV14 0.22U_0402_10V6K
CV14 0.22U_0402_10V6K
DIS@
DIS@
CV15 0.22U_0402_10V6K
CV15 0.22U_0402_10V6K
DIS@
DIS@
CV16 0.22U_0402_10V6K
CV16 0.22U_0402_10V6K
DIS@
DIS@
CV17 0.22U_0402_10V6KDIS@CV17 0.22U_0402_10V6KDIS@
CV18 0.22U_0402_10V6KDIS@CV18 0.22U_0402_10V6KDIS@
CV19 0.22U_0402_10V6KDIS@CV19 0.22U_0402_10V6KDIS@
CV20 0.22U_0402_10V6KDIS@CV20 0.22U_0402_10V6KDIS@
CV21 0.22U_0402_10V6KDIS@CV21 0.22U_0402_10V6KDIS@
CV22 0.22U_0402_10V6KDIS@CV22 0.22U_0402_10V6KDIS@
CV23 0.22U_0402_10V6KDIS@CV23 0.22U_0402_10V6KDIS@
CV24 0.22U_0402_10V6KDIS@CV24 0.22U_0402_10V6KDIS@
CV25 0.22U_0402_10V6KDIS@CV25 0.22U_0402_10V6KDIS@
CV26 0.22U_0402_10V6KDIS@CV26 0.22U_0402_10V6KDIS@
CV27 0.22U_0402_10V6KDIS@CV27 0.22U_0402_10V6KDIS@
CV28 0.22U_0402_10V6KDIS@CV28 0.22U_0402_10V6KDIS@
CV29 0.22U_0402_10V6KDIS@CV29 0.22U_0402_10V6KDIS@
CV30 0.22U_0402_10V6KDIS@CV30 0.22U_0402_10V6KDIS@
CV31 0.22U_0402_10V6KDIS@CV31 0.22U_0402_10V6KDIS@
CV32 0.22U_0402_10V6KDIS@CV32 0.22U_0402_10V6KDIS@
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P0
2
PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_P[0..15]
20
20
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
K35
K32
K29
K26
H33
H30
H27
H24
H21
H18
H15
H13
H10
G35
G32
G29
G26
G23
G20
G17
G11
1
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
VSS199
VSS200
VSS201
VSS202
J34
VSS203
J31
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
Close to CPU
A A
5
RC3
DIS@RC3
DIS@
1K_0402_5%
1K_0402_5%
RC4
DIS@RC4
DIS@
1K_0402_5%
1K_0402_5%
RC5
DIS@RC5
DIS@
1K_0402_5%
1K_0402_5%
RC6
DIS@RC6
DIS@
1K_0402_5%
1K_0402_5%
RC7
DIS@RC7
DIS@
1K_0402_5%
1K_0402_5%
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
FDI_INT
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(1/6) DMI,FDI,PEG
PROCESSOR(1/6) DMI,FDI,PEG
PROCESSOR(1/6) DMI,FDI,PEG
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
1
4 60Wednesday, March 07, 2012
4 60Wednesday, March 07, 2012
4 60Wednesday, March 07, 2012
1.0
1.0
1.0
5
4
3
2
1
RC13
1
2
SUSP44
+3VS
5
P
A2Y
G
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
3
13
13
+3V_PCH
B
A
@RC16
@
+3VS
14
SYSTEM_PWROK
A28
A27
A16
A15
R8
AK1
A5
A4
AP29
AP27
AR26
AR27
AP30
AR28
AP26
XDP_DBRESET#
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
+3V_PCH
CLK_CPU_DMI_R
CLK_CPU_DMI#_R
CLK_CPU_DPLL_R
CLK_CPU_DPLL#_R
H_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
XDP_PRDY#_R
XDP_PREQ#_R
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
XDP_TDI_R
XDP_TDO_R
RC11
RC11
200_0402_1%
200_0402_1%
RC39 0_0402_5%RC39 0_0402_5%
RC36 0_0402_5%RC36 0_0402_5%
RC37 1K_0402_5%RC37 1K_0402_5%
RC41 1K_0402_5%RC41 1K_0402_5%
H_DRAMRST#
D D
PM_DRAM_PWR GD14
C C
JCPU1B
JCPU1B
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWR OK
AR33
RESET#
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
BCLK
BCLK#
CLOCKS
CLOCKS
DDR3
DDR3
JTAG & BPM
JTAG & BPM
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
MISC
MISC
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
TDI
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
RC44
RC44
62_0402_5%
62_0402_5%
CC62
@CC62
@
220P_0402_25V8J
220P_0402_25V8J
@CC63
@
+V1.05S_VCCP
RC4510K_0402_5% RC4510K_0402_5%
CC63
16,38
16
14
16
H_PECI
H_PROCHOT#38,46
H_THERMTRIP#
H_PM_SYNC
H_CPUPWRGD16
VDDPWRGOOD
H_SNB_IVB#
RC42
RC42
56_0402_5%
56_0402_5%
RC50
RC50
0_0402_5%
0_0402_5%
RC54
RC54
0_0402_5%
0_0402_5%
RC58
RC58
130_0402_1%
130_0402_1%
H_CATERR#
H_PROCHOT#_R
H_THERMTRIP#
H_PM_SYNC_R
H_CPUPWRGD_R
VDDPWRGOOD_R
BUF_CPU_RST#
Processor Pullups
H_PROCHOT#
H_CPUPWRGD_R
220P_0402_25V8J
220P_0402_25V8J
B B
A A
RC12
RC12
@RC13
@
10K_0402_5%
10K_0402_5%
0_0402_5%
0_0402_5%
RUN_ON_CPU1.5VS3#44,9
+V1.05S_VCCP
D_PWG
CLK_CPU_DMI
CLK_CPU_DMI#
RC21 0_0402_5%RC 21 0_0402_5%
PLT_RST#15,20,32,33,37,38
6
DDR3 Compensation Signals
SM_RCOMP0 XDP_TDO_R
SM_RCOMP1
SM_RCOMP2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CC33
CC33
5
UC1
UC1
4
Y
VCC
G
MC74VHC1G09DFT2G_SC70-5
MC74VHC1G09DFT2G_SC70-5
3
RC17
@ RC17
@
0_0402_5%
0_0402_5%
RC16
0_0402_5%
0_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CC36
CC36
1
UC2
UC2
BUFO_CPU_RST# BUF_CPU_RST#
4
NC
2
G
G
+V1.05S_VCCP
+1.5V_CPU_VDDQ
@
@
RC25
RC25
39_0402_1%
39_0402_1%
@
@
QC2
QC2
13
D
D
S
S
RC38
RC38
75_0402_5%
75_0402_5%
RC35
RC35
43_0402_1%
43_0402_1%
VDDPWRGOOD
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
PU/PD for JTAG signals
XDP_TMS_R
XDP_TDI_R
RC56140_0402_1% RC56140_0402_1%
RC5925.5_0402_1% RC5925.5_0402_1%
RC61200_0402_1% RC61200_0402_1%
XDP_PREQ#_R
XDP_TCK_R
XDP_TRST#_R
RC14
RC14
200_0402_1%
200_0402_1%
@
@
RC40
RC40
0_0402_5%
0_0402_5%
+V1.05S_VCCP
RC4651_0402_5% RC4651_0402_5%
RC4751_0402_5% RC4751_0402_5%
RC4851_0402_5% @ RC4851_0402_5% @
RC4951_0402_5% RC4951_0402_5%
RC5351_0402_5% RC5351_0402_5%
RC5551_0402_5% RC5551_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(2/6) PM,XDP,CLK
PROCESSOR(2/6) PM,XDP,CLK
PROCESSOR(2/6) PM,XDP,CLK
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
1
of
5 60Wednesday, March 07, 2012
5 60Wednesday, March 07, 2012
5 60Wednesday, March 07, 2012
1.0
1.0
1.0
5
JCPU1C
JCPU1C
10
DDR_A_D[0..63]
D D
C C
10
10
10
10
10
10
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
C5
SA_DQ[0]
D5
SA_DQ[1]
D3
SA_DQ[2]
D2
SA_DQ[3]
D6
SA_DQ[4]
C6
SA_DQ[5]
C2
SA_DQ[6]
C3
SA_DQ[7]
F10
SA_DQ[8]
F8
SA_DQ[9]
G10
SA_DQ[10]
G9
SA_DQ[11]
F9
SA_DQ[12]
F7
SA_DQ[13]
G8
SA_DQ[14]
G7
SA_DQ[15]
K4
SA_DQ[16]
K5
SA_DQ[17]
K1
SA_DQ[18]
J1
SA_DQ[19]
J5
SA_DQ[20]
J4
SA_DQ[21]
J2
SA_DQ[22]
K2
SA_DQ[23]
M8
SA_DQ[24]
N10
SA_DQ[25]
N8
SA_DQ[26]
N7
SA_DQ[27]
M10
SA_DQ[28]
M9
SA_DQ[29]
N9
SA_DQ[30]
M7
SA_DQ[31]
AG6
SA_DQ[32]
AG5
SA_DQ[33]
AK6
SA_DQ[34]
AK5
SA_DQ[35]
AH5
SA_DQ[36]
AH6
SA_DQ[37]
AJ5
SA_DQ[38]
AJ6
SA_DQ[39]
AJ8
SA_DQ[40]
AK8
SA_DQ[41]
AJ9
SA_DQ[42]
AK9
SA_DQ[43]
AH8
SA_DQ[44]
AH9
SA_DQ[45]
AL9
SA_DQ[46]
AL8
SA_DQ[47]
AP11
SA_DQ[48]
AN11
SA_DQ[49]
AL12
SA_DQ[50]
AM12
SA_DQ[51]
AM11
SA_DQ[52]
AL11
SA_DQ[53]
AP12
SA_DQ[54]
AN12
SA_DQ[55]
AJ14
SA_DQ[56]
AH14
SA_DQ[57]
AL15
SA_DQ[58]
AK15
SA_DQ[59]
AL14
SA_DQ[60]
AK14
SA_DQ[61]
AJ15
SA_DQ[62]
AH15
SA_DQ[63]
AE10
SA_BS[0]
AF10
SA_BS[1]
V6
SA_BS[2]
AE8
SA_CAS#
AD9
SA_RAS#
AF9
SA_WE#
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
4
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE0
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE1
DDRA_SCS0#
DDRA_SCS1#
DDRA_ODT0
DDRA_ODT1
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
3
10
10
10
10
10
10
10
10
10
10
10
10
10
11
DDR_B_D[0..63]
11
DDR_B_BS0
11
DDR_B_BS1
11
DDR_B_BS2
11
DDR_B_CAS#
11
DDR_B_RAS#
11
DDR_B_WE#
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
2
JCPU1D
JCPU1D
C9
SB_DQ[0]
A7
SB_DQ[1]
D10
SB_DQ[2]
C8
SB_DQ[3]
A9
SB_DQ[4]
A8
SB_DQ[5]
D9
SB_DQ[6]
D8
SB_DQ[7]
G4
SB_DQ[8]
F4
SB_DQ[9]
F1
SB_DQ[10]
G1
SB_DQ[11]
G5
SB_DQ[12]
F5
SB_DQ[13]
F2
SB_DQ[14]
G2
SB_DQ[15]
J7
SB_DQ[16]
J8
SB_DQ[17]
K10
SB_DQ[18]
K9
SB_DQ[19]
J9
SB_DQ[20]
J10
SB_DQ[21]
K8
SB_DQ[22]
K7
SB_DQ[23]
M5
SB_DQ[24]
N4
SB_DQ[25]
N2
SB_DQ[26]
N1
SB_DQ[27]
M4
SB_DQ[28]
N5
SB_DQ[29]
M2
SB_DQ[30]
M1
SB_DQ[31]
AM5
SB_DQ[32]
AM6
SB_DQ[33]
AR3
SB_DQ[34]
AP3
SB_DQ[35]
AN3
SB_DQ[36]
AN2
SB_DQ[37]
AN1
SB_DQ[38]
AP2
SB_DQ[39]
AP5
SB_DQ[40]
AN9
SB_DQ[41]
AT5
SB_DQ[42]
AT6
SB_DQ[43]
AP6
SB_DQ[44]
AN8
SB_DQ[45]
AR6
SB_DQ[46]
AR5
SB_DQ[47]
AR9
SB_DQ[48]
AJ11
SB_DQ[49]
AT8
SB_DQ[50]
AT9
SB_DQ[51]
AH11
SB_DQ[52]
AR8
SB_DQ[53]
AJ12
SB_DQ[54]
AH12
SB_DQ[55]
AT11
SB_DQ[56]
AN14
SB_DQ[57]
AR14
SB_DQ[58]
AT14
SB_DQ[59]
AT12
SB_DQ[60]
AN15
SB_DQ[61]
AR15
SB_DQ[62]
AT15
SB_DQ[63]
AA9
SB_BS[0]
AA7
SB_BS[1]
R6
SB_BS[2]
AA10
SB_CAS#
AB8
SB_RAS#
AB9
SB_WE#
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
1
DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE1
DDRB_SCS0#
DDRB_SCS1#
DDRB_ODT0
DDRB_ODT1
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
11
11
11
11
11
11
11
11
11
11
11
11
11
+1.5V
DDR3_DRAMRST#_R
@
@
RC75 0_0402_5%
RC75 0_0402_5%
Q3
Q3
D
S
D
A A
H_DRAMRST#
4.99K_0402_1%
4.99K_0402_1%
5
RC78
RC78
S
G
G
2
13
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
DRAMRST_CNTRL
CC37
CC37
0.047U_0402_16V4Z
0.047U_0402_16V4Z
RC76
RC76
1K_0402_5%
1K_0402_5%
RC77 1K_0402_5%RC77 1K_0402_5%
RC73 0_0402_5%RC73 0_0402_5%
4
@
@
RC9
RC9
1M_0402_5%
1M_0402_5%
SM_DRAMRST#
DRAMRST_CNTRL_PCH13
10,11H_DRAMRST#5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(3/6) DDRIII
PROCESSOR(3/6) DDRIII
PROCESSOR(3/6) DDRIII
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
1
1.0
1.0
6 60Wednesday, March 07, 2012
6 60Wednesday, March 07, 2012
6 60Wednesday, March 07, 2012
1.0
5
4
3
2
1
CFG Straps for Processor
D D
JCPU1E
JCPU1E
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
KEY
CLK_RES_ITP 13
CLK_RES_ITP# 13
PEG Static Lane Reversal - CFG2 is for the 16x
Display Port Presence Strap
PCIE Port Bifurcation Straps
CFG[6:5]
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
+GFX_CORE
C C
+VCC_CORE
INTEL recommand
to add RC115, RC116, RC117, RC118
Please place as close as JCPU1
B B
RC115 49.9_0402_1%RC115 49.9_0402_1%
RC116 49.9_0402_1%RC116 49.9_0402_1%
RC105 100_0402_1%@RC105 100_0402_1%@
RC117 49.9_0402_1%RC117 49.9_0402_1%
RC106 100_0402_1%@RC106 100_0402_1%@
RC118 49.9_0402_1%RC118 49.9_0402_1%
VCC_AXG_VAL_SENSE
VSS_AXG_VAL_SENSEVSS_AXG_VAL_SENSEVSS_AXG_VAL_SENSEVSS_AXG_VAL_SENSEVSS_AXG_VAL_SENSEVSS_AXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
VCC_DIE_SENSE
VSS_DIE_SENSE
CFG
CFG
RESERVED
RESERVED
RSVD_NCTF10
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
CFG2
RC79
RC79
1K_0402_1%
1K_0402_1%
1:(Default) Nor mal Operation; Lane #
CFG2
definition matc hes socket pin map definition
0:Lane Reversed
CFG4
RC82
@RC82
@
1K_0402_1%
1K_0402_1%
1 : Disabled; N o Physical Disp lay Port
CFG4
attached to Emb edded Display P ort
0 : Enabled; An external Displ ay Port device is
connected to th e Embedded Disp lay Port
CFG6
CFG5
RC83
@RC83
@
1K_0402_1%
1K_0402_1%
RC84
@RC84
@
1K_0402_1%
1K_0402_1%
11: (Default) x 16 - Device 1 f unctions 1 and 2 disabled
10: x8, x8 - De vice 1 function 1 enabled ; fu nction 2
disabled
01: Reserved - (Device 1 funct ion 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functi ons 1 and 2 ena bled
CFG7
RC85
@RC85
@
1K_0402_1%
1K_0402_1%
PEG DEFER TRAINING
1: (Default) PE G Train immedia tely
CFG7
following RESET B de assertion
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0: PEG Wait for BIOS for train ing
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(4/6) RSVD,CFG
PROCESSOR(4/6) RSVD,CFG
PROCESSOR(4/6) RSVD,CFG
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
7 60Wednesday, March 07, 2012
7 60Wednesday, March 07, 2012
7 60Wednesday, March 07, 2012
1
1.0
1.0
1.0
5
JCPU1H
JCPU1H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
D D
C C
B B
A A
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
TYCO_201362 0-2_IVY BRIDGE
TYCO_201362 0-2_IVY BRIDGE
CONN@
CONN@
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
4
JCPU1F
JCPU1F
+VCC_CORE
97A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
TYCO_201362 0-2_IVY BRIDGE
TYCO_201362 0-2_IVY BRIDGE
CONN@
CONN@
3
POWER
POWER
CORE SUPPLY
CORE SUPPLY
PEG AND DDR
PEG AND DDR
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
+V1.05S_VCCP
8.5A
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
H_CPU_SVIDALRT#
AJ29
H_CPU_SVIDCLK
AJ30
H_CPU_SVIDDAT
AJ28
Place the PU
resistors close to CPU
VCCSENSE_R
AJ35
VSSSENSE_R
AJ34
B10
A10
+V1.05S_VCCP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CC49
CC49
RC90
RC90
43_0402_1 %
43_0402_1 %
+V1.05S_VCCP
RC91
RC91
130_0402_ 1%
130_0402_ 1%
H_CPU_SVIDDAT
RC94 0_0402 _5%RC94 0_0402 _5%
RC95 0_0402 _5%RC95 0_0402 _5%
12
RC98
RC98
10_0402_1 %
10_0402_1 %
2
H_CPU_SVIDCLK
Place the PU
resistors close to CPU
RC89
RC89
75_0402_5 %
75_0402_5 %
VCCIO_SENSE
RC88 0_0402_5 %RC88 0_040 2_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CC50
CC50
RC92 0_0402_5%RC92 0_0402 _5%
50
VCCIO_SENSE
+VCC_CORE
RC93
RC93
100_0402_ 1%
100_0402_ 1%
RC97
RC97
100_0402_ 1%
100_0402_ 1%
Close to CPU
R75
R75
1 2
10_0402_5 %
10_0402_5 %
VR_SVID_ALRT#
VCCSENSE
VSSSENSE
VR_SVID_CLK
VR_SVID_DAT
53
53
+V1.05S_VCCP
1
53
53
53
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.
5
4
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.
3
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(5/6) PWR,BYPASS
PROCESSOR(5/6) PWR,BYPASS
PROCESSOR(5/6) PWR,BYPASS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
8 60Wednesday, March 07, 2 012
8 60Wednesday, March 07, 2 012
8 60Wednesday, March 07, 2 012
1
1.0
1.0
1.0
5
D D
RC103
@RC103
SUSP#32,38,44,49,50,51,56
+GFX_CORE
C C
B B
@
0_0402_5%
0_0402_5%
RC104
RC104
0_0402_5%
0_0402_5%
33A
AM24
AM23
AM21
AM20
AM18
AM17
AK24
AK23
AK21
AK20
AK18
AK17
AH24
AH23
AH21
AH20
AH18
AH17
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AL24
AL23
AL21
AL20
AL18
AL17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
+1.8VS +1.8VS_VCCPLL
RC119
RC119
0_0805_5%
0_0805_5%
A A
10U_0805_6.3V6M
10U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CC58
CC58
CC59
CC59
2
2
5
1.5A
330U_X_2VM_R6M
330U_X_2VM_R6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC61
CC61
CC60
CC60
+
+
2
@
@
4
61
2
JCPU1G
JCPU1G
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
4
RC101
RC101
100K_0402_5%
100K_0402_5%
RUN_ON_CPU1.5VS3#
QC5A
QC5A
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
POWER
POWER
SENSE
SENSE
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
VAXG_SENSE
VSSAXG_SENSE
LINES
LINES
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
3
+1.5V_CPU_VDDQ
QC4
QC4
+1.5V +1.5V_CPU_VDDQ
MDU1512RH_PPAK56-8-5
+VSBP+3VALW
RC99
RC99
100K_0402_5%
100K_0402_5%
RUN_ON_CPU1.5VS3
3
QC5B
QC5B
5
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
4
RUN_ON_CPU1.5VS3#
AK35
AK34
+V_SM_VREF_CNT
AL1
B4
D1
+1.5V_CPU_VDDQ
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
IVY Bridge drives VCCIO_SEL low
VCCP_PWRCTRL:0
Sandy Bridge is NC for A19
VCCP_PWRCTRL:1
MDU1512RH_PPAK56-8-5
5
44,5CPU1.5V_S3_GATE38
Close to CPU
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_SENSE
VSS_AXG_SENSE
10A
10U_0805_10VM
10U_0805_10VM
CC51
CC51
H_VCCSA_VID0
H_VCCSA_VID1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
4
RC102
RC102
330K_0402_1%
330K_0402_1%
R78
R78
0_0402_5%
0_0402_5%
DIS@
DIS@
R78 100_0402_1%
R78 100_0402_1%
R79 100_0402_1%
R79 100_0402_1%
53
53
10U_0805_10VM
10U_0805_10VM
10U_0805_10VM
10U_0805_10VM
CC52
CC52
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
CC40
CC40
CC41
CC41
52
52
RC112
@RC112
@
10K_0402_5%
10K_0402_5%
RC1140_0402_5% @RC1140_0402_5% @
1
2
3
CC38
CC38
RC100
RC100
20K_0402_5%
10U_0805_10V4Z
10U_0805_10V4Z
R79
R79
0_0402_5%
0_0402_5%
DIS@
DIS@
+GFX_CORE
QC6
QC6
S
S
G
G
10U_0805_10VM
10U_0805_10VM
CC55
CC55
10U_0603_6.3V6M
10U_0603_6.3V6M
1
@
@
+
+
CC43
CC43
2
@
@
+VCCSA_SENSE
20K_0402_5%
RC1070_0402_5% RC1070_0402_5%
@
@
D
D
13
PMV45EN_SOT23-3
PMV45EN_SOT23-3
2
10U_0805_10VM
10U_0805_10VM
1
CC56
CC56
+
+
CC57
CC57
330U_X_2VM_R6M
330U_X_2VM_R6M
2
CC44
CC44
330U_X_2VM_R6M
330U_X_2VM_R6M
52
Compal Secret Data
Compal Secret Data
Compal Secret Data
+V_SM_VREF
@JP0901
@
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
+VCCSA
1 2
RH235 100_0402_5%RH235 100_0402_5%
Deciphered Date
Deciphered Date
Deciphered Date
0.1U_0603_50V7K
0.1U_0603_50V7K
CC39
CC39
UMA@
UMA@
UMA@
UMA@
RUN_ON_CPU1.5VS3
10U_0805_10VM
10U_0805_10VM
CC53
CC53
CC54
CC54
10U_0805_6.3V6M
10U_0805_6.3V6M
CC42
CC42
RC111
@ RC111
@
0_0402_5%
0_0402_5%
+3VS
VCCP_PWRCTRLH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SELH_VCCP_SEL
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
JP0901
+VCCSA_SENSE
2
+1.5V_CPU_VDDQ
+1.5V
2
RC108
RC108
1K_0402_1%
1K_0402_1%
RC110
RC110
1K_0402_1%
1K_0402_1%
+V_SM_VREF should
have 10 mil trace width
+1.5V_CPU_VDDQ +1.5V
CC45 0.1U_0402_10V7KCC45 0.1U_0402_10V7K
CC46 0.1U_0402_10V7KCC46 0.1U_0402_10V7K
CC47 0.1U_0402_10V7KCC47 0.1U_0402_10V7K
CC48 0.1U_0402_10V7KCC48 0.1U_0402_10V7K
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(6/6) PWR,VSS
PROCESSOR(6/6) PWR,VSS
PROCESSOR(6/6) PWR,VSS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1.0
1.0
9 60Wednesday, March 07, 2012
9 60Wednesday, March 07, 2012
9 60Wednesday, March 07, 2012
1
1.0
5
+1.5V
RD1
RD1
1K_0402_1%
1K_0402_1%
+V_DDR_REFA
RD2
D D
C C
B B
A A
RD2
1K_0402_1%
1K_0402_1%
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0603_6.3V6K
CD50
CD50
DDRA_CKE06
DDR_A_BS26
DDRA_CLK06
DDRA_CLK0#6
DDR_A_BS06
DDR_A_WE#6
DDR_A_CAS#6
DDRA_SCS1#6
+3VS
5
2.2U_0603_6.3V6K
CD1
CD1
CD2
CD2
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
CD25
CD25
+1.5V +1.5V
DDR3 SO-DIMM A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDRA_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDRA_CLK0
DDRA_CLK0#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS# DDRA_ODT0
DDR_A_MA13
DDRA_SCS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
CD26
CD26
RD9
10K_0402_5%
RD9
10K_0402_5%
RD8
10K_0402_5%
RD8
10K_0402_5%
3A@1.5V
3A@1.5V
3A@1.5V3A@1.5V
JDDRL
@JDDRL
@
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013022-2
TYCO_2-2013022-2
4
4
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DM1
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
VTT2
DQ4
DQ5
DQ6
DQ7
A15
A14
A11
CK1
BA1
S0#
NC2
SCL
3
6
DDR_A_D[0..63]
6
DDR_A_DQS[0..7]
6
DDR_A_DQS#[0..7]
6
DDRA_CKE1
DDR_A_MA[0..15]
11,6
6
6
6
6
6
6
6
6
0.1U_0402_10V6K
0.1U_0402_10V6K
CD15
CD15
11,13,32
11,13,32
3
+1.5V
RD6
RD6
1K_0402_1%
1K_0402_1%
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
CD16
CD16
RD7
RD7
1K_0402_1%
1K_0402_1%
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
+VREF_CA
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
DDR_A_D4
4
DDR_A_D5
6
8
DDR_A_DQS#0
10
DDR_A_DQS0
12
14
DDR_A_D6
16
DDR_A_D7
18
20
DDR_A_D12
22
DDR_A_D13
24
26
28
SM_DRAMRST#
30
32
DDR_A_D14
34
DDR_A_D15
36
38
DDR_A_D20
40
DDR_A_D21
42
44
46
48
DDR_A_D22
50
DDR_A_D23
52
54
DDR_A_D28
56
DDR_A_D29
58
60
DDR_A_DQS#3
62
DDR_A_DQS3
64
66
DDR_A_D30
68
DDR_A_D31
70
72
DDRA_CKE1
74
76
DDR_A_MA15
78
DDR_A_MA14
80
82
DDR_A_MA11
84
DDR_A_MA7
86
A7
88
DDR_A_MA6
90
A6
A4
A2
A0
G2
DDR_A_MA4
92
94
DDR_A_MA2
96
DDR_A_MA0
98
100
DDRA_CLK1
102
DDRA_CLK1#
104
106
DDR_A_BS1
108
DDR_A_RAS#
110
112
DDRA_SCS0#
114
116
118
DDRA_ODT1
120
122
124
126
128
DDR_A_D36
130
DDR_A_D37
132
134
136
138
DDR_A_D38
140
DDR_A_D39
142
144
DDR_A_D44
146
DDR_A_D45
148
150
DDR_A_DQS#5
152
DDR_A_DQS5
154
156
DDR_A_D46
158
DDR_A_D47
160
162
DDR_A_D52
164
DDR_A_D53
166
168
170
172
DDR_A_D54
174
DDR_A_D55
176
178
DDR_A_D60
180
DDR_A_D61
182
184
DDR_A_DQS#7
186
DDR_A_DQS7
188
190
DDR_A_D62
192
DDR_A_D63
194
196
198
PCH_SMBDATA
200
PCH_SMBCLK
202
204
206
+0.75VS
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
SM_DRAMRST#
DDRA_CLK1
DDRA_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
PCH_SMBDATA
PCH_SMBCLK
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Layout Note:
+1.5V
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
@
@
1
+
+
2
2
Place near JDDRL
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD7
CD7
CD8
CD8
1
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
CD10
CD10
CD9
CD9
1
1
2
2
Layout Note: Place these 4 Caps near
Command and Control signals of JDDRL
+1.5V
0.1U_0402_10V6K
0.1U_0402_10V6K
CD17
CD17
Layout Note:
Place near JDDRL.203,204
+0.75VS
CD21
1U_0402_6.3V6K
CD21
1U_0402_6.3V6K
1
1
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRIII-DDRL
DDRIII-DDRL
DDRIII-DDRL
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD11
CD11
CD12
CD12
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
CD18
CD18
CD22
1U_0402_6.3V6K
CD22
1U_0402_6.3V6K
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
CD19
CD19
CD23
1U_0402_6.3V6K
CD23
1U_0402_6.3V6K
1
CD14
CD14
CD13
CD13
1
1
@
@
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
CD20
CD20
CD24
1U_0402_6.3V6K
CD24
1U_0402_6.3V6K
1
2
1.0
1.0
10 60Wednesday, March 07, 2012
10 60Wednesday, March 07, 2012
10 60Wednesday, March 07, 2012
1.0
5
+1.5V
RD10
RD10
1K_0402_1%
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1K_0402_1%
0.1U_0402_10V6K
0.1U_0402_10V6K
CD28
CD28
DDRB_CKE06
DDR_B_BS26
DDRB_CLK06
DDRB_CLK0#6
DDR_B_BS06
DDR_B_WE#6
DDR_B_CAS#6
DDRB_SCS1#6
+3VS
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_B_D0
RD11
RD11
CD27
CD27
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
CD48
CD48
DDR_B_D1
CD51
CD51
DDR_B_D2
DDR_B_D3
DDR_B_D8
1K_0402_1%
1K_0402_1%
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDRB_CKE0
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDRB_CLK0
DDRB_CLK0#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS# DDRB_ODT0
DDR_B_MA13
DDRB_SCS1#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
RD14
RD14
10K_0402_5%
10K_0402_5%
0.1U_0402_10V6K
0.1U_0402_10V6K
CD49
CD49
RD15 10K_0402_5%RD15 10K_0402_5%
5
+V_DDR_REFB
D D
C C
B B
A A
+1.5V +1.5V
3A@1.5V
3A@1.5V
3A@1.5V3A@1.5V
JDDRH
@JDDRH
@
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO 2-1932300-1 204P H8.0
TYCO 2-1932300-1 204P H8.0
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
DQ4
DQ5
DQ6
DQ7
DM1
DM2
CK1
CK1#
BA1
NC2
DM4
DM6
SDA
SCL
VTT2
4
2
DDR_B_D4
4
DDR_B_D5
6
8
DDR_B_DQS#0
10
DDR_B_DQS0
12
14
DDR_B_D6
16
DDR_B_D7
18
20
DDR_B_D12
22
DDR_B_D13
24
26
28
SM_DRAMRST#
30
32
DDR_B_D14
34
DDR_B_D15
36
38
DDR_B_D20
40
DDR_B_D21
42
44
46
48
DDR_B_D22
50
DDR_B_D23
52
54
DDR_B_D28
56
DDR_B_D29
58
60
DDR_B_DQS#3
62
DDR_B_DQS3
64
66
DDR_B_D30
68
DDR_B_D31
70
72
DDRB_CKE1
74
76
DDR_B_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
DDR_B_MA14
80
82
DDR_B_MA11
84
DDR_B_MA7
86
88
DDR_B_MA6
90
DDR_B_MA4
92
94
DDR_B_MA2
96
DDR_B_MA0
98
100
DDRB_CLK1
102
DDRB_CLK1#
104
106
DDR_B_BS1
108
DDR_B_RAS#
110
112
DDRB_SCS0#
114
116
118
DDRB_ODT1
120
122
124
+VREF_CB
126
128
DDR_B_D36
130
DDR_B_D37
132
134
136
138
DDR_B_D38
140
DDR_B_D39
142
144
DDR_B_D44
146
DDR_B_D45
148
150
DDR_B_DQS#5
152
DDR_B_DQS5
154
156
DDR_B_D46
158
DDR_B_D47
160
162
DDR_B_D52
164
DDR_B_D53
166
168
170
172
DDR_B_D54
174
DDR_B_D55
176
178
DDR_B_D60
180
DDR_B_D61
182
184
DDR_B_DQS#7
186
DDR_B_DQS7
188
190
DDR_B_D62
192
DDR_B_D63
194
196
198
PCH_SMBDATA
200
PCH_SMBCLK
202
204
206
4
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
SM_DRAMRST#
DDRB_CKE1
DDRB_CLK1
DDRB_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
0.1U_0402_10V6K
0.1U_0402_10V6K
PCH_SMBDATA
PCH_SMBCLK
+0.75VS
10,6
6
6
6
6
6
6
6
6
CD46
CD46
10,13,32
10,13,32
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
6
DDR_B_DQS#[0..7]
6
DDR_B_D[0..63]
6
DDR_B_DQS[0..7]
6
DDR_B_MA[0..15]
RD12
RD12
1K_0402_1%
1K_0402_1%
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
CD47
CD47
RD13
RD13
1K_0402_1%
1K_0402_1%
3
+1.5V
Compal Secret Data
Compal Secret Data
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Layout Note:
Place near JDDRH
+1.5V
2
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
CD31
CD31
CD34
CD34
CD35
1
+
+
2
CD35
1
@
@
@
@
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD36
CD36
CD37
CD37
1
1
2
1
2
2
Layout Note: Place these 4 Caps near
Command and Control signals of JDDRH
+1.5V
Layout Note:
Place near JDDRH.203 and 204
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD38
CD38
CD39
CD39
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
CD32
CD32
CD29
CD29
+0.75VS
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
CD42
CD42
DDRIII-DDRH
DDRIII-DDRH
DDRIII-DDRH
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD40
CD40
0.1U_0402_10V6K
0.1U_0402_10V6K
CD30
CD30
1U_0603_10V6K
1U_0603_10V6K
CD44
CD44
CD43
CD43
11 60Wednesday, March 07, 2012
11 60Wednesday, March 07, 2012
11 60Wednesday, March 07, 2012
10U_0603_6.3V6M
10U_0603_6.3V6M
CD41
CD41
1
1
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
CD33
CD33
1U_0603_10V6K
1U_0603_10V6K
CD45
CD45
1.0
1.0
1.0
5
PCH_RTCX1
RH2 10M_0402_5%RH2 10M_0402_5%
1 2
YH1 32.768KHZ_12.5PF_CM31532768DZFTYH1 32.768KHZ_12.5PF_CM31532768DZFT
15P_0402_50V8J
15P_0402_50V8J
1
CH2
CH2
2
D D
50@
50@
CH2
CH2
18P_50V_NPO_0402
18P_50V_NPO_0402
ME_EN from EC.
Please place close to RH29 aviod the branch.
ME_EN38
34
AZ_BITCLK_HD
34
AZ_RST_HD#
C C
AZ_SDOUT_HD34
+3V_PCH +3V_PCH +3V_PCH
RH38
RH38
XDP@
XDP@
200_0402_5%
200_0402_5%
PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS
RH44
RH44
XDP@
XDP@
100_0402_1%
100_0402_1%
RH50
Intel DPDG Rev1.2 requirement.
B B
34
AZ_SYNC_HD
PCH_RTCX2
1
CH3
CH3
15P_0402_50V8J
15P_0402_50V8J
2
50@
50@
CH3
CH3
18P_50V_NPO_0402
18P_50V_NPO_0402
31@
31@
CH3
CH3
18P_50V_NPO_0402
18P_50V_NPO_0402
+RTCVCC
RH25 0_0402_5%RH25 0_0402_5%
1 2
RH27 33_0402_5%RH27 33_0402_5%
1 2
RH30 33_0402_5%RH30 33_0402_5%
1 2
RH32 33_0402_5%RH32 33_0402_5%
RH39
RH39
XDP@
XDP@
200_0402_5%
200_0402_5%
RH45
XDP@
XDP@
100_0402_1%
100_0402_1%
51_0402_5%
51_0402_5%
1 2
PCH_JTAG_TCK
1M_0402_5%
1M_0402_5%
XDP@RH50
XDP@
RH54 33_0402_5%RH54 33_0402_5%
+RTCVCC
1U_0603_10V4Z
1U_0603_10V4Z
RH23 20K_0402_5%RH23 20K_0402_5%
RH24 20K_0402_5%RH24 20K_0402_5%
1U_0603_10V4Z
1U_0603_10V4Z
HDA_SDOUT
HDA_BIT_CLK
HDA_RST#
HDA_SDOUT
RH40
RH40
XDP@
XDP@
200_0402_5%
200_0402_5%
RH46
RH46
XDP@
XDP@
100_0402_1%
100_0402_1%
12
RH56
RH56
RH12 1M_0402_5%RH12 1M_0402_5%
12
CMOS
CLRP1
34
G
G
2
D
S
D
S
BSS138_SOT23
BSS138_SOT23
QH1
QH1
39
39
39
39
39
13
CLRP1
SHORT PADS
SHORT PADS
12
CLRP2
CLRP2
SHORT PADS
SHORT PADS
ME CMOS
CLP1 & CLP2 place near DIMM
PCH_SPKR
AZ_SDIN0_HD
PCH_SPI_CLK
PCH_SPI_CS#
PCH_SPI_CS1#
PCH_SPI_MOSI
PCH_SPI_MISO
HDA_SYNCAZ_SYNC_HD_R
+5VS
CH4
CH4
CH5
CH5
SM_INTRUDER#
4
HM75@
HM75@
UH1
UH1
HM75
HM75
HM76@
HM76@
UH1
UH1
HM76
HM76
UH1A
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
HDA_BIT_CLK
HDA_SYNC
PCH_SPKR
HDA_RST#
AZ_SDIN0_HD
HDA_SDOUT
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_SPI_CLK
PCH_SPI_CS#
PCH_SPI_CS1#
PCH_SPI_MOSI
PCH_SPI_MISO
A20
C20
D20
G22
K22
C17
N34
L34
T10
K34
E34
34
G34
C34
A34
A36
C36
N32
J3
H7
K5
H1
T3
Y14
T1
V4
U3
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
UH1A
RTCX1
RTCX2
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
HDA_BCLK
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST # / GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
JTAG
JTAG
SPI ROM FOR ME ( 4MByte )
RTCIHDA
RTCIHDA
SPI
SPI
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
LPC_AD0
C38
LPC_AD1
A38
LPC_AD2
B37
LPC_AD3
C37
LPC_FRAME#
D36
LPC_LDRQ0#
E36
LPC_LDRQ1#
K36
SERIRQ
V5
SATA_PRX_C_DTX_N0
AM3
SATA_PRX_C_DTX_P0
AM1
SATA_PTX_DRX_N0
AP7
SATA_PTX_DRX_P0
AP5
AM10
AM8
AP11
AP10
SATA_PRX_C_DTX_N2
AD7
SATA_PRX_C_DTX_P2
AD5
SATA_PTX_DRX_N2
AH5
SATA_PTX_DRX_P2
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
PCH_SATALED#
P3
PCH_GPIO21
V14
BBS_BIT0_R
P1
3
SATA_COMP
SATA3_COMP
RBIAS_SATA3
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
SERIRQ 37,38
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
+1.05VS_VCC_SATA
RH41 37.4_0402_1%RH41 37.4_0402_1%
RH43 49.9_0402_1%RH43 49.9_0402_1%RH45
RH48 750_0402_1%RH48 750_0402_1%
+1.05VS_SATA3
PCH_SATALED#
37,38
37,38
37,38
37,38
37,38
2
36
36
36
36
36
36
36
36
42
HDD
+RTCVCC
PCH_INTVRMEN
RH33 330K_0402_5%RH33 330K_0402_5%
PCH_INTVRMEN
ODD
HDA_SDO
ME debug mode , this signal has a weak internal PD
L=>security measures defined in the Flash
Descriptor will be in effect (default)
H=>Flash Descriptor Security will be overridden
RH35 330K_0402_5%@RH35 330K_0402_5%@
INTVRMEN
H：Integrated VRM enable
*
L：Integrated VRM disable
SERIRQ
PCH_GPIO21
PCH_SATALED#
BBS_BIT0_R
PCH_SPKR
HDA_SDOUT
HDA_SYNC
This signal has a weak interna l pull-down
On Die PLL VR i s supplied by
1.5V when smapl ed high
1.8V when sampl ed low
Needs to be pul led High for Ch ief River platf rom
HDA_SYNC
RH55 1K_0402_5%RH55 1K_0402_5%
1
RH28 10K_0402_5%RH28 10K_0402_5%
RH29 10K_0402_5%RH29 10K_0402_5%
RH31 10K_0402_5%RH31 10K_0402_5%
RH34 4.7K_0402_5%@RH34 4.7K_0402_5%@
RH36 1K_0402_5%@RH36 1K_0402_5%@
LOW=Default
HIGH=No Reboot
*
RH42 1K_0402_5%@RH42 1K_0402_5%@
Low = Disabled
*
High = Enabled
+3VS
+3VS
+3V_PCH
+3V_PCH
Intel recommend
RTC Battery
+RTCBATT
MAX. 8000mil
RH62
CH7
CH7
RH65
RH65
PCH_SPI_CLK
0_0402_5%
10P_0402_50V8J
10P_0402_50V8J
Reserve for EMI
A A
0_0402_5%
5
+RTCVCC
W=20mils
1
CH8
CH8
1U_0603_10V4Z
1U_0603_10V4Z
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS
DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS
DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.
4
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.
3
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH (1/8) SATA,HDA,SPI, LPC
PCH (1/8) SATA,HDA,SPI, LPC
PCH (1/8) SATA,HDA,SPI, LPC
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
RH62
1K_0402_5%
1K_0402_5%
1
DH1
DH1
W=20mils
2
3
BAS40-04_SOT23-3
BAS40-04_SOT23-3
1
+CHGRTC
W=20mils
1.0
1.0
12 60Wednesday, March 07, 2012
12 60Wednesday, March 07, 2012
12 60Wednesday, March 07, 2012
1.0
5
D D
10/100/1G LAN --->
MiniWLAN (Mini Card 1)--->
EXPRESS_CARD --->
C C
10/100/1G LAN --->
MiniWLAN (Mini Card 1)--->
EXPRESS_CARD --->
B B
@
@
RH113
CLK_PCI_LPBACK
Reserve for EMI please close t o
UH4
CH26
CH26
1
15P_0402_50V8J
15P_0402_50V8J
1
2
A A
RH113
33_0402_5%
33_0402_5%
RH1171M_0402_5% RH1171M_0402_5%
YH2
YH2
1
GND
GND
2
4
CH27
25MHZ_20PF_7V25000016
25MHZ_20PF_7V25000016
CH27
3
1 2
12
22P_0402_50V8J
22P_0402_50V8J
3
12P_0402_50V8J
12P_0402_50V8J
1
2
5
PCIE_PRX_GLANTX_N133
PCIE_PRX_GLANTX_P133
33
PCIE_PTX_GLANRX_N1
33
PCIE_PTX_GLANRX_P1
PCIE_PRX_WLANTX_N232
PCIE_PRX_WLANTX_P232
32
PCIE_PTX_WLANRX_N2
32
PCIE_PTX_WLANRX_P2
PCIE_PRX_EXPTX_N332
PCIE_PRX_EXPTX_P332
32
PCIE_PTX_EXPRX_N3
32
PCIE_PTX_EXPRX_P3
@
@
CH25
CH25
XTAL25_IN
XTAL25_OUT
7
CLK_RES_ITP#
7
CLK_RES_ITP
33
CLK_PCIE_LAN#
33
CLK_PCIE_LAN
32
CLK_PCIE_WLAN#
32
CLK_PCIE_WLAN
WLANCLK_REQ#32
32
CLK_PCIE_EXP#
32
CLK_PCIE_EXP
EXPCLK_REQ#32
CH9 0.1U_0402_10V7KCH9 0.1U_0402_10V7K
CH12 0.1U_0402_10V7KCH12 0.1U_0402_10V7K
CH13 0.1U_0402_10V7KCH13 0.1U_0402_10V7K
CH14 0.1U_0402_10V7KCH14 0.1U_0402_10V7K
CH10 0.1U_0402_10V7KCH10 0.1U_0402_10V7K
CH15 0.1U_0402_10V7KCH15 0.1U_0402_10V7K
RH92 0_0402_5%RH92 0_0402_5%
RH93 0_0402_5%RH93 0_0402_5%
+3V_PCH
LANCLK_REQ#33
+3VS
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
RH95 10K_0402_5%RH95 10K_0402_5%
RH97 0_0402_5%RH97 0_0402_5%
RH98 0_0402_5%RH98 0_0402_5%
RH99 10K_0402_5%RH99 10K_0402_5%
RH100 0_0402_5%RH100 0_0402_5%
RH101 0_0402_5%RH101 0_0402_5%
RH104 10K_0402_5%RH104 10K_0402_5%
RH107 10K_0402_5%RH107 10K_0402_5%
RH109 10K_0402_5%RH109 10K_0402_5%
RH112 10K_0402_5%RH112 10K_0402_5%
RH114 10K_0402_5%RH114 10K_0402_5%
RH116 10K_0402_5%RH116 10K_0402_5%
RH119 10K_0402_5%RH119 10K_0402_5%
RH122 0_0402_5%@RH122 0_0402_5%@
RH123 0_0402_5%@RH123 0_0402_5%@
4
PCIE_PRX_GLANTX_N1
PCIE_PRX_GLANTX_P1
PCIE_PTX_GLANRX_N1_C
PCIE_PTX_GLANRX_P1_C
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2_C
PCIE_PTX_WLANRX_P2_C
PCIE_PRX_EXPTX_N3
PCIE_PRX_EXPTX_P3
PCIE_PTX_EXPRX_N3_C
PCIE_PTX_EXPRX_P3_C
PCIE_LAN#
PCIE_LAN
LANCLK_REQ#
PCIE_WLAN#
PCIE_WLAN
WLANCLK_REQ#
PCIE_EXP#
PCIE_EXP
EXPCLK_REQ#
PCH_GPIO25
PCH_GPIO26
PCH_GPIO44
PCH_GPIO56
PCH_GPIO45
PCH_GPIO46
CLK_BCLK_ITP#
CLK_BCLK_ITP
4
UH1B
UH1B
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
3
PCH_GPIO11
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
CLKIN_PCILOOPBACK
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
3
E12
SMBCLK
H14
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
CLKIN_DMI_N
CLKIN_DMI_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SMBDATA
C9
DRAMRST_CNTRL_PCH
A12
SML0CLK
C8
SML0DATA
G12
PCH_HOT#
C13
SML1CLK
E14
SML1DATA
M16
M7
T11
P10
PEG_CLKREQ#
M10
CLK_PCIE_VGA#
AB37
CLK_PCIE_VGA
AB38
CLK_CPU_DMI#
AV22
CLK_CPU_DMI
AU22
AM12
AM13
CLKIN_DMI#
BF18
CLKIN_DMI
BE18
CLKIN_DMI2#
BJ30
CLKIN_DMI2
BG30
CLKIN_DOT96#
G24
CLKIN_DOT96
E24
CLKIN_SATA#
AK7
CLKIN_SATA
AK5
CLK_PCH_14M
K45
CLK_PCI_LPBACK
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
K43
F47
H47
K49
MEMORY
DRAMRST_CNTRL_PCH
PCH_HOT#
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_PCI_LPBACK
RH115 90.9_0402_1%RH115 90.9_0402_1%
Compal Secret Data
Compal Secret Data
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
Compal Secret Data
2
6
38
RH9010K_0402_5% DIS@ RH9010K_0402_5% DIS@
RH8910K_0402_5% UMA@ RH8910K_0402_5% UMA@
20
VGA
20
5
5
15
+1.05VS_VCCDIFFCLKN
Deciphered Date
Deciphered Date
Deciphered Date
2
+3V_PCH
PEG_CLKREQ#
SMBCLK
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
SMBDATA
20
6 1
SML1CLK
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
SML1DATA
1
PCH_GPIO11
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA
PCH_HOT#
DRAMRST_CNTRL_PCH
CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M
If use extenal CLK gen, please place close to CLK gen
else, please pl ace close to PC H
RH102
RH102
2.2K_0402_5%
2.2K_0402_5%
2
QH3A
QH3A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
5
3
4
QH3B
QH3B
+3VS
2
6 1
QH4A
QH4A
3
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
QH4B
QH4B
Title
Title
Title
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
PCH (2/8) PCIE, SMBUS, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
Date: Sheet
Date: Sheet of
Date: Sheet of
RH105 10K_0402_5%RH105 10K_0402_5%
RH70 2.2K_0402_5%RH70 2.2K_0402_5%
RH72 2.2K_0402_5%RH72 2.2K_0402_5%
RH77 2.2K_0402_5%RH77 2.2K_0402_5%
RH73 2.2K_0402_5%RH73 2.2K_0402_5%
RH74 2.2K_0402_5%RH74 2.2K_0402_5%
RH78 2.2K_0402_5%RH78 2.2K_0402_5%
RH75 10K_0402_5%RH75 10K_0402_5%
RH76 1K_0402_1%RH76 1K_0402_1%
RH79
RH79
RH80
RH80
RH81 10K_0402_5%RH81 10K_0402_5%
RH82 10K_0402_5%RH82 10K_0402_5%
RH83 10K_0402_5%RH83 10K_0402_5%
RH84 10K_0402_5%RH84 10K_0402_5%
RH85 10K_0402_5%RH85 10K_0402_5%
RH86 10K_0402_5%RH86 10K_0402_5%
RH87 10K_0402_5%RH87 10K_0402_5%
+3VS+3VS
RH103
RH103
2.2K_0402_5%
2.2K_0402_5%
5
4
Compal Electronics, Inc.
1
+3V_PCH
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
PCH_SMBCLK
PCH_SMBDATA
10,11,32
10,11,32
PCH_SMLCLK 20,38
PCH_SMLDATA 20,38
of
13 60Wednesday, March 07, 2012
13 60Wednesday, March 07, 2012
13 60Wednesday, March 07, 2012
1.0
1.0
1.0
5
4
3
2
1
UH1C
UH1C
DMI_CTX_PRX_N04
DMI_CTX_PRX_N14
DMI_CTX_PRX_N24
DMI_CTX_PRX_N34
DMI_CTX_PRX_P04
PBTN_OUT#38
DMI_CTX_PRX_P14
DMI_CTX_PRX_P24
DMI_CTX_PRX_P34
4
DMI_CRX_PTX_N0
4
DMI_CRX_PTX_N1
4
DMI_CRX_PTX_N2
4
DMI_CRX_PTX_N3
4
DMI_CRX_PTX_P0
4
DMI_CRX_PTX_P1
4
DMI_CRX_PTX_P2
4
DMI_CRX_PTX_P3
+1.05VS_VCC_EXP
SYSTEM_PWROK
RH130 0_0402_5%RH130 0_0402_5%
RH131 0_0402_5%RH131 0_0402_5%
RH134
RH134
ACIN20,38,47
RB751V-40_SOD323-2
RB751V-40_SOD323-2
RH147 0_0402_5%RH147 0_0402_5%
PCH_PWROK
RH126 49.9_0402_1%RH126 49.9_0402_1%
RH127 750_0402_1%RH127 750_0402_1%
4mil width and place
within 500mil of the PCH
PM_DRAM_PWRGD
RH137 0_0402_5%RH137 0_0402_5%
1 2
5
D D
C C
B B
A A
PCH_PWROK38
5
PM_DRAM_PWRGD
PCH_RSMRST#38
VGATE38,53
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
XDP_DBRESET#_R
SYSTEM_PWROK_I
PM_PWROK_R
RH132 0_0402_5%RH132 0_0402_5%
PCH_RSMRST#_R
0_0402_5%
0_0402_5%
SUSWARN#
DH2
DH2
AC_PRESENT_R
+3VS
5
UH5
UH5
2
P
B
4
Y
1
A
G
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
PCH_GPIO72
RI#
WAKE#
AC_PRESENT_R
SUSWARN#
PCH_GPIO29
XDP_DBRESET#_R
PCH_RSMRST#
DMI_IRCOMP
RBIAS_CPY
PBTN_OUT#_R
RH155 10K_0402_5%RH155 10K_0402_5%
RH157 10K_0402_5%RH157 10K_0402_5%
RH159 10K_0402_5%RH159 10K_0402_5%
RH161 330K_0402_5%RH161 330K_0402_5%
RH234 10K_0402_5%RH234 10K_0402_5%
RH162 10K_0402_5%@ RH162 10K_0402_5%@
RH156 1K_0402_5%RH156 1K_0402_5%
RH163 10K_0402_5%RH163 10K_0402_5%
PCH_GPIO72
RI#
SYSTEM_PWROK
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
SYSTEM_PWROK
+3V_PCH
+3VS
DMI
DMI
SUS_STAT# / GPIO61
System Power Management
System Power Management
5
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI
FDI
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
CLKRUN# / GPIO32
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
Check EC for S3 S4 LED
DSWODVREN
DSWODVREN
DSWODVREN - On Die DSW VR Enab le
H：Enable
*
L：Disable
4
FDI_CTX_PRX_N0
BJ14
FDI_CTX_PRX_N1
AY14
FDI_CTX_PRX_N2
BE14
FDI_CTX_PRX_N3
BH13
FDI_CTX_PRX_N4
BC12
FDI_CTX_PRX_N5
BJ12
FDI_CTX_PRX_N6
BG10
FDI_CTX_PRX_N7
BG9
FDI_CTX_PRX_P0
BG14
FDI_CTX_PRX_P1
BB14
FDI_CTX_PRX_P2
BF14
FDI_CTX_PRX_P3
BG13
FDI_CTX_PRX_P4
BE12
FDI_CTX_PRX_P5
BG12
FDI_CTX_PRX_P6
BJ10
FDI_CTX_PRX_P7
BH9
FDI_INT
AW16
FDI_FSYNC0
AV12
FDI_FSYNC1
BC10
FDI_LSYNC0
AV14
FDI_LSYNC1
BB10
DSWODVREN
A18
E22
WAKE#
RH129
B9
N3
G8
N14
D10
H4
F4
G10
G16
AP14
K14
PM_CLKRUN#
RH129
0_0402_5%
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
H_PM_SYNC
PCH_GPIO29
+3VS
0_0402_5%
RH133
RH133
RH256
RH256
8.2K_0402_5%
8.2K_0402_5%
RH160
RH160
10K_0402_5%
10K_0402_5%
@
@
PM_CLKRUN#
SUSCLK
RH150 330K_0402_5%RH150 330K_0402_5%
RH151 330K_0402_5%@RH151 330K_0402_5%@
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
RH128 0_0402_5%RH128 0_0402_5%
0_0402_5%
0_0402_5%
H_PM_SYNC
+RTCVCC
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
PCH_RSMRST#_RPCH_DPWROK
PCIE_WAKE# 32,33
PM_CLKRUN#
SUSCLK_R
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
37
38
38
38
38
Can be left NC when IAMT is
not support on the platfrom
5
3
Pull high at LVDS conn side.
38
PCH_ENBKL
29
PCH_ENVDD
29
PCH_BL_PWM
29
LCD_EDID_CLK
29
LCD_EDID_DATA
RH245 2.37K_0402_1%RH245 2.37K_0402_1%
29
LCD_TXCLK-
29
LCD_TXCLK+
29
LCD_TXOUT0-
29
LCD_TXOUT1-
29
LCD_TXOUT2-
29
LCD_TXOUT0+
29
LCD_TXOUT1+
29
LCD_TXOUT2+
29
LCD_TZCLK-
29
LCD_TZCLK+
29
LCD_TZOUT0-
29
LCD_TZOUT1-
29
LCD_TZOUT2-
29
LCD_TZOUT0+
29
LCD_TZOUT1+
29
LCD_TZOUT2+
30
PCH_CRT_B
30
PCH_CRT_G
30
PCH_CRT_R
30
PCH_CRT_CLK
30
PCH_CRT_DATA
PCH_CRT_HSYNC30
PCH_CRT_VSYNC30
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
33_0402_5%
33_0402_5%
R286
UMA@ R286
UMA@
R288
UMA@ R288
UMA@
33_0402_5%
33_0402_5%
1K_0402_0.5%
1K_0402_0.5%
+3VS
UMA@
UMA@
RH294 2.2K_0402_5%
RH294 2.2K_0402_5%
UMA@
UMA@
RH295 2.2K_0402_5%
RH295 2.2K_0402_5%
UMA@
UMA@
RH135 150_0402_1%
RH135 150_0402_1%
UMA@
UMA@
RH136 150_0402_1%
RH136 150_0402_1%
UMA@
UMA@
RH139 150_0402_1%
RH139 150_0402_1%
2011/05/23 2012/12/31
2011/05/23 2012/12/31
2011/05/23 2012/12/31
PCH_ENBKL
CTRL_CLK
CTRL_DATA
LVDS_IBG
12
LCD_TXCLKLCD_TXCLK+
LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2-
LCD_TXOUT0+
LCD_TXOUT1+
LCD_TXOUT2+
LCD_TZCLK-
LCD_TZCLK+
LCD_TZOUT0LCD_TZOUT1LCD_TZOUT2-
LCD_TZOUT0+
LCD_TZOUT1+
LCD_TZOUT2+
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_HSYNC_R
12
PCH_CRT_VSYNC_R
12
CRT_IREF
RH138
RH138
1 2
1 2
1 2
1 2
1 2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
UH1D
UH1D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
2
LVDS
LVDS
CRT
CRT
DPC_HPD
100K_0402_5%
100K_0402_5%
DPD_HPD
100K_0402_5%
100K_0402_5%
UMA_HDMI_HPD
100K_0402_5%
100K_0402_5%
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
RH254
@RH254
@
RH141
@RH141
@
RH142
RH142
+3VS
UMA@
UMA@
R368 2.2K_0402_5%
R368 2.2K_0402_5%
1 2
UMA@
UMA@
R369 2.2K_0402_5%
R369 2.2K_0402_5%
1 2
UMA@
UMA@
R394 2.2K_0402_5%
R394 2.2K_0402_5%
1 2
UMA@
UMA@
R393 2.2K_0402_5%
R393 2.2K_0402_5%
1 2
UMA@
UMA@
R395 2.2K_0402_5%
R395 2.2K_0402_5%
1 2
UMA@
UMA@
R396 2.2K_0402_5%
R396 2.2K_0402_5%
1 2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
UMA_HDMI_TX2UMA_HDMI_TX2+
UMA_HDMI_TX1UMA_HDMI_TX1+
UMA_HDMI_TX0UMA_HDMI_TX0+
UMA_HDMI_TXCUMA_HDMI_TXC+
DPC_HPD
DPD_HPD
CTRL_CLK
CTRL_DATA
LCD_EDID_CLK
LCD_EDID_DATA
UMA_HDMI_CLK
UMA_HDMI_DATA
UMA_HDMI_CLK
UMA_HDMI_DATA
UMA_HDMI_HPD
UMA_HDMI_TX2UMA_HDMI_TX2+
UMA_HDMI_TX1UMA_HDMI_TX1+
UMA_HDMI_TX0UMA_HDMI_TX0+
UMA_HDMI_TXCUMA_HDMI_TXC+
Compal Electronics, Inc.
PCH (3/8) DMI,FDI,PM,GFX,DP
PCH (3/8) DMI,FDI,PM,GFX,DP
PCH (3/8) DMI,FDI,PM,GFX,DP
QAL51, LA-7871P MB
QAL51, LA-7871P MB
QAL51, LA-7871P MB
1
14 60Wednesday, March 07, 2012
14 60Wednesday, March 07, 2012
14 60Wednesday, March 07, 2012
31
31
31
31
31
31
31
31
31
31
31
1.0
1.0
1.0
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