Compal LA-7852P Schematics

A

B

C

D

E

MODEL NAME :

PCB NO :

QBL00

QC:LA-7851P, DAA00003200 DC:LA-7852P, DAA00003300

BOM P/N :

1 1

TBD

Dell/Compal Confidential

GV+Hyn M 1G R1

UV4

H5GQ2H24MFR-T2C_BGA 170P~D

GVHM@

UV5

H5GQ2H24MFR-T2C_BGA 170P~D

GVHM@

UV6

H5GQ2H24MFR-T2C_BGA 170P~D

GVHM@

UV7

Phantom(Chief River)

Ivy Bridge(BGA1224) + Panther Point

Schematic Document

DISCRETE VGA N13P-GS(optimus)

H5GQ2H24MFR-T2C_BGA 170P~D

2 2

GVHM@

GV+SAM C 1G R1

UV4

K4G20325FC-HC04_FBGA170P~D

GVSC@

UV5

K4G20325FC-HC04_FBGA170P~D

GVSC@

UV6

K4G20325FC-HC04_FBGA170P~D

GVSC@

UV7

3 3

K4G20325FC-HC04_FBGA170P~D

GVSC@

GV+SAM D 1G R1

UV7

K4G20325FC-HC04_FBGA170P~D

GVSD@

UV4

K4G20325FC-HC04_FBGA170P~D

GVSD@

UV5

K4G20325FC-HC04_FBGA170P~D

GVSD@

UV6

4 4

K4G20325FC-HC04_FBGA170P~D

GVSD@

GS+SAM D 2G R1 GS+Hyn M 2G R1

UV4

K4G20325FC-HC04_FBGA170P~D

GSSD@

UV5

K4G20325FC-HC04_FBGA170P~D

GSSD@

UV6

K4G20325FC-HC04_FBGA170P~D

GSSD@

UV7

K4G20325FC-HC04_FBGA170P~D

GSSD@

UV8

K4G20325FC-HC04_FBGA170P~D

GSSD@

UV9

K4G20325FC-HC04_FBGA170P~D

GSSD@

UV10

K4G20325FC-HC04_FBGA170P~D

GSSD@

UV11

K4G20325FC-HC04_FBGA170P~D

GSSD@

UV4

H5GQ2H24MFR-T2C_BGA 170P~D

GSHM@

UV5

H5GQ2H24MFR-T2C_BGA 170P~D

GSHM@

UV6

H5GQ2H24MFR-T2C_BGA 170P~D

GSHM@

UV7

H5GQ2H24MFR-T2C_BGA 170P~D

GSHM@

UV8

H5GQ2H24MFR-T2C_BGA 170P~D

GSHM@

UV9

H5GQ2H24MFR-T2C_BGA 170P~D

GSHM@

UV10

H5GQ2H24MFR-T2C_BGA 170P~D

GSHM@

UV11

H5GQ2H24MFR-T2C_BGA 170P~D

GSHM@

2011-08-02

Rev: 0.1 (X00)

@ : Nopop Component CONN@ : Connector Component DP1.2@ : DP output from DGPU DP1.1A@ : DP output from iGPU GV@ : GPU N13-GV GS@ : GPU N13-GS GVH@ :GV+Hynix VRAM GVS@ : GV+Samsung VRAM GSH@ : GS+Hynix VRAM GSS@ : GS+Samsung VRAM GVHA@ : GV+Hynix VRAM A-die GVHM@ : GV+Hynix VRAM M-die GVSC@ : GV+Samsung VRAM C-die GVSD@ : GV+Samsung VRAM D-die SB@ : Sandy bridge CPU TPM@ : With TPM

GS+SAM D 2G R3

UV8

K4G20325FC-HC04_FBGA170P~D

GSSDR3@

UV9

K4G20325FC-HC04_FBGA170P~D

GSSDR3@

UV10

K4G20325FC-HC04_FBGA170P~D

GSSDR3@

UV11

K4G20325FC-HC04_FBGA170P~D

GSSDR3@

GS+HYN M 2G R3

UV8

K4G20325FC-HC04_FBGA170P~D

GSHMR3@

UV9

K4G20325FC-HC04_FBGA170P~D

GSHMR3@

UV10

K4G20325FC-HC04_FBGA170P~D

GSHMR3@

UV11

K4G20325FC-HC04_FBGA170P~D

GSHMR3@

UV4

K4G20325FC-HC04_FBGA170P~D

GSSDR3@

UV7

K4G20325FC-HC04_FBGA170P~D

GSSDR3@

UV5

K4G20325FC-HC04_FBGA170P~D

GSSDR3@

UV6

K4G20325FC-HC04_FBGA170P~D

GSSDR3@

UV4

K4G20325FC-HC04_FBGA170P~D

GSHMR3@

UV7

K4G20325FC-HC04_FBGA170P~D

GSHMR3@

UV6

K4G20325FC-HC04_FBGA170P~D

GSHMR3@

UV5

K4G20325FC-HC04_FBGA170P~D

GSHMR3@

GV+Hyn M 1G R3

UV6

H5GQ2H24MFR-T2C_BGA 170P~D

GVHMR3@

UV4

H5GQ2H24MFR-T2C_BGA 170P~D

GVHMR3@

UV5

H5GQ2H24MFR-T2C_BGA 170P~D

GVHMR3@

UV7

H5GQ2H24MFR-T2C_BGA 170P~D

GVHMR3@

GV+SAM C 1G R3

UV7

K4G20325FC-HC04_FBGA170P~D

GVSCR3@

UV4

K4G20325FC-HC04_FBGA170P~D

GVSCR3@

UV5

K4G20325FC-HC04_FBGA170P~D

GVSCR3@

UV6

K4G20325FC-HC04_FBGA170P~D

GVSCR3@

GV+SAM D 1G R3

UV7

K4G20325FC-HC04_FBGA170P~D

GVSDR3@

UV4

K4G20325FC-HC04_FBGA170P~D

GVSDR3@

UV5

K4G20325FC-HC04_FBGA170P~D

GVSDR3@

UV6

K4G20325FC-HC04_FBGA170P~D

GVSDR3@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/08/25 2011/08/25

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-7851P

E

1 65Monday, March 26, 2012

0.1

A

B

C

D

E

FFS

ZZZ

R1@

1 1

PCB-MB

ZZZ

R3@

PCB-MB

2 2

QT

Mini DP Conn.

LVDS Conn.

HDMI Conn.

Port 4

P.31~32

128M*16 x4 =1G

VRAM * 4 GDDR5

reserve for N13P-GS

P.37

P.35

P.36

PCIE Re-driver SN65LVPE501RGER

P.40

3 3

Card Reader

RTS5209

9 in 1

Socket

Daughter board

RTC CKT.

Power On/Off CKT.

4 4

DC/DC Interface CKT.

P.16

P.39

P.33~34

128M*16 x4 =1G

VRAM * 4 GDDR5

GPU N13P-GV / N13P-GS

64bit

Port 3

Mini Card-1 WLAN / BT4.0

Half

USB2.0

Port 4

P.42

Discrete TPM AT97SC3204

64bit

GB4-128

P.24~28

0 ohm

DisplayPort

P.40

P.29~30

PCI-E x1

LAN(GbE)

RTL8111F

RJ45

SPI ROM

PEG 3.0 x16

DisplayPort

0 ohm

LVDS

HDMI

Port 1

P.41

P.16

Intel

Ivy Bridge Processor

35W QC

35W DC

100MHz 100MHz

2.7GT/s

BGA 1224

BGA 1023

Intel

Panther Point

PCH HM77

BGA 989 Balls

SPI

Int.KBD

P.39

LPC Bus

33MHz

ENE KBC KB9012

PS/2

Touch Pad

P.39

P.38

Memory Bus (DDR3)

1.5V DDR3 1333 MHz

P.5~13

DMI x4FDI x8

5GB/s

SATA3.0

USB 3.0

USB2.0

HD Audio

P16~23

Dual Channel

Port 1,3

Port 0,2

Port 0

Port 1

Port 2

Port 1

Port 12

Port 4

Fan Control

P.43

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7

SATA3 Re-Driver PS8520

Mini Card-2 (mSATA)

( Full )

SATA ODD Conn.

USB 3.0 Conn. X2

PI5USB1457

Digital Camera

Mini Card-1 (WLAN)

( Half )

Audio Codec ALC3260

AMP TI 3113

Int. Speaker x2

P.39

8GB Max

P.46

P.47

CPU XDP Conn.

page 14,15

P.43

P.42

P.43

P.44

P.45

P.35

P.42

P.6

SATA HDD Conn.

P.43

Daughter board

USB 3.0 Conn. X1

( USB Charger )

P.45

Daughter board

Digi Mic x2

Headphone Jack

Headphone / Mic. Jack

( Combo )

www.schematic-x.blogspot.com

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

C

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

D

Compal Electronics,Inc.

Title

Size Document Number Rev

2 66Monday, March 26, 2012

Date: Sheet of

E

2 66Monday, March 26, 2012

0.1C

A

B

C

D

E

Compal Confidential

Project Code : QBL00 File Name : LA-7851P

1 1

LA-7851P M/B

JCCD

JLVDS

2 2

JHDD

JTB1

JODD

JBLEDJLED

JTB2

26 pin

2 pin

12 pin

40 pin

24 pin

26 pin

Wire

FFC

Camera

LCD Panel

HDD

Touch Pad

3 3

FFC12 pin

JP1

LS-7854P

ODD/B

FFC4 pin

JLED

LS-7853P LS-7852P

LED/B BATT LED/B

JP1

FFC8 pin

Hot BarHot BarHot BarHot Bar

Led x 5Led x 2

Wire

JIO1JP2

LS-7851P

Audio/B

FFC

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

E

0.1

3 66Monday, March 26, 2012

0.1

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5%

100K +/- 5% 200K +/- 5%

NC

AD_BID

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

max

EC AD3

0x00-0x0C 0x0D-0x1C 0x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF

A

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

PCB Revision

0.1

0.2

0.3

0.4

1.0

PCH

USB PORT#

0

1

2

3

4

5

DESTINATION

USB Conn 1

USB Conn 3 (Power share)

USB Conn 2

None

JMINI1 (WLAN)

None

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

1 1

DESTINATION

10/100/1G LAN

None

MINI CARD-1 WLAN

CARD READER

None

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

DESTINATION

HDD

SSD

ODD

None None

None

CLKOUT

PCI0

PCI1

PCI2

PCI3

PCI4

None

DESTINATION

PCH_LOOPBACK

EC LPC

None

6

7

8

9

10

11

12

13

None

CAMERA

None

Lane 8 None

CLK

CLKOUT_PCIE0

CLKOUT_PCIE1

CLKOUT_PCIE2

CLKOUT_PCIE3

CLKOUT_PCIE4

CLKOUT_PCIE5

CLKOUT_PCIE6

DESTINATIONDIFFERENTIAL

10/100/1G LAN

None

MINI CARD-1 WLAN

CARD READER

None

FLEX CLOCKS DESTINATION

CLKOUTFLEX0None

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

CLK_PCI_TPM

None

LAN_25M

None

USB3

1

2

3

4

Symbol Note :

: means Digital Ground

DESTINATION

USB Conn 1

USB Conn 3 (Power share)

USB Conn 2

None

CLKOUT_PCIE7 None

CLKOUT_PEG_B

None

: means Analog Ground

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-7851P

4 66Monday, March 26, 2012

0.1

5

4

3

2

1

+3VS

SMBUS Address [0x9a]

D D

H14

C9

SMBCLK

SMBDATA

PCH

A8

A7

2.2K

SML0CLK

SML0DATA

+3V_PCH

EC_SMB_CK1

EC_SMB_DA1

C8

G12

E14M16

SML1CLK

C C

SML1DATA

KBC

B B

2.2K

+3V_PCH

+3VALW_EC

+3VS

DMN66D0

2.2K

+3VS_WLAN

2.2K

100 ohm

30

32

100 ohm

+3VS_WLAN

9

8

4

5

SMBUS Address [TBD]WLAN

CHARGER

BATTERY CONN

SMBUS Address [TBD]

202

200

202

200

4

5

4

6

51

53

DIMMA

DIMMB

G Sensor

XDP

TP

SMBUS Address [A0]

SMBUS Address [TBD]

+3VS

2.2K

+3VS

DMN66D0

2.2K

10

ALS

9

+3V_GPU

2.2K

Issued Date

2.2K

D9

D8

2011/08/25 2012/07/15

3

SMBUS Address [0x9E]

GPU

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

SMBus Block Diagram

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

5 66Monday, March 26, 2012

1

0.1

+3VS

B8

PCH_SMLCLK

A6

PCH_SMLDATA

A A

5

2.2K

4

+3V_GPU

DMN66D0

Security Classification

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

5

4

3

2

1

XDP CONN

+VCCP +VCCP

JXDP

D D

C C

The resistor for HOOK2 shoul d be placed such tha t the stub is very sm all on CFG0 net

XDP_PREQ#(8) XDP_PRDY#(8)

XDP_BPM#0(8) XDP_BPM#1(8)

XDP_BPM#2(8) XDP_BPM#3(8)

CFG10(10) CFG11(10)

XDP_BPM#4(8) XDP_BPM#5(8)

XDP_BPM#6(8) XDP_BPM#7(8)

H_CPUPWRGD(8,20)

PBTN_OUT#(18,38)

CFG0(10)

VGATE(18,38,59)

PCH_SMBDATA(14,15,17,39,43)

PCH_SMBCLK(14,15,17,39,43)

XDP_TCK(8)

+3VS

XDP_TCK

RU36 1K_0402_5%@RU36 1K_0402_5%@

RU13 0_0402_5%~D@RU13 0_0402_5%~D@ RU14 0_0402_5%~D@RU14 0_0402_5%~D@

RU7 1K_0402_5%~D@RU7 1K_0402_5%~D@ RU8 0_0402_5%~D@RU8 0_0402_5%~D@

RU9 1K_0402_5%~D@RU9 1K_0402_5%~D@ RU10 0_0402_5%~D@RU10 0_0402_5%~D@

1 2

1 2 1 2

T32 PAD@ T32 PAD@

XDP_PREQ# XDP_PRDY#

XDP_BPM#0 XDP_BPM#1

XDP_BPM#2 XDP_BPM#3

CFG10_R CFG11_R

XDP_BPM#4 XDP_BPM#5

XDP_BPM#6 XDP_BPM#7

H_CPUPWRGD_XDP CFD_PWRBTN#_X DP

CFG0_R SYS_PWROK_XDP

SYS_PWROK_XDP

JXDP

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

52

515152

54

535354

56

555556

58

575758

60

595960

SAMTE_BSH-030-01-L-D-A-TR

CONN@

CLK_CPU_ITP CLK_CPU_ITP#

XDP_RST#_R XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

Place near JXDP

+VCCP

1

@CU33

@

0.1U_0402_25V6K~D

2

CLK_CPU_ITP (17)

1 2

CLK_CPU_ITP# (17)

XDP_DBRESET# (8,18)

XDP_TDO (8) XDP_TRST# (8) XDP_TDI (8) XDP_TMS (8)

RU12 1K_0402_5%~D@RU12 1K_0402_5%~D@

CU33

1

CU34

@CU34

@

0.1U_0402_25V6K~D

2

PLT_RST# (8,19,38,40,41,42)

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

1

0.1

6 66Monday, March 26, 2012

0.1

5

D D

UU1

E0@

AV8063801130703 QC02 E0 2.1G

UU1

QCR1@

S IC AV8063801130704 SR0MR E1 2.1G BGA 1224

UU1

QCR3@

C C

B B

QCR3@

S IC AV8063801130704 SR0MR E1 2.1G BGA 1224 A31 !

ST

DMI_CRX_PTX_N0(18) DMI_CRX_PTX_N1(18) DMI_CRX_PTX_N2(18) DMI_CRX_PTX_N3(18)

DMI_CRX_PTX_P0(18) DMI_CRX_PTX_P1(18)

QT

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

DMI_CRX_PTX_P2(18) DMI_CRX_PTX_P3(18)

DMI_CTX_PRX_N0(18) DMI_CTX_PRX_N1(18) DMI_CTX_PRX_N2(18) DMI_CTX_PRX_N3(18)

DMI_CTX_PRX_P0(18) DMI_CTX_PRX_P1(18) DMI_CTX_PRX_P2(18) DMI_CTX_PRX_P3(18)

FDI_CTX_PRX_N0(18) FDI_CTX_PRX_N1(18) FDI_CTX_PRX_N2(18) FDI_CTX_PRX_N3(18) FDI_CTX_PRX_N4(18) FDI_CTX_PRX_N5(18) FDI_CTX_PRX_N6(18) FDI_CTX_PRX_N7(18)

FDI_CTX_PRX_P0(18) FDI_CTX_PRX_P1(18) FDI_CTX_PRX_P2(18) FDI_CTX_PRX_P3(18) FDI_CTX_PRX_P4(18) FDI_CTX_PRX_P5(18) FDI_CTX_PRX_P6(18) FDI_CTX_PRX_P7(18)

FDI_FSYNC0(18) FDI_FSYNC1(18)

FDI_INT(18)

FDI_LSYNC0(18) FDI_LSYNC1(18)

+VCCP

RU2 24.9_0402_1%RU2 24.9_0402_1%

1 2

4

EDP_COMP

UU1A

N10

DMI_RX#[0]

R10

DMI_RX#[1]

R8

DMI_RX#[2]

U10

DMI_RX#[3]

N8

DMI_RX[0]

T9

DMI_RX[1]

R6

DMI_RX[2]

U8

DMI_RX[3]

N4

DMI_TX#[0]

R4

DMI_TX#[1]

P1

DMI_TX#[2]

U6

DMI_TX#[3]

N2

DMI_TX[0]

R2

DMI_TX[1]

P3

DMI_TX[2]

T5

DMI_TX[3]

V7

FDI0_TX#[0]

W8

FDI0_TX#[1]

AA8

FDI0_TX#[2]

AC10

FDI0_TX#[3]

U4

FDI1_TX#[0]

W2

FDI1_TX#[1]

V1

FDI1_TX#[2]

Y5

FDI1_TX#[3]

W6

FDI0_TX[0]

W10

FDI0_TX[1]

Y9

FDI0_TX[2]

AA10

FDI0_TX[3]

U2

FDI1_TX[0]

W4

FDI1_TX[1]

V3

FDI1_TX[2]

AA6

FDI1_TX[3]

AC8

FDI0_FSYNC

AA2

FDI1_FSYNC

AD9

FDI_INT

AB7

FDI0_LSYNC

AB3

FDI1_LSYNC

AC2

eDP_COMPIO

AB1

eDP_ICOMPO

AE8

eDP_HPD#

AE4

eDP_AUX

AE2

eDP_AUX#

AG4

eDP_TX[0]

AF3

eDP_TX[1]

AF7

eDP_TX[2]

AG8

eDP_TX[3]

AG2

eDP_TX#[0]

AF1

eDP_TX#[1]

AE6

eDP_TX#[2]

AG6

eDP_TX#[3]

AV8063801108003_BGA1224~D

E1@

3

PEG_COMP

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

G2 H1 F3

PEG_GTX_C_HRX_N15

F23

PEG_GTX_C_HRX_N14

H23

PEG_GTX_C_HRX_N13

H21

PEG_GTX_C_HRX_N12

H19

PEG_GTX_C_HRX_N11

J20

PEG_GTX_C_HRX_N10

G18

PEG_GTX_C_HRX_N9

K17

PEG_GTX_C_HRX_N8

F15

PEG_GTX_C_HRX_N7

H15

PEG_GTX_C_HRX_N6

H13

PEG_GTX_C_HRX_N5

H11

PEG_GTX_C_HRX_N4

J12

PEG_GTX_C_HRX_N3

E8

PEG_GTX_C_HRX_N2

G10

PEG_GTX_C_HRX_N1

J8

PEG_GTX_C_HRX_N0

F7

PEG_GTX_C_HRX_P15

G22

PEG_GTX_C_HRX_P14

K23

PEG_GTX_C_HRX_P13

K21

PEG_GTX_C_HRX_P12

F19

PEG_GTX_C_HRX_P11

K19

PEG_GTX_C_HRX_P10

H17

PEG_GTX_C_HRX_P9

K15

PEG_GTX_C_HRX_P8

G14

PEG_GTX_C_HRX_P7

J16

PEG_GTX_C_HRX_P6

K13

PEG_GTX_C_HRX_P5

F11

PEG_GTX_C_HRX_P4

K11

PEG_GTX_C_HRX_P3

F9

PEG_GTX_C_HRX_P2

H9

PEG_GTX_C_HRX_P1

H7

PEG_GTX_C_HRX_P0

G6

PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15

A22

PEG_HTX_GRX_N14 PEG_HTX_C_GRX_N14

B23

PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13

C18

PEG_HTX_GRX_N12 PEG_HTX_C_GRX_N12

D21

PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11

B19

PEG_HTX_GRX_N10 PEG_HTX_C_GRX_N10

E20

PEG_HTX_GRX_N9 PEG_HTX_C_GRX_N9

A14

PEG_HTX_GRX_N8 PEG_HTX_C_GRX_N8

D17

PEG_HTX_GRX_N7 PEG_HTX_C_GRX_N7

B15

PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6

E16

PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5

D13

PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4

A10

PEG_HTX_GRX_N3 PEG_HTX_C_GRX_N3

B11

PEG_HTX_GRX_N2 PEG_HTX_C_GRX_N2

D9

PEG_HTX_GRX_N1 PEG_HTX_C_GRX_N1

B7

PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0

E12

PEG_HTX_GRX_P15 PEG_HTX_C_GRX_P15

C22

PEG_HTX_GRX_P14 PEG_HTX_C_GRX_P14

D23

PEG_HTX_GRX_P13 PEG_HTX_C_GRX_P13

A18

PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12

B21

PEG_HTX_GRX_P11 PEG_HTX_C_GRX_P11

D19

PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10

F21

PEG_HTX_GRX_P9 PEG_HTX_C_GRX_P9

C14

PEG_HTX_GRX_P8 PEG_HTX_C_GRX_P8

B17

PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7

D15

PEG_HTX_GRX_P6 PEG_HTX_C_GRX_P6

F17

PEG_HTX_GRX_P5 PEG_HTX_C_GRX_P5

B13

PEG_HTX_GRX_P4 PEG_HTX_C_GRX_P4

C10

PEG_HTX_GRX_P3 PEG_HTX_C_GRX_P3

D11

PEG_HTX_GRX_P2 PEG_HTX_C_GRX_P2

B9

PEG_HTX_GRX_P1 PEG_HTX_C_GRX_P1

D7

PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0

F13

Typ- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

DMI Intel(R) FDI DP

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

RU1 24.9_0402_1%RU1 24.9_0402_1%

1 2

CU1 0.22U_0402_16V7K~DCU1 0.22U_0402_16V7K~D

1 2

CU2 0.22U_0402_16V7K~DCU2 0.22U_0402_16V7K~D

1 2

CU3 0.22U_0402_16V7K~DCU3 0.22U_0402_16V7K~D

1 2

CU4 0.22U_0402_16V7K~DCU4 0.22U_0402_16V7K~D

1 2

CU5 0.22U_0402_16V7K~DCU5 0.22U_0402_16V7K~D

1 2

CU6 0.22U_0402_16V7K~DCU6 0.22U_0402_16V7K~D

1 2

CU7 0.22U_0402_16V7K~DCU7 0.22U_0402_16V7K~D

1 2

CU8 0.22U_0402_16V7K~DCU8 0.22U_0402_16V7K~D

1 2

CU9 0.22U_0402_16V7K~DCU9 0.22U_0402_16V7K~D

1 2

CU10 0.22U_0402_16V7K~DCU10 0.22U_0402_16V7K~D

1 2

CU11 0.22U_0402_16V7K~DCU11 0.22U_0402_16V7K~D

1 2

CU12 0.22U_0402_16V7K~DCU12 0.22U_0402_16V7K~D

1 2

CU13 0.22U_0402_16V7K~DCU13 0.22U_0402_16V7K~D

1 2

CU14 0.22U_0402_16V7K~DCU14 0.22U_0402_16V7K~D

1 2

CU15 0.22U_0402_16V7K~DCU15 0.22U_0402_16V7K~D

1 2

CU16 0.22U_0402_16V7K~DCU16 0.22U_0402_16V7K~D

1 2

CU17 0.22U_0402_16V7K~DCU17 0.22U_0402_16V7K~D

1 2

CU18 0.22U_0402_16V7K~DCU18 0.22U_0402_16V7K~D

1 2

CU19 0.22U_0402_16V7K~DCU19 0.22U_0402_16V7K~D

1 2

CU20 0.22U_0402_16V7K~DCU20 0.22U_0402_16V7K~D

1 2

CU21 0.22U_0402_16V7K~DCU21 0.22U_0402_16V7K~D

1 2

CU22 0.22U_0402_16V7K~DCU22 0.22U_0402_16V7K~D

1 2

CU23 0.22U_0402_16V7K~DCU23 0.22U_0402_16V7K~D

1 2

CU24 0.22U_0402_16V7K~DCU24 0.22U_0402_16V7K~D

1 2

CU25 0.22U_0402_16V7K~DCU25 0.22U_0402_16V7K~D

1 2

CU26 0.22U_0402_16V7K~DCU26 0.22U_0402_16V7K~D

1 2

CU27 0.22U_0402_16V7K~DCU27 0.22U_0402_16V7K~D

1 2

CU28 0.22U_0402_16V7K~DCU28 0.22U_0402_16V7K~D

1 2

CU29 0.22U_0402_16V7K~DCU29 0.22U_0402_16V7K~D

1 2

CU30 0.22U_0402_16V7K~DCU30 0.22U_0402_16V7K~D

1 2

CU31 0.22U_0402_16V7K~DCU31 0.22U_0402_16V7K~D

1 2

CU32 0.22U_0402_16V7K~DCU32 0.22U_0402_16V7K~D

1 2

+VCCP

2

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

PEG_GTX_C_HRX_N[0..15]

PEG_GTX_C_HRX_P[0..15]

PEG_HTX_C_GRX_N[0..15]

PEG_HTX_C_GRX_P[0..15]

1

PEG_GTX_C_HRX_N[0..15] (24)

PEG_GTX_C_HRX_P[0..15] (24)

PEG_HTX_C_GRX_N[0..15] (24)

PEG_HTX_C_GRX_P[0..15] (24)

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

of

7 66Monday, March 26, 2012

1

7 66Monday, March 26, 2012

0.1

5

4

3

2

1

This pin is for compability with future platforms. A pull up resistor to VCCIO is required if connected to the DF_TVS strap on the PCH.

H_SNB_IVB#(20)

PROC_DETECT (Processor Detect): pulled to ground on the processor package. There is no connection to the processor silicon for this

D D

Processor Pullups

+VCCP

RU30 62_0402_5%RU30 62_0402_5%

1 2

place RU32,RU30 near CPU

C C

RU33 10K_0402_5%~DRU33 10K_0402_5%~D

1 2

signal. System board designers may use this signal to determine if the processor is present

H_PECI(20,38)

H_PROCHOT#(38,53)

H_PROCHOT#

H_CPUPWRGD

H_THERMTRIP#(20)

H_PM_SYNC(18)

H_CPUPWRGD(6,20)

H_PROCHOT#

RU43 130_0402_5%RU43 130_0402_5%

ST

RU34 0_0402_5%~D

1 2

S3 circuit:- DRAM_RST# to memory should be high during S3

RU116 0_0402_5%~D@ RU116 0_0402_5%~D@

1 2

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

RU74

4.99K_0402_1%~D

12

G

PT

13

QU3

2

BSS138-G_SOT23-3

RU26 10K_0402_5%~D@RU26 10K_0402_5%~D@

1 2

T1 PAD@ T1 PAD@

ST

RU31 0_0402_5%~D

SHORT

RU31 0_0402_5%~D

SHORT

1 2

RU32 56_0402_5%RU32 56_0402_5%

1 2

SHORT

1 2

PM_SYS_PWRGD_BUF_RPM_SYS_PWRGD_BUF

+1.5V

12

RU72

RU72 1K_0402_5%~D

1K_0402_5%~D

RU73 1K_0402_5%~DRU73 1K_0402_5%~D

1 2

H_CATERR#

H_PECI_ISO

H_PROCHOT#_R

H_THERMTRIP#_R

H_PM_SYNC

H_CPUPWRGD

BUF_CPU_RST#

UU1B

AH9

PROC_SELECT#

B59

PROC_DETECT#

H53

CATERR#

F53

PECI

H51

PROCHOT#

F51

THERMTRIP#

K53

PM_SYNC

C60

UNCOREPWRGOOD

AY25

SM_DRAMPWR OK

K51

RESET#

AV8063801108003_BGA1224~D

DDR3_DRAMRST# (14,15)

CLK_CPU_DMI

D5

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TCK

TDI

CLK_CPU_DMI#

C6

DPLL_REF_CLK

AJ4

DPLL_REF_CLK#

AJ2

K63 K65

H_DRAMRST#

BE24

SM_RCOMP0

BJ46

SM_RCOMP1

BG46

SM_RCOMP2

BF45

XDP_PRDY#

J62

XDP_PREQ#

H65

XDP_TCK

J58

XDP_TMS

H59

XDP_TRST#

H63

XDP_TDI_R

K61

XDP_TDO_R

K59

XDP_DBRESET#_R

H61

XDP_BPM#0_R

C62

XDP_BPM#1_R

D61

XDP_BPM#2_R

E62

XDP_BPM#3_R

F63

XDP_BPM#4_R

D59

XDP_BPM#5_R

F61

XDP_BPM#6_R

F59

XDP_BPM#7_R

G60

XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

RU38 0_0402_5%~D@RU38 0_0402_5%~D@ RU39 0_0402_5%~D@RU39 0_0402_5%~D@

RU41 0_0402_5%~D@RU41 0_0402_5%~D@

RU3 0_0402_5%~D@RU3 0_0402_5%~D@ RU4 0_0402_5%~D@RU4 0_0402_5%~D@ RU5 0_0402_5%~D@RU5 0_0402_5%~D@ RU6 0_0402_5%~D@RU6 0_0402_5%~D@ RU49 0_0402_5%~D@RU49 0_0402_5%~D@ RU51 0_0402_5%~D@RU51 0_0402_5%~D@ RU53 0_0402_5%~D@RU53 0_0402_5%~D@ RU56 0_0402_5%~D@RU56 0_0402_5%~D@

RU11 0_0402_5%~D@RU11 0_0402_5%~D@ RU15 0_0402_5%~D@RU15 0_0402_5%~D@ RU16 0_0402_5%~D@RU16 0_0402_5%~D@ RU17 0_0402_5%~D@RU17 0_0402_5%~D@

XDP_PRDY# (6) XDP_PREQ# (6)

XDP_TCK (6) XDP_TMS (6) XDP_TRST# (6)

1 2 1 2

1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2

CLK_CPU_DMI (17) CLK_CPU_DMI# (17)

CLK_RES_ITP (17) CLK_RES_ITP# (17)

XDP_DBRESET#

XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

CFG12 (10) CFG13 (10) CFG14 (10) CFG15 (10)

DPLL_REF_CLK#

DPLL_REF_CLK

If motherboard only supports external graphics or if it supports Processor Graphics but without eDP

XDP_DBRESET#

XDP_TDI (6) XDP_TDO (6)

XDP_DBRESET# (6,18)

XDP_BPM#0 (6) XDP_BPM#1 (6) XDP_BPM#2 (6) XDP_BPM#3 (6) XDP_BPM#4 (6) XDP_BPM#5 (6) XDP_BPM#6 (6) XDP_BPM#7 (6)

RU24 1K_0402_5%~DRU24 1K_0402_5%~D

1 2

RU23 1K_0402_5%~DRU23 1K_0402_5%~D

1 2

RU35 1K_0402_5%~DRU35 1K_0402_5%~D

1 2

+VCCP

+3VS

B B

DRAMRST_CNTRL_PC H(14,17)

SM_DRAMPWROK

CPU1.5V_S3_GATE(12,38,57)

PM_DRAM_PWR GD(18)

A A

SSI2

+3V_PCH

RU76 200_0402_5%RU76 200_0402_5%

1 2

ST

RU75 0_0402_5%~D

RU62

0_0402_5%~D

SHORT

1 2

5

SHORT

1 2

ST

DRAMRST_CNTRL

SSI2

+3V_PCH

UU3

5

74AHC1G09GW_TSSOP5

1

P

B

O

2

A

G

3

RU71 0_0402_5%~D@RU71 0_0402_5%~D@

1 2

RUN_ON_CPU1.5VS3#(12,34)

1

CU39

0.047U_0402_16V7K

2

1

CU37

0.1U_0402_25V6K~D

2

PM_SYS_PWRGD_BUF

4

PT

+1.5V_CPU_VDDQ

12

RU60

RU60 200_0402_5%

200_0402_5%

12

RU64

@RU64

@

39_0402_5%

13

D

2

G

S

QU2

@

QU2

@

2N7002_SOT23-3~D

4

Buffered reset to CPU

PLT_RST#(6,19,38,40,41,42)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PLT_RST#

3

+3VS +VCCP

1

CU35

0.1U_0402_25V6K~D

2

5

UU2

1

P

NC

4

Y

2

A

G

PT

3

SN74LVC1G07DCKR_SC70-5

2011/08/25 2012/07/25

12

RU42

RU42 75_0402_5%

75_0402_5%

RU48 43_0402_1%RU48 43_0402_1%

Compal Secret Data

Deciphered Date

1 2

12

2

BUF_CPU_RST#

RU55

@RU55

@

0_0402_5%~D

DDR3 Compensation Signals

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

RU58 140_0402_1%RU58 140_0402_1%

1 2

RU59 25.5_0402_1%RU59 25.5_0402_1%

1 2

RU61 200_0402_1%RU61 200_0402_1%

1 2

PU/PD for JTAG signals

XDP_PREQ#

XDP_TMS

XDP_TDI_RBUFO_CPU_RST#

XDP_TDO_R

XDP_TCK

XDP_TRST#

Compal Electronics, Inc.

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

Date: Sheet of

RU69 51_0402_5%@ RU69 51_0402_5%@

1 2

RU63 51_0402_5%RU63 51_0402_5%

1 2

RU65 51_0402_5%RU65 51_0402_5%

1 2

RU66 51_0402_5%RU66 51_0402_5%

1 2

RU67 51_0402_5%RU67 51_0402_5%

1 2

RU68 51_0402_5%RU68 51_0402_5%

1 2

1

+VCCP

8 66Monday, March 26, 2012

0.1

5

UU1C

DDR_A_D[0..63](14)

D D

C C

DDR_A_BS0(14)

B B

DDR_A_BS1(14) DDR_A_BS2(14)

DDR_A_CAS#(14) DDR_A_RAS#(14) DDR_A_WE#(14)

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UU1C

AL6

SA_DQ[0]

AL8

SA_DQ[1]

AP7

SA_DQ[2]

AM5

SA_DQ[3]

AK7

SA_DQ[4]

AL10

SA_DQ[5]

AN10

SA_DQ[6]

AM9

SA_DQ[7]

AR10

SA_DQ[8]

AR8

SA_DQ[9]

AV7

SA_DQ[10]

AY5

SA_DQ[11]

AT5

SA_DQ[12]

AR6

SA_DQ[13]

AW6

SA_DQ[14]

AT9

SA_DQ[15]

BA6

SA_DQ[16]

BA8

SA_DQ[17]

BG6

SA_DQ[18]

AY9

SA_DQ[19]

AW8

SA_DQ[20]

BB7

SA_DQ[21]

BC8

SA_DQ[22]

BE4

SA_DQ[23]

AW12

SA_DQ[24]

AV11

SA_DQ[25]

BB11

SA_DQ[26]

BA12

SA_DQ[27]

BE8

SA_DQ[28]

BA10

SA_DQ[29]

BD11

SA_DQ[30]

BE12

SA_DQ[31]

BB49

SA_DQ[32]

AY49

SA_DQ[33]

BE52

SA_DQ[34]

BD51

SA_DQ[35]

BD49

SA_DQ[36]

BE48

SA_DQ[37]

BA52

SA_DQ[38]

AY51

SA_DQ[39]

BC54

SA_DQ[40]

AY53

SA_DQ[41]

AW54

SA_DQ[42]

AY55

SA_DQ[43]

BD53

SA_DQ[44]

BB53

SA_DQ[45]

BE56

SA_DQ[46]

BA56

SA_DQ[47]

BD57

SA_DQ[48]

BF61

SA_DQ[49]

BA60

SA_DQ[50]

BB61

SA_DQ[51]

BE60

SA_DQ[52]

BD63

SA_DQ[53]

BB59

SA_DQ[54]

BC58

SA_DQ[55]

AW58

SA_DQ[56]

AY59

SA_DQ[57]

AL60

SA_DQ[58]

AP61

SA_DQ[59]

AW60

SA_DQ[60]

AY57

SA_DQ[61]

AN60

SA_DQ[62]

AR60

SA_DQ[63]

BA36

SA_BS[0]

BC38

SA_BS[1]

BB19

SA_BS[2]

BE44

SA_CAS#

BE36

SA_RAS#

BA44

SA_WE#

AV8063801108003_BGA1224~D

SA_DIMM_VREFDQ

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

4

BB31 BA32 BC18

AW34 AY33 BD17

BD41 BD45

BB41 BC46

BF3

AN8 AU6 BC6 BD9 BC50 BB55 BD59 AU60

AN6 AU8 BD5 BC10 BB51 BD55 BD61 AV61

BD27 BA28 BB27 AW26 BB23 BA24 AY21 BD21 BC22 BB21 AW38 AW22 BA20 BB45 BE20 AW18

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 (14) M_CLK_DDR#0 (14) DDR_CKE0_DIMMA (14)

M_CLK_DDR1 (14) M_CLK_DDR#1 (14) DDR_CKE1_DIMMA (14)

DDR_CS0_DIMMA# (14) DDR_CS1_DIMMA# (14)

M_ODT0 (14) M_ODT1 (14)

+V_DDR_REFA_R (14)

DDR_A_DQS#[0..7] (14)

DDR_A_DQS[0..7] (14)

DDR_A_MA[0..15] (14)

M3

3

DDR_B_D[0..63](15)

DDR_B_BS0(15) DDR_B_BS1(15) DDR_B_BS2(15)

DDR_B_CAS#(15) DDR_B_RAS#(15) DDR_B_WE#(15)

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

BF11

BJ10

BH11 BG10

BJ14 BG14 BF17

BJ18 BF13 BH13 BH17 BG18 BH49 BF47 BH53 BG50 BF49 BH47 BF53

BJ50 BF55 BH55

BJ58 BH59

BJ54 BG54 BG58 BF59 BA64 BC62 AU62

AW64

BA62 BC64 AU64

AW62

AR64 AT65

AL64

AM65

AR62 AT63

AL62

AM63

BJ38 BD37 AY29

BH39 BG38 BF39

AK3 AP3 AR2 AL2 AK1 AP1 AR4 AV3 AU4 BA4 BB1 AV1 AU2 BA2 BB3 BC2 BF7

BC4 BH7

AL4

2

UU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

AV8063801108003_BGA1224~D

SB_CLK#[0]

SB_CKE[0]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0] SB_CS#[1]

SB_ODT[0] SB_ODT[1]

SB_OIMM_VREFDQ

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

SB_CK[0]

SB_CK[1]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9]

BF33 BH33 BD25

BF37 BH37 BJ26

BE40 BH41

BG42 BH45

BG4

AN4 AW2 BH9 BF15 BF51 BH57 AY63 AN62

AN2 AW4 BF9 BH15 BH51 BF57 AY65 AN64

BF31 BH31 BB37 BC34 BF27 BB33 BH27 BG30 BH29 BF29 AY37 BJ30 AW30 BA40 BB29 BE28

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

1

M_CLK_DDR2 (15) M_CLK_DDR#2 (15) DDR_CKE2_DIMMB (15)

M_CLK_DDR3 (15) M_CLK_DDR#3 (15) DDR_CKE3_DIMMB (15)

DDR_CS2_DIMMB# (15) DDR_CS3_DIMMB# (15)

M_ODT2 (15) M_ODT3 (15)

+V_DDR_REFB_R (14)

DDR_B_DQS#[0..7] (15)

DDR_B_DQS[0..7] (15)

DDR_B_MA[0..15] (15)

M3

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

1

0.1

9 66Monday, March 26, 2012

0.1

5

4

3

2

1

CFG Straps for Processor

CFG2

UU1E

D D

C C

B B

CFG0(6)

CFG10(6) CFG11(6) CFG12(8) CFG13(8) CFG14(8) CFG15(8)

T17 PAD@T17 PAD@

T18 PAD@T18 PAD@

T24 PAD@T24 PAD@ T25 PAD@T25 PAD@

T26 PAD@T26 PAD@ T27 PAD@T27 PAD@

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

BB17 AY17 BD29 BD33 BC30

BE32

AW42

BA48 BC42

AW46

BG26 BB25 BG34 BH35

BJ34 BF35 BF41 BH43 BJ42 BF43

AW50

BB57 BF63

BD19

AY45 AY41 BG62 BB43

AJ10

D57 B55 A54 A58 D55 C56 E54

G56 F55 K55 F57 E58 H57 H55 D53 K57

AD5 AH5 AJ6

D49 B53

G52 G64

BE6 AA4 AC4 AC6 C52

C24 D25 B25 K47 H47

B57

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7]

J54

CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20

RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27

RSVD30

RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36

RSVD38 RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

D3

RSVD46

C4

RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52

VCC_VAL_SENSE

VSS_VAL_SENSE

VAXG_VAL_SENSE

VSSAXG_VAL_SENSE

VCC_DIE_SENSE

RESERVED

DC_TEST_A4 DC_TEST_A62 DC_TEST_A64

DC_TEST_B3 DC_TEST_B63 DC_TEST_B65 DC_TEST_BF1

DC_TEST_BF65

DC_TEST_BG2

DC_TEST_BG64

DC_TEST_BH1 DC_TEST_BH3

DC_TEST_BH63 DC_TEST_BH65

DC_TEST_BJ2

DC_TEST_BJ4 DC_TEST_BJ62 DC_TEST_BJ64

DC_TEST_C2

DC_TEST_C64

DC_TEST_D1

DC_TEST_D65

RSVD53 RSVD54 RSVD55 RSVD56 RSVD57 RSVD58 RSVD59 RSVD60 RSVD61 RSVD62 RSVD63 RSVD64 RSVD65 RSVD66 RSVD67 RSVD68

RSVD69 RSVD70 RSVD71 RSVD72

RSVD78 RSVD79 RSVD80 RSVD81 RSVD82 RSVD83 RSVD84 RSVD85 RSVD86 RSVD87 RSVD88 RSVD89 RSVD90 RSVD91 RSVD92 RSVD93 RSVD94 RSVD95 RSVD96 RSVD97

F5 K9 H5 L10 G4 K7 K5 M9 L6 J2 L2 P7 M5 J4 L4 N6

G48 K49 H49 J50

D47 C48

B49 A48

VCC_DIE_SENSE

F47

AY13 BB13 BB15 AY15 AW14 BD13 BA16 BE16 BD15 BC14 BF19 BH19 BF21 BH21 BF23 BH23 BF25 BH25 BJ22 BG22

A4 A62

DC_TEST_B63_A64

A64

DC_TEST_B3_C2

B3 B63

DC_TEST_B65_C64

B65 BF1 BF65

DC_TEST_BH1_BG2

BG2

DC_TEST_BG64_BH65

BG64 BH1

DC_TEST_BH3_BJ2

BH3

DC_TEST_BH63_BJ64

BH63 BH65 BJ2 BJ4 BJ62 BJ64 C2 C64 D1 D65

T33PAD @T33PAD @

Intel suggestion

T40PAD @T40PAD @

Those signals should be leave to NC and recommend

T41PAD @T41PAD @ T42PAD @T42PAD @

for test pins

12

RU120

@RU120

@

0_0402_5%~D

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

*

Display Port Presence Strap

CFG4

*

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

12

RU77

RU77 1K_0402_1%~D

1K_0402_1%~D

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

CFG4

12

RU115

@RU115

@

1K_0402_1%~D

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

PT

12

RU85

SB@RU85

SB@

1K_0402_1%~D

12

RU86

@RU86

@

1K_0402_1%~D

RU85 just for Sandy bridge PEG x8

CFG7

12

RU87

@RU87

@

1K_0402_1%~D

PT

AV8063801108003_BGA1224~D

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

0: PEG Wait for BIOS for training

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

10 66Monday, March 26, 2012

1

10 66Monday, March 26, 2012

0.1

5

D D

C C

B B

A A

4

UU1F

53A

+VCC_CORE

A26

VCC1

A28

VCC2

A32

VCC3

A34

VCC4

A38

VCC5

A40

VCC6

A44

VCC7

B29

VCC8

B31

VCC9

B35

VCC10

B37

VCC11

B41

VCC12

B43

VCC13

B45

VCC14

C26

VCC15

C28

VCC16

C32

VCC17

C34

VCC18

C38

VCC19

C40

VCC20

C44

VCC21

D29

VCC22

D31

VCC23

D35

VCC24

D37

VCC25

D41

VCC26

D43

VCC27

D45

VCC28

E26

VCC29

E28

VCC30

E32

VCC31

E34

VCC32

E38

VCC33

E40

VCC34

E44

VCC35

F25

VCC36

F29

VCC37

F31

VCC38

F35

VCC39

F37

VCC40

F41

VCC41

F43

VCC42

F45

VCC43

G26

VCC44

G28

VCC45

G32

VCC46

G34

VCC47

G38

VCC48

G40

VCC49

G44

VCC50

H25

VCC51

H29

VCC52

H31

VCC53

H35

VCC54

H37

VCC55

H41

VCC56

H43

VCC57

H45

VCC58

J26

VCC59

J28

VCC60

J32

VCC61

J34

VCC62

J38

VCC63

J40

VCC64

J44

VCC65

K25

VCC66

K29

VCC67

K31

VCC68

K35

VCC69

K37

VCC70

K41

VCC71

K43

VCC72

K45

VCC73

L22

VCC74

L26

VCC75

L28

VCC76

L32

VCC77

L34

VCC78

L38

VCC79

L40

VCC80

L44

VCC81

M21

VCC82

M23

VCC83

M27

VCC84

M29

VCC85

M34

VCC86

M36

VCC87

M40

VCC88

M42

VCC89

M46

VCC90

N20

VCC91

N24

VCC92

N26

VCC93

N30

VCC94

N33

VCC95

N37

VCC96

N39

VCC97

N43

VCC98

N45

VCC99

R21

VCC100

R23

VCC101

R27

VCC102

R29

VCC103

R34

VCC104

R36

VCC105

R40

VCC106

R42

VCC107

R46

VCC108

AV8063801108003_BGA1224~D

3

CORE SUPPLY

PEG AND DDR

POWER

SVID QUIET RAILS

VSS_SENSE_VCCIO

SENSE LINES

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40 VCCIO41 VCCIO42

VCCIO43 VCCIO44 VCCIO45 VCCIO46 VCCIO47 VCCIO48 VCCIO49 VCCIO50 VCCIO51 VCCIO52 VCCIO53 VCCIO54 VCCIO55 VCCIO56 VCCIO57 VCCIO58 VCCIO59 VCCIO60 VCCIO61 VCCIO62 VCCIO63

VCCIO64 VCCIO65 VCCIO66

VCCPQE1 VCCPQE2 VCCPQE3 VCCPQE4

VCCIO_SEL

VIDALERT#

VIDSCLK

VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

+VCCP

AK56 AK58 AL15 AL17 AL48 AL53 AL55 AN14 AN16 AN18 AN20 AN49 AN52 AN56 AN58 AP48 AP53 AP55 AR14 AR16 AR18 AR20 AR49 AR52 AR56 AR58 AT15 AT17 AT48 AT53 AT55 AU18 AU20 AU49 AU52 AU56 AU58 AV15 AV17 AV48 AV53 AV55

AB14 AB16 AC12 AC15 AC17 AD11 AE12 AE15 AE17 AF14 AF16 AH11 AH14 AH16 AJ12 AJ15 AJ17 AL12 AM11 AT12 AV12

Y11 Y14 Y16

AL21 AP21 AT21 AV21

VCCP_PWRCTRL_R

AJ8

B51

VR_SVID_CLK

D51

VR_SVID_DAT

A50

VCCSENSE_R

B47

VSSSENSE_R

A46

AW10

VSSIO_SENSE

AU10

+1.05V

+1.05VS_VCCPQ

2

8.5A

ST

RU88 0_0603_5%~DSHORTRU88 0_0603_5%~DSHORT

1 2

1

CU122

CU122 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

RU93 43_0402_1%RU93 43_0402_1%

1 2

ST

RU97 0_0402_5%~D

SHORT

1 2

RU98 0_0402_5%~D

SHORT

1 2

ST

RU100 0_0402_5%~D

SHORT

1 2

RU101 10_0402_1%~DRU101 10_0402_1%~D

1 2

VCCIO_SENSE

1

+VCCP

RU91 75_0402_5%RU91 75_0402_5%

+VCC_CORE

VCCIO_SENSE (56) VSSIO_SENSE (56)

1 2

VCCSENSE (59) VSSSENSE (59)

1 2

VR_SVID_ALRT#

VR_SVID_DAT

VR_SVID_ALRT# (59) VR_SVID_CLK (59) VR_SVID_DAT (59)

+VCCP

T14PAD @T14PAD @ RU90 130_0402_5%RU90 130_0402_5%

VR_SVID_ALRT#H_CPU_SVIDALRT#

RU96 100_0402_1%~DRU96 100_0402_1%~D

RU99 100_0402_1%~DRU99 100_0402_1%~D

VCCIO_SENSEVCCIO_SENSE_R

RU104 10_0402_1%~DRU104 10_0402_1%~D

1 2

+VCCP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

11 66Monday, March 26, 2012

1

0.1

5

4

3

2

1

+V_SM_VREF should

33A

+VCC_GFXCORE_AXG

D D

C C

+VCC_GFXCORE_AXG

RU103 100_0402_1%~DRU103 100_0402_1%~D

B B

VCC_AXG_SENSE(59) VSS_AXG_SENSE(59)

+1.8VS

ST

1.2A

RU111 0_0805_5%~DSHORTRU111 0_0805_5%~DSHORT

1 2

+VCCSA

6A

1

+

CU215

CU215 330U_D2_2V_Y

330U_D2_2V_Y

2

A A

5

1

CU207

10U_0603_6.3V6M~D

2

1

2

1U_0402_6.3V6K~D

CU216

1

2

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1 2

ST

RU108 0_0402_5%~D

SHORT

1 2

RU109 0_0402_5%~D

SHORT

1 2

RU112 100_0402_1%~DRU112 100_0402_1%~D

1 2

1

CU205

1U_0402_6.3V6K~D

2

+VCCSA

10U_0603_6.3V6M~D

1

CU211

2

CU217

1

2

CU213

CU212

2

1U_0402_6.3V6K~D

@

CU219

CU218

1

2

+1.8VS_VCCPLL_R

1

CU206

1U_0402_6.3V6K~D

2

10U_0603_6.3V6M~D

1

@

CU214

2

1U_0402_6.3V6K~D

@

CU220

1

2

UU1G

AA60

VAXG1

AA62

VAXG2

AA64

VAXG3

AB56

VAXG4

AB58

VAXG5

AB61

VAXG6

AB63

VAXG7

AB65

VAXG8

AD56

VAXG9

AD58

VAXG10

AD61

VAXG11

AD63

VAXG12

AD65

VAXG13

AE60

VAXG14

AE62

VAXG15

AE64

VAXG16

AF56

VAXG17

AF58

VAXG18

AG60

VAXG19

AG62

VAXG20

AG64

VAXG21

AH56

VAXG22

AH58

VAXG23

AH61

VAXG24

AH63

VAXG25

AH65

VAXG26

L48

VAXG27

L52

VAXG28

L56

VAXG29

M48

VAXG30

M53

VAXG31

M55

VAXG32

M59

VAXG33

M61

VAXG34

M63

VAXG35

M65

VAXG36

N49

VAXG37

N52

VAXG38

N56

VAXG39

N58

VAXG40

N60

VAXG41

N62

VAXG42

N64

VAXG43

R48

VAXG44

R53

VAXG45

R55

VAXG46

R60

VAXG47

R62

VAXG48

R64

VAXG49

T56

VAXG50

T58

VAXG51

T61

VAXG52

T63

VAXG53

T65

VAXG54

V56

VAXG55

V58

VAXG56

V61

VAXG57

V63

VAXG58

V65

VAXG59

W60

VAXG60

W62

VAXG61

W64

VAXG62

Y56

VAXG63

Y58

VAXG64

F49

VAXG_SENSE

E50

VSSAXG_SENSE

AK61

VCCPLL1

AK63

VCCPLL2

AK65

VCCPLL3

L14

VCCSA1

L18

VCCSA2

M11

VCCSA3

M12

VCCSA4

M15

VCCSA5

M17

VCCSA6

N14

VCCSA7

N16

VCCSA8

N18

VCCSA9

T11

VCCSA10

T14

VCCSA11

T16

VCCSA12

U12

VCCSA13

U15

VCCSA14

U17

VCCSA15

W12

VCCSA16

W15

VCCSA17

W17

VCCSA18

AV8063801108003_BGA1224~D

4

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VDDQ19 VDDQ20 VDDQ21 VDDQ22 VDDQ23 VDDQ24 VDDQ25 VDDQ26 VDDQ27 VDDQ28 VDDQ29

DDR3 - 1.5V RAILS

SENSE

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0]

VDDQ30 VDDQ31 VDDQ32 VDDQ33 VDDQ34 VDDQ35 VDDQ36 VDDQ37 VDDQ38 VDDQ39 VDDQ40 VDDQ41 VDDQ42 VDDQ43 VDDQ44 VDDQ45 VDDQ46 VDDQ47 VDDQ48 VDDQ49 VDDQ50 VDDQ51 VDDQ52 VDDQ53 VDDQ54 VDDQ55 VDDQ56 VDDQ57 VDDQ58 VDDQ59 VDDQ60 VDDQ61 VDDQ62 VDDQ63 VDDQ64 VDDQ65 VDDQ66 VDDQ67 VDDQ68 VDDQ69

VCCDQ1 VCCDQ2 VCCDQ3 VCCDQ4

VCCSA_VID[1]

GRAPHICS

POWER

LINES

1.8V RAIL

SA RAIL

have 20 mil trace width

BJ44

AL27 AL29 AL34 AL36 AL40 AL42 AL46 AN24 AN26 AN30 AN33 AN37 AN39 AN43 AN45 AP27 AP29 AP34 AP36 AP40 AP42 AP46 AR24 AR26 AR30 AR33 AR37 AR39 AR43 AR45 AT27 AT29 AT34 AT36 AT40 AT42 AT46 AU24 AU26 AU30 AU33 AU37 AU39 AU43 AU45 AV27 AV29 AV34 AV36 AV40 AV42 AV46 AY23 AY27 AY31 AY35 AY39 AY43 AY47 BB35 BD23 BD31 BD39 BD43 BD47 BG32 BG40 BJ28 BJ36

AL23 AP23 AT23 AV23

AY19 AW20

+VCCSA_SENSE

K3

RU114 0_0402_5%~D@RU114 0_0402_5%~D@

H_VCCSA_VID0

AE10

H_VCCSA_VID1

AG10

+SM_VREF

+1.5V_CPU_VDDQ

10U_0603_6.3V6M~D

1

2

1U_0402_6.3V6K~D

CU192

1

2

ST

1 2

3

1

0.1U_0402_25V6K~D

2

1

CU169

2

1U_0402_6.3V6K~D

@

CU193

Security Classification

+1.5V_CPU_VDDQ

12

RU83

@RU83

@

1K_0402_1%~D

RU117 0_0402_5%~D@RU117 0_0402_5%~D@

1 2

1

3

QU4 AP2302GN-HF_SOT23-3~D@QU4 AP2302GN-HF_SOT23-3~D@

RU84

1

2

10U_0603_6.3V6M~D

1

CU173

2

1U_0402_6.3V6K~D

CU197

1

2

RUN_ON_CPU1.5VS3

+0.75VS

+1.5V_CPU_VDDQ

10U_0603_6.3V6M~D

1

2

2011/08/25 2012/07/25

10U_0603_6.3V6M~D

1

CU174

2

1U_0402_6.3V6K~D

CU198

1

2

1

@

CU176

CU175

2

+1.5V_CPU_VDDQ

1U_0402_6.3V6K~D

CU199

1

2

CPU1.5V_S3_GATE(8,38,57)

Compal Secret Data

1

+

2

1U_0402_6.3V6K~D

CU200

330U_D2_2V_Y

CU168

1U_0402_6.3V6K~D

@

CU201

1

2

Deciphered Date

SHORT

1 2

12

@RU84

@

1K_0402_1%~D

CU154

ST

RU118 0_0402_5%~D

5A

10U_0603_6.3V6M~D

CU171

1U_0402_6.3V6K~D

1

2

1

CU172

2

1U_0402_6.3V6K~D

CU195

1

2

+1.5V_CPU_VDDQ

CU208

1

2

CU196

1

CU170

2

1U_0402_6.3V6K~D

CU194

1

2

1U_0402_6.3V6K~D

+VCCSA_SENSE (58)

H_VCCSA_VID0 (58) H_VCCSA_VID1 (58)

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

+V_DDR_REFA

2

+1.5V_CPU_VDDQ

12

RU107

RU107 100K_0402_5%~D

100K_0402_5%~D

RUN_ON_CPU1.5VS3#

61

QU5A

2N7002DW-7-F_SOT363-6

+1.5V

ST

CU177 0.1U_0402_10V7K~DCU177 0.1U_0402_10V7K~D

12

CU178 0.1U_0402_10V7K~DCU178 0.1U_0402_10V7K~D

12

CU179 0.1U_0402_10V7K~DCU179 0.1U_0402_10V7K~D

12

CU191 0.1U_0402_10V7K~DCU191 0.1U_0402_10V7K~D

12

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

6720mA

QU6

AO4728L_SO8~D

+VSBP+3VALW

12

RU105

RU105 100K_0402_5%~D

100K_0402_5%~D

RUN_ON_CPU1.5VS3

3

QU5B

5

2N7002DW-7-F_SOT363-6

4

RUN_ON_CPU1.5VS3# (8,34)

Compal Electronics, Inc.

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

8 7 6 5

12

RU110

RU110 330K_0402_1%

330K_0402_1%

1

AO4728L_SO8~D

1 2 3

4

1

CU204

0.1U_0603_50V_X7R

2

of

12 66Monday, March 26, 2012

0.1

5

UU1H

4

3

2

UU1I

1

BE42

VSS181

A12

VSS1

A16

AA12 AA15 AA17 AA57 AB11

AC57 AC60 AC62 AC64

AD14 AD16

AE57 AF11

AF61 AF63 AF65

AG12 AG15 AG17 AG57

AJ57 AJ60 AJ62

AJ64 AK11 AK14 AK16

AL19

AL25

AL31

AL38

AL44

AL50

AL57

AM61

AN22 AN28 AN35 AN41 AN47 AN54 AP11 AP12 AP15 AP17 AP19 AP25 AP31 AP38 AP44

AP50 AP57 AP63 AP65

AR22 AR28 AR35 AR41 AR47 AR54

AT11 AT19

AM1 AM3

AM7

A20 A24 A30 A36 A42 A52 A56

AB5 AB9

AD1

AD3 AD7

AF5

AF9

AH1 AH3 AH7

AK5 AK9

AP5

AP9

AT1

VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

A8

VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90

VSS

D D

C C

B B

VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180

AT25 AT3 AT31 AT38 AT44 AT50 AT57 AT61 AT7 AU14 AU16 AU22 AU28 AU35 AU41 AU47 AU54 AV19 AV25 AV31 AV38 AV44 AV5 AV50 AV57 AV59 AV63 AV65 AV9 AW16 AW24 AW28 AW32 AW36 AW40 AW44 AW48 AW52 AW56 AY1 AY11 AY3 AY61 AY7 B27 B33 B39 BA14 BA18 BA22 BA26 BA30 BA34 BA38 BA42 BA46 BA50 BA54 BA58 BB39 BB47 BB5 BB63 BB65 BB9 BC12 BC16 BC20 BC24 BC26 BC28 BC32 BC36 BC40 BC44 BC48 BC52 BC56 BC60 BD3 BD35 BD7 BE10 BE14 BE18 BE22 BE26 BE30 BE34 BE38

VSSG_DIE_SENSE

12

RU119

RU119 0_0402_5%~D

0_0402_5%~D

@

BE46 BE50 BE54 BE58 BE62

BG12 BG16 BG20 BG24 BG28 BG36 BG44 BG48 BG52 BG56 BG60

BJ12 BJ16 BJ20 BJ24 BJ32 BJ40 BJ48 BJ52 BJ56

BF5

BG8

C12 C16 C20 C30 C36 C42 C46 C50 C54 C58

D27 D33 D39 D63 E10 E14 E18 E22 E24 E30 E36

E42 E46 E48 E52 E56

E60

G12 G16 G20 G24 G30 G36 G42 G46 G50 G54 G58 G62

H27

H33 H39

VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208

BJ8

VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219

C8

VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231

E4

VSS232 VSS233 VSS234 VSS235 VSS236 VSS237

E6

VSS238 VSS239

F27

VSS240

F33

VSS241

F39

VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254

G8

VSS255 VSS256

H3

VSS257 VSS258 VSS259

J10

VSS260

J14

VSS261

J18

VSS262

J22

VSS263

J24

VSS264

J30

VSS265

J36

VSS266

J42

VSS267

J46

VSS268

J48

VSS269

J52

VSS270

VSS

VSS_NCTF10 VSS_NCTF11 VSS_NCTF12 VSS_NCTF13 VSS_NCTF14 VSS_NCTF15 VSS_NCTF16

VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286 VSS287 VSS288 VSS289 VSS290 VSS291 VSS292 VSS293 VSS294 VSS295 VSS296 VSS297 VSS298 VSS299 VSS300 VSS301 VSS302 VSS303 VSS304 VSS305 VSS306 VSS307 VSS308 VSS309 VSS310 VSS311 VSS312 VSS313 VSS314 VSS315 VSS316 VSS317 VSS318 VSS319 VSS320 VSS321 VSS322 VSS323 VSS324 VSS325 VSS326 VSS327 VSS328 VSS329 VSS330 VSS331 VSS332 VSS333 VSS334 VSS335 VSS336 VSS337 VSS338 VSS339 VSS340 VSS341 VSS342 VSS343 VSS344

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9

J56 J6 J60 J64 K1 K27 K33 K39 L12 L16 L20 L24 L30 L36 L42 L46 L50 L54 L58 L60 L62 L64 L8 M1 M19 M25 M3 M31 M38 M44 M50 M57 M7 N22 N28 N35 N41 N47 N54 P11 P5 P61 P63 P65 P9 R12 R15 R17 R19 R25 R31 R38 R44 R50 R57 T1 T3 T7 U57 U60 U62 U64 V11 V14 V16 V5 V9 W57 Y1 Y3 Y61 Y63 Y65 Y7

A6 A60 B5 B61 BD1 BD65 BE2 BE64 BH5 BH61 BJ6 BJ60 E2 E64 F1 F65

AV8063801108003_BGA1224~D

A A

5

AV8063801108003_BGA1224~D

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

AV8063801108003_BGA1224~D

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

1

13 66Monday, March 26, 2012

0.1

5

DDR_A_DQS#[0..7](9)

DDR_A_DQS[0..7](9)

DDR_A_D[0..63](9)

DDR_A_MA[0..15](9)

D D

All VREF traces should have 10 mil trace width

Layout Note: Place near JDIMM1

+1.5V

1U_0402_6.3V6K~D

CD4

CD3

1

2

C C

B B

A A

+1.5V

10U_0603_6.3V6M~D

1

CD8

CD9

2

Layout Note: Place near JDIMM1.203,204

+0.75VS

1U_0402_6.3V6K~D

CD17

CD18

+3VS

CD18

1

2

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

CD22

CD21

1

2

1

2

Layout Note: Place near JDIMM1.199

5

M1

1U_0402_6.3V6K~D

CD5

1

2

10U_0603_6.3V6M~D

1

CD10

2

1U_0402_6.3V6K~D

CD19

1

2

+1.5V

12

RD2

RD2 1K_0402_1%~D

1K_0402_1%~D

+V_DDR_REFA

12

RD3

RD3 1K_0402_1%~D

1K_0402_1%~D

1U_0402_6.3V6K~D

CD6

10U_0603_6.3V6M~D

CD11

1U_0402_6.3V6K~D

CD20

10U_0603_6.3V6M~D

1

2

CD13

CD12

2

4

+V_DDR_REFA

@

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D CD1

CD1

1

2

DDR_CKE0_DIMMA(9) DDR_CKE1_DIMMA (9)

QT

330U_D2_2.5VY_R15M~D

1

CD7

+

2

DDR_CS1_DIMMA#(9)

RD8 10K_0402_5%~DRD8 10K_0402 _5%~D

1 2

RD9 10K_0402_5%~DRD9 10K_0402 _5%~D

1 2

4

3

+1.5V

JDIMM1

+V_DDR_REFA

DDR_A_D0 DDR_A_D1

DDR_A_D2

0.1U_0402_16V7K~D

CD2

DDR_A_BS2(9)

M_CLK_DDR0(9) M_CLK_DDR#0(9)

DDR_A_BS0(9)

DDR_A_WE#(9) DDR_A_CAS#(9)

DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10

DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

+3VS

+0.75VS

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET#

31

VSS11

33

DQ10

35

DQ11

37

VSS13

39

DQ16

41

DQ17

43

VSS15

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3

65

VSS23

67

DQ26

69

DQ27

71

VSS25

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

BELLW_80011-1021

BELLW_80011-1021 CONN@

CONN@

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

VSS12

DQ14 DQ15

VSS14

DQ20 DQ21

VSS16

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

VSS24

DQ30 DQ31

VSS26

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

CK1#

BA1

NC2

DM4

DM6

SDA

SCL

VTT2

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26 28

DDR3_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44 46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68

DDR_A_D31

70 72

DDR_CKE1_DIMMA

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA# M_ODT0

M_ODT1

+VREF_CA

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PCH_SMBDATA PCH_SMBCLK

+0.75VS

2.2U_0603_6.3V6K~D

1

2

PCH_SMBDATA (6,15,17,39,43) PCH_SMBCLK (6,15,17,39,43)

2

DDR3_DRAMRST# (8,15)

M_CLK_DDR1 (9) M_CLK_DDR#1 (9)

DDR_A_BS1 (9) DDR_A_RAS# (9)

DDR_CS0_DIMMA# (9) M_ODT0 (9)

M_ODT1 (9)

0.1U_0402_16V7K~D

@

CD15

CD16

1

2

DRAMRST_CNTRL_PC H(8,17)

M3

+V_DDR_REFB(15)

+1.5V

12

RD4

RD4 1K_0402_1%~D

1K_0402_1%~D

12

RD5

RD5 1K_0402_1%~D

1K_0402_1%~D

RD6 0_0402_5%~D@RD6 0_0402_5%~D@

+V_DDR_REFA

DRAMRST_CNTRL_PC H

+V_DDR_REFB

DRAMRST_CNTRL_PC H

1 2

RD7 0_0402_5%~D@RD7 0_0402_5%~D@

D

1 3

PT

2

1 2

D

1 3

PT

2

S

QD1

QD1 BSS138-G_SOT23-3

BSS138-G_SOT23-3

G

S

QD2

QD2 BSS138-G_SOT23-3

BSS138-G_SOT23-3

G

1

12

+V_DDR_REFA_R (9)

RD17

@RD17

@

1K_0402_1%~D

+V_DDR_REFB_R (9)

RD18

@RD18

@

1K_0402_1%~D

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

LA-7851P

1

0.1

of

14 66Monday, March 26, 2012

5

M1

D D

C C

B B

A A

DDR_B_DQS#[0..7](9)

DDR_B_DQS[0..7](9)

DDR_B_D[0..63](9)

DDR_B_MA[0..15](9)

+1.5V

1U_0402_6.3V6K~D

CD26

CD25

1

2

+1.5V

10U_0603_6.3V6M~D

1

2

+0.75VS

CD31

CD30

2

Layout Note: Place near JDIMMB.203,204

1U_0402_6.3V6K~D

CD39

1

2

5

Layout Note: Place near JDIMMB

1U_0402_6.3V6K~D

CD27

1

2

10U_0603_6.3V6M~D

1

CD32

2

1U_0402_6.3V6K~D

CD41

CD40

1

2

CD28

10U_0603_6.3V6M~D

1

CD33

CD34

2

1U_0402_6.3V6K~D

CD42

1

2

+1.5V

12

RD11

RD11 1K_0402_1%~D

1K_0402_1%~D

12

RD12

RD12 1K_0402_1%~D

1K_0402_1%~D

10U_0603_6.3V6M~D

1

CD35

2

Layout Note: Place near JDIMMB.199

+V_DDR_REFB

All VREF traces should have 10 mil trace width

4

+V_DDR_REFB(14)

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

@

CD23

CD24

1

2

+3VS

CD24

1

2

0.1U_0402_16V7K~D

1

2

4

2.2U_0603_6.3V6K~D

CD43

CD44

1

2

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

DDR_CKE2_DIMMB(9)

DDR_CS3_DIMMB#(9)

RD16 10K_0402_5%~DRD16 10K_0402_5%~D

1 2

RD15 10K_0402_5%~DRD15 10K_0402_5%~D

+3VS

1 2

DDR_B_BS2(9)

M_CLK_DDR2(9) M_CLK_DDR#2(9)

DDR_B_BS0(9)

DDR_B_WE#(9) DDR_B_CAS#(9)

3

8/15 update for SSI

+1.5V

+V_DDR_REFB

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

+3VS

+0.75VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

JDIMM2

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

BELLW_80001-2021

CONN@

2

VSS

4

DQ4

6

DQ5

8

VSS

10

DQS0#

12

DQS0

14

VSS

16

DQ6

18

DQ7

20

VSS

22

DQ12

24

DQ13

26

VSS

28

DM1

30

RESET#

32

VSS

34

DQ14

36

DQ15

38

VSS

40

DQ20

42

DQ21

44

VSS

46

DM2

48

VSS

50

DQ22

52

DQ23

54

VSS

56

DQ28

58

DQ29

60

VSS

62

DQS3#

64

DQS3

66

VSS

68

DQ30

70

DQ31

72

VSS

74

CKE1

76

VDD

78

A15

80

A14

82

VDD

84

A11

86

A7

88

VDD

90

A6

92

A4

94

VDD

96

A2

98

A0

100

VDD

102

CK1

104

CK1#

106

VDD

108

BA1

110

RAS#

112

VDD

114

S0#

116

ODT0

118

VDD

120

ODT1

122

NC

124

VDD

126

VREF_CA

128

VSS

130

DQ36

132

DQ37

134

VSS

136

DM4

138

VSS

140

DQ38

142

DQ39

144

VSS

146

DQ44

148

DQ45

150

VSS

152

DQS5#

154

DQS5

156

VSS

158

DQ46

160

DQ47

162

VSS

164

DQ52

166

DQ53

168

VSS

170

DM6

172

VSS

174

DQ54

176

DQ55

178

VSS

180

DQ60

182

DQ61

184

VSS

186

DQS7#

188

DQS7

190

VSS

192

DQ62

194

DQ63

196

VSS

198

EVENT#

200

SDA

202

SCL

204

VTT

206

GND2

208

BOSS2

Compal Secret Data

Deciphered Date

2

+1.5V

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

+VREF_CB

DDR_B_D36 DDR_B_D37

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PCH_SMBDATA PCH_SMBCLK

+0.75VS

2

DDR3_DRAMRST# (8,14)

DDR_CKE3_DIMMB (9)

M_CLK_DDR3 (9) M_CLK_DDR#3 (9)

DDR_B_BS1 (9) DDR_B_RAS# (9)

DDR_CS2_DIMMB# (9) M_ODT2 (9)

M_ODT3 (9)

2.2U_0603_6.3V6K~D

@

CD37

1

2

PCH_SMBDATA (6,14,17,39,43) PCH_SMBCLK (6,14,17,39,43)

1

2

Title

Size Document Number Rev

Date: Sheet of

+1.5V

12

RD13

RD13 1K_0402_1%~D

1K_0402_1%~D

0.1U_0402_16V7K~D

12

RD14

CD38

1K_0402_1%~D

Compal Electronics, Inc.

DDRIII DIMMB

LA-7851P

1

0.1

15 66Monday, March 26, 2012

1

15 66Monday, March 26, 2012

0.1

5

4

3

2

1

RTC CRYSTAL

UH1A

PCH_RTCX1

RH1 10M_0402_5%RH1 10M_0402_5%

1 2

YH1

QT

1 2

32.768KHZ_12.5PF_9H03200019

D D

1

CH3

18P_0402_50V8J~D

2

PCH_RTCX2

1

CH4

CH4 18P_0402_50V8J~D

18P_0402_50V8J~D

2

+RTCVCC

RH2 1M_0402_5%~DRH2 1M_0402_5%~D

1 2

+RTCVCC

RH3 20K_0402_5%~DRH3 20K_0402_5%~D

1 2

RH4 20K_0402_5%~DRH4 20K_0402_5%~D

1 2

SM_INTRUDER# HDA_SPKR

CH5

1U_0603_10V6K~D

CH6

1U_0603_10V6K~D

1

12

CMOS

CLRP1

SHORT PADS

2

1

12

CLRP2

SHORT PADS

2

ME CMOS

CLP1 & CLP2 place near DIMM

HDA_SPKR(46)

HDA_SDIN0(46)

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_RST#

HDA_SDIN0

PCH Strap PIN

INTVRMEN Integrated 1.05V VRM Enable/Disable

+RTCVCC

RH13 330K_0402_5%RH13 330K_0402_5%

1 2

RH16 330K_0402_5%@RH16 330K_0402_5%@

1 2

H：Integrated VRM enable

*

C C

L：Integrated VRM disable

PCH_INTVRMEN

ODD_EJECT(38,43)

PT

RH95 0_0402_5%~D@ RH95 0_0402_5%~D@

1 2

DP_PCH_HPD(18,37)

SPKR No Reboot

+3VS

RH17 1K_0402_5%~D@RH17 1K_0402_5%~D@

1 2

LOW=Default

*

HIGH=No Reboot

If the signal i s sampled high, this indicate that the system is strapped to the "No Reboot" mo de

HDA_SPKR

SSI2

T7PAD~D @T7PAD~D @

HDA_SDOUT

DP_PCH_HPD

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS#

PCH_SPI_CS1#

PCH_SPI_SI

PCH_SPI_SO

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST # / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

BD82HM77 QPRG C1 BGA 989P

@

JTAG

RTCIHDA

SPI

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

LPC_AD0

C38

LPC_AD1

A38

LPC_AD2

B37

LPC_AD3

C37

LPC_FRAME#

D36

E36 K36

SERIRQ

V5

AM3 AM1 AP7 AP5

AM10 AM8

SATA_PTX_DRX_N1

AP11

SATA_PTX_DRX_P1

AP10

AD7 AD5

SATA_PTX_DRX_N2

AH5

SATA_PTX_DRX_P2

AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

PCH_SATALED#

P3

PCH_GPIO21

V14

BBS_BIT0

P1

CH18 0.01U_0402_16V7K~DCH18 0.01U_0402_16V7K~D CH17 0.01U_0402_16V7K~DCH17 0.01U_0402_16V7K~D

CH9 0.01U_0402_16V7K~DCH9 0.01U_0402_16V7K~D CH10 0.01U_0402_16V7K~DCH10 0.01U_0402_16V7K~D

SATA_COMP

SATA3_COMP

RBIAS_SATA3

RH21 37.4_0402_1%RH21 37.4_0402_1%

RH22 49.9_0402_1%RH22 49.9_0402_1%

RH28 750_0402_1%~D RH28 750_0402_1%~D

RH14 10K_0402_5%~D@RH14 10K_0402_5%~D@

RH12 10K_0402_5%~DRH12 10K_0402_5%~D

RH29 10K_0402_5%~DRH29 10K_0402_5%~D

BBS_BIT0 (19)

LPC_AD0 (38,40,42) LPC_AD1 (38,40,42) LPC_AD2 (38,40,42) LPC_AD3 (38,40,42)

LPC_FRAME# (38,40,42)

SERIRQ (38,40)

1 2 1 2

1 2

SERIRQ

SATA_PRX_DTX_N0 (43) SATA_PRX_DTX_P0 (43) SATA_PTX_DRX_N0 (43) SATA_PTX_DRX_P0 (43)

SATA_PRX_DTX_N1 (42) SATA_PRX_DTX_P1 (42) SATA_PTX_DRX_N1_C (42) SATA_PTX_DRX_P1_C (42)

SATA_PRX_DTX_N2 (43) SATA_PRX_DTX_P2 (43) SATA_PTX_DRX_N2_C (43) SATA_PTX_DRX_P2_C (43)

+1.05VS_VCC_SATA

+VCCP

+3VS

1 2

+3VS

HDD

SSD

ODD

UH1

QCR1@

S IC BD82HM77 SLJ8C C1 BGA 989P PCH

UH1

QCR3@

QCR3@RH10 10K_0402_5%~DRH10 10K_0402_5%~D

S IC BD82HM77 SLJ8C C1 BGA 989P PCH A31!

RTC Battery

+RTCBATT

+3VLP

W=20mils

3

1

2

RH34

RH34 1K_0402_5%~D

1K_0402_5%~D

1 2

W=20mils

2

DH1

DH1 BAT54CW_SOT323-3

BAT54CW_SOT323-3

CH12

CH12 1U_0603_10V6K~D

1U_0603_10V6K~D

QT

+RTCVCC

HDA_SYNC On-Die PLL Voltage Regulator Voltage Select

+3V_PCH

RH32 1K_0402_5%~D RH32 1K_0402_5%~D

1 2

This signal has a weak interna l pull-down On Die PLL VR i s supplied by

1.5V when smapl ed high

1.8V when sampl ed low

*

B B

Needs to be pul led High for Hu ron River platf rom

HDA_SDO Flash Descriptor Security Override/Intel ME Debug Mode

+3V_PCH

RH23 1K_0402_5%~D@RH23 1K_0402_5%~D@

1 2

Low = Disabled

*

High = Enabled

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

HDA_SYNC

HDA_SDOUT

HD Audio

HDA_BITCLK_AUDIO(46)

HDA_SYNC_AUDIO(46)

HDA_RST_AUDIO#(46)

HDA_SDOUT_AUDIO(46)

HDA_SDO(38)

HDA_BITCLK_AUDIO HDA_BIT_CLK

RH7 33_0402_5%~DRH7 33_0402_5%~D

1 2

RH8 1M_0402_5%~DRH8 1M_0402_5%~D

1 2

RH5 33_0402_5%~DRH5 33_0402_5%~D

1 2

RH6 33_0402_5%~DRH6 33_0402_5%~D

1 2

RH15 33_0402_5% RH15 33_0402_5%

1 2

RH11 1K_0402_5%~DRH11 1K_0402_5%~D

1 2

+5VS

G

2

13

D

S

D

S

PT

QH1

BSS138-G_SOT23-3

1 2

RH9 0_0402_5%~D@RH9 0_0402_5%~D@

HDA_SYNCHDA_SYNC_R

HDA_RST#

HDA_SDOUT

for enable ME code programing

SPI ROM FOR ME ( 8MByte )

+3V_PCH

RH33 3.3K_0402_5%RH33 3.3K_0402_5%

1 2

RH38 3.3K_0402_5%RH38 3.3K_0402_5%

1 2

RH40 3.3K_0402_5%RH40 3.3K_0402_5%

1 2

PCH_SPI_CS#

PCH_SPI_WP#

PCH_SPI_HOLD#

PCH_SPI_CS# PCH_SPI_SO

UH2

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q64FVSSIG_SO8

HOLD#(IO3)

DI(IO0)

SSI2

+3V_PCH

1

CH11

0.1U_0402_16V7K~D

PCH_SPI_HOLD# PCH_SPI_CLKPCH_SPI_WP# PCH_SPI_SI

2

QT

8

VCC

7 6

CLK

5

Reserve for EMI

CH24 10P_0402_50V8J~D@CH24 10P_0402_50V8J~D@

JTAG

+3V_PCH +3V_PCH+3V_PCH

A A

12

RH18

@RH18

@

200_0402_5%

12

RH24

RH24 100_0402_1%~D

100_0402_1%~D

12

RH19

@RH19

@

200_0402_5%

12

RH25

RH25 100_0402_1%~D

100_0402_1%~D

12

RH20

@RH20

@

200_0402_5%

PCH_JTAG_TCKPCH_JTAG_TMSPCH_JTAG_TDO PCH_JTAG_TDI

12

RH26

RH26 100_0402_1%~D

100_0402_1%~D

5

12

RH35

RH35 51_0402_5%

51_0402_5%

4

1 2

CH1 10P_0402_50V8J~D@CH1 10P_0402_50V8J~D@

1 2

CH2 10P_0402_50V8J~D@CH2 10P_0402_50V8J~D@

1 2

Reserve for RF please close to UH1

HDA_BITCLK_AUDIO

HDA_BIT_CLK

HDA_SDOUT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

LA-7851P

1

16 66Monday, March 26, 2012

0.1

5

PCIE_PRX_GLANTX_N1(41)

10/100/1G LAN --->

D D

MiniWLAN (Mini Card 1)--->

CARD_READER --->

C C

10/100/1G LAN --->

MiniWLAN (Mini Card 1)--->

Card Reader --->

B B

A A

PCIE_PRX_GLANTX_P1(41) PCIE_PTX_GLANRX_N1(41) PCIE_PTX_GLANRX_P1(41)

PCIE_PRX_WLANTX_N3(42)

PCIE_PRX_WLANTX_P3(42) PCIE_PTX_WLANRX_N3(42) PCIE_PTX_WLANRX_P3(42)

PCIE_PRX_CARDTX_N4(40)

PCIE_PRX_CARDTX_P4(40) PCIE_PTX_CARDRX_N4(40) PCIE_PTX_CARDRX_P4(40)

CLK_PCIE_LAN#(41) CLK_PCIE_LAN(41)

LANCLK_REQ#(41)

CLK_PCIE_MINI3#(42) CLK_PCIE_MINI3(42)

MINI3CLK_REQ#(42)

CLK_PCIE_CD#(40) CLK_PCIE_CD(40)

CDCLK_REQ#(40)

CLK_CPU_ITP#(6) CLK_CPU_ITP(6)

CLK_RES_ITP#(8) CLK_RES_ITP(8)

CH15 0.1U_0402_10V7K~DCH15 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~DCH16 0.1U_0402_10V7K~D

1 2

CH19 0.1U_0402_10V7K~DCH19 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~DCH20 0.1U_0402_10V7K~D

1 2

CH21 0.1U_0402_10V7K~DCH21 0.1U_0402_10V7K~D

1 2

CH22 0.1U_0402_10V7K~DCH22 0.1U_0402_10V7K~D

1 2

RH66 10K_0402_5%~DRH66 10K_0402_5%~D

+3V_PCH

RH69 10K_0402_5%~DRH69 10K_0402_5%~D

+3VS

RH74 10K_0402_5%~DRH74 10K_0402_5%~D

+3VS

RH77 10K_0402_5%~DRH77 10K_0402_5%~D

+3V_PCH

RH81 10K_0402_5%~DRH81 10K_0402_5%~D

+3V_PCH

RH83 10K_0402_5%~DRH83 10K_0402_5%~D

+3V_PCH

RH84 10K_0402_5%~DRH84 10K_0402_5%~D

+3V_PCH

RH88 10K_0402_5%~DRH88 10K_0402_5%~D

+3V_PCH

RH90 10K_0402_5%~DRH90 10K_0402_5%~D

+3V_PCH

RH91 0_0402_5%~D@RH91 0_0402_5%~D@ RH92 0_0402_5%~D@RH92 0_0402_5%~D@

ST

RH107 0_0402_5%~D@ RH107 0_0402_5%~D@ RH109 0_0402_5%~D@ RH109 0_0402_5%~D@

1 2

1 2 1 2

4

PCIE_PRX_GLANTX_N1 PCIE_PRX_GLANTX_P1 PCIE_PTX_GLANRX_N1_C PCIE_PTX_GLANRX_P1_C

PCIE_PRX_WLANTX_N3 PCIE_PRX_WLANTX_P3 PCIE_PTX_WLANRX_N3_C PCIE_PTX_WLANRX_P3_C

PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_P4 PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C

T2PAD~D @T2PAD~D @ T3PAD~D @T3PAD~D @

PCIECLKREQ0#

LANCLK_REQ#

PCH_GPIO20

MINI3CLK_REQ#

CDCLK_REQ#

PCH_GPIO44

PEG_B_CLKREQ#

PCH_GPIO45

PCH_GPIO46

CLK_BCLK_ITP# CLK_BCLK_ITP

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

BD82HM77 QPRG C1 BGA 989P

@

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

E12

SMBCLK

H14

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

GPIO74

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

No support iAMT

P10

PEG_A_CLKRQ#

M10

CLK_PEG_VGA#

AB37

CLK_PEG_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12 AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_GND1

BJ30 BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

CLK_PCI_TPM_R CLK_PCI_TPM

K43

KB_DET#

F47

LAN_25M_R

H47

CAM_DET#

K49

KB_DET#

ST

RH44 0_0402_5%~D

SMBCLK (42)

SMBDATA (42)

RH64 10K_0402_5%~DRH64 10K_0402_5%~D

1 2

RH85 90.9_0402_1%RH85 90.9_0402_1%

1 2

RH97 22_0402_1%RH97 22_0402_1%

1 2

RH102 22_0402_1%@ RH102 22_0402_1%@

1 2

RH98 100K_0402_5%~DRH98 100K_0402_5%~D

1 2

SHORT

1 2

CLK_PEG_VGA# (24) CLK_PEG_VGA (24)

CLK_CPU_DMI# (8) CLK_CPU_DMI (8)

T31 PAD~D@ T31 PAD~D@ T30 PAD~D@ T30 PAD~D@

CLK_PCI_LPBACK (19)

KB_DET# (39)

T34 PAD~D@ T34 PAD~D@

EC_LID_OUT#PCH_LID_SW_IN#

DRAMRST_CNTRL_PCH (8,14)

2

SMBCLK

DMN66D0LDW-7_SOT363-6~D

SMBDATA

+3V_PCH

PEG_A_CLKRQ# (24)

+VCCP

PT

+3VS

EC_LID_OUT# (38)

6 1

QH2A

DMN66D0LDW-7_SOT363-6~D

SML1CLK

SML1DATA

CLK_PCI_TPM (40)

LAN_25M (41)

CLK_PCI_TPM

1

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK

SML1DATA

GPIO74

PCH_LID_SW_IN#

DRAMRST_CNTRL_PCH

+3VS

RH71

2.2K_0402_5%~D

2

5

3

4

QH2B

+3VS

ST

6 1

QH3A

@QH3A

DMN66D0LDW-7_SOT363-6~D

@

DMN66D0LDW-7_SOT363-6~D

CLKIN_GND1 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen else, please place close to PCH

XTAL25_IN

XTAL25_OUT

PT PT

CH27

15P_0402_50V8J~D

QT

EMI Request

12

CH13

10P_0402_50V8J~D

RH45 2.2K_0402_5%~DRH45 2.2K_0402_5%~D

1 2

RH46 2.2K_0402_5%~DRH46 2.2K_0402_5%~D

1 2

RH47 2.2K_0402_5%~D RH47 2.2K_0402_5%~D

1 2

RH49 2.2K_0402_5%~D RH49 2.2K_0402_5%~D

1 2

RH50 2.2K_0402_5%~DRH50 2.2K_0402_5%~D

1 2

RH51 2.2K_0402_5%~DRH51 2.2K_0402_5%~D

1 2

RH65 10K_0402_5%~DRH65 10K_0402_5%~D

1 2

RH63 10K_0402_5%~DRH63 10K_0402_5%~D

1 2

RH53

+3VS

12

RH72

2.2K_0402_5%~D

PCH to DDR, XDP, TP, FFS, AMP

PT

2

5

3

4

QH3B

@QH3B

@

RH55 10K_0402_5%~DRH55 10K_0402_5%~D

1 2

RH56 10K_0402_5%~DRH56 10K_0402_5%~D

1 2

RH57 10K_0402_5%~DRH57 10K_0402_5%~D

1 2

RH58 10K_0402_5%~DRH58 10K_0402_5%~D

1 2

RH59 10K_0402_5%~DRH59 10K_0402_5%~D

1 2

RH60 10K_0402_5%~DRH60 10K_0402_5%~D

1 2

RH61 10K_0402_5%~DRH61 10K_0402_5%~D

1 2

RH62 10K_0402_5%~DRH62 10K_0402_5%~D

1 2

RH89 1M_0402_5%~DRH89 1M_0402_5%~D

1 2

YH2

1

IN

OUT

2

GND

25MHZ_18PF_X3G025000DI1H-H~D

1

2

1K_0402_5%~D

PCH_SMBCLK (6,14,15,39,43)

PCH_SMBDATA (6,14,15,39,43)

PCH to EC

PT

3

4

+3V_PCH

PCH_SMLCLK (25,35,38)

PCH_SMLDATA (25,35,38)

1

CH28

CH28 15P_0402_50V8J~D

15P_0402_50V8J~D

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

LA-7851P

1

17 66Monday, March 26, 2012

0.1

5

Compal Electronics, Inc.

UH1C

DMI_CTX_PRX_N0( 7) DMI_CTX_PRX_N1( 7) DMI_CTX_PRX_N2( 7) DMI_CTX_PRX_N3( 7)

DMI_CTX_PRX_P0(7) DMI_CTX_PRX_P1(7) DMI_CTX_PRX_P2(7) DMI_CTX_PRX_P3(7)

DMI_CRX_PTX_N0(7)

D D

XDP_DBRESET#( 6,8)

C C

PM_DRAM_PWRGD(8)

PCH_RSMRST#(38)

PT

SUSPWRDNACK(38)

PBTN_OUT#(6,38)

AC_PRESENT(38)

PCH_GPIO72

RI#

B B

WAKE#

AC_PRESENT

PT

SUSPWRDNACK

PCH_RSMRST#

SYS_PWROK

A A

PCH_PWROK(38)

DMI_CRX_PTX_N1(7) DMI_CRX_PTX_N2(7) DMI_CRX_PTX_N3(7)

DMI_CRX_PTX_P0(7) DMI_CRX_PTX_P1(7) DMI_CRX_PTX_P2(7) DMI_CRX_PTX_P3(7)

+1.05VS_VCC_EXP

RH99 49.9_ 0402_1%RH99 49.9_0402_1%

1 2

RH100 750_0402_1%~DRH100 750_0402_1%~D

1 2

4mil width and place within 500mil of the PCH

PCH_PWROK

RH116 10K_0402_5%~DRH116 10K_0402_5%~D

RH117 10K_0402_5%~DRH117 10K_0402_5%~D

RH118 10K_0402_5%~DRH118 10K_0402_5%~D

RH121 10K_0402_5%~DRH121 10K_0402_5%~D

RH124 10K_0402_5%~DRH124 10K_0402_5%~D

RH127 10K_0402_5%~DRH127 10K_0402_5%~D

RH130 10K_0402_5%~DRH130 10K_0402_5%~D

VGATE(6 ,38,59)

RH104 0_0402_5%~D@RH104 0_0402_5%~D@

PCH_RSMRST# PCH_RSMRST#_R

AC_PRESENT

1 2

PCH_PWROK

5

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP

RBIAS_CPY

SUSACK#

T36PAD~D@ T36PAD~D@

XDP_DBRESET#

SYS_PWROK

1 2

ST

RH105 0_0402 _5%~D

RH106 0_0402 _5%~D

ST

RH108 0_0402 _5%~D

ST

RH110 0_0402 _5%~D

RH112 0_0402 _5%~D

1

2

PM_PWROK_R

SHORT

1 2

APWROK_R

SHORT

1 2

PM_DRAM_PWRGD

SHORT

1 2

SUSPWRDNACK

PBTN_OUT#_R

SHORT

1 2

AC_PRESENT_R

SHORT

1 2

PCH_GPIO72

RI#

+3V_PCH

+3VS

5

UH3

IN1

VCC

OUT

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

4

1

2

SYS_PWROK

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82HM77 QPRG C1 BGA 989P

@

PCH Strap PIN

DSWVRMEN Deep S4/S5 Well On-Die Voltage Regulator Enable

DSWODVREN

H：Enable

*

L：Disable

If strap is sampled high, the Integrated Deep S4/S5 Well (DSW) On-Die VR mode is enabled

CH30

0.1U_0402_16V7K~D

4

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

DMI

System Power Management

RH119 330K_0402_5%RH119 330K_0402_5 %

RH122 330K_0402_5%@RH122 330K_0402_5%@

FDI_RXP7

FDI

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

12

4

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

+RTCVCC

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

SHORT

1 2

RH101 0_0402 _5%~D

WAKE#

PM_CLKRUN#

SUS_STAT#

SUSCLK_R

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

SHORT

1 2

RH103 0_0402 _5%~D

SHORT

1 2

RH111 0_0 402_5%~D

FDI_CTX_PRX_N0 ( 7) FDI_CTX_PRX_N1 ( 7) FDI_CTX_PRX_N2 ( 7) FDI_CTX_PRX_N3 ( 7) FDI_CTX_PRX_N4 ( 7) FDI_CTX_PRX_N5 ( 7) FDI_CTX_PRX_N6 ( 7) FDI_CTX_PRX_N7 ( 7)

FDI_CTX_PRX_P0 (7) FDI_CTX_PRX_P1 (7) FDI_CTX_PRX_P2 (7) FDI_CTX_PRX_P3 (7) FDI_CTX_PRX_P4 (7) FDI_CTX_PRX_P5 (7) FDI_CTX_PRX_P6 (7) FDI_CTX_PRX_P7 (7)

FDI_INT (7)

FDI_FSYNC0 (7)

FDI_FSYNC1 (7)

FDI_LSYNC0 (7)

FDI_LSYNC1 (7)

ST

T5 PAD~D @T5 PAD~D @

ST

T37 PAD~D @T37 PAD~D @

T35 PAD~D @T35 PAD~D @

H_PM_SYNC (8)

3

PCH_RSMRST#_RPCH_DPWROK

SSI2

WAKE_PCH# (38)

PM_CLKRUN# (40)

SUSCLK (38)

PM_SLP_S5# (38)

PM_SLP_S4# (38)

PM_SLP_S3# (38,40,43)

PT

+3VS

VGA_LVDDEN(35)

VGA_PWM(35 )

LVDS_DDC_CLK(35)

LVDS_DDC_DATA(35)

LVDS_ACLK-(35 ) LVDS_ACLK+(35)

LVDS_A0-(35) LVDS_A1-(35) LVDS_A2-(35)

LVDS_A0+(35) LVDS_A1+(35) LVDS_A2+(35)

PT

LVDS_BCLK-(35 ) LVDS_BCLK+(35)

LVDS_B0-(35) LVDS_B1-(35) LVDS_B2-(35)

LVDS_B0+(35) LVDS_B1+(35) LVDS_B2+(35)

RH137 2.2K_0402_5%~DRH137 2.2K_0402_5%~D

1 2

RH138 2.2K_0402_5%~DRH138 2.2K_0402_5%~D

1 2

RH123 2.37K_0402_1%~DRH123 2.37K_0402_1%~D

1 2

RH132 100K_0402_5%~DRH132 100K_0402_5%~ D

1 2

RH134 100K_0402_5%~DRH134 100K_0402_5%~ D

1 2

+3VS

RH136

8.2K_0402_5%~D

PM_CLKRUN#

1 2

T4PAD~D@ T4PAD~D@

ENBKL VGA_LVDDEN

LVDS_DDC_CLK LVDS_DDC_DATA

CTRL_CLK CTRL_DATA

LVDS_IBG

LVDS_ACLKLVDS_ACLK+

LVDS_A0LVDS_A1LVDS_A2-

LVDS_A0+ LVDS_A1+ LVDS_A2+

LVDS_BCLKLVDS_BCLK+

LVDS_B0LVDS_B1LVDS_B2-

LVDS_B0+ LVDS_B1+ LVDS_B2+

CRT_IREF

12

RH115

RH115 1K_0402_5%~D

1K_0402_5%~D

LVDS_DDC_CLK

LVDS_DDC_DATA

LVDS_IBG

VGA_LVDDEN

ENBKL

ENBKL(38)

2

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82HM77 QPRG C1 BGA 989P

@

LVDS

CRT

+3VS

RH133 2.2K_0402_5%~DRH133 2.2K_0402_5%~D

RH135 2.2K_0402_5%~DRH135 2.2K_0402_5%~D

RH233 2.2K_0402_5%~DRH233 2.2K_0402_5%~D

RH234 2.2K_0402_5%~DRH234 2.2K_0402_5%~D

RH142 2.2K_0402_5%~D@ RH142 2.2K_0402_5%~D@

RH141 2.2K_0402_5%~D@ RH141 2.2K_0402_5%~D@

PCH Strap PIN

L_DDC_DATA

SDVO_CTRLDATA Port B Detected

RH120

@RH120

@

10K_0402_5%~D

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

DDPC_CTRLDATA Port C Detected

2

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

DDPC_CTRLCLK

DDPC_CTRLDATA

mDP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DMC

1 2

LVDS Detected

1

AP43 AP45

AM42 AM40

AP39

SDVO_INTN

AP40

SDVO_INTP

PCH_SDVO_CTRLCLK

P38

PCH_SDVO_CTRLDATA

M39

AT49

DDPB_AUXN

AT47

DDPB_AUXP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N

DDPB_1P

DDPB_2N

DDPB_2P

DDPB_3N

DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

HDMI_PCH_HPD#

AT40

HDMI_A2N_VGA

AV42

HDMI_A2P_VGA

AV40

HDMI_A1N_VGA

AV45

HDMI_A1P_VGA

AV46

HDMI_A0N_VGA

AU48

HDMI_A0P_VGA

AU47

HDMI_A3N_VGA

AV47

HDMI_A3P_VGA

AV49

DP_DDC_CLK

P46

DP_DDC_DATA

P42

PCH_DPC_AUXN

AP47

PCH_DPC_AUXP

AP49

DP_PCH_HPD

AT38

DISP_A0N_PCH

AY47

DISP_A0P_PCH

AY49

DISP_A1N_PCH

AY43

DISP_A1P_PCH

AY45

DISP_A2N_PCH

BA47

DISP_A2P_PCH

BA48

DISP_A3N_PCH

BB47

DISP_A3P_PCH

BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

CTRL_CLK

CTRL_DATA

PCH_SDVO_CTRLCLK

PCH_SDVO_CTRLDATA

DP_DDC_CLK

DP_DDC_DATA

0 = LVDS is not detected 1 = LVDS is detected

0 = Port B is not detected 1 = Port B is detected

0 = Port C is not detected 1 = Port C is detected

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-7851P

PCH_SDVO_CTRLCLK (36)

PCH_SDVO_CTRLDATA (36)

HDMI_PCH_HPD# (36)

HDMI_A2N_VGA (36)

HDMI_A2P_VGA (36)

HDMI_A1N_VGA (36)

HDMI_A1P_VGA (36)

HDMI_A0N_VGA (36)

HDMI_A0P_VGA (36)

HDMI_A3N_VGA (36)

HDMI_A3P_VGA (36)

DP_DDC_CLK (37) DP_DDC_DATA (37)

PCH_DPC_AUXN (37) PCH_DPC_AUXP (37) DP_PCH_HPD (16,37)

DISP_A0N_PCH (37) DISP_A0P_PCH (37) DISP_A1N_PCH (37) DISP_A1P_PCH (37) DISP_A2N_PCH (37) DISP_A2P_PCH (37) DISP_A3N_PCH (37) DISP_A3P_PCH (37)

PU on DDC Dongle Side

1

0.1

18 66Monday, March 26, 2012

0.1

RPH1

RPH2

RPH3

5

WL_OFF#

18

PCI_PIRQB#

27

PCI_PIRQD#

36

PCI_PIRQC#

45

18

PCH_GPIO52

27

DGPU_PWR_EN#

36

DGPU_HOLD_RST#

45

18

PCI_PIRQA#

27

PCH_GPIO5

36

ODD_DA#

45

WL_OFF#

USB Conn 1 USB Conn 3 (Power share) USB Conn 2

+3VS

8.2K_0804_8P4R_5%

D D

8.2K_0804_8P4R_5%

GNT3# A16 Top-Block Swap Override (Internal PU 20K)

H：Enable

*

L：Default

RH243 1K_0402_5%~D@ RH243 1K_0402_5%~D@

C C

1 2

Boot BIOS Strap

RH245 1K_0402_5%~D@RH245 1K_0402_5%~D@

1 2

RH244 1K_0402_5%~D@RH244 1K_0402_5%~D@

1 2

GPIO19 => BBS_BIT0 GPIO51 => BBS_BIT1

BBS_BIT1

BBS_BIT0 (16)

Boot BIOS Strap

1

0

Boot BIOS Location

LPC

Reserved (NAND)

PCI

SPI

CLK_PCI_LPBACK(17)

CLK_PCI_LPC(38)

CLK_PCI_DEBUG(42)

CLK_PCI_LPBACK CLK_PCI_LPC CLK_PCI_DEBUG

BBS_BIT[1]

BBS_BIT[0]

0 0

0

1

1 1

*

B B

Reserve for EMI

CH14 10P_0402_50V8J~D@ CH14 10P_0402_50V8J~D@

1 2

CH26 10P_0402_50V8J~D@ CH26 10P_0402_50V8J~D@

1 2

PLT_RST#(6,8,38,40,41,42)

A A

5

CLK_PCI_LPC

CLK_PCI_DEBUG

12

RH155

RH155 100K_0402_5%~D

100K_0402_5%~D

+3VS

5

UH5

P

IN1

4

O

IN2

G

SN74AHC1G08DCKR_SC70-5

3

1

2

PCH_PLTRST#

RH157

@RH157

@

10K_0402_5%~D

1 2

4

USB3RN1(44) USB3RN2(45) USB3RN3(44)

USB3RP1(44) USB3RP2(45) USB3RP3(44)

USB3TN1(44) USB3TN2(45) USB3TN3(44)

USB3TP1(44) USB3TP2(45) USB3TP3(44)

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST# PCH_GPIO52 DGPU_PWR_EN#

BBS_BIT1

T6PAD~D @T6PAD~D @

T8PAD~D @T8PAD~D @ T9PAD~D @T9PAD~D @

EN_CAM WL_OFF#

FFS_INT1 ODD_DA# DP_CBL_DET PCH_GPIO5

PCH_PLTRST#

EN_CAM(35) WL_OFF#(42)

FFS_INT1(43)

ODD_DA#(43)

DP_CBL_DET(37)

RH144 22_0402_5%RH144 22_0402_5%

1 2

RH145 22_0402_5%RH145 22_0402_5%

1 2

RH146 22_0402_5%RH146 22_0402_5%

1 2

4

DGPU_PWR_EN(33,60)

USB3RN1 USB3RN2 USB3RN3

USB3RP1 USB3RP2 USB3RP3

USB3TN1 USB3TN2 USB3TN3

USB3TP1 USB3TP2 USB3TP3

CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4

PT

0.01U_0402_16V7K~D

UH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3TP1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82HM77 QPRG C1 BGA 989P

@

1

CH99

2

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

USB

ST

DGPU_PWR_EN#

2

G

QH6

3

RSVD23 RSVD24

RSVD25

RSVD26 RSVD27

RSVD28 RSVD29

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

AV10

AT8

AY5 BA2

AT12 BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

2011/08/25 2012/07/25

RSVD

USB30

PCI

+3VS

RH247

RH247 10K_0402_5%~D

10K_0402_5%~D

1 2

13

D

S

2N7002_SOT23-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Intel Anti-Thef t Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2

USB20_N4 USB20_P4

USB20_N12 USB20_P12

RH139 1 K_0402_5%~D@R H139 1K_0402_5%~D@

USB20_N0 (44) USB20_P0 (44) USB20_N1 (45) USB20_P1 (45) USB20_N2 (44) USB20_P2 (44)

USB20_N4 (42) USB20_P4 (42)

USB20_N12 (35) USB20_P12 (35)

Within 500 mils

USBRBIAS

RH143 22.6_0402_1%RH143 22.6_0402_1%

1 2

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

PLTRST_VGA#(24)

Compal Secret Data

1 2

USB_OC0# (44,45) USB_OC1# (44)

12

RH154

RH154 100K_0402_5%~D

100K_0402_5%~D

Deciphered Date

2

*

+1.8VS

USB Conn 1

USB Conn 3 (Power share)

USB Conn 2

Mini Card(WLAN)

Camera

RH148 0_0402_5%~D@ RH148 0_0402_5%~D@

1 2

PT

+3VS_DELAY

5

UH4

1

P

IN1

4

O

2

IN2

G

SN74AHC1G08DCKR_SC70-5

3

2

USB_OC4# USB_OC0# USB_OC6# USB_OC5#

USB_OC1# USB_OC2# USB_OC3# USB_OC7#

RH151 0_0402_5%~D@ RH151 0_0402_5%~D@

QT

RH152 0_0402_5%~D

12

RH156

RH156 100K_0402_5%~D

100K_0402_5%~D

1

+3V_PCH

RPH4

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%~D

RPH5

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%~D

1 2

SHORT

1 2

Title

PCH (4/8) PCI, USB, NVRAM

Size Document Number Rev

LA-7851P

Date: Sheet of

PCH_PLTRST#

DGPU_HOLD_RST#

Compal Electronics, Inc.

1

DGPU_PWROK (20,37,60)

19 66Monday, March 26, 2012

0.1

5

+3V_PCH

RH189 10K_0402_5%~DRH189 10K_0402_5%~D

1 2

RH183 10K_0402_5%~DRH183 10K_0402_5%~D

1 2

RH179 10K_0402_5%~DRH179 10K_0402_5%~D

1 2

+3VS

RH160 10K_0402_5%~DRH160 10K_0402_5%~D

D D

1 2

RH184 10K_0402_5%~DRH184 10K_0402_5%~D

1 2

RH172 10K_0402_5%~DRH172 10K_0402_5%~D

1 2

RH176 10K_0402_5%~DRH176 10K_0402_5%~D

1 2

RH174 8.2K_0402_5%~DRH174 8.2K_0402_5%~D

1 2

RH180 10K_0402_5%~DRH180 10K_0402_5%~D

1 2

RH171 200K_0402_5%RH171 200K_0402_5%

1 2

RH185 10K_0402_5%~DRH185 10K_0402_5%~D

1 2

RH190 10K_0402_5%~DRH190 10K_0402_5%~D

1 2

RH177 10K_0402_5%~DRH177 10K_0402_5%~D

1 2

RH182 10K_0402_5%~DRH182 10K_0402_5%~D

1 2

EC_SMI#

PCH_GPIO12

HDD_DETECT#

PCH_GPIO0

PCH_GPIO6

PCIE_MCARD1_DET#

PCH_GPIO22

BT_RADIO_DIS#

PCH_GPIO49

ODD_DETECT#

DGPU_PWROK

EC_SCI#

LCD_DBC

LCD_DCR

SSI2

LCD_DBC(35)

SSI2

PCH Strap PIN

C C

GPIO15 TLS Confidentiality

Low - Intel ME Crypto Transpor t Layer Securit y (TLS) cipher suite wi th no confident iality High - Intel ME Crypto Transpo rt Layer Securi ty (TLS) cipher suite wi th confidential ity

*

+3V_PCH

RH158 1K_0402_5%~DRH158 1K_0402_5%~D

1 2

GPIO28 On-Die PLL Voltage Regulator

This signal has a weak internal pull up

H：On-Die voltage regulator enabl e

*

L：On-Die PLL Volt age Regulator d isable

RH165 1K_0402_5%~D@RH165 1K_0402_5%~D@

1 2

B B

PCH_GPIO15

PCH_GPIO28

LCD_DCR(35)

SATA3GP/GPIO37 Reserved

When Unused as GPIO or SATA*GP Use 8.2K-10K pu ll-down to grou nd

4

UH1F

PCH_GPIO1

QT

EC_SCI#(38)

EC_SMI#(38)

ODD_DETECT#(43)

DGPU_PWROK(19,37,60)

T38PAD~D @T38PA D~D @

BT_RADIO_DIS#(42)

T46PAD~D @T46PA D~D @

PCIE_MCARD1_DET#(42)

FFS_INT2(43)

HDD_DETECT#(43)

PCH_GPIO0

PCH_GPIO6

EC_SCI#

EC_SMI#

PCH_GPIO12

PCH_GPIO15

ODD_DETECT#

DGPU_PWROK

PCH_GPIO22

PCH_GPIO27

PCH_GPIO28

BT_RADIO_DIS#

LCD_DBC

PCH_GPIO36

PCH_GPIO37

PCIE_MCARD1_DET#

LCD_DCR

FFS_INT2

PCH_GPIO49

HDD_DETECT#

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82HM77 QPRG C1 BGA 989P

@

3

ODD_EN#

A20GATE

PECI

RCIN#

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

KB_BL_DET

B41

DGPU Board ID

C41

USB_MCARD1_DET#

A40

GATEA20

P4

PCH_PECI_R

AU16

KB_RST#

P5

AY11

H_THERMTRIP#_C

AY10

INIT3_3V#

T14

NV_CLE

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

DMI and FDI Tx/ Rx Termination Voltage

NV_CLE

GPIO

NCTF

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

PROCPWRGD

CPU/MISC

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

2

ODD_EN# (43)

KB_BL_DET (39)

USB_MCARD1_DET# (42)

RH159 10K_0402_5%~DRH159 10K_0402_5%~D

1 2

RH161 0_0402_5%~D@ RH161 0_0402_5%~D@

1 2

KB_RST# (38)

H_CPUPWRGD (6,8)

RH162 390_0402_5%RH162 390_0402_5%

1 2

T28 PAD~D@T28 PAD~D@

+3VS

GATEA20 (38)

H_PECI (8,38)

H_THERMTRIP# (8)

INIT3_3V

This signal has weak internal PU, can't pull low

+VCCPNAND

Weak internal PU,Do not pull low

RH167 1K_0402_5%~D RH167 1K_0402_5%~D

1 2

12

RH166

2.2K_0402_5%~D

CLOSE TO THE BRANCHING POINT

This signal is a strap for sel ecting DMI and FDI termination vol tage.

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

1

ODD_EN#

KB_RST#

RN178 10K_0402_5%~DRN178 10K_0402_5%~D

1 2

RH175 10K_0402_5%~DRH175 10K_0402_5%~D

1 2

DGPU Board ID Optional

DGPU Board ID

N13P

H_SNB_IVB# (8)

+3VS

12

DP1.2@

RH186

10K_0402_5%~D

12

DP1.1@

RH187

10K_0402_5%~D

0 = GV(DP1.1@)Graphics

1 = GS(DP1.2@)

+3VS

RH169 10K_0402_5%~DRH169 10K_0402_5%~D

1 2

A A

5

PCH_GPIO37

+3VS

12

TPM@ RH163

TPM@

10K_0402_5%~D

12

NTPM@ RH164

NTPM@

10K_0402_5%~D

RH163

PCH_GPIO1

RH164

4

QT

TPM BOM Optional

PCH_GPIO1

1 = W/TPM

TPM

0 = W/O TPM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

LA-7851P

1

20 66Monday, March 26, 2012

0.1

Compal LA-7852P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual