Compal LA-7841P QLM00, XPS 14 Schematic

A

B

C

D

E

MODEL NAME : PCB NO : BOM P/N :

1 1

LA-7841P ( DA********** ) TBD

QLM00

Dell/Compal Confidential

Schematic Document

2 2

Ivy Bridge ULV(BGA1023) + Panther Point

DISCRETE VGA N13P-GV(optimus)

Phantom(Chief River)

2012-01-19

Rev: 1.0 (X04)

3 3

@ : Nopop Component CONN@ : Connector Component DIS@ : pop when DIS configuration UMA@ : pop when UMA configuration

MB Type

TPM

TCM

TPM DIS/ TCM DIS 2@

4 4

A

B

BOM P/N

4319EJ31L01

4319EJ31L02

2@

4@

3@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Page

Cover Page LA-7841P

LA-7841P

E

1 65Tuesday, February 07, 2012

of

0.3

VGA

DC

/DC

System

C/DC

D

A

128M*16 x 4 =1GB

VRAM * 4 GDDR5

GPU

N13P

P.33

P.34

VCCP

+

+1.5V / +

0.75VS

P.57

P.58

ZZZ

PCB-MB

1 1

GB2-64

DCIN / BATT

C

ONN

CHARGER

3/5V ALW

2 2

3 3

+1.8VS

+VCCSA

P.53

CPU / iGPU

ORE

C

.54

P

P.55

P.56

Card Reader

RTS5209

3 in 1

Socket

dGPU CORE

Port 4

P.48

.48

P

P.59

P.60

P.61

Mini Card-1

WLAN / BT4.0

LVDS Conn.

HDMI Conn.

Mini DP Conn.

Port 3

Half

USB2.0

ort 4

P

Daughter board

P.42

64 bit

-GV

P.35

P.36

P.37

.29~30

P

P.24 ~ 28

B

PEG 2.0 x16

LVDS (Dual Channel)

HDMI 1.4 (1.65Gb/s)

isplayPort 1.1

D

P

CI-E x1

Port 1

LAN(GbE) R

TL8111F

RJ45

.41

P

SPI ROM

x 1

8M

P.16

Discrete TPM

T97SC3204

A

P.41

P.40

Intel

I

vy Bridge

Processor

ULV 17W DC

BGA 1023 Balls

100MHz 100MHz

2.7GT/s

Intel

Panther Point

PCH HM77

BGA 989 Balls

SPI

ENE KBC

B9012

K

KB matrix

LPC Bus

33MHz

DMI x4FDI x8

20Gb/s

P.16 ~ 23

P.38

.7 ~ 13

P

C

PS/2

Single Channel

1.5V DDR3 1333 MHz

SATA3.0

USB2.0

HD Audio

Port 0

P

ort 1

Port 1USB 3.0

Port 0

ort 2

P

Port 1

Port 5

Port 12

D

DDRIII-DIMM x 1

B

ANK 0, 1, 2, 3, 4 ,5 ,6 ,7

8GB Max

SATA3 Re-Driver

P

S8520

P.43

SATA3 Re-Driver

PS8520

(DIS Only)

P

.43

USB 3.0 Conn. X1

P.44

PI5USB1457

P.45

Mini Card-2

WWAN

(

Full )

Digital Camera

udio Codec

A

ALC3260

P.48

P.35

P.48

Int. Speaker x2

P.48

P.14

SATA HDD Conn.

Mini Card-2

m

SATA

( Full )

USB 3.0 Conn. X1

( Power Share )

SIM

Daughter board

P.48

UMA SKU

Digi Mic (Array)

Headphone / Mic

Jack x 1

( Combo )

Daughter board

P.43

P.48

P.45

P.35

P.48

E

CPU ITP

onn.

P.8

P.39

C

Fan Control LID SW

RTC Circuit

Power SW (Daughter Board)

D

aughter board

DI

S SKU

FFS

P.43

P.40

P.16

P.39

Int.KBD Touch Pad

4 4

A

B

P.39 P.39

C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

D

Compal Electronics,Inc.

Title

Size Document Number Rev

Date: Sheet

E

2 65Tuesday, February 07, 2012

of

0.3C

A

Compal Confidential

Project Code : QLM00 File Name : LA-7841P

B

C

D

E

1 1

LS-7841P POWER BUTTON BOARD

LA-7841P M/B

Camera

LS-7842P LED INDICATE BOARD LS-7843P BATTERY INDICATED BOARD LS-7844P I/O BOARD

40 pin

Wire

LCD Panel

IO/B

FFC

INDICATOR/B

2 2

Led-Wireless Led-CapsLock

Wire

6 pin

10 pin

Wire

4 pin

HDD

FFC

TP LED/B

Touch Pad

3 3

FFC

4 pin

Led x 6

Lid

POWER BUTTON/B

on/off SW

Led x 1

4 pin4 pin

WireWire

FRONT LIGHT L/B FRONT LIGHT R/B

Led x 2 Led x 2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

E

0.3

3 65Tuesday, February 07, 2012

0.3

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

SMBUS Control Table

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SML0CLK PCH PCH_SML0DATA

PCH_SML1CLK PCH_SML1DATA

MEM_SMBCLK MEM_SMBDATA

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5% 18K +/- 5% 3

3K +/- 5%

56K +/- 5%

100K +/- 5% 200K +/- 5%

SOURCE

KB930

PCH

AD_BID

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

MINI2

MINI1 BATT SODIMM

V V

V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

Thermal Sensor 1

V V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

Thermal Sensor 2

max

FFS VGA

EC AD3

0x00-0x0C 0x0D-0x1C 0x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF

VGA Thermal Sensor

V

V V

A

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

DMCVXDP

Charger

V

PCB Revision

0.1

0.2

0.3

0.4

1.0

Link

PCH

USB PORT#

0 1 2 3 4 5 6 7 8 9 10 11

DESTINATION None JUSB1 (2.0 Ext Left Side) Bluetooth CAMERA JMINI1 (WLAN) JMINI2 (WWAN/DMC) ELC 8051 None None None None None

12

CLKOUT

1 1

PCI0 PCI1 PCI2 PCI3 PCI4

CLK

DESTINATION

PCH_LOOPBACK

EC LPC None None None

CLKOUT_PCIE0 CLKOUT_PCIE1 CLKOUT_PCIE2 CLKOUT_PCIE3 CLKOUT_PCIE4 CLKOUT_PCIE5 CLKOUT_PCIE6 CLKOUT_PCIE7 None CLKOUT_PEG_B

DESTINATIONDIFFERENTIAL

10/100/1G LAN MINI CARD-2 WWAN MINI CARD-1 WLAN CARD READER None USB 3.0

None

FLEX CLOCKS DESTINATION CLKOUTFLEX0None CLKOUTFLEX1 CLKOUTFLEX2 CLKOUTFLEX3

None None None None

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

SATA SATA0 SATA1 SATA2 SATA3 SATA4 SATA5

DESTINATION

HDD None ODD None None None

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Secret Data

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

13

PCI EXPRESS

Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Lane 8 None

None None

DESTINATION 10/100/1G LAN MINI CARD-2 WWAN/DMC MINI CARD-1 WLAN CARD READER None USB 3.0 None

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List LA-7841P

LA-7841P

4 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

+3VS

SMBUS Address [0x9a]

D D

C9

H14

SMBCLK SMBDATA

PCH

C8

SML0CLK

SML0DATA

12

G

2.2K

+3V_PCH

2.2K

+3V_PCH

+3VS

DMN66D0 DMN66D0

+3VS_WLAN

2.2K

+3VS_WLAN

2.2K

DMN66D0 DMN66D0

E14M16

C C

SML1CLK

SML1DATA

2.2K

+3V_PCH

IO CONN

14 15

202 200

4 5

30 32

32

WLAN

30

WWAN/mSATA

DIMMA

WLAN

4

G Sensor

6

SMBUS Address [TBD]

SMBUS Address [A0]

SMBUS Address [TBD]

TP

SMBUS Address [TBD]

DMN66D0 DMN66D0

EC_SMB_CK2

EC_SMB_DA2

80 79

KBC

B B

8.2K

+3VS

DMN66D0 DMN66D0

+3VS

2.2K

+3V_GPU

10

Camera

9

2.2K

100 ohm

3

2.2K

100 ohm

D9 D8

4 5

9

8

2011/07/15 2012/07/15

GPU

BATTERY CONN

CHARGER

Compal Secret Data

SMBUS Address [0x9E]

SMBUS Address [TBD]

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

Date: Sheet of

5 65Tuesday, February 07, 2012

1

0.3

+3V_GPU

4.7K

+3VALW

77

EC_SMB_CK1

78

EC_SMB_DA1

A A

5

4.7K

4

DMN66D0 DMN66D0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EN_INVPWR

5

SI3457BDV

Q

V29

+INV_PWR_SRC

RT8207MZQW

U300

P

4

3

2

1

+0.75VS

TPS51461RGER

+VCCP

SI4634DY

UZ1

1.05VSDGPU

AO4728L

QU6

SI3456DDV

UZ4

TPS2062ADR

UI2

SI3456DDV

QN1

SI4800BDY

Z6

Q

AO3419L

QH5

U600

P

SI3456DDV

QZ12

SY8033BDBC

PU400

SI4800BDY

QZ8

AO3419L

QL3

+1.5V_CPU_VDDQ

+1.5VS

+5V_CHGUSB

+5VS_HDD

+5VS

+5V_PCH

+VCCSA

+3V_PCH

+1.8VS

+3VS

+LAN_IO

ODD_EN#

EN_DFAN1

EC_ENVDD / VGA_LVDDEN

EN_CAM

WLAN_EN

FDC655BN

N4

Q

APE8873M

E4

U

AO3419L

QV27

SI2301CDS

QV31

SI3456DDV

QM1

+5VS_ODD

+FAN_POWER

+LCDVDD

+3VS_CAM

+3VS_WLAN

+VCC_CORE/+VCC_GFXCORE_AXG

ISL95836HRTZ-T

+1.5V_CPU_VDDQ

ower Bottom &

P BATBTN & USBCHG_DET

Tc

PWRBTN#

PCH

DPWROK

RSMRST# PCH_RSMRST#

ACPRESENT

LP_S5#

S

SLP_S3#

APWROK

PWROK

SYS_PWROK

PGOOD

AO4728L

4

5

6

7

8

10

11

17

18

16

13

AC mode Ta -> Tb -> Tc DC mode Tc -> Ta -> Tb

ON/OFF

ENE KB9012

PBTN_OUT#

PCH_DPWROK

AC_PRESENT

PM_SLP_S5#

PM_SLP_S3#

PCH_APWROK

PCH_PWROK

VR_ON

VGATE

CPU1.5V_S3_GATE

EC_ON

P

CH_PWR_EN

SYSON

SUSP#

SA_PGOOD

15

Ta

12

+3V/+5V_ALW

R

T8205LZQW

PGOOD

TP0610K

Tb

4

9

AO3419L/SI3456DDV

RT8207MZQW

PGOOD

SY8033BDBC

PGOOD

SI4800BDY

SI3456DDV

TPS51212DSCR

PGOOD

14

+VSBP

+3V/+5V_PCH

+

1.5V/+0.75VS

+1.8VS

+3VS

+5VS

+1.5VS

+VCCP

TPS51461RGER

+VCCSA

GOOD

P

CPU1.5V_S3_GATE

SYSON

RT8207MZQW

PU300

ADAPTER

D D

SUSP#

TPS51212DSCR

PU500

VR_ON

BATTERY

B+

ISL95836HRTZ

U700

P

+1.5V

SUSP#

+VCCP

+VCC_CORE / +

VCC_GFXCORE_AXG

PWRSHARE_EN_EC#

CHARGER

PM_SLP_S3#

SUSP#

PCH_PWR_EN

EC_ON / VCOUT0_PH / MAINPWON

C C

RT8205LZQW

PU200

+5VALW

+V1.05S_VCCP_PWRGOOD

3VALW

+

PCH_PWR_EN

SUSP#

EN_WOL

B B

GPU

DGPU_PWR_EN

+3VS

AO3419L

QZ1

+3V_GPU

RC delay

+1.5V

SI4634DY

UZ2

+1.5VSDGPU

RC delay

+

B+

ISL62883CHRTZ

A A

PU800

+GPU_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Power Diagram

1

0.3

6 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

PEG_RCOMPO (G4)

PEG_ICOMPI (G3)

Trace length M

ax is 500 mils

D D

DMI_CRX_PTX_N0<18> DMI_CRX_PTX_N1<18> DMI_CRX_PTX_N2<18> DMI_CRX_PTX_N3<18>

DMI_CRX_PTX_P0<18> DMI_CRX_PTX_P1<18> DMI_CRX_PTX_P2<18> DMI_CRX_PTX_P3<18>

DMI_CTX_PRX_N0<18> DMI_CTX_PRX_N1<18> DMI_CTX_PRX_N2<18> DMI_CTX_PRX_N3<18>

DMI_CTX_PRX_P0<18> DMI_CTX_PRX_P1<18> DMI_CTX_PRX_P2<18> DMI_CTX_PRX_P3<18>

FDI_CTX_PRX_N0<18> FDI_CTX_PRX_N1<18> FDI_CTX_PRX_N2<18> FDI_CTX_PRX_N3<18> FDI_CTX_PRX_N4<18> FDI_CTX_PRX_N5<18>

+VCCP

FDI_CTX_PRX_N6<18> FDI_CTX_PRX_N7<18>

FDI_CTX_PRX_P0<18> FDI_CTX_PRX_P1<18> FDI_CTX_PRX_P2<18> FDI_CTX_PRX_P3<18> FDI_CTX_PRX_P4<18> FDI_CTX_PRX_P5<18> FDI_CTX_PRX_P6<18> FDI_CTX_PRX_P7<18>

FDI_FSYNC0<18> FDI_FSYNC1<18>

FDI_INT<18> FDI_LSYNC0<18>

FDI_LSYNC1<18>

RU2

1 2

24.9_0402_1%

EDP_COMP

C C

eDP_COMPIO and ICOMPO signals

B B

should be shorted near balls and routed with typical impedance <25 mohms

W11

W10

AA11 AC12

AA10

AG8

AG11

AG4

AE11

AE10

AC9

AA7

AA3 AC8

U11

AF3 AD2

AF4

AC3 AC4

AE7 AC1

AA4 AE6

M2

P6 P1

P10

N3 P7 P3

P11

K1

M8

N4 R2

K3

M7

P4 T3

U7

W1

AA6

W6

V4 Y2

U6 W3 W7

T4

PEG_ICOMPO (G1)

U2A

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]

DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]

DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]

FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3]

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

eDP_COMPIO eDP_ICOMPO eDP_HPD#

eDP_AUX# eDP_AUX

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

IVY-BRIDGE_BGA1023~D

@

Trace length Max is 500 mils

R_COMP place close to CPU

width 4 mils

width 12 mils

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1]

DMI Intel(R) FDI

PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4]

eDP

PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

R_COMP

G3 G1 G4

H22

PEG_GTX_C_HRX_N15

J21

PEG_GTX_C_HRX_N14

B22

PEG_GTX_C_HRX_N13

D21

PEG_GTX_C_HRX_N12

A19

PEG_GTX_C_HRX_N11

D17

PEG_GTX_C_HRX_N10

B14

PEG_GTX_C_HRX_N9

D13

PEG_GTX_C_HRX_N8

A11

PEG_GTX_C_HRX_N7

B10

PEG_GTX_C_HRX_N6

G8

PEG_GTX_C_HRX_N5

A8

PEG_GTX_C_HRX_N4

B6

PEG_GTX_C_HRX_N3

H8

PEG_GTX_C_HRX_N2

E5

PEG_GTX_C_HRX_N1

K7

PEG_GTX_C_HRX_N0

K22

PEG_GTX_C_HRX_P15

K19

PEG_GTX_C_HRX_P14

C21

PEG_GTX_C_HRX_P13

D19

PEG_GTX_C_HRX_P12

C19

PEG_GTX_C_HRX_P11

D16

PEG_GTX_C_HRX_P10

C13

PEG_GTX_C_HRX_P9

D12

PEG_GTX_C_HRX_P8

C11

PEG_GTX_C_HRX_P7

C9

PEG_GTX_C_HRX_P6

F8

PEG_GTX_C_HRX_P5

C8

PEG_GTX_C_HRX_P4

C5

PEG_GTX_C_HRX_P3

H6

PEG_GTX_C_HRX_P2

F6

PEG_GTX_C_HRX_P1

K6

PEG_GTX_C_HRX_P0

G22

PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15

C23

PEG_HTX_GRX_N14 PEG_HTX_C_GRX_N14

D23

PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13

F21

PEG_HTX_GRX_N12 PEG_HTX_C_GRX_N12

H19

PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11

C17

PEG_HTX_GRX_N10 PEG_HTX_C_GRX_N10

K15

PEG_HTX_GRX_N9 PEG_HTX_C_GRX_N9

F17

PEG_HTX_GRX_N8 PEG_HTX_C_GRX_N8

F14

PEG_HTX_GRX_N7 PEG_HTX_C_GRX_N7

A15

PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6

J14

PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5

H13

PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4

M10

PEG_HTX_GRX_N3 PEG_HTX_C_GRX_N3

F10

PEG_HTX_GRX_N2 PEG_HTX_C_GRX_N2

D9

PEG_HTX_GRX_N1 PEG_HTX_C_GRX_N1

J4

PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0

F22

PEG_HTX_GRX_P15 PEG_HTX_C_GRX_P15

A23

PEG_HTX_GRX_P14 PEG_HTX_C_GRX_P14

D24

PEG_HTX_GRX_P13 PEG_HTX_C_GRX_P13

E21

PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12

G19

PEG_HTX_GRX_P11 PEG_HTX_C_GRX_P11

B18

PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10

K17

PEG_HTX_GRX_P9 PEG_HTX_C_GRX_P9

G17

PEG_HTX_GRX_P8 PEG_HTX_C_GRX_P8

E14

PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7

C15

PEG_HTX_GRX_P6 PEG_HTX_C_GRX_P6

K13

PEG_HTX_GRX_P5 PEG_HTX_C_GRX_P5

G13

PEG_HTX_GRX_P4 PEG_HTX_C_GRX_P4

K10

PEG_HTX_GRX_P3 PEG_HTX_C_GRX_P3

G10

PEG_HTX_GRX_P2 PEG_HTX_C_GRX_P2

D8

PEG_HTX_GRX_P1 PEG_HTX_C_GRX_P1

K4

PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0

Typ- suggest 220nF. The change in AC capacitor

alue from 100nF to 220nF is to enable compatibility

v with future platforms having PCIE Gen3 (8GT/s)

VCC_IO

PEG_COMP

+VCCP

RU1

12

24.9_0402_1%

PT

1 2

CU1 0.22U_0402_16V7K~D@CU1 0.22U_0402_16V7K~D@

1 2

CU2 0.22U_0402_16V7K~D@CU2 0.22U_0402_16V7K~D@

1 2

CU3 0.22U_0402_16V7K~D@CU3 0.22U_0402_16V7K~D@

1 2

CU4 0.22U_0402_16V7K~D@CU4 0.22U_0402_16V7K~D@

1 2

CU5 0.22U_0402_16V7K~D@CU5 0.22U_0402_16V7K~D@

1 2

CU6 0.22U_0402_16V7K~D@CU6 0.22U_0402_16V7K~D@

1 2

CU7 0.22U_0402_16V7K~D@CU7 0.22U_0402_16V7K~D@

1 2

CU8 0.22U_0402_16V7K~D@CU8 0.22U_0402_16V7K~D@

1 2

CU9 0.22U_0402_16V7K~DDIS@CU9 0.22U_0402_16V7K~DDIS@

1 2

CU10 0.22U_0402_16V7K~DDIS@CU10 0.22U_0402_16V7K~DDIS@

1 2

CU11 0.22U_0402_16V7K~DDIS@CU11 0.22U_0402_16V7K~DDIS@

1 2

CU12 0.22U_0402_16V7K~DDIS@CU12 0.22U_0402_16V7K~DDIS@

1 2

CU13 0.22U_0402_16V7K~DDIS@CU13 0.22U_0402_16V7K~DDIS@

1 2

CU14 0.22U_0402_16V7K~DDIS@CU14 0.22U_0402_16V7K~DDIS@

1 2

CU15 0.22U_0402_16V7K~DDIS@CU15 0.22U_0402_16V7K~DDIS@

1 2

CU16 0.22U_0402_16V7K~DDIS@CU16 0.22U_0402_16V7K~DDIS@

PT

1 2

CU17 0.22U_0402_16V7K~D@CU17 0.22U_0402_16V7K~D@

1 2

CU18 0.22U_0402_16V7K~D@CU18 0.22U_0402_16V7K~D@

1 2

CU19 0.22U_0402_16V7K~D@CU19 0.22U_0402_16V7K~D@

1 2

CU20 0.22U_0402_16V7K~D@CU20 0.22U_0402_16V7K~D@

1 2

CU21 0.22U_0402_16V7K~D@CU21 0.22U_0402_16V7K~D@

1 2

CU22 0.22U_0402_16V7K~D@CU22 0.22U_0402_16V7K~D@

1 2

CU23 0.22U_0402_16V7K~D@CU23 0.22U_0402_16V7K~D@

1 2

CU24 0.22U_0402_16V7K~D@CU24 0.22U_0402_16V7K~D@

1 2

CU25 0.22U_0402_16V7K~DDIS@CU25 0.22U_0402_16V7K~DDIS@

1 2

CU26 0.22U_0402_16V7K~DDIS@CU26 0.22U_0402_16V7K~DDIS@

1 2

CU27 0.22U_0402_16V7K~DDIS@CU27 0.22U_0402_16V7K~DDIS@

1 2

CU28 0.22U_0402_16V7K~DDIS@CU28 0.22U_0402_16V7K~DDIS@

1 2

CU29 0.22U_0402_16V7K~DDIS@CU29 0.22U_0402_16V7K~DDIS@

1 2

CU30 0.22U_0402_16V7K~DDIS@CU30 0.22U_0402_16V7K~DDIS@

1 2

CU31 0.22U_0402_16V7K~DDIS@CU31 0.22U_0402_16V7K~DDIS@

1 2

CU32 0.22U_0402_16V7K~DDIS@CU32 0.22U_0402_16V7K~DDIS@

PEG_ICOMPI and RCOMPO signals should be shorted and routed with max length = 500 mils

- typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

PEG_GTX_C_HRX_N[0..15] PEG_GTX_C_HRX_P[0..15] PEG_HTX_C_GRX_N[0..15] PEG_HTX_C_GRX_P[0..15]

SSI2

PEG_GTX_C_HRX_N[0..15] <24> PEG_GTX_C_HRX_P[0..15] <24>

PEG_HTX_C_GRX_N[0..15] <24> PEG_HTX_C_GRX_P[0..15] <24>

PT

CPU Option

Sandy Bridge 1.6G

U2

SNB1.6G

CPU_SNB1.6G@

Ivy Bridge 1.5G

U2

IVB1.5G

CPU_IVB1.5G@

Ivy Bridge 1.7G

U2

IVB1.7G

CPU_IVB1.7G@

R_COMP place close to CPU

eDP_COMPIO (AF3)

eDP_ICOMPO (AD2)

A A

width 4 mils

width 12 mils

5

R_COMP

VCC_IO

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

7 65Tuesday, February 07, 2012

1

7 65Tuesday, February 07, 2012

0.3

5

H_SNB_IVB#<20>

D D

T15PAD~D@T15PAD~D

ST

H_PECI<20,38>

close to CPU within 0.3" ~ 1.5"

H_PROCHOT#<38,54>

C C

+VCCP

RU30

RU30 62_0402_5%

62_0402_5%

RU32

1 2

56_0402_5%

H_PROCHOT#_R

1 2

0_0402_5%~D

H_CPUPWRGD<20>

close to main route without stub

RU33 10K_0402_5%~DRU33 10K_0402_5%~D

12

Buffered reset to CPU

B B

PLT_RST#<19,38,40,41,42,48>

Follow DG 0.71

AND Gate and its surrounding parts keep 2" ~ 8" with Res 200 & 130 ohm

CPU1.5V_S3_GATE<12,38,58>

A A

PM_DRAM_PWRGD<18>

+3V_PCH

ST

0_0402_5%~D

1 2

RU117

1 2

200_0402_5%~D

RUN_ON_CPU1.5VS3#<12,34>

5

H_CPUPWRGD

PT

ST

CU36

.1U_0402_16V7K

RU62

SHORT

+3VS

1

CU35

0.1U_0402_16V4Z~D

2

5

U3

1

P

NC

4

Y

2

A

G

3

SN74LVC1G07DCKR_SC70-5

+3V_PCH

1

2

U4

U4 74AHC1G09GW_TSSOP5~D

74AHC1G09GW_TSSOP5~D

5

1

P

B

4

O

2

A

G

3

RU118 0_0402_5%~D

1 2

@

2

G

BUFO_CPU_RST# BUF_CPU_RST#

PM_SYS_PWRGD_BUF PM_SYS_PWRGD_BUF_R

12

RU63

RU63 39_0402_5%

39_0402_5%

@

13

D

SSI2

QU2

QU2 2N7002_SOT23-3

2N7002_SOT23-3

S

@

RU31

SHORT

@

+VCCP

12

@RU18

@

1 2

10K_0402_5%~D

H_CATERR#

H_PECI_ISO

H_PROCHOT#_R

H_THERMTRIP#<20>

H_PM_SYNC<18>

H_CPUPWRGD

PM_SYS_PWRGD_BUF_R

BUF_CPU_RST#

RU42

RU42 75_0402_5%

75_0402_5%

RU47

43_0402_1%

1 2

+1.5V_CPU_VDDQ

12

RU18

close to CPU within 1" ~ 2"

12

@

RU55

RU55 0_0402_5%~D

0_0402_5%~D

RU60

RU60 200_0402_5%~D

200_0402_5%~D

RU43

1 2

130_0402_5%

4

F49

C57

C49

A48

C45

D45

C48

B46

BE45

D44

close to CPU within 0.5" ~ 2"

4

U2B

PROC_SELECT#

PROC_DETECT#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

IVY-BRIDGE_BGA1023~D

@

3

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

Place near JXDP1

+VCCP

ST ST

.1U_0402_16V7K

close to SO-DIMM

S

T

1 2

SHORT

DRAMRST_CNTRL_PCH<14,17>

SHORT

RU75 0_0402_5%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

J3 H2

AG3 AG1

N59 N58

AT30

BF44 BE43 BG43

N53 N55

L56

TCK

L55

TMS

J58 M60

TDI

L59

TDO

K58

G58 E55 E59 G55 G59 H60 J59 J61

1

CU33

@

2

4.99K_0402_1%~D

DRAMRST_CNTRL

2

CLK_CPU_DMI <17> CLK_CPU_DMI# <17>

CLK_CPU_DPLL CLK_CPU_DPLL#

CLK_RES_ITP <17> CLK_RES_ITP# <17>

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI_R XDP_TDO_R

XDP_DBRESET#_R

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

.1U_0402_16V7K

The resistor for HOOK2 should be placed such that the stub is very small on CFG0 net.

@ RU71

@

0_0402_5%~D

1 2

S

RU74

1 2

RU38 0_0402_5%~DRU38 0_0402_5%~D

1 2

RU39 0_0402_5%~DRU39 0_0402_5%~D

1 2

RU41 0_0402_5%~DRU41 0_0402_5%~D

T4930PAD~D

@

T4931PAD~D

@

T4932PAD~D

@

T4933PAD~D

@

T4934PAD~D

@

T4935PAD~D

@

T4936PAD~D

@

T4937PAD~D

@

1

CU34

@

2

RU71

D

13

DDR3_DRAMRST#_RH_DRAMRST#

SSI2

G

QU3

2

BSS138-G_SOT23-3

+1.5V

RU72

1K_0402_5%~D

XDP_TDI XDP_TDO

XDP_DBRESET#

H_CPUPWRGD Res 1K, close to JXDP within 0.5" ~ 3"

PBTN_OUT#<18,38>

CFG0<10>

VGATE<18,38,60>

CLK_CPU_ITP<17>

CLK_CPU_ITP#<17>

PCH_JTAG_TDO<16>

PCH_JTAG_TDI<16>

PCH_JTAG_TMS<16>

PCH_JTAG_TCK<16>

12

RU73

RU73 1K_0402_5%~D

1K_0402_5%~D

1 2

ST

1

CU39

CU39 .047U_0402_16V7K

.047U_0402_16V7K

2

Compal Secret Data

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

2

XDP_DBRESET# <18>

H_CPUPWRGD

RU7 1K_0402_5%~D@RU7 1K_0402_5%~D@ RU8 0_0402_5%~D@RU8 0_0402_5%~D@ RU9 1K_0402_5%~D@RU9 1K_0402_5%~D@ RU10 0_0402_5%~D@RU10 0_0402_5%~D@

RU12 1K_0402_5%~D@RU12 1K_0402_5%~D@

RU13 0_0402_5%~D@RU13 0_0402_5%~D@ RU14 0_0402_5%~D@RU14 0_0402_5%~D@

RU19 0_0402_5%~D@RU19 0_0402_5%~D@ RU20 0_0402_5%~D@RU20 0_0402_5%~D@

DDR3_DRAMRST# <14>

1

CLK_CPU_DPLL# CLK_CPU_DPLL

close to CPU within 0.5" RCOMP0 & 1 : trace width = 20mil RCOMP2 : trace width = 15mil spacing = 20mil

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

1 2

RU25 1K_0402_5%~DRU25 1K_0402_5%~D

1 2

RU24 1K_0402_5%~DRU24 1K_0402_5%~D

RU58 140_0402_1%RU58 140_0402_1% RU59 25.5_0402_1%RU59 25.5_0402_1% RU61 200_0402_1%RU61 200_0402_1%

12 12 12

PU/PD for JTAG signals

XDP_TMS XDP_TDI_R XDP_TDO

XDP_TCK XDP_TRST#

XDP_DBRESET#

XDP_PREQ# XDP_PRDY#

1 2 1 2 1 2 1 2

12

12 12

12

1 2

Title

Size Document Number Rev

Custom

Date: Sheet of

H_CPUPWRGD_XDP CFD_PWRBTN#_XDP CFG0_R SYS_PWROK_XDP

XDP_RST#_RPLT_RST# XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_TCK1

XDP_TCK

Compal Electronics, Inc.

PROCESSOR(2/7) PM,XDP,CLK

1 2

RU17 51_0402_5%RU17 51_0402_5%

1 2

RU23 51_0402_5%RU23 51_0402_5%

1 2

RU27 51_0402_5%RU27 51_0402_5%

1 2

RU28 51_0402_5%RU28 51_0402_5%

1 2

RU29 51_0402_5%RU29 51_0402_5%

1 2

RU35 1K_0402_5%~DRU35 1K_0402_5%~D

+VCCP

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

ACES_87152-26051

1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

8 65Tuesday, February 07, 2012

CONN@

JXDP1

G1 G2

27 28

+VCCP

+3VS

0.3

5

U2C

DDR_A_D[0..63]<14>

D D

C C

DDR_A_BS0<14> DDR_A_BS1<14>

B B

DDR_A_BS2<14>

DDR_A_CAS#<14> DDR_A_RAS#<14> DDR_A_WE#<14>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AP11

AJ10

AR11

AT13

AU13

BA13 BB11

AY13 AV14 AR14

AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45

AT48

AY48 BA49 AV49 BB51

AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54

AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37

BF36 BA28

BE39 BD39

AT41

AG6

AP6 AU6 AV9 AR6 AP8

BC7 BB7

BA7 BA9 BB9

AJ6 AL6 AJ8

AL8 AL7

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

4

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 <14> M_CLK_DDR#0 <14> DDR_CKE0_DIMMA <14>

M_CLK_DDR1 <14> M_CLK_DDR#1 <14> DDR_CKE1_DIMMA <14>

DDR_CS0_DIMMA# <14> DDR_CS1_DIMMA# <14>

M_ODT0 <14> M_ODT1 <14>

DDR_A_DQS#[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_MA[0..15] <14>

3

U2D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

2

BA34

SB_CK[0]

AY34

SB_CK#[0]

AR22

SB_CKE[0]

BA36

SB_CK[1]

BB36

SB_CK#[1]

BF27

SB_CKE[1]

BE41

SB_CS#[0]

BE47

SB_CS#[1]

AT43

SB_ODT[0]

BG47

SB_ODT[1]

AL3

SB_DQS#[0]

AV3

SB_DQS#[1]

BG11

SB_DQS#[2]

BD17

SB_DQS#[3]

BG51

SB_DQS#[4]

BA59

SB_DQS#[5]

AT60

SB_DQS#[6]

AK59

SB_DQS#[7]

AM2

SB_DQS[0]

AV1

SB_DQS[1]

BE11

SB_DQS[2]

BD18

SB_DQS[3]

BE51

SB_DQS[4]

BA61

SB_DQS[5]

AR59

SB_DQS[6]

AK61

SB_DQS[7]

DDR SYSTEM MEMORY B

BF32

SB_MA[0]

BE33

SB_MA[1]

BD33

SB_MA[2]

AU30

SB_MA[3]

BD30

SB_MA[4]

AV30

SB_MA[5]

BG30

SB_MA[6]

BD29

SB_MA[7]

BE30

SB_MA[8]

BE28

SB_MA[9]

BD43

SB_MA[10]

AT28

SB_MA[11]

AV28

SB_MA[12]

BD46

SB_MA[13]

AT26

SB_MA[14]

AU22

SB_MA[15]

1

IVY-BRIDGE_BGA1023~D

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

IVY-BRIDGE_BGA1023~D

@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

1

0.3

9 65Tuesday, February 07, 2012

0.3

5

U2E

CFG0<8>

T18PAD~D@T18PAD~D T17PAD~D@T17PAD~D

D D

follow "458544_CR_PDDG_rev_0.8", section "2.2.1", Intel recommends providing accessibility to the pins F48 & G48 for debug purpose. The pins should be via through to the backside of the board to allow backside probing with no connection to other

C C

rails/components on the platform.

RU83

1K_0402_1%~D

T16PAD~D@T16PAD~D T21PAD~D@T21PAD~D T22PAD~D@T22PAD~D T4917PAD~D@T4917PAD~D T28PAD~D@T28PAD~D T29PAD~D@T29PAD~D T30PAD~D@T30PAD~D T31PAD~D@T31PAD~D T23PAD~D@T23PAD~D T20PAD~D@T20PAD~D

T24PAD~D@T24PAD~D

CFG0 CFG1

@

CFG2 CFG3

@

CFG4 CFG5 CFG6 CFG7 CFG8

@

CFG9

@

CFG10

@

CFG11

@

CFG12

@

CFG13

@

CFG14

@

CFG15

@

CFG16

@

CFG17

@

As PDDG rev0.8, VCC_VAL_SENSE & VAXG_VAL_SENSE are removed.

@

CPU_RSVD6 CPU_RSVD7

12

RU84

RU84 1K_0402_1%~D

1K_0402_1%~D

NAR00 pull down 12/28/09

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

4

RESERVED

RSVD28 RSVD29

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

BE7 BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

3

CFG Straps for Processor

+V_DDR_REFA_M3 <14>

CFG2 CFG4 CFG5 CFG6 CFG7

PCI Express* Static x16 Lane Numbering Reversal

PCI Express* Static x4 Lane Numbering Reversal

eDP enable PEG DEFER TRAINING

PCI Express Bifurcation (x16 Lane)

follow "452823_COUGAR_CANYON(BGA1023)_Customer_Ready_Schematic". It's for Huron River platform, since can't find CPU Ivy bridge BGA1023 schematic for Chief River at this moment.

1 2

RU77 1K_0402_1%~DRU77 1K_0402_1%~D

1 2

RU78 1K_0402_1%~D@RU78 1K_0402_1%~D@

ST

1 2

RU85 1K_0402_1%~D@RU85 1K_0402_1%~D@

1 2

RU86 1K_0402_1%~D@RU86 1K_0402_1%~D@

1 2

RU87 1K_0402_1%~D@RU87 1K_0402_1%~D@

SSI2

CFG2

CFG3 CFG4 CFG7

1 x16 PCI Express (Default value)11

10

2 x8 PCI Express

CFG[6:5]

01

reserved 1 x8, 2 x4 PCI Express

00

2

1 (Default value) 0

Normal operation (match socket pin map)

Disable PEG Train immediately

following RESETB de-assertion

Lane numbers reversed

Enable PEG Wait for

BIOS for training

1

IVY-BRIDGE_BGA1023~D

@

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

10 65Tuesday, February 07, 2012

1

10 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] VCCIO[9]

VCCIO50 VCCIO51

VIDSCLK

VIDSOUT

4

+VCCP decoupling Cap. in Page 62.

+VCCP

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

8.5A

+VCCP

1

CU40

CU40 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

@

+VCCP

1

CU94

CU94 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

H_CPU_SVIDALRT#

VCCSENSE_R VSSSENSE_R

VCCIO_SENSE_R VSS_SENSE_VCCIO

As 473716_Ivy_Bridge_EDS(1 of 2)_Mobile_rev1.5,

T25 PAD~D

Page 92, VCCIO_SEL, "For Chief River platforms this pin should not be used"

RU94 43_0402_1%RU94 43_0402_1%

RU92 130_0402_5%RU92 130_0402_5%

1 2

RU100 10_0402_1%~DRU100 10_0402_1%~D

12

RU103

RU103 10_0402_1%~D

10_0402_1%~D

Issued Date

+VCCP

12

RU93

RU93 75_0402_5%

75_0402_5%

+VCCP

VCCIO_SENSE <57> VSSIO_SENSE <57>

3

VR_SVID_ALRT# <60> VR_SVID_CLK <60> VR_SVID_DAT <60>

+VCC_CORE

RU97

RU97 100_0402_1%~D

100_0402_1%~D

1 2

12

RU102

RU102 100_0402_1%~D

100_0402_1%~D

2011/07/15 2012/07/15

close to CPU within 2"

VCCSENSE <60> VSSSENSE <60>

Compal Secret Data

Deciphered Date

2

close to CPU

ithin 0.3" ~ 1.5"

w

1 2

12

close to CPU within 0.3" ~ 1.5"

close to CPU within 2"

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

11 65Tuesday, February 07, 2012

1

11 65Tuesday, February 07, 2012

0.3

POWER

U2F

+VCC_CORE decoupling Cap. in Page 62.

+VCC_CORE

33A

ULV 17W , Max Current

D D

C C

B B

A A

in Turbo Mode or HFM

5

U2F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023~D

@

POWER

CORE SUPPLY

VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32]

PEG IO AND DDR IO

VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

RAILS

VIDALERT#

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

5

4

3

2

1

RU105 1K_0402_1%~D

1 2

RU107 1K_0402_1%~D

+VCC_GFXCORE_AXG decoupling Cap. in Page 62.

D D

+VCC_GFXCORE_AXG

33A

ULV GT2 , Max Current in Turbo Mode

C C

close to CPU w

ithin 2"

RU114

+VCC_GFXCORE_AXG

B B

A A

VCC_AXG_SENSE<60>

VSS_AXG_SENSE<60>

+VCCSA

Intel PDDG rev0.8 :

30uF x 1 - Bottom CPU edge

3 10uF x 5 - Bottom CPU edge 1uF x 5 - Under CPU

5

ST

Intel PDDG rev0.8 : 330uF x 1 - Bottom CPU edge 1uF x 2 - Top CPU edge

330U_D2_2V_Y

CU142

1

+

2

1 2

RU122 0_0402_5%~D

SHORT

RU122 0_0402_5%~D

SHORT

1 2

RU123 0_0402_5%~D

SHORT

RU123 0_0402_5%~D

SHORT

ST

+1.8VS

10U_0603_6.3V6M~D

CU143

1

2

1U_0402_6.3V6K~D

CU146

1

2

RU116

0_0805_5%~D

1 2

SHORT

CU144

CU147

1 2

100_0402_1%~D

VCC_AXG_SENSE_R VSS_AXG_SENSE_R

RU115

1 2

100_0402_1%~D

+1.8VS_VCCPLL

CU138

330U_D2_2.5VY_R9M~D+CU138

330U_D2_2.5VY_R9M~D

CU140

1U_0402_6.3V6K~D

CU140

1U_0402_6.3V6K~D

CU141

1U_0402_6.3V6K~D

CU141

1

+

2

10U_0603_6.3V6M~D

CU149

CU145

1

2

1U_0402_6.3V6K~D

CU148

CU151

1

2

CU151

1

2

1U_0402_6.3V6K~D

1

2

10U_0603_6.3V6M~D

CU150

1

2

1U_0402_6.3V6K~D

CU152

1

2

4

1.5A

6A

U2G

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023~D

@

POWER

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

+SM_VREF

ST

AY43

SM_VREF

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0] VCCSA_VID[1]

lines

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

.1U_0402_16V7K

5A

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

CU97

100K_0402_5%~D

+1.5V_VCCDQ

VCCSA_SENSE <59>

VCCSA_VID0 <59> VCCSA_VID1 <59>

2011/07/15 2012/07/15

RU107 1K_0402_1%~D

1

2

12

RU121

@

1U_0402_6.3V6K~D

CU98

1

2

1

2

1 2

0_0603_5%~D

0_0402_5%~D

@RU104

@

0_0402_5%~D

3

1U_0402_6.3V6K~D

CU99

10U_0603_6.3V6M~D

CU109

RU125

+1.5V_CPU_VDDQ

12

@

@ @

@

RU120

RU104

+1.5V_CPU_VDDQ

Compal Secret Data

+0.75VS

12

+V_DDR_REFA

12 1

SSI2

QU4

@QU4

@

AP2302GN-HF_SOT23-3

2

RUN_ON_CPU1.5VS3

1U_0402_6.3V6K~D

CU100

1

2

10U_0603_6.3V6M~D

CU110

1

2

VID[0] VID[1] 2011 2012 0 0 0.90 V Yes Yes 0 1 0.85 V Yes Yes 1 0 0.725 V No Yes 1 1 0.675 V No Yes

1U_0402_6.3V6K~D

CU101

CU102

1

2

10U_0603_6.3V6M~D

CU111

CU112

1

2

1

CU137

CU137 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

CPU1.5V_S3_GATE<8,38,58>

SUSP#<34,38,56,57,58>

Deciphered Date

1

2

1

2

VREF traces should have 2

0 mil trace width &

spacing to other signals

1U_0402_6.3V6K~D

CU104

1

2

10U_0603_6.3V6M~D

CU114

1

2

100K_0402_5%~D

RU112

RU112 0_0402_5%~D

0_0402_5%~D

1 2

RU113

@RU113

@

0_0402_5%~D

1 2

ST

CU155

.1U_0402_16V7K

2

1U_0402_6.3V6K~D

CU105

10U_0603_6.3V6M~D

CU115

RU110

@

CU103

10U_0603_6.3V6M~D

CU113

+1.5V_CPU_VDDQ +1.5V

12 12 12 12

+VSBP

12

RU108

RU108 100K_0402_5%~D

100K_0402_5%~D

RUN_ON_CPU1.5VS3

34

QU6B

QU6B 2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

RUN_ON_CPU1.5VS3# <8,34>

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

1

2

1

2

1

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

2

CU106

CU116

+3VALW

12

61

CU95 0.1U_0402_10V7KCU95 0.1U_0402_10V7K CU96 0.1U_0402_10V7KCU96 0.1U_0402_10V7K CU153 0.1U_0402_10V7KCU153 0.1U_0402_10V7K CU154 0.1U_0402_10V7KCU154 0.1U_0402_10V7K

1U_0402_6.3V6K~D

CU107

1

Intel PDDG rev0.8 : 330uF x 1 - Bottom CPU edge

2

10uF x 8 - Bottom CPU edge 1uF x 10 - Under CPU

330U_D2_2V_Y

CU117

1

+

2

5

QU6A

QU6A 2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

Custom

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

QU5

AO4728L_SO8

8 7 6 5

RU111

330K_0402_5%

4

12

1

CU136

0.1U_0402_25V6K~D

2

1

1 2 3

12 65Tuesday, February 07, 2012

0.3

5

U2H

D D

C C

B B

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AD17 AD20

AD61 AE13

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58

AF59 AG10 AG14 AG18 AG47 AG52 AG61

AH58

AJ13

AJ16

AJ20

AJ22

AJ26

AJ30

AJ34

AJ38

AJ42

AJ45

AJ48

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61

AM13 AM20 AM22 AM26 AM30 AM34

AC6

AD4

AE8 AF1

AG7 AH4

AK1

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20]

AA8

VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69]

AJ7

VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

VSS

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

4

U2I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G51

VSS[221]

G6

VSS[222]

G61

VSS[223]

H10

VSS[224]

H14

VSS[225]

H17

VSS[226]

H21

VSS[227]

H4

VSS[228]

H53

VSS[229]

H58

VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233]

K11

VSS[234]

K21

VSS[235]

K51

VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247]

M11

VSS[248]

M15

VSS[249]

IVY-BRIDGE_BGA1023~D

@

VSS

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11

NCTF

VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

3

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

RU119

1 2

0_0402_5%~D@

Dell short to ground

2

follow "458544_CR_PDDG_rev_0.8", section "2.2.1", Intel recommends providing accessibility to the pins F48 & G48 for debug purpose. The pins should be via through to the backside of the board to allow backside probing with no connection to other rails/components on the platform.

1

A A

IVY-BRIDGE_BGA1023~D

@

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

1

0.3

13 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

+0.75VS

+1.5V

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

BELLW_80001-1021

DQS0#

RESET#

DQS3#

VREF_CA

DQS5#

DQS7#

EVENT#

GND2

BOSS2

DDR_A_DQS#[0..7]<9>

DDR_A_DQS[0..7]<9> DDR_A_D[0..63]<9> DDR_A_MA[0..15]<9>

D D

M1 Circuit (Voltage Divider)

+1.5V

12

RD2

RD2 1K_0402_1%~D

1K_0402_1%~D

12

RD3

RD3 1K_0402_1%~D

1K_0402_1%~D

+V_DDR_REFA

M3+M1: Default Recommendation

All VREF traces should have 20mil trace width & spacing

+V_DDR_REFA

2.2U_0603_6.3V6K~D

1

CD1

2

0.1U_0402_16V7K~D

1

CD2

2

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

1 2

RD6 0_0402_5%~D@RD6 0_0402_5%~D@

QD1 BSS138-G_SOT23-3

1 3

D

S

D

+V_DDR_REFA

DRAMRST_CNTRL_PCH<8,17>

S

SSI2

G

2

close to SO-DIMM

C C

+1.5V

1U_0402_6.3V6K~D

+1.5V

10U_0603_6.3V6M~D

B B

+0.75VS

A A

CD4

CD3

1

2

10U_0603_6.3V6M~D

CD8

CD9

1

2

1U_0402_6.3V6K~D

1

CD17

2

1U_0402_6.3V6K~D

CD10

1

2

CD18

CD6

CD5

1

2

10U_0603_6.3V6M~D

CD12

CD11

1

2

1U_0402_6.3V6K~D

1

CD19

CD20

2

ST

330U_D2_2.5VM_R6M~D

10U_0603_6.3V6M~D

330U_D2_2.5VM_R6M~D

1

CD7

CD13

1

+

2

12

RD10

RD10 1K_0402_5%~D

1K_0402_5%~D

@

+V_DDR_REFA_M3 <10>

DDR_CKE0_DIMMA<9> DDR_CKE1_DIMMA <9>

DDR_A_BS2<9>

M_CLK_DDR0<9> M_CLK_DDR#0<9>

DDR_A_BS0<9> DDR_A_WE#<9>

DDR_A_CAS#<9>

DDR_CS1_DIMMA#<9>

1 2

+3VS

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D CD22

CD22

1

2

CD21

1

2

RD8 10K_0402_5%~DRD8 10K_0402_5%~D

1 2

RD9 10K_0402_5%~DRD9 10K_0402_5%~D

VSS DQ4 DQ5 VSS

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1 RAS#

VDD

ODT0

VDD

ODT1

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS DQS7

VSS DQ62 DQ63

VSS

SDA

SCL

VTT

+1.5V

2 4

DDR_A_D4

6

DDR_A_D5

8 10

DDR_A_DQS#0

12

DDR_A_DQS0

14 16

DDR_A_D6

18

DDR_A_D7

20 22

DDR_A_D12

24

DDR_A_D13

26 28 30 32 34

DDR_A_D14

36

DDR_A_D15

38 40

DDR_A_D20

42

DDR_A_D21

44 46 48 50

DDR_A_D22

52

DDR_A_D23

54 56

DDR_A_D28

58

DDR_A_D29

60 62

DDR_A_DQS#3

64

DDR_A_DQS3

66 68

DDR_A_D30

70

DDR_A_D31

72

74 76 78

A15 A14

A11

A7 A6

A4 A2

A0

S0#

NC

DDR_A_MA15

80

DDR_A_MA14

82 84

DDR_A_MA11

86

DDR_A_MA7

88 90

DDR_A_MA6

92

DDR_A_MA4

94 96

DDR_A_MA2

98

DDR_A_MA0

100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130

DDR_A_D36

132

DDR_A_D37

134 136 138 140

DDR_A_D38

142

DDR_A_D39

144 146

DDR_A_D44

148

DDR_A_D45

150 152

DDR_A_DQS#5

154

DDR_A_DQS5

156 158

DDR_A_D46

160

DDR_A_D47

162 164

DDR_A_D52

166

DDR_A_D53

168 170 172 174

DDR_A_D54

176

DDR_A_D55

178 180

DDR_A_D60

182

DDR_A_D61

184 186

DDR_A_DQS#7

188

DDR_A_DQS7

190 192

DDR_A_D62

194

DDR_A_D63

196 198 200 202 204

+0.75VS

206 208

DDR3_DRAMRST# <8>

M_CLK_DDR1 <9> M_CLK_DDR#1 <9>

DDR_A_BS1 <9> DDR_A_RAS# <9>

DDR_CS0_DIMMA# <9> M_ODT0 <9>

M_ODT1 <9>

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

CD16

1

2

PCH_SMBDATA <17,39,43,48> PCH_SMBCLK <17,39,43,48>

+VREF_CA

CD15

+1.5V

12

RD4

RD4 1K_0402_1%~D

1K_0402_1%~D

12

RD5

RD5 1K_0402_1%~D

1K_0402_1%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

DDRIII DIMMA LA-7841P

LA-7841P

1

0.3

14 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

intent to blank

D D

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

DDRIII DIMMB LA-7841P

LA-7841P

1

0.3

15 65Tuesday, February 07, 2012

0.3

5

1 2

RH1 10M_0402_5%RH1 10M_0402_5%

1 2

YH1

32.768KHZ_12.5PF_9H03200019

15P_0402_50V8J~D

SSI2

1

CH3

2

D D

PT

far away hot spot

HDA_BITCLK_AUDIO<48>

HDA_RST_AUDIO#<48>

HDA_SYNC_AUDIO<48>

HDA_SDOUT_AUDIO<48>

C C

B B

12

RH19

200_0402_5%~D

@

12

RH25

RH25 100_0402_1%~D

100_0402_1%~D

HDA_SDO<38>

+3VS

PCH_JTAG_TCK

+3V_PCH +3V_PCH+3V_PCH

PCH_RTCX1 PCH_RTCX2

1

CH4

CH4 18P_0402_50V8J~D

18P_0402_50V8J~D

2

1 2

RH5

1 2

RH6

1 2

RH7

1 2

RH8

1 2

RH15

1 2

RH11

for enable ME code programing

1 2

RH251 8.2K_0402_5%~DRH251 8.2K_0402_5%~D

1 2

RH35 51_0402_5%RH35 51_0402_5%

12

RH20

200_0402_5%~D

@

PCH_JTAG_TDI PCH_JTAG_TDOPCH_JTAG_TMS

12

RH26

100_0402_1%~D

12

+RTCVCC

RH2

1 2

1M_0402_5%~D

CH5

+RTCVCC

HDA_BIT_CLK

33_0402_5%~D

HDA_SYNC_R HDA_SYNC

33_0402_5%~D

1M_0402_5%~D

HDA_SDOUT

33_0402_5%~D

1K_0402_5%~D

USB_WWAN_DET#

RH18

200_0402_5%~D

@

RH24

100_0402_1%~D

CH5

1U_0402_6.3V6K~D

1 2

RH3 20K_0402_5%~DRH3 20K_0402_5%~D

1 2

RH4 20K_0402_5%~DRH4 20K_0402_5%~D

CH6

1U_0402_6.3V6K~D

HDA_RST#

BSS138-G_SOT23-3

Reserve for RF, close to PCH

+5VS

G

2

S

QH1

SSI2

CH14

10P_0402_50V8J~D@

1

12

2

1

12

2

13

D

USB_WWAN_DET#<48>

12

SM_INTRUDER#

CLP1 & CLP2 place near DIMM

E CMOS

M

CLRP1

@CLRP1

@

SHORT PADS

ME CMOS

CLRP2

@CLRP2

@

SHORT PADS

HDA_SPKR<48>

HDA_SDIN0<48>

PCH_JTAG_TCK<8> PCH_JTAG_TMS<8> PCH_JTAG_TDI<8> PCH_JTAG_TDO<8>

PCH_SPI_CLK

PCH_RTCX1 PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#

HDA_SDOUT

USB_WWAN_DET#

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_SI PCH_SPI_SO

T4921PAD~D @T4921PAD~D @

4

CH1 10P_0402_50V8J~D

CH2 10P_0402_50V8J~D

Reserve for RF, close to PCH

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

BD82PPSM-QNHN-A0_BGA989~D

@

12

RTCIHDA

JTAG

SPI

HDA_SDOUT

HDA_BIT_CLK

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19

LDRQ0#

SERIRQ

C38 A38 B37 C37

D36 E36

K36

RH10 10K_0402_5%~DRH10 10K_0402_5%~D

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

SATA_COMP

AB12 AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

BBS_BIT0 <19>

3

LPC_AD0 <38,40,42> LPC_AD1 <38,40,42> LPC_AD2 <38,40,42> LPC_AD3 <38,40,42>

LPC_FRAME# <38,40,42>

12

SERIRQ <38,40>

SATA_PRX_DTX_N0 <43> SATA_PRX_DTX_P0 <43> SATA_PTX_DRX_N0 <43> SATA_PTX_DRX_P0 <43>

SATA_PRX_DTX_N1 <43> SATA_PRX_DTX_P1 <43> SATA_PTX_DRX_N1 <43> SATA_PTX_DRX_P1 <43>

close PCH within 500mil

1 2

RH21 37.4_0402_1%RH21 37.4_0402_1%

1 2

RH22 49.9_0402_1%RH22 49.9_0402_1%

1 2

RH28 750_0402_1%~DRH28 750_0402_1%~D

RH14 10K_0402_5%~D@RH14 10K_0402_5%~D@ RH12 10K_0402_5%~DRH12 10K_0402_5%~D RH29 10K_0402_5%~DRH29 10K_0402_5%~D

+3VS

+VCCP

12 12 12

+3VS

W=20mils

HDD

mSATA

RTC Battery

+RTCBATT

+3VLP

3

1

2

RH34

RH34 1K_0402_5%~D

1K_0402_5%~D

1 2 2

DH1

DH1 BAT54CW_SOT323-3

BAT54CW_SOT323-3

+RTCVCC

CH12

CH12 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

SATA Gen3 topology, AC cap close to device within 200mil

2

PCH_INTVRMEN

Integrated 1.05V VRM Enable / Disable (should always be pulled high to VccRTC)

INTVRMEN

HDA_SYNC

PLL ODVR VOLTAGE (Internal PD 20K)

HDA_SYNC

HDA_SPKR

No Reboot strap (Internal PD 20K)

SPKR

HDA_SDOUT

Flash Descriptor Security Override / Intel ME Debug Mode (Internal PD 20K)

HDA_SDO

1

RH13 330K_0402_5%RH13 330K_0402_5% RH16 330K_0402_5%@RH16 330K_0402_5%@

Low = X High = enable

RH32 1K_0402_5%~DRH32 1K_0402_5%~D

LOW = SET VCCVRM TO 1.8 V (DEFAULT)

HIGH = SET VCCVRM TO 1.5 V

RH17 1K_0402_5%~D@RH17 1K_0402_5%~D@

Low = Default High = No Reboot

RH23 1K_0402_5%~D@RH23 1K_0402_5%~D@

LOW = Secure HIGH = Override

12 12

12

+RTCVCC

+3V_PCH

+3VS

+3V_PCH

RH41

SPI BIOS Pinout

1)CS# (5)DIO

( (2)DO (6)CLK (3)WP# (7)HOLD# (4)GND (8)VCC

W25X32

@RH41

@

1 2

12

22P_0402_50V8J~D

CH13

@CH13

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC LA-7841P

LA-7841P

1

16 65Tuesday, February 07, 2012

0.3

SPI ROM FOR BIOS & EC ( 8MByte )

+3V_PCH

8 7 6 5

12

RH40

3.3K_0402_5%

PCH_SPI_CLK PCH_SPI_SI

Reserve for EMI, close to UH2

PCH_SPI_CLK

33_0402_5%~D

12

RH33

RH38

1 2

RH38

3.3K_0402_5%

PCH_SPI_CS0# PCH_SPI_SO

A A

1

ST

CH11

CH11 .1U_0402_16V7K

.1U_0402_16V7K

2

UH2

1

/CS

2

DO

/HOLD

3

/WP GND4DIO

W25Q64CVSSIG_SO8~D

5

VCC

CLK

5

PCIE_PRX_GLANTX_N1<41>

10/100/1G LAN

D D

MiniWLAN (Mini Card 1)

CARD_READER

C C

10/100/1G LAN

MiniWLAN (Mini Card 1)

CARD_READER

B B

A A

PCIE_PRX_GLANTX_P1<41> PCIE_PTX_GLANRX_N1<41> PCIE_PTX_GLANRX_P1<41>

PCIE_PRX_WLANTX_N3<42> PCIE_PRX_WLANTX_P3<42> PCIE_PTX_WLANRX_N3<42> PCIE_PTX_WLANRX_P3<42>

PCIE_PRX_CARDTX_N4<48> PCIE_PRX_CARDTX_P4<48> PCIE_PTX_CARDRX_N4<48> PCIE_PTX_CARDRX_P4<48>

CLK_PCIE_LAN#<41> CLK_PCIE_LAN<41>

LANCLK_REQ#<41>

CLK_PCIE_MINI1#<42> CLK_PCIE_MINI1<42>

MINI1CLK_REQ#<42>

CLK_PCIE_CD#<48> CLK_PCIE_CD<48>

CDCLK_REQ#<48>

CLK_CPU_ITP#<8> CLK_CPU_ITP<8>

CLK_RES_ITP#<8> CLK_RES_ITP<8>

1 2

CH15 0.1U_0402_10V7K~DCH15 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~DCH16 0.1U_0402_10V7K~D

1 2

CH19 0.1U_0402_10V7K~DCH19 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~DCH20 0.1U_0402_10V7K~D

1 2

CH21 0.1U_0402_10V7K~DCH21 0.1U_0402_10V7K~D

1 2

CH22 0.1U_0402_10V7K~DCH22 0.1U_0402_10V7K~D

RH66 10K_0402_5%~DRH66 10K_0402_5%~D

+3V_PCH

RH69 10K_0402_5%~DRH69 10K_0402_5%~D

+3VS

RH74 10K_0402_5%~DRH74 10K_0402_5%~D

+3VS

RH77 10K_0402_5%~DRH77 10K_0402_5%~D

+3V_PCH

RH81 10K_0402_5%~DRH81 10K_0402_5%~D

+3V_PCH

RH83 10K_0402_5%~DRH83 10K_0402_5%~D

+3V_PCH

RH84 10K_0402_5%~DRH84 10K_0402_5%~D

+3V_PCH

RH88 10K_0402_5%~DRH88 10K_0402_5%~D

+3V_PCH

RH90 10K_0402_5%~DRH90 10K_0402_5%~D

+3V_PCH

PT2

RH91 0_0402_5%~D@RH91 0_0402_5%~D@ RH92 0_0402_5%~D@RH92 0_0402_5%~D@

RH93 0_0402_5%~D@RH93 0_0402_5%~D@ RH94 0_0402_5%~D@RH94 0_0402_5%~D@

1 2

4

12

12 12

PCIE_PTX_GLANRX_N1_C PCIE_PTX_GLANRX_P1_C

PCIE_PTX_WLANRX_N3_C PCIE_PTX_WLANRX_P3_C

PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C

T2PAD~D @T2PAD~D @ T3PAD~D @T3PAD~D @

PCIECLKREQ0#

PCH_GPIO20

PCH_GPIO44

PEG_B_CLKREQ#

PCH_GPIO45

PCH_GPIO46 CLK_BCLK_ITP#

CLK_BCLK_ITP

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

BD82PPSM-QNHN-A0_BGA989~D

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

E12

PCH_LID_SW_IN#

H14

SMBCLK

C9

SMBDATA

A12

DRAMRST_CNTRL_PCH

C8

SML0CLK

G12

SML0DATA

C13

PCH_GPIO74

E14

SML1CLK

M16

SML1DATA

M7

connects to a Wireless LAN Device supporting Intel Active Management Technology(iAMT)

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18

CLKIN_DMI#

BE18

CLKIN_DMI

BJ30 BG30

G24

CLKIN_DOT96#

E24

CLKIN_DOT96

AK7

CLKIN_SATA#

AK5

CLKIN_SATA

K45

CLK_PCH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

CLKOUTFLEX0 CLK_PCI_TPM

F47

KB_DET#

H47

CLKOUTFLEX2

K49

SSI2

KB_DET#

ST

1 2

SHORT

RH44 0_0402_5%~D

+3V_PCH

RH64

RH64 10K_0402_5%~D

10K_0402_5%~D

1 2

T26 PAD~D@ T26 PAD~D@ T27 PAD~D@ T27 PAD~D@

CLKIN_GND1

1 2

RH85 90.9_0402_1%RH85 90.9_0402_1%

1 2

RH97

1 2

RH245

@RH245

@

Remove CAM_DET#

RH98 100K_0402_5%~DRH98 100K_0402_5%~D

12

SMBCLK <42> SMBDATA <42>

DRAMRST_CNTRL_PCH <8,14>

PEG_A_CLKRQ# <24>

CLK_PEG_VGA# <24> CLK_PEG_VGA <24>

CLK_CPU_DMI# <8> CLK_CPU_DMI <8>

22_0402_1%

2

CLK_PCI_LPBACK <19>

+VCCP

KB_DET# <39>

+3VS

EC_LID_OUT# <38>

PCH <-> MEM, LCD, TP, WLAN, FFS, IO

CLK_PCI_TPM <40>

LAN_25M <41>

6 1

SMBCLK

DMN66D0LDW-7_SOT363-6~D

1 2

0_0402_5%~D

SMBDATA

PCH <-> EC

SML1CLK

SML1DATA

ST

6 1

DMN66D0LDW-7_SOT363-6~D

option for LAN 25MHz

SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA PCH_LID_SW_IN#

DRAMRST_CNTRL_PCH

PCH_GPIO74

+3VS +3VS

2.2K_0402_5%~D

2

QH2A

RH78

@

DMN66D0LDW-7_SOT363-6~D

@

QH3A

DMN66D0LDW-7_SOT363-6~D

+3VS

2

5

3

4

QH2B

RH82

1 2

@

0_0402_5%~D

PT

5

3

4

@

QH3B

CLKIN_DMI# CLKIN_DMI CLKIN_GND1 CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

P

T PT

1

1 2

RH45 2.2K_0402_5%~DRH45 2.2K_0402_5%~D

1 2

RH46 2.2K_0402_5%~DRH46 2.2K_0402_5%~D

1 2

RH47 2.2K_0402_5%~DRH47 2.2K_0402_5%~D

1 2

RH49 2.2K_0402_5%~DRH49 2.2K_0402_5%~D

1 2

RH50 2.2K_0402_5%~DRH50 2.2K_0402_5%~D

1 2

RH51 2.2K_0402_5%~DRH51 2.2K_0402_5%~D

1 2

RH52 10K_0402_5%~DRH52 10K_0402_5%~D

1 2

RH53 1K_0402_5%~DRH53 1K_0402_5%~D

1 2

RH240 10K_0402_5%~DRH240 10K_0402_5%~D

RH71

RH72

2.2K_0402_5%~D

1 2

PCH_SMBCLK <14,39,43,48>

PCH_SMBDATA <14,39,43,48>

PCH_SMLCLK <24,35,38>

PCH_SMLDATA <24,35,38>

1 2

RH56 10K_0402_5%~DRH56 10K_0402_5%~D

1 2

RH57 10K_0402_5%~DRH57 10K_0402_5%~D

1 2

RH55 10K_0402_5%~DRH55 10K_0402_5%~D

1 2

RH58 10K_0402_5%~DRH58 10K_0402_5%~D

1 2

RH59 10K_0402_5%~DRH59 10K_0402_5%~D

1 2

RH60 10K_0402_5%~DRH60 10K_0402_5%~D

1 2

RH61 10K_0402_5%~DRH61 10K_0402_5%~D

1 2

RH62 10K_0402_5%~DRH62 10K_0402_5%~D

ST

RH65

33_0402_5%~D

RH65

CLK_PCI_LPBACK

Reserve for EMI, close to PCH

12

RH891M_0402_5%~D RH891M_0402_5%~D

YH2

1

IN

OUT

2

GND

1

25MHZ_18PF_X3G025000DI1H-H~D

15P_0402_50V8J~D

CH27

2

GND

SSI2

ST

CLK_PCI_TPM

1 2

CH98 10P_0402_50V8J~DCH98 10P_0402_50V8J~D

+3V_PCH

CH26

1 2

12

22P_0402_50V8J~D

XTAL25_IN XTAL25_OUT

3 4

1

2

15P_0402_50V8J~D

CH28

Reserve for EMI, close to PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK LA-7841P

LA-7841P

1

17 65Tuesday, February 07, 2012

0.3

5

UH1C

DMI_CTX_PRX_N0<7> DMI_CTX_PRX_N1<7> DMI_CTX_PRX_N2<7> DMI_CTX_PRX_N3<7>

DMI_CTX_PRX_P0<7> DMI_CTX_PRX_P1<7> DMI_CTX_PRX_P2<7> DMI_CTX_PRX_P3<7>

DMI_CRX_PTX_N0<7>

D D

4mil width and close PCH within 500mil

XDP_DBRESET#<8>

C C

PM_DRAM_PWRGD<8>

PCH_RSMRST#<38>

SUSPWRDNACK<38>

PT

PBTN_OUT#<8,38>

AC_PRESENT<38>

B B

PCH_GPIO72 RI# WAKE# AC_PRESENT SUSPWRDNACK

P

T

PCH_RSMRST# SYS_PWROK

+1.05VS_VCC_EXP

PCH_PWROK

1 2

RH116 10K_0402_5%~DRH116 10K_0402_5%~D

1 2

RH117 10K_0402_5%~DRH117 10K_0402_5%~D

1 2

RH118 10K_0402_5%~DRH118 10K_0402_5%~D

1 2

RH121 10K_0402_5%~DRH121 10K_0402_5%~D

1 2

RH124 10K_0402_5%~DRH124 10K_0402_5%~D

1 2

RH127 10K_0402_5%~DRH127 10K_0402_5%~D

1 2

RH130 10K_0402_5%~DRH130 10K_0402_5%~D

DMI_CRX_PTX_N1<7> DMI_CRX_PTX_N2<7> DMI_CRX_PTX_N3<7>

DMI_CRX_PTX_P0<7> DMI_CRX_PTX_P1<7> DMI_CRX_PTX_P2<7> DMI_CRX_PTX_P3<7>

1 2

RH99 49.9_0402_1%RH99 49.9_0402_1%

1 2

RH100 750_0402_1%~DRH100 750_0402_1%~D

RH104 0_0402_5%~D

RH105 0_0402_5%~D

RH106 0_0402_5%~D

ST

T

S

PCH_RSMRST# PCH_RSMRST#_R

RH108 0_0402_5%~D

SUSPWRDNACK

RH110 0_0402_5%~D

AC_PRESENT

RH112 0_0402_5%~D

ST

T4924PAD~D@T4924PAD~D

@

1 2

@

1 2

SHORT

1 2

SHORT

1 2

SHORT

1 2

SHORT

1 2

SHORT

+3V_PCH

DMI_IRCOMP RBIAS_CPY

SUSACK#

SYS_PWROK

PM_PWROK_R SUS_STAT#

APWROK_R

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82PPSM-QNHN-A0_BGA989~D

DSWODVREN

Deep S4/S5 Well On-Die Voltage Regulator Enable

DSWVRMEN

4

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

DMI

System Power Management

RH119 330K_0402_5%RH119 330K_0402_5% RH122 330K_0402_5%@RH122 330K_0402_5%@

ow = disable

L

FDI_RXP7

FDI

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

12 12

High = enable

+RTCVCC

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

SSI2

A18

DSWODVREN

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

1 2

WAKE#

SHORT

RH103 0_0402_5%~D

PM_CLKRUN#

ST

SUSCLK_R

RH107 0_0402_5%~D

SLP_A#

PM_SLP_SUS#

SUSCLK_R

Reserve for RF, close to PCH

FDI_CTX_PRX_N0 <7> FDI_CTX_PRX_N1 <7> FDI_CTX_PRX_N2 <7> FDI_CTX_PRX_N3 <7> FDI_CTX_PRX_N4 <7> FDI_CTX_PRX_N5 <7> FDI_CTX_PRX_N6 <7> FDI_CTX_PRX_N7 <7>

FDI_CTX_PRX_P0 <7> FDI_CTX_PRX_P1 <7> FDI_CTX_PRX_P2 <7> FDI_CTX_PRX_P3 <7> FDI_CTX_PRX_P4 <7> FDI_CTX_PRX_P5 <7> FDI_CTX_PRX_P6 <7> FDI_CTX_PRX_P7 <7>

FDI_INT <7> FDI_FSYNC0 <7> FDI_FSYNC1 <7> FDI_LSYNC0 <7> FDI_LSYNC1 <7>

1 2

SHORT

RH101 0_0402_5%~D

T5 PAD~D

@

@RH105 0_0402_5%~D

SHORT

T4938 PAD~D

@

T4927 PAD~D

@

H_PM_SYNC <8>

@

ST

12

PM_SLP_S5# <38>

PM_SLP_S4# <38>

PM_SLP_S3# <38,43>

PT

CH29

12

10P_0402_50V8J~D

3

+3VS

PCH_RSMRST#_RPCH_DPWROK

WAKE_PCH# <38>

SSI2

PM_CLKRUN# <40>

SUSCLK <38>

ENBKL<38> VGA_LVDDEN<35>

VGA_PWM<35>

LVDS_DDC_CLK<35>

LVDS_DDC_DATA<35>

1 2

RH133 2.2K_0402_5%~DRH133 2.2K_0402_5%~D

1 2

RH135 2.2K_0402_5%~DRH135 2.2K_0402_5%~D

1 2

RH123 2.37K_0402_1%~DRH123 2.37K_0402_1%~D

LVDS_ACLK-<35> LVDS_ACLK+<35>

LVDS_A0-<35> LVDS_A1-<35> LVDS_A2-<35>

LVDS_A0+<35> LVDS_A1+<35> LVDS_A2+<35>

LVDS_BCLK-<35> LVDS_BCLK+<35>

LVDS_B0-<35> LVDS_B1-<35> LVDS_B2-<35>

LVDS_B0+<35> LVDS_B1+<35> LVDS_B2+<35>

RH115

1K_0402_0.5%~D

+3VS

1 2

RH136 8.2K_0402_5%~DRH136 8.2K_0402_5%~D

1 2

RH137 2.2K_0402_5%~DRH137 2.2K_0402_5%~D

1 2

RH138 2.2K_0402_5%~DRH138 2.2K_0402_5%~D

1 2

RH132 100K_0402_5%~DRH132 100K_0402_5%~D

1 2

RH134 100K_0402_5%~DRH134 100K_0402_5%~D

1 2

RH241 1M_0402_5%~DRH241 1M_0402_5%~D

ENBKL VGA_LVDDEN

LVDS_DDC_CLK LVDS_DDC_DATA

CTRL_CLK CTRL_DATA

LVDS_IBG

T4PAD~D@ T4PAD~D@

CRT_IREF

12

2

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82PPSM-QNHN-A0_BGA989~D

PM_CLKRUN# LVDS_DDC_CLK LVDS_DDC_DATA

VGA_LVDDEN ENBKL DP_PCH_HPD

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

mDP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

DMC

DP_PCH_HPD

1

PCH_SDVO_CTRLCLK <36>

PCH_SDVO_CTRLDATA <36>

HDMI_PCH_HPD# <36>

HDMI_A0N_VGA <36> HDMI_A0P_VGA <36> HDMI_A1N_VGA <36> HDMI_A1P_VGA <36> HDMI_A2N_VGA <36> HDMI_A2P_VGA <36> HDMI_A3N_VGA <36> HDMI_A3P_VGA <36>

PCH_DDPC_CTRLCLK <37> PCH_DDPC_CTRLDATA <37>

PCH_DPC_AUXN <37> PCH_DPC_AUXP <37>

DP_PCH_HPD <37>

PCH_DPC_N0 <37> PCH_DPC_P0 <37> PCH_DPC_N1 <37> PCH_DPC_P1 <37> PCH_DPC_N2 <37> PCH_DPC_P2 <37> PCH_DPC_N3 <37> PCH_DPC_P3 <37>

+3VS

1

CH30

0.1U_0402_16V7K~D

PCH_PWROK<38>

A A

VGATE<8,38,60>

PCH_PWROK

5

2

5

1

IN1

VCC

OUT

2

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

UH3

4

SYS_PWROK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP LA-7841P

LA-7841P

1

18 65Tuesday, February 07, 2012

0.3

5

1 2

RH242 1K_0402_5%~D@RH242 1K_0402_5%~D@

1 2

BBS_BIT1

@

RH244 1K_0402_5%~D

BBS_BIT0 <16>

Boot BIOS Strap (Both internal PU 20K) BIT 1

BIT 0

0 1

0

+3VS

8.2K_0804_8P4R_5%

SSI2

Boot BIOS Location

LPC Reserved PCI(non-mobile) SPI

RPH1

18

PCI_PIRQA#

27

PCI_PIRQB#

36

PCI_PIRQD#

45

PCI_PIRQC#

RPH2

18

DGPU_HOLD_RST#

27

PCH_GPIO52

36

DGPU_PWR_EN#

45

WL_OFF#

RPH3

18

FFS_INT1

27

ODD_DA#

36

PCH_GPIO5

45

+3VS

1 2

2

1

D

CH99

DIS@

D

1

S

3

RH247

RH247 10K_0402_5%~D

10K_0402_5%~D

DIS@

2

DGPU_PWR_EN#

G

QH6

DIS@

QH6

DIS@

ME2N7002D-G_SOT23-3

USB Conn 1 USB Conn 2 (Power Share)

GNT[1:3]# have internal w

eak PU, and disable

after PLTRST# deassert

SATA1GPGNT1#

0

D D

0 1 1 1

C C

DGPU_PWR_EN<33,61>

0.01U_0402_16V7K~D

1 2

RH243 1K_0402_5%~D

A16 Top-Block Swap Override (Internal PU 20K)

Low = swap enabled

GNT3#

High = Default

REQ[1:3]# & GNT[1:3]# are used as GPIO on Mobile

ST

B B

Switchable Graphics

DGPU_PWR_EN# GPIO54 Output High High Must have

DGPU_PWROK GPIO17 Input - - Must have

A A

DGPU_HOLD_RST# GPIO50 Output Low Low Must have

CH31

S

T

Reserve for RF, close to PCH

12

CLK_PCI1

10P_0402_50V8J~D

CH100

1 2

CLK_LPC_DEBUG

@

27P_0402_50V8J

CLK_PCI_LPBACK<17>

CLK_PCI_LPC<38>

CLK_LPC_DEBUG<42>

Signal GPIO Type DuringReset After Reset Usage Description

Driven by Switchable Graphics Driver to turn on/off the discrete graphics power. 0 = dGPU power switch turned on 1 = Power switch turned off

Driven by dGPU VR to indicate the power status to PCH. Used to enable clocks to dGPU. 0 = dGPU power is not stable. Keep clock disabled & reset asserted. 1 = dGPU power is stable. Clock can be enabled; reset can be deasserted If DGPU_PRSNT# is 1, in-order to get regular discrete GFX cards working, program DGPU_PWROK as GPO and assert a high value (1) on the pin.

Discrete Graphics Enable signal. Controlled by Switchable Graphics Driver and driven by PCH GPIO. Used to gate with Platform Reset to enable the Reset for dGPU. 0 = Keep dGPU in reset. 1 = Reset is released. This action taken 100 ms after DGPU_PWROK to ensure clock is stable.

5

4

WL_OFF#

@

USB3RN1<44> USB3RN2<45>

USB3RP1<44> USB3RP2<45>

USB3TN1<44> USB3TN2<45>

USB3TP1<44> USB3TP2<45>

EN_CAM<35>

WL_OFF#<42>

FFS_INT1<43> DP_CBL_DET<37>

T6PAD~D @T6PAD~D @

1 2 1 2

4

12

T8PAD~D @T8PAD~D @ T9PAD~D @T9PAD~D @

RH144 22_0402_5%RH144 22_0402_5% RH145 22_0402_5%RH145 22_0402_5% RH252 22_0402_5%RH252 22_0402_5%

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST# PCH_GPIO52 DGPU_PWR_EN#

BBS_BIT1 EN_CAM WL_OFF#

FFS_INT1 ODD_DA#

PCH_GPIO5

PCH_PLTRST#

CLK_PCI0 CLK_PCI1 CLK_LPC_DEBUG_R CLK_PCI3 CLK_PCI4

UH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3TP1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82PPSM-QNHN-A0_BGA989~D

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

RSVD

USB30

PCI

USB

PLT_RST#<8,38,40,41,42,48>

100K_0402_5%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

1 2

RH149 0_0402_5%~D

12

RH155

SN74AHC1G08DCKR_SC70-5

3

NV_ALE

AV10 AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

USBRBIAS

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

USB_OC3#

L16

USB_OC4#

A16

USB_OC5#

D14

USB_OC6#

C14

USB_OC7#

@

+3VS

5

1

P

IN1

4

O

2

IN2

G

3

UH5

@

2011/07/15 2012/07/15

1 2

RH139 1K_0402_5%~D@RH139 1K_0402_5%~D@

Intel Anti-Theft Techonlogy

NV_ALE

USB20_N0 <44> USB20_P0 <44> USB20_N1 <45> USB20_P1 <45>

USB20_N4 <42> USB20_P4 <42> USB20_N5 <48> USB20_P5 <48>

USB20_N12 <35> USB20_P12 <35>

Within 500 mils

1 2

RH143 22.6_0402_1%RH143 22.6_0402_1%

USB_OC0# <44> USB_OC1# <45>

PCH_PLTRST#

RH157

RH157 10K_0402_5%~D

10K_0402_5%~D

1 2

Compal Secret Data

Deciphered Date

Low = disable High = enable

USB Conn 1 USB Conn 2 (Power Share)

Mini Card(WLAN) Mini Card(WWAN)

Camera

PLTRST_VGA#<24>

2

+1.8VS

RH154

DIS@ RH154

DIS@

100K_0402_5%~D

PT

2

10K_1206_8P4R_5%~D

1 2

RH148 0_0402_5%~D@RH148 0_0402_5%~D@

+3V_GPU

5

P

IN1

4

O

IN2

G

3

UH4

DIS@

4 5 3 6 2 7 1 8

1 2

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB_OC4# USB_OC5# USB_OC6# USB_OC7#

12

SN74AHC1G08DCKR_SC70-5

RPH4

RPH5

PT

1

+3V_PCH

1 2

RH151 0_0402_5%~D@RH151 0_0402_5%~D@

1 2

RH152 0_0402_5%~DDIS@ RH152 0_0402_5%~DDIS@

12

RH156 100K_0402_5%~D

100K_0402_5%~D

PT

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM LA-7841P

LA-7841P

DIS@RH156

DIS@

DGPU_HOLD_RST#

PT

PCH_PLTRST#

1

DGPU_PWROK <20,61>

19 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

PCH_GPIO0 PCH_GPIO1 PCH_GPIO6 EC_SCI# PCIE_MCARD1_DET# MSATA_DET#

D D

BT_RADIO_DIS# PCH_GPIO16 WWAN_RADIO_DIS# KB_RST#

EC_SMI# PCH_GPIO12 HDD_DETECT#

PCH_GPIO36 PCH_GPIO37 DBC_EN CE_EN

C C

SSI2

PCH_GPIO15

RH158 1K_0402_5%~DRH158 1K_0402_5%~D

1 2

RH170 10K_0402_5%~DRH170 10K_0402_5%~D

1 2

RH164 10K_0402_5%~DRH164 10K_0402_5%~D

1 2

RH184 10K_0402_5%~DRH184 10K_0402_5%~D

1 2

RH160 10K_0402_5%~DRH160 10K_0402_5%~D

1 2

RH172 10K_0402_5%~DRH172 10K_0402_5%~D

1 2

RH176 10K_0402_5%~DRH176 10K_0402_5%~D

1 2

RH174 8.2K_0402_5%~DRH174 8.2K_0402_5%~D

1 2

RH181 10K_0402_5%~DRH181 10K_0402_5%~D

1 2

RH180 10K_0402_5%~DRH180 10K_0402_5%~D

1 2

RH175 10K_0402_5%~DRH175 10K_0402_5%~D

1 2

RH183 10K_0402_5%~DRH183 10K_0402_5%~D

1 2

RH248 10K_0402_5%~DRH248 10K_0402_5%~D

1 2

RH179 10K_0402_5%~DRH179 10K_0402_5%~D

1 2

RH171 10K_0402_5%~DRH171 10K_0402_5%~D

1 2

RH246 10K_0402_5%~DRH246 10K_0402_5%~D

1 2

RH177 10K_0402_5%~DRH177 10K_0402_5%~D

1 2

RH182 10K_0402_5%~DRH182 10K_0402_5%~D

1 2

+3V_PCH

TLS Confidentiality (Internal PD 20K)

Low = no confidentiality

GPIO15

High = confidentiality

1 2

RH165 1K_0402_5%~D@RH165 1K_0402_5%~D@

On-Die PLL Voltage Regulator (Internal PU 20K)

B B

GPIO28

PCH_GPIO28 needs to be connected to XDP_FN8 PCH_GPIO35 needs to be connected to XDP_FN9 PCH_GPIO15 needs to be connected to XDP_FN16

PCH_GPIO28

Low = Disable High = Enable

+3VS

+3V_PCH

SSI2

DBC_EN<35>

SSI2

CE_EN<35>

UH1F

PCH_GPIO0 PCH_GPIO1 PCH_GPIO6

T4915PAD~D@T4915PAD~D

@

EC_SCI# EC_SMI# PCH_GPIO12 PCH_GPIO15

PCH_GPIO16

MSATA_DET#

PCH_GPIO27 PCH_GPIO28 BT_RADIO_DIS# DBC_EN PCH_GPIO36 PCH_GPIO37 PCIE_MCARD1_DET# CE_EN

WWAN_RADIO_DIS# HDD_DETECT#

PCH_GPIO35

EC_SCI#<38> EC_SMI#<38>

DGPU_PWROK<19,61>

MSATA_DET#<48>

BT_RADIO_DIS#<42>

PCIE_MCARD1_DET#<42>

FFS_INT2<43>

WWAN_RADIO_DIS#<48>

HDD_DETECT#<43>

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82PPSM-QNHN-A0_BGA989~D

TACH[0:7] are not a

vailable on Mobile,

used as GPIO

GPIO

NCTF

TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

CFG_ID

PCH_PECI_R KB_RST#

H_THERMTRIP#_C INIT3_3V# NV_CLE

KB_BL_DET <39>

USB_MCARD1_DET# <42>

T4914 PAD~D

@

INIT3_3Vl has weak internal PU, can't pull low

Weak internal PU, Do not pull low

NV_CLE

1K_0402_5%~D

RH167

RH161

1 2

0_0402_5%~D@

1 2

RH162

390_0402_5%

+VCCPNAND

12

+3VS

12

put two Res close to minimize the stub

DMI and FDI Tx/Rx Termination Voltage (Internal PD 20K)

Low=Set to Vss

DF_TVS

High=Set to Vcc

RH159

RH159 10K_0402_5%~D

10K_0402_5%~D

1 2

RH166

2.2K_0402_5%~D

H_SNB_IVB# <8>

GATEA20 <38> H_PECI <8,38> KB_RST# <38> H_CPUPWRGD <8>

H_THERMTRIP# <8>

close to PCH within 0.25" ~ 2.5"

Configuration ID : DIS = High UMA = Low

10K_0402_5%~D

CFG_ID

10K_0402_5%~D

RH250

DIS@

RH249

UMA@

+3VS

1 2

Please refer to Huron River Debug Board DG 0.5

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC LA-7841P

LA-7841P

1

20 65Tuesday, February 07, 2012

0.3