Compal LA-7841P QLM00, XPS 14 Schematic

A

B

C

D

E

MODEL NAME : PCB NO : BOM P/N :

1 1

LA-7841P ( DA********** ) TBD

QLM00

Dell/Compal Confidential

Schematic Document

2 2

Ivy Bridge ULV(BGA1023) + Panther Point

DISCRETE VGA N13P-GV(optimus)

Phantom(Chief River)

2012-01-19

Rev: 1.0 (X04)

3 3

@ : Nopop Component CONN@ : Connector Component DIS@ : pop when DIS configuration UMA@ : pop when UMA configuration

MB Type

TPM

TCM

TPM DIS/ TCM DIS 2@

4 4

A

B

BOM P/N

4319EJ31L01

4319EJ31L02

2@

4@

3@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

Cover Page

Cover Page LA-7841P

LA-7841P

E

1 65Tuesday, February 07, 2012

of

0.3

VGA

DC

/DC

System

C/DC

D

A

128M*16 x 4 =1GB

VRAM * 4 GDDR5

GPU

N13P

P.33

P.34

VCCP

+

+1.5V / +

0.75VS

P.57

P.58

ZZZ

PCB-MB

1 1

GB2-64

DCIN / BATT

C

ONN

CHARGER

3/5V ALW

2 2

3 3

+1.8VS

+VCCSA

P.53

CPU / iGPU

ORE

C

.54

P

P.55

P.56

Card Reader

RTS5209

3 in 1

Socket

dGPU CORE

Port 4

P.48

.48

P

P.59

P.60

P.61

Mini Card-1

WLAN / BT4.0

LVDS Conn.

HDMI Conn.

Mini DP Conn.

Port 3

Half

USB2.0

ort 4

P

Daughter board

P.42

64 bit

-GV

P.35

P.36

P.37

.29~30

P

P.24 ~ 28

B

PEG 2.0 x16

LVDS (Dual Channel)

HDMI 1.4 (1.65Gb/s)

isplayPort 1.1

D

P

CI-E x1

Port 1

LAN(GbE) R

TL8111F

RJ45

.41

P

SPI ROM

x 1

8M

P.16

Discrete TPM

T97SC3204

A

P.41

P.40

Intel

I

vy Bridge

Processor

ULV 17W DC

BGA 1023 Balls

100MHz 100MHz

2.7GT/s

Intel

Panther Point

PCH HM77

BGA 989 Balls

SPI

ENE KBC

B9012

K

KB matrix

LPC Bus

33MHz

DMI x4FDI x8

20Gb/s

P.16 ~ 23

P.38

.7 ~ 13

P

C

PS/2

Single Channel

1.5V DDR3 1333 MHz

SATA3.0

USB2.0

HD Audio

Port 0

P

ort 1

Port 1USB 3.0

Port 0

ort 2

P

Port 1

Port 5

Port 12

D

DDRIII-DIMM x 1

B

ANK 0, 1, 2, 3, 4 ,5 ,6 ,7

8GB Max

SATA3 Re-Driver

P

S8520

P.43

SATA3 Re-Driver

PS8520

(DIS Only)

P

.43

USB 3.0 Conn. X1

P.44

PI5USB1457

P.45

Mini Card-2

WWAN

(

Full )

Digital Camera

udio Codec

A

ALC3260

P.48

P.35

P.48

Int. Speaker x2

P.48

P.14

SATA HDD Conn.

Mini Card-2

m

SATA

( Full )

USB 3.0 Conn. X1

( Power Share )

SIM

Daughter board

P.48

UMA SKU

Digi Mic (Array)

Headphone / Mic

Jack x 1

( Combo )

Daughter board

P.43

P.48

P.45

P.35

P.48

E

CPU ITP

onn.

P.8

P.39

C

Fan Control LID SW

RTC Circuit

Power SW (Daughter Board)

D

aughter board

DI

S SKU

FFS

P.43

P.40

P.16

P.39

Int.KBD Touch Pad

4 4

A

B

P.39 P.39

C

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THI S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

D

Compal Electronics,Inc.

Title

Size Document Number Rev

Date: Sheet

E

2 65Tuesday, February 07, 2012

of

0.3C

A

Compal Confidential

Project Code : QLM00 File Name : LA-7841P

B

C

D

E

1 1

LS-7841P POWER BUTTON BOARD

LA-7841P M/B

Camera

LS-7842P LED INDICATE BOARD LS-7843P BATTERY INDICATED BOARD LS-7844P I/O BOARD

40 pin

Wire

LCD Panel

IO/B

FFC

INDICATOR/B

2 2

Led-Wireless Led-CapsLock

Wire

6 pin

10 pin

Wire

4 pin

HDD

FFC

TP LED/B

Touch Pad

3 3

FFC

4 pin

Led x 6

Lid

POWER BUTTON/B

on/off SW

Led x 1

4 pin4 pin

WireWire

FRONT LIGHT L/B FRONT LIGHT R/B

Led x 2 Led x 2

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

E

0.3

3 65Tuesday, February 07, 2012

0.3

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

0 1 2 3 4 5 6 7 NC

SMBUS Control Table

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SML0CLK PCH PCH_SML0DATA

PCH_SML1CLK PCH_SML1DATA

MEM_SMBCLK MEM_SMBDATA

100K +/- 5%Ra

Rb V min

0 0 V

8.2K +/- 5% 18K +/- 5% 3

3K +/- 5%

56K +/- 5%

100K +/- 5% 200K +/- 5%

SOURCE

KB930

PCH

AD_BID

0.168 V

0.375 V 0.503 V

0.634 V

0.958 V

1.372 V

1.851 V 2.200 V

2.433 V

MINI2

MINI1 BATT SODIMM

V V

V

V typ

AD_BID

0 V 0.155 V

0.250 V

0.819 V

1.185 V

1.650 V

3.300 V

Thermal Sensor 1

V V

V

AD_BID

0.362 V

0.621 V

0.945 V

1.359 V

1.838 V

2.420 V

3.300 V

Thermal Sensor 2

max

FFS VGA

EC AD3

0x00-0x0C 0x0D-0x1C 0x1D-0x30 0x31-0x49 0x4A-0x69 0x6A-0x8E 0x8F-0xBB 0xBC-0xFF

VGA Thermal Sensor

V

V V

A

BOARD ID Table

Board ID

0 1 2 3 4 5 6 7

DMCVXDP

Charger

V

PCB Revision

0.1

0.2

0.3

0.4

1.0

Link

PCH

USB PORT#

0 1 2 3 4 5 6 7 8 9 10 11

DESTINATION None JUSB1 (2.0 Ext Left Side) Bluetooth CAMERA JMINI1 (WLAN) JMINI2 (WWAN/DMC) ELC 8051 None None None None None

12

CLKOUT

1 1

PCI0 PCI1 PCI2 PCI3 PCI4

CLK

DESTINATION

PCH_LOOPBACK

EC LPC None None None

CLKOUT_PCIE0 CLKOUT_PCIE1 CLKOUT_PCIE2 CLKOUT_PCIE3 CLKOUT_PCIE4 CLKOUT_PCIE5 CLKOUT_PCIE6 CLKOUT_PCIE7 None CLKOUT_PEG_B

DESTINATIONDIFFERENTIAL

10/100/1G LAN MINI CARD-2 WWAN MINI CARD-1 WLAN CARD READER None USB 3.0

None

FLEX CLOCKS DESTINATION CLKOUTFLEX0None CLKOUTFLEX1 CLKOUTFLEX2 CLKOUTFLEX3

None None None None

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

SATA SATA0 SATA1 SATA2 SATA3 SATA4 SATA5

DESTINATION

HDD None ODD None None None

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Secret Data

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

13

PCI EXPRESS

Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Lane 8 None

None None

DESTINATION 10/100/1G LAN MINI CARD-2 WWAN/DMC MINI CARD-1 WLAN CARD READER None USB 3.0 None

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List LA-7841P

LA-7841P

4 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

+3VS

SMBUS Address [0x9a]

D D

C9

H14

SMBCLK SMBDATA

PCH

C8

SML0CLK

SML0DATA

12

G

2.2K

+3V_PCH

2.2K

+3V_PCH

+3VS

DMN66D0 DMN66D0

+3VS_WLAN

2.2K

+3VS_WLAN

2.2K

DMN66D0 DMN66D0

E14M16

C C

SML1CLK

SML1DATA

2.2K

+3V_PCH

IO CONN

14 15

202 200

4 5

30 32

32

WLAN

30

WWAN/mSATA

DIMMA

WLAN

4

G Sensor

6

SMBUS Address [TBD]

SMBUS Address [A0]

SMBUS Address [TBD]

TP

SMBUS Address [TBD]

DMN66D0 DMN66D0

EC_SMB_CK2

EC_SMB_DA2

80 79

KBC

B B

8.2K

+3VS

DMN66D0 DMN66D0

+3VS

2.2K

+3V_GPU

10

Camera

9

2.2K

100 ohm

3

2.2K

100 ohm

D9 D8

4 5

9

8

2011/07/15 2012/07/15

GPU

BATTERY CONN

CHARGER

Compal Secret Data

SMBUS Address [0x9E]

SMBUS Address [TBD]

Deciphered Date

2

Compal Electronics, Inc.

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

Date: Sheet of

5 65Tuesday, February 07, 2012

1

0.3

+3V_GPU

4.7K

+3VALW

77

EC_SMB_CK1

78

EC_SMB_DA1

A A

5

4.7K

4

DMN66D0 DMN66D0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EN_INVPWR

5

SI3457BDV

Q

V29

+INV_PWR_SRC

RT8207MZQW

U300

P

4

3

2

1

+0.75VS

TPS51461RGER

+VCCP

SI4634DY

UZ1

1.05VSDGPU

AO4728L

QU6

SI3456DDV

UZ4

TPS2062ADR

UI2

SI3456DDV

QN1

SI4800BDY

Z6

Q

AO3419L

QH5

U600

P

SI3456DDV

QZ12

SY8033BDBC

PU400

SI4800BDY

QZ8

AO3419L

QL3

+1.5V_CPU_VDDQ

+1.5VS

+5V_CHGUSB

+5VS_HDD

+5VS

+5V_PCH

+VCCSA

+3V_PCH

+1.8VS

+3VS

+LAN_IO

ODD_EN#

EN_DFAN1

EC_ENVDD / VGA_LVDDEN

EN_CAM

WLAN_EN

FDC655BN

N4

Q

APE8873M

E4

U

AO3419L

QV27

SI2301CDS

QV31

SI3456DDV

QM1

+5VS_ODD

+FAN_POWER

+LCDVDD

+3VS_CAM

+3VS_WLAN

+VCC_CORE/+VCC_GFXCORE_AXG

ISL95836HRTZ-T

+1.5V_CPU_VDDQ

ower Bottom &

P BATBTN & USBCHG_DET

Tc

PWRBTN#

PCH

DPWROK

RSMRST# PCH_RSMRST#

ACPRESENT

LP_S5#

S

SLP_S3#

APWROK

PWROK

SYS_PWROK

PGOOD

AO4728L

4

5

6

7

8

10

11

17

18

16

13

AC mode Ta -> Tb -> Tc DC mode Tc -> Ta -> Tb

ON/OFF

ENE KB9012

PBTN_OUT#

PCH_DPWROK

AC_PRESENT

PM_SLP_S5#

PM_SLP_S3#

PCH_APWROK

PCH_PWROK

VR_ON

VGATE

CPU1.5V_S3_GATE

EC_ON

P

CH_PWR_EN

SYSON

SUSP#

SA_PGOOD

15

Ta

12

+3V/+5V_ALW

R

T8205LZQW

PGOOD

TP0610K

Tb

4

9

AO3419L/SI3456DDV

RT8207MZQW

PGOOD

SY8033BDBC

PGOOD

SI4800BDY

SI3456DDV

TPS51212DSCR

PGOOD

14

+VSBP

+3V/+5V_PCH

+

1.5V/+0.75VS

+1.8VS

+3VS

+5VS

+1.5VS

+VCCP

TPS51461RGER

+VCCSA

GOOD

P

CPU1.5V_S3_GATE

SYSON

RT8207MZQW

PU300

ADAPTER

D D

SUSP#

TPS51212DSCR

PU500

VR_ON

BATTERY

B+

ISL95836HRTZ

U700

P

+1.5V

SUSP#

+VCCP

+VCC_CORE / +

VCC_GFXCORE_AXG

PWRSHARE_EN_EC#

CHARGER

PM_SLP_S3#

SUSP#

PCH_PWR_EN

EC_ON / VCOUT0_PH / MAINPWON

C C

RT8205LZQW

PU200

+5VALW

+V1.05S_VCCP_PWRGOOD

3VALW

+

PCH_PWR_EN

SUSP#

EN_WOL

B B

GPU

DGPU_PWR_EN

+3VS

AO3419L

QZ1

+3V_GPU

RC delay

+1.5V

SI4634DY

UZ2

+1.5VSDGPU

RC delay

+

B+

ISL62883CHRTZ

A A

PU800

+GPU_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Power Diagram

1

0.3

6 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

PEG_RCOMPO (G4)

PEG_ICOMPI (G3)

Trace length M

ax is 500 mils

D D

DMI_CRX_PTX_N0<18> DMI_CRX_PTX_N1<18> DMI_CRX_PTX_N2<18> DMI_CRX_PTX_N3<18>

DMI_CRX_PTX_P0<18> DMI_CRX_PTX_P1<18> DMI_CRX_PTX_P2<18> DMI_CRX_PTX_P3<18>

DMI_CTX_PRX_N0<18> DMI_CTX_PRX_N1<18> DMI_CTX_PRX_N2<18> DMI_CTX_PRX_N3<18>

DMI_CTX_PRX_P0<18> DMI_CTX_PRX_P1<18> DMI_CTX_PRX_P2<18> DMI_CTX_PRX_P3<18>

FDI_CTX_PRX_N0<18> FDI_CTX_PRX_N1<18> FDI_CTX_PRX_N2<18> FDI_CTX_PRX_N3<18> FDI_CTX_PRX_N4<18> FDI_CTX_PRX_N5<18>

+VCCP

FDI_CTX_PRX_N6<18> FDI_CTX_PRX_N7<18>

FDI_CTX_PRX_P0<18> FDI_CTX_PRX_P1<18> FDI_CTX_PRX_P2<18> FDI_CTX_PRX_P3<18> FDI_CTX_PRX_P4<18> FDI_CTX_PRX_P5<18> FDI_CTX_PRX_P6<18> FDI_CTX_PRX_P7<18>

FDI_FSYNC0<18> FDI_FSYNC1<18>

FDI_INT<18> FDI_LSYNC0<18>

FDI_LSYNC1<18>

RU2

1 2

24.9_0402_1%

EDP_COMP

C C

eDP_COMPIO and ICOMPO signals

B B

should be shorted near balls and routed with typical impedance <25 mohms

W11

W10

AA11 AC12

AA10

AG8

AG11

AG4

AE11

AE10

AC9

AA7

AA3 AC8

U11

AF3 AD2

AF4

AC3 AC4

AE7 AC1

AA4 AE6

M2

P6 P1

P10

N3 P7 P3

P11

K1

M8

N4 R2

K3

M7

P4 T3

U7

W1

AA6

W6

V4 Y2

U6 W3 W7

T4

PEG_ICOMPO (G1)

U2A

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]

DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]

DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]

FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3]

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

eDP_COMPIO eDP_ICOMPO eDP_HPD#

eDP_AUX# eDP_AUX

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

IVY-BRIDGE_BGA1023~D

@

Trace length Max is 500 mils

R_COMP place close to CPU

width 4 mils

width 12 mils

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1]

DMI Intel(R) FDI

PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4]

eDP

PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

R_COMP

G3 G1 G4

H22

PEG_GTX_C_HRX_N15

J21

PEG_GTX_C_HRX_N14

B22

PEG_GTX_C_HRX_N13

D21

PEG_GTX_C_HRX_N12

A19

PEG_GTX_C_HRX_N11

D17

PEG_GTX_C_HRX_N10

B14

PEG_GTX_C_HRX_N9

D13

PEG_GTX_C_HRX_N8

A11

PEG_GTX_C_HRX_N7

B10

PEG_GTX_C_HRX_N6

G8

PEG_GTX_C_HRX_N5

A8

PEG_GTX_C_HRX_N4

B6

PEG_GTX_C_HRX_N3

H8

PEG_GTX_C_HRX_N2

E5

PEG_GTX_C_HRX_N1

K7

PEG_GTX_C_HRX_N0

K22

PEG_GTX_C_HRX_P15

K19

PEG_GTX_C_HRX_P14

C21

PEG_GTX_C_HRX_P13

D19

PEG_GTX_C_HRX_P12

C19

PEG_GTX_C_HRX_P11

D16

PEG_GTX_C_HRX_P10

C13

PEG_GTX_C_HRX_P9

D12

PEG_GTX_C_HRX_P8

C11

PEG_GTX_C_HRX_P7

C9

PEG_GTX_C_HRX_P6

F8

PEG_GTX_C_HRX_P5

C8

PEG_GTX_C_HRX_P4

C5

PEG_GTX_C_HRX_P3

H6

PEG_GTX_C_HRX_P2

F6

PEG_GTX_C_HRX_P1

K6

PEG_GTX_C_HRX_P0

G22

PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15

C23

PEG_HTX_GRX_N14 PEG_HTX_C_GRX_N14

D23

PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13

F21

PEG_HTX_GRX_N12 PEG_HTX_C_GRX_N12

H19

PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11

C17

PEG_HTX_GRX_N10 PEG_HTX_C_GRX_N10

K15

PEG_HTX_GRX_N9 PEG_HTX_C_GRX_N9

F17

PEG_HTX_GRX_N8 PEG_HTX_C_GRX_N8

F14

PEG_HTX_GRX_N7 PEG_HTX_C_GRX_N7

A15

PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6

J14

PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5

H13

PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4

M10

PEG_HTX_GRX_N3 PEG_HTX_C_GRX_N3

F10

PEG_HTX_GRX_N2 PEG_HTX_C_GRX_N2

D9

PEG_HTX_GRX_N1 PEG_HTX_C_GRX_N1

J4

PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0

F22

PEG_HTX_GRX_P15 PEG_HTX_C_GRX_P15

A23

PEG_HTX_GRX_P14 PEG_HTX_C_GRX_P14

D24

PEG_HTX_GRX_P13 PEG_HTX_C_GRX_P13

E21

PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12

G19

PEG_HTX_GRX_P11 PEG_HTX_C_GRX_P11

B18

PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10

K17

PEG_HTX_GRX_P9 PEG_HTX_C_GRX_P9

G17

PEG_HTX_GRX_P8 PEG_HTX_C_GRX_P8

E14

PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7

C15

PEG_HTX_GRX_P6 PEG_HTX_C_GRX_P6

K13

PEG_HTX_GRX_P5 PEG_HTX_C_GRX_P5

G13

PEG_HTX_GRX_P4 PEG_HTX_C_GRX_P4

K10

PEG_HTX_GRX_P3 PEG_HTX_C_GRX_P3

G10

PEG_HTX_GRX_P2 PEG_HTX_C_GRX_P2

D8

PEG_HTX_GRX_P1 PEG_HTX_C_GRX_P1

K4

PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0

Typ- suggest 220nF. The change in AC capacitor

alue from 100nF to 220nF is to enable compatibility

v with future platforms having PCIE Gen3 (8GT/s)

VCC_IO

PEG_COMP

+VCCP

RU1

12

24.9_0402_1%

PT

1 2

CU1 0.22U_0402_16V7K~D@CU1 0.22U_0402_16V7K~D@

1 2

CU2 0.22U_0402_16V7K~D@CU2 0.22U_0402_16V7K~D@

1 2

CU3 0.22U_0402_16V7K~D@CU3 0.22U_0402_16V7K~D@

1 2

CU4 0.22U_0402_16V7K~D@CU4 0.22U_0402_16V7K~D@

1 2

CU5 0.22U_0402_16V7K~D@CU5 0.22U_0402_16V7K~D@

1 2

CU6 0.22U_0402_16V7K~D@CU6 0.22U_0402_16V7K~D@

1 2

CU7 0.22U_0402_16V7K~D@CU7 0.22U_0402_16V7K~D@

1 2

CU8 0.22U_0402_16V7K~D@CU8 0.22U_0402_16V7K~D@

1 2

CU9 0.22U_0402_16V7K~DDIS@CU9 0.22U_0402_16V7K~DDIS@

1 2

CU10 0.22U_0402_16V7K~DDIS@CU10 0.22U_0402_16V7K~DDIS@

1 2

CU11 0.22U_0402_16V7K~DDIS@CU11 0.22U_0402_16V7K~DDIS@

1 2

CU12 0.22U_0402_16V7K~DDIS@CU12 0.22U_0402_16V7K~DDIS@

1 2

CU13 0.22U_0402_16V7K~DDIS@CU13 0.22U_0402_16V7K~DDIS@

1 2

CU14 0.22U_0402_16V7K~DDIS@CU14 0.22U_0402_16V7K~DDIS@

1 2

CU15 0.22U_0402_16V7K~DDIS@CU15 0.22U_0402_16V7K~DDIS@

1 2

CU16 0.22U_0402_16V7K~DDIS@CU16 0.22U_0402_16V7K~DDIS@

PT

1 2

CU17 0.22U_0402_16V7K~D@CU17 0.22U_0402_16V7K~D@

1 2

CU18 0.22U_0402_16V7K~D@CU18 0.22U_0402_16V7K~D@

1 2

CU19 0.22U_0402_16V7K~D@CU19 0.22U_0402_16V7K~D@

1 2

CU20 0.22U_0402_16V7K~D@CU20 0.22U_0402_16V7K~D@

1 2

CU21 0.22U_0402_16V7K~D@CU21 0.22U_0402_16V7K~D@

1 2

CU22 0.22U_0402_16V7K~D@CU22 0.22U_0402_16V7K~D@

1 2

CU23 0.22U_0402_16V7K~D@CU23 0.22U_0402_16V7K~D@

1 2

CU24 0.22U_0402_16V7K~D@CU24 0.22U_0402_16V7K~D@

1 2

CU25 0.22U_0402_16V7K~DDIS@CU25 0.22U_0402_16V7K~DDIS@

1 2

CU26 0.22U_0402_16V7K~DDIS@CU26 0.22U_0402_16V7K~DDIS@

1 2

CU27 0.22U_0402_16V7K~DDIS@CU27 0.22U_0402_16V7K~DDIS@

1 2

CU28 0.22U_0402_16V7K~DDIS@CU28 0.22U_0402_16V7K~DDIS@

1 2

CU29 0.22U_0402_16V7K~DDIS@CU29 0.22U_0402_16V7K~DDIS@

1 2

CU30 0.22U_0402_16V7K~DDIS@CU30 0.22U_0402_16V7K~DDIS@

1 2

CU31 0.22U_0402_16V7K~DDIS@CU31 0.22U_0402_16V7K~DDIS@

1 2

CU32 0.22U_0402_16V7K~DDIS@CU32 0.22U_0402_16V7K~DDIS@

PEG_ICOMPI and RCOMPO signals should be shorted and routed with max length = 500 mils

- typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

PEG_GTX_C_HRX_N[0..15] PEG_GTX_C_HRX_P[0..15] PEG_HTX_C_GRX_N[0..15] PEG_HTX_C_GRX_P[0..15]

SSI2

PEG_GTX_C_HRX_N[0..15] <24> PEG_GTX_C_HRX_P[0..15] <24>

PEG_HTX_C_GRX_N[0..15] <24> PEG_HTX_C_GRX_P[0..15] <24>

PT

CPU Option

Sandy Bridge 1.6G

U2

SNB1.6G

CPU_SNB1.6G@

Ivy Bridge 1.5G

U2

IVB1.5G

CPU_IVB1.5G@

Ivy Bridge 1.7G

U2

IVB1.7G

CPU_IVB1.7G@

R_COMP place close to CPU

eDP_COMPIO (AF3)

eDP_ICOMPO (AD2)

A A

width 4 mils

width 12 mils

5

R_COMP

VCC_IO

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

7 65Tuesday, February 07, 2012

1

7 65Tuesday, February 07, 2012

0.3

5

H_SNB_IVB#<20>

D D

T15PAD~D@T15PAD~D

ST

H_PECI<20,38>

close to CPU within 0.3" ~ 1.5"

H_PROCHOT#<38,54>

C C

+VCCP

RU30

RU30 62_0402_5%

62_0402_5%

RU32

1 2

56_0402_5%

H_PROCHOT#_R

1 2

0_0402_5%~D

H_CPUPWRGD<20>

close to main route without stub

RU33 10K_0402_5%~DRU33 10K_0402_5%~D

12

Buffered reset to CPU

B B

PLT_RST#<19,38,40,41,42,48>

Follow DG 0.71

AND Gate and its surrounding parts keep 2" ~ 8" with Res 200 & 130 ohm

CPU1.5V_S3_GATE<12,38,58>

A A

PM_DRAM_PWRGD<18>

+3V_PCH

ST

0_0402_5%~D

1 2

RU117

1 2

200_0402_5%~D

RUN_ON_CPU1.5VS3#<12,34>

5

H_CPUPWRGD

PT

ST

CU36

.1U_0402_16V7K

RU62

SHORT

+3VS

1

CU35

0.1U_0402_16V4Z~D

2

5

U3

1

P

NC

4

Y

2

A

G

3

SN74LVC1G07DCKR_SC70-5

+3V_PCH

1

2

U4

U4 74AHC1G09GW_TSSOP5~D

74AHC1G09GW_TSSOP5~D

5

1

P

B

4

O

2

A

G

3

RU118 0_0402_5%~D

1 2

@

2

G

BUFO_CPU_RST# BUF_CPU_RST#

PM_SYS_PWRGD_BUF PM_SYS_PWRGD_BUF_R

12

RU63

RU63 39_0402_5%

39_0402_5%

@

13

D

SSI2

QU2

QU2 2N7002_SOT23-3

2N7002_SOT23-3

S

@

RU31

SHORT

@

+VCCP

12

@RU18

@

1 2

10K_0402_5%~D

H_CATERR#

H_PECI_ISO

H_PROCHOT#_R

H_THERMTRIP#<20>

H_PM_SYNC<18>

H_CPUPWRGD

PM_SYS_PWRGD_BUF_R

BUF_CPU_RST#

RU42

RU42 75_0402_5%

75_0402_5%

RU47

43_0402_1%

1 2

+1.5V_CPU_VDDQ

12

RU18

close to CPU within 1" ~ 2"

12

@

RU55

RU55 0_0402_5%~D

0_0402_5%~D

RU60

RU60 200_0402_5%~D

200_0402_5%~D

RU43

1 2

130_0402_5%

4

F49

C57

C49

A48

C45

D45

C48

B46

BE45

D44

close to CPU within 0.5" ~ 2"

4

U2B

PROC_SELECT#

PROC_DETECT#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

IVY-BRIDGE_BGA1023~D

@

3

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

Place near JXDP1

+VCCP

ST ST

.1U_0402_16V7K

close to SO-DIMM

S

T

1 2

SHORT

DRAMRST_CNTRL_PCH<14,17>

SHORT

RU75 0_0402_5%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

J3 H2

AG3 AG1

N59 N58

AT30

BF44 BE43 BG43

N53 N55

L56

TCK

L55

TMS

J58 M60

TDI

L59

TDO

K58

G58 E55 E59 G55 G59 H60 J59 J61

1

CU33

@

2

4.99K_0402_1%~D

DRAMRST_CNTRL

2

CLK_CPU_DMI <17> CLK_CPU_DMI# <17>

CLK_CPU_DPLL CLK_CPU_DPLL#

CLK_RES_ITP <17> CLK_RES_ITP# <17>

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI_R XDP_TDO_R

XDP_DBRESET#_R

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

.1U_0402_16V7K

The resistor for HOOK2 should be placed such that the stub is very small on CFG0 net.

@ RU71

@

0_0402_5%~D

1 2

S

RU74

1 2

RU38 0_0402_5%~DRU38 0_0402_5%~D

1 2

RU39 0_0402_5%~DRU39 0_0402_5%~D

1 2

RU41 0_0402_5%~DRU41 0_0402_5%~D

T4930PAD~D

@

T4931PAD~D

@

T4932PAD~D

@

T4933PAD~D

@

T4934PAD~D

@

T4935PAD~D

@

T4936PAD~D

@

T4937PAD~D

@

1

CU34

@

2

RU71

D

13

DDR3_DRAMRST#_RH_DRAMRST#

SSI2

G

QU3

2

BSS138-G_SOT23-3

+1.5V

RU72

1K_0402_5%~D

XDP_TDI XDP_TDO

XDP_DBRESET#

H_CPUPWRGD Res 1K, close to JXDP within 0.5" ~ 3"

PBTN_OUT#<18,38>

CFG0<10>

VGATE<18,38,60>

CLK_CPU_ITP<17>

CLK_CPU_ITP#<17>

PCH_JTAG_TDO<16>

PCH_JTAG_TDI<16>

PCH_JTAG_TMS<16>

PCH_JTAG_TCK<16>

12

RU73

RU73 1K_0402_5%~D

1K_0402_5%~D

1 2

ST

1

CU39

CU39 .047U_0402_16V7K

.047U_0402_16V7K

2

Compal Secret Data

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

2

XDP_DBRESET# <18>

H_CPUPWRGD

RU7 1K_0402_5%~D@RU7 1K_0402_5%~D@ RU8 0_0402_5%~D@RU8 0_0402_5%~D@ RU9 1K_0402_5%~D@RU9 1K_0402_5%~D@ RU10 0_0402_5%~D@RU10 0_0402_5%~D@

RU12 1K_0402_5%~D@RU12 1K_0402_5%~D@

RU13 0_0402_5%~D@RU13 0_0402_5%~D@ RU14 0_0402_5%~D@RU14 0_0402_5%~D@

RU19 0_0402_5%~D@RU19 0_0402_5%~D@ RU20 0_0402_5%~D@RU20 0_0402_5%~D@

DDR3_DRAMRST# <14>

1

CLK_CPU_DPLL# CLK_CPU_DPLL

close to CPU within 0.5" RCOMP0 & 1 : trace width = 20mil RCOMP2 : trace width = 15mil spacing = 20mil

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

1 2

RU25 1K_0402_5%~DRU25 1K_0402_5%~D

1 2

RU24 1K_0402_5%~DRU24 1K_0402_5%~D

RU58 140_0402_1%RU58 140_0402_1% RU59 25.5_0402_1%RU59 25.5_0402_1% RU61 200_0402_1%RU61 200_0402_1%

12 12 12

PU/PD for JTAG signals

XDP_TMS XDP_TDI_R XDP_TDO

XDP_TCK XDP_TRST#

XDP_DBRESET#

XDP_PREQ# XDP_PRDY#

1 2 1 2 1 2 1 2

12

12 12

12

1 2

Title

Size Document Number Rev

Custom

Date: Sheet of

H_CPUPWRGD_XDP CFD_PWRBTN#_XDP CFG0_R SYS_PWROK_XDP

XDP_RST#_RPLT_RST# XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_TCK1

XDP_TCK

Compal Electronics, Inc.

PROCESSOR(2/7) PM,XDP,CLK

1 2

RU17 51_0402_5%RU17 51_0402_5%

1 2

RU23 51_0402_5%RU23 51_0402_5%

1 2

RU27 51_0402_5%RU27 51_0402_5%

1 2

RU28 51_0402_5%RU28 51_0402_5%

1 2

RU29 51_0402_5%RU29 51_0402_5%

1 2

RU35 1K_0402_5%~DRU35 1K_0402_5%~D

+VCCP

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

ACES_87152-26051

1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

8 65Tuesday, February 07, 2012

CONN@

JXDP1

G1 G2

27 28

+VCCP

+3VS

0.3

5

U2C

DDR_A_D[0..63]<14>

D D

C C

DDR_A_BS0<14> DDR_A_BS1<14>

B B

DDR_A_BS2<14>

DDR_A_CAS#<14> DDR_A_RAS#<14> DDR_A_WE#<14>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

AP11

AJ10

AR11

AT13

AU13

BA13 BB11

AY13 AV14 AR14

AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45

AT48

AY48 BA49 AV49 BB51

AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54

AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37

BF36 BA28

BE39 BD39

AT41

AG6

AP6 AU6 AV9 AR6 AP8

BC7 BB7

BA7 BA9 BB9

AJ6 AL6 AJ8

AL8 AL7

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

4

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 <14> M_CLK_DDR#0 <14> DDR_CKE0_DIMMA <14>

M_CLK_DDR1 <14> M_CLK_DDR#1 <14> DDR_CKE1_DIMMA <14>

DDR_CS0_DIMMA# <14> DDR_CS1_DIMMA# <14>

M_ODT0 <14> M_ODT1 <14>

DDR_A_DQS#[0..7] <14>

DDR_A_DQS[0..7] <14>

DDR_A_MA[0..15] <14>

3

U2D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]

BD13

SB_DQ[18]

BF12

SB_DQ[19]

BF8

SB_DQ[20]

BD10

SB_DQ[21]

BD14

SB_DQ[22]

BE13

SB_DQ[23]

BF16

SB_DQ[24]

BE17

SB_DQ[25]

BE18

SB_DQ[26]

BE21

SB_DQ[27]

BE14

SB_DQ[28]

BG14

SB_DQ[29]

BG18

SB_DQ[30]

BF19

SB_DQ[31]

BD50

SB_DQ[32]

BF48

SB_DQ[33]

BD53

SB_DQ[34]

BF52

SB_DQ[35]

BD49

SB_DQ[36]

BE49

SB_DQ[37]

BD54

SB_DQ[38]

BE53

SB_DQ[39]

BF56

SB_DQ[40]

BE57

SB_DQ[41]

BC59

SB_DQ[42]

AY60

SB_DQ[43]

BE54

SB_DQ[44]

BG54

SB_DQ[45]

BA58

SB_DQ[46]

AW59

SB_DQ[47]

AW58

SB_DQ[48]

AU58

SB_DQ[49]

AN61

SB_DQ[50]

AN59

SB_DQ[51]

AU59

SB_DQ[52]

AU61

SB_DQ[53]

AN58

SB_DQ[54]

AR58

SB_DQ[55]

AK58

SB_DQ[56]

AL58

SB_DQ[57]

AG58

SB_DQ[58]

AG59

SB_DQ[59]

AM60

SB_DQ[60]

AL59

SB_DQ[61]

AF61

SB_DQ[62]

AH60

SB_DQ[63]

BG39

SB_BS[0]

BD42

SB_BS[1]

AT22

SB_BS[2]

AV43

SB_CAS#

BF40

SB_RAS#

BD45

SB_WE#

2

BA34

SB_CK[0]

AY34

SB_CK#[0]

AR22

SB_CKE[0]

BA36

SB_CK[1]

BB36

SB_CK#[1]

BF27

SB_CKE[1]

BE41

SB_CS#[0]

BE47

SB_CS#[1]

AT43

SB_ODT[0]

BG47

SB_ODT[1]

AL3

SB_DQS#[0]

AV3

SB_DQS#[1]

BG11

SB_DQS#[2]

BD17

SB_DQS#[3]

BG51

SB_DQS#[4]

BA59

SB_DQS#[5]

AT60

SB_DQS#[6]

AK59

SB_DQS#[7]

AM2

SB_DQS[0]

AV1

SB_DQS[1]

BE11

SB_DQS[2]

BD18

SB_DQS[3]

BE51

SB_DQS[4]

BA61

SB_DQS[5]

AR59

SB_DQS[6]

AK61

SB_DQS[7]

DDR SYSTEM MEMORY B

BF32

SB_MA[0]

BE33

SB_MA[1]

BD33

SB_MA[2]

AU30

SB_MA[3]

BD30

SB_MA[4]

AV30

SB_MA[5]

BG30

SB_MA[6]

BD29

SB_MA[7]

BE30

SB_MA[8]

BE28

SB_MA[9]

BD43

SB_MA[10]

AT28

SB_MA[11]

AV28

SB_MA[12]

BD46

SB_MA[13]

AT26

SB_MA[14]

AU22

SB_MA[15]

1

IVY-BRIDGE_BGA1023~D

@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

IVY-BRIDGE_BGA1023~D

@

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

1

0.3

9 65Tuesday, February 07, 2012

0.3

5

U2E

CFG0<8>

T18PAD~D@T18PAD~D T17PAD~D@T17PAD~D

D D

follow "458544_CR_PDDG_rev_0.8", section "2.2.1", Intel recommends providing accessibility to the pins F48 & G48 for debug purpose. The pins should be via through to the backside of the board to allow backside probing with no connection to other

C C

rails/components on the platform.

RU83

1K_0402_1%~D

T16PAD~D@T16PAD~D T21PAD~D@T21PAD~D T22PAD~D@T22PAD~D T4917PAD~D@T4917PAD~D T28PAD~D@T28PAD~D T29PAD~D@T29PAD~D T30PAD~D@T30PAD~D T31PAD~D@T31PAD~D T23PAD~D@T23PAD~D T20PAD~D@T20PAD~D

T24PAD~D@T24PAD~D

CFG0 CFG1

@

CFG2 CFG3

@

CFG4 CFG5 CFG6 CFG7 CFG8

@

CFG9

@

CFG10

@

CFG11

@

CFG12

@

CFG13

@

CFG14

@

CFG15

@

CFG16

@

CFG17

@

As PDDG rev0.8, VCC_VAL_SENSE & VAXG_VAL_SENSE are removed.

@

CPU_RSVD6 CPU_RSVD7

12

RU84

RU84 1K_0402_1%~D

1K_0402_1%~D

NAR00 pull down 12/28/09

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

4

RESERVED

RSVD28 RSVD29

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RSVD45

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

BE7 BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

3

CFG Straps for Processor

+V_DDR_REFA_M3 <14>

CFG2 CFG4 CFG5 CFG6 CFG7

PCI Express* Static x16 Lane Numbering Reversal

PCI Express* Static x4 Lane Numbering Reversal

eDP enable PEG DEFER TRAINING

PCI Express Bifurcation (x16 Lane)

follow "452823_COUGAR_CANYON(BGA1023)_Customer_Ready_Schematic". It's for Huron River platform, since can't find CPU Ivy bridge BGA1023 schematic for Chief River at this moment.

1 2

RU77 1K_0402_1%~DRU77 1K_0402_1%~D

1 2

RU78 1K_0402_1%~D@RU78 1K_0402_1%~D@

ST

1 2

RU85 1K_0402_1%~D@RU85 1K_0402_1%~D@

1 2

RU86 1K_0402_1%~D@RU86 1K_0402_1%~D@

1 2

RU87 1K_0402_1%~D@RU87 1K_0402_1%~D@

SSI2

CFG2

CFG3 CFG4 CFG7

1 x16 PCI Express (Default value)11

10

2 x8 PCI Express

CFG[6:5]

01

reserved 1 x8, 2 x4 PCI Express

00

2

1 (Default value) 0

Normal operation (match socket pin map)

Disable PEG Train immediately

following RESETB de-assertion

Lane numbers reversed

Enable PEG Wait for

BIOS for training

1

IVY-BRIDGE_BGA1023~D

@

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

10 65Tuesday, February 07, 2012

1

10 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] VCCIO[9]

VCCIO50 VCCIO51

VIDSCLK

VIDSOUT

4

+VCCP decoupling Cap. in Page 62.

+VCCP

AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

8.5A

+VCCP

1

CU40

CU40 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

@

+VCCP

1

CU94

CU94 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

H_CPU_SVIDALRT#

VCCSENSE_R VSSSENSE_R

VCCIO_SENSE_R VSS_SENSE_VCCIO

As 473716_Ivy_Bridge_EDS(1 of 2)_Mobile_rev1.5,

T25 PAD~D

Page 92, VCCIO_SEL, "For Chief River platforms this pin should not be used"

RU94 43_0402_1%RU94 43_0402_1%

RU92 130_0402_5%RU92 130_0402_5%

1 2

RU100 10_0402_1%~DRU100 10_0402_1%~D

12

RU103

RU103 10_0402_1%~D

10_0402_1%~D

Issued Date

+VCCP

12

RU93

RU93 75_0402_5%

75_0402_5%

+VCCP

VCCIO_SENSE <57> VSSIO_SENSE <57>

3

VR_SVID_ALRT# <60> VR_SVID_CLK <60> VR_SVID_DAT <60>

+VCC_CORE

RU97

RU97 100_0402_1%~D

100_0402_1%~D

1 2

12

RU102

RU102 100_0402_1%~D

100_0402_1%~D

2011/07/15 2012/07/15

close to CPU within 2"

VCCSENSE <60> VSSSENSE <60>

Compal Secret Data

Deciphered Date

2

close to CPU

ithin 0.3" ~ 1.5"

w

1 2

12

close to CPU within 0.3" ~ 1.5"

close to CPU within 2"

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

11 65Tuesday, February 07, 2012

1

11 65Tuesday, February 07, 2012

0.3

POWER

U2F

+VCC_CORE decoupling Cap. in Page 62.

+VCC_CORE

33A

ULV 17W , Max Current

D D

C C

B B

A A

in Turbo Mode or HFM

5

U2F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023~D

@

POWER

CORE SUPPLY

VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32]

PEG IO AND DDR IO

VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

RAILS

VIDALERT#

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

5

4

3

2

1

RU105 1K_0402_1%~D

1 2

RU107 1K_0402_1%~D

+VCC_GFXCORE_AXG decoupling Cap. in Page 62.

D D

+VCC_GFXCORE_AXG

33A

ULV GT2 , Max Current in Turbo Mode

C C

close to CPU w

ithin 2"

RU114

+VCC_GFXCORE_AXG

B B

A A

VCC_AXG_SENSE<60>

VSS_AXG_SENSE<60>

+VCCSA

Intel PDDG rev0.8 :

30uF x 1 - Bottom CPU edge

3 10uF x 5 - Bottom CPU edge 1uF x 5 - Under CPU

5

ST

Intel PDDG rev0.8 : 330uF x 1 - Bottom CPU edge 1uF x 2 - Top CPU edge

330U_D2_2V_Y

CU142

1

+

2

1 2

RU122 0_0402_5%~D

SHORT

RU122 0_0402_5%~D

SHORT

1 2

RU123 0_0402_5%~D

SHORT

RU123 0_0402_5%~D

SHORT

ST

+1.8VS

10U_0603_6.3V6M~D

CU143

1

2

1U_0402_6.3V6K~D

CU146

1

2

RU116

0_0805_5%~D

1 2

SHORT

CU144

CU147

1 2

100_0402_1%~D

VCC_AXG_SENSE_R VSS_AXG_SENSE_R

RU115

1 2

100_0402_1%~D

+1.8VS_VCCPLL

CU138

330U_D2_2.5VY_R9M~D+CU138

330U_D2_2.5VY_R9M~D

CU140

1U_0402_6.3V6K~D

CU140

1U_0402_6.3V6K~D

CU141

1U_0402_6.3V6K~D

CU141

1

+

2

10U_0603_6.3V6M~D

CU149

CU145

1

2

1U_0402_6.3V6K~D

CU148

CU151

1

2

CU151

1

2

1U_0402_6.3V6K~D

1

2

10U_0603_6.3V6M~D

CU150

1

2

1U_0402_6.3V6K~D

CU152

1

2

4

1.5A

6A

U2G

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023~D

@

POWER

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

+SM_VREF

ST

AY43

SM_VREF

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0] VCCSA_VID[1]

lines

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

.1U_0402_16V7K

5A

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

CU97

100K_0402_5%~D

+1.5V_VCCDQ

VCCSA_SENSE <59>

VCCSA_VID0 <59> VCCSA_VID1 <59>

2011/07/15 2012/07/15

RU107 1K_0402_1%~D

1

2

12

RU121

@

1U_0402_6.3V6K~D

CU98

1

2

1

2

1 2

0_0603_5%~D

0_0402_5%~D

@RU104

@

0_0402_5%~D

3

1U_0402_6.3V6K~D

CU99

10U_0603_6.3V6M~D

CU109

RU125

+1.5V_CPU_VDDQ

12

@

@ @

@

RU120

RU104

+1.5V_CPU_VDDQ

Compal Secret Data

+0.75VS

12

+V_DDR_REFA

12 1

SSI2

QU4

@QU4

@

AP2302GN-HF_SOT23-3

2

RUN_ON_CPU1.5VS3

1U_0402_6.3V6K~D

CU100

1

2

10U_0603_6.3V6M~D

CU110

1

2

VID[0] VID[1] 2011 2012 0 0 0.90 V Yes Yes 0 1 0.85 V Yes Yes 1 0 0.725 V No Yes 1 1 0.675 V No Yes

1U_0402_6.3V6K~D

CU101

CU102

1

2

10U_0603_6.3V6M~D

CU111

CU112

1

2

1

CU137

CU137 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

CPU1.5V_S3_GATE<8,38,58>

SUSP#<34,38,56,57,58>

Deciphered Date

1

2

1

2

VREF traces should have 2

0 mil trace width &

spacing to other signals

1U_0402_6.3V6K~D

CU104

1

2

10U_0603_6.3V6M~D

CU114

1

2

100K_0402_5%~D

RU112

RU112 0_0402_5%~D

0_0402_5%~D

1 2

RU113

@RU113

@

0_0402_5%~D

1 2

ST

CU155

.1U_0402_16V7K

2

1U_0402_6.3V6K~D

CU105

10U_0603_6.3V6M~D

CU115

RU110

@

CU103

10U_0603_6.3V6M~D

CU113

+1.5V_CPU_VDDQ +1.5V

12 12 12 12

+VSBP

12

RU108

RU108 100K_0402_5%~D

100K_0402_5%~D

RUN_ON_CPU1.5VS3

34

QU6B

QU6B 2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

RUN_ON_CPU1.5VS3# <8,34>

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

1

2

1

2

1

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

2

CU106

CU116

+3VALW

12

61

CU95 0.1U_0402_10V7KCU95 0.1U_0402_10V7K CU96 0.1U_0402_10V7KCU96 0.1U_0402_10V7K CU153 0.1U_0402_10V7KCU153 0.1U_0402_10V7K CU154 0.1U_0402_10V7KCU154 0.1U_0402_10V7K

1U_0402_6.3V6K~D

CU107

1

Intel PDDG rev0.8 : 330uF x 1 - Bottom CPU edge

2

10uF x 8 - Bottom CPU edge 1uF x 10 - Under CPU

330U_D2_2V_Y

CU117

1

+

2

5

QU6A

QU6A 2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

Custom

+1.5V_CPU_VDDQ Source

+1.5V +1.5V_CPU_VDDQ

QU5

AO4728L_SO8

8 7 6 5

RU111

330K_0402_5%

4

12

1

CU136

0.1U_0402_25V6K~D

2

1

1 2 3

12 65Tuesday, February 07, 2012

0.3

5

U2H

D D

C C

B B

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AD17 AD20

AD61 AE13

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58

AF59 AG10 AG14 AG18 AG47 AG52 AG61

AH58

AJ13

AJ16

AJ20

AJ22

AJ26

AJ30

AJ34

AJ38

AJ42

AJ45

AJ48

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61

AM13 AM20 AM22 AM26 AM30 AM34

AC6

AD4

AE8 AF1

AG7 AH4

AK1

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20]

AA8

VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69]

AJ7

VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

VSS

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

4

U2I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46

VSS[204]

D50

VSS[205]

D54

VSS[206]

D58

VSS[207]

D6

VSS[208]

E25

VSS[209]

E29

VSS[210]

E3

VSS[211]

E35

VSS[212]

E40

VSS[213]

F13

VSS[214]

F15

VSS[215]

F19

VSS[216]

F29

VSS[217]

F35

VSS[218]

F40

VSS[219]

F55

VSS[220]

G51

VSS[221]

G6

VSS[222]

G61

VSS[223]

H10

VSS[224]

H14

VSS[225]

H17

VSS[226]

H21

VSS[227]

H4

VSS[228]

H53

VSS[229]

H58

VSS[230]

J1

VSS[231]

J49

VSS[232]

J55

VSS[233]

K11

VSS[234]

K21

VSS[235]

K51

VSS[236]

K8

VSS[237]

L16

VSS[238]

L20

VSS[239]

L22

VSS[240]

L26

VSS[241]

L30

VSS[242]

L34

VSS[243]

L38

VSS[244]

L43

VSS[245]

L48

VSS[246]

L61

VSS[247]

M11

VSS[248]

M15

VSS[249]

IVY-BRIDGE_BGA1023~D

@

VSS

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11

NCTF

VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

3

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

RU119

1 2

0_0402_5%~D@

Dell short to ground

2

follow "458544_CR_PDDG_rev_0.8", section "2.2.1", Intel recommends providing accessibility to the pins F48 & G48 for debug purpose. The pins should be via through to the backside of the board to allow backside probing with no connection to other rails/components on the platform.

1

A A

IVY-BRIDGE_BGA1023~D

@

5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

1

0.3

13 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

+0.75VS

+1.5V

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

BELLW_80001-1021

DQS0#

RESET#

DQS3#

VREF_CA

DQS5#

DQS7#

EVENT#

GND2

BOSS2

DDR_A_DQS#[0..7]<9>

DDR_A_DQS[0..7]<9> DDR_A_D[0..63]<9> DDR_A_MA[0..15]<9>

D D

M1 Circuit (Voltage Divider)

+1.5V

12

RD2

RD2 1K_0402_1%~D

1K_0402_1%~D

12

RD3

RD3 1K_0402_1%~D

1K_0402_1%~D

+V_DDR_REFA

M3+M1: Default Recommendation

All VREF traces should have 20mil trace width & spacing

+V_DDR_REFA

2.2U_0603_6.3V6K~D

1

CD1

2

0.1U_0402_16V7K~D

1

CD2

2

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

1 2

RD6 0_0402_5%~D@RD6 0_0402_5%~D@

QD1 BSS138-G_SOT23-3

1 3

D

S

D

+V_DDR_REFA

DRAMRST_CNTRL_PCH<8,17>

S

SSI2

G

2

close to SO-DIMM

C C

+1.5V

1U_0402_6.3V6K~D

+1.5V

10U_0603_6.3V6M~D

B B

+0.75VS

A A

CD4

CD3

1

2

10U_0603_6.3V6M~D

CD8

CD9

1

2

1U_0402_6.3V6K~D

1

CD17

2

1U_0402_6.3V6K~D

CD10

1

2

CD18

CD6

CD5

1

2

10U_0603_6.3V6M~D

CD12

CD11

1

2

1U_0402_6.3V6K~D

1

CD19

CD20

2

ST

330U_D2_2.5VM_R6M~D

10U_0603_6.3V6M~D

330U_D2_2.5VM_R6M~D

1

CD7

CD13

1

+

2

12

RD10

RD10 1K_0402_5%~D

1K_0402_5%~D

@

+V_DDR_REFA_M3 <10>

DDR_CKE0_DIMMA<9> DDR_CKE1_DIMMA <9>

DDR_A_BS2<9>

M_CLK_DDR0<9> M_CLK_DDR#0<9>

DDR_A_BS0<9> DDR_A_WE#<9>

DDR_A_CAS#<9>

DDR_CS1_DIMMA#<9>

1 2

+3VS

0.1U_0402_16V7K~D

2.2U_0603_6.3V6K~D

2.2U_0603_6.3V6K~D CD22

CD22

1

2

CD21

1

2

RD8 10K_0402_5%~DRD8 10K_0402_5%~D

1 2

RD9 10K_0402_5%~DRD9 10K_0402_5%~D

VSS DQ4 DQ5 VSS

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1 RAS#

VDD

ODT0

VDD

ODT1

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS DQS7

VSS DQ62 DQ63

VSS

SDA

SCL

VTT

+1.5V

2 4

DDR_A_D4

6

DDR_A_D5

8 10

DDR_A_DQS#0

12

DDR_A_DQS0

14 16

DDR_A_D6

18

DDR_A_D7

20 22

DDR_A_D12

24

DDR_A_D13

26 28 30 32 34

DDR_A_D14

36

DDR_A_D15

38 40

DDR_A_D20

42

DDR_A_D21

44 46 48 50

DDR_A_D22

52

DDR_A_D23

54 56

DDR_A_D28

58

DDR_A_D29

60 62

DDR_A_DQS#3

64

DDR_A_DQS3

66 68

DDR_A_D30

70

DDR_A_D31

72

74 76 78

A15 A14

A11

A7 A6

A4 A2

A0

S0#

NC

DDR_A_MA15

80

DDR_A_MA14

82 84

DDR_A_MA11

86

DDR_A_MA7

88 90

DDR_A_MA6

92

DDR_A_MA4

94 96

DDR_A_MA2

98

DDR_A_MA0

100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130

DDR_A_D36

132

DDR_A_D37

134 136 138 140

DDR_A_D38

142

DDR_A_D39

144 146

DDR_A_D44

148

DDR_A_D45

150 152

DDR_A_DQS#5

154

DDR_A_DQS5

156 158

DDR_A_D46

160

DDR_A_D47

162 164

DDR_A_D52

166

DDR_A_D53

168 170 172 174

DDR_A_D54

176

DDR_A_D55

178 180

DDR_A_D60

182

DDR_A_D61

184 186

DDR_A_DQS#7

188

DDR_A_DQS7

190 192

DDR_A_D62

194

DDR_A_D63

196 198 200 202 204

+0.75VS

206 208

DDR3_DRAMRST# <8>

M_CLK_DDR1 <9> M_CLK_DDR#1 <9>

DDR_A_BS1 <9> DDR_A_RAS# <9>

DDR_CS0_DIMMA# <9> M_ODT0 <9>

M_ODT1 <9>

2.2U_0603_6.3V6K~D

0.1U_0402_16V7K~D

CD16

1

2

PCH_SMBDATA <17,39,43,48> PCH_SMBCLK <17,39,43,48>

+VREF_CA

CD15

+1.5V

12

RD4

RD4 1K_0402_1%~D

1K_0402_1%~D

12

RD5

RD5 1K_0402_1%~D

1K_0402_1%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

DDRIII DIMMA LA-7841P

LA-7841P

1

0.3

14 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

intent to blank

D D

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMB

DDRIII DIMMB LA-7841P

LA-7841P

1

0.3

15 65Tuesday, February 07, 2012

0.3

5

1 2

RH1 10M_0402_5%RH1 10M_0402_5%

1 2

YH1

32.768KHZ_12.5PF_9H03200019

15P_0402_50V8J~D

SSI2

1

CH3

2

D D

PT

far away hot spot

HDA_BITCLK_AUDIO<48>

HDA_RST_AUDIO#<48>

HDA_SYNC_AUDIO<48>

HDA_SDOUT_AUDIO<48>

C C

B B

12

RH19

200_0402_5%~D

@

12

RH25

RH25 100_0402_1%~D

100_0402_1%~D

HDA_SDO<38>

+3VS

PCH_JTAG_TCK

+3V_PCH +3V_PCH+3V_PCH

PCH_RTCX1 PCH_RTCX2

1

CH4

CH4 18P_0402_50V8J~D

18P_0402_50V8J~D

2

1 2

RH5

1 2

RH6

1 2

RH7

1 2

RH8

1 2

RH15

1 2

RH11

for enable ME code programing

1 2

RH251 8.2K_0402_5%~DRH251 8.2K_0402_5%~D

1 2

RH35 51_0402_5%RH35 51_0402_5%

12

RH20

200_0402_5%~D

@

PCH_JTAG_TDI PCH_JTAG_TDOPCH_JTAG_TMS

12

RH26

100_0402_1%~D

12

+RTCVCC

RH2

1 2

1M_0402_5%~D

CH5

+RTCVCC

HDA_BIT_CLK

33_0402_5%~D

HDA_SYNC_R HDA_SYNC

33_0402_5%~D

1M_0402_5%~D

HDA_SDOUT

33_0402_5%~D

1K_0402_5%~D

USB_WWAN_DET#

RH18

200_0402_5%~D

@

RH24

100_0402_1%~D

CH5

1U_0402_6.3V6K~D

1 2

RH3 20K_0402_5%~DRH3 20K_0402_5%~D

1 2

RH4 20K_0402_5%~DRH4 20K_0402_5%~D

CH6

1U_0402_6.3V6K~D

HDA_RST#

BSS138-G_SOT23-3

Reserve for RF, close to PCH

+5VS

G

2

S

QH1

SSI2

CH14

10P_0402_50V8J~D@

1

12

2

1

12

2

13

D

USB_WWAN_DET#<48>

12

SM_INTRUDER#

CLP1 & CLP2 place near DIMM

E CMOS

M

CLRP1

@CLRP1

@

SHORT PADS

ME CMOS

CLRP2

@CLRP2

@

SHORT PADS

HDA_SPKR<48>

HDA_SDIN0<48>

PCH_JTAG_TCK<8> PCH_JTAG_TMS<8> PCH_JTAG_TDI<8> PCH_JTAG_TDO<8>

PCH_SPI_CLK

PCH_RTCX1 PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#

HDA_SDOUT

USB_WWAN_DET#

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_SI PCH_SPI_SO

T4921PAD~D @T4921PAD~D @

4

CH1 10P_0402_50V8J~D

CH2 10P_0402_50V8J~D

Reserve for RF, close to PCH

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

BD82PPSM-QNHN-A0_BGA989~D

@

12

RTCIHDA

JTAG

SPI

HDA_SDOUT

HDA_BIT_CLK

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19

LDRQ0#

SERIRQ

C38 A38 B37 C37

D36 E36

K36

RH10 10K_0402_5%~DRH10 10K_0402_5%~D

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

SATA_COMP

AB12 AB13

SATA3_COMP

AH1

RBIAS_SATA3

P3

PCH_SATALED#

V14

PCH_GPIO21

P1

BBS_BIT0 <19>

3

LPC_AD0 <38,40,42> LPC_AD1 <38,40,42> LPC_AD2 <38,40,42> LPC_AD3 <38,40,42>

LPC_FRAME# <38,40,42>

12

SERIRQ <38,40>

SATA_PRX_DTX_N0 <43> SATA_PRX_DTX_P0 <43> SATA_PTX_DRX_N0 <43> SATA_PTX_DRX_P0 <43>

SATA_PRX_DTX_N1 <43> SATA_PRX_DTX_P1 <43> SATA_PTX_DRX_N1 <43> SATA_PTX_DRX_P1 <43>

close PCH within 500mil

1 2

RH21 37.4_0402_1%RH21 37.4_0402_1%

1 2

RH22 49.9_0402_1%RH22 49.9_0402_1%

1 2

RH28 750_0402_1%~DRH28 750_0402_1%~D

RH14 10K_0402_5%~D@RH14 10K_0402_5%~D@ RH12 10K_0402_5%~DRH12 10K_0402_5%~D RH29 10K_0402_5%~DRH29 10K_0402_5%~D

+3VS

+VCCP

12 12 12

+3VS

W=20mils

HDD

mSATA

RTC Battery

+RTCBATT

+3VLP

3

1

2

RH34

RH34 1K_0402_5%~D

1K_0402_5%~D

1 2 2

DH1

DH1 BAT54CW_SOT323-3

BAT54CW_SOT323-3

+RTCVCC

CH12

CH12 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

SATA Gen3 topology, AC cap close to device within 200mil

2

PCH_INTVRMEN

Integrated 1.05V VRM Enable / Disable (should always be pulled high to VccRTC)

INTVRMEN

HDA_SYNC

PLL ODVR VOLTAGE (Internal PD 20K)

HDA_SYNC

HDA_SPKR

No Reboot strap (Internal PD 20K)

SPKR

HDA_SDOUT

Flash Descriptor Security Override / Intel ME Debug Mode (Internal PD 20K)

HDA_SDO

1

RH13 330K_0402_5%RH13 330K_0402_5% RH16 330K_0402_5%@RH16 330K_0402_5%@

Low = X High = enable

RH32 1K_0402_5%~DRH32 1K_0402_5%~D

LOW = SET VCCVRM TO 1.8 V (DEFAULT)

HIGH = SET VCCVRM TO 1.5 V

RH17 1K_0402_5%~D@RH17 1K_0402_5%~D@

Low = Default High = No Reboot

RH23 1K_0402_5%~D@RH23 1K_0402_5%~D@

LOW = Secure HIGH = Override

12 12

12

+RTCVCC

+3V_PCH

+3VS

+3V_PCH

RH41

SPI BIOS Pinout

1)CS# (5)DIO

( (2)DO (6)CLK (3)WP# (7)HOLD# (4)GND (8)VCC

W25X32

@RH41

@

1 2

12

22P_0402_50V8J~D

CH13

@CH13

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC LA-7841P

LA-7841P

1

16 65Tuesday, February 07, 2012

0.3

SPI ROM FOR BIOS & EC ( 8MByte )

+3V_PCH

8 7 6 5

12

RH40

3.3K_0402_5%

PCH_SPI_CLK PCH_SPI_SI

Reserve for EMI, close to UH2

PCH_SPI_CLK

33_0402_5%~D

12

RH33

RH38

1 2

RH38

3.3K_0402_5%

PCH_SPI_CS0# PCH_SPI_SO

A A

1

ST

CH11

CH11 .1U_0402_16V7K

.1U_0402_16V7K

2

UH2

1

/CS

2

DO

/HOLD

3

/WP GND4DIO

W25Q64CVSSIG_SO8~D

5

VCC

CLK

5

PCIE_PRX_GLANTX_N1<41>

10/100/1G LAN

D D

MiniWLAN (Mini Card 1)

CARD_READER

C C

10/100/1G LAN

MiniWLAN (Mini Card 1)

CARD_READER

B B

A A

PCIE_PRX_GLANTX_P1<41> PCIE_PTX_GLANRX_N1<41> PCIE_PTX_GLANRX_P1<41>

PCIE_PRX_WLANTX_N3<42> PCIE_PRX_WLANTX_P3<42> PCIE_PTX_WLANRX_N3<42> PCIE_PTX_WLANRX_P3<42>

PCIE_PRX_CARDTX_N4<48> PCIE_PRX_CARDTX_P4<48> PCIE_PTX_CARDRX_N4<48> PCIE_PTX_CARDRX_P4<48>

CLK_PCIE_LAN#<41> CLK_PCIE_LAN<41>

LANCLK_REQ#<41>

CLK_PCIE_MINI1#<42> CLK_PCIE_MINI1<42>

MINI1CLK_REQ#<42>

CLK_PCIE_CD#<48> CLK_PCIE_CD<48>

CDCLK_REQ#<48>

CLK_CPU_ITP#<8> CLK_CPU_ITP<8>

CLK_RES_ITP#<8> CLK_RES_ITP<8>

1 2

CH15 0.1U_0402_10V7K~DCH15 0.1U_0402_10V7K~D

1 2

CH16 0.1U_0402_10V7K~DCH16 0.1U_0402_10V7K~D

1 2

CH19 0.1U_0402_10V7K~DCH19 0.1U_0402_10V7K~D

1 2

CH20 0.1U_0402_10V7K~DCH20 0.1U_0402_10V7K~D

1 2

CH21 0.1U_0402_10V7K~DCH21 0.1U_0402_10V7K~D

1 2

CH22 0.1U_0402_10V7K~DCH22 0.1U_0402_10V7K~D

RH66 10K_0402_5%~DRH66 10K_0402_5%~D

+3V_PCH

RH69 10K_0402_5%~DRH69 10K_0402_5%~D

+3VS

RH74 10K_0402_5%~DRH74 10K_0402_5%~D

+3VS

RH77 10K_0402_5%~DRH77 10K_0402_5%~D

+3V_PCH

RH81 10K_0402_5%~DRH81 10K_0402_5%~D

+3V_PCH

RH83 10K_0402_5%~DRH83 10K_0402_5%~D

+3V_PCH

RH84 10K_0402_5%~DRH84 10K_0402_5%~D

+3V_PCH

RH88 10K_0402_5%~DRH88 10K_0402_5%~D

+3V_PCH

RH90 10K_0402_5%~DRH90 10K_0402_5%~D

+3V_PCH

PT2

RH91 0_0402_5%~D@RH91 0_0402_5%~D@ RH92 0_0402_5%~D@RH92 0_0402_5%~D@

RH93 0_0402_5%~D@RH93 0_0402_5%~D@ RH94 0_0402_5%~D@RH94 0_0402_5%~D@

1 2

4

12

12 12

PCIE_PTX_GLANRX_N1_C PCIE_PTX_GLANRX_P1_C

PCIE_PTX_WLANRX_N3_C PCIE_PTX_WLANRX_P3_C

PCIE_PTX_CARDRX_N4_C PCIE_PTX_CARDRX_P4_C

T2PAD~D @T2PAD~D @ T3PAD~D @T3PAD~D @

PCIECLKREQ0#

PCH_GPIO20

PCH_GPIO44

PEG_B_CLKREQ#

PCH_GPIO45

PCH_GPIO46 CLK_BCLK_ITP#

CLK_BCLK_ITP

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

BD82PPSM-QNHN-A0_BGA989~D

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

E12

PCH_LID_SW_IN#

H14

SMBCLK

C9

SMBDATA

A12

DRAMRST_CNTRL_PCH

C8

SML0CLK

G12

SML0DATA

C13

PCH_GPIO74

E14

SML1CLK

M16

SML1DATA

M7

connects to a Wireless LAN Device supporting Intel Active Management Technology(iAMT)

T11

P10

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18

CLKIN_DMI#

BE18

CLKIN_DMI

BJ30 BG30

G24

CLKIN_DOT96#

E24

CLKIN_DOT96

AK7

CLKIN_SATA#

AK5

CLKIN_SATA

K45

CLK_PCH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

CLKOUTFLEX0 CLK_PCI_TPM

F47

KB_DET#

H47

CLKOUTFLEX2

K49

SSI2

KB_DET#

ST

1 2

SHORT

RH44 0_0402_5%~D

+3V_PCH

RH64

RH64 10K_0402_5%~D

10K_0402_5%~D

1 2

T26 PAD~D@ T26 PAD~D@ T27 PAD~D@ T27 PAD~D@

CLKIN_GND1

1 2

RH85 90.9_0402_1%RH85 90.9_0402_1%

1 2

RH97

1 2

RH245

@RH245

@

Remove CAM_DET#

RH98 100K_0402_5%~DRH98 100K_0402_5%~D

12

SMBCLK <42> SMBDATA <42>

DRAMRST_CNTRL_PCH <8,14>

PEG_A_CLKRQ# <24>

CLK_PEG_VGA# <24> CLK_PEG_VGA <24>

CLK_CPU_DMI# <8> CLK_CPU_DMI <8>

22_0402_1%

2

CLK_PCI_LPBACK <19>

+VCCP

KB_DET# <39>

+3VS

EC_LID_OUT# <38>

PCH <-> MEM, LCD, TP, WLAN, FFS, IO

CLK_PCI_TPM <40>

LAN_25M <41>

6 1

SMBCLK

DMN66D0LDW-7_SOT363-6~D

1 2

0_0402_5%~D

SMBDATA

PCH <-> EC

SML1CLK

SML1DATA

ST

6 1

DMN66D0LDW-7_SOT363-6~D

option for LAN 25MHz

SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA PCH_LID_SW_IN#

DRAMRST_CNTRL_PCH

PCH_GPIO74

+3VS +3VS

2.2K_0402_5%~D

2

QH2A

RH78

@

DMN66D0LDW-7_SOT363-6~D

@

QH3A

DMN66D0LDW-7_SOT363-6~D

+3VS

2

5

3

4

QH2B

RH82

1 2

@

0_0402_5%~D

PT

5

3

4

@

QH3B

CLKIN_DMI# CLKIN_DMI CLKIN_GND1 CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

P

T PT

1

1 2

RH45 2.2K_0402_5%~DRH45 2.2K_0402_5%~D

1 2

RH46 2.2K_0402_5%~DRH46 2.2K_0402_5%~D

1 2

RH47 2.2K_0402_5%~DRH47 2.2K_0402_5%~D

1 2

RH49 2.2K_0402_5%~DRH49 2.2K_0402_5%~D

1 2

RH50 2.2K_0402_5%~DRH50 2.2K_0402_5%~D

1 2

RH51 2.2K_0402_5%~DRH51 2.2K_0402_5%~D

1 2

RH52 10K_0402_5%~DRH52 10K_0402_5%~D

1 2

RH53 1K_0402_5%~DRH53 1K_0402_5%~D

1 2

RH240 10K_0402_5%~DRH240 10K_0402_5%~D

RH71

RH72

2.2K_0402_5%~D

1 2

PCH_SMBCLK <14,39,43,48>

PCH_SMBDATA <14,39,43,48>

PCH_SMLCLK <24,35,38>

PCH_SMLDATA <24,35,38>

1 2

RH56 10K_0402_5%~DRH56 10K_0402_5%~D

1 2

RH57 10K_0402_5%~DRH57 10K_0402_5%~D

1 2

RH55 10K_0402_5%~DRH55 10K_0402_5%~D

1 2

RH58 10K_0402_5%~DRH58 10K_0402_5%~D

1 2

RH59 10K_0402_5%~DRH59 10K_0402_5%~D

1 2

RH60 10K_0402_5%~DRH60 10K_0402_5%~D

1 2

RH61 10K_0402_5%~DRH61 10K_0402_5%~D

1 2

RH62 10K_0402_5%~DRH62 10K_0402_5%~D

ST

RH65

33_0402_5%~D

RH65

CLK_PCI_LPBACK

Reserve for EMI, close to PCH

12

RH891M_0402_5%~D RH891M_0402_5%~D

YH2

1

IN

OUT

2

GND

1

25MHZ_18PF_X3G025000DI1H-H~D

15P_0402_50V8J~D

CH27

2

GND

SSI2

ST

CLK_PCI_TPM

1 2

CH98 10P_0402_50V8J~DCH98 10P_0402_50V8J~D

+3V_PCH

CH26

1 2

12

22P_0402_50V8J~D

XTAL25_IN XTAL25_OUT

3 4

1

2

15P_0402_50V8J~D

CH28

Reserve for EMI, close to PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK LA-7841P

LA-7841P

1

17 65Tuesday, February 07, 2012

0.3

5

UH1C

DMI_CTX_PRX_N0<7> DMI_CTX_PRX_N1<7> DMI_CTX_PRX_N2<7> DMI_CTX_PRX_N3<7>

DMI_CTX_PRX_P0<7> DMI_CTX_PRX_P1<7> DMI_CTX_PRX_P2<7> DMI_CTX_PRX_P3<7>

DMI_CRX_PTX_N0<7>

D D

4mil width and close PCH within 500mil

XDP_DBRESET#<8>

C C

PM_DRAM_PWRGD<8>

PCH_RSMRST#<38>

SUSPWRDNACK<38>

PT

PBTN_OUT#<8,38>

AC_PRESENT<38>

B B

PCH_GPIO72 RI# WAKE# AC_PRESENT SUSPWRDNACK

P

T

PCH_RSMRST# SYS_PWROK

+1.05VS_VCC_EXP

PCH_PWROK

1 2

RH116 10K_0402_5%~DRH116 10K_0402_5%~D

1 2

RH117 10K_0402_5%~DRH117 10K_0402_5%~D

1 2

RH118 10K_0402_5%~DRH118 10K_0402_5%~D

1 2

RH121 10K_0402_5%~DRH121 10K_0402_5%~D

1 2

RH124 10K_0402_5%~DRH124 10K_0402_5%~D

1 2

RH127 10K_0402_5%~DRH127 10K_0402_5%~D

1 2

RH130 10K_0402_5%~DRH130 10K_0402_5%~D

DMI_CRX_PTX_N1<7> DMI_CRX_PTX_N2<7> DMI_CRX_PTX_N3<7>

DMI_CRX_PTX_P0<7> DMI_CRX_PTX_P1<7> DMI_CRX_PTX_P2<7> DMI_CRX_PTX_P3<7>

1 2

RH99 49.9_0402_1%RH99 49.9_0402_1%

1 2

RH100 750_0402_1%~DRH100 750_0402_1%~D

RH104 0_0402_5%~D

RH105 0_0402_5%~D

RH106 0_0402_5%~D

ST

T

S

PCH_RSMRST# PCH_RSMRST#_R

RH108 0_0402_5%~D

SUSPWRDNACK

RH110 0_0402_5%~D

AC_PRESENT

RH112 0_0402_5%~D

ST

T4924PAD~D@T4924PAD~D

@

1 2

@

1 2

SHORT

1 2

SHORT

1 2

SHORT

1 2

SHORT

1 2

SHORT

+3V_PCH

DMI_IRCOMP RBIAS_CPY

SUSACK#

SYS_PWROK

PM_PWROK_R SUS_STAT#

APWROK_R

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

BD82PPSM-QNHN-A0_BGA989~D

DSWODVREN

Deep S4/S5 Well On-Die Voltage Regulator Enable

DSWVRMEN

4

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

DMI

System Power Management

RH119 330K_0402_5%RH119 330K_0402_5% RH122 330K_0402_5%@RH122 330K_0402_5%@

ow = disable

L

FDI_RXP7

FDI

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

12 12

High = enable

+RTCVCC

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

SSI2

A18

DSWODVREN

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

1 2

WAKE#

SHORT

RH103 0_0402_5%~D

PM_CLKRUN#

ST

SUSCLK_R

RH107 0_0402_5%~D

SLP_A#

PM_SLP_SUS#

SUSCLK_R

Reserve for RF, close to PCH

FDI_CTX_PRX_N0 <7> FDI_CTX_PRX_N1 <7> FDI_CTX_PRX_N2 <7> FDI_CTX_PRX_N3 <7> FDI_CTX_PRX_N4 <7> FDI_CTX_PRX_N5 <7> FDI_CTX_PRX_N6 <7> FDI_CTX_PRX_N7 <7>

FDI_CTX_PRX_P0 <7> FDI_CTX_PRX_P1 <7> FDI_CTX_PRX_P2 <7> FDI_CTX_PRX_P3 <7> FDI_CTX_PRX_P4 <7> FDI_CTX_PRX_P5 <7> FDI_CTX_PRX_P6 <7> FDI_CTX_PRX_P7 <7>

FDI_INT <7> FDI_FSYNC0 <7> FDI_FSYNC1 <7> FDI_LSYNC0 <7> FDI_LSYNC1 <7>

1 2

SHORT

RH101 0_0402_5%~D

T5 PAD~D

@

@RH105 0_0402_5%~D

SHORT

T4938 PAD~D

@

T4927 PAD~D

@

H_PM_SYNC <8>

@

ST

12

PM_SLP_S5# <38>

PM_SLP_S4# <38>

PM_SLP_S3# <38,43>

PT

CH29

12

10P_0402_50V8J~D

3

+3VS

PCH_RSMRST#_RPCH_DPWROK

WAKE_PCH# <38>

SSI2

PM_CLKRUN# <40>

SUSCLK <38>

ENBKL<38> VGA_LVDDEN<35>

VGA_PWM<35>

LVDS_DDC_CLK<35>

LVDS_DDC_DATA<35>

1 2

RH133 2.2K_0402_5%~DRH133 2.2K_0402_5%~D

1 2

RH135 2.2K_0402_5%~DRH135 2.2K_0402_5%~D

1 2

RH123 2.37K_0402_1%~DRH123 2.37K_0402_1%~D

LVDS_ACLK-<35> LVDS_ACLK+<35>

LVDS_A0-<35> LVDS_A1-<35> LVDS_A2-<35>

LVDS_A0+<35> LVDS_A1+<35> LVDS_A2+<35>

LVDS_BCLK-<35> LVDS_BCLK+<35>

LVDS_B0-<35> LVDS_B1-<35> LVDS_B2-<35>

LVDS_B0+<35> LVDS_B1+<35> LVDS_B2+<35>

RH115

1K_0402_0.5%~D

+3VS

1 2

RH136 8.2K_0402_5%~DRH136 8.2K_0402_5%~D

1 2

RH137 2.2K_0402_5%~DRH137 2.2K_0402_5%~D

1 2

RH138 2.2K_0402_5%~DRH138 2.2K_0402_5%~D

1 2

RH132 100K_0402_5%~DRH132 100K_0402_5%~D

1 2

RH134 100K_0402_5%~DRH134 100K_0402_5%~D

1 2

RH241 1M_0402_5%~DRH241 1M_0402_5%~D

ENBKL VGA_LVDDEN

LVDS_DDC_CLK LVDS_DDC_DATA

CTRL_CLK CTRL_DATA

LVDS_IBG

T4PAD~D@ T4PAD~D@

CRT_IREF

12

2

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

BD82PPSM-QNHN-A0_BGA989~D

PM_CLKRUN# LVDS_DDC_CLK LVDS_DDC_DATA

VGA_LVDDEN ENBKL DP_PCH_HPD

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

HDMI

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

mDP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

DMC

DP_PCH_HPD

1

PCH_SDVO_CTRLCLK <36>

PCH_SDVO_CTRLDATA <36>

HDMI_PCH_HPD# <36>

HDMI_A0N_VGA <36> HDMI_A0P_VGA <36> HDMI_A1N_VGA <36> HDMI_A1P_VGA <36> HDMI_A2N_VGA <36> HDMI_A2P_VGA <36> HDMI_A3N_VGA <36> HDMI_A3P_VGA <36>

PCH_DDPC_CTRLCLK <37> PCH_DDPC_CTRLDATA <37>

PCH_DPC_AUXN <37> PCH_DPC_AUXP <37>

DP_PCH_HPD <37>

PCH_DPC_N0 <37> PCH_DPC_P0 <37> PCH_DPC_N1 <37> PCH_DPC_P1 <37> PCH_DPC_N2 <37> PCH_DPC_P2 <37> PCH_DPC_N3 <37> PCH_DPC_P3 <37>

+3VS

1

CH30

0.1U_0402_16V7K~D

PCH_PWROK<38>

A A

VGATE<8,38,60>

PCH_PWROK

5

2

5

1

IN1

VCC

OUT

2

IN2

GND

MC74VHC1G08DFT2G_SC70-5

3

UH3

4

SYS_PWROK

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP LA-7841P

LA-7841P

1

18 65Tuesday, February 07, 2012

0.3

5

1 2

RH242 1K_0402_5%~D@RH242 1K_0402_5%~D@

1 2

BBS_BIT1

@

RH244 1K_0402_5%~D

BBS_BIT0 <16>

Boot BIOS Strap (Both internal PU 20K) BIT 1

BIT 0

0 1

0

+3VS

8.2K_0804_8P4R_5%

SSI2

Boot BIOS Location

LPC Reserved PCI(non-mobile) SPI

RPH1

18

PCI_PIRQA#

27

PCI_PIRQB#

36

PCI_PIRQD#

45

PCI_PIRQC#

RPH2

18

DGPU_HOLD_RST#

27

PCH_GPIO52

36

DGPU_PWR_EN#

45

WL_OFF#

RPH3

18

FFS_INT1

27

ODD_DA#

36

PCH_GPIO5

45

+3VS

1 2

2

1

D

CH99

DIS@

D

1

S

3

RH247

RH247 10K_0402_5%~D

10K_0402_5%~D

DIS@

2

DGPU_PWR_EN#

G

QH6

DIS@

QH6

DIS@

ME2N7002D-G_SOT23-3

USB Conn 1 USB Conn 2 (Power Share)

GNT[1:3]# have internal w

eak PU, and disable

after PLTRST# deassert

SATA1GPGNT1#

0

D D

0 1 1 1

C C

DGPU_PWR_EN<33,61>

0.01U_0402_16V7K~D

1 2

RH243 1K_0402_5%~D

A16 Top-Block Swap Override (Internal PU 20K)

Low = swap enabled

GNT3#

High = Default

REQ[1:3]# & GNT[1:3]# are used as GPIO on Mobile

ST

B B

Switchable Graphics

DGPU_PWR_EN# GPIO54 Output High High Must have

DGPU_PWROK GPIO17 Input - - Must have

A A

DGPU_HOLD_RST# GPIO50 Output Low Low Must have

CH31

S

T

Reserve for RF, close to PCH

12

CLK_PCI1

10P_0402_50V8J~D

CH100

1 2

CLK_LPC_DEBUG

@

27P_0402_50V8J

CLK_PCI_LPBACK<17>

CLK_PCI_LPC<38>

CLK_LPC_DEBUG<42>

Signal GPIO Type DuringReset After Reset Usage Description

Driven by Switchable Graphics Driver to turn on/off the discrete graphics power. 0 = dGPU power switch turned on 1 = Power switch turned off

Driven by dGPU VR to indicate the power status to PCH. Used to enable clocks to dGPU. 0 = dGPU power is not stable. Keep clock disabled & reset asserted. 1 = dGPU power is stable. Clock can be enabled; reset can be deasserted If DGPU_PRSNT# is 1, in-order to get regular discrete GFX cards working, program DGPU_PWROK as GPO and assert a high value (1) on the pin.

Discrete Graphics Enable signal. Controlled by Switchable Graphics Driver and driven by PCH GPIO. Used to gate with Platform Reset to enable the Reset for dGPU. 0 = Keep dGPU in reset. 1 = Reset is released. This action taken 100 ms after DGPU_PWROK to ensure clock is stable.

5

4

WL_OFF#

@

USB3RN1<44> USB3RN2<45>

USB3RP1<44> USB3RP2<45>

USB3TN1<44> USB3TN2<45>

USB3TP1<44> USB3TP2<45>

EN_CAM<35>

WL_OFF#<42>

FFS_INT1<43> DP_CBL_DET<37>

T6PAD~D @T6PAD~D @

1 2 1 2

4

12

T8PAD~D @T8PAD~D @ T9PAD~D @T9PAD~D @

RH144 22_0402_5%RH144 22_0402_5% RH145 22_0402_5%RH145 22_0402_5% RH252 22_0402_5%RH252 22_0402_5%

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST# PCH_GPIO52 DGPU_PWR_EN#

BBS_BIT1 EN_CAM WL_OFF#

FFS_INT1 ODD_DA#

PCH_GPIO5

PCH_PLTRST#

CLK_PCI0 CLK_PCI1 CLK_LPC_DEBUG_R CLK_PCI3 CLK_PCI4

UH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3TP1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

BD82PPSM-QNHN-A0_BGA989~D

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

RSVD

USB30

PCI

USB

PLT_RST#<8,38,40,41,42,48>

100K_0402_5%~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

1 2

RH149 0_0402_5%~D

12

RH155

SN74AHC1G08DCKR_SC70-5

3

NV_ALE

AV10 AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

USBRBIAS

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

USB_OC3#

L16

USB_OC4#

A16

USB_OC5#

D14

USB_OC6#

C14

USB_OC7#

@

+3VS

5

1

P

IN1

4

O

2

IN2

G

3

UH5

@

2011/07/15 2012/07/15

1 2

RH139 1K_0402_5%~D@RH139 1K_0402_5%~D@

Intel Anti-Theft Techonlogy

NV_ALE

USB20_N0 <44> USB20_P0 <44> USB20_N1 <45> USB20_P1 <45>

USB20_N4 <42> USB20_P4 <42> USB20_N5 <48> USB20_P5 <48>

USB20_N12 <35> USB20_P12 <35>

Within 500 mils

1 2

RH143 22.6_0402_1%RH143 22.6_0402_1%

USB_OC0# <44> USB_OC1# <45>

PCH_PLTRST#

RH157

RH157 10K_0402_5%~D

10K_0402_5%~D

1 2

Compal Secret Data

Deciphered Date

Low = disable High = enable

USB Conn 1 USB Conn 2 (Power Share)

Mini Card(WLAN) Mini Card(WWAN)

Camera

PLTRST_VGA#<24>

2

+1.8VS

RH154

DIS@ RH154

DIS@

100K_0402_5%~D

PT

2

10K_1206_8P4R_5%~D

1 2

RH148 0_0402_5%~D@RH148 0_0402_5%~D@

+3V_GPU

5

P

IN1

4

O

IN2

G

3

UH4

DIS@

4 5 3 6 2 7 1 8

1 2

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USB_OC4# USB_OC5# USB_OC6# USB_OC7#

12

SN74AHC1G08DCKR_SC70-5

RPH4

RPH5

PT

1

+3V_PCH

1 2

RH151 0_0402_5%~D@RH151 0_0402_5%~D@

1 2

RH152 0_0402_5%~DDIS@ RH152 0_0402_5%~DDIS@

12

RH156 100K_0402_5%~D

100K_0402_5%~D

PT

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM LA-7841P

LA-7841P

DIS@RH156

DIS@

DGPU_HOLD_RST#

PT

PCH_PLTRST#

1

DGPU_PWROK <20,61>

19 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

PCH_GPIO0 PCH_GPIO1 PCH_GPIO6 EC_SCI# PCIE_MCARD1_DET# MSATA_DET#

D D

BT_RADIO_DIS# PCH_GPIO16 WWAN_RADIO_DIS# KB_RST#

EC_SMI# PCH_GPIO12 HDD_DETECT#

PCH_GPIO36 PCH_GPIO37 DBC_EN CE_EN

C C

SSI2

PCH_GPIO15

RH158 1K_0402_5%~DRH158 1K_0402_5%~D

1 2

RH170 10K_0402_5%~DRH170 10K_0402_5%~D

1 2

RH164 10K_0402_5%~DRH164 10K_0402_5%~D

1 2

RH184 10K_0402_5%~DRH184 10K_0402_5%~D

1 2

RH160 10K_0402_5%~DRH160 10K_0402_5%~D

1 2

RH172 10K_0402_5%~DRH172 10K_0402_5%~D

1 2

RH176 10K_0402_5%~DRH176 10K_0402_5%~D

1 2

RH174 8.2K_0402_5%~DRH174 8.2K_0402_5%~D

1 2

RH181 10K_0402_5%~DRH181 10K_0402_5%~D

1 2

RH180 10K_0402_5%~DRH180 10K_0402_5%~D

1 2

RH175 10K_0402_5%~DRH175 10K_0402_5%~D

1 2

RH183 10K_0402_5%~DRH183 10K_0402_5%~D

1 2

RH248 10K_0402_5%~DRH248 10K_0402_5%~D

1 2

RH179 10K_0402_5%~DRH179 10K_0402_5%~D

1 2

RH171 10K_0402_5%~DRH171 10K_0402_5%~D

1 2

RH246 10K_0402_5%~DRH246 10K_0402_5%~D

1 2

RH177 10K_0402_5%~DRH177 10K_0402_5%~D

1 2

RH182 10K_0402_5%~DRH182 10K_0402_5%~D

1 2

+3V_PCH

TLS Confidentiality (Internal PD 20K)

Low = no confidentiality

GPIO15

High = confidentiality

1 2

RH165 1K_0402_5%~D@RH165 1K_0402_5%~D@

On-Die PLL Voltage Regulator (Internal PU 20K)

B B

GPIO28

PCH_GPIO28 needs to be connected to XDP_FN8 PCH_GPIO35 needs to be connected to XDP_FN9 PCH_GPIO15 needs to be connected to XDP_FN16

PCH_GPIO28

Low = Disable High = Enable

+3VS

+3V_PCH

SSI2

DBC_EN<35>

SSI2

CE_EN<35>

UH1F

PCH_GPIO0 PCH_GPIO1 PCH_GPIO6

T4915PAD~D@T4915PAD~D

@

EC_SCI# EC_SMI# PCH_GPIO12 PCH_GPIO15

PCH_GPIO16

MSATA_DET#

PCH_GPIO27 PCH_GPIO28 BT_RADIO_DIS# DBC_EN PCH_GPIO36 PCH_GPIO37 PCIE_MCARD1_DET# CE_EN

WWAN_RADIO_DIS# HDD_DETECT#

PCH_GPIO35

EC_SCI#<38> EC_SMI#<38>

DGPU_PWROK<19,61>

MSATA_DET#<48>

BT_RADIO_DIS#<42>

PCIE_MCARD1_DET#<42>

FFS_INT2<43>

WWAN_RADIO_DIS#<48>

HDD_DETECT#<43>

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

BD82PPSM-QNHN-A0_BGA989~D

TACH[0:7] are not a

vailable on Mobile,

used as GPIO

GPIO

NCTF

TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

CFG_ID

PCH_PECI_R KB_RST#

H_THERMTRIP#_C INIT3_3V# NV_CLE

KB_BL_DET <39>

USB_MCARD1_DET# <42>

T4914 PAD~D

@

INIT3_3Vl has weak internal PU, can't pull low

Weak internal PU, Do not pull low

NV_CLE

1K_0402_5%~D

RH167

RH161

1 2

0_0402_5%~D@

1 2

RH162

390_0402_5%

+VCCPNAND

12

+3VS

12

put two Res close to minimize the stub

DMI and FDI Tx/Rx Termination Voltage (Internal PD 20K)

Low=Set to Vss

DF_TVS

High=Set to Vcc

RH159

RH159 10K_0402_5%~D

10K_0402_5%~D

1 2

RH166

2.2K_0402_5%~D

H_SNB_IVB# <8>

GATEA20 <38> H_PECI <8,38> KB_RST# <38> H_CPUPWRGD <8>

H_THERMTRIP# <8>

close to PCH within 0.25" ~ 2.5"

Configuration ID : DIS = High UMA = Low

10K_0402_5%~D

CFG_ID

10K_0402_5%~D

RH250

DIS@

RH249

UMA@

+3VS

1 2

Please refer to Huron River Debug Board DG 0.5

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC LA-7841P

LA-7841P

1

20 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

D D

UH1G

+VCCP

C C

+VCCP +1.05VS_VCC_EXP

1 2

10U_0603_6.3V6M~D

B B

+VCCP

@

RH194 0_0603_5%~D

+1.5VS +VCCAFDI_VRM

RH197

0_0603_5%~D

+1.05VS_VCCCORE

@

JP1

12

JUMP_43X39

CH35

10U_0603_6.3V6M~D

+VCCP

JP15

@

JUMP_43X118

CH45

+1.05VS_VCCAPLL_FDI

12

1

2

LH3

@LH3

@

1 2

1UH_LB2012T1R0M_20%~D

10U_0603_6.3V6M~D

1

CH46

2

1U_0402_6.3V6K~D

+3VS

1

CH53

2

@

1U_0402_6.3V6K~D

1

CH36

CH37

2

1U_0402_6.3V6K~D

+VCCAPLLEXP

CH42

@

1

CH47

2

1U_0402_6.3V6K~D

1

CH51

0.1U_0402_10V7K~D

2

1

CH38

2

1U_0402_6.3V6K~D

+VCCP

1

2

1

CH49

CH48

2

1U_0402_6.3V6K~D

+VCCAFDI_VRM

+VCCP

1U_0402_6.3V6K~D

UH1G

1300mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

BD82PPSM-QNHN-A0_BGA989~D

POWER

2925mA

CRTLVDS

1mA

VCC CORE

60mA

20mA

DMI

VCCIO

190mA

DFT / SPI HVCMOS

FDI

1mA

VCCADAC

VSSADAC

VCCALVDS VSSALVDS

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

20mA

VCCSPI

U48

U47

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

+3V_VCCPSPI

1

2

0.01U_0402_16V7K~D

1

CH39

2

+3VS

1

CH43

0.1U_0402_10V7K~D

2

+VCCAFDI_VRM

+VCCP

1

CH50

CH50 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+VCCPNAND

1

2

1

2

+VCCADAC

1

CH33

CH32

2

0.1U_0402_10V7K~D

0.01U_0402_16V7K~D

+VCCTX_LVDS

0.01U_0402_16V7K~D

22U_0805_6.3V6M~D

1

CH40

2

+VCCP

1

CH44

2

1U_0402_6.3V6K~D

JP16

@ JP16

@

JUMP_43X39

CH52

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D JP17

@ JP17

@

JUMP_43X39

CH54

CH54 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

LH1

BLM18PG181SN1_0603~D

1

CH34

CH34 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

2

LH2

0.1UH_MLF1608DR10KT_10%_1608

CH41

1

0.1uH inductor, 200mA

2

12

+1.8VS

12

+3V_PCH

+3VS

12

+3VS

+1.8VS

12

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

1.05

S0 Iccmax Current (A)

0.001

5

0.001

0.266

0.001

0.08

1.3

0.042

1.05VccIO 2.925

1.05VccASW 1.01

3.3VccSPI 0.02

3.3VccDSW 0.003

1.8 0.19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1.5 0.16

1.05VccCLKDMI

0.02

VccSSC 1.05 0.095

ccDIFFCLKN 1.05 0.055

V

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.06

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (6/8) PWR

PCH (6/8) PWR LA-7841P

LA-7841P

1

0.3

21 65Tuesday, February 07, 2012

0.3

5

+3V_PCH

D D

C C

+VCCP

1 2

+VCCA_DPLLA

+VCCA_DPLLB

RH239 0_0402_5%~DRH239 0_0402_5%~D

RH232 0_0402_5%~DRH232 0_0402_5%~D

B B

A A

SSI2

+VCCP

@LH4

@

1 2

10U_0603_6.3V6M~D

SSI2

LH7

LH7 10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

1 2

LH8

10UH_LBR2012T100M_20%~D

SSI2

+VCCP

1

CH87

4.7U_0603_6.3V6K~D

2

LH4 10UH_LBR2012T100M_20%~D

10UH_LBR2012T100M_20%~D

+VCCP

CH59

@

+VCCP

1

CH80

CH80 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

CH82

CH82 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

CH88

0.1U_0402_10V7K~D

2

+VCCAPLL_CPY_PCH

1

2

1

+

2

+VCCP

1 2

SHORT

RH199 0_0603_5%~D

ST

@

JP18

12

JUMP_43X39

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

1

CH94

CH96

2

1U_0402_6.3V6K~D

220U_B2_2.5VM_R35M~D

+VCCP

RH219 0_0603_5%~D

1

CH89

0.1U_0402_10V7K~D

2

0.1U_0402_10V7K~D

1

+

CH95

2

220U_B2_2.5VM_R35M~D

0.1U_0402_10V7K~D

1

CH84

CH84 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

@

4

12

@

RH198 0_0603_5%~D

1

CH55

2

CH58

@ CH58

@

0.1U_0402_10V7K~D

+3VS

CH75

1U_0402_6.3V6K~D

+1.05VM_VCCASW

1

CH68

2

1U_0402_6.3V6K~D

1

CH97

2

1U_0402_6.3V6K~D

1

CH79

2

12

1

@

CH86

CH86 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+RTCVCC

+VCCACLK

+VCCPDSW

12

+PCH_VCCDSW

1

+VCCAPLL_CPY_PCH

2

+VCCP

+VCCSUS1

1

@

CH62

CH62 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

1

CH65

CH66

2

1

2

CH85 0.1U_0402_10V7K~DCH85 0.1U_0402_10V7K~D

1

2

CH66

2

22U_0805_6.3V6M~D

1

CH69

CH70

2

1U_0402_6.3V6K~D

+VCCRTCEXT

+VCCAFDI_VRM

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

12

+VCCSST

+1.05VM_VCCSUS

1

CH90

CH91

2

0.1U_0402_10V7K~D

UH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

1

BD82PPSM-QNHN-A0_BGA989~D

CH92

2

1U_0402_6.3V6K~D

3

POWER

VCCIO[29]

119mA

PCI/GPIO/LPCMISC

SATA USB

10mA

HDA

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

1mA

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

1mA

VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5]

VCC3_3[1] VCC3_3[8] VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12] VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2] VCCIO[3] VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

V5REF

3mA

1010mA

Clock and Miscellaneous

80mA 80mA

55mA

95mA

1mA

CPURTC

N26 P26 P28 T27 T29

T23 T24 V23 V24 P24

T26

M26

+PCH_V5REF_SUS

AN23

+VCCA_USBSUS

AN24

P34

+PCH_V5REF_RUN

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

T21

V21

T19

P32

CH93

0.1U_0402_10V7K~D

+VCCP

1

CH56

CH56 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+3V_PCH

1

CH60

0.1U_0402_10V7K~D

2

+VCCP

1

CH71

CH71 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+3VS

+VCCAFDI_VRM

+VCCP

+3V_PCH

1

2

CH63

@ CH63

@

1 2

1U_0402_6.3V6K~D

+3V_PCH

+3VS

1

CH76

0.1U_0402_10V7K~D

2

1

CH77

0.1U_0402_10V7K~D

2

1

CH83

CH83 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

+3VS

+3V_PCH

0.1U_0402_10V7K~D

1

2

1

CH61

0.1U_0402_10V7K~D

2

+3V_PCH

1

CH67

2

CH73

0.1U_0402_10V7K~D

+VCCP

1

CH78

CH78 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

2

SSI2

LH6

@LH6

@

10UH_LBR2012T100M_20%~D

1 2

1

CH81

CH81 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

@

2

RH201

0_0603_5%~D

PCH_PWR_EN#<34>

+VCCP+VCCSATAPLL

QH5

QH5 AO3419L_SOT23-3

AO3419L_SOT23-3

12

PT

RH208

10_0402_1%~D

RH212

10_0402_1%~D

1

+5V_PCH+5VALW

D

S

D

S

G

2

+3V_PCH+5V_PCH

12

+3VS+5VS

12

13

1

CH57

2

0.1U_0402_10V7K~D

21

DH2

DH2 RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

+PCH_V5REF_SUS

1

CH64

0.1U_0402_10V7K~D

2

21

DH3

DH3 RB751S40T1_SOD523-2~D

RB751S40T1_SOD523-2~D

+PCH_V5REF_RUN

1

CH72

CH72 1U_0402_16V6K

1U_0402_16V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (7/8) PWR

PCH (7/8) PWR LA-7841P

LA-7841P

1

0.3

22 65Tuesday, February 07, 2012

0.3

5

UH1H

D D

C C

B B

A A

UH1H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

BD82PPSM-QNHN-A0_BGA989~D

4

AK38

VSS[80]

AK4

VSS[81]

AK42

VSS[82]

AK46

VSS[83]

AK8

VSS[84]

AL16

VSS[85]

AL17

VSS[86]

AL19

VSS[87]

AL2

VSS[88]

AL21

VSS[89]

AL23

VSS[90]

AL26

VSS[91]

AL27

VSS[92]

AL31

VSS[93]

AL33

VSS[94]

AL34

VSS[95]

AL48

VSS[96]

AM11

VSS[97]

AM14

VSS[98]

AM36

VSS[99]

AM39

VSS[100]

AM43

VSS[101]

AM45

VSS[102]

AM46

VSS[103]

AM7

VSS[104]

AN2

VSS[105]

AN29

VSS[106]

AN3

VSS[107]

AN31

VSS[108]

AP12

VSS[109]

AP19

VSS[110]

AP28

VSS[111]

AP30

VSS[112]

AP32

VSS[113]

AP38

VSS[114]

AP4

VSS[115]

AP42

VSS[116]

AP46

VSS[117]

AP8

VSS[118]

AR2

VSS[119]

AR48

VSS[120]

AT11

VSS[121]

AT13

VSS[122]

AT18

VSS[123]

AT22

VSS[124]

AT26

VSS[125]

AT28

VSS[126]

AT30

VSS[127]

AT32

VSS[128]

AT34

VSS[129]

AT39

VSS[130]

AT42

VSS[131]

AT46

VSS[132]

AT7

VSS[133]

AU24

VSS[134]

AU30

VSS[135]

AV16

VSS[136]

AV20

VSS[137]

AV24

VSS[138]

AV30

VSS[139]

AV38

VSS[140]

AV4

VSS[141]

AV43

VSS[142]

AV8

VSS[143]

AW14

VSS[144]

AW18

VSS[145]

AW2

VSS[146]

AW22

VSS[147]

AW26

VSS[148]

AW28

VSS[149]

AW32

VSS[150]

AW34

VSS[151]

AW36

VSS[152]

AW40

VSS[153]

AW48

VSS[154]

AV11

VSS[155]

AY12

VSS[156]

AY22

VSS[157]

AY28

VSS[158]

3

UH1I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

BD82PPSM-QNHN-A0_BGA989~D

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

2

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (8/8) VSS

PCH (8/8) VSS LA-7841P

LA-7841P

1

0.3

23 65Tuesday, February 07, 2012

0.3

5

PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_P4

D D

PT

5

QV2401

DIS@

2N7002H 1N_SOT23-3

PEG_HTX_C_GRX_P[0..15] PEG_HTX_C_GRX_N[0..15] PEG_GTX_C_HRX_P[0..15] PEG_GTX_C_HRX_N[0..15]

12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

CLK_PEG_VGA<17>

CLK_PEG_VGA#<17>

PLTRST_VGA#<19>

+3V_GPU

2

G

1 3

D

S

D

S

@

1 2

RV2401 0_0402_5%~D

PEG_HTX_C_GRX_P[0..15]<7> PEG_HTX_C_GRX_N[0..15]<7> PEG_GTX_C_HRX_P[0..15]<7> PEG_GTX_C_HRX_N[0..15]<7>

PEG_GTX_C_HRX_P0

C C

PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_N12

B B

PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_N15

A A

PEG_A_CLKRQ#<17>

CV2402 0.22U_0402_16V7K~DDIS@CV2402 0.22U_0402_16V7K~DDIS@ CV2403 0.22U_0402_16V7K~DDIS@CV2403 0.22U_0402_16V7K~DDIS@ CV2404 0.22U_0402_16V7K~DDIS@CV2404 0.22U_0402_16V7K~DDIS@ CV2405 0.22U_0402_16V7K~DDIS@CV2405 0.22U_0402_16V7K~DDIS@ CV2406 0.22U_0402_16V7K~DDIS@CV2406 0.22U_0402_16V7K~DDIS@ CV2407 0.22U_0402_16V7K~DDIS@CV2407 0.22U_0402_16V7K~DDIS@ CV2408 0.22U_0402_16V7K~DDIS@CV2408 0.22U_0402_16V7K~DDIS@ CV2401 0.22U_0402_16V7K~DDIS@CV2401 0.22U_0402_16V7K~DDIS@ CV2409 0.22U_0402_16V7K~DDIS@CV2409 0.22U_0402_16V7K~DDIS@ CV2410 0.22U_0402_16V7K~DDIS@CV2410 0.22U_0402_16V7K~DDIS@ CV2411 0.22U_0402_16V7K~DDIS@CV2411 0.22U_0402_16V7K~DDIS@ CV2412 0.22U_0402_16V7K~DDIS@CV2412 0.22U_0402_16V7K~DDIS@ CV2413 0.22U_0402_16V7K~DDIS@CV2413 0.22U_0402_16V7K~DDIS@ CV2414 0.22U_0402_16V7K~DDIS@CV2414 0.22U_0402_16V7K~DDIS@ CV2415 0.22U_0402_16V7K~DDIS@CV2415 0.22U_0402_16V7K~DDIS@ CV2416 0.22U_0402_16V7K~DDIS@CV2416 0.22U_0402_16V7K~DDIS@ CV2417 0.22U_0402_16V7K~D@CV2417 0.22U_0402_16V7K~D@ CV2418 0.22U_0402_16V7K~D@CV2418 0.22U_0402_16V7K~D@ CV2419 0.22U_0402_16V7K~D@CV2419 0.22U_0402_16V7K~D@ CV2420 0.22U_0402_16V7K~D@CV2420 0.22U_0402_16V7K~D@ CV2421 0.22U_0402_16V7K~D@CV2421 0.22U_0402_16V7K~D@ CV2422 0.22U_0402_16V7K~D@CV2422 0.22U_0402_16V7K~D@ CV2423 0.22U_0402_16V7K~D@CV2423 0.22U_0402_16V7K~D@ CV2424 0.22U_0402_16V7K~D@CV2424 0.22U_0402_16V7K~D@ CV2425 0.22U_0402_16V7K~D@CV2425 0.22U_0402_16V7K~D@ CV2426 0.22U_0402_16V7K~D@CV2426 0.22U_0402_16V7K~D@ CV2427 0.22U_0402_16V7K~D@CV2427 0.22U_0402_16V7K~D@ CV2428 0.22U_0402_16V7K~D@CV2428 0.22U_0402_16V7K~D@ CV2429 0.22U_0402_16V7K~D@CV2429 0.22U_0402_16V7K~D@ CV2430 0.22U_0402_16V7K~D@CV2430 0.22U_0402_16V7K~D@ CV2431 0.22U_0402_16V7K~D@CV2431 0.22U_0402_16V7K~D@ CV2432 0.22U_0402_16V7K~D@CV2432 0.22U_0402_16V7K~D@

PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_N15

PEG_GTX_HRX_P0 PEG_GTX_HRX_N0 PEG_GTX_HRX_P1 PEG_GTX_HRX_N1 PEG_GTX_HRX_P2 PEG_GTX_HRX_N2 PEG_GTX_HRX_P3 PEG_GTX_HRX_N3 PEG_GTX_HRX_P4 PEG_GTX_HRX_N4 PEG_GTX_HRX_P5 PEG_GTX_HRX_N5 PEG_GTX_HRX_P6 PEG_GTX_HRX_N6 PEG_GTX_HRX_P7 PEG_GTX_HRX_N7 PEG_GTX_HRX_P8 PEG_GTX_HRX_N8 PEG_GTX_HRX_P9 PEG_GTX_HRX_N9 PEG_GTX_HRX_P10 PEG_GTX_HRX_N10 PEG_GTX_HRX_P11 PEG_GTX_HRX_N11 PEG_GTX_HRX_P12 PEG_GTX_HRX_N12 PEG_GTX_HRX_P13 PEG_GTX_HRX_N13 PEG_GTX_HRX_P14 PEG_GTX_HRX_N14 PEG_GTX_HRX_P15 PEG_GTX_HRX_N15

RV2425 200_0402_5%~DDIS@RV2425 200_0402_5%~DDIS@ RV2426 2.49K_0402_1%~DDIS@RV2426 2.49K_0402_1%~DDIS@ RV2427 0_0402_5%~DDIS@RV2427 0_0402_5%~DDIS@

CLKRQ_GPU#

+3V_GPU

DIS@

RV2433

RV2433 10K_0402_5%~D

10K_0402_5%~D

1 2

CLKRQ_GPU#

RV2434

@RV2434

@

10K_0402_5%~D

1 2

4

UV1A

AG6

PEX_RX0

AG7

PEX_RX0_N

AF7

PEX_RX1

AE7

PEX_RX1_N

AE9

PEX_RX2

AF9

PEX_RX2_N

AG9

PEX_RX3

AG10

PEX_RX3_N

AF10

PEX_RX4

AE10

PEX_RX4_N

AE12

PEX_RX5

AF12

PEX_RX5_N

AG12

PEX_RX6

AG13

PEX_RX6_N

AF13

PEX_RX7

AE13

PEX_RX7_N

AE15

PEX_RX8

AF15

PEX_RX8_N

AG15

PEX_RX9

AG16

PEX_RX9_N

AF16

PEX_RX10

AE16

PEX_RX10_N

AE18

PEX_RX11

AF18

PEX_RX11_N

AG18

PEX_RX12

AG19

PEX_RX12_N

AF19

PEX_RX13

AE19

PEX_RX13_N

AE21

PEX_RX14

AF21

PEX_RX14_N

AG21

PEX_RX15

AG22

PEX_RX15_N

AC9

PEX_TX0

AB9

PEX_TX0_N

AB10

PEX_TX1

AC10

PEX_TX1_N

AD11

PEX_TX2

AC11

PEX_TX2_N

AC12

PEX_TX3

AB12

PEX_TX3_N

AB13

PEX_TX4

AC13

PEX_TX4_N

AD14

PEX_TX5

AC14

PEX_TX5_N

AC15

PEX_TX6

AB15

PEX_TX6_N

AB16

PEX_TX7

AC16

PEX_TX7_N

AD17

PEX_TX8

AC17

PEX_TX8_N

AC18

PEX_TX9

AB18

PEX_TX9_N

AB19

PEX_TX10

AC19

PEX_TX10_N

AD20

PEX_TX11

AC20

PEX_TX11_N

AC21

PEX_TX12

AB21

PEX_TX12_N

AD23

PEX_TX13

AE23

PEX_TX13_N

AF24

PEX_TX14

AE24

PEX_TX14_N

AG24

PEX_TX15

AG25

PEX_TX15_N

AE8

PEX_REFCLK

AD8

PEX_REFCLK_N

AF22

PEX_TSTCLK_OUT

AE22 12 12

AF25

AC7 AC6

N13P-GV-S_FCBGA595~D

DIS@

4

PEX_TSTCLK_OUT_N PEX_TERMP PEX_RST_N PEX_CLKREQ_N

Part 1 of 5

C6

GPIO0

B2

GPIO1

D6

GPIO2

C7

GPIO3

F9

GPIO4

A3

GPIO5

A4

GPIO6

B6

GPIO7

A6

GPIO8

F8

GPIO9

C5

GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

JTAG_TDI

I2CA_SCL I2CA_SDA

I2CB_SCL I2CB_SDA

I2CC_SCL I2CC_SDA

I2CS_SCL I2CS_SDA

XTAL_IN

PGOOD

CEC

E7 D7 B4 B3 C3 D5 D4 C2 F7 E6 C4

AE3 AE4

AG3 AF3 AF4

AE2 AF2

AE5 AE6 AF6 AD6 AG4

AD9

B7 A7

C9 C8

A9 B9

D9 D8

A10 C10 B10 C11

AB6 D10 E9

GPIO

DACA_HSYNC

DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_VREF DACA_RSET

JTAG_TCK

JTAG_TDO JTAG_TMS

JTAG_TRST_N

PCI EXPRESS

TEST

TESTMODE

I2C DACA

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

CLK

PEX_WAKE_N

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

GPU_VID_4 GPU_VID_3

1 2

RV3526 0_0402_5%~D@RV3526 0_0402_5%~D@

GPU_VID_1 GPU_VID_2

1 2

RV2402 10K_0402_5%~DDIS@RV2402 10K_0402_5%~DDIS@

THM_ALERT# GPU_VID_0

GPU_GPIO12 GPU_VID_5

1 2

RV2405 100K_0402_5%~DDIS@RV2405 100K_0402_5%~DDIS@

1 2

RV2406 100K_0402_5%~DDIS@RV2406 100K_0402_5%~DDIS@

1 2

RV2407 100K_0402_5%~DDIS@RV2407 100K_0402_5%~DDIS@

1 2

RV2408 100K_0402_5%~DDIS@RV2408 100K_0402_5%~DDIS@

1 2

RV2409 100K_0402_5%~DDIS@RV2409 100K_0402_5%~DDIS@

GPU_JTAG_TCK GPU_JTAG_TDI GPU_JTAG_TDO GPU_JTAG_TMS

1 2

RV2419 10K_0402_5%~DDIS@RV2419 10K_0402_5%~DDIS@

GPU_TESTMODE

I2CA_SCL I2CA_SDA

I2CB_SCL I2CB_SDA

I2CC_SCL I2CC_SDA

EC_SMB_CK2_PX EC_SMB_DA2_PX

1 2

RV2423 10K_0402_5%~DDIS@RV2423 10K_0402_5%~DDIS@

1 2

RV2424 10K_0402_5%~DDIS@RV2424 10K_0402_5%~DDIS@

XTAL_OUT EC_SMB_DA2_PX XTALIN

1 2

RV2428 10K_0402_5%~DDIS@RV2428 10K_0402_5%~DDIS@

1 2

RV2429 10K_0402_5%~DDIS@RV2429 10K_0402_5%~DDIS@

2011/07/15 2012/07/15

3

+3V_GPU

FBVREF_ALTV <29,30>

TV2401@ TV2401@ TV2402@ TV2402@ TV2403@ TV2403@ TV2404@ TV2404@

I2C Slave Address 0X9E

+3V_GPU

Compal Secret Data

H_DPRSLPVRGPU_GPIO3

GPU_TESTMODE

10P_0402_50V8J~D

Deciphered Date

P

T PT

DIS@

CV2433

2

H_DPRSLPVR <61>

SSI2

GPU_GPIO12

+3V_GPU

12

RV2412

@RV2412

@

10K_0402_5%~D

12

DIS@

RV2422

RV2422 10K_0402_5%~D

10K_0402_5%~D

EC_SMB_CK2_PX

RV2431 10M_0402_5%@RV2431 10M_0402_5%@

XTALIN XTAL_OUT

1

27MHZ_12PF_X3G027000FC1H-H~D

2

SSI2

2

DV6 RB751V-40_SOD323-2DIS@ DV6 RB751V-40_SOD323-2DIS@

DIS@

DMN66D0LDW-7_SOT363-6~D

1 2

DIS@

YV2401

1

IN

OUT

2

GND

Title

Size Document Number Rev

Custom

Date: Sheet of

GPU_VID_0 GPU_VID_1 GPU_VID_2 GPU_VID_3 GPU_VID_4 GPU_VID_5

2 1

SSI2SSI2

GPU_GPIO3 GPU_GPIO12 THM_ALERT# I2CA_SCL I2CA_SDA I2CB_SCL I2CB_SDA I2CC_SCL I2CC_SDA EC_SMB_CK2_PX

ST

EC_SMB_DA2_PX

+3V_GPU

2

61

QV2402A

DMN66D0LDW-7_SOT363-6~D

3 4

LA-7841P

1

GPU_VID_0 <61> GPU_VID_1 <61> GPU_VID_2 <61> GPU_VID_3 <61> GPU_VID_4 <61> GPU_VID_5 <61>

GPU_HOT# <38>

+3V_GPU

1 2

DIS@

1 2

RV3527 10K_0402_5%~D

DIS@

12

DIS@

RV2432 10K_0402_5%~D

RV2432 10K_0402_5%~D RV2442 2.2K_0402_5%~D

RV2442 2.2K_0402_5%~D RV2413 2.2K_0402_5%~D

RV2413 2.2K_0402_5%~D RV2414 2.2K_0402_5%~D

RV2414 2.2K_0402_5%~D RV2415 2.2K_0402_5%~D

RV2415 2.2K_0402_5%~D RV2416 2.2K_0402_5%~D

RV2416 2.2K_0402_5%~D RV2417 2.2K_0402_5%~D

RV2417 2.2K_0402_5%~D RV2418 2.2K_0402_5%~D

RV2418 2.2K_0402_5%~D RV2420 2.2K_0402_5%~D

RV2420 2.2K_0402_5%~D RV2421 2.2K_0402_5%~D

RV2421 2.2K_0402_5%~D

DIS@

DIS@ DIS@

DIS@

12 12 12 12 12 12 12 12

ST

5

4

DIS@

Compal Electronics, Inc.

N13P(1/5)_PCIE/GPIO/I2C/DAC

3

QV2402B

1

DIS@

CV2434

CV2434 10P_0402_50V8J~D

10P_0402_50V8J~D

2

PCH_SMLCLK <17,35,38>

ST

PCH_SMLDATA <17,35,38>

1

24 65Tuesday, February 07, 2012

0.3

5

UV1C

AC3

IFPA_TXC

AC4

IFPA_TXC_N

Y4

IFPA_TXD0

Y3

IFPA_TXD0_N

AA3

IFPA_TXD1

AA2

IFPA_TXD1_N

AB1

IFPA_TXD2

AA1

IFPA_TXD2_N

AA4

IFPA_TXD3

AA5

RV2507

10K_0402_1%~D

1 2

@ RV2507

@

RV2515

1 2

34.8K_0402_1%~D

DIS@ RV2515

DIS@

PT

IFPA_TXD3_N

AB5

IFPB_TXC

AB4

IFPB_TXC_N

AB3

IFPB_TXD4

AB2

IFPB_TXD4_N

AD3

IFPB_TXD5

AD2

IFPB_TXD5_N

AE1

IFPB_TXD6

AD1

IFPB_TXD6_N

AD4

IFPB_TXD7

AD5

IFPB_TXD7_N

N4

IFPC_AUX_I2CW_SCL

N5

IFPC_AUX_I2CW_SDA_N

T2

IFPC_L0

T3

IFPC_L0_N

T1

IFPC_L1

R1

IFPC_L1_N

R2

IFPC_L2

R3

IFPC_L2_N

N2

IFPC_L3

N3

IFPC_L3_N

P3

IFPD_AUX_I2CX_SCL

P4

IFPD_AUX_I2CX_SDA_N

V3

IFPD_L0

V4

IFPD_L0_N

U3

IFPD_L1

U4

IFPD_L1_N

T4

IFPD_L2

T5

IFPD_L2_N

R4

IFPD_L3

R5

IFPD_L3_N

J2

IFPE_AUX_I2CY_SCL

J3

IFPE_AUX_I2CY_SDA_N

N1

IFPE_L0

M1

IFPE_L0_N

M2

IFPE_L1

M3

IFPE_L1_N

K2

IFPE_L2

K3

IFPE_L2_N

K1

IFPE_L3

J1

IFPE_L3_N

H3

IFPF_AUX_I2CZ_SCL

H4

IFPF_AUX_I2CZ_SDA_N

M4

IFPF_L0

M5

IFPF_L0_N

L3

IFPF_L1

L4

IFPF_L1_N

K4

IFPF_L2

K5

IFPF_L2_N

J4

IFPF_L3

J5

IFPF_L3_N

N13P-GV-S_FCBGA595~D

DIS@

RV2508

1 2

@

34.8K_0402_1%~D

4.99K_0402_1%~D

RV2516

10K_0402_1%~D

1 2

DIS@ RV2516

DIS@

D D

C C

B B

A A

+3V_GPU

RV2504

10K_0402_1%~D

@ RV2504

@

RV2512

10K_0402_1%~D

10K_0402_1%~D@1 2

@ RV2512

RV2506

RV2505

1 2

@

4.99K_0402_1%~D

DIS@ RV2506

DIS@

RV2513

RV2514

10K_0402_1%~D

1 2

@ RV2514

@

DIS@ RV2513

DIS@

Part 3 of 5

LVDS / TMDS

RV2511

RV2509

10K_0402_1%~D

1 2

@ RV2509

@

RV2517

10K_0402_1%~D

1 2

DIS@ RV2517

DIS@

RV2511

RV2510

1 2

@

4.99K_0402_1%~D

RV2518

RV2501

1 2

10K_0402_1%~D

1 2

DIS@ RV2518

DIS@

DIS@ RV2501

DIS@

1 2

34.8K_0402_1%~D

10K_0402_1%~D

1 2

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 STRAP5

BUFRST_N

THERMDN THERMDP

GENERAL STRAPSERIAL

ROM_CS_N

ROM_SCLK

ROM_SI

ROM_SO

IFPAB_RSET

IFPC_RSET IFPD_RSET

IFPEF_RSET

NC NC NC

NC_G1 NC_G2 NC_G3 NC_G4 NC_G5 NC_G6 NC_G7

NC_V1 NC_V2 NC_V5 NC_V6

NC_W1 NC_W2 NC_W3 NC_W4

VMON_IN0 VMON_IN1

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 ROM_SCLK_GPU ROM_SI_GPU ROM_SO_GPU

4

D1

STRAP0

D2

STRAP1

E4

STRAP2

E3

STRAP3

D3

STRAP4

C1

D11

BUFRST

E12 F12

D12

ROM_CS#

RV2503 10K_0402_5%~D

C12

ROM_SCLK_GPU

B12

ROM_SI_GPU

A12

ROM_SO_GPU

AA6 T6 U6 K6

AD10 AD7 B19

G1 G2 G3 G4 G5 G6 G7

V1 V2 V5 V6

W1 W2 W3 W4

E10 F10

VRAM Setting

PT

12

DIS@

RV2502 10K_0402_1%~D

+3V_GPU

STRAP[3:0]

1 2

Vendor

@

1

2

BUFRST

CV2502

@CV2502

@

68P_0402_50V8J~D

Samsung 128MX16 (SA000048E0L) Hynix 128MX16 (SA00004GD0L)

SAMSUNG HYNIX

RV2512

RV2504

10K_0402_1%~D

X76_SAM@

RV2512

10K_0402_1%~D

X76_HYN@

0 1 0 1 0 1 0 0

3

GPU BIOS Device ID

N13P-GV-S-A2 0x1140

PT

Binary Mode Straps

STRAP Pin Name STRAP Mapping Resistance

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 ROM_SCLK ROM_SI ROM_SO VGA_DEVICE

RAM_CFG[0] RAM_CFG[1] RAM_CFG[2] RAM_CFG[3] PCIE_MAX_SPEED SMB_ALT_ADDR SUB_VENDOR

10K Ohm 10K Ohm 10K Ohm 10K Ohm 10K Ohm 10K Ohm 10K Ohm 10K Ohm

2

Polarity

For Hynix Pull-down 10K ohm to GND, Samsung pull-high 10K ohm to 3.3V

Pull-down 10K ohm to GND Pull-up 10K ohm to +3V_GPU Pull-down 10K ohm to GND Pull-down 10K ohm to GND Pull-down 10K ohm to GND Pull-down 10K ohm to GND Pull-down 10K ohm to GND

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N13P(2/5)_LVDS/HDMI/DP/STRP

LA-7841P

1

25 65Tuesday, February 07, 2012

0.3

5

(

42A)

+GPU_CORE

D D

C C

RV2601

1 2

DIS@

GPU_VDD_SENSE<61>

B B

RV2603 10K_0402_5%~DDIS@RV2603 10K_0402_5%~DDIS@ RV2604 10K_0402_5%~DDIS@RV2604 10K_0402_5%~DDIS@ RV2605 10K_0402_5%~DDIS@RV2605 10K_0402_5%~DDIS@ RV2606 10K_0402_5%~DDIS@RV2606 10K_0402_5%~DDIS@ RV2608 10K_0402_5%~DDIS@RV2608 10K_0402_5%~DDIS@ RV2607 10K_0402_5%~DDIS@RV2607 10K_0402_5%~DDIS@

RV2609 10K_0402_5%~DDIS@RV2609 10K_0402_5%~DDIS@ RV2610 10K_0402_5%~DDIS@RV2610 10K_0402_5%~DDIS@

RV2612 10K_0402_5%~DDIS@RV2612 10K_0402_5%~DDIS@ RV2613 10K_0402_5%~DDIS@RV2613 10K_0402_5%~DDIS@

RV2615 10K_0402_5%~DDIS@RV2615 10K_0402_5%~DDIS@ RV2616 10K_0402_5%~DDIS@RV2616 10K_0402_5%~DDIS@

RV2618 10K_0402_5%~DDIS@RV2618 10K_0402_5%~DDIS@ RV2620 10K_0402_5%~DDIS@RV2620 10K_0402_5%~DDIS@

DIS@

0_0402_5%~D

+3.3V_RUN_VDD33

+3.3V_PEX_VDD +3.3V_PEX_VDD

12 12 12 12 12 12

12 12

K10 K12 K14 K16 K18 L11 L13 L15

L17 M10 M12 M14 M16 M18

N11

N13

N15

N17

P10

P12

P14

P16

P18

R11

R13

R15

R17

T10

T12

T14

T16

T18

U11

U13

U15

U17

V10

V12

V14

V16

V18

G10 G12

F11

AB8

UV1D

F2

G8 G9

W6

Y6 P6 R6 H6

J6

V7

W7

M7 N7

R7 T7

J7

K7

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

(3300mA)

VDD VDD

VDD_SENSE VDD33

VDD33 VDD33 VDD33

3V3AUX

PEX_SVDD_3V3 IFPA_IOVDD

IFPB_IOVDD IFPC_IOVDD IFPD_IOVDD IFPE_IOVDD IFPF_IOVDD

IFPAB_PLLVDD IFPAB_PLLVDD

IFPC_PLLVDD IFPC_PLLVDD

IFPD_PLLVDD IFPD_PLLVDD

IFPEF_PLLVDD IFPEF_PLLVDD

Part 4 of 5

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

POWER

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_PLL_HVDD PEX_PLL_HVDD

PEX_PLLVDD

(150mA)

PEX_PLLVDD

VID_PLLVDD

CORE_PLLVDD

FB_PLLAVDD FB_PLLAVDD

FB_DLLAVDD

FB_CAL_PD_VDDQ

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

SP_PLLVDD

DACA_VDD

FB_CLAMP

FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ

4

B26 C25 E23 E26 F14 F21 G13 G14 G15 G16 G18 G19 G20 G21 H24 H26 J21 K21 L22 L24 L26 M21 N21 R21 T21 V21 W21

AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27

AA22 AB23 AC24 AD25 AE26 AE27

AA8 AA9

AA14 AA15 N6 M6 L6 F16 P22 H22

W5 D22 F3

1

@

2

1

2

DIS@

22U_0805_6.3V6M~D

Mid-way between GPU and power supply

+CORE_PLLVDD

1 2

DIS@

RV2614 10K_0402_5%~D

1 2

DIS@

RV2617 40.2_0402_1%~D

1 2

DIS@

RV2619 10K_0402_5%~D

1U_0402_6.3V6K~D

1

CV2625

@

2

1

2

CV2658

CV2657

DIS@

22U_0805_6.3V6M~D

1

2

CV2654

DIS@

22U_0805_6.3V6M~D

+PEX_PLLVDD +SP_PLLVDD

+FB_PLL_AVDD

3

Place Under GPU

1U_0402_6.3V6K~D

1

CV2623

@

2

CV2620

CV2622

DIS@

DIS@ 2

1U_0402_6.3V6K~D

1

DIS@

2

CV2624

CV2615

DIS@

2

DIS@

Place Near GPU

10U_0603_6.3V6M~D

CV2607

CV2613

1

@

2

22U_0805_6.3V6M~D

1

2

CV2653

DIS@

1

@

2

CV2655

CV2656

DIS@

22U_0805_6.3V6M~D

1

2

CV2642

CV2641

DIS@

10U_0603_6.3V6M~D

22U_0805_6.3V6M~D

+PEX_PLLVDD

1

2

CV2671

DIS@

1U_0402_6.3V6K~D

4.7U_0603_6.3VAK~D

CV2607

CV2606

1

@

2

DIS@

1

2

CV2643

CV2652

DIS@

CV2652

DIS@

10U_0603_6.3V6M~D

1

2

CV2672

Place near GPU Place under GPU

+FB_PLL_AVDD

1

2

CV2666

CV2667

DIS@

1U_0402_6.3V6K~D

22U_0805_6.3V6M~D

+1.5V_GPU

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D CV2608

CV2608

1

2

DIS@

10U_0603_6.3V6M~D

CV2610

1

@

2

1

2

CV2647

DIS@

10U_0603_6.3V6M~D

Place under GPUPlace near GPU

1

2

DIS@

0.1U_0402_16V7K~D

One per Pin

1

2

CV2673

DIS@

0.1U_0402_10V7K~D

2

+1.5V_GPU

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D CV2609

CV2609

4.7U_0603_6.3VAK~D

1

2

DIS@

1

2

DIS@

10U_0603_6.3V6M~D

CV2669

1

2

DIS@

0.1U_0402_10V7K~D

0.1U_0402_16V7K~D

CV2616

CV2618

1

2

DIS@

CV2621

CV2644

CV2670

CV2618

1

@

2

4.7U_0603_6.3VAK~D

CV2626

1

@

2

DIS@

1

2

CV2645

DIS@

4.7U_0603_6.3VAK~D

RV2621

DIS@

1 2

0_0402_5%~D

1

2

CV2668

DIS@

0.1U_0402_10V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D CV2617

CV2617

CV2619

1

@

2

4.7U_0603_6.3VAK~D

4.7U_0603_6.3VAK~D CV2628

CV2628

CV2627

1

@

2

Place Under GPUPlace near GPU

1

2

CV2646

DIS@

4.7U_0603_6.3VAK~D

1U_0402_6.3V6K~D

+1.05V_GPU

DIS@

(66mA)

+1.05V_GPU

LV2602

DIS@

12

MMZ1608D301BT_0603

Place Under GPU Per PinPlace Near GPU

+3.3V_RUN_VDD33

1

2

DIS@

4.7U_0603_6.3VAK~D

CV2629

CV2630

1

@

2

+1.05V_GPU

DIS@

4.7U_0603_6.3VAK~D

CV2660

1

2

DIS@

1U_0402_6.3V6K~D

Place Near GPU

1

2

1

CV2648

2

DIS@

1U_0402_6.3V6K~D

1

CV2650

CV2649

CV2651

2

DIS@

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

1

CV2674

2

DIS@

CV2661

4.7U_0603_6.3VAK~D

1

2

DIS@

1

CV2662

2

DIS@

0.1U_0402_16V7K~D

+3.3V_PEX_VDD

CV2675

4.7U_0603_6.3VAK~D

1

2

DIS@

0.1U_0402_16V7K~D

CV2676

1

CV2663

2

DIS@

(210mA)

0_0603_5%~D

RV2611

DIS@

Place near GUP Place under GPU

+SP_PLLVDD

1

2

CV2677

DIS@

22U_0805_6.3V6M~D

4.7U_0603_6.3VAK~D

Place near GPU

1

2

CV2681

DIS@

22U_0805_6.3V6M~D

2

CV2678

DIS@

1

2

CV2680

DIS@

0.1U_0402_10V7K~D

Place under GPU

+CORE_PLLVDD

1

2

CV2682

DIS@

0.1U_0402_10V7K~D

1

CV2664

2

DIS@

0.1U_0402_16V7K~D

+3V_GPU

12

LV2603

DIS@

BLM18PG181SN1_0603~D

1

2

CV2601

DIS@

BLM18PG300SN1D_2P~D

1

DIS@

LV2604

1

2

DIS@

0.1U_0402_16V7K~D

RV2602

1 2

DIS@

0_0603_5%~D

CV2665

+1.05V_GPU

12

+1.05V_GPU

12

+3V_GPU

A A

N13P-GV-S_FCBGA595~D

DIS@

5

4

Security Classification

2011/07/15 2012/07/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/15 2012/07/15

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

N13P(3/5)_POWER

LA-7841P

1

26 65Tuesday, February 07, 2012

0.3

5

UV1E

AA7

GND

A2

D D

C C

B B

GND

A26

GND

AB11

GND

AB14

GND

AB17

GND

AB20

GND

AB24

GND

AC2

GND

AC22

GND

AC26

GND

AC5

GND

AC8

GND

AD12

GND

AD13

GND

AD15

GND

AD16

GND

AD18

GND

AD19

GND

AD21

GND

AD22

GND

AE11

GND

AE14

GND

AE17

GND

AE20

GND

AF1

GND

AF11

GND

AF14

GND

AF17

GND

AF20

GND

AF23

GND

AF5

GND

AF8

GND

AG2

GND

AG26

GND

B1

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B27

GND

B5

GND

B8

GND

E11

GND

E14

GND

E17

GND

E2

GND

E20

GND

E22

GND

E25

GND

E5

GND

E8

GND

H2

GND

H23

GND

H25

GND

H5

GND

K11

GND

K13

GND

K15

GND

K17

GND

N13P-GV-S_FCBGA595~D

DIS@

Part 5 of 5

MULTI_STRAP_REF0_GND MULTI_STRAP_REF1_GND MULTI_STRAP_REF2_GND

4

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND

FB_CAL_PU_GND

FB_CAL_TERM_GND

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND_SENSE

L10 L12 L14 L16 L18 L2 L23 L25 L5 M11 M13 M15 M17 N10 N12 N14 N16 N18 P11 P13 P15 P17 P2 P23 P26 P5 R10 R12 R14 R16 R18 T11 T13 T15 T17 U10 U12 U14 U16 U18 U2 U23 U26 U5 V11 V13 V15 V17 Y2 Y23 Y26 Y5 AB7

C24

RV2701 40.2_0402_1%~DDIS@RV2701 40.2_0402_1%~DDIS@

B25

RV2702 60.4_0402_1%~DDIS@RV2702 60.4_0402_1%~DDIS@

F6

RV2703 40.2K_0402_1%~D@RV2703 40.2K_0402_1%~D@

F4

RV2704 40.2K_0402_1%~D@RV2704 40.2K_0402_1%~D@

F5

RV2705 40.2K_0402_1%~D@RV2705 40.2K_0402_1%~D@

F1

RV2706 0_0402_5%~DDIS@RV2706 0_0402_5%~DDIS@

1 2 1 2 1 2

1 2 1 2

1 2

PT

3

2

1

GPU_VSS_SENSE <61>

A A

Security Classification

2011/07/15 2012/07/15

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/15 2012/07/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N13P(4/5)_GND

LA-7841P

0.3

27 65Tuesday, February 07, 2012

1

5

UV1B

Part 2 of 5

FBA_D[0..31]<29>

D D

FBA_D[32..63]<30>

C C

+1.5V_GPU

1.1K_0402_1%~D

@RV2807

@

12

RV2807

16mil

+FB_VREF

1.1K_0402_1%~D

@RV2808

1.1K_0402_1%~D

@

0.01U_0402_25V7K~D

12

RV2808

@CV2805

@

1

CV2805

2

TV2406 @TV2406 @

CLKA0<29>

CLKA0#<29>

CLKA1<30>

B B

CLKA1#<30>

+FB_VREF

CLKA0

CLKA0#

CLKA1

CLKA1#

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

AA24 AA23

AD27 AB25 AD26 AC25 AA27 AA26

W26

W27 W25

D20 D21

D15

C13

D13 C16

C19 C23

C20 C21 R22 R24

R23 N25 N26 N23 N24

U22

R26 N27

R27

D23 D24

D25 N22

M22

E18 F18 E16 F17

F20 E21 E15

F15 F13

B13 E13

B15 A13

A15 B18 A18 A19

B24 A25

A24 A21 B21

T22

V23 V22 T23

Y24 Y22

Y25 T25

V26 V27

Part 2 of 5

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FB_VREF_PROBE FBA_CLK0

FBA_CLK0_N FBA_CLK1

FBA_CLK1_N

N13P-GV-S_FCBGA595~D

MEMORY INTERFACE

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_DEBUG0 FBA_DEBUG1

4

C27

FBA_CMD0

C26

FBA_CMD1

E24

FBA_CMD2

F24

FBA_CMD3

D27

FBA_CMD4

D26

FBA_CMD5

F25

FBA_CMD6

F26

FBA_CMD7

F23

FBA_CMD8

G22

FBA_CMD9

G23

FBA_CMD10

G24

FBA_CMD11

F27

FBA_CMD12

G25

FBA_CMD13

G27

FBA_CMD14

G26

FBA_CMD15

M24

FBA_CMD16

M23

FBA_CMD17

K24

FBA_CMD18

K23

FBA_CMD19

M27

FBA_CMD20

M26

FBA_CMD21

M25

FBA_CMD22

K26

FBA_CMD23

K22

FBA_CMD24

J23

FBA_CMD25

J25

FBA_CMD26

J24

FBA_CMD27

K27

FBA_CMD28

K25

FBA_CMD29

J27

FBA_CMD30

J26

FBA_CMD31

D19

FBA_DBI0

D14

FBA_DBI1

C17

FBA_DBI2

C22

FBA_DBI3

P24

FBA_DBI4

W24

FBA_DBI5

AA25

FBA_DBI6

U25

FBA_DBI7

F19 C14 A16 A22 P25 W22 AB27 T27

E19

FBA_EDC0

C15

FBA_EDC1

B16

FBA_EDC2

B22

FBA_EDC3

R25

FBA_EDC4

W23

FBA_EDC5

AB26

FBA_EDC6

T26

FBA_EDC7

D18 C18 D17 D16 T24 U24 V24 V25

F22 J22

1 2

RV2801 60.4_0402_1%~DRV2801 60.4_0402_1%~D

1 2

RV2812 60.4_0402_1%~DRV2812 60.4_0402_1%~D

FBA_WCK01 <29> FBA_WCK01# <29> FBA_WCK23 <29> FBA_WCK23# <29> FBA_WCK45 <30> FBA_WCK45# <30> FBA_WCK67 <30> FBA_WCK67# <30>

FBA_CMD[0..31] <29,30>

FBA_DBI[3..0] <29>

FBA_DBI[7..4] <30>

FBA_EDC[3..0] <29>

FBA_EDC[7..4] <30>

+1.5V_GPU

3

2

1

Mode H - Command Mapping

0..31 CS* A3_BA3 A2_BA0 A4_BA2

A5_BA1 WE* A7_A8 A6_A11 ABI*

A12_RFU

A0_A10 A1_A9 RAS* RST* CKE* CAS#CMD15

DATA Bus

32..63

CS* A3_BA3 A2_BA0 A4_BA2 A5_BA1 WE* A7_A8 A6_A11 ABI* A12_RFU A0_A10 A1_A9 RAS* RST* CKE*CMD30 CAS*

Address

CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14

CMD16 CMD17 CMD18 CMD19 CMD20 CMD21 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29

CMD31

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N13P(5/5)_MEMORY INTERFACE

LA-7841P

1

28 65Tuesday, February 07, 2012

0.3

5

Memory Partition A - Lower 32

UV5

bits

FBA_EDC0 FBA_EDC2

D D

CLKA0<28>

RV2907 1K_0402_1%~DDIS@RV2907 1K_0402_1%~DDIS@ RV2908 1K_0402_1%~DDIS@RV2908 1K_0402_1%~DDIS@ RV2909 121_0402_1%~DDIS@RV2909 121_0402_1%~DDIS@

1

CV2927

2

DIS@

820P_0402_50V7K~D

10U_0603_6.3V6M~D

CV2918

1

2

DIS@

CLKA0#<28>

1 2 1 2 1 2

FBA_WCK01#<28> FBA_WCK01<28>

FBA_WCK23#<28> FBA_WCK23<28>

+FBA_VREFC_L

1U_0402_6.3V6K~D

1

CV2919

2

DIS@

1U_0402_6.3V6K~D

PT

CLKA0

RV2902

80.6_0402_1%~D

DIS@

1 2

CLKA0#

0.01U_0402_16V7K~D

1

CV2901

@

2

C C

One Per pin

+FBA_VREFD_L

1

CV2928

2

DIS@

820P_0402_50V7K~D

PLACE 0.1uF CAPS CLOSEST TO THE

B B

MEMORY DEVICES PLACE LARGER CAPACITORS SLIGHTLY FARTHER AWAY

GDDR5 Mode H Mapping

Channel 0 0...31

GB2-64

CS#

CMD0

A3_BA3

CMD1

A2_BA0

CMD2

A4_BA2

CMD3

A5_BA1

CMD4

WE#

CMD5

A7_A8

CMD6

A6_A11

A A

CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15

ABI# A12_RFU A0_A10 A1_A9 RAS# RST# CKE# CAS#

5

FBA_DBI0 FBA_DBI2

CLKA0 CLKA0# FBA_CMD14

FBA_CMD9 FBA_CMD6

FBA_CMD7 FBA_CMD4 FBA_CMD3

FBA_CMD1 FBA_CMD2 FBA_CMD11 FBA_CMD10

FBA_SEN0

FBA_CMD8 FBA_CMD12 FBA_CMD0 FBA_CMD15 FBA_CMD5

FBA_WCK01# FBA_WCK01

FBA_WCK23# FBA_WCK23

1

FBA_CMD13

CV2910

2

DIS@

820P_0402_50V7K~D

+1.5V_GPU

1U_0402_6.3V6K~D

1

CV2921

CV2922

CV2920

CV2922

2

DIS@

UV5

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

170-BALL

SGRAM GDDR5

H5GQ2H24MFR-T2C_BGA170~D

@

4

NORMAL

4

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7

FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23

+1.5V_GPU

128X16 GDDR5

+1.5V_GPU

One Per pin

CV2929

RV2904 1K_0402_1%~DDIS@RV2904 1K_0402_1%~DDIS@ RV2905 1K_0402_1%~DDIS@RV2905 1K_0402_1%~DDIS@ RV2906 121_0402_1%~DDIS@RV2906 121_0402_1%~DDIS@

+FBA_VREFD_L

1

CV2909

2

DIS@

820P_0402_50V7K~D

1 2 1 2 1 2

820P_0402_50V7K~D

PT

SAMSUNG

UV5

PCB-MB

X76_SAM@

HYNIX

UV5

PCB-MB

X76_HYN@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

3

FBA_EDC3 FBA_EDC1

FBA_DBI3 FBA_DBI1

CLKA0 CLKA0#

FBA_CMD14 FBA_CMD9 FBA_CMD10

FBA_CMD11 FBA_CMD1 FBA_CMD2

FBA_CMD4 FBA_CMD3 FBA_CMD7 FBA_CMD6

FBA_SEN1

FBA_CMD8 FBA_CMD15 FBA_CMD5 FBA_CMD12 FBA_CMD0

FBA_WCK23# FBA_WCK23

FBA_WCK01# FBA_WCK01

+FBA_VREFC_L

1 2

DIS@

CV2904 820P_0402_50V7K~D

FBA_CMD13

+1.5V_GPU

UV4

PCB-MB

X76_SAM@

UV4

PCB-MB

X76_HYN@

3

UV4

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

170-BALL

SGRAM GDDR5

H5GQ2H24MFR-T2C_BGA170~D

@

IRROR

M

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31

FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15

+1.5V_GPU

1

FBA_CMD[0..31] FBA_D[0..31] FBA_DBI[0..3] FBA_EDC[0..3]

+1.5V_GPU

DIS@

PLACE 0.1uF CAPS CLOSEST TO THE MEMORY DEVICES PLACE LARGER CAPACITORS SLIGHTLY FARTHER AWAY

1U_0402_6.3V6K~D

1

CV2914

CV2915

2

DIS@

10U_0603_6.3V6M~D

CV2930

1

2

DIS@

+FBA_VREFD_L

FBVREF_ALTV<24,30>

1U_0402_6.3V6K~D

1

CV2913

CV2905

2

DIS@

12

DIS@

RV2913

13

D

2

G

DIS@

S

DIS@

1

2

DIS@

931_0402_1%

QV2901

12

0.1U_0402_10V7K~D

SSM3K7002FU_SC70-3~D

10K_0402_5%~D

CV2906

1 2

FBA_D[0..31] <28>

FBA_DBI[0..3] <28> FBA_EDC[0..3] <28>

RV2911

FBA_CMD14

FBA_CMD13

RV2901

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D CV2903

CV2903

1

2

DIS@

12

DIS@

RV2917

1.33K_0402_1%~D

DIS@

RV2912

1.33K_0402_1%~D

FBA_CMD[0..31] <28,30>

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D CV2907

CV2907

1

2

DIS@

549_0402_1%~D

+FBA_VREFC_L

DIS@

DELL CONFIDENTIAL/PROPRIETARY

123

Title

Size Document Number Rev

Date: Sheet of

123 VRAM A Lower

VRAM A Lower

VRAM A Lower LA-7841P

LA-7841P

1

29 65Tuesday, February 07, 2012

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D CV2908

CV2908

DIS@

RV2914

DIS@

RV2916

12

0.1U_0402_10V7K~D

1

2

DIS@

+1.5V_GPU

RV2915

0.1U_0402_10V7K~D

CV2911

1

2

DIS@

12

931_0402_1%

0.3

CV2912

5

Memory Partition A - Upper 32 bits

UV7

MF=0 MF=1 MF=0MF=1

FBA_SEN2

+1.5V_GPU

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

170-BALL

SGRAM GDDR5

H5GQ2H24MFR-T2C_BGA170~D

@

FBA_EDC7 FBA_EDC5

D D

CLKA1<28>

RV3007 1K_0402_1%~DDIS@RV3007 1K_0402_1%~DDIS@ RV3009 1K_0402_1%~DDIS@RV3009 1K_0402_1%~DDIS@ RV3010 121_0402_1%~DDIS@RV3010 121_0402_1%~DDIS@

+FBA_VREFD_H

1

CV3017

CV3018

2

DIS@

820P_0402_50V7K~D

CLKA1#<28>

1 2 1 2 1 2

FBA_WCK67#<28> FBA_WCK67<28>

FBA_WCK45#<28> FBA_WCK45<28>

1

2

820P_0402_50V7K~D

PT

CLKA1

RV3003

80.6_0402_1%~D

DIS@

1 2

CLKA1#

0.01U_0402_16V7K~D

1

CV3001

@

2

C C

GDDR5 Mode H Mapping

Channel 0 32...63

GB2-64

CS#

CMD16

A3_BA3

CMD17

B B

A A

CMD18 CMD19 CMD20 CMD21 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD31

A2_BA0 A4_BA2 A5_BA1 WE# A7_A8 A6_A11 ABI# A12_RFU A0_A10 A1_A9 RAS# RST# CKE# CAS#

PT

SAMSUNG

UV7

PCB-MB

X76_SAM@

CV3010

DIS@

820P_0402_50V7K~D

UV6

PCB-MB

X76_SAM@

FBA_DBI7 FBA_DBI5

CLKA1 CLKA1# FBA_CMD30

FBA_CMD25 FBA_CMD26

FBA_CMD27 FBA_CMD17 FBA_CMD18

FBA_CMD20 FBA_CMD19 FBA_CMD23 FBA_CMD22

FBA_CMD24 FBA_CMD31 FBA_CMD21 FBA_CMD28 FBA_CMD16

+FBA_VREFC_H

1

FBA_CMD29

2

FBA_WCK67# FBA_WCK67

FBA_WCK45# FBA_WCK45

HYNIX

UV6

PCB-MB

X76_HYN@

5

UV7

PCB-MB

X76_HYN@

4

MIRROR

4

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47

+1.5V_GPU

RV3005 1K_0402_1%~DDIS@RV3005 1K_0402_1%~DDIS@ RV3006 1K_0402_1%~DDIS@RV3006 1K_0402_1%~DDIS@ RV3008 121_0402_1%~DDIS@RV3008 121_0402_1%~DDIS@

+FBA_VREFD_H

1

CV3009

CV3016

2

DIS@

820P_0402_50V7K~D

10U_0603_6.3V6M~D

CV3029

1

2

DIS@

3

UV6

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

FBA_SEN3

FBA_WCK45# FBA_WCK45

FBA_WCK67# FBA_WCK67

FBA_CMD29

1U_0402_6.3V6K~D

1

CV3026

2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

J5

A12/RFU/NC

K4

A8/A7 A10/A0

K5

A11/A6 A9/A1

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

H11

BA0/A2 BA2/A4

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

170-BALL

SGRAM GDDR5

H5GQ2H24MFR-T2C_BGA170~D

@

FBA_EDC6

FBA_DBI4 FBA_DBI6

CLKA1 CLKA1#

FBA_CMD30 FBA_CMD25 FBA_CMD22

FBA_CMD23FBA_D40 FBA_CMD20 FBA_CMD19

FBA_CMD17 FBA_CMD18 FBA_CMD27 FBA_CMD26

1 2 1 2 1 2

FBA_CMD24 FBA_CMD28 FBA_CMD16 FBA_CMD31 FBA_CMD21

+FBA_VREFC_H

1

2

DIS@

1

CV3007

2

DIS@

820P_0402_50V7K~D

1

2

DIS@

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

820P_0402_50V7K~D

+1.5V_GPU

1U_0402_6.3V6K~D

1

CV3025

CV3024

CV3023

2

DIS@

3

DIS@

NORMAL

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

2

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

1

FBA_D32 FBA_D33FBA_EDC4 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39

FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55

+1.5V_GPU+1.5V_GPU

+1.5V_GPU

+FBA_VREFD_H

FBVREF_ALTV<24,29>

DELL CONFIDENTIAL/PROPRIETARY

Title

Size Document Number Rev

Date: Sheet of

FBA_CMD[0..31] FBA_D[32..63] FBA_DBI[4..7] FBA_EDC[4..7]

0.1U_0402_10V7K~D

1

2

DIS@

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

CV3011

1

2

DIS@

12

DIS@

13

D

2

G

DIS@

S

123

123 VRAM A Upper

VRAM A Upper

LA-7841P

CV3028

DIS@

CV3012

DIS@

RV3012

931_0402_1%

QV3001

SSM3K7002FU_SC70-3~D

+1.5V_GPU

DIS@

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D CV3008

CV3008

1

2

DIS@

1U_0402_6.3V6K~D

1

CV3013

2

DIS@

RV3014

1 2

DIS@

1.33K_0402_1%~D

1.33K_0402_1%~D RV3017

RV3017

1 2

DIS@

1.33K_0402_1%~D

FBA_CMD[0..31] <28,29> FBA_D[32..63] <28>

FBA_DBI[4..7] <28> FBA_EDC[4..7] <28>

10K_0402_5%~D

12

RV3001

FBA_CMD30

FBA_CMD29

10K_0402_5%~D

12

RV3002

0.1U_0402_10V7K~D

CV3003

1

2

DIS@

1U_0402_6.3V6K~D

1

CV3014

2

DIS@

12

DIS@ RV3015

DIS@

1

0.1U_0402_10V7K~D

CV3004

1

2

DIS@

CV3015

549_0402_1%~D

+FBA_VREFC_H

RV3015 931_0402_1%

931_0402_1%

30 65Tuesday, February 07, 2012

CV3005

RV3013

DIS@

RV3016

DIS@

0.1U_0402_10V7K~D

1

2

DIS@

+1.5V_GPU

CV3006

12

0.3

5

4

3

2

1

intent to blank

D D

C C

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

1

0.3

31 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

D D

C C

intent to blank

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

1

0.3

32 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

+1.05VS to +1.05V_GPU+3VS to +3V_GPU +1.5VS to +1.5V_GPU

+VSBP+3VALW

PT

5

12

DIS@

RV2804

40.2K_0402_1%~D

3.3VS_GFX_EN

3

DIS@

QV2806B

4

12

DIS@

RV2805

100K_0402_5%~D

D D

DGPU_PWR_EN<19,61>

100K_0402_5%~D

DGPU_PWR_EN

3.3VS_GFX_ON#

61

QV2806A

2

DMN66D0LDW-7_SOT363-6~D

DIS@

+3VS +3V_GPU

ST

RV3525 0_0402_5%~D

12

DIS@

RV3528

RV3528 150K_0402_5%~D

150K_0402_5%~D

PT

DMN66D0LDW-7_SOT363-6~D

Around 1.4 A

DIS@

QV2801

QV2801 SI3456DDV-T1-GE3_TSOP6~D

SI3456DDV-T1-GE3_TSOP6~D

D

6

S

45 2 1

G

12

3

1

@

CV2804

0.1U_0402_25V6K~D

2

SHORT

Around 4.5 A+1.44A X 4pcs VRAM=10.26A

PT2

3.3VS_GFX_EN

ST

DIS@

+1.5V

1 2

RV2811 20K_0402_5%~DDIS@ RV2811 20K_0402_5%~DDIS@

DIS@

QV2803

SIR818DP-T1_POWERPAK-SO8-5~D

5

SSI2

3 2 1

4

1

CV2807

DIS@

0.1U_0402_25V6K~D

2

+1.5V_GPU

3.3VS_GFX_EN

SI2

S

RV2810

1 2

47K_0402_5%~D

DIS@

+VCCP

8 7 6 5

DIS@

QV2804

QV2804 AO4304L_SO8

AO4304L_SO8

4

PT

1

CV2808

DIS@

0.1U_0402_25V6K~D

2

Around 3 A

+1.05V_GPU

1 2 3

GPU Power Discharge Path

C C

+1.5V_GPU +1.05V_GPU

12

DIS@

QZ5A

2

DIS@

RZ10

RZ10 22_0402_5%~D

22_0402_5%~D

61

2N7002DW-7-F_SOT363-6

ST ST

3.3VS_GFX_ON# 3.3VS_GFX_ON#

B B

DIS@

QZ5B

5

12

DIS@

RZ11

RZ11 22_0402_5%~D

22_0402_5%~D

3

3.3VS_GFX_ON# 3.3VS_GFX_ON#

4

2N7002DW-7-F_SOT363-6

+GPU_CORE

12

ST ST

DIS@

RZ40

RZ40 22_0402_5%~D

22_0402_5%~D

3

DIS@

QZ21B

5

4

2N7002DW-7-F_SOT363-6

PT PT

2N7002DW-7-F_SOT363-6

DIS@

QZ21A

2

+3V_GPU

12

61

DIS@

RZ41

RZ41 22_0402_5%~D

22_0402_5%~D

GPU Power Up Power Rail Sequence

+3V_GPU

+GPU_CORE

+1.5V_GPU

+1.05V_GPU The ramp time for any rail must be more than 40us.

2N7002DW-7-F_SOT363-6

GPU Power Down Sequence

First rail to power down

Last rail to power down

Toff < 10ms

GPU Power Up Sub-system Sequence

Driver call t

o enable GPU

T1

T8

Power EN

NV3V3Pgood

27Mhz

GPU all PG T1 Custom

CLK REQ#

100MHz

GPU Reset#

T2 >0 T3 >0 T4 >0 T5 >100us T6 >0 T7 <48ms T8 500ms T9 >0

PCIe Training

T9 T2 T3 T4 T5 T6 T7

GPU Power Down Sub-system Sequence

T1

T7

GPU Disable call

Link tear down

GPU Reset#

Power EN

27Mhz

100MHz

NV3V3Pgood

A A

Call Return

T1 Custom T2 >0 T3 >0 T4 <=0 T5 >=0 T6 Custom T7 Custom

T2 T3 T4 T5 T6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

1

0.3

33 65Tuesday, February 07, 2012

0.3

A

B

C

D

E

+3VALW to +3V_PCH

+VSBP

12

RZ14

5

+VSBP

ST

D

2

G

S

+VSBP +1.5V

SSI2

2

G

RZ14 100K_0402_5%~D

100K_0402_5%~D

3

QZ7B

QZ7B DMN66D0LDW-7_SOT363-6~D

DMN66D0LDW-7_SOT363-6~D

4

12

RZ17

RZ17 100K_0402_5%~D

100K_0402_5%~D

1

QZ10

3

12

RZ21

RZ21 330K_0402_5%

330K_0402_5%

13

D

S

SI4800BDY-T1-GE3_SO8

+3VALW

1 1

+5VALW

12

RZ26

RZ26 100K_0402_5%~D

100K_0402_5%~D

61

PCH_PWR_EN<38>

DMN66D0LDW-7_SOT363-6~D

QZ14A

2

SSI2

2 2

+VSBP

12

RZ27

RZ27 100K_0402_5%~D

100K_0402_5%~D

3

QZ14B

5

DMN66D0LDW-7_SOT363-6~D

4

PCH_PWR_EN# <22>

SI4800BDY-T1-GE3_SO8 QZ12

QZ12

8 7

5

4

1

2

1 2 36

SSI2

CZ48

0.1U_0603_50V_X7R

+3V_PCH

1

CZ45

CZ45 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

2

+5VALW

2

SSI2

12

RZ20

RZ20 100K_0402_5%~D

100K_0402_5%~D

SUSP

61

QZ7A

DMN66D0LDW-7_SOT363-6~D

SUSP

12

RZ36

@RZ36

@

470_0402_5%

+3V_PCH_D

T

S

1

D

2

G

QZ13

@

S

3

ME2N7002D-G_SOT23-3

SUSP#<12,38,56,57,58>

SSI2

SUSP

QZ11

SSM3K7002FU_SC70-3~D

3 3

ME2N7002D-G_SOT23-3

+5VALW to +5VS

+5VALW

8 7

5

+3VALW to +3VS

+3VALW

8 7

5

+1.5V To +1.5VS

PT

8 7 6 5

12

SSI2

RZ42

1.5M_0402_5%~D

SI4800BDY-T1-GE3_SO8

SI4800BDY-T1-GE3_SO8 QZ6

QZ6

4

S

SI2

1

CZ15

0.1U_0603_50V_X7R

2

SI4800BDY-T1-GE3_SO8

SI4800BDY-T1-GE3_SO8 QZ8

QZ8

4

SSI2

1

CZ38

0.1U_0603_50V_X7R

2

QZ4

AO4304L_SO8

4

1

CZ41

0.1U_0603_50V_X7R

2

+5VS

1 2

1

36

CZ11

CZ11 10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

ST

SSI2

+3VS

1 2 36

1

CZ20

CZ20 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

2

SSI2

+1.5VS

1 2

1

3

CZ39

CZ39 10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

2

SSI2

QZ18B

@QZ18B

@

2

5

12

RZ13

@RZ13

@

470_0402_5%

+5VS_D +3VS_D

61

QZ19A

@QZ19A

@

DMN66D0LDW-7_SOT363-6~D

12

RZ37

@RZ37

@

470_0402_5%

3

QZ19B

@QZ19B

@

DMN66D0LDW-7_SOT363-6~D

4

12

RZ34

@RZ34

@

470_0402_5%

+1.5VS_D

3

4

DMN66D0LDW-7_SOT363-6~D

+5VALW

12

RZ33 100K_0402_5%~D

100K_0402_5%~D

ST

4 4

SYSON<38,58>

SYSON#

1

D

2

G

@

S

3

A

+1.5V

12

RZ39

@RZ39

@RZ33

@

QZ20

@

QZ20

@

QZ15

ME2N7002D-G_SOT23-3

@

470_0402_5%

+1.5V_D

13

D

2

G

S

SSM3K7002FU_SC70-3~D

SUSP

+VCCP

SSI2

2

12

RZ35

@RZ35

@

470_0402_5%

+VCCP_D

61

QZ18A

@QZ18A

@

DMN66D0LDW-7_SOT363-6~D

+0.75VS+1.5V_CPU_VDDQ

12

RZ32 220_0402_5%~D

220_0402_5%~D

+1.5V_CPU_VDDQ_CHG

QZ16

@

QZ16

@

13

D

RUN_ON_CPU1.5VS3#<8,12>

B

2

G

S

SSM3K7002FU_SC70-3~D

12

RZ31

@RZ31

@RZ32

@

QZ17

@

QZ17

@

22_0402_5%

+DDR_CHG

13

D

2

G

S

SSM3K7002FU_SC70-3~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

C

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

DC/DC Interface

LA-7841P

E

34 65Tuesday, February 07, 2012

of

0.3

5

L

CD PWR CTRL

+LCDVDD +5VALW

PT

1 2

1

13

D

QV3502

S

RV3507

10K_0402_5%~D

D D

VGA_LVDDEN<18>

EC_ENVDD<38>

EC_ENVDD

SSM3K7002FU_SC70-3~D

DV3501

2

3

BAT54C-7-F_SOT23~D

RV3504

RV3504 100_0402_1%~D

100_0402_1%~D

2

G

2

G

12

RV3505

10K_0402_5%~D

RV3503

RV3503 150K_0402_5%

150K_0402_5%

13

D

QV3503

QV3503 BSS138-G_SOT23-3

BSS138-G_SOT23-3

S

SSI2 PT

LCD backlight PWR CTRL

C C

@

1 2

RV3516 0_0603_5%~D

B+

0.1U_0402_25V6K~D

1

CV3509

PT

2

T

S

SHORT

EN_INVPWR<38>

B B

RV3517 0_0402_5%~D

12

+LCDVDD_R

2

G

4 5

12

RV3514

RV3514 1M_0402_5%~D

1M_0402_5%~D

PWR_SRC_ON

12

RV3515

RV3515 1M_0402_5%~D

1M_0402_5%~D

PT

13

D

QV3505

QV3505 SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

S

QV3504

QV3504 SI3457CDV

SI3457CDV

S

G

3

D

6 2

1

PT

2

4

+3VS

PT

2

12

G

1

CV3504

0.1U_0402_16V7K~D

2

0.1U_0402_25V6K~D

CV3510

1 3

+INV_PWR_SRC

W=60mils

S

QV3501

QV3501 AO3419L_SOT23-3

AO3419L_SOT23-3

D

+LCDVDDVGA_LVDDEN

1

CV3505

4.7U_0603_6.3VAK~D

2

+LCDVDD

1

2

W=60mils

CV3506

0.1U_0402_16V7K~D

BKOFF#<38>

SSI2

EC_INV_PWM<38>

ST

+3VS

VGA_PWM<18>

3

BKOFF#

CH751H-40PT_SOD323-2~D

DV3503

2 1

CH751H-40PT_SOD323-2~D

RV3529

1

CV3528

@CV3528

@

470P_0402_50V7K~D

2

RV3523 0_0402_5%~D@RV3523 0_0402_5%~D@ RV3524 0_0402_5%~D@RV3524 0_0402_5%~D@

12 12

SSI2

USB20_P12<19>

USB20_N12<19>

+3VS

12

RV3502

@ RV3502

@

4.7K_0402_5%~D

21

CE_EN DBC_EN

PT

4.7K_0402_5%~D

DISPOFF#

RV3530

+3VS

12

RV3510

@RV3510

@

10K_0402_5%~D

INV_PWM

12

RV3508

10K_0402_5%~D

PT

DLW21SN900SQ2L_0805_4P~D

1

4

@

2

3

4

LI4

1 2

SHORT

RI6 0_0402_5%~D

1 2

SHORT

RI8 0_0402_5%~D

12

10K_0402_5%~D

10K_0402_5%~D RV3506

RV3506

12

0_0402_5%~D

1

2

0_0402_5%~D

CV3529

@CV3529

@

470P_0402_50V7K~D

Reserve 2 Pins for AUO panel extra feature for Dell. Panel side Pin34 DCR(Dynamic Contrast Ratio) Panel side Pin35 DBC(Dynamic Backlight Control)

2

USB20_P12_L

3

USB20_N12_L

DV3502

12

LVDS_DDC_CLK LVDS_DDC_DATA

0_0402_5%~D

DV5

@

2 1

RB751V-40_SOD323-2

RB751V-40_SOD323-2 DV4

DV4

2 1

RB751V-40_SOD323-2

ST

2

W=60mils

1

LVDS Conn.

LVDS_A0LVDS_A0+

LVDS_A1LVDS_A1+

LVDS_A2LVDS_A2+

LVDS_ACLKLVDS_ACLK+

LVDS_B0LVDS_B0+

LVDS_B1LVDS_B1+

LVDS_B2LVDS_B2+

LVDS_BCLKLVDS_BCLK+

LCD_TEST LVDS_DDC_CLK LVDS_DDC_DATA INV_PWM DISPOFF#

CE_EN DBC_EN

0.1U_0402_16V7K~D

10U_0805_10V4Z~D

CV3501

CV3508

1

2

1

2

S

T

8/25Scott: follow Conn list,check LCD pin define

+3VS

+LCDVDD

+INV_PWR_SRC

LVDS_A0-<18> LVDS_A0+<18>

LVDS_A1-<18> LVDS_A1+<18>

LVDS_A2-<18> LVDS_A2+<18>

LVDS_ACLK-<18> LVDS_ACLK+<18>

LVDS_B0-<18> LVDS_B0+<18>

LVDS_B1-<18> LVDS_B1+<18>

LVDS_B2-<18> LVDS_B2+<18>

LVDS_BCLK-<18> LVDS_BCLK+<18>

LCD_TEST<38> LVDS_DDC_CLK<18> LVDS_DDC_DATA<18>

SSI2ST

0.1U_0402_16V7K~D

CE_EN<20> DBC_EN<20>

CV3507

* Reserved for EMI/ESD/RF need to close to JLVDS

DV3504

V I/O V BUS V I/O

0_0402_5%~D

Ground

RV3519

V I/O

1 2 3

12

1

2

USB20_P12_LDMIC0

USB20_N12_L

DMIC_CLK_R

CV3513

@CV3513

@

470P_0402_50V7K~D

6

DMIC_CLK

5 4

IP4223CZ6_SO6-6@

+5VS

DMIC_CLK_R

DMIC_CLK<48>

ST

JLVDS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

G1

37

G2

38

G3

39

G4

40

G5

ACES_50398-04071-001

41 42 43 44 45

Webcam PWR CTRL

+3VS_CAM+3VS

QV3506

SI2301CDS-T1-GE3_SOT23-3

12

2

RV3522

CV3515

0.1U_0402_16V7K~D

A A

EN_CAM<19>

5

RV3522 100K_0402_5%~D

100K_0402_5%~D

1

D

2

G

QV3508

S

ST

3

ME2N7002D-G_SOT23-3

QV3506

S

D

13

G

2

4

Webcam Conn.

ST

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

3

+3VS+3VS_CAM

USB20_P12_L USB20_N12_L

DMIC0<48>

PCH_SMLCLK<17,24,38>

PCH_SMLDATA<17,24,38>

DMIC0

Remove CAM_DET#

DMIC_CLK_R

2011/07/15 2012/07/15

SSI2

Compal Secret Data

Deciphered Date

2

SSI2

JCAM

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_87036-1001-CP

* Reserved for LCD sequence tuning

+INV_PWR_SRC

+5VALW

RV3521

100K_0402_5%~D

@

QV3507A

+LCDVDD_R

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LVDS /camera conn.

LVDS /camera conn. LA-7841P

LA-7841P

12

RV3520

@RV3520

DMN66D0LDW-7_SOT363-6~D

@

QV3507B

5

1

@

3

4

DMN66D0LDW-7_SOT363-6~D

820_0402_5%~D

35 65Tuesday, February 07, 2012

of

12

61

0.3

5

4

3

2

1

Place close to JHDMI

1 2

D D

HDMI_A3N_VGA<18> HDMI_A3P_VGA<18>

HDMI_A2N_VGA<18> HDMI_A2P_VGA<18>

HDMI_A1N_VGA<18> HDMI_A1P_VGA<18>

HDMI_A0N_VGA<18> HDMI_A0P_VGA<18>

C C

12

CV758 0.1U_0402_10V7K~DCV758 0.1U_0402_10V7K~D

12

CV759 0.1U_0402_10V7K~DCV759 0.1U_0402_10V7K~D

12

CV760 0.1U_0402_10V7K~DCV760 0.1U_0402_10V7K~D

12

CV761 0.1U_0402_10V7K~DCV761 0.1U_0402_10V7K~D

12

CV762 0.1U_0402_10V7K~DCV762 0.1U_0402_10V7K~D

12

CV763 0.1U_0402_10V7K~DCV763 0.1U_0402_10V7K~D

12

CV764 0.1U_0402_10V7K~DCV764 0.1U_0402_10V7K~D

12

CV765 0.1U_0402_10V7K~DCV765 0.1U_0402_10V7K~D

TMDS_TXCN TMDS_TXCP

TMDS_TX0N TMDS_TX0P

TMDS_TX1N TMDS_TX1P

TMDS_TX2N TMDS_TX2P

TMDS_TXCN

TMDS_TXCP

TMDS_TX0N TMDS_L_TX0N

PT

RV429

470_0402_5%

RV429

470_0402_5%

RV430

470_0402_5%

RV430

470_0402_5%

12

RV433

470_0402_5%

RV433

470_0402_5%

RV431

470_0402_5%

RV431

470_0402_5%

RV432

470_0402_5%

RV432

470_0402_5%

12

RV436

470_0402_5%

RV436

470_0402_5%

RV434

470_0402_5%

RV434

470_0402_5%

RV435

470_0402_5%

RV435

470_0402_5%

12

+3VS

13

D

2

QV34

G

2N7002_SOT23-3

G

2N7002_SOT23-3

S

SSI2

+5VS

TMDS_TX0P

TMDS_TX1N

TMDS_TX1P

TMDS_TX2N

TMDS_TX2P

RV422 0_0402_5%~D@RV422 0_0402_5%~D@

LV7

1

4

EXC34CG900U

1 2

RV423 0_0402_5%~D@RV423 0_0402_5%~D@

1 2

RV425 0_0402_5%~D@RV425 0_0402_5%~D@

LV8

1

4

EXC34CG900U

1 2

RV426 0_0402_5%~D

1 2

RV428 0_0402_5%~D@RV428 0_0402_5%~D@

LV9

1

4

EXC34CG900U

1 2

RV437 0_0402_5%~D@RV437 0_0402_5%~D@

1 2

RV439 0_0402_5%~D@RV439 0_0402_5%~D@

LV10

1

4

EXC34CG900U

1 2

RV441 0_0402_5%~D@RV441 0_0402_5%~D@

2

3

2

3

@

2

3

2

3

T

S

ST

TMDS_L_TXCN

TMDS_L_TXCP

TMDS_L_TX0P

TMDS_L_TX1N

TMDS_L_TX1P

TMDS_L_TX2N

TMDS_L_TX2P

ST

12

DV9

RB751V40_SC76-2

61

DDC_CLK_HDMI

DDC_DAT_HDMI

RB751V40_SC76-2

B B

+3VS

12

RV450

2.2K_0402_5%~D

PCH_SDVO_CTRLCLK<18>

PCH_SDVO_CTRLDATA<18>

A A

2.2K_0402_5%~D

12

RV451

4

DMN66D0LDW-7_SOT363-6~D

5

QV35B

QV35A

2

DMN66D0LDW-7_SOT363-6~D

3

1 2

RV443

@RV443

@

0_0402_5%~D

RV445

1 2

2.2K_0402_5%~D

RV447

2.2K_0402_5%~D

SSI2

HDMI_PCH_HPD#<18>

1

CV3517

@CV3517

@

4.7P_0402_50V8C~D

2

1

CV3519

@CV3519

@

4.7P_0402_50V8C~D

2

1

CV3521

@CV3521

@

4.7P_0402_50V8C~D

2

1

CV3523

@CV3523

@

4.7P_0402_50V8C~D

2

1

CV3518

@CV3518

@

4.7P_0402_50V8C~D

2

1

CV3520

@CV3520

@

4.7P_0402_50V8C~D

2

1

CV3522

@CV3522

@

4.7P_0402_50V8C~D

2

1

CV3524

@CV3524

@

4.7P_0402_50V8C~D

2

RV444

RV444 1M_0402_1%~D

1M_0402_1%~D

1 2

+3VS

G

2

QV36

QV36 SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

13

D

S

D

S

HDMI_HPLUG

12

RV442

RV442 20K_0402_5%~D

20K_0402_5%~D

+5VS

W=40mils

DV8

2 1 3

NC

BAT1000-7-F_SOT23-3~D

HDMI Conn.

@

RV424 0_1206_5%~D

12

FV1

12

1.5A_6V_1206L150PR~D

HDMI_HPLUG

DDC_DAT_HDMI DDC_CLK_HDMI HDMI_Reserved HDMI_CEC TMDS_L_TXCN

TMDS_L_TXCP TMDS_L_TX0N

TMDS_L_TX0P TMDS_L_TX1N

TMDS_L_TX1P TMDS_L_TX2N

TMDS_L_TX2P

Part Number Description

RO0000002HM

SSI2

For EMI Reserve

CV3525 0.1U_0402_25V6K~D@ CV3525 0.1U_0402_25V6K~D@ CV3526 0.1U_0402_25V6K~D@ CV3526 0.1U_0402_25V6K~D@ CV3527 0.1U_0402_25V6K~D@ CV3527 0.1U_0402_25V6K~D@

close to JHDMI

0.1U_0402_10V7K~D

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

ROYALTY HDMI W/LOGO46@

HDMI W/Logo:RO0000002HM

1 2 1 2 1 2

+VDISPLAY_VCC

CV766

1

CV767

2

10U_0603_6.3V6M~D

JHDMI

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

CONCR_099AMAC19CBACNF

CONN@

GND GND GND GND

HDMI_HPLUG HDMI_Reserved HDMI_CEC

20 21 22 23

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HDMI

LA-7841P

1

36 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

FV2

+3VS

DP_CBL_DET

QV37

ST

RV449

RV449 0_0402_5%~D

0_0402_5%~D

1 2

+3VS

12

13

D

S

SSI2

SHORT

100K_0402_5%~D

RV452

2

G

D D

C C

PCH_DPC_P0<18> PCH_DPC_N0<18> PCH_DPC_P1<18> PCH_DPC_N1<18> PCH_DPC_P2<18> PCH_DPC_N2<18> PCH_DPC_P3<18> PCH_DPC_N3<18>

PCH_DPC_AUXP<18> PCH_DPC_AUXN<18>

+3VS

12

PCH_DDPC_CTRLCLK<18> PCH_DDPC_CTRLDATA<18>

12

CV779 0.1U_0402_10V6K~DCV779 0.1U_0402_10V6K~D

12

CV780 0.1U_0402_10V6K~DCV780 0.1U_0402_10V6K~D

12

CV781 0.1U_0402_10V6K~DCV781 0.1U_0402_10V6K~D

12

CV782 0.1U_0402_10V6K~DCV782 0.1U_0402_10V6K~D

12

CV783 0.1U_0402_10V6K~DCV783 0.1U_0402_10V6K~D

12

CV784 0.1U_0402_10V6K~DCV784 0.1U_0402_10V6K~D

12

CV785 0.1U_0402_10V6K~DCV785 0.1U_0402_10V6K~D

12

CV786 0.1U_0402_10V6K~DCV786 0.1U_0402_10V6K~D

PCH_DPC_AUXP PCH_DPC_AUXN

12

RV458

RV457

2.2K_0402_5%~D

RV458

2.2K_0402_5%~D

PCH_DDPC_CTRLCLK PCH_DDPC_CTRLDATA

DISP_A0P DISP_A0N DISP_A1P DISP_A1N DISP_A2P DISP_A2N DISP_A3P DISP_A3N

DP_CBL_DET<19>

CAB_DET_SINK#

Close to JMDP1

2N7002_SOT23-3

1 2

1.5A_6V_1206L150PR~D

DISP_HPD_SINK DISP_A0P CAB_DET_SINK DISP_A0N DISP_CEC

DISP_A1P DISP_A3P DISP_A1N DISP_A3N

DISP_A2P DISP_CLK_AUXP_CONN DISP_A2N DISP_DAT_AUXN_CONN

+3VS_DP

CV770

0.1U_0402_16V7K~D

CV770

0.1U_0402_16V7K~D

CV769

10U_0603_6.3V6M~D

CV769

10U_0603_6.3V6M~D

1

2

RV456 5.1M_0402_5%RV456 5.1M_0402_5%

CV787 22U_0805_6.3V6M~DCV787 22U_0805_6.3V6M~D

CV788 0.1U_0402_10V6K~DCV788 0.1U_0402_10V6K~D

RV455 1M_0402_5%~DRV455 1M_0402_5%~D

12

1

2

mDP

JMDP

1

GND

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24

ACON_MAR25-20K1801

LANE0_P

LANE0_N

GND

LANE1_P

LANE1_N

GND

LANE2_P

LANE2_N

GND

GROUND

CONN@

HPD

CONFIG1

CONFIG2

GND

LANE3_P

LANE3_N

GND

AUXCH_P

AUXCH_N

DP_PWR

DDC Dongle SW for DP

B B

+3VS

12

CV790 0.1U_0402_10V6K~DCV7900.1U_0402_10V6K~D

UV13

CAB_DET_SINK# DISP_CLK_AUXP_CONN CAB_DET_SINK

CAB_DET_SINK# DISP_DAT_AUXN_CONN

PCH_DDPC_CTRLDATA

A A

1

BE0

2

A0

3

B0

4

BE1

5

A1

6

B1

7

GND

PI3C3125LEX_TSSOP14~D

5

VCC

14 13

BE3

BE2

A3 B3

A2 B2

12 11

10 9 8

CV792

CV791

0.1U_0402_10V6K~D

12

DISP_CLK_AUXP_CONNPCH_DDPC_CTRLCLK PCH_DPC_AUXP

CAB_DET_SINK

0.1U_0402_10V6K~D

12

DISP_DAT_AUXN_CONN PCH_DPC_AUXN

1 2

RV470 100K_0402_5%~DRV470 100K_0402_5%~D

1 2

RV472 100K_0402_5%~DRV472 100K_0402_5%~D

4

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

DP HPD to PCH (iGPU)

DP_PCH_HPD<18>

SSI2

Title

Size Document Number Rev

Custom

LA-7841P

Date: Sheet

Date: Sheet of

2

Date: Sheet of

+5VS

G

2

13

DISP_HPD_SINK

D

S

D

S

QV3

QV3 BSS138-G_SOT23-3

BSS138-G_SOT23-3

12

RV454

RV454 100K_0402_5%~D

100K_0402_5%~D

Compal Electronics, Inc.

DP/FAN/HDD

of

37 65Tuesday, February 07, 2012

1

37 65Tuesday, February 07, 2012

0.3

5

ST

1 2

RE83 0_0402_5%~D

SHORT

RE83 0_0402_5%~D

+3VALW

D D

KSI[0..7] KSO[0..16]

T

P

+3VALW

1 2

RE17 2.2K_0402_5%~DRE17 2.2K_0402_5%~D

1 2

RE18 2.2K_0402_5%~DRE18 2.2K_0402_5%~D

1 2

@

RE28 10K_0402_5%~D

1 2

@

RE33 10K_0402_5%~D

C C

PT

CLK_PCI_LPC<19> PLT_RST#<8,19,40,41,42,48>

PT

EC_SMB_CK1 EC_SMB_DA1 EAPD_R# WAKE_PCH#

KSI[0..7] <39> KSO[0..16] <39>

+3VALW

SSI2

SHORT

10U_0402_6.3V6M~D

ST

CE11

22P_0402_50V8J~D

12

PLT_RST#

RE57

10K_0402_5%~D

RE11 47K_0402_5%~DRE11 47K_0402_5%~D

12

CE14 0.1U_0402_16V7K~DCE14 0.1U_0402_16V7K~D

12

RE13 33_0402_5%~DRE13 33_0402_5%~D

12

1

CE59

2

0.1U_0402_16V7K~D

BATT_CAP_LED#_LV5<49>

SSI2

0.1U_0402_16V7K~D

1

CE4

2

GATEA20<20> KB_RST#<20>

SERIRQ<16,40>

LPC_FRAME#<16,40,42>

LPC_AD3<16,40,42> LPC_AD2<16,40,42> LPC_AD1<16,40,42> LPC_AD0<16,40,42>

EC_SCI#<20>

1

CE5

2

0.1U_0402_16V7K~D

PT

+3VS

PT

1 2

RE36 2.2K_0402_5%~DRE36 2.2K_0402_5%~D

1 2

RE37 2.2K_0402_5%~DRE37 2.2K_0402_5%~D

12

RE59 10K_0402_5%~D@RE59 10K_0402_5%~D@

KSO3

SSI2

EC_TX

T4913 PAD~D@T4913 PAD~D@

B B

PCH_SMLCLK PCH_SMLDATA

ST

EC to Ambient Light Sensor, GPU

SSI2

PT

GPU_VR_HOT#<61>

PCH_SMLCLK<17,24,35> PCH_SMLDATA<17,24,35>

WAKE_PCH#<18>

AUD_MUTE#<48>

EC to BAT,Charge

ST

PM_SLP_S3#<18,43> PM_SLP_S5#<18>

EC_SMB_CK1<53,54> EC_SMB_DA1<53,54>

ST

RE34 0_0402_5%~D

RE34 0_0402_5%~D RE35 0_0402_5%~D

RE35 0_0402_5%~D

PT

EC_RX<42>

SSI2

SUSCLK<18>

PT

SUSPWRDNACK<18>

1 2

SHORT

1 2

SHORT

EC_SMI#<20>

PS_ID<53>

EC_WLAN_WAKE#<42>

EC_INV_PWM<35>

SYSTEM_FAN_FB<39>

EC_TX<42>

BATT_TURBO_BOOST<54>

USB_PWR_EN#<44>

SSI2

1 2

RE39 0_0402_5%~D

SHORT

RE39 0_0402_5%~D

SHORT

ST

RE40

100K_0402_5%~D

4

LE1

LE1 FBMA-L11-160808-800LMT_0603

FBMA-L11-160808-800LMT_0603

1 2

0.1U_0402_16V7K~D

1

CE6

CE7

2

1000P_0402_50V7K~D

GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_LPC EC_RST#

EC_SCI# BATT_CAP_LED#_LV5

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 HDA_SDO KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16

SUSPWRDNACK

EC_SMB_CK1 EC_SMB_DA1 PCH_SMLCLK PCH_SMLDATA

PM_SLP_S3#_R PM_SLP_S5#_R EC_SMI# PS_ID PBTN_SW# EC_WLAN_WAKE#

USBCHG_DET_EC#

SYSTEM_FAN_FB WAKE_PCH# EC_TX EC_RX AUD_MUTE#

BATT_TURBO_BOOST

USB_PWR_EN#

GPU_VR_HOT#

EC_CRY2

1

CE18

CE18 20P_0402_50V8J~D

20P_0402_50V8J~D

2

1 2

2

CE8

1

UE1

1

GATEA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ

4

LPC_FRAME#

5

LPC_AD3

7

LPC_AD2

8

LPC_AD1

10

LPC_AD0

12

CLK_PCI_EC

13

PCIRST#/GPIO05

37

EC_RST#

20

EC_SCII#/GPIO0E

38

GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

EC_SMB_CK1/GPIO44

78

EC_SMB_DA1/GPIO45

79

EC_SMB_CK2/GPIO46

80

EC_SMB_DA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

GPIO0A

17

GPIO0B

18

GPIO0C

19

GPIO0D

25

EC_INVT_PWM/GPIO11

28

FAN_SPEED1/GPIO14

29

EC_PME#/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

PCH_PWROK/GPIO18

34

SUSP_LED#/GPIO19

36

NUM_LED#/GPIO1A

122

XCLKI/GPIO5D

123

XCLKO/GPIO5E

+3VALW_EC

2

CE9

CE9 1000P_0402_50V7K~D

1000P_0402_50V7K~D

1

LPC & MISC

Int. K/B

Int. K/B Matrix

Matrix

9

EC_VDD/VCC

PS2 Interface

SM Bus

22

33

96

111

125

EC_VDD0

EC_VDD/VCC

PWM Output

AD Input

DA Output

CPU1.5V_S3_GATE/GPXIOA00

SPI Device Interface

SPI Flash ROM

BATT_CHG_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO55

H_PROCHOT#_EC/GPXIOA06

GPO

GPIO

PCH_APWROK/GPXIOA10

GPI

GND/GND

GND0

11

24

35

94

113

+EC_VCCA

1

2

ECAGND

ST

1 2

RE10 0_0402_5%~D

SHORT

RE10 0_0402_5%~D

GPIO0F

BEEP#/GPIO10

GPIO12

ACOFF/GPIO13

BATT_TEMP/GPIO38

GPIO39

ADP_I/GPIO3A

GPIO3B GPIO42

IMON/GPIO43

DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D

IREF/GPIO3E

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH/GPXIOD00

SPIDI/GPIO5B

SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/GPIO40

PECI_KB930/GPIO41

FSTCHG/GPIO50

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

SYSON/GPIO56

VR_ON/GPIO57

PM_SLP_S4#/GPIO59

BKOFF#/GPXIOA08

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

GPXIOD06

V18R

LE2

SHORT

67

EC_VDD/AVCC

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

VCOUT0_PH/GPXIOA07 PBTN_OUT#/GPXIOA09

SA_PGOOD/GPXIOA11

PECI_KB9012/GPXIOD07

AGND/AGND

KB9012QF-A3_LQFP128_14X14

69

ECAGND

FBMA-L11-160808-800LMT_0603

3

CE10

0.1U_0402_16V7K~D

+3VLP

21

KB_LED_PWM

23

BEEP#

26

VGATE

27

ACOFF

63

EC_BATT_PRS

64 65

ADP_I

66

AD_BID0

75 76

AOAC_Thermal

68 70

FAN_CTRL

71

EC_ENVDD

72

83

EAPD_R#

84

PWRSHARE_OE#

85

AC_PRESENT

86

PCH_PWROK

87

TP_CLK

88

TP_DATA

97

EN_INVPWR

98

EN_WOL

99 109

119 120 126 128

73 74 89 90 91 92 93 95 121 127

100 101 102 103 104 105 106 107 108

110 112 114 115 116 117 118

124

12

1 2

RE62 0_0402_5%~D

ST

WLAN_EN# GPU_HOT#_R

ENBKL

PCH_PWR_EN

BATBTN#

BATT_CHG_LED#

CAPS_LED#

LCD_TEST

BATT_LOW_LED#

SYSON

VR_ON

PM_SLP_S4#

PCH_RSMRST#

H_PROCHOT#_EC

VCOUT0_PH#

BKOFF#

CPU1.5V_S3_GATE

EC_LAN_WAKE#

HWPG

AC_IN AC_IN

EC_ON

EC_ON_CTRL#

LID_SW_IN#

SUSP#

PBTN_OUT#

EC_PECI

ST

+V18R

1

CE17

4.7U_0805_10V6K

2

KB_LED_PWM <39> BEEP# <48>

VGATE <8,18,60>

ACOFF <54>

SSD_EN <43,48> ADP_I <53,54>

PWRSHARE_EN_EC# <45>

BATT_CAP_LED#_LV1 <49> EN_DFAN1 <39> EC_ENVDD <35> BATT_CAP_LED#_LV2 <49>

ST

12

RE60 0_0402_5%~D

SHORT

RE60 0_0402_5%~D

SHORT

PWRSHARE_OE# <45> AC_PRESENT <18> PCH_PWROK <18> TP_CLK <39> TP_DATA <39>

EN_INVPWR <35>

EN_WOL <41>

HDA_SDO <16>

SHORT

BATT_CAP_LED#_LV3 <49> BATT_CAP_LED#_LV4 <49>

1 2

RE63 0_0402_5%~D

SHORT

RE63 0_0402_5%~D

SHORT

ST

ENBKL <18>

PCH_PWR_EN <34>

BATT_CHG_LED# <49> CAPS_LED# <39> LCD_TEST <35>

BATT_LOW_LED# <49> SYSON <34,58> VR_ON <60>

PM_SLP_S4# <18>

PCH_RSMRST# <18>

EC_LID_OUT# <17>

BKOFF# <35> CPU1.5V_S3_GATE <8,12,58>

EC_ON <55>

SSI2

LID_SW_IN# <40> SUSP# <12,34,56,57,58> PBTN_OUT# <8,18>

1 2

RE38 43_0402_1%RE38 43_0402_1%

12

ECAGND

CE13 100P_0402_50V8J~DCE13 100P_0402_50V8J~D

EC_BATT_PRS <53,54>

EAPD#

VCIN0_PH <53>

WLAN_EN# <42> GPU_HOT# <24>

ST

1 2

RE64 0_0402_5%~D

SHORT

RE64 0_0402_5%~D

SHORT

VCOUT0_PH# <55>

AC_IN <54>

H_PECI <8,20>

SSI2

EC_LAN_WAKE# <41>

SSI2

PT

EAPD# <48>

SSI2

2

SSI2

VCIN1_PH <53>

PT

Board ID

Ra

Rb

ST

+3VALW

1 2 12

PT

RE76

RE76 100K_0402_5%~D

100K_0402_5%~D

AD_BID0

RE77

RE77 56K_0402_5%

56K_0402_5%

Page 4 for Board ID Rev. mapping

TP_CLK TP_DATA

100K_0402_1%_TSM0B104F4251RZ

1 2

RE14 4.7K_0402_5%~DRE14 4.7K_0402_5%~D

1 2

RE15 4.7K_0402_5%~DRE15 4.7K_0402_5%~D

AOAC_Thermal

SSI2

VCOUT0_PH#

SYSON

AC_IN

EC_ON

1 2

RE78 10K_0402_5%~DRE78 10K_0402_5%~D

1 2

RE75 10K_0402_5%~DRE75 10K_0402_5%~D

1 2

RE58 100K_0402_5%~D@ RE58 100K_0402_5%~D@

CE16 100P_0402_50V8J~DCE16 100P_0402_50V8J~D

SSI2

1 2

CE60 1U_0402_6.3V6K~DCE60 1U_0402_6.3V6K~D

1

CE12

0.1U_0402_16V7K~D

2

+3VS

+3VLP

PT

1 2

12

HE1

12

1

RE74

RE74 47K_0402_1%~D

47K_0402_1%~D

S

T

+3VLP

2

G

USBCHG_DET_EC# USBCHG_DET#_D

+3VLP

12

13

D

S

RE79

RE79 100K_0402_5%~D

100K_0402_5%~D

USBCHG_DET_D <55>

QE4

QE4 2N7002_SOT23-3

2N7002_SOT23-3

SSI2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

3

1 2

+3VLP

RE72 10K_0402_5%~DRE72 10K_0402_5%~D

BATBTN#<49>

1 2

+3VLP

RE73 10K_0402_5%~DRE73 10K_0402_5%~D

PBTN_SW#<39>

PBTN_SW#

2011/07/15 2012/07/15

1 2

RB751V40_SC76-2

1 2

ST

RB751V40_SC76-2

Compal Secret Data

Deciphered Date

Power on Circuit

4

SSI2

USBCHG_DET#<45>

PT2

DE2

1 2

USBCHG_DET_EC#

RB751V40_SC76-2

DE6

1 2

ST

PT

+3VALW

+3VLP

USBCHG_DET#_D

RB751V40_SC76-2

1 2

RE69 10K_0402_5%~DRE69 10K_0402_5%~D

1 2

RE80 100K_0402_5%~DRE80 100K_0402_5%~D

1 2

RE81 150K_0402_5%@ RE81 150K_0402_5%@

T2

P

+3VS

VR_HOT#<60>

ST

RE41

RE41 0_0402_5%~D

0_0402_5%~D

SHORT

1 2

A A

H_PROCHOT#<8,54>

H_PROCHOT# H_PROCHOT#_EC

SN74LVC1G06DCKR_SC70-5

1

CE21

CE21 47P_0402_50V

47P_0402_50V

2

5

Y4A

1

UE2

P

G3NC

1

CE19

0.1U_0402_16V7K~D

2

RE42

RE42 100K_0402_5%~D

100K_0402_5%~D

1 2

+3VLP

PT

SSI2

1 2

SHORT

1 2

SHORT

1 2

SHORT

+3VALW

38 65Tuesday, February 07, 2012

1 2

RE66

RE66 10K_0402_5%~D

10K_0402_5%~D

HWPG

of

0.3

RE49

RE49 100K_0402_5%~D

DE3

DE1

2

100K_0402_5%~D

1 2

EC_ON_CTRL#BATBTN#

1

CE25

0.1U_0402_25V6K~D

2

SSI2

HWPG

POK<53,55>

SA_PGOOD<59>

+1.5V_PWROK<58>

+1.8VS_PWROK<56>

Title

EC ENE-KB930/ ENE3810

Size Document Number Rev

LA-7841P

Date: Sheet

Date: Sheet of

RE67 0_0402_5%~D@ RE67 0_0402_5%~D@

RE68 0_0402_5%~D

RE70 0_0402_5%~D

RE71 0_0402_5%~D

ST

Compal Electronics, Inc.

1

5

4

3

2

1

Power ON Circuit - PWR/Button Board

T

S

SW1

SW1 DTSM-61K-S-Q-T/R(756)

DTSM-61K-S-Q-T/R(756)

PBTN_SW#<38>

D D

1 2

3 4

0817 Hank: Move power BTN to MB

C C

0730: Steg Follow CONN List

KB_BL_DET<20>

Keyboard back light

ST

F1

0.75A_24V_1812L075-24DR

1U_0603_10V6K~D

C11

KB_BL_DET

KB_LED_PWM<38>

0.75A_24V_1812L075-24DR

20mil

1

2

R30 47K_0402_5%~DR30 47K_0402_5%~D

12

R31

R31 100K_0402_5%~D

100K_0402_5%~D

12

KB_BL_PWM

20mil

13

D

2

Q11

G

SSM3K7002FU_SC70-3~D

G

SSM3K7002FU_SC70-3~D

S

+5VS_KBL+5VS

1

2

+5VS_KBL

10U_0603_6.3V6M~D

C12

ACES_50504-0040N-001

6

4

G2

4

5

3

G1

3

2

1

JKBL

PT

+3VALW

12

CAPS_LED#<38>

+VSBP

RE51

100K_0402_5%~D

2

G

+5VS

QE5

QE5 ME2N7002D-G_SOT23-3

ME2N7002D-G_SOT23-3

12

1

D

S

3

1 3

D

RE54

ST

100K_0402_5%~D

QE6

1 2

RE84 470_0402_5%~DRE84 470_0402_5%~D

S

ST

G

2

1

CE61

@CE61

@

0.1U_0402_25V6K~D

2

KB_CAPS_LED

ST

ME2N7002D-G_SOT23-3

FAN Control circuit

+FAN_POWER

+5VS

40mil 40mil

EN_DFAN1<38>

B B

U30

1

VEN

2

VIN

3

VO

4

VSET

G996P11U_SO8

SSI2

SYSTEM_FAN_FB<38>

CE55

1 2

1U_0402_6.3V6K~D

GND GND GND GND

8 7 6 5

SYSTEM_FAN_FB

0730: Steg Follow CONN List

Touch pad

1 2

TP_CLK<38>

TP_DATA<38>

10P_0402_50V8J~D

12

C13

A A

5

L1 BLM18AG601SN1D_0603~DL1 BLM18AG601SN1D_0603~D

1 2

L2 BLM18AG601SN1D_0603~DL2 BLM18AG601SN1D_0603~D

PCH_SMBDATA<14,17,43,48>

PCH_SMBCLK<14,17,43,48>

10P_0402_50V8J~D

12

C14

Close to JTP connector

ST

FAN

+3VS

RE53

1 2

10K_0402_5%~D

2 1

DE4

CH751H-40PT_SOD323-2~D

2

3

10P_0402_50V8J~D

12

C15

DE7

@

1

C15

PESD5V0U2BT_SOT23-3~D

+FAN_POWER

KSI[0..7]<38>

+5VS

RE52

1 2

10K_0402_5%~D

2

3

10P_0402_50V8J~D

C16

1

4

+3VS

DE5

JFAN

1

2

3

4

G1

5

G2

ACES_50271-0030N-001

TP_CLK_R TP_DATA_R

PESD5V0U2BT_SOT23-3~D

ACES_51522-00601-001

1

2

CE54

CE27

2

1

2.2U_0603_10V6K~D

2.2U_0603_10V6K~D 1000P_0402_50V7K~D

1000P_0402_50V7K~D

@

CP1

KSO13 KSO15 KSO16 KSO12

KSO10 KSO11 KSO9

JTP

1

2

3

4

5

6

7

G1

8

G2

KSO14

KSO6 KSO7 KSO4 KSO5

KB_DET# KSO0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CE28 100P_0402_50V8J~D

CE28 100P_0402_50V8J~D CE29 100P_0402_50V8J~D

CE29 100P_0402_50V8J~D

3

81

2

7

3

6

4 5

100P_0805_8P4C_50V8K

@

CP2

81

2

7

3

6

4 5

100P_0805_8P4C_50V8K

@

CP3

81

2

7

3

6

4 5

100P_0805_8P4C_50V8K

@

@ 1 2 1 2

@

Compal Secret Data

2011/07/15 2012/07/15

Compal Secret Data

KSI2 KSI4 KSI6 KSI7

KSI0 KSI3 KSI1 KSI5

KSO2 KSO1 KSO3 KSO8

Deciphered Date

2

KSO[0..16]<38>

@

CP6

81

2

7

3

6

4 5

100P_0805_8P4C_50V8K

@

CP5

81

2

7

3

6

4 5

100P_0805_8P4C_50V8K

@

CP4

81

2

7

3

6

4 5

100P_0805_8P4C_50V8K

KSI[0..7]

KSO[0..16]

KB_DET#<17>

Title

Size Document Number Rev

Custom

LA-7841P

Date: Sheet of

INT_KBD Conn.

JKB

KB_DET# KSI7 KSI6 KSI4 KSI2 KSI5 KSI1 KSI3 KSI0 KSO5 KSO4 KSO7 KSO6 KSO8 KSO3 KSO1 KSO2 KSO0 KSO12 KSO16 KSO15 KSO13 KSO14 KSO9 KSO11 KSO10 KB_CAPS_LED

SSI2

Compal Electronics, Inc.

SW/TP/SCREW

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_88514-3001

1

GND GND

31 32

0.3

39 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

+3VS

ST

1

D D

+3VS

LPC_AD0<16,38,42> LPC_AD1<16,38,42> LPC_AD2<16,38,42> LPC_AD3<16,38,42>

CLK_PCI_TPM<17>

LPC_FRAME#<16,38,42>

PLT_RST#<8,19,38,41,42,48>

SERIRQ<16,38>

PM_CLKRUN#<18>

2

CLK_PCI_TPM

1 2

R34 0_0402_5%~D

ST

C C

CLK_PCI_TPM

12

ST

1

2

ATMEL TPM for XPS

4700P_0402_25V7K~D

0.1U_0402_25V6K~D

TPM@C1

0.1U_0402_25V6K~D

TPM@

@

1

C2

C1

2

SHORT

R2

R2 33_0402_5%~D

33_0402_5%~D

C8

C8 27P_0402_50V8J~D

27P_0402_50V8J~D

U1

5

SB3V

28

LPCPD#

26

LAD0

23

LAD1

20

LAD2

17

LAD3

21

LCLK

22

LFRAME#

16

LRESET#

27

SERIRQ

15

CLKRUN#

1

ATEST_1

2

ATEST_2

3

ATEST_3

AT97SC3204-X2A14-AB_TSSOP28

TPM@

S

T

VCC_0 VCC_1 VCC_2

V_BAT NBO_13 NBO_14

GPIO6

TESTBI

TESTI

NC_7

GND_4 GND_11 GND_18 GND_25

+3VS

ST

R1 4.7K_0402_5%~D@R1 4.7K_0402_5%~D@

50mA

0.1U_0402_25V6K~D

TPM@ C3

TPM@

1

C3

2

1 2

0.1U_0402_25V6K~D

10U_0603_6.3V6M~D

TPM@ C4

TPM@

1

C4

2

10U_0603_6.3V6M~D

TPM@ C5

TPM@

TPM@ C6

TPM@

1

C5

C6

2

+3VS

10 19 24

12 13 14

6 9

8

7

PP

4 11 18 25

Lid Switch

B B

H1

H_2P3

@

H9

H_4P1X3P7

@

A A

1

H2

H_1P3

@

H_4P1X3P7

@

H_3P0

1

H10

H_3P6

1

PT2

H3

H_3P3

@

1

H11

H_3P9

@

1

FD1

FD1 FIDUCAL@

FIDUCAL@

1

5

Screw Hole

H4

@

1

H12

FD2

FD2 FIDUCIAL@

FIDUCIAL@

H_1P7x1P3

1

H5

@

H_2P3

@

H13

H7

H6

H_2P3

@

1

H14

1

H7

H_2P3

@

1

H13

H_3P0

@

1

C9

0.1U_0402_16V7K~D

C9

2

S-5711ACDL-M3T1S_SOT23-3

+3VALW

2

U5

VDD

OUTPUT

GND

1

12

R4

R4 47K_0402_5%~D

47K_0402_5%~D

3

LID_SW_IN# <38>

No CIS Symbol, Change PN to SA00003GI00 as ME recommand.

FD3

FD4

FIDUCAL@

FIDUCIAL@

1

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

CONN & LID

CONN & LID LA-7841P

LA-7841P

1

of

40 65Tuesday, February 07, 2012

0.3

5

+3VALW +LAN_VDD

D

S

D

CL1

100K_0402_5%~D

1 2

13

2

G

S

RL2

G

2

EN_WOL#

RL24

RL24 10K_0402_5%~D

10K_0402_5%~D

D

QL5

QL5 SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D

S

13

QL3

QL3 AO3419L_SOT23-3

AO3419L_SOT23-3

PT

1U_0402_6.3V6K~D

1

2

D D

EN_WOL<38>

RL4

RL4 10K_0402_5%~D

10K_0402_5%~D

1 2

CL20 & CL21 close to chip side

1 2

PCIE_PRX_GLANTX_P1<17> PCIE_PRX_GLANTX_N1<17>

PCIE_PTX_GLANRX_P1<17>

+3VS

PCIE_PTX_GLANRX_N1<17>

RL11

1 2

1K_0402_5%~D

15K_0402_5%

RL13

C C

B B

A A

CL20 0.1U_0402_16V7K~DCL20 0.1U_0402_16V7K~D

1 2

CL21 0.1U_0402_16V7K~DCL21 0.1U_0402_16V7K~D

LANCLK_REQ#<17>

PLT_RST#<8,19,38,40,42,48>

CLK_PCIE_LAN<17>

CLK_PCIE_LAN#<17>

ISOLATEB

+LAN_IO

1 2

+LAN_IO

3.3V : Enable switching regulator 0V : Disable switching regulator

12

RL15 0_0402_5%~DRL15 0_0402_5%~D

RL17 2.49K_0402_1%~DRL17 2.49K_0402_1%~D

PCIE_PRX_GLANTX_P1_C PCIE_PRX_GLANTX_N1_C

XTLO XTLI

PT

LAN_WAKE#

1 2

RL12 10K_0402_5%~DRL12 10K_0402_5%~D

1 2

RL14 1K_0402_5%~DRL14 1K_0402_5%~D

+LAN_VDDREG

1 2

CL26

0.01U_0402_16V7K~D

1 2

4

W=60milsW=60mils

+LAN_IO

CL2

1.5A

1

2

1

CL3

0.1U_0402_16V7K~D

CL4

2

0.1U_0402_16V7K~D

These caps close to Pin 12,27,39,42,47,48

EC_LAN_WAKE#<38>

PT

UL1

22

HSOP

23

HSON

17

HSIP

18

HSIN

16

CLKREQB

25

PERSTB

19

REFCLK_P

20

REFCLK_N

43

CKXTAL1

44

CKXTAL2

28

LANWAKEB

26

ISOLATEB

14

NC/SMBCLK

15

NC/SMBDATA

38

GPO/SMBALERT

33

ENSWREG

34

VDDREG

35

VDDREG

46

RSET

24

GND

49

PGND

RTL8111F-CGT_QFN48_6x6

LAN_IO Rising time (10%~90%) must >1mS and <100mS

+V_DAC LAN_MDIP3 +V_DAC

LAN_MDIN2 LAN_MDIP2

+V_DAC LAN_MDIN1 LAN_MDIP1

+V_DAC LAN_MDIN0 LAN_MDIP0

LED3/EEDO LED1/EESK

LED0

EECS/SCL

EEDI/SDA

MDIP0 MDIN0 MDIP1 MDIN1

NC/MDIP2

NC/MDIN2

NC/MDIP3

NC/MDIN3

DVDD10 DVDD10 DVDD10

DVDD33 DVDD33

AVDD33 AVDD33 AVDD33 AVDD33

EVDD10 AVDD10

AVDD10 AVDD10 AVDD10

REGOUT

31 37 40

30 32

1 2 4 5 7 8 10 11

13 29 41

27 39

12 42 47 48

21 3

6 9 45

36

TL1

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+ TD2-6MX2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

X'FORM_ IH-160 LAN

CL5

0.1U_0402_16V7K~D

+LAN_IO

2

1 3

D

QL6

QL6 2N7002H_SOT23-3

2N7002H_SOT23-3

1 2 1 2

LAN_MDIP0 LAN_MDIN0 LAN_MDIP1 LAN_MDIN1 LAN_MDIP2 LAN_MDIN2 LAN_MDIP3 LAN_MDIN3

MCT1 MX1+

MX1-

MCT2 MX2+

MCT3 MX3+

MX3-

MCT4 MX4+

MX4-

G

1

2

1 2

S

24 23 22

21 20 19

18 17 16

15 14 13

CL6

0.1U_0402_16V7K~D

RL7

RL7 10K_0402_5%~D

10K_0402_5%~D

LAN_WAKE#

+LAN_VDD

+LAN_IO

+LAN_VDD

RJ45_TX3-LAN_MDIN3 RJ45_TX3+

RJ45_TX2RJ45_TX2+

RJ45_RX1RJ45_RX1+

RJ45_TX0RJ45_TX0+

1

2

RL8 10K_0402_5%~DRL8 10K_0402_5%~D RL9 10K_0402_5%~DRL9 10K_0402_5%~D

+LAN_EVDD10

+LAN_SROUT1.05

PT

3

1

2

1

CL7

2

0.1U_0402_16V7K~D

RL19 75_0603_1%RL19 75_0603_1% RL20 75_0603_1%RL20 75_0603_1% RL21 75_0603_1%RL21 75_0603_1% RL22 75_0603_1%RL22 75_0603_1%

PT

+LAN_IO

1 2 1 2 1 2 1 2

+LAN_IO

@RL1

@

470_0603_5%

1 2 13

D

S

1 2

RL5 0_0603_5%~DSHORTRL5 0_0603_5%~DSHORT

ST

RL1

2

EN_WOL#

G

QL4

@

QL4

@

SSM3K7002FU_SC70-3~D

1

CL16

2

X5R

4.7U_0603_6.3V6K~D

+LAN_SROUT1.05

1

CL27

CL27 1000P_1808_3KV7K~D

1000P_1808_3KV7K~D

2

W=40mils W=20mils

+LAN_VDDREG

CL17

2.2UH_NLC252018T-2R2J-N_5%

1

2

0.1U_0402_16V7K~D

W=60mils

2

1

CL9

CL8

2

0.1U_0402_16V7K~D

1

CL10

2

0.1U_0402_16V7K~D

These caps close to Pin 3,6,9,13,29,41,45

+LAN_VDD

RL6 0_0603_5%~D

T

S

LL1

1 2

These components close to Pin 36

( Should be place within 200 mils )

1 2

W=60mils

CL23

CL2215P_0402_50V8J~D CL2215P_0402_50V8J~D

1

2

GND

4

GND

3

CL2515P_0402_50V8J~D CL2515P_0402_50V8J~D

RJ45_TX3RJ45_TX3+ RJ45_RX1RJ45_TX2RJ45_TX2+ RJ45_RX1+ RJ45_TX0RJ45_TX0+

+LAN_VDD

1

CL24

2

0.1U_0402_16V7K~D

XTLI

YL1

YL1 25MHZ_12PF_7V25000012

25MHZ_12PF_7V25000012

XTLO

1

CL11

2

0.1U_0402_16V7K~D

1 2

SHORT

X5RCL24

X5R

4.7U_0603_6.3V6K~D

CL12

0.1U_0402_16V7K~D

+LAN_EVDD10

@

RL10

0_0402_5%~D

JLAN1

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SANTA_130460-2

CONN@

1

2

0.1U_0402_16V7K~D

CL19

CL14

0.1U_0402_16V7K~D

1

2

0.1U_0402_16V7K~D

1

2

1U_0402_6.3V6K~D

LAN_25M <17>

CL13

2

0.1U_0402_16V7K~D

1

CL18

2

12

SSI2

12

GND

11

GND

10

GND

9

GND

0817 Hank: Change to temp part

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

P25-LAN RTL8111E

LA-7841P

1

0.3

41 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

JP11

+1.5VS_WLAN

@JP11

@

112

CM8

0.1U_0402_16V7K~D

CM8

0.1U_0402_16V7K~D

CM9

0.01U_0402_16V7K~D

CM9

CM7

0.1U_0402_16V7K~D

CM7

0.1U_0402_16V7K~D

1

2

0.01U_0402_16V7K~D

1

2

+VSBP +3VALW

PT

+3VALW

RM29

10K_0402_5%~D

D D

WLAN_EN#<38>

SSI2

12

RM7

RM7 330K_0402_5%

2

G

330K_0402_5%

13

D

SSM3K7002FU_SC70-3~D

S

QM1

WLAN_EN

12

RM20

1.5M_0402_5%~D

5

QM3

AON7212L_DFN8-5

4

1

2

1 2 3

CM1

4.7U_0603_6.3V6K~D

CM1

4.7U_0603_6.3V6K~D

1

0.1U_0402_25V6K~D

0.1U_0402_25V6K~D CM28

CM28

2

CM3

0.1U_0402_16V7K~D

CM3

0.1U_0402_16V7K~D

CM2

0.1U_0402_16V7K~D

CM2

0.1U_0402_16V7K~D

1

2

1

2

SSI2

WLAN / BT4.0 PCIE Mini Card

+3VS_WLAN

CM5

47P_0402_50V

CM4

0.01U_0402_16V7K~D

CM4

0.01U_0402_16V7K~D

1

@CM5

@

2

PT

+3VS_WLAN +3VS

RM26

10K_0402_5%~D

12

QM4 2N7002_SOT23-3

2

1 3

D

G

WL_OFF#WL_OFF#_R

S

+1.5VS

2

JUMP_43X39

WL_OFF# <19>

PT

+3VS_WLAN

EC_WLAN_WAKE#<38>

PT

MINI1CLK_REQ#<17> CLK_PCIE_MINI1#<17>

C C

EC_TX<38>

BT_RADIO_DIS#<20>

EC_RX<38>

B B

CLK_PCIE_MINI1<17>

CLK_LPC_DEBUG<19>

PCIE_PRX_WLANTX_N3<17> PCIE_PRX_WLANTX_P3<17>

PCIE_PTX_WLANRX_N3<17> PCIE_PTX_WLANRX_P3<17>

PCIE_MCARD1_DET#<20>

+3VS_WLAN

1 2

RM10 0_0402_5%~DRM10 0_0402_5%~D RM12 100K_0402_5%~DRM12 100K_0402_5%~D

SSI2

1 2

RM13 1K_0402_5%~DRM13 1K_0402_5%~D

1 2

RM25 0_0402_5%~DRM25 0_0402_5%~D

RM28 10K_0402_5%~D@ RM28 10K_0402_5%~D@

PLT_RST#

12

1 2

T10PAD~D @T10PAD~D @ T11PAD~D @T11PAD~D @

1 2

RM24 0_0402_5%~DRM24 0_0402_5%~D

EC_TX_R EC_RX_R

SSI2

JMINI1

1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

GND1

GND2

2 4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

ACES_51722-0520W-001

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

+1.5VS_WLAN

1 2

RM16 0_0402_5%~DRM16 0_0402_5%~D

1 2

RM14 0_0402_5%~DRM14 0_0402_5%~D

1 2

RM17 0_0402_5%~DRM17 0_0402_5%~D

1 2

RM18 0_0402_5%~DRM18 0_0402_5%~D

1 2

RM19 0_0402_5%~DRM19 0_0402_5%~D

WL_OFF#_R PLT_RST#

MINI1_SMBCLK MINI1_SMBDATA

PLT_RST# <8,19,38,40,41,48>

USB20_N4 <19> USB20_P4 <19>

USB_MCARD1_DET# <20>

LPC_FRAME# <16,38,40> LPC_AD3 <16,38,40> LPC_AD2 <16,38,40> LPC_AD1 <16,38,40> LPC_AD0 <16,38,40>

RM22

2.2K_0402_5%~D

MINI1_SMBCLK

MINI1_SMBDATA

12

+3VS_WLAN

RM23

2.2K_0402_5%~D

RM8

@RM8

@

+3VS_WLAN

RM9

@RM9

@

QM2A

2

DMN66D0LDW-7_SOT363-6~D

61

1 2

0_0402_5%~D

QM2B

5

DMN66D0LDW-7_SOT363-6~D

3

4 1 2

0_0402_5%~D

SMBCLK <17>

SMBDATA <17>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

WLAN/WWAN/SIM/BT

LA-7841P

1

0.3

42 65Tuesday, February 07, 2012

0.3

5

SATA III Re-driver for mSATA

S

D D

SSI2

SSD_EN<38,48>

SATA_PTX_DRX_P1<16>

SATA_PTX_DRX_N1<16>

SATA_PRX_DTX_P1<16>

SATA_PRX_DTX_N1<16>

SATA_PTX_DRX_P1 SATA_PTX_DRX_N1

SATA_PRX_DTX_P1 SATA_PRX_DTX_N1

+3VS_RD_M

+3VS

PT2

RN42 0_0402_5%~DMSATA@ RN42 0_0402_5%~DMSATA@

CN30 0.01U_0402_16V7K~DMSATA@ CN30 0.01U_0402_16V7K~DMSATA@ CN31 0.01U_0402_16V7K~DMSATA@ CN31 0.01U_0402_16V7K~DMSATA@

CN11 0.01U_0402_16V7K~DMSATA@ CN11 0.01U_0402_16V7K~DMSATA@ CN10 0.01U_0402_16V7K~DMSATA@ CN10 0.01U_0402_16V7K~DMSATA@

1 2

1 2 1 2

1 2

RN10 10K_0402_5%~DMSATA@ RN10 10K_0402_5%~DMSATA@

1 2

RN11 10K_0402_5%~DMSATA@ RN11 10K_0402_5%~DMSATA@

1 2

RN12 0_0402_5%~D@RN12 0_0402_5%~D@

mSATA_ON SATA_PTX_DRX_P1_C

SATA_PTX_DRX_N1_C SATA_PRX_DTX_P1_C

SATA_PRX_DTX_N1_C mSATA_BPRE1

mSATA_APRE1 mSATA_TEST

4

+3VS

JUMP_43X39

1 2

MSATA@ CN1

MSATA@

.1U_0402_16V7K

0.01U_0402_16V7K~D

CN2

1

2

MSATA@

U44

7 1

2 5

4

17 19

18

3 13 21

0.01U_0402_16V7K~D

1

CN1

2

MSATA@U44

MSATA@

EN A_INp

A_INn B_OUTp

B_OUTn B_PRE1

A_PRE1 TEST

GND GND EPAD

PS8520BTQFN20GTR2_TQFN20_4X4

T

@

JP13

REXT

A_PRE0 B_PRE0

A_OUTp A_OUTn

B_INp B_INn

VDD VDD

NC

+3VS_RD_M

6 16

10 20

9 8

15

SATA_PTX_DRX_P1_RC

14

SATA_PTX_DRX_N1_RC

11

SATA_PRX_DTX_P1_RC

12

SATA_PRX_DTX_N1_RC

REXT_mSATA

mSATA_PE1 mSATA_PE2

MSATA@ CN26

MSATA@

MSATA@ CN27

MSATA@

0.01U_0402_16V7K~D

0.1U_0402_25V6K~D

1

CN26

CN27

2

1 2

RN3 10K_0402_5%~DMSATA@RN3 10K_0402_5%~DMSATA@

1 2

RN4 10K_0402_5%~DMSATA@ RN4 10K_0402_5%~DMSATA@

1 2

CN12 0.01U_0402_16V7K~DMSATA@ CN12 0.01U_0402_16V7K~DMSATA@

1 2

CN13 0.01U_0402_16V7K~DMSATA@ CN13 0.01U_0402_16V7K~DMSATA@

1 2

CN8 0.01U_0402_16V7K~DMSATA@ CN8 0.01U_0402_16V7K~DMSATA@

1 2

CN9 0.01U_0402_16V7K~DMSATA@ CN9 0.01U_0402_16V7K~DMSATA@

3

REXT_mSATA

P

T2

PT2

MSATA@

RN44

2.2K_0402_5%~D

1 2

+3VS_RD_M

SATA_PTX_DRX_P1_RC1 SATA_PTX_DRX_N1_RC1

SATA_PRX_DTX_P1_RC1 SATA_PRX_DTX_N1_RC1

SATA_PTX_DRX_P1_RC1 <48> SATA_PTX_DRX_N1_RC1 <48>

SATA_PRX_DTX_P1_RC1 <48> SATA_PRX_DTX_N1_RC1 <48>

2

1

C C

FFS_INT1<19> FFS_INT2<20>

PCH_SMBDATA<14,17,39,48> PCH_SMBCLK<14,17,39,48>

B B

SATA III Re-driver for HDD

A A

12

JP5

JP5 JUMP_43X39

JUMP_43X39

@

+3.3V_RUN_FFS

0.1U_0402_25V6K~D

10U_0603_6.3V6M~D

1

CN15

CN14

2

FFS_INT1 FFS_INT2

PCH_SMBDATA PCH_SMBCLK

PM_SLP_S3#<18,38>

SATA_PTX_DRX_P0<16>

SATA_PTX_DRX_N0<16>

SATA_PRX_DTX_P0<16>

SATA_PRX_DTX_N0<16>

SATA_PTX_DRX_P0 SATA_PTX_DRX_N0

SATA_PRX_DTX_P0 SATA_PRX_DTX_N0

+3VS_RD

PM_SLP_S3#

UN2

LNG3DM

1

14 11

9 7

6 4

8

1 2

CN32 0.01U_0402_16V7K~DCN32 0.01U_0402_16V7K~D

1 2

CN33 0.01U_0402_16V7K~DCN33 0.01U_0402_16V7K~D

1 2

CN22 0.01U_0402_16V7K~DCN22 0.01U_0402_16V7K~D

1 2

CN23 0.01U_0402_16V7K~DCN23 0.01U_0402_16V7K~D

1 2

RN13 0_0402_5%~D@RN13 0_0402_5%~D@

1 2

RN14 0_0402_5%~D@RN14 0_0402_5%~D@

1 2

RN31 0_0402_5%~D@RN31 0_0402_5%~D@

RES

VDD_IO

RES

VDD

RES RES

INT 1

GND

INT 2

GND SDO/SA0 SDA / SDI / SDO SCL/SPC

NC NC

CS

LNG3DMTR_LGA16_3X3~D

1 2

RN17 0_0402_5%~D@RN17 0_0402_5%~D@

10 13 15 16

5 12

2 3

SATA_PTX_DRX_P0_C SATA_PTX_DRX_N0_C

SATA_PRX_DTX_P0_C SATA_PRX_DTX_N0_C

SATA_BPRE1 SATA_APRE1

SATA_TEST

CN18

1

2

FFS_INT2

ST

0.01U_0402_16V7K~D

7 1

2 5

4

17 19

18

3 13 21

+3VS

12

RN26

RN26 100K_0402_5%~D

100K_0402_5%~D

61

2

+3VS

@

JP14

JUMP_43X39

1 2

.1U_0402_16V7K

CN19

1

2

U45

VDD

EN

VDD A_INp A_INn

B_OUTp B_OUTn

B_PRE1 A_PRE1

TEST GND GND EPAD

PS8520BTQFN20GTR2_TQFN20_4X4

REXT

A_PRE0 B_PRE0

A_OUTp A_OUTn

B_INp B_INn

NC

DMN66D0LDW-7_SOT363-6~D

QN2A

+3VS_RD

6 16

10 20

9 8

15 14

11 12

+5VS

12

RN23

RN23 100K_0402_5%~D

100K_0402_5%~D

DMN66D0LDW-7_SOT363-6~D

3

QN2B

5

4

CN25

1

2

REXT_SATA SATA_APRE0

SATA_BPRE0

SATA_PTX_DRX_P0_RC SATA_PTX_DRX_N0_RC

SATA_PRX_DTX_P0_RC SATA_PRX_DTX_N0_RC

FFS_INT2_Q

0.01U_0402_16V7K~D

0.1U_0402_25V6K~D

CN24

1

2

1 2

RN6 0_0402_5%~D@RN6 0_0402_5%~D@

1 2

RN7 0_0402_5%~D@RN7 0_0402_5%~D@

CN20 0.01U_0402_16V7K~DCN20 0.01U_0402_16V7K~D CN21 0.01U_0402_16V7K~DCN21 0.01U_0402_16V7K~D

CN28 0.01U_0402_16V7K~DCN28 0.01U_0402_16V7K~D CN29 0.01U_0402_16V7K~DCN29 0.01U_0402_16V7K~D

PM_SLP_S3#

ST

1 2 1 2

1 2

RN29 0_0402_5%~D

SHORT

RN29 0_0402_5%~D

SHORT

100K_0402_5%~D

+3VS_RD

SATA_PTX_DRX_P0_RC1

SATA_PTX_DRX_N0_RC1

SATA_PRX_DTX_P0_RC1

SATA_PRX_DTX_N0_RC1

RN25

100K_0402_5%~D

2

12

RN30

REXT_SATA

SSI2

+3VALW

12

61

12

RN45

4.99K_0402_1%~D

+VSBP

12

HDD_EN_5V

3

5

DMN66D0LDW-7_SOT363-6~D

4

QN3A

RN24

RN24 330K_0402_5%

330K_0402_5%

DMN66D0LDW-7_SOT363-6~D

QN3B

SSI2

+5VALW

12

RN46

1.5M_0402_5%~D

QN1

QN1 SI3456DDV-T1-GE3_TSOP6~D

SI3456DDV-T1-GE3_TSOP6~D

D

6 2

1

G

3

0.1U_0402_25V6K~D

1

CN16

2

S

45

+5VS_HDD

1U_0402_6.3V6K~D

10U_0805_10V6K~D

1000P_0402_50V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D CN5

CN5

1

2

1

CN4

2

10U_0805_10V4Z~D

ST

CN7

1

CN6

CN17

2

HDD CONN

JHDD

0.1U_0402_16V7K~D

CN3

+3VS

1

2

J-L_UCNR2234B020-0

JHDD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

GND

22

GND

23

GND

24

GND

SATA_PTX_DRX_P0_RC1 SATA_PTX_DRX_N0_RC1

SATA_PRX_DTX_N0_RC1 SATA_PRX_DTX_P0_RC1

HDD_DETECT#

+5VS_HDD

FFS_INT2_Q

+3VS +5VS_HDD

HDD_DETECT# <20>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

HDD / FFS

Size Document Number Rev

C

LA-7841P

Date: Sheet

1

43 65Tuesday, February 07, 2012

of

0.3

5

4

3

2

1

USB3.0 / USB2.0

PT

DI1

DLW21SN900SQ2L_0805_4P~D

D D

USB3TN1<19>

USB3TP1<19>

USB20_N0<19>

USB20_P0<19>

12

CI3 0.01U_0402_16V7K~DCI3 0.01U_0402_16V7K~D

12

CI4 0.01U_0402_16V7K~DCI4 0.01U_0402_16V7K~D

USB20_N0 USBP0_R_D-

USB20_P0

USB3T_N1

DLW21SN900SQ2L_0805_4P~D

1

2

4

LI1

LI1 RI1 0_0402_5%~D@RI1 0_0402_5%~D@

RI2 0_0402_5%~D@RI2 0_0402_5%~D@

PT

LI2

@LI2

@

4

1

DLW21SN900HQ2L_0805_4P~D

RI3 0_0402_5%~D

RI3 0_0402_5%~D RI4 0_0402_5%~D

RI4 0_0402_5%~D

4

1 2

4

1

1 2

SHORT

1 2

SHORT

3

2

3

2

USBP0_R_D+

USB3TN1_D-

USB3TP1_D+USB3T_P1

USB3TP1_D+ USB3TP1_D+ USB3TN1_D- USB3TN1_DUSB3RP1_D+ USB3RP1_D+ USB3RN1_D- USB3RN1_D-

Place close to JUSB1

ST

T

P

LI3

@LI3

@

C C

USB3RN1<19>

USB3RP1<19>

USB3RN1

USB3RP1

4

1

DLW21SN900HQ2L_0805_4P~D

1 2

RI5 0_0402_5%~D

SHORT

RI5 0_0402_5%~D

SHORT

1 2

RI7 0_0402_5%~D

SHORT

RI7 0_0402_5%~D

SHORT

3

2

USB3RN1_D-

USB3RP1_D+

DI1

@

1 2 4 5 3

8

IP4292CZ10-TB_XSON10U10~D

10 9 7 6

+5VALW

10U_0805_10V6K~D

1

2

0.1U_0402_25V6K~D

USB_PWR_EN#<38>

1

CI6

CI5

2

+USB3_VCCA

RI37

10K_0402_5%~D

PT

+3VALW

12

0.1U_0402_25V6K~D

150U_B2_6.3V-M~D

1

CI1

1

+

2

CI2

2

.0A / Channel

2

UI1

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062ADR_SO8~D

USBP0_R_DUSBP0_R_D+

USB3RN1_D-

2

3

USB3RP1_D+

DI2

PESD5V0U2BT_SOT23-3~D

DI2

PESD5V0U2BT_SOT23-3~D

USB3TN1_DUSB3TP1_D+

1

0816 Hank: Change USB connector to DC233009W00

8

OC1#

7

OUT1

6

OUT2

5

OC2#

SSI2

JUSB1

1

VBUS

2

D-

3

D+

4

GND

5

StdA-SSRX-

6

StdA-SSRX+

7

GND-DRAIN

8

StdA-SSTX-

9

StdA-SSTX+

TAITW_PUBAU3-09FLBS1NN4H0

+USB3_VCCA

USB_OC0# <19>

GND GND GND GND

10 11 12 13

ST

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

USB conn.

USB conn. LA-7841P

LA-7841P

1

0.3

44 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

USB Powershare

SB Power Switch

PI5USB1457 PI5USB1457A

D D

C C

INT

S

ST

1 2

RI17 0_0402_5%~D

SHORT

RI17 0_0402_5%~D

PWRSHARE_OE#<38>

USB20_N1<19> USB20_P1<19>

SHORT

+5VALW +5VALW

1

2

T

UI3

8

SB#

SB

7

Y-

6

Y+

5

0.1U_0402_25V6K~D

VDD

PI5USB1457AZAEX_TDFN8_2X2~D

CI13

GND

1 2 3 4 9

PWRSHARE_EN# USBP1_DUSBP1_D+ SEL

1 2

INT

D-

D+

SEL

0_0402_5%~D

RI18

RI18 10K_0402_5%~D

10K_0402_5%~D

RI19

@ RI19

@

10K_0402_5%~D

PT

ST

PWRSHARE_EN_EC#<38>

12

RI27

@RI27

@

+3VALW

12

RI26

0_0402_5%~D

RI26

0_0402_5%~D

1 2

ST

U

+5VALW

RI38

10K_0402_5%~D

CI11

CI12

10U_0805_10V6K~D

0.1U_0402_16V7K~D

1

2

2.0A

UI2

1

GND

2

IN

OUT1

3

EN1#

OUT2

4

EN2#

TPS2062ADR_SO8~D

OC1#

OC2#

+5V_CHGUSB

8 7 6 5

USB_OC1# <19>

USB3.0 / USB2.0

+5V_CHGUSB

150U_B2_6.3V-M~D

0.1U_0402_25V6K~D

DLW21SN900SQ2L_0805_4P~D

1

USBP1_D- USBP1_R_D-

USBP1_D+

B B

12

USB3TN2<19>

USB3TP2<19>

CI16 0.01U_0402_16V7K~DCI16 0.01U_0402_16V7K~D

CI17 0.01U_0402_16V7K~DCI17 0.01U_0402_16V7K~D

USB3T_N2

12

1

4

LI7

1 2

RI20 0_0402_5%~D@RI20 0_0402_5%~D@

1 2

RI21 0_0402_5%~D@RI21 0_0402_5%~D@

PT

LI8

@LI8

@

4

1

DLW21SN900HQ2L_0805_4P~D

1 2

RI22 0_0402_5%~D

1 2

RI23 0_0402_5%~D

SHORT

SHORT SHORT

SHORT

2

3

USBP1_R_D+

3

2

USB3TN2_D-

USB3TP2_D+USB3T_P2

ST

T

P

LI9

@LI9

@

USB3RN2<19>

USB3RP2<19>

A A

USB3RN2

USB3RP2

4

1

DLW21SN900HQ2L_0805_4P~D

1 2

RI24 0_0402_5%~D

SHORT

RI24 0_0402_5%~D

SHORT

1 2

RI25 0_0402_5%~D

SHORT

RI25 0_0402_5%~D

SHORT

3

2

USB3RN2_D-

USB3RP2_D+

0.1U_0402_25V6K~D

1

CI14

1

+

2

CI15

2

3

DI5

PESD5V0U2BT_SOT23-3~D

DI5

2

PESD5V0U2BT_SOT23-3~D

USBCHG_DET#<38>

1

USBP1_R_DUSBP1_R_D+

USB3RN2_DUSB3RP2_D+

USB3TN2_DUSB3TP2_D+ USBCHG_DET#

PT

DI6

@

USB3TP2_D+ USB3TP2_D+ USB3TN2_D- USB3TN2_DUSB3RP2_D+ USB3RP2_D+ USB3RN2_D- USB3RN2_D-

1 2 4 5 3

8

IP4292CZ10-TB_XSON10U10~D

10 9 7 6

Place close to JUSB3

SSI2

JUSB3

1

VBUS

2

D-

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

10

DET

TAIWI_USB005-107CRL-TW

CONN@

GND GND GND GND

11 12 13 14

ST

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

USB conn.

USB conn. LA-7841P

LA-7841P

1

0.3

45 65Tuesday, February 07, 2012

0.3

A

1 1

2 2

B

C

D

E

F

G

H

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2011/07/15 2012/07/15

E

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

F

Date: Sheet of

Compal Electronics, Inc.

HD Audio ALC275/Audio Jack

G

46 65Tuesday, February 07, 2012

H

A

1 1

2 2

B

C

D

E

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

2012/07/152011/07/15

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Speaker/Audio Jack

LA-7841P

E

47 65Tuesday, February 07, 2012

0.3

5

4

3

2

1

IO BOARD Connector

SSI2

ACES_88194-4041

0730: Steg Follow CONN List 0805: Steg follow CIS Symbol

D D

+3VS

1

CM27

2

0.01U_0402_25V7K

ST

C C

HDA_SPKR<16>

BEEP#<38>

1

CM24

2

.1U_0402_16V7K

.047U_0402_16V7K

ST

CA62 1U_0402_6.3V6K~DCA62 1U_0402_6.3V6K~D

CA63 1U_0402_6.3V6K~DCA63 1U_0402_6.3V6K~D

CM25

12

2

1

4.7U_0603_6.3V6K~D

+1.5VS +RTCBATT

CM6

.1U_0402_16V7K

ST ST

PT

IO_BEEP#

1

CM26

2

.1U_0402_16V7K

+RTCVCC

PCIE_PTX_CARDRX_P4<17> PCIE_PTX_CARDRX_N4<17>

PCIE_PRX_CARDTX_P4<17> PCIE_PRX_CARDTX_N4<17>

CLK_PCIE_CD<17>

CLK_PCIE_CD#<17>

USB20_N5<19> USB20_P5<19>

PCH_SMBCLK<14,17,39,43>

PCH_SMBDATA<14,17,39,43>

T

P

AUD_MUTE#<38>

HDA_SDIN0<16> HDA_RST_AUDIO#<16>

PT

HDA_SYNC_AUDIO<16> HDA_SDOUT_AUDIO<16>

CDCLK_REQ#<17>

PLT_RST#<8,19,38,40,41,42>

SSD_EN<38,43>

MSATA_DET#<20>

USB_WWAN_DET#<16>

DMIC0<35>

DMIC_CLK<35>

EAPD#<38>

WWAN_RADIO_DIS#<20>

IO_BEEP#

CM29

ACES_88194-4041

42

GND

41

GND

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JIO

ST

JSATA

1

2

3

4

5

6

7

8

8 9

10 GND GND

ACES_50463-0104A-001

9 10 11 12

ST

1

CA59

@

.1U_0402_16V7K

2

+5VS

2

CA60

CA60 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1

0816 Hank: P/N Correct, footprint Correct, but not CIS.

SATA_PTX_DRX_P1_RC1 <43> SATA_PTX_DRX_N1_RC1 <43>

SATA_PRX_DTX_P1_RC1 <43> SATA_PRX_DTX_N1_RC1 <43>

HDA_BITCLK_AUDIO <16>

+VSBP

S

T

1

CA61

0.1U_0402_25V6K~D

2

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/15 2012/07/15

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

Card Reader RTS5209

Card Reader RTS5209 LA-7841P

LA-7841P

1

0.3

of

48 65Tuesday, February 07, 2012

5

4

3

2

1

+5VALW

12

D D

BATT_CAP_LED#_LV1<38>

R11100K_0402_5%~DR11100K_0402_5%~D

Q6A

2

G

+5VALW

12

R12100K_0402_5%~DR12100K_0402_5%~D

Q5B

5

G

61

D

DMN66D0LDW-7_SOT363-6~D

S

1 2

34

D

DMN66D0LDW-7_SOT363-6~D

S

R10

820_0402_5%~D

BAT1IBAT1

BATT_CHG_LED#<38>

+5VALW

Power LED

ST

Q3A

2

G

+5VALW

12

R8100K_0402_5%~DR8100K_0402_5%~D

Q3B

5

G

61

D

DMN66D0LDW-7_SOT363-6~D

S

34

D

DMN66D0LDW-7_SOT363-6~D

S

12

R7100K_0402_5%~DR7100K_0402_5%~D

0730: Steg Follow CONN List

R9

1 2

PWR_LED#_DP49_10MIL_1

220_0402_5%~D

BATT_LOW_LED#_D

+5VALW

JLED

1

2

5

3

G1

3

6

4

G2

4

ACES_50504-0040N-001

BATT LOW

Q7A

2

G

+5VALW

Q8A

2

G

12

R18100K_0402_5%~DR18100K_0402_5%~D

Q6B

5

G

61

D

DMN66D0LDW-7_SOT363-6~D

S

12

R21100K_0402_5%~DR21100K_0402_5%~D

Q7B

5

G

61

D

DMN66D0LDW-7_SOT363-6~D

S

R16

1 2

IBAT2 BAT2

820_0402_5%~D

34

D

DMN66D0LDW-7_SOT363-6~D

S

R19

1 2

IBAT3 BAT3

820_0402_5%~D

34

D

DMN66D0LDW-7_SOT363-6~D

S

BATT_LOW_LED#<38>

BATT_CAP_LED#_LV5<38>

12

R17100K_0402_5%~DR17100K_0402_5%~D

C C

BATT_CAP_LED#_LV2<38>

12

R20100K_0402_5%~DR20100K_0402_5%~D

B B

BATT_CAP_LED#_LV3<38>

12

R13100K_0402_5%~DR13100K_0402_5%~D

12

R26100K_0402_5%~DR26100K_0402_5%~D

Q4A

2

G

+5VALW

Q10A

2

G

12

R14100K_0402_5%~DR14100K_0402_5%~D

Q4B

5

G

61

D

DMN66D0LDW-7_SOT363-6~D

S

12

R27100K_0402_5%~DR27100K_0402_5%~D

Q9B

5

G

61

D

DMN66D0LDW-7_SOT363-6~D

S

R15

1 2

P49_10MIL_2

820_0402_5%~D

34

D

DMN66D0LDW-7_SOT363-6~D

S

R25

1 2

IBAT5 BAT5

820_0402_5%~D

34

D

DMN66D0LDW-7_SOT363-6~D

S

+5VALW

Q9A

2

G

12

R24100K_0402_5%~DR24100K_0402_5%~D

Q8B

5

G

61

D

DMN66D0LDW-7_SOT363-6~D

S

R22

1 2

IBAT4 BAT4

820_0402_5%~D

34

D

DMN66D0LDW-7_SOT363-6~D

S

BATBTN#<38>

PESD24VS2UT_SOT23-3~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

3

Compal Secret Data

Deciphered Date

2

2012/07/152011/07/15

12

R23100K_0402_5%~DR23100K_0402_5%~D

BATT_CAP_LED#_LV4<38>

A A

5

0730: Steg Follow CONN List

+5VALW

BAT1 BAT2 BAT3 BAT4 BAT5

2

3

D8

@D8

@

1

10mil ALL

Title

Size Document Number Rev

C

Date: Sheet

JBLED

1

2

3

4

5

6

9

6

G1

7

10

7

G2

8

ACES_51524-0080N-001

Compal Electronics, Inc.

Speaker/Audio Jack

LA-7841P

1

0.3

49 65Tuesday, February 07, 2012

0.3

of

5

4

3

2

Version change list (P.I.R. List) EE section Page 1 of 1

1

Item Reason for change PG# Modify List

D D

1

GRST delay to 2ms

P04-USB3.0

DEL POK to GRST , ADD RC , R62,C154

Date Phase

2 3 4 5 6 7 8

C C

9 10 11 12 13 14 15

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/15 2012/07/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

0.3

50 65Tuesday, February 07, 2012

1

5

D D

C C

4

3

2

1

B B

A A

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

<Title>

<Doc> 0.3

A

<Doc> 0.3

A

<Doc> 0.3

A

51 65Tuesday, February 07, 2012

2

51 65Tuesday, February 07, 2012

1

5

D D

C C

4

3

2

1

B B

A A

Title

Size Document Number Rev

Date: Sheet of

5

4

3

Date: Sheet of

<Title>

<Doc> 0.3

A

<Doc> 0.3

A

<Doc> 0.3

A

52 65Tuesday, February 07, 2012

2

52 65Tuesday, February 07, 2012

1

A

12

PC902

1000P_0402_50V7K

PR917

100_0402_5%~D

1 2

2

PD905

@PD905

@

SM24_SOT23

VIN

12

PR915

PR915 100_0402_5%~D

100_0402_5%~D

PL900

JDCIN9

SINGA_2DC-S060-020F

7

GND_2

6

GND_1

5

V-

1 1

2 2

4

V-

FBMA-L11-453215-800LMA90T_1812

BATT+

12

PC905

PC904

100P_0402_50V8J~D

2

V+

1

V+

3

ID

PL902

1 2

0.01U_0402_25V7K~D

JBATT9

1

2

3

4

CLK_SMB

4

5

DAT_SMB

5

6

BATT_PRS

6

7

SYS_PRS

7

8

9

10

11

ACES_50290-01101-001

ADPIN

PSID

12

BATT++

PC906

1000P_0402_50V7K~D

12

PR938

PC900

@

BATT++BATT+

12

PC907

100P_0402_50V8J~D

1000P_0402_50V7K

1.8K_1206_5%~D

PL901

BLM18BD102SN1D_0603~D

JIMBTY battery connector

SMART

SMARTSMART

Battery:

Battery:Battery:

3 3

1.BATT+

1.BATT+1.BATT+

2.BATT+

2.BATT+2.BATT+

3.BATT+

3.BATT+3.BATT+

4.CLK_SMB

4.CLK_SMB4.CLK_SMB

5.DAT_SMB

5.DAT_SMB5.DAT_SMB

6.BATT_PRS

6.BATT_PRS6.BATT_PRS

7.SYS_PRES

7.SYS_PRES7.SYS_PRES

8.BAT_ALERT

8.BAT_ALERT8.BAT_ALERT

9.GND

9.GND9.GND

10.GND

10.GND10.GND

11.GND

11.GND11.GND

4 4

PL900

FBMA-L11-453215-800LMA90T_1812

1 2

12

PC901

100P_0402_50V8J

12

1

PD904

PD904 SM24_SOT23

SM24_SOT23

@

2

3

PR913

100_0402_5%~D

1 2

12

PR918

PR918 0_0402_5%~D

0_0402_5%~D

SHORT

3

1

B

PC903

100P_0402_50V8J

2

3

@

PD902

SM24_SOT23

EC_SMB_CK1 <38,54> EC_SMB_DA1 <38,54>

PR916

10K_0402_1%~D

1 2

EC_BATT_PRS <38,54>

SM24_SOT23

+3VALW

1

100K_0402_1%

POK<38,55>

+5VALW

PR910

1 2

PR903

1 2

100K_0402_1%

PR906

15K_0402_1%

1 2

PR911

PR911 0_0402_5%

0_0402_5%

1 2

SHORT

C

PSID-1

B+

PQ900

PQ900 FDV301N-G_SOT23-3~D

FDV301N-G_SOT23-3~D

2

VSB_N_002

G

12

PC910

.1U_0402_16V7K

PR900

PR900 0_0402_5%@

0_0402_5%@

1 2

1 3

D

G

2

C

2

PQ901

B

MMST3904-7-F_SOT323~D

E

3 1

PR909

22K_0402_1%

1 2

VSB_N_003

13

D

PQ904

PQ904 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PSID-2

PSID-3

12

PR908

PR902

33_0402_5%

1 2

PR904

PR904 10K_0402_1%

10K_0402_1%

1 2

12

100K_0402_1%

VSB_N_001

D

+3VALW+5VALW

2

3

PD901

1

BAV99W-7-F_SOT323-3~D

+5VALW

PQ903

PQ903 SI3457CDV

SI3457CDV

D

6

S

4 5

2 1

G

PC908

3

0.22U_0603_25V7K

2.2K_0402_5%

PR901

1 2

PS_ID <38>

+VSBP

12

PC909

0.1U_0402_25V6

PH901 under CPU botten side :

CPU thermal protection at 90 degree C Recovery at 50 degree C

ADP_I <38,54>

PR936

13.7K_0402_1%

1 2

12

1 2

13.7K_0402_1%

PC911

PR937

0.1U_0402_25V6

@

VCIN0_PH<38>VCIN1_PH<38>

100K_0402_1%_TSM0B104F4251RZ

PH901

+3VLP

PR935

PR935 13K_0402_1%~D

13K_0402_1%~D

1 2

12

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-DCIN / BATT CONN / OTP

XPS14

D

53 65Tuesday, February 07, 2012

0.1

A

B

C

D

Iada=0~3.34A(65W)

ADP_I = 19.9*Iadapter*Rsense

PQ100

P2

PQ102

AO4423L_SO8

PQ101

PR138

2K_0603_5%

PDTA144EU PNP_SOT323

12

PR102

200K_0402_1%~D

2

V1

61

PQ106A

DMN66D0LDW-7 2N SOT363-6

PR121

47K_0402_5%~D

1 2

PR143

@PR143

@

0_0402_5%~D

1 2

ACOFF

12

13

D

@

S

PQ142

PQ142 2N7002_SOT23

2N7002_SOT23

PQ101 AO4407A_SO8

AO4407A_SO8

8 7

5

PQ103

2

13

2

10K_0402_1%~D

1U_0603_25V6K

1 2 36

4

1 3

PQ104

PQ104 DDTC115EUA-7-F_SOT323

DDTC115EUA-7-F_SOT323

3

5

4

DMN66D0LDW-7 2N SOT363-6

ACON

13

PQ111

H_PROCHOT# <8,38>

+3VALW

PR109

@PR109

@

1 2

12

PC127

@PC127

@

12

PR111

150K_0402_1%~D

A+

PQ106B

AC_IN<38>

121K_0402_1%~D

DDTC115EUA-7-F_SOT323

2

G

PC104

PACIN

13

D

S

0.1U_0603_25V7K~D

PR119

1 1

VIN

12

1M_0402_5%~D

3

4

1M_0402_5%~D

PACIN

1U_0603_25V6K

PR137

2K_0603_5%

PQ109B

DMN66D0LDW-7

ACOFF<38>

PC124

@PC124

@

2

PACIN

G

12

ACOV

@

2

12

PR101

3.3_1210_5%~D

12

PR103

3.3_1210_5%~D

12

PC107

2.2U_0805_25V6K

2 2

3 3

4 4

ACOFF

2

G

12

PR146

5.1K_0805_1%

PQ113

PQ113 2N7002-7-F_SOT23-3

2N7002-7-F_SOT23-3

13

D

S

2

12

PC129

0.1U_0603_25V7K~D

PR147

61

1 2

EC_BATT_PRS<38,53>

5.1K_0805_1%

12

PQ109A

DMN66D0LDW-7

PR131

PR131 200K_0402_1%~D

200K_0402_1%~D

A

PR136

5

PR142

1 2 3 6

12

PR104

200K_0402_1%~D

12

1000P_0402_25V8-J

GNDA_24737

12

EC_SMB_CK1<38,53>

EC_SMB_DA1<38,53>

ADP_I<38,53>

GNDA_24737

A+

PQ108

PQ108 2N7002-7-F_SOT23-3

2N7002-7-F_SOT23-3

AO4423L_SO8

4

PC111

1 2

PR114

49.9K_0402_1%~D

1 2

CHARGER_LDO

12

PR116

PR116 100K_0402_5%~D

100K_0402_5%~D

@PR134

@

1 2

0_0402_5%~D

13

D

2

G

PQ112

S

2N7002-7-F_SOT23-3

P3 B+

8 7

5

VIN

2

3

1 2

1

5600P_0402_25V7K~D

PC105

10_1206_1%

VIN

PR134

PR124

0_0402_5%~D

SHORT

1 2

PR126

0_0402_5%~D

SHORT

1 2

12

PC123

PC123 100P_0402_50V8J~D

100P_0402_50V8J~D

B

1 2

1U_0603_25V6K

PR112

1 2

316K_0402_1%~D

ACSETIN

12

PR117

100K_0402_5%~D

12

PR122

@

121K_0402_1%~D

PR129

100_0402_1%~D

1 2

GNDA_24737

@ PC115

@

1000P_0402_25V8J~D

1 2

0_0402_5%~D

PROPRIETARY NOT E: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS C ONTAINS CONFIDE NTIAL TRADE SECRET AN D OTHER PROPRI ETARY INFORMAT ION OF DELL INC . ("DELL") THI S DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITH OUT THE EXPRES S WRITTEN AUTHO RIZATION OF DE LL. IN ADDITION , NEITHER THIS SH EET NOR THE IN FORMATION IT C ONTAINS WAY BE USED BY OR DIS CLOSED TO ANY T HIRD PARTY WITHOUT D ELL'S EXPRESS WRITTEN CONSEN T.

PR110

ACOV

1 2

PR145

PD100

BAS40CW_SOT323-3

PC110

GNDA_24737

100K_0402_1%

PC115

PR100

0.01_2512_1%

1

4 3

2

CSIP

12

PR105

PR105 0_0402_5%~D

0_0402_5%~D

SHORT

PC106

1 2

0.1U_0603_25V7K~D

12

20

PU100

VCC

6

ACDET

5

ACOK

BQ24737RGRR_VQFN20_3P5X3P5~D

9

SCL

8

SDA

7

IOUT

11

+3VALW

PR125

10K_0402_5%~D

1 2 12

PR127

PR130

121K_0402_1%

PR148 10K_0402_5%~D@PR148 10K_0402_5%~D

12

@

12

PC125

0.01U_0402_25V7K

VIN

PR144

@

1 2

316K_0402_1%~D

ACSETIN_A

CSIN

12

PR106

PR106 0_0402_5%~D

0_0402_5%~D

SHORT

12

PC109

0.1U_0603_25V7K~D

1

2

ACP

ACN

CMPIN

ILIM10BM#

4

CMPIN_1

1 2

PR128 0_0402_5%~DPR128 0_0402_5%~D

1 2

GNDA_24737

BATT_TURBO_BOOST

3

CMPOUT

SRN12SRP

13

PR133

1 2

6.8_0402_1%~D

1 2

PC121

0.1U_0603_25V7K~D

PR141 0_0402_5%~DPR141 0_0402_5%~D

PC126

1 2

GNDA_24737GNDA_24737

PC108

0.1U_0603_25V7K~D

1 2

14

GND

BTST

REGN

HIDRV

PHASE

LODRV

PAD

0.1U_0603_25V7K~D

<38>

@

17

16

18

19

15

21

1 2

PR139 3M_0402_5%@ PR139 3M_0402_5%@

1 2

PR140 0_0402_5%~D@PR140 0_0402_5%~D@

BST

CHARGER_LDO

GNDA_24737

PR132

10_0402_1%~D

@PC122

@

PJP100

@PJP100

@ 2

JUMP_43X118

PR113

0_0603_5%~D

1 2

DH_CHG

LX_CHG

DL_CHG

1 2

PR135

0_0402_5%~D

SHORT

12

GNDA_24737

PC122

0.1U_0603_25V7K~D

112

PC100

CMPIN_1

PACIN

BST_CHGA

PD103

BAT54HT1G_SOD323-2~D

1 2

C

CHG_B+

12

PC101

4.7U_0805_25V6-K

PC112

0.047U_0603_25V7K~D

1 2

PC113

1U_0603_10V6K~D

1 2

@

Title

Size Document Number Rev

Date: Sheet of

12

PC102

PC103

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D 2200P_0402_25V7K~D

2200P_0402_25V7K~D

786

5

PQ107

4

786

5

PQ110

4

PC128

PC128 .1U_0402_16V7K~D

.1U_0402_16V7K~D

1 2

Compal Electronics, Inc.

PWR-Charger

XPS14

PQ105

DDTC115EUA-7-F_SOT323

AO4466L_SO8~D

123

4.7UH_ETQP3W4R7WFN_5.5A_20%

PR123

AO4712L_SO8~D

123

CSSP CSSN

PQ100

AO4407A_SO8

1 2 3 6

4

PR108

PR108 10K_0402_1%~D

10K_0402_1%~D

1 2 13

2

PC114

2200P_0402_25V7K~D

PL100

1 2

12

4.7_1206_5%~D

12

PC116

680P_0402_50V7K~D

54 65Tuesday, February 07, 2012

8 7

5

PR115

100K_0402_1%~D

12

1

CHG

2

0.1

PR107

47K_0402_1%~D

1 2

12

V1

PR120 0.01_2512_1%PR120 0.01_2512_1%

4 3

D

VIN

12

PC118

PC117

@

10U_0805_25V6K

CC = 4.1A CV = 17.7V

BATT+

12

PC119

PC120

@

10U_0805_25V6K

A

B

C

D

E

2VREF_8205

1U_0603_16V6K

1 1

PC218

0.1U_0402_25V6@

1 2

PR200

13.7K_0402_1%

1 2

PR202

B+

PJP200

@PJP200

@

2

112

JUMP_43X118

2 2

PL200

2.2UH_FDSD0630-H-2R2M-P3_8.3A_20%

+3VALWP

3 3

3.3VALWP

1 2

1

+

PC210

2

150U_D2_6.3VM

TDC 7.64A Peak Current 10.7A OCP current 12.84A TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :11mohm , 14mohm

B++

+3VLP

12

PC201

0.1U_0402_25V6

PR208

PC212

12

PC202

2200P_0402_50V7K

12

2.2_1206_5%

SNUB_3V

12

1000P_0603_50V7K~D

PC203

SSM6N7002FU-2N_SOT363-6

PQ200

PQ200 AON7408L_DFN8-5

AON7408L_DFN8-5

10U_0603_6.3V6M

4.7U_0805_25V6-K

3 5

123

PQ204A

241

5

PQ202

PQ202 AON7702A_DFN8-5

AON7702A_DFN8-5

4

@PC221

@

.1U_0402_16V7K~D

ENTRIP1

61

2

UG_3V

LG_3V

PC221

VCOUT0_PH#

N_3_5V_001

10U_0603_6.3V6M

12

PR211

@PR211

@

0_0402_5%

1 2

5

0.22U_0603_10V7K

499K_0402_1%

ENTRIP2

34

12

PC205

PC208

12

PR219

@

PR210

@PR210

@

PR212

@

200K_0402_1%

PQ204B

PQ204B SSM6N7002FU-2N_SOT363-6

SSM6N7002FU-2N_SOT363-6

2.2_0603_5%

B++

12

0_0402_5%

2 1

12

PC215

@

1U_0603_10V6K

PR206

1 2

PD906

@

BZT52-B5V6S_SOD323-2

20K_0402_1%

1 2

133K_0402_1%~D

1 2

BST_3V

25

10 11 12

PR202

PR204

7 8 9

PU200

P PAD

VOUT2 VREG3 BOOT2 UGATE2 PHASE2 LGATE2

PC200

PR215

0_0402_5%

SHORT

B++

12

FB_3V

ENTRIP2

5

6

FB2

ENTRIP2

SKIPSEL

EN

14

13

1 2

2VREF_8205

1 2

PR216 0_0402_5%

4

TONSEL

15

100P_0402_50V8J~D

1 2

FB_5V

SHORT

1 2

ENTRIP1

2

3

1

FB1

REF

ENTRIP1 VOUT1

PGOOD

BOOT1 UGATE1 PHASE1

LGATE1

SECFB18VREG5

VIN16GND

RT8205LZQW(2)_WQFN24_4X4

17

12

PC214

4.7U_0805_10V6K

12

PC216

0.1U_0402_25V6

PC219

12

PR201

30.9K_0402_1%

PR203

PR203 20K_0402_1%

20K_0402_1%

PR205

76.8K_0402_1%

24 23 22 21 20 19

VL

BST_5V BST1_5VBST1_3V

POK <38,53>

PR207

1 2

2.2_0603_5%

B++

12

PC206

0.1U_0402_25V6

12

PC207

2200P_0402_50V7K

PC209

0.22U_0603_10V7K

12

@

PC222

PC222 .1U_0402_16V7K~D

.1U_0402_16V7K~D

PC204

4.7U_0805_25V6-K

UG_5V

LX_5VLX_3V LG_5V

4

PQ203

AON7702A_DFN8-5

PQ201

PQ201 AON7408L_DFN8-5

AON7408L_DFN8-5

3 5

241

4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%

5

123

PR209

PC213

12

2.2_1206_5%

SNUB_5V

12

1000P_0603_50V7K~D

PL201

1 2

1

+

PC211

2

5VALWP TDC 4.54A Peak Current 6.49A OCP current 7.788A TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :11mohm , 14mohm

150U_D2_6.3VM

+5VALWP

PJP202

PJP201

USBCHG_DET_D<38>

PR217

4 4

EC_ON<38>

VCOUT0_PH#<38>

A

1K_0402_5%

12

2 1

PD907 RB751V40_SC76-2PD907 RB751V40_SC76-2

2 1

PD908 RB751V40_SC76-2PD908 RB751V40_SC76-2

PD909 RB751V40_SC76-2PD909 RB751V40_SC76-2

21

2.2U_0603_10V7K

PC1335

@PC1335

@

2

G

1 2

B

1 2

100K_0402_5%

13

D

PQ205

PQ205 2N7002-7-F_SOT23-3

2N7002-7-F_SOT23-3

S

PR214

VL

+5VALWP

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

PJP201

1 2

@

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP203

PJP203

1 2

@

PAD-OPEN 4x4m

C

+5VALW

+3VALWP

PJP202

1 2

@

PAD-OPEN 4x4m

PAD-OPEN 4x4m PJP204

PJP204

1 2

@

PAD-OPEN 4x4m

+3VALW

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

PWR-3VALWP/5VALWP

XPS14

55 65Tuesday, February 07, 2012

E

0.1

A

B

C

D

1 1

@

PJP400

1 2

PAD-OPEN 3x3m

SUSP#<12,34,38,57,58>

2 2

12

1 2

PR402 0_0402_5%PR402 0_0402_5%

PC400

PC400 22U_0805_6.3V6M

22U_0805_6.3V6M

EN_1.8VSP

47K_0402_5%

1.8VSP_VIN

PR403

@PR403

@

+1.8VS_PWROK<38>

PL400

PU400

4

10

PVIN

9

PVIN

8

SVIN

5

EN

12

PC404

@

0.1U_0402_10V7K

2

LX

PG

3

LX

6

FB

TP

NC

7

1

11

SY8033BDBC_DFN10_3X3

1.8VSP_LX

1.8VSP_FB

PL400

1UH_PH041H-1R0MS_3.8A_20%

1 2

12

PR401

20K_0402_1%

PR400

4.7_1206_5%

SNUB_1.8VSP

12

PC405

680P_0603_50V7K

PR404

10K_0402_1%

12

PC401

@

12

22P_0402_50V8J

12

PC402

22U_0805_6.3VAM

<Vo=1.8V> VFB=0.6V Vo=VFB*(1+PR401/PR404)=0.6*(1+20K/10K)=1.8V

+1.8VS+3VALW

+1.8VSP TDC 1.092A Peak Current 1.56A

PC403

22U_0805_6.3VAM

3 3

4 4

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

A

B

C

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-1.8VSP

XPS14

D

56 65Tuesday, February 07, 2012

0.1

5

+3VS

D D

1 2

+V1.05S_VCCP_PWRGOOD<59>

PR502

43K_0402_1%

1 2

PR503

0_0402_5%

SUSP#<12,34,38,56,58>

C C

1 2

@

PC505

0.1U_0402_16V7K

12

TRIP_+V1.05S_VCCPP EN_+V1.05S_VCCPP FB_+V1.05S_VCCPP RF_+V1.05S_VCCPP

12

PR505

470K_0402_1%

PR507

4.99K_0402_1%

4

PR500

PR500 100K_0402_5%

100K_0402_5%

PU500

1 2 3 4 5

VBST

PGOOD TRIP

DRVH

EN

SW

V5IN

VFB

DRVL

TST

TPS51212DSCR_SON10_3X3

@ PC510

@

TP

12

PC510

1000P_0402_50V7K

12

10

BST_+V1.05S_VCCPP

9

UG_+V1.05S_VCCPP

8

SW_+V1.05S_VCCPP

7

+V1.05S_VCCPP_5V

6

LG_+V1.05S_VCCPP

11

PR506

@PR506

@

1.2K_0402_1%

3

+V1.05S_VCCPP_B+

5

PQ500

4

PR501

2.2_0603_5%

1 2

PC506

PC506 1U_0603_6.3V6M

1U_0603_6.3V6M

12

PC504

0.1U_0603_50V7K~D

1 2

+5VALW

4

PQ500

123

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

SIR472DP-T1-GE3_POWERPAK8-5~D

5

PQ501

SIR818DP-T1-GE3

123

12

@PR504

@

4.7_1206_5%

12

@PC508

@

1000P_0402_50V7K

PR504

PC508

2

12

PC501

PC500

0.1U_0402_25V6

PL500

1 2

1

PJP500

@ PJP500

@

2

112

JUMP_43X118

12

PC502

PC503

4.7U_0805_25V6-K

2200P_0402_50V7K

1 2

4.7U_0805_25V6-K

PC509

@

0.1U_0402_10V7K

PR508

0_0402_5%

12

SHORT

B+

+VCCP

VCCIO_SENSE <11>

PR510

PR510 10K_0402_1%~D

10K_0402_1%~D

1 2

PR509

0_0402_5%

B B

0_0402_5%

1 2

SHORT

VSSIO_SENSE <11>

+V1.05S_VCCPP TDC 11.9A Peak Current 17A OCP current 20.4A

TYP MAX H/S Rds(on) :10mohm , 14.5mohm L/S Rds(on) :3mohm , 3.6mohm

A A

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-V1.05S_VCCPP

XPS14

57 65Tuesday, February 07, 2012

1

0.1

5

PJP301

@ PJP301

@

B+

D D

+1.5V

C C

2

112

JUMP_43X118

0.56UH_PDME104T-R56MS1R407_30A_20%~D

1

+

PC308

PC308 220U_D2_4VY_R15M~D

220U_D2_4VY_R15M~D

2

PL300

1 2

1.5V_B+

12

PC302

PC300

4.7U_0805_25V6K~D

PR302

PC311

PC303

4.7U_0805_25V6K~D

0.1U_0402_25V6K~D

12

2.2_1206_5%

SNUB_1.5V

12

1000P_0603_50V7K~D

1.5VP TDC 13.83A Peak Current 19.7A OCP current 23.6A TYP MAX H/S Rds(on) :10mohm , 14.5mohm L/S Rds(on) :3mohm , 3.6mohm

4

PR300

2.2_0603_5%~D

1 2

12

PC304

2200P_0402_50V7K~D

5

PQ300

123

SIR472DP-T1-GE3_POWERPAK8-5~D

5

PQ302

SIR818DP-T1-GE3

123

1 2

4

CPU1.5V_S3_GATE<8,12,38>

PC301

0.22U_0603_10V7K

+5VALW

SYSON<34,38>

SUSP#<12,34,38,56,57>

PR303

5.1_0603_5%~D

1 2

PC310

1U_0603_10V6K~D

0_0402_5%~D

1 2

@PR308

@

0_0402_5%~D

1 2

0_0402_5%~D

1 2

PR306

PR308

PR323

3

BOOT_1.5V

DH_1.5V

SW_1.5V

DL_1.5V

PR301

6.04K_0402_1%

1 2

PC307

1U_0603_10V6K~D

12

@

CS_1.5V

VDD_1.5V

+5VALW

+1.5V_PWROK<38>

1.5V_B+

PC313

0.1U_0402_16V7K~D

16

15

LGATE

14

PGND

13

CS

RT8207MZQW_WQFN20_3X3

12

VDDP

11

VDD

10

PR305

1M_0402_1%~D

1 2

S5_1.5V

2

@

PJP300

VLDOIN_1.5V

18

17

19

20

PU300

VTT

PHASE

PGOOD

BOOT

UGATE

S5

TON

8

9

PAD

VLDOIN

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

S3

6

7

1.5V_FB

S3_1.5V

12

PAD-OPEN1x1m

21 1

2

3

4

VTTREF_1.5V

5

PR307

9.53K_0402_1%~D

1 2

+1.5V

PC309

0.033U_0402_16V7~D

+1.5V

PC314

220P_0402_50V7K~D

1 2

PR304

10K_0402_1%~D

12

0.75Volt +/- 5% TDC 0.7A Peak Current 1A OCP Current 1.2A

12

PC305

PC305 10U_0603_6.3V6M

10U_0603_6.3V6M

12

PC312

0.1U_0402_16V7K~D

@

+1.5V

1

12

PC306

PC306 10U_0603_6.3V6M

10U_0603_6.3V6M

+0.75VSP

B B

PR118

0_0603_5%~D

+0.75VSP

A A

5

4

1 2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

+0.75VS

3

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR-1.5VP/0.75VSP

XPS14

58 65Tuesday, February 07, 2012

1

0.1

5

4

3

2

1

VID [0] VID[1] VCCSA Vout 0 0 0.9V

The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that

D D

SA_PGOOD<38> VCCSA_VID1 <12>

+5VALW

PR603

10_0402_1%

12

3300P_0402_50V7K

10_0402_1%

19

20

21

22

23

24

PC617

12

PU600

PGND

VIN

PC601

2.2U_0603_10V7K

1 2

C C

1

PC613

PC612

PAD-OPEN 43X118

PJP600

@ PJP600

@

12

+3VALW

B B

+VCCSA_PWR_SRC +VCCSA_PWR_SRC

PC612

1 2

2

0.1U_0402_25V6

2200P_0402_50V7K

12

PC615

PC614

4.7U_0805_25V6-K

PC616

0.22U_0402_10V6K

@

1 2

12

17

18

V5FILT

V5DRV

TPS51463RGER_QFN24_4X4

GND

VREF

1

2

PR609

5.1K_0402_5%

+3VS

12

PR601

100K_0402_5%

PC600

1U_0603_10V6K

16

PGOOD

COMP

3

12

PC619 0.033U_0402_16V7K~D@PC619 0.033U_0402_16V7K~D@

PR600 1K_0402_5%PR600 1K_0402_5%

PR602 1K_0402_5%PR602 1K_0402_5%

PC620 0.033U_0402_16V7K~DPC620 0.033U_0402_16V7K~D

13

14

15

EN

VID0

VID1

BST

VOUT

MODE

SLEW

5

6

4

PC618

0.01U_0402_25V7K

1 2

SW

TP

12

+VCCSA_EN

12

11

10

9

8

7

25

12

+VCCSA_PHASE

PR607

33K_0402_5%

VCCSA VID is 00 prior to VCCIO stability.

VCCSA_VID0 <12>

PR604

0_0402_5%

1 2

PR605

2.2_0603_5%~D

1 2

12

+VCCSA_BT_1+VCCSA_BT

+V1.05S_VCCP_PWRGOOD <57>

PC602

0.1U_0603_50V7K~D

1 2

12

PR606

2.2_1206_5%

12

PC603

1000P_0603_50V7K~D

PL600

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

1 2

PC604

@

22U_0805_6.3V6M

0 1 0.85V 1 0 0.775V 1 1 0.75V

output voltage adjustable network for ULV CPU

+VCC_SAP

DC 4.2A

T Peak Current 6A

12

PC607

PC606

0.1U_0402_10V7K

PR608

100_0402_1%

PR610

PR610 0_0402_5%~D

0_0402_5%~D

22U_0805_6.3V6M

12

SHORT

1 2

PC605

22U_0805_6.3V6M

12

PC608

1 2

22U_0805_6.3V6M

PC609

2200P_0402_50V7K

VCCSA_SENSE <12>

PC610

PC611

1 2

22U_0805_6.3V6M

+VCCSA

A A

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

5

4

3

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

AND SPECIFICATIONS CONTAINS CONFIDENTIAL

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-VCC_SAP

XPS14

1

59 65Tuesday, February 07, 2012

0.1

5

PR701

12

3.83K_0402_1%~D

VSUMG+

D D

C C

B B

A A

VSUMG-

VR_SVID_CLK<11> VR_SVID_ALRT#<11> VR_SVID_DAT<11>

PR706

2.61K_0402_1%~D

1 2

12

PH701

PH701 10K_0402_5%_ERTJ0ER103J

10K_0402_5%_ERTJ0ER103J

12

PC714

PC714 .1U_0402_16V7K~D

.1U_0402_16V7K~D

VR_HOT#<38>

+VCCP

12

PH700

470K_0402_5%_ERTJ0EV474J~D

1 2

PR704

27.4K_0402_1%~D

+VCCP

12

PR717

130_0402_1%~D

PR725

@PR725

@

1 2

499_0402_1%~D

PR726

1 2

3.83K_0402_1%~D

5

NTCG

PR709

1 2

11K_0402_1%~D

12

PR719

54.9_0402_1%~D

+5VS

12

PC717

43P_0603_50V8J

Local sense put on HW site

VCC_AXG_SENSE<12>

VSS_AXG_SENSE<12>

12

PC711

PC710

0.22U_0402_16V7K~D

0.022U_0402_25V7K~D

PR720

0_0402_5%~D

SHORT

1 2

VR_ON<38>

1 2

PH702

470K_0402_5%_ERTJ0EV474J~D

12

PR727

27.4K_0402_1%~D

VSUM+

12

PR741

2.61K_0402_1%~D

1 2

VSUM-

12

PC745

PH703

10K_0402_5%_ERTJ0ER103J

.1U_0402_16V7K~D

1 2

PR723

1 2

0_0402_5%~D

+5VS

12

PR744

11K_0402_1%~D

PR707 100_0402_1%~D

100_0402_1%~D

PR712

PR712 332_0402_1%

332_0402_1%

12

PC741

PC702

@PC702

@

1 2

330P_0402_50V7K~D

PC706

0.01U_0402_16V7K~D

@PR707

@

12

ISEN2G NTCG

12

PC742

0.1U_0402_25V7K~D

4

12

@

PC712

470P_0402_50V7K~D

1 2

1 2 3 4 5 6 7 8 9

10

NTC

41

PR736

0_0402_5%

1 2

12

PC743

0.033U_0402_16V7

0.1U_0402_25V6

PR750

@PR750

@

1 2

649_0402_1%~D

4

@

PC707

40

PU700

ISUMPG ISEN1G ISEN2G NTCG SCLK ALERT# SDA VR_HOT# VR_ON NTC

TP

11

1 2

PR748

340_0402_1%

@

PC746

1 2

2200P_0402_25V7K~D

12

39

38

RTNG

ISUMNG

ISEN212FB17ISUMP14ISEN3/FB2

13

ISEN2

330P_0402_50V7K~D

150K_0402_1%~D

36

37

FBG

COMPG

PGOODG

15

PC700 330P_0402_50V7K~DPC700 330P_0402_50V7K~D

PR702

2.49K_0402_1%~D

1 2

PR705

12

499_0402_1%~D

PR708

1 2

PWMG2

LGATE1G

PHASE1G

UGATE1G

BOOT1G

35

34

33

32

31

PWM2G

BOOT1G

LGATE1G

PHASE1G

UGATE1G

BOOT2 UGATE2 PHASE2 LGATE2

VCCP

VDD

PWM3 LGATE1 PHASE1 UGATE1

COMP

PGOOD19ISUMN

RTN16ISEN1

BOOT1

18

20

ISL95836HRTZ-T_TQFN40_5X5~D

BOOT1

COMP

FB

PR733

499_0402_1%~D

330P_0402_50V7K~D

@

1 2

PC739

330P_0402_50V7K~D

12

1 2

PR700

1 2

2K_0402_1%~D

PC703

12

390P_0402_50V7K~D

PR716

@PR716

@

0_0402_5%

12

30 29 28 27 26 25 24

PWM3

23

LGATE1

22

PHASE1

21

UGATE1

PR728

1 2

1.91K_0402_1%~D

PC728

470P_0402_50V7K~D

12

PR737

1 2

1.91K_0402_1%~D

PC737

@PC737

@

PC738

0.01U_0402_16V7K~D

12

Local sense put on HW site

PROPRIETARY NOT E: THIS SHEET OF ENGINEERING DRAWING AND SP ECIFICATIONS C ONTAINS CONFIDE NTIAL TRADE SECRET AN D OTHER PROPRI ETARY INFORMAT ION OF DELL INC . ("DELL") THI S DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITH OUT THE EXPRES S WRITTEN AUTHO RIZATION OF DE LL. IN ADDITION , NEITHER THIS SH EET NOR THE IN FORMATION IT C ONTAINS WAY BE USED BY OR DIS CLOSED TO ANY T HIRD PARTY WITHOUT D ELL'S EXPRESS WRITTEN CONSEN T.

3

267K_0402_1%~D

+5VS

+5VALW

VGATE <8,18,38>

267K_0402_1%~D

1 2

PR740

PR740 2K_0402_1%~D

2K_0402_1%~D

3

PR703

12

PC708

1 2

47P_0402_50V8J~D

BOOT1G

PR710

2.2_0603_5%~D

PR729

PR729 1_0603_5%

1_0603_5%

12 12

PR724

@PR724

@

1_0603_5%

+3VS

PC729

47P_0402_50V7K~D

12

PR738

12

PC730

150P_0402_50V8J~D

PC733

1 2

680P_0402_50V7K~D

VCCSENSE <11>

BOOT1

VSSSENSE <11>

PC701

150P_0402_50V8J~D

12

0.22U_0603_10V7K

1 2

12

PC718

1U_0603_10V6K~D

1 2

PR734

42.2K_0402_1%~D

12

1 2

PR742

2.2_0603_5%~D

UGATE1G

PHASE1G

PC713

LGATE1G

PC719

1U_0603_10V6K~D

0.22U_0603_10V7K

12

PR721

0_0402_5%~D

SHORT

1 2

PR722

0_0603_5%~D

SHORT

CPU_B+

UGATE1

PHASE1

PC740

LGATE1

GFX_B+

5

4

123

5

4

123

+5VS

12

HCB4532KF-800T90_1812~D

4

12

4

PC748

PQ700

SIR472DP-T1-GE3_POWERPAK8-5~D

PQ701

4

SIR818DP-T1-GE3

PL702

@PL702

@

1 2

PJP701

@ PJP701

@

2

112

JUMP_43X118

5

123

5

123

2

PL700

@PL700

@

HCB4532KF-800T90_1812~D

1 2

PJP700

@ PJP700

@

12

PC747

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

2200P_0402_50V7K

5

PQ702

SIR818DP-T1-GE3

123

5

PQ706

4

SIR472DP-T1-GE3_POWERPAK8-5~D

5

PQ707

4

SIR818DP-T1-GE3

2

12

PC704

PC705

4.7U_0805_25V6-K

12

PR711

4.7_1206_5%~D

12

PC715

680P_0402_50V7K~D

VAXG_core TDC 21.5A Peak Current 29A OCP current 39.6A Load line -3.9mV/A FSW=300kHz CHOCK DCR 0.82mohm +/- 5%

TYP MAX H/S Rds(on) :10mohm , 14.5mohm L/S Rds(on) :3mohm , 3.6mohm

B+

CPU_B+

PQ703

@

123

SIR472DP-T1-GE3_POWERPAK8-5~D

PQ708

PR743

4.7_1206_5%~D

SIR818DP-T1-GE3

123

2

12

PC709

4.7U_0805_25V6-K

VCC_core TDC 16A Peak Current 33A OCP current 39.6A Load line -2.9mV/A FSW=300kHz CPU_Vcore: CHOCK DCR 0.82mohm +/-5%

TYP MAX H/S Rds(on) :10mohm , 14.5mohm L/S Rds(on) :3mohm , 3.6mohm

12

PC750

PC749

0.1U_0402_25V6

12

PC744

680P_0402_50V7K~D

Title

Size Document Number Rev

Date: Sheet of

112

JUMP_43X118

0.36UH_PDME104T-R36MS0R825_37A_20%~D

4 3

PR714

3.65K_0603_1%

1 2

VSUMG+

VSUMG-

12

PC736

PC735

PC734

4.7U_0805_25V6-K

2200P_0402_50V7K

0.36UH_PDME104T-R36MS0R825_37A_20%~D

PR747

3.65K_0603_1%~D

VSUM+

VSUM-

Compal Electronics, Inc.

PWR-CPU_CORE

1

B+

PL701

1 2

12

PR715

PR715 1_0402_5%

1_0402_5%

Change Ecology A2a

1

12

+

PC724

33U_25V_M

2

4.7U_0805_25V6-K

PL704

1

4 3

2

12

1 2

XPS14

1

+VCC_GFXCORE_AXG

+VCC_CORE

PR749

PR749 1_0402_5%~D

1_0402_5%~D

60 65Tuesday, February 07, 2012

0.1

8

H H

DGPU_PWR_EN<19,33>

H_DPRSLPVR<24>

PR818

DIS@ PR818

12

PC809

DIS@ PC809

DIS@

1 2

PR840

+GPU_CORE

DIS@ PR826

DIS@

0_0402_5%

+3VS

@ PR831

@

DIS@ PR837

DIS@

1000P_0402_50V7K

DIS@ PR839

DIS@

2.2K_0402_5%

1 2

PR826

1 2

DIS@ PR829

DIS@

2.2K_0402_5%

1 2

PR831

27.4K_0402_1%

12

PH800

@PH800

@

PR837

562_0402_1%

1 2

PR839

3.57K_0402_1%~D

1 2

ISEN2_VGA ISEN1_VGA

12

PR842

@PR842

@

249K_0402_1%~D

VSUM-_VGA

0_0402_5%~D

+3VS

DIS@ PR827

DIS@

2.2K_0402_5%

1 2

PR829

12

1 2

390P_0402_50V7K

1 2

PR844

@PR844

@

100_0402_5%

1 2

PR848

0_0402_5%~D

SHORT

PR855

SHORT

1 2

PR856

@PR856

@

100_0402_5%

12

@ PR825

@

1.91K_0402_1%

PR827

1 2

DIS@ PC808

DIS@

22P_0402_50V8J

DIS@ PC811

DIS@

G G

DGPU_PWROK<19,20>

F F

E E

@

D D

150P_0402_50V8J

C C

B B

GPU_VR_HOT#<38>

4.02K_0402_1%~D

PR835

1 2

249K_0402_1%

33P_0402_50V8J~D

PC813

DIS@ PC813

DIS@

DIS@ PR828

DIS@

PR833

1 2

PR836

DIS@ PR836

DIS@

DIS@ PC812

DIS@

1 2

PR828

47K_0402_1%~D

1 2

+3VS

@

470K_0402_5%_ERTJ0EV474J~D

12

8.06K_0402_1%

PC812

1 2

DIS@ PR840

DIS@

412K_0402_1%

GPU_VDD_SENSE<26>

GPU_VSS_SENSE<27>

DIS@ PR806

DIS@

1K_0402_5%

DIS@ PC803

DIS@

0.1U_0402_25V6

1 2

H_DPRSLPVR

PR819

@ PR819

@

1.91K_0402_1%

1 2

PR825

PSI#

PC808

PC811

12

PC814

0.22U_0402_16V7K~D

DIS@ PC814

DIS@

PC822

DIS@ PC822

DIS@

330P_0402_50V7K

PC828

DIS@ PC828

DIS@

1000P_0402_50V7K

7

PR806

12

PC803

CLK_ENABLE#

DIS@

1 2 3 4 5 6 7 8 9

10 41

12

PC815

0.22U_0402_16V7K~D

DIS@ PC815

DIS@

PU800

PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2

AGND

12

1 2

GPU_VID_6

37

38

39

40

VR_ON

CLK_EN#

DPRSLPVR

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

PR810

DIS@ PR810

DIS@

0_0402_5%

GPU_VID_5

GPU_VID_3

GPU_VID_4

35

VID4

VIN

17

16

12

PR845

@

12

PC823

@

1 2

DIS@ PR857

DIS@

1.65K_0402_1%~D

GPU_VID_2

PC816

DIS@ PC816

DIS@

82.5_0402_5%

0.01U_0402_25V7K

GPU_VID_0

GPU_VID_1

GPU_VID_2

GPU_VID_3

GPU_VID_4

GPU_VID_5

H_DPRSLPVR

PSI#

GPU_VID_1

GPU_VID_0

VID031VID132VID233VID334VID536VID6

30

BOOT2

29

UGATE2

28

PHASE2

27

VSSP2

26

LGATE2

25

VCCP

24

PWM3

23

LGATE1

22

VSSP1

21

PHASE1

IMON18BOOT119UGATE1

20

ISL62883CHRTZ-T_TQFN40_5X5

12

DIS@ PC817

DIS@

0.22U_0603_25V7K

1U_0603_10V6K

12

PC824

0.1U_0402_25V6

DIS@ PC824

DIS@

PR857

6

GPU_VID_5 <24>

GPU_VID_4 <24>

GPU_VID_3 <24>

GPU_VID_2 <24>

GPU_VID_1 <24>

GPU_VID_0 <24>

DIS@ PC807

DIS@

1U_0603_10V6K

1 2

12

PC810 1U_0603_10V6K

1U_0603_10V6K

0_0402_5%~D

1 2

PC817

12

PC825

0.1U_0402_25V6

DIS@ PC825

DIS@

12

1 2 1 2

1 2

PC807

PR834

0_0402_5%~D

SHORT

DIS@PC810

DIS@

PR838

DIS@ PR841

DIS@

0_0402_5%

DIS@ PR843

DIS@

1_0402_5%

PR853

DIS@ PR853

DIS@

DIS@ PC830

DIS@

0.1U_0402_16V7K

PR800 2.2K_0402_5%@ PR800 2.2K_0402_5%@ PR801 2.2K_0402_5%DIS@ PR801 2.2K_0402_5%DIS@

PR802 2.2K_0402_5%DIS@ PR802 2.2K_0402_5%DIS@ PR805 2.2K_0402_5%@ PR805 2.2K_0402_5%@

PR804 2.2K_0402_5%@ PR804 2.2K_0402_5%@ PR803 2.2K_0402_5%DIS@ PR803 2.2K_0402_5%DIS@

PR807 2.2K_0402_5%@ PR807 2.2K_0402_5%@ PR808 2.2K_0402_5%DIS@ PR808 2.2K_0402_5%DIS@

PR811 2.2K_0402_5%DIS@ PR811 2.2K_0402_5%DIS@ PR812 2.2K_0402_5%@ PR812 2.2K_0402_5%@

PR814 2.2K_0402_5%DIS@ PR814 2.2K_0402_5%DIS@ PR813 2.2K_0402_5%@ PR813 2.2K_0402_5%@

PR815 2.2K_0402_5%@ PR815 2.2K_0402_5%@

PR817 2.2K_0402_5%@ PR817 2.2K_0402_5%@

SHORT

+5VS

+VGA_B+

PR841

+5VS

PR843

VSUM+_VGA

12

PR846

2.61K_0402_1%

DIS@ PR846

DIS@

12

DIS@ PH801

DIS@

10K_0402_1%_TSM0A103F34D1RZ

11K_0402_1%

VSUM-_VGA

Layout Note: Place near Phase1 Choke

PC830

5

+3V_GPU

DIS@ PR816

DIS@

2.2_0603_5%~D

BOOT2_VGA BOOT2_2_VGA

1 2

PR832

0_0402_5%~D

SHORT

PH801

1 2

+5VS

BOOT1_VGA

PR816

DIS@ PR847

DIS@

2.2_0603_5%~D

1 2

PR847

BOOT1_1_VGA

PC804

DIS@ PC804

DIS@

0.22U_0603_10V7K

1 2

UGATE2_VGA

DIS@ PC821

DIS@

0.22U_0603_10V7K

1 2

4

PHASE2_VGA

LGATE2_VGA

UGATE1_VGA

PC821

PHASE1_VGA

LGATE1_VGA

3

+VGA_B+

12

PC832

0.1U_0402_25V6

5

DIS@

PQ800

4

123

SIR472DP-T1-GE3_POWERPAK8-5~D

DIS@

5

PQ802

4

SIR818DP-T1-GE3

123

5

DIS@PQ803

DIS@

PQ803

4

123

DIS@

5

PQ804

4

123

DIS@

5

PQ801

123

DIS@

PR820

DIS@ PR820

DIS@

2.2_1206_5%

SIR818DP-T1-GE3

PC833

0.1U_0402_25V6

DIS@ PC833

DIS@

PQ805

SIR818DP-T1-GE3

123

4

SIR472DP-T1-GE3_POWERPAK8-5~D

5

4

SIR818DP-T1-GE3

0.1U_0402_25V6

DIS@ PC832

DIS@

12

PR821

12

1 2

PC806

DIS@ PR821

DIS@

3.65K_0603_1%~D

1000P_0603_50V7K~D

DIS@ PC806

1000P_0603_50V7K~D

DIS@

VSUM+_VGA

12

PC834

PC818

DIS@ PC834

DIS@

DIS@ PC818

DIS@

4.7U_0805_25V6-K

2200P_0402_50V7K

12

PR851

DIS@ PR851

DIS@

2.2_1206_5%

12

PR849

PC829

DIS@ PR849

DIS@

1000P_0603_50V7K~D

DIS@ PC829

1000P_0603_50V7K~D

DIS@

2

PJP800

@ PJP800

@ 2

112

JUMP_43X118

12

PC800

PC831

DIS@ PC800

DIS@

DIS@ PC831

DIS@

4.7U_0805_25V6-K

2200P_0402_50V7K

12

PC801

PC802

DIS@ PC801

DIS@

DIS@ PC802

DIS@

4.7U_0805_25V6-K

Change Ecology A2a

PL800

DIS@ PL800

DIS@

0.22UH_FDUE0640J-H-R22M-P3_25A_20%~D

PR822

1 2

DIS@ PR822

DIS@

10K_0603_1%~D

ISEN2_VGA

N13P-GV TDC 42A Peak Current 54A OCP current 85A FSW=400kHz CHOCK DCR 0.89mohm +/- 7%

TYP MAX H/S Rds(on) :10mohm , 14.5mohm L/S Rds(on) :3mohm , 3.6mohm

+VGA_B+

PC820

12

PC819

10U_0805_25V6K

DIS@ PC819

DIS@

DIS@ PC820

DIS@

V1P_VGA V1N_VGA

PR850

1 2

DIS@ PR850

DIS@

VSUM+_VGA

3.65K_0603_1%~D

ISEN1_VGA

12

PR859

PR809

0_0402_5%

DIS@

1 2

V2N_VGAV2P_VGA

V1N_VGA

V2N_VGA

12

1 2

PR830

PR830 0_0402_5%

0_0402_5%

DIS@

12

PR824

@PR824

@

10K_0402_1%~D

1 2

12

PL801

DIS@ PL801

DIS@

0.22UH_FDUE0640J-H-R22M-P3_25A_20%~D

PR858

PR858 0_0402_5%

0_0402_5%

DIS@

1 2

10K_0603_1%~D

1 2

PR854

@ PR854

@

10K_0402_1%~D

DIS@

PR823

PR823 1_0402_5%

1_0402_5%

VSUM-_VGA

12

PR852

DIS@ PR852

DIS@

VSUM-_VGA

1

B+

+GPU_CORE

1

+

PC805

2

330U_D2_2V_Y

DIS@

+GPU_CORE

1

+

PC826

PC827

2

330U_D2_2V_Y

DIS@

1_0402_5%

DIS@

A A

8

7

6

5

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

4

3

Title

Size Document Number Rev

Date: Sheet of

2

Compal Electronics, Inc.

PWR-VGA_CORE

XPS14

61 65Tuesday, February 07, 2012

1

0.1

5

4

3

2

1

+VCC_CORE +VCC_GFXCORE_AXG

+VCC_CORE

+VCC_GFXCORE_AXG

D D

C C

12

PC1219

2.2U_0402_6.3V6M~D

12

PC1228

2.2U_0402_6.3V6M~D

12

PC1236

2.2U_0402_6.3V6M~D

+VCC_CORE

1

2

1

2

1

2

B B

12

2.2U_0402_6.3V6M~D

12

2.2U_0402_6.3V6M~D

12

2.2U_0402_6.3V6M~D

PC1315

PC1315 22U_0805_6.3VAM

22U_0805_6.3VAM

PC1322

PC1322 22U_0805_6.3VAM

22U_0805_6.3VAM

PC1327

PC1327 22U_0805_6.3VAM

22U_0805_6.3VAM

PC1220

PC1229

PC1237

1

PC1316

PC1316 22U_0805_6.3VAM

22U_0805_6.3VAM

2

1

PC1323

PC1323 22U_0805_6.3VAM

22U_0805_6.3VAM

2

1

PC1328

PC1328 22U_0805_6.3VAM

22U_0805_6.3VAM

2

12

PC1221

2.2U_0402_6.3V6M~D

12

PC1230

2.2U_0402_6.3V6M~D

12

PC1238

2.2U_0402_6.3V6M~D

1

PC1317

PC1317 22U_0805_6.3VAM

22U_0805_6.3VAM

2

1

PC1324

PC1324 22U_0805_6.3VAM

22U_0805_6.3VAM

2

1

PC1329

PC1329 22U_0805_6.3VAM

22U_0805_6.3VAM

2

12

PC1222

2.2U_0402_6.3V6M~D

12

PC1231

2.2U_0402_6.3V6M~D

12

PC1239

2.2U_0402_6.3V6M~D

1

PC1318

PC1318 22U_0805_6.3VAM

22U_0805_6.3VAM

2

1

PC1325

PC1325 22U_0805_6.3VAM

22U_0805_6.3VAM

2

1

PC1330

PC1330 22U_0805_6.3VAM

22U_0805_6.3VAM

2

12

PC1223

2.2U_0402_6.3V6M~D

12

PC1232

2.2U_0402_6.3V6M~D

12

PC1240

2.2U_0402_6.3V6M~D

1

PC1319

PC1319 22U_0805_6.3VAM

22U_0805_6.3VAM

2

1

PC1326

PC1326 22U_0805_6.3VAM

22U_0805_6.3VAM

2

12

PC1259

2.2U_0402_6.3V6M~D

12

PC1233

2.2U_0402_6.3V6M~D

12

PC1241

2.2U_0402_6.3V6M~D

1

PC1225

PC1224

2

22U_0805_6.3V6M

12

PC1253

PC1254

10U_0603_6.3V6M~D

12

PC1276

PC1281

1U_0402_6.3V6K~D

12

PC1300

PC1292

1U_0402_6.3V6K~D

1

+

2

+

PC1313

2

470U_D2_2VM_R4.5M

1

PC1226

PC1227

2

22U_0805_6.3V6M

12

PC1255

PC1256

10U_0603_6.3V6M~D

12

PC1278

PC1287

1U_0402_6.3V6K~D

12

PC1301

PC1294

1U_0402_6.3V6K~D

PC1314

470U_D2_2VM_R4.5M

1

PC1235

PC1234

2

22U_0805_6.3V6M

12

PC1257

PC1258

10U_0603_6.3V6M~D

12

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

12

PC1279

PC1285

1U_0402_6.3V6K~D

12

PC1297

1U_0402_6.3V6K~D

Charlie note: iGfx_Cout1

1.22uF*6 (SE000000I10)

2.10uF*6 (SE000005T8L)

3.1uF*11 (SE000000K8L) iGfx_Cout2

1.330uF 9m *2 (SGA20331E10)

+VCCP

12

PC1244

PC1243

PC1242

1U_0402_6.3V6K~D

12

PC1265

@

1U_0402_6.3V6K~D

Charlie note: +1.05V_RUN_VTT_1

3.1uF*26 (SE000000K8L)

4.10uF*10 (SE000005T8L)

+1.05V_RUN_VTT_2

5.330uF 6m *2 (SGA00001Q80)

@

1U_0402_6.3V6K~D

12

PC1267

PC1266

1U_0402_6.3V6K~D

12

PC1304

PC1303

10U_0603_6.3V6M~D

+VCCP

12

PC1246

PC1245

@

1U_0402_6.3V6K~D

12

PC1269

PC1268

1U_0402_6.3V6K~D

12

PC1248

PC1249

PC1247

1U_0402_6.3V6K~D

12

PC1270

1U_0402_6.3V6K~D

PC1249

1U_0402_6.3V6K~D

12

PC1272

PC1271

1U_0402_6.3V6K~D

12

PC1288

12

@

10U_0603_6.3V6M~D

12

PC1307

PC1305

10U_0603_6.3V6M~D

PC1307

PC1306

10U_0603_6.3V6M~D

12

PC1309

PC1308

10U_0603_6.3V6M~D

12

PC1250

1U_0402_6.3V6K~D

12

PC1273

1U_0402_6.3V6K~D

12

PC1289

@

1U_0402_6.3V6K~D

12

PC1310

@

10U_0603_6.3V6M~D

12

PC1251

PC1252

1U_0402_6.3V6K~D

12

1U_0402_6.3V6K~D

12

1U_0402_6.3V6K~D

12

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

12

PC1274

PC1275

@

1U_0402_6.3V6K~D

12

PC1290

PC1291

1U_0402_6.3V6K~D

12

PC1312

PC1311

10U_0603_6.3V6M~D

1

+

PC1320

PC1321

2

330U_X_2VM_R6M

+VCC_CORE

1

+

PC1332

2

470U_D2_2VM_R4.5M

A A

1

+

PC1333

2

330U_D2_2VM_R6M

5

1

+

PC1334

2

330U_D2_2VM_R6M

Charlie note: Vcore_Cout1

1.2.2uF*16 (SE00000888L)

2.22uF*12 (SE000008L80) Vcore_Cout2

1.330uF 9m *3 (SGA20331E10)

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR DECOUPLING

XPS14

62 65Tuesday, February 07, 2012

1

0.1

5

4

3

2

1

+GPU_CORE (place under GPU) +GPU_CORE (place near GPU)

+GPU_CORE +GPU_CORE

DIS@ PC1179

DIS@ PC1177

DIS@

DIS@ PC1176

D D

C C

DIS@

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D PC1177

PC1176

12

DIS@

DIS@ PC1180

DIS@ PC1178

DIS@

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D PC1178

12

DIS@

4.7U_0603_6.3V6K~D

PC1179

PC1180

12

DIS@ PC1182

DIS@

DIS@ PC1181

DIS@

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D PC1182

PC1181

12

+GPU_CORE +GPU_CORE

DIS@ PC1213

DIS@

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D PC1183

DIS@ PC1196

DIS@

0.1U_0402_16V7K~D

PC1196

1

2

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D PC1185

PC1184

12

DIS@ PC1198

DIS@

DIS@ PC1199

DIS@

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D PC1199

1

2

DIS@ PC1197

DIS@

0.1U_0402_16V7K~D

PC1198

PC1197

1

2

12

DIS@ PC1185

DIS@

DIS@ PC1184

DIS@

DIS@ PC1183

DIS@

DIS@ PC1212

DIS@

22U_0805_6.3V6M

47U_0805_6.3V6M~D

PC1213

PC1212

12

DIS@ PC1214

DIS@

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D PC1214

12

DIS@ PC1216

DIS@

DIS@ PC1217

DIS@ PC1215

DIS@

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D PC1215

12

DIS@

4.7U_0603_6.3V6K~D

PC1216

PC1217

12

DIS@ PC1218

DIS@

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D PC1218

12

B B

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

GPU DECOUPLING

XPS14

63 65Tuesday, February 07, 2012

1

0.1

5

Request

Item

Item Issue Description

ItemItem

D D

C C

Page# Title

Page#Page#

X XX XXX XX'XX/XX Compal_XX XXXXX Change PRXX from Xohm to XXKohm. X01

Title

TitleTitle

Date

DateDate

RequestRequest Owner

Owner

OwnerOwner

4

Version Change List ( P. I. R. List )

Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )

Issue DescriptionDate

Issue DescriptionIssue Description

3

Page 1

Page 1Page 1

2

Solution Description

Solution Description Rev.

Solution DescriptionSolution Description

1

Rev.Page#

Rev.Rev.

B B

A A

Compal Electronics, Inc.

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

4

3

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PWR-PIR

XPS14

64 65Tuesday, February 07, 2012

1

0.1

5

4

3

2

1

Model

QLM00

D D

C C

B B

Item Page ECN NumberDate Rev. Issue Description Solution Description

1

38 01/12 1.0 PCB REV change to 1.0 Change RE77 to 56K 24 01/12 Change RV2420,RV2421 to 2.2KChange EC_SMB_CK2_PX/EC_SMB_DA2_PX pull up resistor as design guide1.02

3

39 01/12 1.0 Adjust CAPS_LED brightness Change RE84 to 470ohm

4

45 01/12 1.0 Sync up with XPS 15" for pull up power rail RI38 pull up from +5VALW to +3VALW

5

17,24,35 01/12 1.0 Solve adaptor detect issue Depop QH3; change GPU SMBus/Ambient Light Sensor connect to

6

45 01/12 1.0 Purchase recommand Change UI3 to high active parts

7

40 01/12 1.0 BOM structure control ADD TPM@ for TPM circuit

8

38 01/12 1.0 For USBCHG_DET_D can't turn on 3V/5V issue Change RE78 pull up to +3VLP

9

45 01/12 1.0 Vendor recommand UI2 EN pin pull up resistor RI38 change to 10K

10

35 01/12 1.0 Change JLVDS connector PN and footprint as assembly issue

11

39 01/12 1.0 ME change SW1 PN change to SN100005100

12

33 01/16 1.0 Solve 1.5V voltage drop issue Change QV2803 to SB00000SJ0L to lower Rds on

13

14

10 01/17 1.0 Change setting for Ivy Bridge support 1x16 PCI Epress and Sandy Bridge

15

49 01/17 1.0 ME requirement for LED brightness tunning R9 Change to 220ohm for Power LED(White)

16

39 01/18 1.0 EMI requirement Add DE7 on TP SMBus

17

38,35,39

18

35 01/19 1.0 JLVDS pin define change for opertion risk JLVDS Pin38 NC and up shift to Pin33

19

33 01/20 1.0 Change RZ10,RZ11,RZ40,RZ41 PN to SD028220A8LChange HF part

20

17,19,40 01/20

21

36 01/20 1.0 EMI requirement for LVDS Change LV7,LV8,LV9,LV10 to SM070002S00

22 23

39 01/30 1.0 Change HF part Change F1 to SP040003200

24

48,53 01/30 1.0 Solve audio power consumption issue Change PQ903 PN to SB93457001L, JSATA pin8 B+ change to +VSBP

25

17,38 01/30 1.0 EMI requirement Populate CH98,CE11,RE13

26

14 02/01 1.0 1.5V power rail reach up to 1.614V, change for derating concern CD7 capacitor change from 2V to 2.5V

27

15 02/02 1.0 EMI requirement Add RV3529,RV3530,CV3528,CV3529

28

01/16 1.0 Remove 0 ohm to short pad for MP RI22,RI23,RI24,RI25,RI17,RI3,RI4,RI5,RI7,RN29,RM10,RM25,RL25,RL6,R34,RE83,

01/19 1.0 Thailand flood disaster, original material shortage Change DE1,DE2,DE3,DE6 PN to SCS00002G00;

02/02 1.0 Customer concern Y5V MLCC performance

Item Id

PCH_SMLDATA and PCH_SMLCLK

Change JLVDS connector PN to SP01001BT00, footprint to ACES_59003-04006-001_40P

RE10,RE34,RE35,RE39, RE68,RE70,RE71,RE60,RE62,RE63,RE64,RV449, RV3519,RV3517,RI6,RI8,RV3525,RH199,RH105,RH106,RH108,RH110,RH112,RH101, RH103,RH107,RH44,RU125,RU122,RU123,RU116,RU131,RU75,RU62

only UMA Config

Depop RU85

QE5,QE6,QV3508,QZ10,QZ13,QZ15 to SB00000M700; DV9 to SCS00002G00

1.0

Change JSATA footprint to ACES_50463-0104A-001_10P-TManufacture highlight change01/2048

1.0 EMI requirement Populate PCI CLK reserved parts RH65,CH26,CH31,R2,C8

Change CA59 to SE076104K80; CE17 to SE064475KL0;CN2,CH11,CN19,CM25,CM26, CM29,CU33,CU34,CU35,CU36,CU97,CU155 to SE076104K80; CM24,CU39 change to SE076473K80; CN7,CZ11,CV3508 change to SE064106M8L

29 30

A A

31 32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/15 2012/07/15

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Change List

Change List LA-7841P

LA-7841P

0.3

65 65Tuesday, February 07, 2012

1

0.3

Compal LA-7841P QLM00, XPS 14 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual